1 /* Main header for the Hitachi h8/300 architecture. */
8 /* These define the size of main memory for the simulator.
10 Note the size of main memory for the H8/300H is only 256k. Keeping it
11 small makes the simulator run much faster and consume less memory.
13 The linker knows about the limited size of the simulator's main memory
14 on the H8/300H (via the h8300h.sc linker script). So if you change
15 H8300H_MSIZE, be sure to fix the linker script too.
17 Also note that there's a separate "eightbit" area aside from main
18 memory. For simplicity, the simulator assumes any data memory reference
19 outside of main memory refers to the eightbit area (in theory, this
20 can only happen when simulating H8/300H programs). We make no attempt
21 to catch overlapping addresses, wrapped addresses, etc etc. */
23 #define H8300_MSIZE (1 << 16)
26 Next 2 macros are ugly for any workstation, but while they're work.
27 Memory size MUST be configurable. */
28 #define H8300H_MSIZE (1 << 24)
29 #define H8300S_MSIZE (1 << 24)
43 SP_REGNUM
= R7_REGNUM
, /* Contains address of top of stack */
44 FP_REGNUM
= R6_REGNUM
, /* Contains address of executing
46 CCR_REGNUM
= 8, /* Contains processor status */
47 PC_REGNUM
= 9, /* Contains program counter */
62 OP_REG
, /* Register direct. */
63 OP_LOWREG
, /* Special reg syntax for "bra". */
64 OP_DISP
, /* Register indirect w/displacement. */
65 /* Note: h8300, h8300h, and h8300s permit only pre-decr and post-incr. */
66 OP_PREDEC
, /* Register indirect w/pre-decrement. */
67 OP_POSTDEC
, /* Register indirect w/post-decrement. */
68 OP_PREINC
, /* Register indirect w/pre-increment. */
69 OP_POSTINC
, /* Register indirect w/post-increment. */
70 OP_PCREL
, /* PC Relative. */
71 OP_MEM
, /* Absolute memory address. */
72 OP_CCR
, /* Condition Code Register. */
73 OP_IMM
, /* Immediate value. */
74 /*OP_ABS*/ /* Un-used (duplicates op_mem?). */
75 OP_EXR
, /* EXtended control Register. */
76 OP_SBR
, /* Vector Base Register. */
77 OP_VBR
, /* Short-address Base Register. */
78 OP_MACH
, /* Multiply Accumulator - high. */
79 OP_MACL
, /* Multiply Accumulator - low. */
80 /* FIXME: memory indirect? */
81 OP_INDEXB
, /* Byte index mode */
82 OP_INDEXW
, /* Word index mode */
83 OP_INDEXL
, /* Long index mode */
84 OP_REG_DEC
, /* Register direct. affect address decrement. */
85 OP_REG_INC
, /* Register direct. affect address increment. */
88 /* Structure used to describe addressing */
97 /* Struct for instruction decoder. */
108 struct h8_opcode
*op
;
112 struct h8300_sim_cpu
{
113 unsigned int regs
[20]; /* 8 GR's plus ZERO, SBR, and VBR. */
116 int macS
; /* MAC Saturating mode */
117 int macV
; /* MAC Overflow */
118 int macN
; /* MAC Negative */
119 int macZ
; /* MAC Zero */
122 char **command_line
; /* Pointer to command line arguments. */
124 unsigned char *memory
;
127 #define H8300_SIM_CPU(sd) ((struct h8300_sim_cpu *) CPU_ARCH_DATA (sd))
129 struct h8300_sim_state
{
130 unsigned long memory_size
;
135 #define H8300_SIM_STATE(sd) ((struct h8300_sim_state *) STATE_ARCH_DATA (sd))
137 /* The current state of the processor; registers, memory, etc. */
139 #define cpu_set_pc(cpu, val) (H8300_SIM_CPU (cpu)->pc = (val))
140 #define cpu_get_pc(cpu) (H8300_SIM_CPU (cpu)->pc)
142 /* Magic numbers used to distinguish an exit from a breakpoint. */
143 #define LIBC_EXIT_MAGIC1 0xdead
144 #define LIBC_EXIT_MAGIC2 0xbeef
145 /* Local version of macros for decoding exit status.
146 (included here rather than try to find target version of wait.h)
148 #define SIM_WIFEXITED(V) (((V) & 0xff) == 0)
149 #define SIM_WIFSTOPPED(V) (!SIM_WIFEXITED (V))
150 #define SIM_WEXITSTATUS(V) (((V) >> 8) & 0xff)
151 #define SIM_WSTOPSIG(V) ((V) & 0x7f)
153 #endif /* H8300_SIM_H */