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[binutils-gdb.git] / gdb / xtensa-tdep.c
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1 /* Target-dependent code for the Xtensa port of GDB, the GNU debugger.
3 Copyright (C) 2003-2022 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "defs.h"
21 #include "frame.h"
22 #include "solib-svr4.h"
23 #include "symtab.h"
24 #include "gdbtypes.h"
25 #include "gdbcore.h"
26 #include "value.h"
27 #include "osabi.h"
28 #include "regcache.h"
29 #include "reggroups.h"
30 #include "regset.h"
32 #include "dwarf2/frame.h"
33 #include "frame-base.h"
34 #include "frame-unwind.h"
36 #include "arch-utils.h"
37 #include "gdbarch.h"
39 #include "command.h"
40 #include "gdbcmd.h"
42 #include "xtensa-isa.h"
43 #include "xtensa-tdep.h"
44 #include "xtensa-config.h"
45 #include <algorithm>
48 static unsigned int xtensa_debug_level = 0;
50 #define DEBUGWARN(args...) \
51 if (xtensa_debug_level > 0) \
52 gdb_printf (gdb_stdlog, "(warn ) " args)
54 #define DEBUGINFO(args...) \
55 if (xtensa_debug_level > 1) \
56 gdb_printf (gdb_stdlog, "(info ) " args)
58 #define DEBUGTRACE(args...) \
59 if (xtensa_debug_level > 2) \
60 gdb_printf (gdb_stdlog, "(trace) " args)
62 #define DEBUGVERB(args...) \
63 if (xtensa_debug_level > 3) \
64 gdb_printf (gdb_stdlog, "(verb ) " args)
67 /* According to the ABI, the SP must be aligned to 16-byte boundaries. */
68 #define SP_ALIGNMENT 16
71 /* On Windowed ABI, we use a6 through a11 for passing arguments
72 to a function called by GDB because CALL4 is used. */
73 #define ARGS_NUM_REGS 6
74 #define REGISTER_SIZE 4
77 /* Extract the call size from the return address or PS register. */
78 #define PS_CALLINC_SHIFT 16
79 #define PS_CALLINC_MASK 0x00030000
80 #define CALLINC(ps) (((ps) & PS_CALLINC_MASK) >> PS_CALLINC_SHIFT)
81 #define WINSIZE(ra) (4 * (( (ra) >> 30) & 0x3))
83 /* On TX, hardware can be configured without Exception Option.
84 There is no PS register in this case. Inside XT-GDB, let us treat
85 it as a virtual read-only register always holding the same value. */
86 #define TX_PS 0x20
88 /* ABI-independent macros. */
89 #define ARG_NOF(tdep) \
90 (tdep->call_abi \
91 == CallAbiCall0Only ? C0_NARGS : (ARGS_NUM_REGS))
92 #define ARG_1ST(tdep) \
93 (tdep->call_abi == CallAbiCall0Only \
94 ? (tdep->a0_base + C0_ARGS) \
95 : (tdep->a0_base + 6))
97 /* XTENSA_IS_ENTRY tests whether the first byte of an instruction
98 indicates that the instruction is an ENTRY instruction. */
100 #define XTENSA_IS_ENTRY(gdbarch, op1) \
101 ((gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG) \
102 ? ((op1) == 0x6c) : ((op1) == 0x36))
104 #define XTENSA_ENTRY_LENGTH 3
106 /* windowing_enabled() returns true, if windowing is enabled.
107 WOE must be set to 1; EXCM to 0.
108 Note: We assume that EXCM is always 0 for XEA1. */
110 #define PS_WOE (1<<18)
111 #define PS_EXC (1<<4)
113 /* Big enough to hold the size of the largest register in bytes. */
114 #define XTENSA_MAX_REGISTER_SIZE 64
116 static int
117 windowing_enabled (struct gdbarch *gdbarch, unsigned int ps)
119 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
121 /* If we know CALL0 ABI is set explicitly, say it is Call0. */
122 if (tdep->call_abi == CallAbiCall0Only)
123 return 0;
125 return ((ps & PS_EXC) == 0 && (ps & PS_WOE) != 0);
128 /* Convert a live A-register number to the corresponding AR-register
129 number. */
130 static int
131 arreg_number (struct gdbarch *gdbarch, int a_regnum, ULONGEST wb)
133 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
134 int arreg;
136 arreg = a_regnum - tdep->a0_base;
137 arreg += (wb & ((tdep->num_aregs - 1) >> 2)) << WB_SHIFT;
138 arreg &= tdep->num_aregs - 1;
140 return arreg + tdep->ar_base;
143 /* Convert a live AR-register number to the corresponding A-register order
144 number in a range [0..15]. Return -1, if AR_REGNUM is out of WB window. */
145 static int
146 areg_number (struct gdbarch *gdbarch, int ar_regnum, unsigned int wb)
148 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
149 int areg;
151 areg = ar_regnum - tdep->ar_base;
152 if (areg < 0 || areg >= tdep->num_aregs)
153 return -1;
154 areg = (areg - wb * 4) & (tdep->num_aregs - 1);
155 return (areg > 15) ? -1 : areg;
158 /* Read Xtensa register directly from the hardware. */
159 static unsigned long
160 xtensa_read_register (int regnum)
162 ULONGEST value;
164 regcache_raw_read_unsigned (get_current_regcache (), regnum, &value);
165 return (unsigned long) value;
168 /* Write Xtensa register directly to the hardware. */
169 static void
170 xtensa_write_register (int regnum, ULONGEST value)
172 regcache_raw_write_unsigned (get_current_regcache (), regnum, value);
175 /* Return the window size of the previous call to the function from which we
176 have just returned.
178 This function is used to extract the return value after a called function
179 has returned to the caller. On Xtensa, the register that holds the return
180 value (from the perspective of the caller) depends on what call
181 instruction was used. For now, we are assuming that the call instruction
182 precedes the current address, so we simply analyze the call instruction.
183 If we are in a dummy frame, we simply return 4 as we used a 'pseudo-call4'
184 method to call the inferior function. */
186 static int
187 extract_call_winsize (struct gdbarch *gdbarch, CORE_ADDR pc)
189 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
190 int winsize = 4;
191 int insn;
192 gdb_byte buf[4];
194 DEBUGTRACE ("extract_call_winsize (pc = 0x%08x)\n", (int) pc);
196 /* Read the previous instruction (should be a call[x]{4|8|12}. */
197 read_memory (pc-3, buf, 3);
198 insn = extract_unsigned_integer (buf, 3, byte_order);
200 /* Decode call instruction:
201 Little Endian
202 call{0,4,8,12} OFFSET || {00,01,10,11} || 0101
203 callx{0,4,8,12} OFFSET || 11 || {00,01,10,11} || 0000
204 Big Endian
205 call{0,4,8,12} 0101 || {00,01,10,11} || OFFSET
206 callx{0,4,8,12} 0000 || {00,01,10,11} || 11 || OFFSET. */
208 if (byte_order == BFD_ENDIAN_LITTLE)
210 if (((insn & 0xf) == 0x5) || ((insn & 0xcf) == 0xc0))
211 winsize = (insn & 0x30) >> 2; /* 0, 4, 8, 12. */
213 else
215 if (((insn >> 20) == 0x5) || (((insn >> 16) & 0xf3) == 0x03))
216 winsize = (insn >> 16) & 0xc; /* 0, 4, 8, 12. */
218 return winsize;
222 /* REGISTER INFORMATION */
224 /* Find register by name. */
225 static int
226 xtensa_find_register_by_name (struct gdbarch *gdbarch, const char *name)
228 int i;
229 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
231 for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++)
232 if (strcasecmp (tdep->regmap[i].name, name) == 0)
233 return i;
235 return -1;
238 /* Returns the name of a register. */
239 static const char *
240 xtensa_register_name (struct gdbarch *gdbarch, int regnum)
242 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
244 /* Return the name stored in the register map. */
245 if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
246 return tdep->regmap[regnum].name;
248 internal_error (__FILE__, __LINE__, _("invalid register %d"), regnum);
249 return 0;
252 /* Return the type of a register. Create a new type, if necessary. */
254 static struct type *
255 xtensa_register_type (struct gdbarch *gdbarch, int regnum)
257 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
259 /* Return signed integer for ARx and Ax registers. */
260 if ((regnum >= tdep->ar_base
261 && regnum < tdep->ar_base + tdep->num_aregs)
262 || (regnum >= tdep->a0_base
263 && regnum < tdep->a0_base + 16))
264 return builtin_type (gdbarch)->builtin_int;
266 if (regnum == gdbarch_pc_regnum (gdbarch)
267 || regnum == tdep->a0_base + 1)
268 return builtin_type (gdbarch)->builtin_data_ptr;
270 /* Return the stored type for all other registers. */
271 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
273 xtensa_register_t* reg = &tdep->regmap[regnum];
275 /* Set ctype for this register (only the first time). */
277 if (reg->ctype == 0)
279 struct ctype_cache *tp;
280 int size = reg->byte_size;
282 /* We always use the memory representation,
283 even if the register width is smaller. */
284 switch (size)
286 case 1:
287 reg->ctype = builtin_type (gdbarch)->builtin_uint8;
288 break;
290 case 2:
291 reg->ctype = builtin_type (gdbarch)->builtin_uint16;
292 break;
294 case 4:
295 reg->ctype = builtin_type (gdbarch)->builtin_uint32;
296 break;
298 case 8:
299 reg->ctype = builtin_type (gdbarch)->builtin_uint64;
300 break;
302 case 16:
303 reg->ctype = builtin_type (gdbarch)->builtin_uint128;
304 break;
306 default:
307 for (tp = tdep->type_entries; tp != NULL; tp = tp->next)
308 if (tp->size == size)
309 break;
311 if (tp == NULL)
313 std::string name = string_printf ("int%d", size * 8);
315 tp = XNEW (struct ctype_cache);
316 tp->next = tdep->type_entries;
317 tdep->type_entries = tp;
318 tp->size = size;
319 tp->virtual_type
320 = arch_integer_type (gdbarch, size * 8, 1, name.c_str ());
323 reg->ctype = tp->virtual_type;
326 return reg->ctype;
329 internal_error (__FILE__, __LINE__, _("invalid register number %d"), regnum);
330 return 0;
334 /* Return the 'local' register number for stubs, dwarf2, etc.
335 The debugging information enumerates registers starting from 0 for A0
336 to n for An. So, we only have to add the base number for A0. */
338 static int
339 xtensa_reg_to_regnum (struct gdbarch *gdbarch, int regnum)
341 int i;
342 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
344 if (regnum >= 0 && regnum < 16)
345 return tdep->a0_base + regnum;
347 for (i = 0; i < gdbarch_num_cooked_regs (gdbarch); i++)
348 if (regnum == tdep->regmap[i].target_number)
349 return i;
351 return -1;
355 /* Write the bits of a masked register to the various registers.
356 Only the masked areas of these registers are modified; the other
357 fields are untouched. The size of masked registers is always less
358 than or equal to 32 bits. */
360 static void
361 xtensa_register_write_masked (struct regcache *regcache,
362 xtensa_register_t *reg, const gdb_byte *buffer)
364 unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4];
365 const xtensa_mask_t *mask = reg->mask;
367 int shift = 0; /* Shift for next mask (mod 32). */
368 int start, size; /* Start bit and size of current mask. */
370 unsigned int *ptr = value;
371 unsigned int regval, m, mem = 0;
373 int bytesize = reg->byte_size;
374 int bitsize = bytesize * 8;
375 int i, r;
377 DEBUGTRACE ("xtensa_register_write_masked ()\n");
379 /* Copy the masked register to host byte-order. */
380 if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG)
381 for (i = 0; i < bytesize; i++)
383 mem >>= 8;
384 mem |= (buffer[bytesize - i - 1] << 24);
385 if ((i & 3) == 3)
386 *ptr++ = mem;
388 else
389 for (i = 0; i < bytesize; i++)
391 mem >>= 8;
392 mem |= (buffer[i] << 24);
393 if ((i & 3) == 3)
394 *ptr++ = mem;
397 /* We might have to shift the final value:
398 bytesize & 3 == 0 -> nothing to do, we use the full 32 bits,
399 bytesize & 3 == x -> shift (4-x) * 8. */
401 *ptr = mem >> (((0 - bytesize) & 3) * 8);
402 ptr = value;
403 mem = *ptr;
405 /* Write the bits to the masked areas of the other registers. */
406 for (i = 0; i < mask->count; i++)
408 start = mask->mask[i].bit_start;
409 size = mask->mask[i].bit_size;
410 regval = mem >> shift;
412 if ((shift += size) > bitsize)
413 error (_("size of all masks is larger than the register"));
415 if (shift >= 32)
417 mem = *(++ptr);
418 shift -= 32;
419 bitsize -= 32;
421 if (shift > 0)
422 regval |= mem << (size - shift);
425 /* Make sure we have a valid register. */
426 r = mask->mask[i].reg_num;
427 if (r >= 0 && size > 0)
429 /* Don't overwrite the unmasked areas. */
430 ULONGEST old_val;
431 regcache_cooked_read_unsigned (regcache, r, &old_val);
432 m = 0xffffffff >> (32 - size) << start;
433 regval <<= start;
434 regval = (regval & m) | (old_val & ~m);
435 regcache_cooked_write_unsigned (regcache, r, regval);
441 /* Read a tie state or mapped registers. Read the masked areas
442 of the registers and assemble them into a single value. */
444 static enum register_status
445 xtensa_register_read_masked (readable_regcache *regcache,
446 xtensa_register_t *reg, gdb_byte *buffer)
448 unsigned int value[(XTENSA_MAX_REGISTER_SIZE + 3) / 4];
449 const xtensa_mask_t *mask = reg->mask;
451 int shift = 0;
452 int start, size;
454 unsigned int *ptr = value;
455 unsigned int regval, mem = 0;
457 int bytesize = reg->byte_size;
458 int bitsize = bytesize * 8;
459 int i;
461 DEBUGTRACE ("xtensa_register_read_masked (reg \"%s\", ...)\n",
462 reg->name == 0 ? "" : reg->name);
464 /* Assemble the register from the masked areas of other registers. */
465 for (i = 0; i < mask->count; i++)
467 int r = mask->mask[i].reg_num;
468 if (r >= 0)
470 enum register_status status;
471 ULONGEST val;
473 status = regcache->cooked_read (r, &val);
474 if (status != REG_VALID)
475 return status;
476 regval = (unsigned int) val;
478 else
479 regval = 0;
481 start = mask->mask[i].bit_start;
482 size = mask->mask[i].bit_size;
484 regval >>= start;
486 if (size < 32)
487 regval &= (0xffffffff >> (32 - size));
489 mem |= regval << shift;
491 if ((shift += size) > bitsize)
492 error (_("size of all masks is larger than the register"));
494 if (shift >= 32)
496 *ptr++ = mem;
497 bitsize -= 32;
498 shift -= 32;
500 if (shift == 0)
501 mem = 0;
502 else
503 mem = regval >> (size - shift);
507 if (shift > 0)
508 *ptr = mem;
510 /* Copy value to target byte order. */
511 ptr = value;
512 mem = *ptr;
514 if (gdbarch_byte_order (regcache->arch ()) == BFD_ENDIAN_BIG)
515 for (i = 0; i < bytesize; i++)
517 if ((i & 3) == 0)
518 mem = *ptr++;
519 buffer[bytesize - i - 1] = mem & 0xff;
520 mem >>= 8;
522 else
523 for (i = 0; i < bytesize; i++)
525 if ((i & 3) == 0)
526 mem = *ptr++;
527 buffer[i] = mem & 0xff;
528 mem >>= 8;
531 return REG_VALID;
535 /* Read pseudo registers. */
537 static enum register_status
538 xtensa_pseudo_register_read (struct gdbarch *gdbarch,
539 readable_regcache *regcache,
540 int regnum,
541 gdb_byte *buffer)
543 DEBUGTRACE ("xtensa_pseudo_register_read (... regnum = %d (%s) ...)\n",
544 regnum, xtensa_register_name (gdbarch, regnum));
545 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
547 /* Read aliases a0..a15, if this is a Windowed ABI. */
548 if (tdep->isa_use_windowed_registers
549 && (regnum >= tdep->a0_base)
550 && (regnum <= tdep->a0_base + 15))
552 ULONGEST value;
553 enum register_status status;
555 status = regcache->raw_read (tdep->wb_regnum,
556 &value);
557 if (status != REG_VALID)
558 return status;
559 regnum = arreg_number (gdbarch, regnum, value);
562 /* We can always read non-pseudo registers. */
563 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
564 return regcache->raw_read (regnum, buffer);
566 /* We have to find out how to deal with priveleged registers.
567 Let's treat them as pseudo-registers, but we cannot read/write them. */
569 else if (tdep->call_abi == CallAbiCall0Only
570 || regnum < tdep->a0_base)
572 buffer[0] = (gdb_byte)0;
573 buffer[1] = (gdb_byte)0;
574 buffer[2] = (gdb_byte)0;
575 buffer[3] = (gdb_byte)0;
576 return REG_VALID;
578 /* Pseudo registers. */
579 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
581 xtensa_register_t *reg = &tdep->regmap[regnum];
582 xtensa_register_type_t type = reg->type;
583 int flags = tdep->target_flags;
585 /* We cannot read Unknown or Unmapped registers. */
586 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
588 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
590 warning (_("cannot read register %s"),
591 xtensa_register_name (gdbarch, regnum));
592 return REG_VALID;
596 /* Some targets cannot read TIE register files. */
597 else if (type == xtRegisterTypeTieRegfile)
599 /* Use 'fetch' to get register? */
600 if (flags & xtTargetFlagsUseFetchStore)
602 warning (_("cannot read register"));
603 return REG_VALID;
606 /* On some targets (esp. simulators), we can always read the reg. */
607 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
609 warning (_("cannot read register"));
610 return REG_VALID;
614 /* We can always read mapped registers. */
615 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
616 return xtensa_register_read_masked (regcache, reg, buffer);
618 /* Assume that we can read the register. */
619 return regcache->raw_read (regnum, buffer);
621 else
622 internal_error (__FILE__, __LINE__,
623 _("invalid register number %d"), regnum);
627 /* Write pseudo registers. */
629 static void
630 xtensa_pseudo_register_write (struct gdbarch *gdbarch,
631 struct regcache *regcache,
632 int regnum,
633 const gdb_byte *buffer)
635 DEBUGTRACE ("xtensa_pseudo_register_write (... regnum = %d (%s) ...)\n",
636 regnum, xtensa_register_name (gdbarch, regnum));
637 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
639 /* Renumber register, if aliases a0..a15 on Windowed ABI. */
640 if (tdep->isa_use_windowed_registers
641 && (regnum >= tdep->a0_base)
642 && (regnum <= tdep->a0_base + 15))
644 ULONGEST value;
645 regcache_raw_read_unsigned (regcache,
646 tdep->wb_regnum, &value);
647 regnum = arreg_number (gdbarch, regnum, value);
650 /* We can always write 'core' registers.
651 Note: We might have converted Ax->ARy. */
652 if (regnum >= 0 && regnum < gdbarch_num_regs (gdbarch))
653 regcache->raw_write (regnum, buffer);
655 /* We have to find out how to deal with priveleged registers.
656 Let's treat them as pseudo-registers, but we cannot read/write them. */
658 else if (regnum < tdep->a0_base)
660 return;
662 /* Pseudo registers. */
663 else if (regnum >= 0 && regnum < gdbarch_num_cooked_regs (gdbarch))
665 xtensa_register_t *reg = &tdep->regmap[regnum];
666 xtensa_register_type_t type = reg->type;
667 int flags = tdep->target_flags;
669 /* On most targets, we cannot write registers
670 of type "Unknown" or "Unmapped". */
671 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
673 if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
675 warning (_("cannot write register %s"),
676 xtensa_register_name (gdbarch, regnum));
677 return;
681 /* Some targets cannot read TIE register files. */
682 else if (type == xtRegisterTypeTieRegfile)
684 /* Use 'store' to get register? */
685 if (flags & xtTargetFlagsUseFetchStore)
687 warning (_("cannot write register"));
688 return;
691 /* On some targets (esp. simulators), we can always write
692 the register. */
693 else if ((flags & xtTargetFlagsNonVisibleRegs) == 0)
695 warning (_("cannot write register"));
696 return;
700 /* We can always write mapped registers. */
701 else if (type == xtRegisterTypeMapped || type == xtRegisterTypeTieState)
703 xtensa_register_write_masked (regcache, reg, buffer);
704 return;
707 /* Assume that we can write the register. */
708 regcache->raw_write (regnum, buffer);
710 else
711 internal_error (__FILE__, __LINE__,
712 _("invalid register number %d"), regnum);
715 static const reggroup *xtensa_ar_reggroup;
716 static const reggroup *xtensa_user_reggroup;
717 static const reggroup *xtensa_vectra_reggroup;
718 static const reggroup *xtensa_cp[XTENSA_MAX_COPROCESSOR];
720 static void
721 xtensa_init_reggroups (void)
723 int i;
725 xtensa_ar_reggroup = reggroup_new ("ar", USER_REGGROUP);
726 xtensa_user_reggroup = reggroup_new ("user", USER_REGGROUP);
727 xtensa_vectra_reggroup = reggroup_new ("vectra", USER_REGGROUP);
729 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
730 xtensa_cp[i] = reggroup_new (xstrprintf ("cp%d", i).release (),
731 USER_REGGROUP);
734 static void
735 xtensa_add_reggroups (struct gdbarch *gdbarch)
737 /* Xtensa-specific groups. */
738 reggroup_add (gdbarch, xtensa_ar_reggroup);
739 reggroup_add (gdbarch, xtensa_user_reggroup);
740 reggroup_add (gdbarch, xtensa_vectra_reggroup);
742 for (int i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
743 reggroup_add (gdbarch, xtensa_cp[i]);
746 static int
747 xtensa_coprocessor_register_group (const struct reggroup *group)
749 int i;
751 for (i = 0; i < XTENSA_MAX_COPROCESSOR; i++)
752 if (group == xtensa_cp[i])
753 return i;
755 return -1;
758 #define SAVE_REST_FLAGS (XTENSA_REGISTER_FLAGS_READABLE \
759 | XTENSA_REGISTER_FLAGS_WRITABLE \
760 | XTENSA_REGISTER_FLAGS_VOLATILE)
762 #define SAVE_REST_VALID (XTENSA_REGISTER_FLAGS_READABLE \
763 | XTENSA_REGISTER_FLAGS_WRITABLE)
765 static int
766 xtensa_register_reggroup_p (struct gdbarch *gdbarch,
767 int regnum,
768 const struct reggroup *group)
770 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
771 xtensa_register_t* reg = &tdep->regmap[regnum];
772 xtensa_register_type_t type = reg->type;
773 xtensa_register_group_t rg = reg->group;
774 int cp_number;
776 if (group == save_reggroup)
777 /* Every single register should be included into the list of registers
778 to be watched for changes while using -data-list-changed-registers. */
779 return 1;
781 /* First, skip registers that are not visible to this target
782 (unknown and unmapped registers when not using ISS). */
784 if (type == xtRegisterTypeUnmapped || type == xtRegisterTypeUnknown)
785 return 0;
786 if (group == all_reggroup)
787 return 1;
788 if (group == xtensa_ar_reggroup)
789 return rg & xtRegisterGroupAddrReg;
790 if (group == xtensa_user_reggroup)
791 return rg & xtRegisterGroupUser;
792 if (group == float_reggroup)
793 return rg & xtRegisterGroupFloat;
794 if (group == general_reggroup)
795 return rg & xtRegisterGroupGeneral;
796 if (group == system_reggroup)
797 return rg & xtRegisterGroupState;
798 if (group == vector_reggroup || group == xtensa_vectra_reggroup)
799 return rg & xtRegisterGroupVectra;
800 if (group == restore_reggroup)
801 return (regnum < gdbarch_num_regs (gdbarch)
802 && (reg->flags & SAVE_REST_FLAGS) == SAVE_REST_VALID);
803 cp_number = xtensa_coprocessor_register_group (group);
804 if (cp_number >= 0)
805 return rg & (xtRegisterGroupCP0 << cp_number);
806 else
807 return 1;
811 /* Supply register REGNUM from the buffer specified by GREGS and LEN
812 in the general-purpose register set REGSET to register cache
813 REGCACHE. If REGNUM is -1 do this for all registers in REGSET. */
815 static void
816 xtensa_supply_gregset (const struct regset *regset,
817 struct regcache *rc,
818 int regnum,
819 const void *gregs,
820 size_t len)
822 const xtensa_elf_gregset_t *regs = (const xtensa_elf_gregset_t *) gregs;
823 struct gdbarch *gdbarch = rc->arch ();
824 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
825 int i;
827 DEBUGTRACE ("xtensa_supply_gregset (..., regnum==%d, ...)\n", regnum);
829 if (regnum == gdbarch_pc_regnum (gdbarch) || regnum == -1)
830 rc->raw_supply (gdbarch_pc_regnum (gdbarch), (char *) &regs->pc);
831 if (regnum == gdbarch_ps_regnum (gdbarch) || regnum == -1)
832 rc->raw_supply (gdbarch_ps_regnum (gdbarch), (char *) &regs->ps);
833 if (regnum == tdep->wb_regnum || regnum == -1)
834 rc->raw_supply (tdep->wb_regnum,
835 (char *) &regs->windowbase);
836 if (regnum == tdep->ws_regnum || regnum == -1)
837 rc->raw_supply (tdep->ws_regnum,
838 (char *) &regs->windowstart);
839 if (regnum == tdep->lbeg_regnum || regnum == -1)
840 rc->raw_supply (tdep->lbeg_regnum,
841 (char *) &regs->lbeg);
842 if (regnum == tdep->lend_regnum || regnum == -1)
843 rc->raw_supply (tdep->lend_regnum,
844 (char *) &regs->lend);
845 if (regnum == tdep->lcount_regnum || regnum == -1)
846 rc->raw_supply (tdep->lcount_regnum,
847 (char *) &regs->lcount);
848 if (regnum == tdep->sar_regnum || regnum == -1)
849 rc->raw_supply (tdep->sar_regnum,
850 (char *) &regs->sar);
851 if (regnum >=tdep->ar_base
852 && regnum < tdep->ar_base
853 + tdep->num_aregs)
854 rc->raw_supply
855 (regnum, (char *) &regs->ar[regnum - tdep->ar_base]);
856 else if (regnum == -1)
858 for (i = 0; i < tdep->num_aregs; ++i)
859 rc->raw_supply (tdep->ar_base + i,
860 (char *) &regs->ar[i]);
865 /* Xtensa register set. */
867 static struct regset
868 xtensa_gregset =
870 NULL,
871 xtensa_supply_gregset
875 /* Iterate over supported core file register note sections. */
877 static void
878 xtensa_iterate_over_regset_sections (struct gdbarch *gdbarch,
879 iterate_over_regset_sections_cb *cb,
880 void *cb_data,
881 const struct regcache *regcache)
883 DEBUGTRACE ("xtensa_iterate_over_regset_sections\n");
885 cb (".reg", sizeof (xtensa_elf_gregset_t), sizeof (xtensa_elf_gregset_t),
886 &xtensa_gregset, NULL, cb_data);
890 /* Handling frames. */
892 /* Number of registers to save in case of Windowed ABI. */
893 #define XTENSA_NUM_SAVED_AREGS 12
895 /* Frame cache part for Windowed ABI. */
896 typedef struct xtensa_windowed_frame_cache
898 int wb; /* WINDOWBASE of the previous frame. */
899 int callsize; /* Call size of this frame. */
900 int ws; /* WINDOWSTART of the previous frame. It keeps track of
901 life windows only. If there is no bit set for the
902 window, that means it had been already spilled
903 because of window overflow. */
905 /* Addresses of spilled A-registers.
906 AREGS[i] == -1, if corresponding AR is alive. */
907 CORE_ADDR aregs[XTENSA_NUM_SAVED_AREGS];
908 } xtensa_windowed_frame_cache_t;
910 /* Call0 ABI Definitions. */
912 #define C0_MAXOPDS 3 /* Maximum number of operands for prologue
913 analysis. */
914 #define C0_CLESV 12 /* Callee-saved registers are here and up. */
915 #define C0_SP 1 /* Register used as SP. */
916 #define C0_FP 15 /* Register used as FP. */
917 #define C0_RA 0 /* Register used as return address. */
918 #define C0_ARGS 2 /* Register used as first arg/retval. */
919 #define C0_NARGS 6 /* Number of A-regs for args/retvals. */
921 /* Each element of xtensa_call0_frame_cache.c0_rt[] describes for each
922 A-register where the current content of the reg came from (in terms
923 of an original reg and a constant). Negative values of c0_rt[n].fp_reg
924 mean that the original content of the register was saved to the stack.
925 c0_rt[n].fr.ofs is NOT the offset from the frame base because we don't
926 know where SP will end up until the entire prologue has been analyzed. */
928 #define C0_CONST -1 /* fr_reg value if register contains a constant. */
929 #define C0_INEXP -2 /* fr_reg value if inexpressible as reg + offset. */
930 #define C0_NOSTK -1 /* to_stk value if register has not been stored. */
932 extern xtensa_isa xtensa_default_isa;
934 typedef struct xtensa_c0reg
936 int fr_reg; /* original register from which register content
937 is derived, or C0_CONST, or C0_INEXP. */
938 int fr_ofs; /* constant offset from reg, or immediate value. */
939 int to_stk; /* offset from original SP to register (4-byte aligned),
940 or C0_NOSTK if register has not been saved. */
941 } xtensa_c0reg_t;
943 /* Frame cache part for Call0 ABI. */
944 typedef struct xtensa_call0_frame_cache
946 int c0_frmsz; /* Stack frame size. */
947 int c0_hasfp; /* Current frame uses frame pointer. */
948 int fp_regnum; /* A-register used as FP. */
949 int c0_fp; /* Actual value of frame pointer. */
950 int c0_fpalign; /* Dynamic adjustment for the stack
951 pointer. It's an AND mask. Zero,
952 if alignment was not adjusted. */
953 int c0_old_sp; /* In case of dynamic adjustment, it is
954 a register holding unaligned sp.
955 C0_INEXP, when undefined. */
956 int c0_sp_ofs; /* If "c0_old_sp" was spilled it's a
957 stack offset. C0_NOSTK otherwise. */
959 xtensa_c0reg_t c0_rt[C0_NREGS]; /* Register tracking information. */
960 } xtensa_call0_frame_cache_t;
962 typedef struct xtensa_frame_cache
964 CORE_ADDR base; /* Stack pointer of this frame. */
965 CORE_ADDR pc; /* PC of this frame at the function entry point. */
966 CORE_ADDR ra; /* The raw return address of this frame. */
967 CORE_ADDR ps; /* The PS register of the previous (older) frame. */
968 CORE_ADDR prev_sp; /* Stack Pointer of the previous (older) frame. */
969 int call0; /* It's a call0 framework (else windowed). */
970 union
972 xtensa_windowed_frame_cache_t wd; /* call0 == false. */
973 xtensa_call0_frame_cache_t c0; /* call0 == true. */
975 } xtensa_frame_cache_t;
978 static struct xtensa_frame_cache *
979 xtensa_alloc_frame_cache (int windowed)
981 xtensa_frame_cache_t *cache;
982 int i;
984 DEBUGTRACE ("xtensa_alloc_frame_cache ()\n");
986 cache = FRAME_OBSTACK_ZALLOC (xtensa_frame_cache_t);
988 cache->base = 0;
989 cache->pc = 0;
990 cache->ra = 0;
991 cache->ps = 0;
992 cache->prev_sp = 0;
993 cache->call0 = !windowed;
994 if (cache->call0)
996 cache->c0.c0_frmsz = -1;
997 cache->c0.c0_hasfp = 0;
998 cache->c0.fp_regnum = -1;
999 cache->c0.c0_fp = -1;
1000 cache->c0.c0_fpalign = 0;
1001 cache->c0.c0_old_sp = C0_INEXP;
1002 cache->c0.c0_sp_ofs = C0_NOSTK;
1004 for (i = 0; i < C0_NREGS; i++)
1006 cache->c0.c0_rt[i].fr_reg = i;
1007 cache->c0.c0_rt[i].fr_ofs = 0;
1008 cache->c0.c0_rt[i].to_stk = C0_NOSTK;
1011 else
1013 cache->wd.wb = 0;
1014 cache->wd.ws = 0;
1015 cache->wd.callsize = -1;
1017 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
1018 cache->wd.aregs[i] = -1;
1020 return cache;
1024 static CORE_ADDR
1025 xtensa_frame_align (struct gdbarch *gdbarch, CORE_ADDR address)
1027 return address & ~15;
1031 static CORE_ADDR
1032 xtensa_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1034 gdb_byte buf[8];
1035 CORE_ADDR pc;
1037 DEBUGTRACE ("xtensa_unwind_pc (next_frame = %s)\n",
1038 host_address_to_string (next_frame));
1040 frame_unwind_register (next_frame, gdbarch_pc_regnum (gdbarch), buf);
1041 pc = extract_typed_address (buf, builtin_type (gdbarch)->builtin_func_ptr);
1043 DEBUGINFO ("[xtensa_unwind_pc] pc = 0x%08x\n", (unsigned int) pc);
1045 return pc;
1049 static struct frame_id
1050 xtensa_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1052 CORE_ADDR pc, fp;
1053 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1055 /* THIS-FRAME is a dummy frame. Return a frame ID of that frame. */
1057 pc = get_frame_pc (this_frame);
1058 fp = get_frame_register_unsigned
1059 (this_frame, tdep->a0_base + 1);
1061 /* Make dummy frame ID unique by adding a constant. */
1062 return frame_id_build (fp + SP_ALIGNMENT, pc);
1065 /* Returns true, if instruction to execute next is unique to Xtensa Window
1066 Interrupt Handlers. It can only be one of L32E, S32E, RFWO, or RFWU. */
1068 static int
1069 xtensa_window_interrupt_insn (struct gdbarch *gdbarch, CORE_ADDR pc)
1071 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1072 unsigned int insn = read_memory_integer (pc, 4, byte_order);
1073 unsigned int code;
1075 if (byte_order == BFD_ENDIAN_BIG)
1077 /* Check, if this is L32E or S32E. */
1078 code = insn & 0xf000ff00;
1079 if ((code == 0x00009000) || (code == 0x00009400))
1080 return 1;
1081 /* Check, if this is RFWU or RFWO. */
1082 code = insn & 0xffffff00;
1083 return ((code == 0x00430000) || (code == 0x00530000));
1085 else
1087 /* Check, if this is L32E or S32E. */
1088 code = insn & 0x00ff000f;
1089 if ((code == 0x090000) || (code == 0x490000))
1090 return 1;
1091 /* Check, if this is RFWU or RFWO. */
1092 code = insn & 0x00ffffff;
1093 return ((code == 0x00003400) || (code == 0x00003500));
1097 /* Returns the best guess about which register is a frame pointer
1098 for the function containing CURRENT_PC. */
1100 #define XTENSA_ISA_BSZ 32 /* Instruction buffer size. */
1101 #define XTENSA_ISA_BADPC ((CORE_ADDR)0) /* Bad PC value. */
1103 static unsigned int
1104 xtensa_scan_prologue (struct gdbarch *gdbarch, CORE_ADDR current_pc)
1106 #define RETURN_FP goto done
1108 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1109 unsigned int fp_regnum = tdep->a0_base + 1;
1110 CORE_ADDR start_addr;
1111 xtensa_isa isa;
1112 xtensa_insnbuf ins, slot;
1113 gdb_byte ibuf[XTENSA_ISA_BSZ];
1114 CORE_ADDR ia, bt, ba;
1115 xtensa_format ifmt;
1116 int ilen, islots, is;
1117 xtensa_opcode opc;
1118 const char *opcname;
1120 find_pc_partial_function (current_pc, NULL, &start_addr, NULL);
1121 if (start_addr == 0)
1122 return fp_regnum;
1124 isa = xtensa_default_isa;
1125 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
1126 ins = xtensa_insnbuf_alloc (isa);
1127 slot = xtensa_insnbuf_alloc (isa);
1128 ba = 0;
1130 for (ia = start_addr, bt = ia; ia < current_pc ; ia += ilen)
1132 if (ia + xtensa_isa_maxlength (isa) > bt)
1134 ba = ia;
1135 bt = (ba + XTENSA_ISA_BSZ) < current_pc
1136 ? ba + XTENSA_ISA_BSZ : current_pc;
1137 if (target_read_memory (ba, ibuf, bt - ba) != 0)
1138 RETURN_FP;
1141 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
1142 ifmt = xtensa_format_decode (isa, ins);
1143 if (ifmt == XTENSA_UNDEFINED)
1144 RETURN_FP;
1145 ilen = xtensa_format_length (isa, ifmt);
1146 if (ilen == XTENSA_UNDEFINED)
1147 RETURN_FP;
1148 islots = xtensa_format_num_slots (isa, ifmt);
1149 if (islots == XTENSA_UNDEFINED)
1150 RETURN_FP;
1152 for (is = 0; is < islots; ++is)
1154 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
1155 RETURN_FP;
1157 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
1158 if (opc == XTENSA_UNDEFINED)
1159 RETURN_FP;
1161 opcname = xtensa_opcode_name (isa, opc);
1163 if (strcasecmp (opcname, "mov.n") == 0
1164 || strcasecmp (opcname, "or") == 0)
1166 unsigned int register_operand;
1168 /* Possible candidate for setting frame pointer
1169 from A1. This is what we are looking for. */
1171 if (xtensa_operand_get_field (isa, opc, 1, ifmt,
1172 is, slot, &register_operand) != 0)
1173 RETURN_FP;
1174 if (xtensa_operand_decode (isa, opc, 1, &register_operand) != 0)
1175 RETURN_FP;
1176 if (register_operand == 1) /* Mov{.n} FP A1. */
1178 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot,
1179 &register_operand) != 0)
1180 RETURN_FP;
1181 if (xtensa_operand_decode (isa, opc, 0,
1182 &register_operand) != 0)
1183 RETURN_FP;
1185 fp_regnum
1186 = tdep->a0_base + register_operand;
1187 RETURN_FP;
1191 if (
1192 /* We have problems decoding the memory. */
1193 opcname == NULL
1194 || strcasecmp (opcname, "ill") == 0
1195 || strcasecmp (opcname, "ill.n") == 0
1196 /* Hit planted breakpoint. */
1197 || strcasecmp (opcname, "break") == 0
1198 || strcasecmp (opcname, "break.n") == 0
1199 /* Flow control instructions finish prologue. */
1200 || xtensa_opcode_is_branch (isa, opc) > 0
1201 || xtensa_opcode_is_jump (isa, opc) > 0
1202 || xtensa_opcode_is_loop (isa, opc) > 0
1203 || xtensa_opcode_is_call (isa, opc) > 0
1204 || strcasecmp (opcname, "simcall") == 0
1205 || strcasecmp (opcname, "syscall") == 0)
1206 /* Can not continue analysis. */
1207 RETURN_FP;
1210 done:
1211 xtensa_insnbuf_free(isa, slot);
1212 xtensa_insnbuf_free(isa, ins);
1213 return fp_regnum;
1216 /* The key values to identify the frame using "cache" are
1218 cache->base = SP (or best guess about FP) of this frame;
1219 cache->pc = entry-PC (entry point of the frame function);
1220 cache->prev_sp = SP of the previous frame. */
1222 static void
1223 call0_frame_cache (struct frame_info *this_frame,
1224 xtensa_frame_cache_t *cache, CORE_ADDR pc);
1226 static void
1227 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
1228 xtensa_frame_cache_t *cache,
1229 CORE_ADDR pc);
1231 static struct xtensa_frame_cache *
1232 xtensa_frame_cache (struct frame_info *this_frame, void **this_cache)
1234 xtensa_frame_cache_t *cache;
1235 CORE_ADDR ra, wb, ws, pc, sp, ps;
1236 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1237 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1238 unsigned int fp_regnum;
1239 int windowed, ps_regnum;
1241 if (*this_cache)
1242 return (struct xtensa_frame_cache *) *this_cache;
1244 pc = get_frame_register_unsigned (this_frame, gdbarch_pc_regnum (gdbarch));
1245 ps_regnum = gdbarch_ps_regnum (gdbarch);
1246 ps = (ps_regnum >= 0
1247 ? get_frame_register_unsigned (this_frame, ps_regnum) : TX_PS);
1249 windowed = windowing_enabled (gdbarch, ps);
1251 /* Get pristine xtensa-frame. */
1252 cache = xtensa_alloc_frame_cache (windowed);
1253 *this_cache = cache;
1255 if (windowed)
1257 LONGEST op1;
1258 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1260 /* Get WINDOWBASE, WINDOWSTART, and PS registers. */
1261 wb = get_frame_register_unsigned (this_frame,
1262 tdep->wb_regnum);
1263 ws = get_frame_register_unsigned (this_frame,
1264 tdep->ws_regnum);
1266 if (safe_read_memory_integer (pc, 1, byte_order, &op1)
1267 && XTENSA_IS_ENTRY (gdbarch, op1))
1269 int callinc = CALLINC (ps);
1270 ra = get_frame_register_unsigned
1271 (this_frame, tdep->a0_base + callinc * 4);
1273 /* ENTRY hasn't been executed yet, therefore callsize is still 0. */
1274 cache->wd.callsize = 0;
1275 cache->wd.wb = wb;
1276 cache->wd.ws = ws;
1277 cache->prev_sp = get_frame_register_unsigned
1278 (this_frame, tdep->a0_base + 1);
1280 /* This only can be the outermost frame since we are
1281 just about to execute ENTRY. SP hasn't been set yet.
1282 We can assume any frame size, because it does not
1283 matter, and, let's fake frame base in cache. */
1284 cache->base = cache->prev_sp - 16;
1286 cache->pc = pc;
1287 cache->ra = (cache->pc & 0xc0000000) | (ra & 0x3fffffff);
1288 cache->ps = (ps & ~PS_CALLINC_MASK)
1289 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1291 return cache;
1293 else
1295 fp_regnum = xtensa_scan_prologue (gdbarch, pc);
1296 ra = get_frame_register_unsigned (this_frame,
1297 tdep->a0_base);
1298 cache->wd.callsize = WINSIZE (ra);
1299 cache->wd.wb = (wb - cache->wd.callsize / 4)
1300 & (tdep->num_aregs / 4 - 1);
1301 cache->wd.ws = ws & ~(1 << wb);
1303 cache->pc = get_frame_func (this_frame);
1304 cache->ra = (pc & 0xc0000000) | (ra & 0x3fffffff);
1305 cache->ps = (ps & ~PS_CALLINC_MASK)
1306 | ((WINSIZE(ra)/4) << PS_CALLINC_SHIFT);
1309 if (cache->wd.ws == 0)
1311 int i;
1313 /* Set A0...A3. */
1314 sp = get_frame_register_unsigned
1315 (this_frame, tdep->a0_base + 1) - 16;
1317 for (i = 0; i < 4; i++, sp += 4)
1319 cache->wd.aregs[i] = sp;
1322 if (cache->wd.callsize > 4)
1324 /* Set A4...A7/A11. */
1325 /* Get the SP of the frame previous to the previous one.
1326 To achieve this, we have to dereference SP twice. */
1327 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1328 sp = (CORE_ADDR) read_memory_integer (sp - 12, 4, byte_order);
1329 sp -= cache->wd.callsize * 4;
1331 for ( i = 4; i < cache->wd.callsize; i++, sp += 4)
1333 cache->wd.aregs[i] = sp;
1338 if ((cache->prev_sp == 0) && ( ra != 0 ))
1339 /* If RA is equal to 0 this frame is an outermost frame. Leave
1340 cache->prev_sp unchanged marking the boundary of the frame stack. */
1342 if ((cache->wd.ws & (1 << cache->wd.wb)) == 0)
1344 /* Register window overflow already happened.
1345 We can read caller's SP from the proper spill location. */
1346 sp = get_frame_register_unsigned
1347 (this_frame, tdep->a0_base + 1);
1348 cache->prev_sp = read_memory_integer (sp - 12, 4, byte_order);
1350 else
1352 /* Read caller's frame SP directly from the previous window. */
1353 int regnum = arreg_number
1354 (gdbarch, tdep->a0_base + 1,
1355 cache->wd.wb);
1357 cache->prev_sp = xtensa_read_register (regnum);
1361 else if (xtensa_window_interrupt_insn (gdbarch, pc))
1363 /* Execution stopped inside Xtensa Window Interrupt Handler. */
1365 xtensa_window_interrupt_frame_cache (this_frame, cache, pc);
1366 /* Everything was set already, including cache->base. */
1367 return cache;
1369 else /* Call0 framework. */
1371 call0_frame_cache (this_frame, cache, pc);
1372 fp_regnum = cache->c0.fp_regnum;
1375 cache->base = get_frame_register_unsigned (this_frame, fp_regnum);
1377 return cache;
1380 static int xtensa_session_once_reported = 1;
1382 /* Report a problem with prologue analysis while doing backtracing.
1383 But, do it only once to avoid annoying repeated messages. */
1385 static void
1386 warning_once (void)
1388 if (xtensa_session_once_reported == 0)
1389 warning (_("\
1390 \nUnrecognised function prologue. Stack trace cannot be resolved. \
1391 This message will not be repeated in this session.\n"));
1393 xtensa_session_once_reported = 1;
1397 static void
1398 xtensa_frame_this_id (struct frame_info *this_frame,
1399 void **this_cache,
1400 struct frame_id *this_id)
1402 struct xtensa_frame_cache *cache =
1403 xtensa_frame_cache (this_frame, this_cache);
1405 if (cache->prev_sp == 0)
1406 return;
1408 (*this_id) = frame_id_build (cache->prev_sp, cache->pc);
1411 static struct value *
1412 xtensa_frame_prev_register (struct frame_info *this_frame,
1413 void **this_cache,
1414 int regnum)
1416 struct gdbarch *gdbarch = get_frame_arch (this_frame);
1417 struct xtensa_frame_cache *cache;
1418 ULONGEST saved_reg = 0;
1419 int done = 1;
1420 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1422 if (*this_cache == NULL)
1423 *this_cache = xtensa_frame_cache (this_frame, this_cache);
1424 cache = (struct xtensa_frame_cache *) *this_cache;
1426 if (regnum ==gdbarch_pc_regnum (gdbarch))
1427 saved_reg = cache->ra;
1428 else if (regnum == tdep->a0_base + 1)
1429 saved_reg = cache->prev_sp;
1430 else if (!cache->call0)
1432 if (regnum == tdep->ws_regnum)
1433 saved_reg = cache->wd.ws;
1434 else if (regnum == tdep->wb_regnum)
1435 saved_reg = cache->wd.wb;
1436 else if (regnum == gdbarch_ps_regnum (gdbarch))
1437 saved_reg = cache->ps;
1438 else
1439 done = 0;
1441 else
1442 done = 0;
1444 if (done)
1445 return frame_unwind_got_constant (this_frame, regnum, saved_reg);
1447 if (!cache->call0) /* Windowed ABI. */
1449 /* Convert A-register numbers to AR-register numbers,
1450 if we deal with A-register. */
1451 if (regnum >= tdep->a0_base
1452 && regnum <= tdep->a0_base + 15)
1453 regnum = arreg_number (gdbarch, regnum, cache->wd.wb);
1455 /* Check, if we deal with AR-register saved on stack. */
1456 if (regnum >= tdep->ar_base
1457 && regnum <= (tdep->ar_base
1458 + tdep->num_aregs))
1460 int areg = areg_number (gdbarch, regnum, cache->wd.wb);
1462 if (areg >= 0
1463 && areg < XTENSA_NUM_SAVED_AREGS
1464 && cache->wd.aregs[areg] != -1)
1465 return frame_unwind_got_memory (this_frame, regnum,
1466 cache->wd.aregs[areg]);
1469 else /* Call0 ABI. */
1471 int reg = (regnum >= tdep->ar_base
1472 && regnum <= (tdep->ar_base
1473 + C0_NREGS))
1474 ? regnum - tdep->ar_base : regnum;
1476 if (reg < C0_NREGS)
1478 CORE_ADDR spe;
1479 int stkofs;
1481 /* If register was saved in the prologue, retrieve it. */
1482 stkofs = cache->c0.c0_rt[reg].to_stk;
1483 if (stkofs != C0_NOSTK)
1485 /* Determine SP on entry based on FP. */
1486 spe = cache->c0.c0_fp
1487 - cache->c0.c0_rt[cache->c0.fp_regnum].fr_ofs;
1489 return frame_unwind_got_memory (this_frame, regnum,
1490 spe + stkofs);
1495 /* All other registers have been either saved to
1496 the stack or are still alive in the processor. */
1498 return frame_unwind_got_register (this_frame, regnum, regnum);
1502 static const struct frame_unwind
1503 xtensa_unwind =
1505 "xtensa prologue",
1506 NORMAL_FRAME,
1507 default_frame_unwind_stop_reason,
1508 xtensa_frame_this_id,
1509 xtensa_frame_prev_register,
1510 NULL,
1511 default_frame_sniffer
1514 static CORE_ADDR
1515 xtensa_frame_base_address (struct frame_info *this_frame, void **this_cache)
1517 struct xtensa_frame_cache *cache =
1518 xtensa_frame_cache (this_frame, this_cache);
1520 return cache->base;
1523 static const struct frame_base
1524 xtensa_frame_base =
1526 &xtensa_unwind,
1527 xtensa_frame_base_address,
1528 xtensa_frame_base_address,
1529 xtensa_frame_base_address
1533 static void
1534 xtensa_extract_return_value (struct type *type,
1535 struct regcache *regcache,
1536 void *dst)
1538 struct gdbarch *gdbarch = regcache->arch ();
1539 bfd_byte *valbuf = (bfd_byte *) dst;
1540 int len = TYPE_LENGTH (type);
1541 ULONGEST pc, wb;
1542 int callsize, areg;
1543 int offset = 0;
1545 DEBUGTRACE ("xtensa_extract_return_value (...)\n");
1547 gdb_assert(len > 0);
1549 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1550 if (tdep->call_abi != CallAbiCall0Only)
1552 /* First, we have to find the caller window in the register file. */
1553 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1554 callsize = extract_call_winsize (gdbarch, pc);
1556 /* On Xtensa, we can return up to 4 words (or 2 for call12). */
1557 if (len > (callsize > 8 ? 8 : 16))
1558 internal_error (__FILE__, __LINE__,
1559 _("cannot extract return value of %d bytes long"),
1560 len);
1562 /* Get the register offset of the return
1563 register (A2) in the caller window. */
1564 regcache_raw_read_unsigned
1565 (regcache, tdep->wb_regnum, &wb);
1566 areg = arreg_number (gdbarch,
1567 tdep->a0_base + 2 + callsize, wb);
1569 else
1571 /* No windowing hardware - Call0 ABI. */
1572 areg = tdep->a0_base + C0_ARGS;
1575 DEBUGINFO ("[xtensa_extract_return_value] areg %d len %d\n", areg, len);
1577 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1578 offset = 4 - len;
1580 for (; len > 0; len -= 4, areg++, valbuf += 4)
1582 if (len < 4)
1583 regcache->raw_read_part (areg, offset, len, valbuf);
1584 else
1585 regcache->raw_read (areg, valbuf);
1590 static void
1591 xtensa_store_return_value (struct type *type,
1592 struct regcache *regcache,
1593 const void *dst)
1595 struct gdbarch *gdbarch = regcache->arch ();
1596 const bfd_byte *valbuf = (const bfd_byte *) dst;
1597 unsigned int areg;
1598 ULONGEST pc, wb;
1599 int callsize;
1600 int len = TYPE_LENGTH (type);
1601 int offset = 0;
1603 DEBUGTRACE ("xtensa_store_return_value (...)\n");
1605 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1606 if (tdep->call_abi != CallAbiCall0Only)
1608 regcache_raw_read_unsigned
1609 (regcache, tdep->wb_regnum, &wb);
1610 regcache_raw_read_unsigned (regcache, gdbarch_pc_regnum (gdbarch), &pc);
1611 callsize = extract_call_winsize (gdbarch, pc);
1613 if (len > (callsize > 8 ? 8 : 16))
1614 internal_error (__FILE__, __LINE__,
1615 _("unimplemented for this length: %s"),
1616 pulongest (TYPE_LENGTH (type)));
1617 areg = arreg_number (gdbarch,
1618 tdep->a0_base + 2 + callsize, wb);
1620 DEBUGTRACE ("[xtensa_store_return_value] callsize %d wb %d\n",
1621 callsize, (int) wb);
1623 else
1625 areg = tdep->a0_base + C0_ARGS;
1628 if (len < 4 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1629 offset = 4 - len;
1631 for (; len > 0; len -= 4, areg++, valbuf += 4)
1633 if (len < 4)
1634 regcache->raw_write_part (areg, offset, len, valbuf);
1635 else
1636 regcache->raw_write (areg, valbuf);
1641 static enum return_value_convention
1642 xtensa_return_value (struct gdbarch *gdbarch,
1643 struct value *function,
1644 struct type *valtype,
1645 struct regcache *regcache,
1646 gdb_byte *readbuf,
1647 const gdb_byte *writebuf)
1649 /* Structures up to 16 bytes are returned in registers. */
1651 int struct_return = ((valtype->code () == TYPE_CODE_STRUCT
1652 || valtype->code () == TYPE_CODE_UNION
1653 || valtype->code () == TYPE_CODE_ARRAY)
1654 && TYPE_LENGTH (valtype) > 16);
1656 if (struct_return)
1657 return RETURN_VALUE_STRUCT_CONVENTION;
1659 DEBUGTRACE ("xtensa_return_value(...)\n");
1661 if (writebuf != NULL)
1663 xtensa_store_return_value (valtype, regcache, writebuf);
1666 if (readbuf != NULL)
1668 gdb_assert (!struct_return);
1669 xtensa_extract_return_value (valtype, regcache, readbuf);
1671 return RETURN_VALUE_REGISTER_CONVENTION;
1675 /* DUMMY FRAME */
1677 static CORE_ADDR
1678 xtensa_push_dummy_call (struct gdbarch *gdbarch,
1679 struct value *function,
1680 struct regcache *regcache,
1681 CORE_ADDR bp_addr,
1682 int nargs,
1683 struct value **args,
1684 CORE_ADDR sp,
1685 function_call_return_method return_method,
1686 CORE_ADDR struct_addr)
1688 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1689 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1690 int size, onstack_size;
1691 gdb_byte *buf = (gdb_byte *) alloca (16);
1692 CORE_ADDR ra, ps;
1693 struct argument_info
1695 const bfd_byte *contents;
1696 int length;
1697 int onstack; /* onstack == 0 => in reg */
1698 int align; /* alignment */
1699 union
1701 int offset; /* stack offset if on stack. */
1702 int regno; /* regno if in register. */
1703 } u;
1706 struct argument_info *arg_info =
1707 (struct argument_info *) alloca (nargs * sizeof (struct argument_info));
1709 CORE_ADDR osp = sp;
1711 DEBUGTRACE ("xtensa_push_dummy_call (...)\n");
1713 if (xtensa_debug_level > 3)
1715 DEBUGINFO ("[xtensa_push_dummy_call] nargs = %d\n", nargs);
1716 DEBUGINFO ("[xtensa_push_dummy_call] sp=0x%x, return_method=%d, "
1717 "struct_addr=0x%x\n",
1718 (int) sp, (int) return_method, (int) struct_addr);
1720 for (int i = 0; i < nargs; i++)
1722 struct value *arg = args[i];
1723 struct type *arg_type = check_typedef (value_type (arg));
1724 gdb_printf (gdb_stdlog, "%2d: %s %3s ", i,
1725 host_address_to_string (arg),
1726 pulongest (TYPE_LENGTH (arg_type)));
1727 switch (arg_type->code ())
1729 case TYPE_CODE_INT:
1730 gdb_printf (gdb_stdlog, "int");
1731 break;
1732 case TYPE_CODE_STRUCT:
1733 gdb_printf (gdb_stdlog, "struct");
1734 break;
1735 default:
1736 gdb_printf (gdb_stdlog, "%3d", arg_type->code ());
1737 break;
1739 gdb_printf (gdb_stdlog, " %s\n",
1740 host_address_to_string (value_contents (arg).data ()));
1744 /* First loop: collect information.
1745 Cast into type_long. (This shouldn't happen often for C because
1746 GDB already does this earlier.) It's possible that GDB could
1747 do it all the time but it's harmless to leave this code here. */
1749 size = 0;
1750 onstack_size = 0;
1752 if (return_method == return_method_struct)
1753 size = REGISTER_SIZE;
1755 for (int i = 0; i < nargs; i++)
1757 struct argument_info *info = &arg_info[i];
1758 struct value *arg = args[i];
1759 struct type *arg_type = check_typedef (value_type (arg));
1761 switch (arg_type->code ())
1763 case TYPE_CODE_INT:
1764 case TYPE_CODE_BOOL:
1765 case TYPE_CODE_CHAR:
1766 case TYPE_CODE_RANGE:
1767 case TYPE_CODE_ENUM:
1769 /* Cast argument to long if necessary as the mask does it too. */
1770 if (TYPE_LENGTH (arg_type)
1771 < TYPE_LENGTH (builtin_type (gdbarch)->builtin_long))
1773 arg_type = builtin_type (gdbarch)->builtin_long;
1774 arg = value_cast (arg_type, arg);
1776 /* Aligment is equal to the type length for the basic types. */
1777 info->align = TYPE_LENGTH (arg_type);
1778 break;
1780 case TYPE_CODE_FLT:
1782 /* Align doubles correctly. */
1783 if (TYPE_LENGTH (arg_type)
1784 == TYPE_LENGTH (builtin_type (gdbarch)->builtin_double))
1785 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_double);
1786 else
1787 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1788 break;
1790 case TYPE_CODE_STRUCT:
1791 default:
1792 info->align = TYPE_LENGTH (builtin_type (gdbarch)->builtin_long);
1793 break;
1795 info->length = TYPE_LENGTH (arg_type);
1796 info->contents = value_contents (arg).data ();
1798 /* Align size and onstack_size. */
1799 size = (size + info->align - 1) & ~(info->align - 1);
1800 onstack_size = (onstack_size + info->align - 1) & ~(info->align - 1);
1802 if (size + info->length > REGISTER_SIZE * ARG_NOF (tdep))
1804 info->onstack = 1;
1805 info->u.offset = onstack_size;
1806 onstack_size += info->length;
1808 else
1810 info->onstack = 0;
1811 info->u.regno = ARG_1ST (tdep) + size / REGISTER_SIZE;
1813 size += info->length;
1816 /* Adjust the stack pointer and align it. */
1817 sp = align_down (sp - onstack_size, SP_ALIGNMENT);
1819 /* Simulate MOVSP, if Windowed ABI. */
1820 if ((tdep->call_abi != CallAbiCall0Only)
1821 && (sp != osp))
1823 read_memory (osp - 16, buf, 16);
1824 write_memory (sp - 16, buf, 16);
1827 /* Second Loop: Load arguments. */
1829 if (return_method == return_method_struct)
1831 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, struct_addr);
1832 regcache->cooked_write (ARG_1ST (tdep), buf);
1835 for (int i = 0; i < nargs; i++)
1837 struct argument_info *info = &arg_info[i];
1839 if (info->onstack)
1841 int n = info->length;
1842 CORE_ADDR offset = sp + info->u.offset;
1844 /* Odd-sized structs are aligned to the lower side of a memory
1845 word in big-endian mode and require a shift. This only
1846 applies for structures smaller than one word. */
1848 if (n < REGISTER_SIZE
1849 && gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1850 offset += (REGISTER_SIZE - n);
1852 write_memory (offset, info->contents, info->length);
1855 else
1857 int n = info->length;
1858 const bfd_byte *cp = info->contents;
1859 int r = info->u.regno;
1861 /* Odd-sized structs are aligned to the lower side of registers in
1862 big-endian mode and require a shift. The odd-sized leftover will
1863 be at the end. Note that this is only true for structures smaller
1864 than REGISTER_SIZE; for larger odd-sized structures the excess
1865 will be left-aligned in the register on both endiannesses. */
1867 if (n < REGISTER_SIZE && byte_order == BFD_ENDIAN_BIG)
1869 ULONGEST v;
1870 v = extract_unsigned_integer (cp, REGISTER_SIZE, byte_order);
1871 v = v >> ((REGISTER_SIZE - n) * TARGET_CHAR_BIT);
1873 store_unsigned_integer (buf, REGISTER_SIZE, byte_order, v);
1874 regcache->cooked_write (r, buf);
1876 cp += REGISTER_SIZE;
1877 n -= REGISTER_SIZE;
1878 r++;
1880 else
1881 while (n > 0)
1883 regcache->cooked_write (r, cp);
1885 cp += REGISTER_SIZE;
1886 n -= REGISTER_SIZE;
1887 r++;
1892 /* Set the return address of dummy frame to the dummy address.
1893 The return address for the current function (in A0) is
1894 saved in the dummy frame, so we can safely overwrite A0 here. */
1896 if (tdep->call_abi != CallAbiCall0Only)
1898 ULONGEST val;
1900 ra = (bp_addr & 0x3fffffff) | 0x40000000;
1901 regcache_raw_read_unsigned (regcache, gdbarch_ps_regnum (gdbarch), &val);
1902 ps = (unsigned long) val & ~0x00030000;
1903 regcache_cooked_write_unsigned
1904 (regcache, tdep->a0_base + 4, ra);
1905 regcache_cooked_write_unsigned (regcache,
1906 gdbarch_ps_regnum (gdbarch),
1907 ps | 0x00010000);
1909 /* All the registers have been saved. After executing
1910 dummy call, they all will be restored. So it's safe
1911 to modify WINDOWSTART register to make it look like there
1912 is only one register window corresponding to WINDOWEBASE. */
1914 regcache->raw_read (tdep->wb_regnum, buf);
1915 regcache_cooked_write_unsigned
1916 (regcache, tdep->ws_regnum,
1917 1 << extract_unsigned_integer (buf, 4, byte_order));
1919 else
1921 /* Simulate CALL0: write RA into A0 register. */
1922 regcache_cooked_write_unsigned
1923 (regcache, tdep->a0_base, bp_addr);
1926 /* Set new stack pointer and return it. */
1927 regcache_cooked_write_unsigned (regcache,
1928 tdep->a0_base + 1, sp);
1929 /* Make dummy frame ID unique by adding a constant. */
1930 return sp + SP_ALIGNMENT;
1933 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1935 static int
1936 xtensa_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
1938 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
1940 if (tdep->isa_use_density_instructions)
1941 return 2;
1942 else
1943 return 4;
1946 /* Return a breakpoint for the current location of PC. We always use
1947 the density version if we have density instructions (regardless of the
1948 current instruction at PC), and use regular instructions otherwise. */
1950 #define BIG_BREAKPOINT { 0x00, 0x04, 0x00 }
1951 #define LITTLE_BREAKPOINT { 0x00, 0x40, 0x00 }
1952 #define DENSITY_BIG_BREAKPOINT { 0xd2, 0x0f }
1953 #define DENSITY_LITTLE_BREAKPOINT { 0x2d, 0xf0 }
1955 /* Implement the sw_breakpoint_from_kind gdbarch method. */
1957 static const gdb_byte *
1958 xtensa_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
1960 *size = kind;
1962 if (kind == 4)
1964 static unsigned char big_breakpoint[] = BIG_BREAKPOINT;
1965 static unsigned char little_breakpoint[] = LITTLE_BREAKPOINT;
1967 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1968 return big_breakpoint;
1969 else
1970 return little_breakpoint;
1972 else
1974 static unsigned char density_big_breakpoint[] = DENSITY_BIG_BREAKPOINT;
1975 static unsigned char density_little_breakpoint[]
1976 = DENSITY_LITTLE_BREAKPOINT;
1978 if (gdbarch_byte_order (gdbarch) == BFD_ENDIAN_BIG)
1979 return density_big_breakpoint;
1980 else
1981 return density_little_breakpoint;
1985 /* Call0 ABI support routines. */
1987 /* Return true, if PC points to "ret" or "ret.n". */
1989 static int
1990 call0_ret (CORE_ADDR start_pc, CORE_ADDR finish_pc)
1992 #define RETURN_RET goto done
1993 xtensa_isa isa;
1994 xtensa_insnbuf ins, slot;
1995 gdb_byte ibuf[XTENSA_ISA_BSZ];
1996 CORE_ADDR ia, bt, ba;
1997 xtensa_format ifmt;
1998 int ilen, islots, is;
1999 xtensa_opcode opc;
2000 const char *opcname;
2001 int found_ret = 0;
2003 isa = xtensa_default_isa;
2004 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2005 ins = xtensa_insnbuf_alloc (isa);
2006 slot = xtensa_insnbuf_alloc (isa);
2007 ba = 0;
2009 for (ia = start_pc, bt = ia; ia < finish_pc ; ia += ilen)
2011 if (ia + xtensa_isa_maxlength (isa) > bt)
2013 ba = ia;
2014 bt = (ba + XTENSA_ISA_BSZ) < finish_pc
2015 ? ba + XTENSA_ISA_BSZ : finish_pc;
2016 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2017 RETURN_RET;
2020 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2021 ifmt = xtensa_format_decode (isa, ins);
2022 if (ifmt == XTENSA_UNDEFINED)
2023 RETURN_RET;
2024 ilen = xtensa_format_length (isa, ifmt);
2025 if (ilen == XTENSA_UNDEFINED)
2026 RETURN_RET;
2027 islots = xtensa_format_num_slots (isa, ifmt);
2028 if (islots == XTENSA_UNDEFINED)
2029 RETURN_RET;
2031 for (is = 0; is < islots; ++is)
2033 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2034 RETURN_RET;
2036 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2037 if (opc == XTENSA_UNDEFINED)
2038 RETURN_RET;
2040 opcname = xtensa_opcode_name (isa, opc);
2042 if ((strcasecmp (opcname, "ret.n") == 0)
2043 || (strcasecmp (opcname, "ret") == 0))
2045 found_ret = 1;
2046 RETURN_RET;
2050 done:
2051 xtensa_insnbuf_free(isa, slot);
2052 xtensa_insnbuf_free(isa, ins);
2053 return found_ret;
2056 /* Call0 opcode class. Opcodes are preclassified according to what they
2057 mean for Call0 prologue analysis, and their number of significant operands.
2058 The purpose of this is to simplify prologue analysis by separating
2059 instruction decoding (libisa) from the semantics of prologue analysis. */
2061 enum xtensa_insn_kind
2063 c0opc_illegal, /* Unknown to libisa (invalid) or 'ill' opcode. */
2064 c0opc_uninteresting, /* Not interesting for Call0 prologue analysis. */
2065 c0opc_flow, /* Flow control insn. */
2066 c0opc_entry, /* ENTRY indicates non-Call0 prologue. */
2067 c0opc_break, /* Debugger software breakpoints. */
2068 c0opc_add, /* Adding two registers. */
2069 c0opc_addi, /* Adding a register and an immediate. */
2070 c0opc_and, /* Bitwise "and"-ing two registers. */
2071 c0opc_sub, /* Subtracting a register from a register. */
2072 c0opc_mov, /* Moving a register to a register. */
2073 c0opc_movi, /* Moving an immediate to a register. */
2074 c0opc_l32r, /* Loading a literal. */
2075 c0opc_s32i, /* Storing word at fixed offset from a base register. */
2076 c0opc_rwxsr, /* RSR, WRS, or XSR instructions. */
2077 c0opc_l32e, /* L32E instruction. */
2078 c0opc_s32e, /* S32E instruction. */
2079 c0opc_rfwo, /* RFWO instruction. */
2080 c0opc_rfwu, /* RFWU instruction. */
2081 c0opc_NrOf /* Number of opcode classifications. */
2084 /* Return true, if OPCNAME is RSR, WRS, or XSR instruction. */
2086 static int
2087 rwx_special_register (const char *opcname)
2089 char ch = *opcname++;
2091 if ((ch != 'r') && (ch != 'w') && (ch != 'x'))
2092 return 0;
2093 if (*opcname++ != 's')
2094 return 0;
2095 if (*opcname++ != 'r')
2096 return 0;
2097 if (*opcname++ != '.')
2098 return 0;
2100 return 1;
2103 /* Classify an opcode based on what it means for Call0 prologue analysis. */
2105 static xtensa_insn_kind
2106 call0_classify_opcode (xtensa_isa isa, xtensa_opcode opc)
2108 const char *opcname;
2109 xtensa_insn_kind opclass = c0opc_uninteresting;
2111 DEBUGTRACE ("call0_classify_opcode (..., opc = %d)\n", opc);
2113 /* Get opcode name and handle special classifications. */
2115 opcname = xtensa_opcode_name (isa, opc);
2117 if (opcname == NULL
2118 || strcasecmp (opcname, "ill") == 0
2119 || strcasecmp (opcname, "ill.n") == 0)
2120 opclass = c0opc_illegal;
2121 else if (strcasecmp (opcname, "break") == 0
2122 || strcasecmp (opcname, "break.n") == 0)
2123 opclass = c0opc_break;
2124 else if (strcasecmp (opcname, "entry") == 0)
2125 opclass = c0opc_entry;
2126 else if (strcasecmp (opcname, "rfwo") == 0)
2127 opclass = c0opc_rfwo;
2128 else if (strcasecmp (opcname, "rfwu") == 0)
2129 opclass = c0opc_rfwu;
2130 else if (xtensa_opcode_is_branch (isa, opc) > 0
2131 || xtensa_opcode_is_jump (isa, opc) > 0
2132 || xtensa_opcode_is_loop (isa, opc) > 0
2133 || xtensa_opcode_is_call (isa, opc) > 0
2134 || strcasecmp (opcname, "simcall") == 0
2135 || strcasecmp (opcname, "syscall") == 0)
2136 opclass = c0opc_flow;
2138 /* Also, classify specific opcodes that need to be tracked. */
2139 else if (strcasecmp (opcname, "add") == 0
2140 || strcasecmp (opcname, "add.n") == 0)
2141 opclass = c0opc_add;
2142 else if (strcasecmp (opcname, "and") == 0)
2143 opclass = c0opc_and;
2144 else if (strcasecmp (opcname, "addi") == 0
2145 || strcasecmp (opcname, "addi.n") == 0
2146 || strcasecmp (opcname, "addmi") == 0)
2147 opclass = c0opc_addi;
2148 else if (strcasecmp (opcname, "sub") == 0)
2149 opclass = c0opc_sub;
2150 else if (strcasecmp (opcname, "mov.n") == 0
2151 || strcasecmp (opcname, "or") == 0) /* Could be 'mov' asm macro. */
2152 opclass = c0opc_mov;
2153 else if (strcasecmp (opcname, "movi") == 0
2154 || strcasecmp (opcname, "movi.n") == 0)
2155 opclass = c0opc_movi;
2156 else if (strcasecmp (opcname, "l32r") == 0)
2157 opclass = c0opc_l32r;
2158 else if (strcasecmp (opcname, "s32i") == 0
2159 || strcasecmp (opcname, "s32i.n") == 0)
2160 opclass = c0opc_s32i;
2161 else if (strcasecmp (opcname, "l32e") == 0)
2162 opclass = c0opc_l32e;
2163 else if (strcasecmp (opcname, "s32e") == 0)
2164 opclass = c0opc_s32e;
2165 else if (rwx_special_register (opcname))
2166 opclass = c0opc_rwxsr;
2168 return opclass;
2171 /* Tracks register movement/mutation for a given operation, which may
2172 be within a bundle. Updates the destination register tracking info
2173 accordingly. The pc is needed only for pc-relative load instructions
2174 (eg. l32r). The SP register number is needed to identify stores to
2175 the stack frame. Returns 0, if analysis was successful, non-zero
2176 otherwise. */
2178 static int
2179 call0_track_op (struct gdbarch *gdbarch, xtensa_c0reg_t dst[], xtensa_c0reg_t src[],
2180 xtensa_insn_kind opclass, int nods, unsigned odv[],
2181 CORE_ADDR pc, int spreg, xtensa_frame_cache_t *cache)
2183 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2184 unsigned litbase, litaddr, litval;
2185 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2187 switch (opclass)
2189 case c0opc_addi:
2190 /* 3 operands: dst, src, imm. */
2191 gdb_assert (nods == 3);
2192 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2193 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + odv[2];
2194 break;
2195 case c0opc_add:
2196 /* 3 operands: dst, src1, src2. */
2197 gdb_assert (nods == 3);
2198 if (src[odv[1]].fr_reg == C0_CONST)
2200 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2201 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs + src[odv[1]].fr_ofs;
2203 else if (src[odv[2]].fr_reg == C0_CONST)
2205 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2206 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs + src[odv[2]].fr_ofs;
2208 else dst[odv[0]].fr_reg = C0_INEXP;
2209 break;
2210 case c0opc_and:
2211 /* 3 operands: dst, src1, src2. */
2212 gdb_assert (nods == 3);
2213 if (cache->c0.c0_fpalign == 0)
2215 /* Handle dynamic stack alignment. */
2216 if ((src[odv[0]].fr_reg == spreg) && (src[odv[1]].fr_reg == spreg))
2218 if (src[odv[2]].fr_reg == C0_CONST)
2219 cache->c0.c0_fpalign = src[odv[2]].fr_ofs;
2220 break;
2222 else if ((src[odv[0]].fr_reg == spreg)
2223 && (src[odv[2]].fr_reg == spreg))
2225 if (src[odv[1]].fr_reg == C0_CONST)
2226 cache->c0.c0_fpalign = src[odv[1]].fr_ofs;
2227 break;
2229 /* else fall through. */
2231 if (src[odv[1]].fr_reg == C0_CONST)
2233 dst[odv[0]].fr_reg = src[odv[2]].fr_reg;
2234 dst[odv[0]].fr_ofs = src[odv[2]].fr_ofs & src[odv[1]].fr_ofs;
2236 else if (src[odv[2]].fr_reg == C0_CONST)
2238 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2239 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs & src[odv[2]].fr_ofs;
2241 else dst[odv[0]].fr_reg = C0_INEXP;
2242 break;
2243 case c0opc_sub:
2244 /* 3 operands: dst, src1, src2. */
2245 gdb_assert (nods == 3);
2246 if (src[odv[2]].fr_reg == C0_CONST)
2248 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2249 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs - src[odv[2]].fr_ofs;
2251 else dst[odv[0]].fr_reg = C0_INEXP;
2252 break;
2253 case c0opc_mov:
2254 /* 2 operands: dst, src [, src]. */
2255 gdb_assert (nods == 2);
2256 /* First, check if it's a special case of saving unaligned SP
2257 to a spare register in case of dynamic stack adjustment.
2258 But, only do it one time. The second time could be initializing
2259 frame pointer. We don't want to overwrite the first one. */
2260 if ((odv[1] == spreg) && (cache->c0.c0_old_sp == C0_INEXP))
2261 cache->c0.c0_old_sp = odv[0];
2263 dst[odv[0]].fr_reg = src[odv[1]].fr_reg;
2264 dst[odv[0]].fr_ofs = src[odv[1]].fr_ofs;
2265 break;
2266 case c0opc_movi:
2267 /* 2 operands: dst, imm. */
2268 gdb_assert (nods == 2);
2269 dst[odv[0]].fr_reg = C0_CONST;
2270 dst[odv[0]].fr_ofs = odv[1];
2271 break;
2272 case c0opc_l32r:
2273 /* 2 operands: dst, literal offset. */
2274 gdb_assert (nods == 2);
2275 /* litbase = xtensa_get_litbase (pc); can be also used. */
2276 litbase = (tdep->litbase_regnum == -1)
2277 ? 0 : xtensa_read_register
2278 (tdep->litbase_regnum);
2279 litaddr = litbase & 1
2280 ? (litbase & ~1) + (signed)odv[1]
2281 : (pc + 3 + (signed)odv[1]) & ~3;
2282 litval = read_memory_integer (litaddr, 4, byte_order);
2283 dst[odv[0]].fr_reg = C0_CONST;
2284 dst[odv[0]].fr_ofs = litval;
2285 break;
2286 case c0opc_s32i:
2287 /* 3 operands: value, base, offset. */
2288 gdb_assert (nods == 3 && spreg >= 0 && spreg < C0_NREGS);
2289 /* First, check if it's a spill for saved unaligned SP,
2290 when dynamic stack adjustment was applied to this frame. */
2291 if ((cache->c0.c0_fpalign != 0) /* Dynamic stack adjustment. */
2292 && (odv[1] == spreg) /* SP usage indicates spill. */
2293 && (odv[0] == cache->c0.c0_old_sp)) /* Old SP register spilled. */
2294 cache->c0.c0_sp_ofs = odv[2];
2296 if (src[odv[1]].fr_reg == spreg /* Store to stack frame. */
2297 && (src[odv[1]].fr_ofs & 3) == 0 /* Alignment preserved. */
2298 && src[odv[0]].fr_reg >= 0 /* Value is from a register. */
2299 && src[odv[0]].fr_ofs == 0 /* Value hasn't been modified. */
2300 && src[src[odv[0]].fr_reg].to_stk == C0_NOSTK) /* First time. */
2302 /* ISA encoding guarantees alignment. But, check it anyway. */
2303 gdb_assert ((odv[2] & 3) == 0);
2304 dst[src[odv[0]].fr_reg].to_stk = src[odv[1]].fr_ofs + odv[2];
2306 break;
2307 /* If we end up inside Window Overflow / Underflow interrupt handler
2308 report an error because these handlers should have been handled
2309 already in a different way. */
2310 case c0opc_l32e:
2311 case c0opc_s32e:
2312 case c0opc_rfwo:
2313 case c0opc_rfwu:
2314 return 1;
2315 default:
2316 return 1;
2318 return 0;
2321 /* Analyze prologue of the function at start address to determine if it uses
2322 the Call0 ABI, and if so track register moves and linear modifications
2323 in the prologue up to the PC or just beyond the prologue, whichever is
2324 first. An 'entry' instruction indicates non-Call0 ABI and the end of the
2325 prologue. The prologue may overlap non-prologue instructions but is
2326 guaranteed to end by the first flow-control instruction (jump, branch,
2327 call or return). Since an optimized function may move information around
2328 and change the stack frame arbitrarily during the prologue, the information
2329 is guaranteed valid only at the point in the function indicated by the PC.
2330 May be used to skip the prologue or identify the ABI, w/o tracking.
2332 Returns: Address of first instruction after prologue, or PC (whichever
2333 is first), or 0, if decoding failed (in libisa).
2334 Input args:
2335 start Start address of function/prologue.
2336 pc Program counter to stop at. Use 0 to continue to end of prologue.
2337 If 0, avoids infinite run-on in corrupt code memory by bounding
2338 the scan to the end of the function if that can be determined.
2339 nregs Number of general registers to track.
2340 InOut args:
2341 cache Xtensa frame cache.
2343 Note that these may produce useful results even if decoding fails
2344 because they begin with default assumptions that analysis may change. */
2346 static CORE_ADDR
2347 call0_analyze_prologue (struct gdbarch *gdbarch,
2348 CORE_ADDR start, CORE_ADDR pc,
2349 int nregs, xtensa_frame_cache_t *cache)
2351 CORE_ADDR ia; /* Current insn address in prologue. */
2352 CORE_ADDR ba = 0; /* Current address at base of insn buffer. */
2353 CORE_ADDR bt; /* Current address at top+1 of insn buffer. */
2354 gdb_byte ibuf[XTENSA_ISA_BSZ];/* Instruction buffer for decoding prologue. */
2355 xtensa_isa isa; /* libisa ISA handle. */
2356 xtensa_insnbuf ins, slot; /* libisa handle to decoded insn, slot. */
2357 xtensa_format ifmt; /* libisa instruction format. */
2358 int ilen, islots, is; /* Instruction length, nbr slots, current slot. */
2359 xtensa_opcode opc; /* Opcode in current slot. */
2360 xtensa_insn_kind opclass; /* Opcode class for Call0 prologue analysis. */
2361 int nods; /* Opcode number of operands. */
2362 unsigned odv[C0_MAXOPDS]; /* Operand values in order provided by libisa. */
2363 xtensa_c0reg_t *rtmp; /* Register tracking info snapshot. */
2364 int j; /* General loop counter. */
2365 int fail = 0; /* Set non-zero and exit, if decoding fails. */
2366 CORE_ADDR body_pc; /* The PC for the first non-prologue insn. */
2367 CORE_ADDR end_pc; /* The PC for the lust function insn. */
2369 struct symtab_and_line prologue_sal;
2371 DEBUGTRACE ("call0_analyze_prologue (start = 0x%08x, pc = 0x%08x, ...)\n",
2372 (int)start, (int)pc);
2374 /* Try to limit the scan to the end of the function if a non-zero pc
2375 arg was not supplied to avoid probing beyond the end of valid memory.
2376 If memory is full of garbage that classifies as c0opc_uninteresting.
2377 If this fails (eg. if no symbols) pc ends up 0 as it was.
2378 Initialize the Call0 frame and register tracking info.
2379 Assume it's Call0 until an 'entry' instruction is encountered.
2380 Assume we may be in the prologue until we hit a flow control instr. */
2382 rtmp = NULL;
2383 body_pc = UINT_MAX;
2384 end_pc = 0;
2386 /* Find out, if we have an information about the prologue from DWARF. */
2387 prologue_sal = find_pc_line (start, 0);
2388 if (prologue_sal.line != 0) /* Found debug info. */
2389 body_pc = prologue_sal.end;
2391 /* If we are going to analyze the prologue in general without knowing about
2392 the current PC, make the best assumption for the end of the prologue. */
2393 if (pc == 0)
2395 find_pc_partial_function (start, 0, NULL, &end_pc);
2396 body_pc = std::min (end_pc, body_pc);
2398 else
2399 body_pc = std::min (pc, body_pc);
2401 cache->call0 = 1;
2402 rtmp = (xtensa_c0reg_t*) alloca(nregs * sizeof(xtensa_c0reg_t));
2404 isa = xtensa_default_isa;
2405 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2406 ins = xtensa_insnbuf_alloc (isa);
2407 slot = xtensa_insnbuf_alloc (isa);
2409 for (ia = start, bt = ia; ia < body_pc ; ia += ilen)
2411 /* (Re)fill instruction buffer from memory if necessary, but do not
2412 read memory beyond PC to be sure we stay within text section
2413 (this protection only works if a non-zero pc is supplied). */
2415 if (ia + xtensa_isa_maxlength (isa) > bt)
2417 ba = ia;
2418 bt = (ba + XTENSA_ISA_BSZ) < body_pc ? ba + XTENSA_ISA_BSZ : body_pc;
2419 if (target_read_memory (ba, ibuf, bt - ba) != 0 )
2420 error (_("Unable to read target memory ..."));
2423 /* Decode format information. */
2425 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2426 ifmt = xtensa_format_decode (isa, ins);
2427 if (ifmt == XTENSA_UNDEFINED)
2429 fail = 1;
2430 goto done;
2432 ilen = xtensa_format_length (isa, ifmt);
2433 if (ilen == XTENSA_UNDEFINED)
2435 fail = 1;
2436 goto done;
2438 islots = xtensa_format_num_slots (isa, ifmt);
2439 if (islots == XTENSA_UNDEFINED)
2441 fail = 1;
2442 goto done;
2445 /* Analyze a bundle or a single instruction, using a snapshot of
2446 the register tracking info as input for the entire bundle so that
2447 register changes do not take effect within this bundle. */
2449 for (j = 0; j < nregs; ++j)
2450 rtmp[j] = cache->c0.c0_rt[j];
2452 for (is = 0; is < islots; ++is)
2454 /* Decode a slot and classify the opcode. */
2456 fail = xtensa_format_get_slot (isa, ifmt, is, ins, slot);
2457 if (fail)
2458 goto done;
2460 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2461 DEBUGVERB ("[call0_analyze_prologue] instr addr = 0x%08x, opc = %d\n",
2462 (unsigned)ia, opc);
2463 if (opc == XTENSA_UNDEFINED)
2464 opclass = c0opc_illegal;
2465 else
2466 opclass = call0_classify_opcode (isa, opc);
2468 /* Decide whether to track this opcode, ignore it, or bail out. */
2470 switch (opclass)
2472 case c0opc_illegal:
2473 case c0opc_break:
2474 fail = 1;
2475 goto done;
2477 case c0opc_uninteresting:
2478 continue;
2480 case c0opc_flow: /* Flow control instructions stop analysis. */
2481 case c0opc_rwxsr: /* RSR, WSR, XSR instructions stop analysis. */
2482 goto done;
2484 case c0opc_entry:
2485 cache->call0 = 0;
2486 ia += ilen; /* Skip over 'entry' insn. */
2487 goto done;
2489 default:
2490 cache->call0 = 1;
2493 /* Only expected opcodes should get this far. */
2495 /* Extract and decode the operands. */
2496 nods = xtensa_opcode_num_operands (isa, opc);
2497 if (nods == XTENSA_UNDEFINED)
2499 fail = 1;
2500 goto done;
2503 for (j = 0; j < nods && j < C0_MAXOPDS; ++j)
2505 fail = xtensa_operand_get_field (isa, opc, j, ifmt,
2506 is, slot, &odv[j]);
2507 if (fail)
2508 goto done;
2510 fail = xtensa_operand_decode (isa, opc, j, &odv[j]);
2511 if (fail)
2512 goto done;
2515 /* Check operands to verify use of 'mov' assembler macro. */
2516 if (opclass == c0opc_mov && nods == 3)
2518 if (odv[2] == odv[1])
2520 nods = 2;
2521 if ((odv[0] == 1) && (odv[1] != 1))
2522 /* OR A1, An, An , where n != 1.
2523 This means we are inside epilogue already. */
2524 goto done;
2526 else
2528 opclass = c0opc_uninteresting;
2529 continue;
2533 /* Track register movement and modification for this operation. */
2534 fail = call0_track_op (gdbarch, cache->c0.c0_rt, rtmp,
2535 opclass, nods, odv, ia, 1, cache);
2536 if (fail)
2537 goto done;
2540 done:
2541 DEBUGVERB ("[call0_analyze_prologue] stopped at instr addr 0x%08x, %s\n",
2542 (unsigned)ia, fail ? "failed" : "succeeded");
2543 xtensa_insnbuf_free(isa, slot);
2544 xtensa_insnbuf_free(isa, ins);
2545 return fail ? XTENSA_ISA_BADPC : ia;
2548 /* Initialize frame cache for the current frame in CALL0 ABI. */
2550 static void
2551 call0_frame_cache (struct frame_info *this_frame,
2552 xtensa_frame_cache_t *cache, CORE_ADDR pc)
2554 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2555 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
2556 CORE_ADDR start_pc; /* The beginning of the function. */
2557 CORE_ADDR body_pc=UINT_MAX; /* PC, where prologue analysis stopped. */
2558 CORE_ADDR sp, fp, ra;
2559 int fp_regnum = C0_SP, c0_hasfp = 0, c0_frmsz = 0, prev_sp = 0, to_stk;
2560 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2562 sp = get_frame_register_unsigned
2563 (this_frame, tdep->a0_base + 1);
2564 fp = sp; /* Assume FP == SP until proven otherwise. */
2566 /* Find the beginning of the prologue of the function containing the PC
2567 and analyze it up to the PC or the end of the prologue. */
2569 if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
2571 body_pc = call0_analyze_prologue (gdbarch, start_pc, pc, C0_NREGS, cache);
2573 if (body_pc == XTENSA_ISA_BADPC)
2575 warning_once ();
2576 ra = 0;
2577 goto finish_frame_analysis;
2581 /* Get the frame information and FP (if used) at the current PC.
2582 If PC is in the prologue, the prologue analysis is more reliable
2583 than DWARF info. We don't not know for sure, if PC is in the prologue,
2584 but we do know no calls have yet taken place, so we can almost
2585 certainly rely on the prologue analysis. */
2587 if (body_pc <= pc)
2589 /* Prologue analysis was successful up to the PC.
2590 It includes the cases when PC == START_PC. */
2591 c0_hasfp = cache->c0.c0_rt[C0_FP].fr_reg == C0_SP;
2592 /* c0_hasfp == true means there is a frame pointer because
2593 we analyzed the prologue and found that cache->c0.c0_rt[C0_FP]
2594 was derived from SP. Otherwise, it would be C0_FP. */
2595 fp_regnum = c0_hasfp ? C0_FP : C0_SP;
2596 c0_frmsz = - cache->c0.c0_rt[fp_regnum].fr_ofs;
2597 fp_regnum += tdep->a0_base;
2599 else /* No data from the prologue analysis. */
2601 c0_hasfp = 0;
2602 fp_regnum = tdep->a0_base + C0_SP;
2603 c0_frmsz = 0;
2604 start_pc = pc;
2607 if (cache->c0.c0_fpalign)
2609 /* This frame has a special prologue with a dynamic stack adjustment
2610 to force an alignment, which is bigger than standard 16 bytes. */
2612 CORE_ADDR unaligned_sp;
2614 if (cache->c0.c0_old_sp == C0_INEXP)
2615 /* This can't be. Prologue code should be consistent.
2616 Unaligned stack pointer should be saved in a spare register. */
2618 warning_once ();
2619 ra = 0;
2620 goto finish_frame_analysis;
2623 if (cache->c0.c0_sp_ofs == C0_NOSTK)
2624 /* Saved unaligned value of SP is kept in a register. */
2625 unaligned_sp = get_frame_register_unsigned
2626 (this_frame, tdep->a0_base + cache->c0.c0_old_sp);
2627 else
2628 /* Get the value from stack. */
2629 unaligned_sp = (CORE_ADDR)
2630 read_memory_integer (fp + cache->c0.c0_sp_ofs, 4, byte_order);
2632 prev_sp = unaligned_sp + c0_frmsz;
2634 else
2635 prev_sp = fp + c0_frmsz;
2637 /* Frame size from debug info or prologue tracking does not account for
2638 alloca() and other dynamic allocations. Adjust frame size by FP - SP. */
2639 if (c0_hasfp)
2641 fp = get_frame_register_unsigned (this_frame, fp_regnum);
2643 /* Update the stack frame size. */
2644 c0_frmsz += fp - sp;
2647 /* Get the return address (RA) from the stack if saved,
2648 or try to get it from a register. */
2650 to_stk = cache->c0.c0_rt[C0_RA].to_stk;
2651 if (to_stk != C0_NOSTK)
2652 ra = (CORE_ADDR)
2653 read_memory_integer (sp + c0_frmsz + cache->c0.c0_rt[C0_RA].to_stk,
2654 4, byte_order);
2656 else if (cache->c0.c0_rt[C0_RA].fr_reg == C0_CONST
2657 && cache->c0.c0_rt[C0_RA].fr_ofs == 0)
2659 /* Special case for terminating backtrace at a function that wants to
2660 be seen as the outermost one. Such a function will clear it's RA (A0)
2661 register to 0 in the prologue instead of saving its original value. */
2662 ra = 0;
2664 else
2666 /* RA was copied to another register or (before any function call) may
2667 still be in the original RA register. This is not always reliable:
2668 even in a leaf function, register tracking stops after prologue, and
2669 even in prologue, non-prologue instructions (not tracked) may overwrite
2670 RA or any register it was copied to. If likely in prologue or before
2671 any call, use retracking info and hope for the best (compiler should
2672 have saved RA in stack if not in a leaf function). If not in prologue,
2673 too bad. */
2675 int i;
2676 for (i = 0;
2677 (i < C0_NREGS)
2678 && (i == C0_RA || cache->c0.c0_rt[i].fr_reg != C0_RA);
2679 ++i);
2680 if (i >= C0_NREGS && cache->c0.c0_rt[C0_RA].fr_reg == C0_RA)
2681 i = C0_RA;
2682 if (i < C0_NREGS)
2684 ra = get_frame_register_unsigned
2685 (this_frame,
2686 tdep->a0_base + cache->c0.c0_rt[i].fr_reg);
2688 else ra = 0;
2691 finish_frame_analysis:
2692 cache->pc = start_pc;
2693 cache->ra = ra;
2694 /* RA == 0 marks the outermost frame. Do not go past it. */
2695 cache->prev_sp = (ra != 0) ? prev_sp : 0;
2696 cache->c0.fp_regnum = fp_regnum;
2697 cache->c0.c0_frmsz = c0_frmsz;
2698 cache->c0.c0_hasfp = c0_hasfp;
2699 cache->c0.c0_fp = fp;
2702 static CORE_ADDR a0_saved;
2703 static CORE_ADDR a7_saved;
2704 static CORE_ADDR a11_saved;
2705 static int a0_was_saved;
2706 static int a7_was_saved;
2707 static int a11_was_saved;
2709 /* Simulate L32E instruction: AT <-- ref (AS + offset). */
2710 static void
2711 execute_l32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2713 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2714 int atreg = arreg_number (gdbarch, tdep->a0_base + at, wb);
2715 int asreg = arreg_number (gdbarch, tdep->a0_base + as, wb);
2716 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2717 unsigned int spilled_value
2718 = read_memory_unsigned_integer (addr, 4, gdbarch_byte_order (gdbarch));
2720 if ((at == 0) && !a0_was_saved)
2722 a0_saved = xtensa_read_register (atreg);
2723 a0_was_saved = 1;
2725 else if ((at == 7) && !a7_was_saved)
2727 a7_saved = xtensa_read_register (atreg);
2728 a7_was_saved = 1;
2730 else if ((at == 11) && !a11_was_saved)
2732 a11_saved = xtensa_read_register (atreg);
2733 a11_was_saved = 1;
2736 xtensa_write_register (atreg, spilled_value);
2739 /* Simulate S32E instruction: AT --> ref (AS + offset). */
2740 static void
2741 execute_s32e (struct gdbarch *gdbarch, int at, int as, int offset, CORE_ADDR wb)
2743 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2744 int atreg = arreg_number (gdbarch, tdep->a0_base + at, wb);
2745 int asreg = arreg_number (gdbarch, tdep->a0_base + as, wb);
2746 CORE_ADDR addr = xtensa_read_register (asreg) + offset;
2747 ULONGEST spilled_value = xtensa_read_register (atreg);
2749 write_memory_unsigned_integer (addr, 4,
2750 gdbarch_byte_order (gdbarch),
2751 spilled_value);
2754 #define XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN 200
2756 enum xtensa_exception_handler_t
2758 xtWindowOverflow,
2759 xtWindowUnderflow,
2760 xtNoExceptionHandler
2763 /* Execute instruction stream from current PC until hitting RFWU or RFWO.
2764 Return type of Xtensa Window Interrupt Handler on success. */
2765 static xtensa_exception_handler_t
2766 execute_code (struct gdbarch *gdbarch, CORE_ADDR current_pc, CORE_ADDR wb)
2768 xtensa_isa isa;
2769 xtensa_insnbuf ins, slot;
2770 gdb_byte ibuf[XTENSA_ISA_BSZ];
2771 CORE_ADDR ia, bt, ba;
2772 xtensa_format ifmt;
2773 int ilen, islots, is;
2774 xtensa_opcode opc;
2775 int insn_num = 0;
2776 void (*func) (struct gdbarch *, int, int, int, CORE_ADDR);
2777 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2779 uint32_t at, as, offset;
2781 /* WindowUnderflow12 = true, when inside _WindowUnderflow12. */
2782 int WindowUnderflow12 = (current_pc & 0x1ff) >= 0x140;
2784 isa = xtensa_default_isa;
2785 gdb_assert (XTENSA_ISA_BSZ >= xtensa_isa_maxlength (isa));
2786 ins = xtensa_insnbuf_alloc (isa);
2787 slot = xtensa_insnbuf_alloc (isa);
2788 ba = 0;
2789 ia = current_pc;
2790 bt = ia;
2792 a0_was_saved = 0;
2793 a7_was_saved = 0;
2794 a11_was_saved = 0;
2796 while (insn_num++ < XTENSA_MAX_WINDOW_INTERRUPT_HANDLER_LEN)
2798 if (ia + xtensa_isa_maxlength (isa) > bt)
2800 ba = ia;
2801 bt = (ba + XTENSA_ISA_BSZ);
2802 if (target_read_memory (ba, ibuf, bt - ba) != 0)
2803 return xtNoExceptionHandler;
2805 xtensa_insnbuf_from_chars (isa, ins, &ibuf[ia-ba], 0);
2806 ifmt = xtensa_format_decode (isa, ins);
2807 if (ifmt == XTENSA_UNDEFINED)
2808 return xtNoExceptionHandler;
2809 ilen = xtensa_format_length (isa, ifmt);
2810 if (ilen == XTENSA_UNDEFINED)
2811 return xtNoExceptionHandler;
2812 islots = xtensa_format_num_slots (isa, ifmt);
2813 if (islots == XTENSA_UNDEFINED)
2814 return xtNoExceptionHandler;
2815 for (is = 0; is < islots; ++is)
2817 if (xtensa_format_get_slot (isa, ifmt, is, ins, slot))
2818 return xtNoExceptionHandler;
2819 opc = xtensa_opcode_decode (isa, ifmt, is, slot);
2820 if (opc == XTENSA_UNDEFINED)
2821 return xtNoExceptionHandler;
2822 switch (call0_classify_opcode (isa, opc))
2824 case c0opc_illegal:
2825 case c0opc_flow:
2826 case c0opc_entry:
2827 case c0opc_break:
2828 /* We expect none of them here. */
2829 return xtNoExceptionHandler;
2830 case c0opc_l32e:
2831 func = execute_l32e;
2832 break;
2833 case c0opc_s32e:
2834 func = execute_s32e;
2835 break;
2836 case c0opc_rfwo: /* RFWO. */
2837 /* Here, we return from WindowOverflow handler and,
2838 if we stopped at the very beginning, which means
2839 A0 was saved, we have to restore it now. */
2840 if (a0_was_saved)
2842 int arreg = arreg_number (gdbarch,
2843 tdep->a0_base,
2844 wb);
2845 xtensa_write_register (arreg, a0_saved);
2847 return xtWindowOverflow;
2848 case c0opc_rfwu: /* RFWU. */
2849 /* Here, we return from WindowUnderflow handler.
2850 Let's see if either A7 or A11 has to be restored. */
2851 if (WindowUnderflow12)
2853 if (a11_was_saved)
2855 int arreg = arreg_number (gdbarch,
2856 tdep->a0_base + 11,
2857 wb);
2858 xtensa_write_register (arreg, a11_saved);
2861 else if (a7_was_saved)
2863 int arreg = arreg_number (gdbarch,
2864 tdep->a0_base + 7,
2865 wb);
2866 xtensa_write_register (arreg, a7_saved);
2868 return xtWindowUnderflow;
2869 default: /* Simply skip this insns. */
2870 continue;
2873 /* Decode arguments for L32E / S32E and simulate their execution. */
2874 if ( xtensa_opcode_num_operands (isa, opc) != 3 )
2875 return xtNoExceptionHandler;
2876 if (xtensa_operand_get_field (isa, opc, 0, ifmt, is, slot, &at))
2877 return xtNoExceptionHandler;
2878 if (xtensa_operand_decode (isa, opc, 0, &at))
2879 return xtNoExceptionHandler;
2880 if (xtensa_operand_get_field (isa, opc, 1, ifmt, is, slot, &as))
2881 return xtNoExceptionHandler;
2882 if (xtensa_operand_decode (isa, opc, 1, &as))
2883 return xtNoExceptionHandler;
2884 if (xtensa_operand_get_field (isa, opc, 2, ifmt, is, slot, &offset))
2885 return xtNoExceptionHandler;
2886 if (xtensa_operand_decode (isa, opc, 2, &offset))
2887 return xtNoExceptionHandler;
2889 (*func) (gdbarch, at, as, offset, wb);
2892 ia += ilen;
2894 return xtNoExceptionHandler;
2897 /* Handle Window Overflow / Underflow exception frames. */
2899 static void
2900 xtensa_window_interrupt_frame_cache (struct frame_info *this_frame,
2901 xtensa_frame_cache_t *cache,
2902 CORE_ADDR pc)
2904 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2905 CORE_ADDR ps, wb, ws, ra;
2906 int epc1_regnum, i, regnum;
2907 xtensa_exception_handler_t eh_type;
2908 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
2910 /* Read PS, WB, and WS from the hardware. Note that PS register
2911 must be present, if Windowed ABI is supported. */
2912 ps = xtensa_read_register (gdbarch_ps_regnum (gdbarch));
2913 wb = xtensa_read_register (tdep->wb_regnum);
2914 ws = xtensa_read_register (tdep->ws_regnum);
2916 /* Execute all the remaining instructions from Window Interrupt Handler
2917 by simulating them on the remote protocol level. On return, set the
2918 type of Xtensa Window Interrupt Handler, or report an error. */
2919 eh_type = execute_code (gdbarch, pc, wb);
2920 if (eh_type == xtNoExceptionHandler)
2921 error (_("\
2922 Unable to decode Xtensa Window Interrupt Handler's code."));
2924 cache->ps = ps ^ PS_EXC; /* Clear the exception bit in PS. */
2925 cache->call0 = 0; /* It's Windowed ABI. */
2927 /* All registers for the cached frame will be alive. */
2928 for (i = 0; i < XTENSA_NUM_SAVED_AREGS; i++)
2929 cache->wd.aregs[i] = -1;
2931 if (eh_type == xtWindowOverflow)
2932 cache->wd.ws = ws ^ (1 << wb);
2933 else /* eh_type == xtWindowUnderflow. */
2934 cache->wd.ws = ws | (1 << wb);
2936 cache->wd.wb = (ps & 0xf00) >> 8; /* Set WB to OWB. */
2937 regnum = arreg_number (gdbarch, tdep->a0_base,
2938 cache->wd.wb);
2939 ra = xtensa_read_register (regnum);
2940 cache->wd.callsize = WINSIZE (ra);
2941 cache->prev_sp = xtensa_read_register (regnum + 1);
2942 /* Set regnum to a frame pointer of the frame being cached. */
2943 regnum = xtensa_scan_prologue (gdbarch, pc);
2944 regnum = arreg_number (gdbarch,
2945 tdep->a0_base + regnum,
2946 cache->wd.wb);
2947 cache->base = get_frame_register_unsigned (this_frame, regnum);
2949 /* Read PC of interrupted function from EPC1 register. */
2950 epc1_regnum = xtensa_find_register_by_name (gdbarch,"epc1");
2951 if (epc1_regnum < 0)
2952 error(_("Unable to read Xtensa register EPC1"));
2953 cache->ra = xtensa_read_register (epc1_regnum);
2954 cache->pc = get_frame_func (this_frame);
2958 /* Skip function prologue.
2960 Return the pc of the first instruction after prologue. GDB calls this to
2961 find the address of the first line of the function or (if there is no line
2962 number information) to skip the prologue for planting breakpoints on
2963 function entries. Use debug info (if present) or prologue analysis to skip
2964 the prologue to achieve reliable debugging behavior. For windowed ABI,
2965 only the 'entry' instruction is skipped. It is not strictly necessary to
2966 skip the prologue (Call0) or 'entry' (Windowed) because xt-gdb knows how to
2967 backtrace at any point in the prologue, however certain potential hazards
2968 are avoided and a more "normal" debugging experience is ensured by
2969 skipping the prologue (can be disabled by defining DONT_SKIP_PROLOG).
2970 For example, if we don't skip the prologue:
2971 - Some args may not yet have been saved to the stack where the debug
2972 info expects to find them (true anyway when only 'entry' is skipped);
2973 - Software breakpoints ('break' instrs) may not have been unplanted
2974 when the prologue analysis is done on initializing the frame cache,
2975 and breaks in the prologue will throw off the analysis.
2977 If we have debug info ( line-number info, in particular ) we simply skip
2978 the code associated with the first function line effectively skipping
2979 the prologue code. It works even in cases like
2981 int main()
2982 { int local_var = 1;
2983 ....
2986 because, for this source code, both Xtensa compilers will generate two
2987 separate entries ( with the same line number ) in dwarf line-number
2988 section to make sure there is a boundary between the prologue code and
2989 the rest of the function.
2991 If there is no debug info, we need to analyze the code. */
2993 /* #define DONT_SKIP_PROLOGUE */
2995 static CORE_ADDR
2996 xtensa_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR start_pc)
2998 struct symtab_and_line prologue_sal;
2999 CORE_ADDR body_pc;
3001 DEBUGTRACE ("xtensa_skip_prologue (start_pc = 0x%08x)\n", (int) start_pc);
3003 #if DONT_SKIP_PROLOGUE
3004 return start_pc;
3005 #endif
3007 /* Try to find first body line from debug info. */
3009 prologue_sal = find_pc_line (start_pc, 0);
3010 if (prologue_sal.line != 0) /* Found debug info. */
3012 /* In Call0, it is possible to have a function with only one instruction
3013 ('ret') resulting from a one-line optimized function that does nothing.
3014 In that case, prologue_sal.end may actually point to the start of the
3015 next function in the text section, causing a breakpoint to be set at
3016 the wrong place. Check, if the end address is within a different
3017 function, and if so return the start PC. We know we have symbol
3018 information. */
3020 CORE_ADDR end_func;
3022 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
3023 if ((tdep->call_abi == CallAbiCall0Only)
3024 && call0_ret (start_pc, prologue_sal.end))
3025 return start_pc;
3027 find_pc_partial_function (prologue_sal.end, NULL, &end_func, NULL);
3028 if (end_func != start_pc)
3029 return start_pc;
3031 return prologue_sal.end;
3034 /* No debug line info. Analyze prologue for Call0 or simply skip ENTRY. */
3035 body_pc = call0_analyze_prologue (gdbarch, start_pc, 0, 0,
3036 xtensa_alloc_frame_cache (0));
3037 return body_pc != 0 ? body_pc : start_pc;
3040 /* Verify the current configuration. */
3041 static void
3042 xtensa_verify_config (struct gdbarch *gdbarch)
3044 xtensa_gdbarch_tdep *tdep = gdbarch_tdep<xtensa_gdbarch_tdep> (gdbarch);
3045 string_file log;
3047 /* Verify that we got a reasonable number of AREGS. */
3048 if ((tdep->num_aregs & -tdep->num_aregs) != tdep->num_aregs)
3049 log.printf (_("\
3050 \n\tnum_aregs: Number of AR registers (%d) is not a power of two!"),
3051 tdep->num_aregs);
3053 /* Verify that certain registers exist. */
3055 if (tdep->pc_regnum == -1)
3056 log.printf (_("\n\tpc_regnum: No PC register"));
3057 if (tdep->isa_use_exceptions && tdep->ps_regnum == -1)
3058 log.printf (_("\n\tps_regnum: No PS register"));
3060 if (tdep->isa_use_windowed_registers)
3062 if (tdep->wb_regnum == -1)
3063 log.printf (_("\n\twb_regnum: No WB register"));
3064 if (tdep->ws_regnum == -1)
3065 log.printf (_("\n\tws_regnum: No WS register"));
3066 if (tdep->ar_base == -1)
3067 log.printf (_("\n\tar_base: No AR registers"));
3070 if (tdep->a0_base == -1)
3071 log.printf (_("\n\ta0_base: No Ax registers"));
3073 if (!log.empty ())
3074 internal_error (__FILE__, __LINE__,
3075 _("the following are invalid: %s"), log.c_str ());
3079 /* Derive specific register numbers from the array of registers. */
3081 static void
3082 xtensa_derive_tdep (xtensa_gdbarch_tdep *tdep)
3084 xtensa_register_t* rmap;
3085 int n, max_size = 4;
3087 tdep->num_regs = 0;
3088 tdep->num_nopriv_regs = 0;
3090 /* Special registers 0..255 (core). */
3091 #define XTENSA_DBREGN_SREG(n) (0x0200+(n))
3092 /* User registers 0..255. */
3093 #define XTENSA_DBREGN_UREG(n) (0x0300+(n))
3095 for (rmap = tdep->regmap, n = 0; rmap->target_number != -1; n++, rmap++)
3097 if (rmap->target_number == 0x0020)
3098 tdep->pc_regnum = n;
3099 else if (rmap->target_number == 0x0100)
3100 tdep->ar_base = n;
3101 else if (rmap->target_number == 0x0000)
3102 tdep->a0_base = n;
3103 else if (rmap->target_number == XTENSA_DBREGN_SREG(72))
3104 tdep->wb_regnum = n;
3105 else if (rmap->target_number == XTENSA_DBREGN_SREG(73))
3106 tdep->ws_regnum = n;
3107 else if (rmap->target_number == XTENSA_DBREGN_SREG(233))
3108 tdep->debugcause_regnum = n;
3109 else if (rmap->target_number == XTENSA_DBREGN_SREG(232))
3110 tdep->exccause_regnum = n;
3111 else if (rmap->target_number == XTENSA_DBREGN_SREG(238))
3112 tdep->excvaddr_regnum = n;
3113 else if (rmap->target_number == XTENSA_DBREGN_SREG(0))
3114 tdep->lbeg_regnum = n;
3115 else if (rmap->target_number == XTENSA_DBREGN_SREG(1))
3116 tdep->lend_regnum = n;
3117 else if (rmap->target_number == XTENSA_DBREGN_SREG(2))
3118 tdep->lcount_regnum = n;
3119 else if (rmap->target_number == XTENSA_DBREGN_SREG(3))
3120 tdep->sar_regnum = n;
3121 else if (rmap->target_number == XTENSA_DBREGN_SREG(5))
3122 tdep->litbase_regnum = n;
3123 else if (rmap->target_number == XTENSA_DBREGN_SREG(230))
3124 tdep->ps_regnum = n;
3125 else if (rmap->target_number == XTENSA_DBREGN_UREG(231))
3126 tdep->threadptr_regnum = n;
3127 #if 0
3128 else if (rmap->target_number == XTENSA_DBREGN_SREG(226))
3129 tdep->interrupt_regnum = n;
3130 else if (rmap->target_number == XTENSA_DBREGN_SREG(227))
3131 tdep->interrupt2_regnum = n;
3132 else if (rmap->target_number == XTENSA_DBREGN_SREG(224))
3133 tdep->cpenable_regnum = n;
3134 #endif
3136 if (rmap->byte_size > max_size)
3137 max_size = rmap->byte_size;
3138 if (rmap->mask != 0 && tdep->num_regs == 0)
3139 tdep->num_regs = n;
3140 if ((rmap->flags & XTENSA_REGISTER_FLAGS_PRIVILEGED) != 0
3141 && tdep->num_nopriv_regs == 0)
3142 tdep->num_nopriv_regs = n;
3144 if (tdep->num_regs == 0)
3145 tdep->num_regs = tdep->num_nopriv_regs;
3147 /* Number of pseudo registers. */
3148 tdep->num_pseudo_regs = n - tdep->num_regs;
3150 /* Empirically determined maximum sizes. */
3151 tdep->max_register_raw_size = max_size;
3152 tdep->max_register_virtual_size = max_size;
3155 /* Module "constructor" function. */
3157 extern xtensa_gdbarch_tdep xtensa_tdep;
3159 static struct gdbarch *
3160 xtensa_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
3162 struct gdbarch *gdbarch;
3164 DEBUGTRACE ("gdbarch_init()\n");
3166 if (!xtensa_default_isa)
3167 xtensa_default_isa = xtensa_isa_init (0, 0);
3169 /* We have to set the byte order before we call gdbarch_alloc. */
3170 info.byte_order = XCHAL_HAVE_BE ? BFD_ENDIAN_BIG : BFD_ENDIAN_LITTLE;
3172 xtensa_gdbarch_tdep *tdep = &xtensa_tdep;
3173 gdbarch = gdbarch_alloc (&info, tdep);
3174 xtensa_derive_tdep (tdep);
3176 /* Verify our configuration. */
3177 xtensa_verify_config (gdbarch);
3178 xtensa_session_once_reported = 0;
3180 set_gdbarch_wchar_bit (gdbarch, 2 * TARGET_CHAR_BIT);
3181 set_gdbarch_wchar_signed (gdbarch, 0);
3183 /* Pseudo-Register read/write. */
3184 set_gdbarch_pseudo_register_read (gdbarch, xtensa_pseudo_register_read);
3185 set_gdbarch_pseudo_register_write (gdbarch, xtensa_pseudo_register_write);
3187 /* Set target information. */
3188 set_gdbarch_num_regs (gdbarch, tdep->num_regs);
3189 set_gdbarch_num_pseudo_regs (gdbarch, tdep->num_pseudo_regs);
3190 set_gdbarch_sp_regnum (gdbarch, tdep->a0_base + 1);
3191 set_gdbarch_pc_regnum (gdbarch, tdep->pc_regnum);
3192 set_gdbarch_ps_regnum (gdbarch, tdep->ps_regnum);
3194 /* Renumber registers for known formats (stabs and dwarf2). */
3195 set_gdbarch_stab_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3196 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, xtensa_reg_to_regnum);
3198 /* We provide our own function to get register information. */
3199 set_gdbarch_register_name (gdbarch, xtensa_register_name);
3200 set_gdbarch_register_type (gdbarch, xtensa_register_type);
3202 /* To call functions from GDB using dummy frame. */
3203 set_gdbarch_push_dummy_call (gdbarch, xtensa_push_dummy_call);
3205 set_gdbarch_believe_pcc_promotion (gdbarch, 1);
3207 set_gdbarch_return_value (gdbarch, xtensa_return_value);
3209 /* Advance PC across any prologue instructions to reach "real" code. */
3210 set_gdbarch_skip_prologue (gdbarch, xtensa_skip_prologue);
3212 /* Stack grows downward. */
3213 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
3215 /* Set breakpoints. */
3216 set_gdbarch_breakpoint_kind_from_pc (gdbarch,
3217 xtensa_breakpoint_kind_from_pc);
3218 set_gdbarch_sw_breakpoint_from_kind (gdbarch,
3219 xtensa_sw_breakpoint_from_kind);
3221 /* After breakpoint instruction or illegal instruction, pc still
3222 points at break instruction, so don't decrement. */
3223 set_gdbarch_decr_pc_after_break (gdbarch, 0);
3225 /* We don't skip args. */
3226 set_gdbarch_frame_args_skip (gdbarch, 0);
3228 set_gdbarch_unwind_pc (gdbarch, xtensa_unwind_pc);
3230 set_gdbarch_frame_align (gdbarch, xtensa_frame_align);
3232 set_gdbarch_dummy_id (gdbarch, xtensa_dummy_id);
3234 /* Frame handling. */
3235 frame_base_set_default (gdbarch, &xtensa_frame_base);
3236 frame_unwind_append_unwinder (gdbarch, &xtensa_unwind);
3237 dwarf2_append_unwinders (gdbarch);
3239 set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
3241 xtensa_add_reggroups (gdbarch);
3242 set_gdbarch_register_reggroup_p (gdbarch, xtensa_register_reggroup_p);
3244 set_gdbarch_iterate_over_regset_sections
3245 (gdbarch, xtensa_iterate_over_regset_sections);
3247 set_solib_svr4_fetch_link_map_offsets
3248 (gdbarch, svr4_ilp32_fetch_link_map_offsets);
3250 /* Hook in the ABI-specific overrides, if they have been registered. */
3251 gdbarch_init_osabi (info, gdbarch);
3253 return gdbarch;
3256 static void
3257 xtensa_dump_tdep (struct gdbarch *gdbarch, struct ui_file *file)
3259 error (_("xtensa_dump_tdep(): not implemented"));
3262 void _initialize_xtensa_tdep ();
3263 void
3264 _initialize_xtensa_tdep ()
3266 gdbarch_register (bfd_arch_xtensa, xtensa_gdbarch_init, xtensa_dump_tdep);
3267 xtensa_init_reggroups ();
3269 add_setshow_zuinteger_cmd ("xtensa",
3270 class_maintenance,
3271 &xtensa_debug_level,
3272 _("Set Xtensa debugging."),
3273 _("Show Xtensa debugging."), _("\
3274 When non-zero, Xtensa-specific debugging is enabled. \
3275 Can be 1, 2, 3, or 4 indicating the level of debugging."),
3276 NULL,
3277 NULL,
3278 &setdebuglist, &showdebuglist);