| blob | d441f364a04243e317ee2261b91f4b43b2423602 |
1 // i386 register table.
2 // Copyright (C) 2007-2024 Free Software Foundation, Inc.
3 //
4 // This file is part of the GNU opcodes library.
5 //
6 // This library is free software; you can redistribute it and/or modify
7 // it under the terms of the GNU General Public License as published by
8 // the Free Software Foundation; either version 3, or (at your option)
9 // any later version.
10 //
11 // It is distributed in the hope that it will be useful, but WITHOUT
12 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
13 // or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
14 // License for more details.
15 //
16 // You should have received a copy of the GNU General Public License
17 // along with GAS; see the file COPYING. If not, write to the Free
18 // Software Foundation, 51 Franklin Street - Fifth Floor, Boston, MA
19 // 02110-1301, USA.
21 // The code in gas backend for SCFI relies on the relative ordering
22 // of 8 bit / 16 bit / 32 bit / 64 bit regs
24 // 8 bit regs
25 al, Class=Reg|Instance=Accum|Byte, 0, 0, Dw2Inval, Dw2Inval
26 cl, Class=Reg|Instance=RegC|Byte, 0, 1, Dw2Inval, Dw2Inval
27 dl, Class=Reg|Byte, 0, 2, Dw2Inval, Dw2Inval
28 bl, Class=Reg|Byte, 0, 3, Dw2Inval, Dw2Inval
29 ah, Class=Reg|Byte, 0, 4, Dw2Inval, Dw2Inval
30 ch, Class=Reg|Byte, 0, 5, Dw2Inval, Dw2Inval
31 dh, Class=Reg|Byte, 0, 6, Dw2Inval, Dw2Inval
32 bh, Class=Reg|Byte, 0, 7, Dw2Inval, Dw2Inval
33 axl, Class=Reg|Byte, RegRex64, 0, Dw2Inval, Dw2Inval
34 cxl, Class=Reg|Byte, RegRex64, 1, Dw2Inval, Dw2Inval
35 dxl, Class=Reg|Byte, RegRex64, 2, Dw2Inval, Dw2Inval
36 bxl, Class=Reg|Byte, RegRex64, 3, Dw2Inval, Dw2Inval
37 spl, Class=Reg|Byte, RegRex64, 4, Dw2Inval, Dw2Inval
38 bpl, Class=Reg|Byte, RegRex64, 5, Dw2Inval, Dw2Inval
39 sil, Class=Reg|Byte, RegRex64, 6, Dw2Inval, Dw2Inval
40 dil, Class=Reg|Byte, RegRex64, 7, Dw2Inval, Dw2Inval
41 r8b, Class=Reg|Byte, RegRex|RegRex64, 0, Dw2Inval, Dw2Inval
42 r9b, Class=Reg|Byte, RegRex|RegRex64, 1, Dw2Inval, Dw2Inval
43 r10b, Class=Reg|Byte, RegRex|RegRex64, 2, Dw2Inval, Dw2Inval
44 r11b, Class=Reg|Byte, RegRex|RegRex64, 3, Dw2Inval, Dw2Inval
45 r12b, Class=Reg|Byte, RegRex|RegRex64, 4, Dw2Inval, Dw2Inval
46 r13b, Class=Reg|Byte, RegRex|RegRex64, 5, Dw2Inval, Dw2Inval
47 r14b, Class=Reg|Byte, RegRex|RegRex64, 6, Dw2Inval, Dw2Inval
48 r15b, Class=Reg|Byte, RegRex|RegRex64, 7, Dw2Inval, Dw2Inval
49 r16b, Class=Reg|Byte, RegRex2|RegRex64, 0, Dw2Inval, Dw2Inval
50 r17b, Class=Reg|Byte, RegRex2|RegRex64, 1, Dw2Inval, Dw2Inval
51 r18b, Class=Reg|Byte, RegRex2|RegRex64, 2, Dw2Inval, Dw2Inval
52 r19b, Class=Reg|Byte, RegRex2|RegRex64, 3, Dw2Inval, Dw2Inval
53 r20b, Class=Reg|Byte, RegRex2|RegRex64, 4, Dw2Inval, Dw2Inval
54 r21b, Class=Reg|Byte, RegRex2|RegRex64, 5, Dw2Inval, Dw2Inval
55 r22b, Class=Reg|Byte, RegRex2|RegRex64, 6, Dw2Inval, Dw2Inval
56 r23b, Class=Reg|Byte, RegRex2|RegRex64, 7, Dw2Inval, Dw2Inval
57 r24b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 0, Dw2Inval, Dw2Inval
58 r25b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 1, Dw2Inval, Dw2Inval
59 r26b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 2, Dw2Inval, Dw2Inval
60 r27b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 3, Dw2Inval, Dw2Inval
61 r28b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 4, Dw2Inval, Dw2Inval
62 r29b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 5, Dw2Inval, Dw2Inval
63 r30b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 6, Dw2Inval, Dw2Inval
64 r31b, Class=Reg|Byte, RegRex2|RegRex64|RegRex, 7, Dw2Inval, Dw2Inval
65 // 16 bit regs
66 ax, Class=Reg|Instance=Accum|Word, 0, 0, Dw2Inval, Dw2Inval
67 cx, Class=Reg|Word, 0, 1, Dw2Inval, Dw2Inval
68 dx, Class=Reg|Instance=RegD|Word, 0, 2, Dw2Inval, Dw2Inval
69 bx, Class=Reg|Word|BaseIndex, 0, 3, Dw2Inval, Dw2Inval
70 sp, Class=Reg|Word, 0, 4, Dw2Inval, Dw2Inval
71 bp, Class=Reg|Word|BaseIndex, 0, 5, Dw2Inval, Dw2Inval
72 si, Class=Reg|Word|BaseIndex, 0, 6, Dw2Inval, Dw2Inval
73 di, Class=Reg|Word|BaseIndex, 0, 7, Dw2Inval, Dw2Inval
74 r8w, Class=Reg|Word, RegRex, 0, Dw2Inval, Dw2Inval
75 r9w, Class=Reg|Word, RegRex, 1, Dw2Inval, Dw2Inval
76 r10w, Class=Reg|Word, RegRex, 2, Dw2Inval, Dw2Inval
77 r11w, Class=Reg|Word, RegRex, 3, Dw2Inval, Dw2Inval
78 r12w, Class=Reg|Word, RegRex, 4, Dw2Inval, Dw2Inval
79 r13w, Class=Reg|Word, RegRex, 5, Dw2Inval, Dw2Inval
80 r14w, Class=Reg|Word, RegRex, 6, Dw2Inval, Dw2Inval
81 r15w, Class=Reg|Word, RegRex, 7, Dw2Inval, Dw2Inval
82 r16w, Class=Reg|Word, RegRex2, 0, Dw2Inval, Dw2Inval
83 r17w, Class=Reg|Word, RegRex2, 1, Dw2Inval, Dw2Inval
84 r18w, Class=Reg|Word, RegRex2, 2, Dw2Inval, Dw2Inval
85 r19w, Class=Reg|Word, RegRex2, 3, Dw2Inval, Dw2Inval
86 r20w, Class=Reg|Word, RegRex2, 4, Dw2Inval, Dw2Inval
87 r21w, Class=Reg|Word, RegRex2, 5, Dw2Inval, Dw2Inval
88 r22w, Class=Reg|Word, RegRex2, 6, Dw2Inval, Dw2Inval
89 r23w, Class=Reg|Word, RegRex2, 7, Dw2Inval, Dw2Inval
90 r24w, Class=Reg|Word, RegRex2|RegRex, 0, Dw2Inval, Dw2Inval
91 r25w, Class=Reg|Word, RegRex2|RegRex, 1, Dw2Inval, Dw2Inval
92 r26w, Class=Reg|Word, RegRex2|RegRex, 2, Dw2Inval, Dw2Inval
93 r27w, Class=Reg|Word, RegRex2|RegRex, 3, Dw2Inval, Dw2Inval
94 r28w, Class=Reg|Word, RegRex2|RegRex, 4, Dw2Inval, Dw2Inval
95 r29w, Class=Reg|Word, RegRex2|RegRex, 5, Dw2Inval, Dw2Inval
96 r30w, Class=Reg|Word, RegRex2|RegRex, 6, Dw2Inval, Dw2Inval
97 r31w, Class=Reg|Word, RegRex2|RegRex, 7, Dw2Inval, Dw2Inval
98 // 32 bit regs
99 eax, Class=Reg|Instance=Accum|Dword|BaseIndex, 0, 0, 0, Dw2Inval
100 ecx, Class=Reg|Instance=RegC|Dword|BaseIndex, 0, 1, 1, Dw2Inval
101 edx, Class=Reg|Instance=RegD|Dword|BaseIndex, 0, 2, 2, Dw2Inval
102 ebx, Class=Reg|Instance=RegB|Dword|BaseIndex, 0, 3, 3, Dw2Inval
103 esp, Class=Reg|Dword, 0, 4, 4, Dw2Inval
104 ebp, Class=Reg|Dword|BaseIndex, 0, 5, 5, Dw2Inval
105 esi, Class=Reg|Dword|BaseIndex, 0, 6, 6, Dw2Inval
106 edi, Class=Reg|Dword|BaseIndex, 0, 7, 7, Dw2Inval
107 r8d, Class=Reg|Dword|BaseIndex, RegRex, 0, Dw2Inval, Dw2Inval
108 r9d, Class=Reg|Dword|BaseIndex, RegRex, 1, Dw2Inval, Dw2Inval
109 r10d, Class=Reg|Dword|BaseIndex, RegRex, 2, Dw2Inval, Dw2Inval
110 r11d, Class=Reg|Dword|BaseIndex, RegRex, 3, Dw2Inval, Dw2Inval
111 r12d, Class=Reg|Dword|BaseIndex, RegRex, 4, Dw2Inval, Dw2Inval
112 r13d, Class=Reg|Dword|BaseIndex, RegRex, 5, Dw2Inval, Dw2Inval
113 r14d, Class=Reg|Dword|BaseIndex, RegRex, 6, Dw2Inval, Dw2Inval
114 r15d, Class=Reg|Dword|BaseIndex, RegRex, 7, Dw2Inval, Dw2Inval
115 r16d, Class=Reg|Dword|BaseIndex, RegRex2, 0, Dw2Inval, Dw2Inval
116 r17d, Class=Reg|Dword|BaseIndex, RegRex2, 1, Dw2Inval, Dw2Inval
117 r18d, Class=Reg|Dword|BaseIndex, RegRex2, 2, Dw2Inval, Dw2Inval
118 r19d, Class=Reg|Dword|BaseIndex, RegRex2, 3, Dw2Inval, Dw2Inval
119 r20d, Class=Reg|Dword|BaseIndex, RegRex2, 4, Dw2Inval, Dw2Inval
120 r21d, Class=Reg|Dword|BaseIndex, RegRex2, 5, Dw2Inval, Dw2Inval
121 r22d, Class=Reg|Dword|BaseIndex, RegRex2, 6, Dw2Inval, Dw2Inval
122 r23d, Class=Reg|Dword|BaseIndex, RegRex2, 7, Dw2Inval, Dw2Inval
123 r24d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 0, Dw2Inval, Dw2Inval
124 r25d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 1, Dw2Inval, Dw2Inval
125 r26d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 2, Dw2Inval, Dw2Inval
126 r27d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 3, Dw2Inval, Dw2Inval
127 r28d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 4, Dw2Inval, Dw2Inval
128 r29d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 5, Dw2Inval, Dw2Inval
129 r30d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 6, Dw2Inval, Dw2Inval
130 r31d, Class=Reg|Dword|BaseIndex, RegRex2|RegRex, 7, Dw2Inval, Dw2Inval
131 rax, Class=Reg|Instance=Accum|Qword|BaseIndex, 0, 0, Dw2Inval, 0
132 rcx, Class=Reg|Instance=RegC|Qword|BaseIndex, 0, 1, Dw2Inval, 2
133 rdx, Class=Reg|Instance=RegD|Qword|BaseIndex, 0, 2, Dw2Inval, 1
134 rbx, Class=Reg|Instance=RegB|Qword|BaseIndex, 0, 3, Dw2Inval, 3
135 rsp, Class=Reg|Qword, 0, 4, Dw2Inval, 7
136 rbp, Class=Reg|Qword|BaseIndex, 0, 5, Dw2Inval, 6
137 rsi, Class=Reg|Qword|BaseIndex, 0, 6, Dw2Inval, 4
138 rdi, Class=Reg|Qword|BaseIndex, 0, 7, Dw2Inval, 5
139 r8, Class=Reg|Qword|BaseIndex, RegRex, 0, Dw2Inval, 8
140 r9, Class=Reg|Qword|BaseIndex, RegRex, 1, Dw2Inval, 9
141 r10, Class=Reg|Qword|BaseIndex, RegRex, 2, Dw2Inval, 10
142 r11, Class=Reg|Qword|BaseIndex, RegRex, 3, Dw2Inval, 11
143 r12, Class=Reg|Qword|BaseIndex, RegRex, 4, Dw2Inval, 12
144 r13, Class=Reg|Qword|BaseIndex, RegRex, 5, Dw2Inval, 13
145 r14, Class=Reg|Qword|BaseIndex, RegRex, 6, Dw2Inval, 14
146 r15, Class=Reg|Qword|BaseIndex, RegRex, 7, Dw2Inval, 15
147 r16, Class=Reg|Qword|BaseIndex, RegRex2, 0, Dw2Inval, 130
148 r17, Class=Reg|Qword|BaseIndex, RegRex2, 1, Dw2Inval, 131
149 r18, Class=Reg|Qword|BaseIndex, RegRex2, 2, Dw2Inval, 132
150 r19, Class=Reg|Qword|BaseIndex, RegRex2, 3, Dw2Inval, 133
151 r20, Class=Reg|Qword|BaseIndex, RegRex2, 4, Dw2Inval, 134
152 r21, Class=Reg|Qword|BaseIndex, RegRex2, 5, Dw2Inval, 135
153 r22, Class=Reg|Qword|BaseIndex, RegRex2, 6, Dw2Inval, 136
154 r23, Class=Reg|Qword|BaseIndex, RegRex2, 7, Dw2Inval, 137
155 r24, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 0, Dw2Inval, 138
156 r25, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 1, Dw2Inval, 139
157 r26, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 2, Dw2Inval, 140
158 r27, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 3, Dw2Inval, 141
159 r28, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 4, Dw2Inval, 142
160 r29, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 5, Dw2Inval, 143
161 r30, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 6, Dw2Inval, 144
162 r31, Class=Reg|Qword|BaseIndex, RegRex2|RegRex, 7, Dw2Inval, 145
163 // Vector mask registers.
164 k0, Class=RegMask, 0, 0, 93, 118
165 k1, Class=RegMask, 0, 1, 94, 119
166 k2, Class=RegMask, 0, 2, 95, 120
167 k3, Class=RegMask, 0, 3, 96, 121
168 k4, Class=RegMask, 0, 4, 97, 122
169 k5, Class=RegMask, 0, 5, 98, 123
170 k6, Class=RegMask, 0, 6, 99, 124
171 k7, Class=RegMask, 0, 7, 100, 125
172 // Segment registers.
173 es, Class=SReg, 0, 0, 40, 50
174 cs, Class=SReg, 0, 1, 41, 51
175 ss, Class=SReg, 0, 2, 42, 52
176 ds, Class=SReg, 0, 3, 43, 53
177 fs, Class=SReg, 0, 4, 44, 54
178 gs, Class=SReg, 0, 5, 45, 55
179 flat, Class=SReg, 0, RegFlat, Dw2Inval, Dw2Inval
180 // Control registers.
181 cr0, Class=RegCR, 0, 0, Dw2Inval, Dw2Inval
182 cr1, Class=RegCR, 0, 1, Dw2Inval, Dw2Inval
183 cr2, Class=RegCR, 0, 2, Dw2Inval, Dw2Inval
184 cr3, Class=RegCR, 0, 3, Dw2Inval, Dw2Inval
185 cr4, Class=RegCR, 0, 4, Dw2Inval, Dw2Inval
186 cr5, Class=RegCR, 0, 5, Dw2Inval, Dw2Inval
187 cr6, Class=RegCR, 0, 6, Dw2Inval, Dw2Inval
188 cr7, Class=RegCR, 0, 7, Dw2Inval, Dw2Inval
189 cr8, Class=RegCR, RegRex, 0, Dw2Inval, Dw2Inval
190 cr9, Class=RegCR, RegRex, 1, Dw2Inval, Dw2Inval
191 cr10, Class=RegCR, RegRex, 2, Dw2Inval, Dw2Inval
192 cr11, Class=RegCR, RegRex, 3, Dw2Inval, Dw2Inval
193 cr12, Class=RegCR, RegRex, 4, Dw2Inval, Dw2Inval
194 cr13, Class=RegCR, RegRex, 5, Dw2Inval, Dw2Inval
195 cr14, Class=RegCR, RegRex, 6, Dw2Inval, Dw2Inval
196 cr15, Class=RegCR, RegRex, 7, Dw2Inval, Dw2Inval
197 // Debug registers.
198 db0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
199 db1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
200 db2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
201 db3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
202 db4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
203 db5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
204 db6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
205 db7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
206 db8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
207 db9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
208 db10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
209 db11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
210 db12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
211 db13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
212 db14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
213 db15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
214 dr0, Class=RegDR, 0, 0, Dw2Inval, Dw2Inval
215 dr1, Class=RegDR, 0, 1, Dw2Inval, Dw2Inval
216 dr2, Class=RegDR, 0, 2, Dw2Inval, Dw2Inval
217 dr3, Class=RegDR, 0, 3, Dw2Inval, Dw2Inval
218 dr4, Class=RegDR, 0, 4, Dw2Inval, Dw2Inval
219 dr5, Class=RegDR, 0, 5, Dw2Inval, Dw2Inval
220 dr6, Class=RegDR, 0, 6, Dw2Inval, Dw2Inval
221 dr7, Class=RegDR, 0, 7, Dw2Inval, Dw2Inval
222 dr8, Class=RegDR, RegRex, 0, Dw2Inval, Dw2Inval
223 dr9, Class=RegDR, RegRex, 1, Dw2Inval, Dw2Inval
224 dr10, Class=RegDR, RegRex, 2, Dw2Inval, Dw2Inval
225 dr11, Class=RegDR, RegRex, 3, Dw2Inval, Dw2Inval
226 dr12, Class=RegDR, RegRex, 4, Dw2Inval, Dw2Inval
227 dr13, Class=RegDR, RegRex, 5, Dw2Inval, Dw2Inval
228 dr14, Class=RegDR, RegRex, 6, Dw2Inval, Dw2Inval
229 dr15, Class=RegDR, RegRex, 7, Dw2Inval, Dw2Inval
230 // Test registers.
231 tr0, Class=RegTR, 0, 0, Dw2Inval, Dw2Inval
232 tr1, Class=RegTR, 0, 1, Dw2Inval, Dw2Inval
233 tr2, Class=RegTR, 0, 2, Dw2Inval, Dw2Inval
234 tr3, Class=RegTR, 0, 3, Dw2Inval, Dw2Inval
235 tr4, Class=RegTR, 0, 4, Dw2Inval, Dw2Inval
236 tr5, Class=RegTR, 0, 5, Dw2Inval, Dw2Inval
237 tr6, Class=RegTR, 0, 6, Dw2Inval, Dw2Inval
238 tr7, Class=RegTR, 0, 7, Dw2Inval, Dw2Inval
239 // MMX and simd registers.
240 mm0, Class=RegMMX, 0, 0, 29, 41
241 mm1, Class=RegMMX, 0, 1, 30, 42
242 mm2, Class=RegMMX, 0, 2, 31, 43
243 mm3, Class=RegMMX, 0, 3, 32, 44
244 mm4, Class=RegMMX, 0, 4, 33, 45
245 mm5, Class=RegMMX, 0, 5, 34, 46
246 mm6, Class=RegMMX, 0, 6, 35, 47
247 mm7, Class=RegMMX, 0, 7, 36, 48
248 xmm0, Class=RegSIMD|Instance=Accum|Xmmword, 0, 0, 21, 17
249 xmm1, Class=RegSIMD|Xmmword, 0, 1, 22, 18
250 xmm2, Class=RegSIMD|Xmmword, 0, 2, 23, 19
251 xmm3, Class=RegSIMD|Xmmword, 0, 3, 24, 20
252 xmm4, Class=RegSIMD|Xmmword, 0, 4, 25, 21
253 xmm5, Class=RegSIMD|Xmmword, 0, 5, 26, 22
254 xmm6, Class=RegSIMD|Xmmword, 0, 6, 27, 23
255 xmm7, Class=RegSIMD|Xmmword, 0, 7, 28, 24
256 xmm8, Class=RegSIMD|Xmmword, RegRex, 0, Dw2Inval, 25
257 xmm9, Class=RegSIMD|Xmmword, RegRex, 1, Dw2Inval, 26
258 xmm10, Class=RegSIMD|Xmmword, RegRex, 2, Dw2Inval, 27
259 xmm11, Class=RegSIMD|Xmmword, RegRex, 3, Dw2Inval, 28
260 xmm12, Class=RegSIMD|Xmmword, RegRex, 4, Dw2Inval, 29
261 xmm13, Class=RegSIMD|Xmmword, RegRex, 5, Dw2Inval, 30
262 xmm14, Class=RegSIMD|Xmmword, RegRex, 6, Dw2Inval, 31
263 xmm15, Class=RegSIMD|Xmmword, RegRex, 7, Dw2Inval, 32
264 xmm16, Class=RegSIMD|Xmmword, RegVRex, 0, Dw2Inval, 67
265 xmm17, Class=RegSIMD|Xmmword, RegVRex, 1, Dw2Inval, 68
266 xmm18, Class=RegSIMD|Xmmword, RegVRex, 2, Dw2Inval, 69
267 xmm19, Class=RegSIMD|Xmmword, RegVRex, 3, Dw2Inval, 70
268 xmm20, Class=RegSIMD|Xmmword, RegVRex, 4, Dw2Inval, 71
269 xmm21, Class=RegSIMD|Xmmword, RegVRex, 5, Dw2Inval, 72
270 xmm22, Class=RegSIMD|Xmmword, RegVRex, 6, Dw2Inval, 73
271 xmm23, Class=RegSIMD|Xmmword, RegVRex, 7, Dw2Inval, 74
272 xmm24, Class=RegSIMD|Xmmword, RegVRex|RegRex, 0, Dw2Inval, 75
273 xmm25, Class=RegSIMD|Xmmword, RegVRex|RegRex, 1, Dw2Inval, 76
274 xmm26, Class=RegSIMD|Xmmword, RegVRex|RegRex, 2, Dw2Inval, 77
275 xmm27, Class=RegSIMD|Xmmword, RegVRex|RegRex, 3, Dw2Inval, 78
276 xmm28, Class=RegSIMD|Xmmword, RegVRex|RegRex, 4, Dw2Inval, 79
277 xmm29, Class=RegSIMD|Xmmword, RegVRex|RegRex, 5, Dw2Inval, 80
278 xmm30, Class=RegSIMD|Xmmword, RegVRex|RegRex, 6, Dw2Inval, 81
279 xmm31, Class=RegSIMD|Xmmword, RegVRex|RegRex, 7, Dw2Inval, 82
280 // AVX registers.
281 ymm0, Class=RegSIMD|Ymmword, 0, 0, 21, 17
282 ymm1, Class=RegSIMD|Ymmword, 0, 1, 22, 18
283 ymm2, Class=RegSIMD|Ymmword, 0, 2, 23, 19
284 ymm3, Class=RegSIMD|Ymmword, 0, 3, 24, 20
285 ymm4, Class=RegSIMD|Ymmword, 0, 4, 25, 21
286 ymm5, Class=RegSIMD|Ymmword, 0, 5, 26, 22
287 ymm6, Class=RegSIMD|Ymmword, 0, 6, 27, 23
288 ymm7, Class=RegSIMD|Ymmword, 0, 7, 28, 24
289 ymm8, Class=RegSIMD|Ymmword, RegRex, 0, Dw2Inval, 25
290 ymm9, Class=RegSIMD|Ymmword, RegRex, 1, Dw2Inval, 26
291 ymm10, Class=RegSIMD|Ymmword, RegRex, 2, Dw2Inval, 27
292 ymm11, Class=RegSIMD|Ymmword, RegRex, 3, Dw2Inval, 28
293 ymm12, Class=RegSIMD|Ymmword, RegRex, 4, Dw2Inval, 29
294 ymm13, Class=RegSIMD|Ymmword, RegRex, 5, Dw2Inval, 30
295 ymm14, Class=RegSIMD|Ymmword, RegRex, 6, Dw2Inval, 31
296 ymm15, Class=RegSIMD|Ymmword, RegRex, 7, Dw2Inval, 32
297 // AVX512 / AVX10 registers.
298 ymm16, Class=RegSIMD|Ymmword, RegVRex, 0, Dw2Inval, 67
299 ymm17, Class=RegSIMD|Ymmword, RegVRex, 1, Dw2Inval, 68
300 ymm18, Class=RegSIMD|Ymmword, RegVRex, 2, Dw2Inval, 69
301 ymm19, Class=RegSIMD|Ymmword, RegVRex, 3, Dw2Inval, 70
302 ymm20, Class=RegSIMD|Ymmword, RegVRex, 4, Dw2Inval, 71
303 ymm21, Class=RegSIMD|Ymmword, RegVRex, 5, Dw2Inval, 72
304 ymm22, Class=RegSIMD|Ymmword, RegVRex, 6, Dw2Inval, 73
305 ymm23, Class=RegSIMD|Ymmword, RegVRex, 7, Dw2Inval, 74
306 ymm24, Class=RegSIMD|Ymmword, RegVRex|RegRex, 0, Dw2Inval, 75
307 ymm25, Class=RegSIMD|Ymmword, RegVRex|RegRex, 1, Dw2Inval, 76
308 ymm26, Class=RegSIMD|Ymmword, RegVRex|RegRex, 2, Dw2Inval, 77
309 ymm27, Class=RegSIMD|Ymmword, RegVRex|RegRex, 3, Dw2Inval, 78
310 ymm28, Class=RegSIMD|Ymmword, RegVRex|RegRex, 4, Dw2Inval, 79
311 ymm29, Class=RegSIMD|Ymmword, RegVRex|RegRex, 5, Dw2Inval, 80
312 ymm30, Class=RegSIMD|Ymmword, RegVRex|RegRex, 6, Dw2Inval, 81
313 ymm31, Class=RegSIMD|Ymmword, RegVRex|RegRex, 7, Dw2Inval, 82
314 // AVX512 registers.
315 zmm0, Class=RegSIMD|Zmmword, 0, 0, 21, 17
316 zmm1, Class=RegSIMD|Zmmword, 0, 1, 22, 18
317 zmm2, Class=RegSIMD|Zmmword, 0, 2, 23, 19
318 zmm3, Class=RegSIMD|Zmmword, 0, 3, 24, 20
319 zmm4, Class=RegSIMD|Zmmword, 0, 4, 25, 21
320 zmm5, Class=RegSIMD|Zmmword, 0, 5, 26, 22
321 zmm6, Class=RegSIMD|Zmmword, 0, 6, 27, 23
322 zmm7, Class=RegSIMD|Zmmword, 0, 7, 28, 24
323 zmm8, Class=RegSIMD|Zmmword, RegRex, 0, Dw2Inval, 25
324 zmm9, Class=RegSIMD|Zmmword, RegRex, 1, Dw2Inval, 26
325 zmm10, Class=RegSIMD|Zmmword, RegRex, 2, Dw2Inval, 27
326 zmm11, Class=RegSIMD|Zmmword, RegRex, 3, Dw2Inval, 28
327 zmm12, Class=RegSIMD|Zmmword, RegRex, 4, Dw2Inval, 29
328 zmm13, Class=RegSIMD|Zmmword, RegRex, 5, Dw2Inval, 30
329 zmm14, Class=RegSIMD|Zmmword, RegRex, 6, Dw2Inval, 31
330 zmm15, Class=RegSIMD|Zmmword, RegRex, 7, Dw2Inval, 32
331 zmm16, Class=RegSIMD|Zmmword, RegVRex, 0, Dw2Inval, 67
332 zmm17, Class=RegSIMD|Zmmword, RegVRex, 1, Dw2Inval, 68
333 zmm18, Class=RegSIMD|Zmmword, RegVRex, 2, Dw2Inval, 69
334 zmm19, Class=RegSIMD|Zmmword, RegVRex, 3, Dw2Inval, 70
335 zmm20, Class=RegSIMD|Zmmword, RegVRex, 4, Dw2Inval, 71
336 zmm21, Class=RegSIMD|Zmmword, RegVRex, 5, Dw2Inval, 72
337 zmm22, Class=RegSIMD|Zmmword, RegVRex, 6, Dw2Inval, 73
338 zmm23, Class=RegSIMD|Zmmword, RegVRex, 7, Dw2Inval, 74
339 zmm24, Class=RegSIMD|Zmmword, RegVRex|RegRex, 0, Dw2Inval, 75
340 zmm25, Class=RegSIMD|Zmmword, RegVRex|RegRex, 1, Dw2Inval, 76
341 zmm26, Class=RegSIMD|Zmmword, RegVRex|RegRex, 2, Dw2Inval, 77
342 zmm27, Class=RegSIMD|Zmmword, RegVRex|RegRex, 3, Dw2Inval, 78
343 zmm28, Class=RegSIMD|Zmmword, RegVRex|RegRex, 4, Dw2Inval, 79
344 zmm29, Class=RegSIMD|Zmmword, RegVRex|RegRex, 5, Dw2Inval, 80
345 zmm30, Class=RegSIMD|Zmmword, RegVRex|RegRex, 6, Dw2Inval, 81
346 zmm31, Class=RegSIMD|Zmmword, RegVRex|RegRex, 7, Dw2Inval, 82
347 // TMM registers for AMX
348 tmm0, Class=RegSIMD|Tmmword, 0, 0, Dw2Inval, Dw2Inval
349 tmm1, Class=RegSIMD|Tmmword, 0, 1, Dw2Inval, Dw2Inval
350 tmm2, Class=RegSIMD|Tmmword, 0, 2, Dw2Inval, Dw2Inval
351 tmm3, Class=RegSIMD|Tmmword, 0, 3, Dw2Inval, Dw2Inval
352 tmm4, Class=RegSIMD|Tmmword, 0, 4, Dw2Inval, Dw2Inval
353 tmm5, Class=RegSIMD|Tmmword, 0, 5, Dw2Inval, Dw2Inval
354 tmm6, Class=RegSIMD|Tmmword, 0, 6, Dw2Inval, Dw2Inval
355 tmm7, Class=RegSIMD|Tmmword, 0, 7, Dw2Inval, Dw2Inval
356 // Bound registers for MPX
357 bnd0, Class=RegBND, 0, 0, Dw2Inval, 126
358 bnd1, Class=RegBND, 0, 1, Dw2Inval, 127
359 bnd2, Class=RegBND, 0, 2, Dw2Inval, 128
360 bnd3, Class=RegBND, 0, 3, Dw2Inval, 129
361 // No Class=Reg will make these registers rejected for all purposes except
362 // for addressing. This saves creating one extra type for RIP/EIP.
363 rip, Qword, RegRex64, RegIP, Dw2Inval, 16
364 eip, Dword, RegRex64, RegIP, 8, Dw2Inval
365 // No Class=Reg will make these registers rejected for all purposes except
366 // for addressing.
367 riz, Qword|BaseIndex, RegRex64, RegIZ, Dw2Inval, Dw2Inval
368 eiz, Dword|BaseIndex, 0, RegIZ, Dw2Inval, Dw2Inval
369 // fp regs. No need for an explicit st(0) here.
370 st, Class=Reg|Instance=Accum|Tbyte, 0, 0, 11, 33
371 st(1), Class=Reg|Tbyte, 0, 1, 12, 34
372 st(2), Class=Reg|Tbyte, 0, 2, 13, 35
373 st(3), Class=Reg|Tbyte, 0, 3, 14, 36
374 st(4), Class=Reg|Tbyte, 0, 4, 15, 37
375 st(5), Class=Reg|Tbyte, 0, 5, 16, 38
376 st(6), Class=Reg|Tbyte, 0, 6, 17, 39
377 st(7), Class=Reg|Tbyte, 0, 7, 18, 40
378 // Pseudo-register names only used in .cfi_* directives
379 eflags, 0, 0, 0, 9, 49
380 rflags, 0, 0, 0, Dw2Inval, 49
381 fs.base, 0, 0, 0, Dw2Inval, 58
382 gs.base, 0, 0, 0, Dw2Inval, 59
383 tr, 0, 0, 0, 48, 62
384 ldtr, 0, 0, 0, 49, 63
385 // st0...7 for backward compatibility
386 st0, 0, 0, 0, 11, 33
387 st1, 0, 0, 1, 12, 34
388 st2, 0, 0, 2, 13, 35
389 st3, 0, 0, 3, 14, 36
390 st4, 0, 0, 4, 15, 37
391 st5, 0, 0, 5, 16, 38
392 st6, 0, 0, 6, 17, 39
393 st7, 0, 0, 7, 18, 40
394 fcw, 0, 0, 0, 37, 65
395 fsw, 0, 0, 0, 38, 66
396 mxcsr, 0, 0, 0, 39, 64