gprofng/common/hwctable.c

   1 /* Copyright (C) 2021-2024 Free Software Foundation, Inc.
   2    Contributed by Oracle.
   3
   4    This file is part of GNU Binutils.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 #include <stdlib.h>
  22 #include <stdio.h>
  23 #include <errno.h>
  24 #include <string.h>
  25 #include <limits.h>
  26 #include <linux/perf_event.h>
  27
  28 #include "hwcdrv.h"
  29
  30 /*---------------------------------------------------------------------------*/
  31 /* compile options */
  32
  33 #define DISALLOW_USI_USII_6357446
  34 /* Solaris 9/libcpc1 allows cpc_bind() to work on US-IIe processors, even
  35    though this processor cannot generate profiling interrupts. */
  36
  37 #define DISALLOW_PENTIUM_PRO_MMX_7007575
  38 /* Solaris/libcpc2 defaults to "Pentium Pro with MMX, Pentium II"
  39    when it doesn't recognize an Intel processor.  As a result,
  40    when collect attempts to start Pentium Pro counters on a
  41    new machine (e.g. Westmere as of 1/2011), the OS may hang.  */
  42
  43 /* Register 0 counter doesn't work on Niagara T1 version (?) */
  44 #define WORKAROUND_6231196_NIAGARA1_NO_CTR_0
  45
  46 /*---------------------------------------------------------------------------*/
  47 /* consts, macros */
  48
  49 /* 10^N rates */
  50 #define PRELOADS_9      1001000001
  51 #define PRELOADS_85      320100001
  52 #define PRELOADS_8       100100001
  53 #define PRELOADS_75       32010001
  54 #define PRELOADS_7        10010001
  55 #define PRELOADS_65        3201001
  56 #define PRELOADS_6         1001001
  57 #define PRELOADS_55         320101
  58 #define PRELOADS_5          100101
  59 #define PRELOADS_45          32001
  60 #define PRELOADS_4           10001
  61 #define PRELOADS_35           3201
  62 #define PRELOADS_3            1001
  63 #define PRELOADS_25            301
  64
  65 #define ABST_TBD        ABST_NONE /* to be determined */
  66
  67 /*---------------------------------------------------------------------------*/
  68 /* prototypes */
  69 static void hwc_cb (uint_t cpc_regno, const char *name);
  70 static void attrs_cb (const char *attr);
  71 static int attr_is_valid (int forKernel, const char *attr);
  72
  73 /*---------------------------------------------------------------------------*/
  74 /* HWC definition tables */
  75
  76 /*
  77   comments on hwcentry tables
  78   ---------------------------
  79   name:          this field should not contain '~'.
  80   int_name:      actual name of register, may contain ~ attribute specifications.
  81   regnum:        assigned register.
  82   metric:        if non-NULL, is a 'standard' counter that will show up in help.
  83   timecvt:       >0: can convert to time, 'timecvt' CPU cycles per event
  84                  =0: counts events
  85                  <0: can convert to time, count reference-clock cycles at '-timecvt' MHz
  86   memop:         see description for ABST_type enum
  87  */
  88
  89 // PRELOAD(): generates an interval based on the cycles/event and CPU GHZ.
  90 // Note: the macro tweaks the interval so that it ends in decimal 001.
  91 #define CYC_PER_SAMPLE (1000ULL*1000*1000/100) // cycles per signal at 1ghz, 100 samples/second
  92 #define PRELOAD(min_cycles_per_event,ghz) (((ghz)*CYC_PER_SAMPLE/(min_cycles_per_event))/100*100+1)
  93
  94 // PRELOAD_DEF: initial value for uncalibrated events.
  95 // This value should be based on a rate that will work for the slowest changing
  96 // HWCs, HWCs where there are many CPU cycles between events.
  97 //
  98 // The interval needs to target the slowest HWCs so that
  99 // automatic adjustment of HWC overflow intervals can adapt.
 100 #define PRELOAD_DEF PRELOAD(1000,3)  // default interval targets 1000 cycles/event at 3ghz
 101 // For er_kernel, which HWC intervals cannot be adjusted automatically for ON/HI/LO,
 102 // The interval should target some safe interval for fast events
 103 #define PRELOAD_DEF_ERKERNEL PRELOAD(4,4)  // default interval targets 4 cycles/event at 4ghz
 104
 105 static const Hwcentry empty_ctr = {NULL, NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, 0};
 106
 107
 108 // --- use cycles counter to expose "system_time" on Linux ---
 109 #define SYSTIME_REGNOS REGNO_ANY // Linux: make sys_time/usr_time available for data collection
 110 // Note: For x86, Linux and Solaris use different ref-clock names
 111 #define USE_INTEL_REF_CYCLES(MHZ) \
 112     {"usr_time","unhalted-reference-cycles",                SYSTIME_REGNOS, STXT("User CPU"),   PRELOAD(900,MHZ),  -(MHZ), ABST_NONE}, \
 113     {"usr_time","cpu_clk_unhalted.ref_p",                   SYSTIME_REGNOS, STXT("User CPU"),   PRELOAD(900,MHZ),  -(MHZ), ABST_NONE}, \
 114     {"sys_time","unhalted-reference-cycles~system=1~user=0", SYSTIME_REGNOS, STXT("System CPU"), PRELOAD(900,MHZ), -(MHZ), ABST_NONE}, \
 115     {"sys_time","cpu_clk_unhalted.ref_p~system=1~user=0",   SYSTIME_REGNOS, STXT("System CPU"), PRELOAD( 900,MHZ), -(MHZ), ABST_NONE}, \
 116     {"cycles0", "unhalted-reference-cycles",                0,  NULL,   PRELOAD( 900,MHZ),  -(MHZ), ABST_NONE}, /*hidden*/ \
 117     {"cycles0", "cpu_clk_unhalted.ref_p",                   0,  NULL,   PRELOAD( 900,MHZ),  -(MHZ), ABST_NONE}, /*hidden*/ \
 118     {"cycles1", "unhalted-reference-cycles",                1,  NULL,   PRELOAD( 910,MHZ),  -(MHZ), ABST_NONE}, /*hidden*/ \
 119     {"cycles1", "cpu_clk_unhalted.ref_p",                   1,  NULL,   PRELOAD( 910,MHZ),  -(MHZ), ABST_NONE}, /*hidden*/ \
 120     /* end of list */
 121
 122 #define SPARC_CYCLES \
 123     {"usr_time","Cycles_user",                  SYSTIME_REGNOS, STXT("User CPU"),   PRELOADS_75,1, ABST_NONE}, \
 124     {"sys_time","Cycles_user~system=1~user=0",  SYSTIME_REGNOS, STXT("System CPU"), PRELOADS_75,1, ABST_NONE}, \
 125     /* end of list */
 126
 127
 128 /* --- PERF_EVENTS "software" definitions --- */
 129 #define PERF_EVENTS_SW_EVENT_ALIASES \
 130 // none supported for now
 131 #if 0
 132     {"usr",             "PERF_COUNT_SW_TASK_CLOCK",                     REGNO_ANY, STXT("User CPU"),                    PRELOADS_7, -(1000), ABST_NONE}, \
 133     {"sys",             "PERF_COUNT_SW_TASK_CLOCK~system=1~user=0",     REGNO_ANY, STXT("System CPU"),                  PRELOADS_7, -(1000), ABST_NONE}, \
 134     /* end of list */
 135 #endif
 136
 137 #define PERF_EVENTS_SW_EVENT_DEFS \
 138 // none supported for now
 139 #if 0
 140     {"PERF_COUNT_SW_TASK_CLOCK",                                        NULL, REGNO_ANY, NULL, PRELOADS_7, -(1000),ABST_NONE}, \
 141     /* end of list */
 142 #endif
 143
 144 /*
 145  * The PAPI descriptive strings used to be wrapped with STXT(),
 146  * a macro defined in perfan/include/i18n.h.  For the time being,
 147  * we want to demote the PAPI counters by omitting the
 148  * descriptions.  So we use a new macro PAPITXT() for this purpose.
 149  */
 150 #define PAPITXT(x)  NULL
 151
 152 /* Solaris "Generic" Counters */
 153 static Hwcentry papi_generic_list[] = {
 154   {"PAPI_l1_dcm", NULL, REGNO_ANY, PAPITXT ("L1 D-cache misses"), PRELOADS_65, 0, ABST_NONE},
 155   {"PAPI_l1_icm", NULL, REGNO_ANY, PAPITXT ("L1 I-cache misses"), PRELOADS_6, 0, ABST_NONE},
 156   {"PAPI_l2_dcm", NULL, REGNO_ANY, PAPITXT ("L2 D-cache misses"), PRELOADS_6, 0, ABST_NONE},
 157   {"PAPI_l2_icm", NULL, REGNO_ANY, PAPITXT ("L2 I-cache misses"), PRELOADS_6, 0, ABST_NONE},
 158   {"PAPI_l3_dcm", NULL, REGNO_ANY, PAPITXT ("L3 D-cache misses"), PRELOADS_5, 0, ABST_NONE},
 159   {"PAPI_l3_icm", NULL, REGNO_ANY, PAPITXT ("L3 I-cache misses"), PRELOADS_5, 0, ABST_NONE},
 160   {"PAPI_l1_tcm", NULL, REGNO_ANY, PAPITXT ("L1 misses"), PRELOADS_65, 0, ABST_NONE},
 161   {"PAPI_l2_tcm", NULL, REGNO_ANY, PAPITXT ("L2 misses"), PRELOADS_6, 0, ABST_NONE},
 162   {"PAPI_l3_tcm", NULL, REGNO_ANY, PAPITXT ("L3 misses"), PRELOADS_5, 0, ABST_NONE},
 163   {"PAPI_ca_snp", NULL, REGNO_ANY, PAPITXT ("Requests for a snoop"), PRELOADS_6, 0, ABST_NONE},
 164   {"PAPI_ca_shr", NULL, REGNO_ANY, PAPITXT ("Requests for exclusive access to shared cache line"), PRELOADS_6, 0, ABST_NONE},
 165   {"PAPI_ca_cln", NULL, REGNO_ANY, PAPITXT ("Requests for exclusive access to clean cache line"), PRELOADS_6, 0, ABST_NONE},
 166   {"PAPI_ca_inv", NULL, REGNO_ANY, PAPITXT ("Requests for cache line invalidation"), PRELOADS_6, 0, ABST_NONE},
 167   {"PAPI_ca_itv", NULL, REGNO_ANY, PAPITXT ("Requests for cache line intervention"), PRELOADS_6, 0, ABST_NONE},
 168   {"PAPI_l3_ldm", NULL, REGNO_ANY, PAPITXT ("L3 load misses"), PRELOADS_5, 0, ABST_NONE},
 169   {"PAPI_l3_stm", NULL, REGNO_ANY, PAPITXT ("L3 store misses"), PRELOADS_5, 0, ABST_NONE},
 170   {"PAPI_bru_idl", NULL, REGNO_ANY, PAPITXT ("Cycles branch units are idle"), PRELOADS_7, 1, ABST_NONE},
 171   {"PAPI_fxu_idl", NULL, REGNO_ANY, PAPITXT ("Cycles integer units are idle"), PRELOADS_7, 1, ABST_NONE},
 172   {"PAPI_fpu_idl", NULL, REGNO_ANY, PAPITXT ("Cycles FP units are idle"), PRELOADS_7, 1, ABST_NONE},
 173   {"PAPI_lsu_idl", NULL, REGNO_ANY, PAPITXT ("Cycles load/store units are idle"), PRELOADS_7, 1, ABST_NONE},
 174   {"PAPI_tlb_dm", NULL, REGNO_ANY, PAPITXT ("DTLB misses"), PRELOADS_6, 0, ABST_NONE},
 175   {"PAPI_tlb_im", NULL, REGNO_ANY, PAPITXT ("ITLB misses"), PRELOADS_6, 0, ABST_NONE},
 176   {"PAPI_tlb_tl", NULL, REGNO_ANY, PAPITXT ("Total TLB misses"), PRELOADS_6, 0, ABST_NONE},
 177   {"PAPI_tlb_tm", NULL, REGNO_ANY, PAPITXT ("Total TLB misses"), PRELOADS_6, 0, ABST_NONE},
 178   {"PAPI_l1_ldm", NULL, REGNO_ANY, PAPITXT ("L1 load misses"), PRELOADS_65, 0, ABST_NONE},
 179   {"PAPI_l1_stm", NULL, REGNO_ANY, PAPITXT ("L1 store misses"), PRELOADS_65, 0, ABST_NONE},
 180   {"PAPI_l2_ldm", NULL, REGNO_ANY, PAPITXT ("L2 load misses"), PRELOADS_6, 0, ABST_NONE},
 181   {"PAPI_l2_stm", NULL, REGNO_ANY, PAPITXT ("L2 store misses"), PRELOADS_6, 0, ABST_NONE},
 182   {"PAPI_btac_m", NULL, REGNO_ANY, PAPITXT ("Branch target address cache misses"), PRELOADS_5, 0, ABST_NONE},
 183   {"PAPI_prf_dm", NULL, REGNO_ANY, PAPITXT ("Data prefetch cache misses"), PRELOADS_65, 0, ABST_NONE},
 184   {"PAPI_l3_dch", NULL, REGNO_ANY, PAPITXT ("L3 D-cache hits"), PRELOADS_6, 0, ABST_NONE},
 185   {"PAPI_tlb_sd", NULL, REGNO_ANY, PAPITXT ("TLB shootdowns"), PRELOADS_6, 0, ABST_NONE},
 186   {"PAPI_csr_fal", NULL, REGNO_ANY, PAPITXT ("Failed store conditional instructions"), PRELOADS_6, 0, ABST_NONE},
 187   {"PAPI_csr_suc", NULL, REGNO_ANY, PAPITXT ("Successful store conditional instructions"), PRELOADS_7, 0, ABST_NONE},
 188   {"PAPI_csr_tot", NULL, REGNO_ANY, PAPITXT ("Total store conditional instructions"), PRELOADS_7, 0, ABST_NONE},
 189   {"PAPI_mem_scy", NULL, REGNO_ANY, PAPITXT ("Cycles Stalled Waiting for memory accesses"), PRELOADS_7, 1, ABST_NONE},
 190   {"PAPI_mem_rcy", NULL, REGNO_ANY, PAPITXT ("Cycles Stalled Waiting for memory reads"), PRELOADS_7, 1, ABST_NONE},
 191   {"PAPI_mem_wcy", NULL, REGNO_ANY, PAPITXT ("Cycles Stalled Waiting for memory writes"), PRELOADS_7, 1, ABST_NONE},
 192   {"PAPI_stl_icy", NULL, REGNO_ANY, PAPITXT ("Cycles with no instruction issue"), PRELOADS_7, 1, ABST_NONE},
 193   {"PAPI_ful_icy", NULL, REGNO_ANY, PAPITXT ("Cycles with maximum instruction issue"), PRELOADS_7, 1, ABST_NONE},
 194   {"PAPI_stl_ccy", NULL, REGNO_ANY, PAPITXT ("Cycles with no instructions completed"), PRELOADS_7, 1, ABST_NONE},
 195   {"PAPI_ful_ccy", NULL, REGNO_ANY, PAPITXT ("Cycles with maximum instructions completed"), PRELOADS_7, 1, ABST_NONE},
 196   {"PAPI_hw_int", NULL, REGNO_ANY, PAPITXT ("Hardware interrupts"), PRELOADS_5, 0, ABST_NONE},
 197   {"PAPI_br_ucn", NULL, REGNO_ANY, PAPITXT ("Unconditional branch instructions"), PRELOADS_7, 0, ABST_NONE},
 198   {"PAPI_br_cn", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions"), PRELOADS_7, 0, ABST_NONE},
 199   {"PAPI_br_tkn", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions taken"), PRELOADS_7, 0, ABST_NONE},
 200   {"PAPI_br_ntk", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions not taken"), PRELOADS_7, 0, ABST_NONE},
 201   {"PAPI_br_msp", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions mispredicted"), PRELOADS_6, 0, ABST_NONE},
 202   {"PAPI_br_prc", NULL, REGNO_ANY, PAPITXT ("Cond. branch instructions correctly predicted"), PRELOADS_7, 0, ABST_NONE},
 203   {"PAPI_fma_ins", NULL, REGNO_ANY, PAPITXT ("FMA instructions completed"), PRELOADS_65, 0, ABST_NONE},
 204   {"PAPI_tot_iis", NULL, REGNO_ANY, PAPITXT ("Instructions issued"), PRELOADS_7, 0, ABST_NONE},
 205   {"PAPI_tot_ins", NULL, REGNO_ANY, PAPITXT ("Instructions completed"), PRELOADS_7, 0, ABST_NONE},
 206   {"PAPI_int_ins", NULL, REGNO_ANY, PAPITXT ("Integer instructions"), PRELOADS_7, 0, ABST_NONE},
 207   {"PAPI_fp_ins", NULL, REGNO_ANY, PAPITXT ("Floating-point instructions"), PRELOADS_7, 0, ABST_NONE},
 208   {"PAPI_ld_ins", NULL, REGNO_ANY, PAPITXT ("Load instructions"), PRELOADS_7, 0, ABST_NONE},
 209   {"PAPI_sr_ins", NULL, REGNO_ANY, PAPITXT ("Store instructions"), PRELOADS_7, 0, ABST_NONE},
 210   {"PAPI_br_ins", NULL, REGNO_ANY, PAPITXT ("Branch instructions"), PRELOADS_7, 0, ABST_NONE},
 211   {"PAPI_vec_ins", NULL, REGNO_ANY, PAPITXT ("Vector/SIMD instructions"), PRELOADS_7, 0, ABST_NONE},
 212   {"PAPI_res_stl", NULL, REGNO_ANY, PAPITXT ("Cycles stalled on any resource"), PRELOADS_7, 1, ABST_NONE},
 213   {"PAPI_fp_stal", NULL, REGNO_ANY, PAPITXT ("Cycles the FP unit(s) are stalled"), PRELOADS_7, 1, ABST_NONE},
 214   {"PAPI_tot_cyc", NULL, REGNO_ANY, PAPITXT ("Total cycles"), PRELOADS_7, 1, ABST_NONE},
 215   {"PAPI_lst_ins", NULL, REGNO_ANY, PAPITXT ("Load/store instructions completed"), PRELOADS_7, 0, ABST_NONE},
 216   {"PAPI_syc_ins", NULL, REGNO_ANY, PAPITXT ("Sync instructions completed"), PRELOADS_65, 0, ABST_NONE},
 217   {"PAPI_l1_dch", NULL, REGNO_ANY, PAPITXT ("L1 D-cache hits"), PRELOADS_7, 0, ABST_NONE},
 218   {"PAPI_l2_dch", NULL, REGNO_ANY, PAPITXT ("L2 D-cache hits"), PRELOADS_65, 0, ABST_NONE},
 219   {"PAPI_l1_dca", NULL, REGNO_ANY, PAPITXT ("L1 D-cache accesses"), PRELOADS_7, 0, ABST_NONE},
 220   {"PAPI_l2_dca", NULL, REGNO_ANY, PAPITXT ("L2 D-cache accesses"), PRELOADS_65, 0, ABST_NONE},
 221   {"PAPI_l3_dca", NULL, REGNO_ANY, PAPITXT ("L3 D-cache accesses"), PRELOADS_6, 0, ABST_NONE},
 222   {"PAPI_l1_dcr", NULL, REGNO_ANY, PAPITXT ("L1 D-cache reads"), PRELOADS_7, 0, ABST_NONE},
 223   {"PAPI_l2_dcr", NULL, REGNO_ANY, PAPITXT ("L2 D-cache reads"), PRELOADS_65, 0, ABST_NONE},
 224   {"PAPI_l3_dcr", NULL, REGNO_ANY, PAPITXT ("L3 D-cache reads"), PRELOADS_6, 0, ABST_NONE},
 225   {"PAPI_l1_dcw", NULL, REGNO_ANY, PAPITXT ("L1 D-cache writes"), PRELOADS_7, 0, ABST_NONE},
 226   {"PAPI_l2_dcw", NULL, REGNO_ANY, PAPITXT ("L2 D-cache writes"), PRELOADS_65, 0, ABST_NONE},
 227   {"PAPI_l3_dcw", NULL, REGNO_ANY, PAPITXT ("L3 D-cache writes"), PRELOADS_6, 0, ABST_NONE},
 228   {"PAPI_l1_ich", NULL, REGNO_ANY, PAPITXT ("L1 I-cache hits"), PRELOADS_7, 0, ABST_NONE},
 229   {"PAPI_l2_ich", NULL, REGNO_ANY, PAPITXT ("L2 I-cache hits"), PRELOADS_65, 0, ABST_NONE},
 230   {"PAPI_l3_ich", NULL, REGNO_ANY, PAPITXT ("L3 I-cache hits"), PRELOADS_6, 0, ABST_NONE},
 231   {"PAPI_l1_ica", NULL, REGNO_ANY, PAPITXT ("L1 I-cache accesses"), PRELOADS_7, 0, ABST_NONE},
 232   {"PAPI_l2_ica", NULL, REGNO_ANY, PAPITXT ("L2 I-cache accesses"), PRELOADS_65, 0, ABST_NONE},
 233   {"PAPI_l3_ica", NULL, REGNO_ANY, PAPITXT ("L3 I-cache accesses"), PRELOADS_6, 0, ABST_NONE},
 234   {"PAPI_l1_icr", NULL, REGNO_ANY, PAPITXT ("L1 I-cache reads"), PRELOADS_7, 0, ABST_NONE},
 235   {"PAPI_l2_icr", NULL, REGNO_ANY, PAPITXT ("L2 I-cache reads"), PRELOADS_65, 0, ABST_NONE},
 236   {"PAPI_l3_icr", NULL, REGNO_ANY, PAPITXT ("L3 I-cache reads"), PRELOADS_6, 0, ABST_NONE},
 237   {"PAPI_l1_icw", NULL, REGNO_ANY, PAPITXT ("L1 I-cache writes"), PRELOADS_7, 0, ABST_NONE},
 238   {"PAPI_l2_icw", NULL, REGNO_ANY, PAPITXT ("L2 I-cache writes"), PRELOADS_65, 0, ABST_NONE},
 239   {"PAPI_l3_icw", NULL, REGNO_ANY, PAPITXT ("L3 I-cache writes"), PRELOADS_6, 0, ABST_NONE},
 240   {"PAPI_l1_tch", NULL, REGNO_ANY, PAPITXT ("L1 total hits"), PRELOADS_7, 0, ABST_NONE},
 241   {"PAPI_l2_tch", NULL, REGNO_ANY, PAPITXT ("L2 total hits"), PRELOADS_65, 0, ABST_NONE},
 242   {"PAPI_l3_tch", NULL, REGNO_ANY, PAPITXT ("L3 total hits"), PRELOADS_6, 0, ABST_NONE},
 243   {"PAPI_l1_tca", NULL, REGNO_ANY, PAPITXT ("L1 total accesses"), PRELOADS_7, 0, ABST_NONE},
 244   {"PAPI_l2_tca", NULL, REGNO_ANY, PAPITXT ("L2 total accesses"), PRELOADS_65, 0, ABST_NONE},
 245   {"PAPI_l3_tca", NULL, REGNO_ANY, PAPITXT ("L3 total accesses"), PRELOADS_6, 0, ABST_NONE},
 246   {"PAPI_l1_tcr", NULL, REGNO_ANY, PAPITXT ("L1 total reads"), PRELOADS_7, 0, ABST_NONE},
 247   {"PAPI_l2_tcr", NULL, REGNO_ANY, PAPITXT ("L2 total reads"), PRELOADS_65, 0, ABST_NONE},
 248   {"PAPI_l3_tcr", NULL, REGNO_ANY, PAPITXT ("L3 total reads"), PRELOADS_6, 0, ABST_NONE},
 249   {"PAPI_l1_tcw", NULL, REGNO_ANY, PAPITXT ("L1 total writes"), PRELOADS_7, 0, ABST_NONE},
 250   {"PAPI_l2_tcw", NULL, REGNO_ANY, PAPITXT ("L2 total writes"), PRELOADS_65, 0, ABST_NONE},
 251   {"PAPI_l3_tcw", NULL, REGNO_ANY, PAPITXT ("L3 total writes"), PRELOADS_6, 0, ABST_NONE},
 252   {"PAPI_fml_ins", NULL, REGNO_ANY, PAPITXT ("FP multiply instructions"), PRELOADS_7, 0, ABST_NONE},
 253   {"PAPI_fad_ins", NULL, REGNO_ANY, PAPITXT ("FP add instructions"), PRELOADS_7, 0, ABST_NONE},
 254   {"PAPI_fdv_ins", NULL, REGNO_ANY, PAPITXT ("FP divide instructions"), PRELOADS_7, 0, ABST_NONE},
 255   {"PAPI_fsq_ins", NULL, REGNO_ANY, PAPITXT ("FP square root instructions"), PRELOADS_65, 0, ABST_NONE},
 256   {"PAPI_fnv_ins", NULL, REGNO_ANY, PAPITXT ("FP inverse instructions"), PRELOADS_7, 0, ABST_NONE},
 257   {"PAPI_fp_ops", NULL, REGNO_ANY, PAPITXT ("FP operations"), PRELOADS_7, 0, ABST_NONE},
 258   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 259 };
 260
 261 static Hwcentry usIlist[] = {
 262   {"cycles", "Cycle_cnt", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
 263   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 264   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 265 };
 266
 267 static Hwcentry usIIIlist[] = /* III, IIIi, IIIp.  Note that some counters are processor-specific */{
 268   {"cycles", "Cycle_cnt", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
 269   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 270   {"icm", "IC_miss", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE},
 271   {"dcrm", "DC_rd_miss", REGNO_ANY, STXT ("D$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 272   {"dcwm", "DC_wr_miss", REGNO_ANY, STXT ("D$ Write Misses"), PRELOADS_5, 0, ABST_STORE},
 273   {"dcr", "DC_rd", REGNO_ANY, STXT ("D$ Read Refs"), PRELOADS_6, 0, ABST_LOAD},
 274   {"dcw", "DC_wr", REGNO_ANY, STXT ("D$ Write Refs"), PRELOADS_6, 0, ABST_STORE},
 275   {"ecref", "EC_ref", REGNO_ANY, STXT ("E$ Refs"), PRELOADS_6, 0, ABST_LDST},
 276   {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
 277   {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_US_DTLBM},
 278   {"ecm", "EC_misses", REGNO_ANY, STXT ("E$ Misses"), PRELOADS_5, 0, ABST_LDST},
 279   {"ecrm", "EC_rd_miss", REGNO_ANY, STXT ("E$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 280   {"ecml", "EC_miss_local", REGNO_ANY, STXT ("E$ Local Misses"), PRELOADS_5, 0, ABST_LDST},
 281   {"ecmr", "EC_miss_remote", REGNO_ANY, STXT ("E$ Remote Misses"), PRELOADS_5, 0, ABST_LDST},
 282   {"ecim", "EC_ic_miss", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE},
 283   {"icstall", "Dispatch0_IC_miss", REGNO_ANY, STXT ("I$ Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 284   {"dcstall", "Re_DC_miss", REGNO_ANY, STXT ("D$ and E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 285   {"ecstall", "Re_EC_miss", REGNO_ANY, STXT ("E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 286   {"sqstall", "Rstall_storeQ", REGNO_ANY, STXT ("StoreQ Stall Cycles"), PRELOADS_6, 1, ABST_STORE},
 287   {"rawstall", "Re_RAW_miss", REGNO_ANY, STXT ("RAW Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 288   {"dcmissov", "Re_DC_missovhd", REGNO_ANY, STXT ("DC Miss Ovhd"), PRELOADS_6, 1, ABST_LOAD},
 289   {"fpustall", "Re_FPU_bypass", REGNO_ANY, STXT ("FPU Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 290   {"fpusestall", "Rstall_FP_use", REGNO_ANY, STXT ("FPU Use Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 291   {"iustall", "Rstall_IU_use", REGNO_ANY, STXT ("IU Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 292   {"fpadd", "FA_pipe_completion", REGNO_ANY, STXT ("FP Adds"), PRELOADS_6, 0, ABST_NONE},
 293   {"fpmul", "FM_pipe_completion", REGNO_ANY, STXT ("FP Muls"), PRELOADS_6, 0, ABST_NONE},
 294
 295   /* explicit definitions of (hidden) entries for proper counters */
 296   /*  Only counters that can be time converted, or are load-store need to be in this table */
 297   {"Cycle_cnt", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
 298   {"EC_miss_mtag_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 299   {"DC_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 300   {"DC_wr_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 301   {"DC_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 302   {"DC_wr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 303   {"EC_ref", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 304   {"EC_snoop_inv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 305   {"EC_wb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 306   {"EC_wb_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 307   {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_US_DTLBM},
 308   {"EC_misses", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 309   {"EC_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 310   {"PC_port0_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 311   {"EC_miss_local", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 312   {"EC_miss_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 313   {"EC_snoop_cb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 314   {"WC_snoop_cb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 315   {"WC_scrubbed", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 316   {"WC_wb_wo_read", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 317   {"PC_MS_misses", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 318   {"PC_soft_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 319   {"PC_hard_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 320   {"PC_port1_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 321   {"PC_snoop_inv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE /*?*/},
 322   {"SW_count_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_COUNT},
 323   {"SW_count_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_COUNT},
 324   {"Dispatch0_IC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 325   {"Dispatch0_mispred", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 326   {"Dispatch0_br_target", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 327   {"Dispatch0_2nd_br", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 328   {"Dispatch_rs_mispred", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 329   {"Rstall_storeQ", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_STORE},
 330   {"Rstall_FP_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 331   {"Rstall_IU_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 332   {"EC_write_hit_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 333   {"Re_RAW_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 334   {"Re_DC_missovhd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 335   {"Re_endian_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 336   {"Re_FPU_bypass", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 337   {"Re_DC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 338   {"Re_EC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 339   {"Re_PC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 340   {"SI_snoop", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 341   {"SI_ciq_flow", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 342   {"SI_owned", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 343   {"MC_msl_busy_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 344   {"MC_mdb_overflow_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 345   {"MC_page_close_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 346   {"MC_reads_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 347   {"MC_reads_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 348   {"MC_reads_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 349   {"MC_reads_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 350   {"MC_writes_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 351   {"MC_writes_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 352   {"MC_writes_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 353   {"MC_writes_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 354   {"MC_stalls_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 355   {"MC_stalls_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 356   {"MC_stalls_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 357   {"MC_stalls_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 358
 359   /* additional (hidden) aliases, for convenience */
 360   {"cycles0", "Cycle_cnt", 0, NULL, PRELOADS_75, 1, ABST_NONE},
 361   {"cycles1", "Cycle_cnt", 1, NULL, PRELOADS_75, 1, ABST_NONE},
 362   {"insts0", "Instr_cnt", 0, NULL, PRELOADS_75, 0, ABST_NONE},
 363   {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE},
 364   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 365 };
 366
 367 static Hwcentry usIVplist[] = {
 368   {"cycles", "Cycle_cnt", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
 369   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 370   {"icm", "IC_fill", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE},
 371   {"dcrm", "DC_rd_miss", REGNO_ANY, STXT ("D$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 372   {"dcwm", "DC_wr_miss", REGNO_ANY, STXT ("D$ Write Misses"), PRELOADS_5, 0, ABST_STORE},
 373   {"dcr", "DC_rd", REGNO_ANY, STXT ("D$ Read Refs"), PRELOADS_6, 0, ABST_LOAD},
 374   {"dcw", "DC_wr", REGNO_ANY, STXT ("D$ Write Refs"), PRELOADS_6, 0, ABST_STORE},
 375   {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
 376   {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_US_DTLBM},
 377   {"l2ref", "L2_ref", REGNO_ANY, STXT ("L2$ Refs"), PRELOADS_5, 0, ABST_LDST},
 378   {"l2m", "L2_miss", REGNO_ANY, STXT ("L2$ Misses"), PRELOADS_5, 0, ABST_LDST},
 379   {"l2rm", "L2_rd_miss", REGNO_ANY, STXT ("L2$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 380   {"l2im", "L2_IC_miss", REGNO_ANY, STXT ("L2$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE},
 381   {"ecm", "L3_miss", REGNO_ANY, STXT ("E$ Misses"), PRELOADS_5, 0, ABST_LDST},
 382   {"ecrm", "L3_rd_miss", REGNO_ANY, STXT ("E$ Read Misses"), PRELOADS_5, 0, ABST_LOAD},
 383   {"ecml", "SSM_L3_miss_local", REGNO_ANY, STXT ("E$ Local Misses"), PRELOADS_5, 0, ABST_LDST},
 384   {"ecmr", "SSM_L3_miss_remote", REGNO_ANY, STXT ("E$ Remote Misses"), PRELOADS_5, 0, ABST_LDST},
 385   {"ecim", "L3_IC_miss", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE},
 386   {"icstall", "Dispatch0_IC_miss", REGNO_ANY, STXT ("I$ Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 387   {"dcstall", "Re_DC_miss", REGNO_ANY, STXT ("D$ and E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 388   {"ecstall", "Re_L3_miss", REGNO_ANY, STXT ("E$ Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 389   {"sqstall", "Rstall_storeQ", REGNO_ANY, STXT ("StoreQ Stall Cycles"), PRELOADS_6, 1, ABST_STORE},
 390   {"rawstall", "Re_RAW_miss", REGNO_ANY, STXT ("RAW Stall Cycles"), PRELOADS_6, 1, ABST_LOAD},
 391   {"dcmissov", "Re_DC_missovhd", REGNO_ANY, STXT ("DC Miss Ovhd"), PRELOADS_6, 1, ABST_LOAD},
 392   {"fpustall", "Re_FPU_bypass", REGNO_ANY, STXT ("FPU Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 393   {"fpusestall", "Rstall_FP_use", REGNO_ANY, STXT ("FPU Use Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 394   {"iustall", "Rstall_IU_use", REGNO_ANY, STXT ("IU Stall Cycles"), PRELOADS_6, 1, ABST_NONE},
 395   {"fpadd", "FA_pipe_completion", REGNO_ANY, STXT ("FP Adds"), PRELOADS_6, 0, ABST_NONE},
 396   {"fpmul", "FM_pipe_completion", REGNO_ANY, STXT ("FP Muls"), PRELOADS_6, 0, ABST_NONE},
 397
 398   /* explicit definitions of (hidden) entries for proper counters */
 399   /*  Only counters that can be time converted, or are load-store need to be in this table */
 400   {"Cycle_cnt", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
 401   {"DC_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 402   {"DC_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 403   {"DC_wr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 404   {"DC_wr_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 405   {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_US_DTLBM},
 406   {"Dispatch0_2nd_br", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 407   {"Dispatch0_IC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 408   {"Dispatch0_other", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 409   {"L2L3_snoop_cb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 410   {"L2L3_snoop_inv_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 411   {"L2_hit_I_state_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/},
 412   {"L2_hit_other_half", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 413   {"L2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 414   {"L2_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 415   {"L2_ref", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 416   {"L2_snoop_cb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 417   {"L2_snoop_inv_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC /*?*/},
 418   {"L2_wb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 419   {"L2_wb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 420   {"L2_write_hit_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 421   {"L2_write_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 422   {"L3_hit_I_state_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 423   {"L3_hit_other_half", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 424   {"L3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 425   {"L3_rd_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 426   {"L3_wb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 427   {"L3_wb_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 428   {"L3_write_hit_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 429   {"L3_write_miss_RTO", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE},
 430   {"MC_reads_0_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 431   {"MC_reads_1_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 432   {"MC_reads_2_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 433   {"MC_reads_3_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 434   {"MC_stalls_0_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 435   {"MC_stalls_1_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 436   {"MC_stalls_2_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 437   {"MC_stalls_3_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 438   {"MC_writes_0_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 439   {"MC_writes_1_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 440   {"MC_writes_2_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 441   {"MC_writes_3_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 442   /*? {"PC_MS_misses",  NULL, REGNO_ANY, NULL, PRELOAD_DEF,     0, ABST_LOAD}, */
 443   {"PC_hard_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 444   {"PC_inv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE /*?*/},
 445   {"PC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 446   {"PC_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 447   {"PC_soft_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LOAD},
 448   {"Re_DC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 449   {"Re_DC_missovhd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 450   {"Re_FPU_bypass", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 451   {"Re_L2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 452   {"Re_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 453   {"Re_PFQ_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 454   {"Re_RAW_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_LOAD},
 455   {"Rstall_FP_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 456   {"Rstall_IU_use", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 457   {"Rstall_storeQ", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_STORE},
 458   {"SI_RTO_src_data", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 459   {"SI_RTS_src_data", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 460   {"SI_ciq_flow_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NOPC},
 461   {"SI_owned_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 462   {"SI_snoop_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NOPC},
 463   {"ecml", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 464   {"ecmr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST},
 465   {"SSM_L3_miss_local", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/},
 466   {"SSM_L3_miss_mtag_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/},
 467   {"SSM_L3_miss_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_LDST /*?*/},
 468   {"SSM_L3_wb_remote", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_STORE /*?*/},
 469   {"SSM_new_transaction_sh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_TBD /*?*/},
 470
 471   /* additional (hidden) aliases, for convenience */
 472   {"cycles0", "Cycle_cnt", 0, NULL, PRELOADS_75, 1, ABST_NONE},
 473   {"cycles1", "Cycle_cnt", 1, NULL, PRELOADS_75, 1, ABST_NONE},
 474   {"insts0", "Instr_cnt", 0, NULL, PRELOADS_75, 0, ABST_NONE},
 475   {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE},
 476   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 477 };
 478
 479 static Hwcentry niagara1[] =
 480         /* CPC_ULTRA_T1              , "UltraSPARC T1" */{
 481   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 482 #ifndef WORKAROUND_6231196_NIAGARA1_NO_CTR_0 /* since register 0 counter don't work XXX */
 483   {"icm", "IC_miss", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE},
 484   {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
 485   {"ecim", "L2_imiss", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_4, 0, ABST_NONE},
 486   {"dcm", "DC_miss", REGNO_ANY, STXT ("D$ Misses"), PRELOADS_5, 0, ABST_EXACT},
 487   {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_EXACT},
 488   {"ecdm", "L2_dmiss_ld", REGNO_ANY, STXT ("E$ Data Misses"), PRELOADS_4, 0, ABST_EXACT},
 489   {"flops", "FP_instr_cnt", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_6, 0, ABST_NONE},
 490
 491   /* explicit definitions of (hidden) entries for proper counters */
 492   /*  Only counters that can be time converted, or are load-store need to be in this table */
 493   {"SB_full", NULL, REGNO_ANY, NULL, PRELOADS_6, 1, ABST_NONE},
 494   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOADS_6, 0, ABST_EXACT},
 495   {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOADS_6, 0, ABST_EXACT},
 496   {"L2_dmiss_ld", NULL, REGNO_ANY, NULL, PRELOADS_6, 0, ABST_EXACT},
 497 #endif
 498
 499   /* additional (hidden) aliases, for convenience */
 500   {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE},
 501   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 502 };
 503
 504 static Hwcentry niagara2[] = {
 505   /* CPC_ULTRA_T2              , "UltraSPARC T2" */
 506   /* CPC_ULTRA_T2              , "UltraSPARC T2+" */
 507   {"insts", "Instr_cnt", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
 508   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 509   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_6, 0, ABST_EXACT},
 510   {"dcm", "DC_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_EXACT},
 511   {"dtlbm", "DTLB_miss", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
 512   {"l2drm", "L2_dmiss_ld", REGNO_ANY, STXT ("L2 D-cache Read Misses (See Bug 15664448)"), PRELOADS_5, 0, ABST_EXACT},
 513   {"icm", "IC_miss", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_5, 0, ABST_NONE},
 514   {"itlbm", "ITLB_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
 515   {"l2im", "L2_imiss", REGNO_ANY, STXT ("L2 I-cache Misses"), PRELOADS_4, 0, ABST_NONE},
 516
 517   /* explicit definitions of (hidden) entries for proper counters */
 518   /* Only counters that can be time converted, or are load-store need to be in this table */
 519   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOADS_7, 0, ABST_EXACT},
 520   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
 521   {"Atomics", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
 522   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
 523   {"L2_dmiss_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
 524   {"DTLB_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
 525   {"DES_3DES_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 526   {"AES_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 527   {"Kasumi_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 528   {"MD5_SHA-1_SHA-256_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 529   {"MA_busy_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 530
 531   /* additional (hidden) aliases, for convenience */
 532   {"insts1", "Instr_cnt", 1, NULL, PRELOADS_75, 0, ABST_NONE},
 533   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 534 };
 535
 536 static Hwcentry sparc_t4[] = {
 537   // Identical to sparc_t5_m6 except for: l3m_spec
 538   // when updating this table, also update sparc_t5_m6[]
 539   // obsolete aliases marked with REGNO_INVALID (allows reading of older experiments)
 540   {"l2l3dh", "DC_miss_L2_L3_hit_nospec", REGNO_INVALID, STXT ("L2 or L3 D-cache Hits"), PRELOADS_6, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 541   {"l3m", "DC_miss_remote_L3_hit_nospec~emask=0x6", REGNO_INVALID, STXT ("L3 D-cache Misses"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 542   {"lmh", "DC_miss_local_hit_nospec", REGNO_INVALID, STXT ("Local Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 543   {"rmh", "DC_miss_remote_L3_hit_nospec", REGNO_INVALID, STXT ("Remote Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 544   {"pqs", "PQ_tag_wait", REGNO_INVALID, STXT ("Pick Queue Stalls"), PRELOADS_7, 1, ABST_NONE}, // old alias name
 545   {"raw_stb", "RAW_hit_st_buf", REGNO_INVALID, STXT ("RAW Hazard in Store Buffer"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_q)
 546   {"raw_stq", "RAW_hit_st_q", REGNO_INVALID, STXT ("RAW Hazard in Store Queue"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_buf)
 547   {"sel_stalls", "Sel_0_ready", REGNO_INVALID, STXT ("Stalls Another Thread Selected"), PRELOADS_7, 1, ABST_NONE},
 548   {"icm", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Misses"), PRELOADS_55, 0, ABST_NONE}, // 20@ l2/l3 hit (guess)
 549   {"icm_stalls", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Miss Est Stalls"), PRELOADS_55, 25, ABST_NONE}, // 25@ l2-20/l3-50
 550
 551   // current aliases
 552   SPARC_CYCLES
 553   {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
 554   {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
 555   {"c_stalls", "Commit_0", REGNO_ANY, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
 556   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 557   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_7, 0, ABST_EXACT},
 558   {"dcm", "DC_miss_nospec", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_EXACT},
 559   {"l3m_spec", "DC_miss_local_hit~emask=0x6", REGNO_ANY, STXT ("L3 D-cache Speculative Misses"), PRELOADS_5, 0, ABST_NONE, STXT ("Loads that speculatively missed local L3")}, // T4 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile
 560   //  {"l3m_spec",      "DC_miss_local_hit~emask=0x30",         REGNO_ANY, STXT("L3 D-cache Speculative Misses"),PRELOADS_5,0, ABST_NONE, STXT("Loads that speculatively missed local L3")}, // T5/M6 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile
 561   {"lmh_spec", "DC_miss_local_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 562   {"rmh_spec", "DC_miss_remote_L3_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 563   //
 564   {"dtlbm", "DTLB_miss_asynch", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_55, 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap  0.001 events/cycle
 565   {"dtlb_hwtw_stalls", "DTLB_HWTW_all", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOADS_55, 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50
 566   {"dtlb_trap_stalls", "DTLB_fill_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOADS_35, 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap
 567   {"rawhaz", "RAW_hit_st_q~emask=0xf", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOADS_55, 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")},
 568   {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOADS_6, 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad
 569   {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE}, // 24@miss, %5 of branches is bad
 570   {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE}, // 2 cycles minimum
 571   {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE}, // 24@miss, %5 of branches is bad
 572   {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE}, // 1 cycle/event
 573
 574   /* explicit definitions of (hidden) entries for proper counters */
 575   /* Counters that can be time converted, support memspace, or have a short_desc need to be in this table */
 576
 577   {"Sel_pipe_drain_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")},
 578   {"Sel_0_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved")},
 579   {"Sel_0_ready", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")},
 580   {"Sel_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that only 1 instruction or uop was selected")},
 581   {"Sel_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that 2 instructions or uops were selected")},
 582
 583   {"Pick_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 584   {"Pick_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 585   {"Pick_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 586   {"Pick_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 587   {"Pick_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 588
 589   {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")},
 590   {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")},
 591   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")},
 592   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")},
 593   {"SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")},
 594   {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 4), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")},
 595   {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 0, ABST_NONE, STXT ("Total instructions completed")},
 596
 597   {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")},
 598   {"Sw_count_intr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("SW Count instructions completed")},
 599   {"Atomics", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")},
 600   {"SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")},
 601   {"Block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Block load/store instructions completed")},
 602
 603   {"BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")},
 604
 605   {"ITLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")},
 606   {"ITLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")},
 607   {"ITLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")},
 608   {"ITLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")},
 609   {"ITLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 610   {"ITLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")},
 611   {"ITLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")},
 612
 613   {"Fetch_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 614   {"Fetch_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 615
 616   {"Instr_buffer_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 617
 618   {"PQ_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 619   {"ROB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 620   {"LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 621   {"ROB_LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 622   {"SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 623   {"ROB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 624   {"LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 625   {"ROB_LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 626   {"DTLB_miss_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 627
 628   {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")},
 629   {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 630   {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")},
 631   {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")},
 632   {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 633   {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")},
 634   {"DTLB_HWTW_all", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")},
 635
 636   {"DC_miss_L2_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT},
 637   {"DC_miss_local_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_EXACT},
 638   {"DC_miss_remote_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_EXACT},
 639   {"DC_miss_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT, STXT ("Loads that missed local L1D")},
 640
 641   {"DTLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")},
 642   {"DTLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")},
 643   {"DTLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")},
 644   {"DTLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")},
 645   {"DTLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 646   {"DTLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")},
 647   {"DTLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")},
 648   {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")},
 649   {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")},
 650
 651   {"St_q_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 652
 653   {"St_hit_L2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")},
 654   {"St_hit_L3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")},
 655
 656   {"DC_miss_L2_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D or L3")},
 657   {"DC_miss_local_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")},
 658   {"DC_miss_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache or remote memory")},
 659   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed L1D")},
 660
 661   {"L2_pipe_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 662
 663   {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")},
 664   {"Br_trg_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")},
 665   {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")},
 666
 667   {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")},
 668   //
 669   {"Commit_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")},
 670   {"Commit_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")},
 671   {"Commit_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 uop commits from this hardware thread")},
 672   {"Commit_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 2 uops commit from this hardware thread")},
 673   {"Commit_1_or_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 or 2 uops commit from this hardware thread")},
 674
 675   /* additional (hidden) aliases, for convenience */
 676   {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE},
 677   {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE},
 678   {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE},
 679   {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE},
 680   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 681 };
 682
 683 static Hwcentry sparc_t5_m6[] = {
 684   // Identical to sparc_t4 except for: l3m_spec
 685   // when updating this table, also update sparc_t4[]
 686   // obsolete aliases marked with REGNO_INVALID (allows reading of older experiments)
 687   {"l2l3dh", "DC_miss_L2_L3_hit_nospec", REGNO_INVALID, STXT ("L2 or L3 D-cache Hits"), PRELOADS_6, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 688   {"l3m", "DC_miss_remote_L3_hit_nospec~emask=0x6", REGNO_INVALID, STXT ("L3 D-cache Misses"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 689   {"lmh", "DC_miss_local_hit_nospec", REGNO_INVALID, STXT ("Local Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 690   {"rmh", "DC_miss_remote_L3_hit_nospec", REGNO_INVALID, STXT ("Remote Mem. Hits"), PRELOADS_5, 0, ABST_EXACT}, // undercounts due to thread-hog issue
 691   {"pqs", "PQ_tag_wait", REGNO_INVALID, STXT ("Pick Queue Stalls"), PRELOADS_7, 1, ABST_NONE}, // old alias name
 692   {"raw_stb", "RAW_hit_st_buf", REGNO_INVALID, STXT ("RAW Hazard in Store Buffer"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_q)
 693   {"raw_stq", "RAW_hit_st_q", REGNO_INVALID, STXT ("RAW Hazard in Store Queue"), PRELOADS_55, 0, ABST_NONE}, // 11@full hit, 60@partial hit (in future, combine w/st_buf)
 694   {"sel_stalls", "Sel_0_ready", REGNO_INVALID, STXT ("Stalls Another Thread Selected"), PRELOADS_7, 1, ABST_NONE},
 695   {"icm", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Misses"), PRELOADS_55, 0, ABST_NONE}, // 20@ l2/l3 hit (guess)
 696   {"icm_stalls", "IC_miss", REGNO_INVALID, STXT ("L1 I-Cache Miss Est Stalls"), PRELOADS_55, 25, ABST_NONE}, // 25@ l2-20/l3-50
 697
 698   // current aliases
 699   SPARC_CYCLES
 700   {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
 701   {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
 702   {"c_stalls", "Commit_0", REGNO_ANY, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
 703
 704   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 705   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_7, 0, ABST_EXACT},
 706   {"dcm", "DC_miss_nospec", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_EXACT},
 707   //  {"l3m_spec",      "DC_miss_local_hit~emask=0x6",          REGNO_ANY, STXT("L3 D-cache Speculative Misses"),PRELOADS_5,0, ABST_NONE, STXT("Loads that speculatively missed local L3")}, // T4 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile
 708   {"l3m_spec", "DC_miss_local_hit~emask=0x30", REGNO_ANY, STXT ("L3 D-cache Speculative Misses"), PRELOADS_5, 0, ABST_NONE, STXT ("Loads that speculatively missed local L3")}, // T5/M6 encoding (430 lm, 690 rm) ~5 misses overlap on t5/pico_ile
 709   {"lmh_spec", "DC_miss_local_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 710   {"rmh_spec", "DC_miss_remote_L3_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 711   //
 712   {"dtlbm", "DTLB_miss_asynch", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_55, 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap  0.001 events/cycle
 713   {"dtlb_hwtw_stalls", "DTLB_HWTW_all", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOADS_55, 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50
 714   {"dtlb_trap_stalls", "DTLB_fill_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOADS_35, 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap
 715   {"rawhaz", "RAW_hit_st_q~emask=0xf", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOADS_55, 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")},
 716   {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOADS_6, 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad
 717   {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE}, // 24@miss, %5 of branches is bad
 718   {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE}, // 2 cycles minimum
 719   {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE}, // 24@miss, %5 of branches is bad
 720   {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE}, // 1 cycle/event
 721
 722   /* explicit definitions of (hidden) entries for proper counters */
 723   /* Counters that can be time converted, support memspace, or have a short_desc need to be in this table */
 724
 725   {"Sel_pipe_drain_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")},
 726   {"Sel_0_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved")},
 727   {"Sel_0_ready", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")},
 728   {"Sel_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that only 1 instruction or uop was selected")},
 729   {"Sel_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that 2 instructions or uops were selected")},
 730
 731   {"Pick_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 732   {"Pick_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 733   {"Pick_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 734   {"Pick_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 735   {"Pick_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 736
 737   {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")},
 738   {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")},
 739   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")},
 740   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")},
 741   {"SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")},
 742   {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 4), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")},
 743   {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 0, ABST_NONE, STXT ("Total instructions completed")},
 744
 745   {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")},
 746   {"Sw_count_intr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("SW Count instructions completed")},
 747   {"Atomics", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")},
 748   {"SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")},
 749   {"Block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Block load/store instructions completed")},
 750
 751   {"BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")},
 752
 753   {"ITLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")},
 754   {"ITLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")},
 755   {"ITLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")},
 756   {"ITLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")},
 757   {"ITLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 758   {"ITLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")},
 759   {"ITLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")},
 760
 761   {"Fetch_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 762   {"Fetch_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 763
 764   {"Instr_buffer_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 765
 766   {"PQ_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 767   {"ROB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 768   {"LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 769   {"ROB_LB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 770   {"SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 771   {"ROB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 772   {"LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 773   {"ROB_LB_SB_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 774   {"DTLB_miss_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 775
 776   {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")},
 777   {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 778   {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")},
 779   {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")},
 780   {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 781   {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")},
 782   {"DTLB_HWTW_all", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")},
 783
 784   {"DC_miss_L2_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT},
 785   {"DC_miss_local_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_EXACT},
 786   {"DC_miss_remote_L3_hit_nospec", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_EXACT},
 787   {"DC_miss_nospec", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT, STXT ("Loads that missed local L1D")},
 788
 789   {"DTLB_fill_8KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")},
 790   {"DTLB_fill_64KB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")},
 791   {"DTLB_fill_4MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")},
 792   {"DTLB_fill_256MB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")},
 793   {"DTLB_fill_2GB", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 794   {"DTLB_fill_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")},
 795   {"DTLB_miss_asynch", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")},
 796   {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")},
 797   {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")},
 798
 799   {"St_q_tag_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 800
 801   {"St_hit_L2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")},
 802   {"St_hit_L3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")},
 803
 804   {"DC_miss_L2_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D or L3")},
 805   {"DC_miss_local_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")},
 806   {"DC_miss_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache or remote memory")},
 807   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed L1D")},
 808
 809   {"L2_pipe_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 810
 811   {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")},
 812   {"Br_trg_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")},
 813   {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")},
 814
 815   {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")},
 816   //
 817   {"Commit_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")},
 818   {"Commit_0_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")},
 819   {"Commit_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 uop commits from this hardware thread")},
 820   {"Commit_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 2 uops commit from this hardware thread")},
 821   {"Commit_1_or_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 or 2 uops commit from this hardware thread")},
 822
 823   /* additional (hidden) aliases, for convenience */
 824   {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE},
 825   {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE},
 826   {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE},
 827   {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE},
 828   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 829 };
 830
 831 static Hwcentry sparc_m7[] = {
 832   // obsolete aliases marked with REGNO_INVALID (allows reading of older experiments)
 833   {"icm", "IC_miss_commit", REGNO_INVALID, STXT ("L1 I-Cache Misses"), PRELOADS_6, 0, ABST_EXACT},
 834   {"raw_stb", "RAW_hit_st_buf", REGNO_INVALID, STXT ("RAW Hazard in Store Buffer"), PRELOADS_55, 0, ABST_NONE},
 835   {"raw_stq", "RAW_hit_st_q", REGNO_INVALID, STXT ("RAW Hazard in Store Queue"), PRELOADS_55, 0, ABST_NONE},
 836   {"pqs", "PQ_tag_wait_cyc", REGNO_INVALID, STXT ("Pick Queue Stalls"), PRELOADS_7, 1, ABST_NONE},
 837   {"sel_stalls", "Sel_0_ready_cyc", REGNO_INVALID, STXT ("Stalls Another Thread Selected"), PRELOADS_7, 1, ABST_NONE},
 838
 839   // current aliases
 840   SPARC_CYCLES
 841   {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
 842   {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
 843   {"c_stalls", "Commit_0_cyc", REGNO_ANY, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
 844
 845   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 846   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_6, 0, ABST_EXACT},
 847   {"dcm", "DC_miss_commit", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_EXACT},
 848
 849   {"l3m_spec", "DC_miss_L3_miss", REGNO_ANY, STXT ("L3 D-cache Speculative Misses"), PRELOADS_5, 0, ABST_NONE},
 850   {"lmh_spec", "DC_miss_local_mem_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 851   {"rmh_spec", "DC_miss_remote_mem_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 852   //
 853   {"dtlbm", "DTLB_HWTW_search", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_55, 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap  0.001 events/cycle
 854   {"dtlb_hwtw_stalls", "DTLB_HWTW_ref", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOADS_55, 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50
 855   {"dtlb_trap_stalls", "DTLB_HWTW_miss_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOADS_35, 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap
 856   {"rawhaz", "RAW_hit_st_q~emask=0xf", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOADS_55, 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")},
 857   {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOADS_6, 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad
 858   {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE},
 859   {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE},
 860   {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE},
 861   {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE},
 862   {"spill_fill", "Flush_arch_exception", REGNO_ANY, STXT ("Reg Window Spill/Fill Est Stalls"), PRELOAD (100, 4), 80, ABST_NONE, STXT ("Estimated time stalled on flushing pipeline due to register window spill/fill")},
 863
 864   /* explicit definitions of (hidden) entries for proper counters */
 865   /*  Counters that can be time converted, support memspace, or have a short_desc need to be in this table */
 866   {"Sel_pipe_drain_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")},
 867   {"Sel_0_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved")},
 868   {"Sel_0_ready_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")},
 869   {"Sel_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that only 1 instruction or uop was selected")},
 870   {"Sel_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles that 2 instructions or uops were selected")},
 871
 872   {"Pick_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 873   {"Pick_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 874   {"Pick_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 875   {"Pick_3_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 876   {"Pick_any_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 877
 878   {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")},
 879   {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")},
 880   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")},
 881   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")},
 882   {"Instr_SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")},
 883   {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 4), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")},
 884   {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 0, ABST_NONE, STXT ("Total instructions completed")},
 885
 886   {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")},
 887   {"Instr_SW_count", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("SW Count instructions completed")},
 888   {"Instr_atomic", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")},
 889   {"Instr_SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")},
 890   {"Instr_block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_EXACT, STXT ("Block load/store instructions completed")},
 891
 892   {"Br_BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")},
 893
 894   {"ITLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")},
 895   {"ITLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")},
 896   {"ITLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")},
 897   {"ITLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")},
 898   {"ITLB_HWTW_hit_2G_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 899   {"ITLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")},
 900   {"ITLB_HWTW_search", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")},
 901
 902   {"Fetch_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 903   {"Fetch_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 904
 905   {"Instr_buffer_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 906
 907   {"PQ_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 908   {"ROB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 909   {"LB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 910   {"SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 911   {"ROB_LB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 912   {"ROB_SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 913   {"LB_SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 914   {"ROB_LB_SB_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 915   {"DTLB_miss_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 916
 917   {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")},
 918   {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 919   {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")},
 920   {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")},
 921   {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")},
 922   {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")},
 923   {"DTLB_HWTW_ref", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")},
 924
 925   {"DC_miss_L2_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT},
 926   {"DC_miss_nbr_scc_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_EXACT},
 927   {"DC_miss_nbr_scc_miss_commit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_EXACT},
 928   {"DC_miss_commit", NULL, REGNO_ANY, NULL, PRELOAD (25, 4), 0, ABST_EXACT, STXT ("Loads that missed local L1D")},
 929
 930   {"DTLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")},
 931   {"DTLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")},
 932   {"DTLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")},
 933   {"DTLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")},
 934   {"DTLB_HWTW_hit_2G_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 2G or 16G page")},
 935   {"DTLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")},
 936   {"DTLB_HWTW_search", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")},
 937   {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")},
 938   {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")},
 939
 940   {"St_q_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
 941
 942   {"St_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")},
 943   {"St_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")},
 944
 945   {"DC_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Loads that speculatively hit local L1D")},
 946   {"DC_miss_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D")},
 947   {"DC_miss_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local L3")},
 948   {"DC_miss_nbr_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit neighbor L2D via local L3")},
 949   {"DC_miss_nbr_scc_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit neighbor L3 on same socket")},
 950   {"DC_miss_nbr_scc_miss", NULL, REGNO_ANY, NULL, PRELOAD (400, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed all caches on same socket")},
 951   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (10, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed local L1D")},
 952   {"DC_miss_L2_miss", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed local L2D")},
 953   {"DC_miss_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (200, 4), 0, ABST_NONE, STXT ("Loads that speculatively missed local L3")},
 954
 955   {"DC_miss_remote_scc_hit", NULL, REGNO_ANY, NULL, PRELOAD (800, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache on different socket")},
 956   {"DC_miss_local_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")},
 957   {"DC_miss_remote_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (1000, 4), 0, ABST_NONE, STXT ("Loads that speculatively hit remote memory")},
 958   {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")},
 959   {"Br_tgt_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")},
 960   {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")},
 961
 962   {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 4), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")},
 963
 964   {"Flush_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to a load that misses L3 when more than 1 hardware thread is active on the core")},
 965   {"Flush_br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to a branch misprediction")},
 966   {"Flush_arch_exception", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to SPARC architecture exceptions and trap entry/return")},
 967   {"Flush_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 4), 0, ABST_NONE, STXT ("Pipeline flushes due to hardware thread state change to/from halted/paused state")},
 968   //
 969   {"Commit_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")},
 970   {"Commit_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")},
 971   {"Commit_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 uop commits from this hardware thread")},
 972   {"Commit_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 2 uops commit from this hardware thread")},
 973   {"Commit_1_or_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles 1 or 2 uops commit from this hardware thread")},
 974
 975
 976   /* additional (hidden) aliases, for convenience */
 977   {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE},
 978   {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE},
 979   {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE},
 980   {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE},
 981   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
 982 };
 983
 984 static Hwcentry sparc_m8[] = {
 985   // current aliases
 986   SPARC_CYCLES
 987   {"cycles", "Cycles_user", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
 988   {"insts", "Instr_all", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
 989   {"c_stalls", "Commit_0_cyc", 3, STXT ("Stall Cycles"), PRELOADS_7, 1, ABST_NONE}, // 22825776: limit to reg 3
 990   {"Sel_0_wait_cyc", "Sel_0_cyc~emask=0x3f", REGNO_ANY, STXT ("Select Stall Cycles"), PRELOADS_7, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for various conditions to be resolved that prevent it being selected")},
 991
 992   {"loads", "Instr_ld", REGNO_ANY, STXT ("Load Instructions"), PRELOADS_7, 0, ABST_EXACT},
 993   {"stores", "Instr_st", REGNO_ANY, STXT ("Store Instructions"), PRELOADS_6, 0, ABST_EXACT},
 994   {"dcm", "DC_miss_commit", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_EXACT},
 995
 996   {"lmh_spec", "DC_miss_local_mem_hit", REGNO_ANY, STXT ("Local Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 997   {"rmh_spec", "DC_miss_remote_mem_hit", REGNO_ANY, STXT ("Remote Mem Speculative Hits"), PRELOADS_5, 0, ABST_NONE},
 998
 999   {"dtlbm", "DTLB_HWTW", REGNO_ANY, STXT ("DTLB Misses"), PRELOAD (40, 5), 0, ABST_NONE}, // 10@l1 hit, 24@l2 hit, 60@l3 hit, 500@l3 miss, 5000@trap  0.001 events/cycle
1000   {"dtlb_hwtw_stalls", "DTLB_HWTW", REGNO_ANY, STXT ("DTLB HWTW Est Stalls"), PRELOAD (40, 5), 25, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss requiring a HW tablewalk")}, // l2-20, l3-50
1001   {"dtlb_trap_stalls", "DTLB_HWTW_miss_trap", REGNO_ANY, STXT ("DTLB Trap Est Stalls"), PRELOAD (800, 5), 5000, ABST_NONE, STXT ("Estimated time stalled on a DTLB miss with HW tablewalk unsuccessful")}, // 5000@trap
1002   {"rawhaz", "RAW_hit", REGNO_ANY, STXT ("Read-after-write Hazards"), PRELOAD (40, 5), 0, ABST_NONE},
1003   {"br_msp_stalls", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict Stalls"), PRELOAD (40, 5), 24, ABST_NONE, STXT ("Estimated time stalled on Branch mispredictions")}, // 24@miss, %5 of branches is bad
1004   {"br_msp", "Br_mispred", REGNO_ANY, STXT ("Branch Mispredict"), PRELOAD (40, 5), 0, ABST_NONE},
1005   {"br_tkn", "Br_taken", REGNO_ANY, STXT ("Branch Taken"), PRELOADS_7, 0, ABST_NONE},
1006   {"br_ins", "Branches", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE},
1007   {"fgu", "Instr_FGU_crypto", REGNO_ANY, STXT ("FP/VIS/Crypto Instructions"), PRELOADS_7, 0, ABST_NONE},
1008   {"spill_fill", "Flush_spill_fill", REGNO_ANY, STXT ("Reg Window Spill/Fill Est Stalls"), PRELOAD (100, 5), 80, ABST_NONE, STXT ("Estimated time stalled on flushing pipeline due to register window spill/fill")},
1009
1010   /* explicit definitions of (hidden) entries for proper counters */
1011   /*  Counters that can be time converted, support memspace, or have a short_desc need to be in this table */
1012   //0x01
1013   {"Fetch_stall_IFU_reset_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1014   {"Fetch_stall_IC_miss_MB_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1015   {"Fetch_stall_IC_miss_MB_avail_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1016   {"Fetch_stall_IC_miss_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1017   {"Fetch_stall_ITLB_miss_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1018   {"Fetch_stall_SEL_buf_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1019   {"Fetch_ready_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1020   {"Fetch_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1021   {"Fetch_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1022   //0x02
1023   {"Fetch_1_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1024   {"Fetch_2_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1025   {"Fetch_3_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1026   {"Fetch_4_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1027   {"Fetch_5_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1028   {"Fetch_6_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1029   {"Fetch_7_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1030   {"Fetch_8_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1031   {"Fetch_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1032   //0x07
1033   {"ITLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 8K page")},
1034   {"ITLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 64K page")},
1035   {"ITLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 4M page")},
1036   {"ITLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 256M page")},
1037   {"ITLB_HWTW_hit_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 16G page")},
1038   {"ITLB_HWTW_hit_1T", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk successfully loaded translation for 1T page")},
1039   //  { "ITLB_HWTW_miss_RA2PAC",                0x0740, 0xf07ff },
1040   //  { "ITLB_HWTW_miss_not_RA2PAC",            0x0780, 0xf07ff },
1041   {"ITLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (1000, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk unsuccessful")},
1042   {"ITLB_HWTW", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk search done")},
1043   //0x08
1044   {"Br_BTC_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branches delayed a few extra cycles because branch target not found in Branch Target Cache")},
1045   //0x09
1046   {"Sel_0_no_instr_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select because no instructions are available")},
1047   {"Sel_0_pipe_drain_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting with correct instructions when pipeline has to drain after branch misprediction")},
1048   {"Sel_0_postsync_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select waiting for prior instructions to commit")},
1049   {"Sel_0_presync_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select with instruction that cannot decode until prior instructions have committed")},
1050   {"Sel_0_thread_hog_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select to prevent strand monopolizing resources")},
1051   {"Sel_0_tag_stall_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread stalls at Select because no required tags are available")},
1052   {"Sel_0_ready_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread was ready to have its instructions selected but another hardware thread was selected instead")},
1053   {"Sel_0_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles a hardware thread is not selected")},
1054   // No direct equivalent Sel_1/2_cyc. Nearest is Decode_uop, which increments by 0-4 each cycle according to how many uops were decoded.
1055   //0x13
1056   {"ITLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L2D")},
1057   {"ITLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk hit local L3 or neighbor L2D")},
1058   {"ITLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 5), 0, ABST_NONE, STXT ("ITLB miss and HW tablewalk missed all local caches")},
1059   {"DTLB_HWTW_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L2D")},
1060   {"DTLB_HWTW_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (80, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk hit local L3 or neighbor L2D")},
1061   {"DTLB_HWTW_L3_miss", NULL, REGNO_ANY, NULL, PRELOAD (800, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk missed all local caches")},
1062   {"DTLB_HWTW_ref", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss requiring HW tablewalk")},
1063   //0x0E
1064   {"Instr_FGU_crypto", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("FP and VIS instructions completed by the Floating Point and Graphics Unit")},
1065   {"Instr_ld", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Load instructions completed")},
1066   {"Instr_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Store instructions completed")},
1067   {"Instr_block_ld_st", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_EXACT, STXT ("Block load/store instructions completed")},
1068   {"Instr_SPR_ring_ops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("Specialized instructions that require internal use of SPR ring completed")},
1069   {"Instr_atomic", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_EXACT, STXT ("Atomic instructions, including CASA/XA, completed")},
1070   {"Instr_SW_prefetch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT, STXT ("PREFETCH and PREFETCHA instructions completed")},
1071   {"Instr_other", NULL, REGNO_ANY, NULL, PRELOAD (2, 5), 0, ABST_NONE, STXT ("Basic arithmetic and logical instructions completed")},
1072   {"Instr_all", NULL, REGNO_ANY, NULL, PRELOAD (1, 5), 0, ABST_NONE, STXT ("Total instructions completed")},
1073   //0x0F
1074   {"Branches", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Control transfer instructions completed, excluding trap-related transfers")},
1075   //0x10
1076   {"Br_taken", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Branch instructions taken and completed")},
1077   //0x11
1078   {"Rename_tag_wait_PQ_1_EXU_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1079   {"Rename_tag_wait_PQ_0_LSU_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1080   {"Rename_wait_crypto_diag_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1081   {"Sel_0_wait_ROB_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1082   {"Sel_0_wait_WRF_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1083   {"Sel_0_wait_LB_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1084   {"Sel_0_wait_SB_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1085   //0x12
1086   {"Fetch_stall_BDA_tag_unavail_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1087   {"Fetch_stall_BTA_tag_unavail_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1088   {"Fetch_stall_misc_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1089   {"Fetch_stall_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1090   {"MMU_TTE_buffer_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1091   {"MMU_PRQ_pool_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1092   //0x15
1093   {"L2I_request_block_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1094   {"L2I_thread_hog_stall_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1095   {"L2I_MB_full_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1096   {"L2I_snoop_eviction", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1097   {"L2I_stall_no_request_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1098   {"L2I_stall_no_response_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1099   //0x16
1100   {"Flush_thread_hog", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes to prevent thread from monopolizing resources")},
1101   {"Flush_br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to a branch misprediction")},
1102   {"Flush_arch_exception", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to SPARC architecture exceptions and trap entry/return")},
1103   {"Flush_evil_twin", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to detecting floating point evil twin condition")},
1104   {"Flush_LSU_trap", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes to refetch Next-PC")},
1105   {"Flush_mode_change", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to strand mode change")},
1106   {"Flush_misalign", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to detecting misaligned load/store requiring transition to misaligned mitigation mode")},
1107   {"Flush_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to hardware thread state change to/from halted/paused state")},
1108   {"Flush_all", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to any reason")},
1109   //0x17
1110   {"Flush_spill_n_normal", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to spill_n_normal exception")},
1111   {"Flush_spill_n_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to spill_n_other exception")},
1112   {"Flush_fill_n_normal", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to fill_n_normal exception")},
1113   {"Flush_fill_n_other", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to fill_n_other exception")},
1114   {"Flush_spill_fill", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to spill/fill exceptions")},
1115   {"Flush_lost_load", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Pipeline flushes due to speculatively executed load violating memory order")},
1116   //0x21
1117   {"Br_dir_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Branch instructions completed whose direction was mispredicted")},
1118   {"Br_tgt_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Branch instructions completed whose target was mispredicted")},
1119   {"Br_mispred", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Branch instructions completed whose direction or target was mispredicted")},
1120   //0x23
1121   {"LSU_st_q_tag_wait_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1122   {"LSU_st_q_tag_wait_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1123   {"L2D_stall_no_request_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1124   {"L2D_stall_no_response_credit_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1125   //0x27
1126   {"DC_miss_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local L2D")},
1127   {"DC_miss_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local L3")},
1128   {"DC_miss_L3_dirty_copyback", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local L3 but require copyback from L2D within same CPC")},
1129   {"DC_miss_nbr_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit neighbor L3 on same socket")},
1130   {"DC_miss_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (400, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit remote cache on different socket")},
1131   {"DC_miss_local_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit local memory")},
1132   {"DC_miss_remote_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (1000, 5), 0, ABST_NONE, STXT ("Loads that speculatively hit remote memory")},
1133   {"DC_miss", NULL, REGNO_ANY, NULL, PRELOAD (10, 5), 0, ABST_NONE, STXT ("Loads that speculatively missed local L1D")},
1134   //0x28
1135   {"DC_sec_miss_L2_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1136   {"DC_miss_L2_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1137   {"DC_miss_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1138   {"DC_miss_L3_dirty_copyback_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1139   {"DC_miss_nbr_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1140   {"DC_miss_remote_L3_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1141   {"DC_miss_local_mem_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1142   {"DC_miss_remote_mem_hit_commit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_EXACT},
1143   {"DC_miss_commit", NULL, REGNO_ANY, NULL, PRELOAD (25, 5), 0, ABST_EXACT, STXT ("Loads that missed local L1D")},
1144   //0x29
1145   //  {"Store_DC_sec_miss_L2_hit",       NULL, REGNO_ANY, NULL, PRELOAD_DEF,     0, ABST_NONE,  STXT("")},
1146   {"Store_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (20, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L2D")},
1147   {"Store_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local L3")},
1148   {"Store_nbr_L2_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in neighbor L2 on same socket")},
1149   {"Store_nbr_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (100, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in neighbor L3 on same socket")},
1150   {"Store_remote_L3_hit", NULL, REGNO_ANY, NULL, PRELOAD (400, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in remote cache on different socket")},
1151   {"Store_local_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (500, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in local memory")},
1152   {"Store_remote_mem_hit", NULL, REGNO_ANY, NULL, PRELOAD (1000, 5), 0, ABST_NONE, STXT ("Stores whose cacheline being updated was in remote memory")},
1153   {"Store_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE, STXT ("Stores whose cacheline being updated was observed to be somewhere in the memory hierarchy")},
1154   //0x2d
1155   {"RAW_hit_st_buf", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) still in store buffer not yet committed")},
1156   {"RAW_hit_st_q", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write) committed but in store queue not yet written to L2D")},
1157   {"RAW_hit", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("Loads delayed by a previous store (read-after-write hazards)")},
1158   //0x2f
1159   {"Cycles_user_non_MLA", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1160   {"Cycles_user_MLA", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1161   {"Cycles_user", NULL, REGNO_ANY, NULL, PRELOAD (1, 5), 1, ABST_NONE, STXT ("Cycles hardware thread is active in specified mode(s)")},
1162   //0x37
1163   {"DTLB_HWTW_hit_8K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 8K page")},
1164   {"DTLB_HWTW_hit_64K", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 64K page")},
1165   {"DTLB_HWTW_hit_4M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 4M page")},
1166   {"DTLB_HWTW_hit_256M", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 256M page")},
1167   {"DTLB_HWTW_hit_16G", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 16G page")},
1168   {"DTLB_HWTW_hit_1T", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk successfully loaded translation for 1T page")},
1169   {"DTLB_HWTW_miss_trap", NULL, REGNO_ANY, NULL, PRELOAD (800, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk unsuccessful")},
1170   {"DTLB_HWTW", NULL, REGNO_ANY, NULL, PRELOAD (40, 5), 0, ABST_NONE, STXT ("DTLB miss and HW tablewalk search done")},
1171   //0x3f
1172   {"Commit_0_cyc", /*22825776*/ NULL, 3, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from this hardware thread")},
1173   {"Commit_0_all_cyc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE, STXT ("Cycles no uop commits from any hardware thread on this core")},
1174   // Similar situation to Sel_1_cyc etc. No direct equivalent, nearest is Commit_uop, which increments by 0-4 each cycle according to how many uops were committed.
1175
1176   /* additional (hidden) aliases, for convenience */
1177   {"cycles0", "Cycles_user", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1178   {"cycles1", "Cycles_user", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1179   {"insts0", "Instr_all", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1180   {"insts1", "Instr_all", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1181   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1182 };
1183
1184 static Hwcentry usfuji_V_list[] = {
1185   {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
1186   {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
1187   {"flops", "floating_instructions", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_6, 0, ABST_NONE},
1188
1189   /* explicit definitions of (hidden) entries for proper counters */
1190   /*  Only counters that can be time converted, or are load-store need to be in this table */
1191   {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
1192   {"load_store_instructions", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1193
1194   /* additional (hidden) aliases for convenience */
1195   {"cycles0", "cycle_counts", 0, NULL, PRELOADS_75, 1, ABST_NONE},
1196   {"cycles1", "cycle_counts", 1, NULL, PRELOADS_75, 1, ABST_NONE},
1197   {"insts0", "instruction_counts", 0, NULL, PRELOADS_75, 0, ABST_NONE},
1198   {"insts1", "instruction_counts", 1, NULL, PRELOADS_75, 0, ABST_NONE},
1199   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1200 };
1201
1202 static Hwcentry usfuji_VI_VII_list[] = {
1203   {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1204   {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1205   {"dcm", "op_r_iu_req_mi_go", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_6, 0, ABST_NONE},
1206   {"dcstall", "op_wait_all", REGNO_ANY, STXT ("L1 D-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1207   {"dtlbm", "write_op_uTLB", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_5, 0, ABST_NONE},
1208   // l2m: mem_cache_load test shows undercount of 3x, however, we don't care too much about this chip, keeping the alias for now
1209   {"l2m", "sx_miss_count_dm", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_5, 0, ABST_NONE}, /*YXXX undercounts?*/
1210   {"l2wm", "dvp_count_dm", REGNO_ANY, STXT ("L2 Cache Writeback Misses"), PRELOADS_5, 0, ABST_NONE},
1211   {"l2ref", "sx_read_count_dm", REGNO_ANY, STXT ("L2 Cache Refs"), PRELOADS_6, 0, ABST_NONE},
1212   {"l2stall", "sx_miss_wait_dm", REGNO_ANY, STXT ("L2 Cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1213   {"icm", "if_r_iu_req_mi_go", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_6, 0, ABST_NONE},
1214   {"icstall", "if_wait_all", REGNO_ANY, STXT ("L1 I-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1215   {"itlbm", "write_if_uTLB", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
1216   {"flops", "floating_instructions", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_7, 0, ABST_NONE},
1217
1218   /* explicit definitions of (hidden) entries for proper counters */
1219   /*  Only counters that can be time converted, or are load-store need to be in this table */
1220   {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1221   {"op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1222   {"load_store_instructions", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1223   {"active_cycle_count", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1224   {"op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1225   {"branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1226   {"write_op_uTLB", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1227   {"sx_miss_wait_pf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1228   {"sx_miss_wait_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1229   {"op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1230   {"op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1231   {"eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1232   {"sx_miss_count_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1233   {"fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1234   {"op_r_iu_req_mi_go", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1235   {"sx_miss_count_dm_if", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1236   {"op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1237   {"swpf_lbs_hit", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1238   {"sx_read_count_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1239   {"trap_DMMU_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1240   {"op_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1241   {"sx_miss_count_dm_opex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1242   {"if_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1243   {"dvp_count_dm", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1244   {"sx_miss_count_dm_opsh", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 0, ABST_NONE},
1245
1246   /* additional (hidden) aliases for convenience */
1247   {"cycles0", "cycle_counts", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1248   {"cycles1", "cycle_counts", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1249   {"insts0", "instruction_counts", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1250   {"insts1", "instruction_counts", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1251   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1252 };
1253
1254
1255 static Hwcentry usfuji_X_list[] = {
1256   {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1257   {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1258   {"dcm", "L1D_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
1259   {"dcstall", "L1D_wait_all", REGNO_ANY, STXT ("L1 D-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1260
1261   /* explicit definitions of (hidden) entries for proper counters */
1262   /*  Only counters that can be time converted, or are load-store need to be in this table */
1263   {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1264   {"w_op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1265   {"op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1266   {"eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1267   {"L2_miss_wait_pf_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1268   {"op_stv_wait_pfp_busy_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1269   {"L2_miss_wait_dm_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1270   {"w_branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1271   {"w_op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1272   {"op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1273   {"L2_miss_wait_pf_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1274   {"w_eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1275   {"w_op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1276   {"op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1277   {"branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1278   {"L2_miss_wait_dm_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1279   {"d_move_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1280   {"w_op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1281   {"w_fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1282   {"op_stv_wait_pfp_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1283   {"fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1284   {"L2_miss_wait_pf_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1285   {"op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1286   {"L2_miss_wait_dm_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1287   {"w_op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1288   {"op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1289   {"op_stv_wait_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1290   {"L1D_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1291   {"L2_miss_wait_pf_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1292   {"cse_priority_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1293   {"op_stv_wait_pfp_busy_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1294   {"L1I_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1295   {"L2_miss_wait_dm_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1296
1297   {"single_mode_cycle_counts", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1298   {"suspend_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1299   {"sleep_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1300
1301   /* additional (hidden) aliases for convenience */
1302   {"cycles0", "cycle_counts", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1303   {"cycles1", "cycle_counts", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1304   {"insts0", "instruction_counts", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1305   {"insts1", "instruction_counts", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1306   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1307 };
1308
1309 static Hwcentry usfuji_XII_list[] = {
1310   {"cycles", "cycle_counts", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1311   {"insts", "instruction_counts", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1312   {"dcm", "L1D_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
1313   {"dcstall", "L1D_wait_all", REGNO_ANY, STXT ("L1 D-cache Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
1314
1315   /* explicit definitions of (hidden) entries for proper counters */
1316   /*  Only counters that can be time converted, or are load-store need to be in this table */
1317   {"cycle_counts", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1318   {"L1D_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1319   {"L1I_wait_all", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1320   {"L2_miss_wait_dm_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1321   {"L2_miss_wait_dm_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1322   {"L2_miss_wait_dm_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1323   {"L2_miss_wait_dm_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1324   {"L2_miss_wait_pf_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1325   {"L2_miss_wait_pf_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1326   {"L2_miss_wait_pf_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1327   {"L2_miss_wait_pf_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1328   {"LL_miss_wait_dm_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1329   {"LL_miss_wait_dm_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1330   {"LL_miss_wait_dm_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1331   {"LL_miss_wait_dm_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1332   {"LL_miss_wait_pf_bank0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1333   {"LL_miss_wait_pf_bank1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1334   {"LL_miss_wait_pf_bank2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1335   {"LL_miss_wait_pf_bank3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1336   {"branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1337   {"cse_priority_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1338   {"d_move_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1339   {"eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1340   {"fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1341   {"l2_sy_miss_wait_dm_part1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1342   {"l2_sy_miss_wait_dm_part2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1343   {"msgr_reqp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1344   {"msgr_rtnp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1345   {"msgs_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1346   {"op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1347   {"op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1348   {"op_stv_wait_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1349   {"op_stv_wait_l1d_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1350   {"op_stv_wait_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1351   {"op_stv_wait_l2_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1352   {"op_stv_wait_ll_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1353   {"op_stv_wait_ll_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1354   {"op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1355   {"op_stv_wait_pfp_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1356   {"op_stv_wait_pfp_busy_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1357   {"op_stv_wait_pfp_busy_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1358   {"op_stv_wait_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1359   {"op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1360   {"op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1361   {"w_branch_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1362   {"w_eu_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1363   {"w_fl_comp_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1364   {"w_op_stv_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1365   {"w_op_stv_wait_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1366   {"w_op_stv_wait_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1367   {"w_op_stv_wait_l1d_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1368   {"w_op_stv_wait_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1369   {"w_op_stv_wait_l2_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1370   {"w_op_stv_wait_ll_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1371   {"w_op_stv_wait_ll_miss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1372   {"w_op_stv_wait_nc_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1373   {"w_op_stv_wait_pfp_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1374   {"w_op_stv_wait_pfp_busy_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1375   {"w_op_stv_wait_pfp_busy_swpf", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1376   {"w_op_stv_wait_sxmiss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1377   {"w_op_stv_wait_sxmiss_ex", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1378
1379   {"single_mode_cycle_counts", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1380   {"suspend_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1381   {"sleep_cycle", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1382
1383   /* additional (hidden) aliases for convenience */
1384   {"cycles0", "cycle_counts", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1385   {"cycles1", "cycle_counts", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1386   {"insts0", "instruction_counts", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1387   {"insts1", "instruction_counts", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1388   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1389 };
1390
1391 /* Kernel profiling pseudo-chip, OBSOLETE (To support 12.3 and earlier, TBR) */
1392 static Hwcentry kproflist[] = {
1393   {"kcycles", "kcycles", 0, STXT ("KCPU Cycles"), PRELOADS_5, 1, ABST_NONE},
1394   {"kucycles", "kucycles", 0, STXT ("KUCPU Cycles"), PRELOADS_5, 1, ABST_NONE},
1395   {"kthr", "kthr", 0, STXT ("KTHR Cycles"), PRELOADS_5, 1, ABST_NONE},
1396   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1397 };
1398
1399 static Hwcentry pentiumIIlist[] = {
1400   /*  note -- missing entries for dtlbm, ecm */
1401   {"cycles", "cpu_clk_unhalted", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
1402   {"insts", "inst_retired", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
1403   {"icm", "ifu_ifetch_miss", REGNO_ANY, STXT ("I$ Misses"), PRELOADS_5, 0, ABST_NONE},
1404   {"dcrm", "dcu_m_lines_in", REGNO_ANY, STXT ("D$ Read Misses"), PRELOADS_5, 0, ABST_NONE},
1405   {"dcwm", "dcu_m_lines_out", REGNO_ANY, STXT ("D$ Write Misses"), PRELOADS_5, 0, ABST_NONE},
1406   {"flops", "flops", REGNO_ANY, STXT ("Floating-point Ops"), PRELOADS_7, 0, ABST_NONE},
1407   {"itlbm", "itlb_miss", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_5, 0, ABST_NONE},
1408   {"ecim", "l2_ifetch", REGNO_ANY, STXT ("E$ Instr. Misses"), PRELOADS_5, 0, ABST_NONE},
1409
1410   /* explicit definitions of (hidden) entries for proper counters */
1411   /*  Only counters that can be time converted, or are load-store need to be in this table */
1412   {"cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
1413
1414   /* additional (hidden) aliases for convenience */
1415   {"cycles0", "cpu_clk_unhalted", 0, NULL, PRELOADS_75, 1, ABST_NONE},
1416   {"cycles1", "cpu_clk_unhalted", 1, NULL, PRELOADS_75, 1, ABST_NONE},
1417   {"insts0", "inst_retired", 0, NULL, PRELOADS_75, 0, ABST_NONE},
1418   {"insts1", "inst_retired", 1, NULL, PRELOADS_75, 0, ABST_NONE},
1419   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1420 };
1421
1422 static Hwcentry pentiumIIIlist[] = {
1423   /*  note -- many missing entries; no reference machine to try */
1424   {"cycles", "cpu_clk_unhalted", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
1425   {"insts", "inst_retired", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
1426
1427   /* explicit definitions of (hidden) entries for proper counters */
1428   /*  Only counters that can be time converted, or are load-store need to be in this table */
1429   {"cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
1430
1431   /* additional (hidden) aliases for convenience */
1432   {"cycles0", "cpu_clk_unhalted", 0, NULL, PRELOADS_75, 1, ABST_NONE},
1433   {"cycles1", "cpu_clk_unhalted", 1, NULL, PRELOADS_75, 1, ABST_NONE},
1434   {"insts0", "inst_retired", 0, NULL, PRELOADS_75, 0, ABST_NONE},
1435   {"insts1", "inst_retired", 1, NULL, PRELOADS_75, 0, ABST_NONE},
1436   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1437 };
1438
1439 static Hwcentry pentium4[] = {
1440   {"cycles", "TC_deliver_mode~threshold=0xf~complement=1~compare=1", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
1441   {"insts", "instr_retired~emask=0x3", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
1442   {"l1m", "BSQ_cache_reference~emask=0x0507", REGNO_ANY, STXT ("L1 Cache Misses"), PRELOADS_7, 0, ABST_NONE},
1443   {"l2h", "BSQ_cache_reference~emask=0x0007", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_7, 0, ABST_NONE},
1444   {"l2m", "BSQ_cache_reference~emask=0x0500", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE},
1445
1446   /* explicit definitions of (hidden) entries for proper counters */
1447   /*  Only counters that can be time converted, or are load-store need to be in this table */
1448   {"TC_deliver_mode", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1449   {"machine_clear", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1450
1451   /* additional (hidden) aliases, for convenience */
1452   {"cycles0", "TC_deliver_mode~threshold=0xf~complement=1~compare=1", 5, NULL, PRELOADS_75, 1, ABST_NONE},
1453   {"cycles1", "TC_deliver_mode~threshold=0xf~complement=1~compare=1", 6, NULL, PRELOADS_75, 1, ABST_NONE},
1454   {"insts0", "instr_retired~emask=0x3", 15, NULL, PRELOADS_75, 0, ABST_NONE},
1455   {"insts1", "instr_retired~emask=0x3", 16, NULL, PRELOADS_75, 0, ABST_NONE},
1456   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1457 };
1458
1459 static Hwcentry intelCore2list[] = {
1460   // For post-processing, both Linux and Solaris definitions need to be "live".
1461   // However, for data collection, OS-specific definitions may need to be hidden.
1462   // Use REGNO_INVALID for definitions that should be hidden for data collection.
1463 #define LINUX_ONLY   REGNO_ANY
1464 #define SOLARIS_ONLY REGNO_INVALID /* hidden for Linux data collection */
1465
1466   {"cycles", "cpu_clk_unhalted.core", /*6759307*/ SOLARIS_ONLY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1467   {"cycles", "cpu_clk_unhalted.thread", /*6759307*/ SOLARIS_ONLY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1468   /* Linux Note: 7046312 Many HWC tests fail on system Core2 system with perf_events if above alias used */
1469   {"cycles", "cpu_clk_unhalted", LINUX_ONLY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1470
1471   {"insts", "instr_retired.any", SOLARIS_ONLY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1472   /* Linux Note: 7046312 Many HWC tests fail on system Core2 system with perf_events if above alias used */
1473   {"insts", "inst_retired", LINUX_ONLY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1474
1475   // The following counters were identified in "Cycle Accounting Analysis on Intel Core2 Processors" by David Levinthal
1476   {"uops_stalled", "rs_uops_dispatched~cmask=1~inv=1", REGNO_ANY, STXT ("uOps Stalled"), PRELOADS_7, 1, ABST_NONE},
1477   {"l2m", "mem_load_retired~umask=0x08", REGNO_ANY, STXT ("L2 Line Misses"), PRELOADS_5, 0, ABST_NONE},
1478   {"dtlbm", "mem_load_retired~umask=0x10", REGNO_ANY, STXT ("L1 DTLB Misses"), PRELOADS_5, 0, ABST_NONE},
1479   {"l1m", "mem_load_retired~umask=0x02", REGNO_ANY, STXT ("L1 Line Misses"), PRELOADS_6, 0, ABST_NONE},
1480   // {"stalls_resources","resource_stalls~umask=0x1f",          REGNO_ANY, STXT("Resource Stalls"),             PRELOADS_6, 1, ABST_NONE},
1481   {"rs_full", "resource_stalls~umask=0x02", REGNO_ANY, STXT ("Reservation Station Full"), PRELOADS_6, 1, ABST_NONE},
1482   {"br_miss_flush", "resource_stalls~umask=0x10", REGNO_ANY, STXT ("Mispredicted Branch Flushes"), PRELOADS_6, 1, ABST_NONE},
1483   {"ld_st_full", "resource_stalls~umask=0x04", REGNO_ANY, STXT ("Load/Store Buffers Full"), PRELOADS_6, 1, ABST_NONE},
1484   {"rob_full", "resource_stalls~umask=0x01", REGNO_ANY, STXT ("Reorder Buffer Full"), PRELOADS_6, 1, ABST_NONE},
1485   {"slow_decode", "ild_stall", REGNO_ANY, STXT ("Slow Instruction Decode"), PRELOADS_6, 1, ABST_NONE},
1486   {"br_miss", "br_cnd_missp_exec", REGNO_ANY, STXT ("Mispredicted Branches"), PRELOADS_5, 0, ABST_NONE},
1487   {"ret_miss", "br_call_missp_exec", REGNO_ANY, STXT ("Mispredicted Return Calls"), PRELOADS_5, 0, ABST_NONE},
1488   {"div_busy", "idle_during_div", REGNO_ANY, STXT ("Divider Unit Busy"), PRELOADS_5, 1, ABST_NONE},
1489   {"fp_assists", "fp_assist", REGNO_ANY, STXT ("FP Microcode Assists"), PRELOADS_5, 0, ABST_NONE},
1490   {"bus_busy", "bus_drdy_clocks~umask=0x60", REGNO_ANY, STXT ("Busy Data Bus"), PRELOADS_5, 1, ABST_NONE},
1491
1492   /* explicit definitions of (hidden) entries for proper counters */
1493   /*  Only counters that can be time converted, or are load-store need to be in this table */
1494   {/*30a*/"cpu_clk_unhalted.core", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1495   {/*30a*/"cpu_clk_unhalted.thread", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1496   {/*03*/"store_block", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1497   {/*03*/"store_block.drain_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1498   {/*03*/"store_block.order", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1499   {/*03*/"store_block.snoop", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1500   {/*09*/"memory_disambiguation.reset", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1501   {/*0c*/"page_walks.cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1502   {/*14*/"cycles_div_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1503   {/*18*/"idle_during_div", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1504   {/*19*/"delayed_bypass.load", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1505   {/*21*/"l2_ads", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1506   {/*23*/"l2_dbus_busy_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1507   {/*32*/"l2_no_req", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1508   {/*3c*/"cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1509   {/*3c*/"cpu_clk_unhalted.core_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1510   {/*3c*/"cpu_clk_unhalted.bus", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1511   {/*3c*/"cpu_clk_unhalted.no_other", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1512   {/*42*/"l1d_cache_lock.duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1513   {/*62*/"bus_drdy_clocks", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1514   {/*63*/"bus_lock_clocks", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1515   {/*64*/"bus_data_rcv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1516   {/*7a*/"bus_hit_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1517   {/*7b*/"bus_hitm_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1518   {/*7d*/"busq_empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1519   {/*7e*/"snoop_stall_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1520   {/*7f*/"bus_io_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1521   {/*83*/"inst_queue", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1522   {/*83*/"inst_queue.full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1523   {/*86*/"cycles_l1i_mem_stalled", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1524   {/*87*/"ild_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1525   {/*a1*/"rs_uops_dispatched", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1526   {/*a1*/"rs_uops_dispatched_port", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1527   {/*a1*/"rs_uops_dispatched_port.0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1528   {/*a1*/"rs_uops_dispatched_port.1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1529   {/*a1*/"rs_uops_dispatched_port.2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1530   {/*a1*/"rs_uops_dispatched_port.3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1531   {/*a1*/"rs_uops_dispatched_port.4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1532   {/*a1*/"rs_uops_dispatched_port.5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1533   {/*6c*/"cycles_int", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1534   {/*6c*/"cycles_int.masked", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1535   {/*6c*/"cycles_int.pending_and_masked", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1536   {/*d2*/"rat_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1537   {/*d2*/"rat_stalls.rob_read_port", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1538   {/*d2*/"rat_stalls.partial_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1539   {/*d2*/"rat_stalls.flags", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1540   {/*d2*/"rat_stalls.fpsw", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1541   {/*d2*/"rat_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1542   {/*d2*/"rat_stalls.other_serialization_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1543   {/*d4*/"seg_rename_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1544   {/*d4*/"seg_rename_stalls.es", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1545   {/*d4*/"seg_rename_stalls.ds", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1546   {/*d4*/"seg_rename_stalls.fs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1547   {/*d4*/"seg_rename_stalls.gs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1548   {/*d4*/"seg_rename_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1549   {/*dc*/"resource_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1550   {/*dc*/"resource_stalls.rob_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1551   {/*dc*/"resource_stalls.rs_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1552   {/*dc*/"resource_stalls.ld_st", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1553   {/*dc*/"resource_stalls.fpcw", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1554   {/*dc*/"resource_stalls.br_miss_clear", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1555   {/*dc*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1556   /* "Architectural" events: */
1557   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1558
1559   /* additional (hidden) aliases for convenience */
1560   {"cycles0", "cpu_clk_unhalted", 0, NULL, PRELOADS_8, 1, ABST_NONE},
1561   {"cycles1", "cpu_clk_unhalted", 1, NULL, PRELOADS_8, 1, ABST_NONE},
1562   {"insts0", "inst_retired", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1563   {"insts1", "inst_retired", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1564   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1565 };
1566
1567
1568 static Hwcentry intelNehalemList[] = {
1569   /* 6832635: on Linux, we're not seeing consistent overflows on FFCs */
1570   /* 15634344==6940930: HWC overflow profiling can cause system hang on Solaris/core-i7 systems */
1571   /* 17578620: counter overflow for fixed-function counters hangs systems */
1572   /* same issues for intelSandyBridgeList and intelHaswellList */
1573   PERF_EVENTS_SW_EVENT_ALIASES
1574   USE_INTEL_REF_CYCLES (133)
1575   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1576   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1577   // cpu_clk_unhalted.ref: at the ref requency of the cpu. Should not be affected by Speedstep or Turbo.
1578   // cpu_clk_unhalted.thread_p: with HT & 2 threads, 2x cycles.  Affected by Speedstep and Turbo.
1579
1580   // PEBs (Sampling)
1581   {"l2m_latency", "mem_inst_retired.latency_above_threshold", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 33, ABST_EXACT_PEBS_PLUS1},
1582
1583   // See file hwctable.README.corei7
1584   {"dch", "mem_load_retired.l1d_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
1585   {"dcm", "0xCB~umask=0x1e", REGNO_ANY, STXT ("L1 D-Cache Misses"), PRELOADS_65, 0, ABST_NONE}, /*mem_load_retired*/
1586   {"lfbdh", "mem_load_retired.hit_lfb", REGNO_ANY, STXT ("LFB D-cache Hits"), PRELOADS_65, 0, ABST_NONE},
1587   {"l2h", "mem_load_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
1588   {"l2m", "0xCB~umask=0x1c", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE}, /*mem_load_retired*/
1589   {"l3h", "mem_load_retired.llc_unshared_hit", REGNO_ANY, STXT ("L3 Cache Hit w/o Snoop"), PRELOADS_6, 0, ABST_NONE},
1590   {"l3h_stall", "mem_load_retired.llc_unshared_hit", REGNO_ANY, STXT ("L3 Cache Hit w/o Snoop x 35: Est. Stalls"), PRELOADS_6, 35, ABST_NONE},
1591   {"l3hsnoop", "mem_load_retired.other_core_l2_hit_hitm", REGNO_ANY, STXT ("L3 Cache Hit w/Snoop"), PRELOADS_6, 0, ABST_NONE},
1592   {"l3hsnoop_stall", "mem_load_retired.other_core_l2_hit_hitm", REGNO_ANY, STXT ("L3 Cache Hit w/Snoop x 74: Est. Stalls"), PRELOADS_6, 74, ABST_NONE},
1593   {"l3m", "mem_load_retired.llc_miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE},
1594   {"l3m_stall", "mem_load_retired.llc_miss", REGNO_ANY, STXT ("L3 Cache Misses x 180: Estimated Stalls"), PRELOADS_5, 180, ABST_NONE},
1595   {"dtlbm", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1596   {"dtlbm_stall", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses x 30: Estimated Stalls"), PRELOADS_6, 30, ABST_NONE},
1597   {"addr_alias_stall", "partial_address_alias", REGNO_ANY, STXT ("Partial Address Aliases x 3: Est. Stalls"), PRELOADS_6, 3, ABST_NONE},
1598   {"uope_stall", "uops_executed.port234~cmask=1~inv=1", REGNO_ANY, STXT ("UOP Execute Stalls per Core"), PRELOADS_7, 1, ABST_NONE},
1599   {"uopr_stall", "uops_retired.any~cmask=1~inv=1", REGNO_ANY, STXT ("UOP Retired Stalls"), PRELOADS_7, 1, ABST_NONE},
1600   {"itlbm", "itlb_miss_retired", REGNO_ANY, STXT ("ITLB Misses"), PRELOADS_6, 0, ABST_NONE},
1601   {"l1i_stall", "l1i.cycles_stalled", REGNO_ANY, STXT ("L1 I-cache Stalls"), PRELOADS_6, 1, ABST_NONE},
1602   {"br_rets", "br_inst_retired.all_branches", REGNO_ANY, STXT ("Branch Instruction Retires"), PRELOADS_7, 0, ABST_NONE},
1603   {"br_misp", "br_misp_exec.any", REGNO_ANY, STXT ("Branch Mispredicts"), PRELOADS_6, 0, ABST_NONE},
1604   {"mach_clear", "machine_clears.cycles", REGNO_ANY, STXT ("Machine Clear Asserted"), PRELOADS_6, 1, ABST_NONE},
1605   {"fp_mmx", "fp_mmx_trans.any", REGNO_ANY, STXT ("FP-MMX Transistions"), PRELOADS_6, 0, ABST_NONE},
1606   {"div_busy", "arith.cycles_div_busy", REGNO_ANY, STXT ("Divider Busy Cycles"), PRELOADS_6, 1, ABST_NONE},
1607
1608   /* explicit definitions of (hidden) entries for proper counters */
1609   /*  Only counters that can be time converted, or are load-store need to be in this table */
1610   {/*30a*/"cpu_clk_unhalted.core", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1611   {/*30a*/"cpu_clk_unhalted.thread", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1612   {/*04*/"sb_drain.cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1613   {/*08.04*/"dtlb_load_misses.walk_cycles", /*westmere*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1614   //{/*0e*/"uops_issued.stalled_cycles",/*future, multibit*/            NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1615   {/*09*/"memory_disambiguation.reset", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1616   {/*09*/"memory_disambiguation.watch_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1617   {/*0b*/"mem_inst_retired.latency_above_threshold", /*PEBS*/ NULL, REGNO_ANY, NULL, PRELOADS_4, 33, ABST_EXACT_PEBS_PLUS1}, //non-standard overflow
1618   {/*14*/"arith.cycles_div_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1619   {/*17*/"inst_queue_write_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1620   {/*1d*/"hw_int.cycles_masked", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1621   {/*1d*/"hw_int.cycles_pending_and_masked", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1622   {/*3c*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1623   {/*48*/"l1d_pend_miss.load_buffers_full", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1624   {/*49.04*/"dtlb_misses.walk_cycles", /*westmere*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1625   {/*4e*/"sfence_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1626   {/*4f.10*/"ept.walk_cycles", /*westmere*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1627   {/*60*/"offcore_requests_outstanding.demand.read_data", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1628   {/*60*/"offcore_requests_outstanding.demand.read_code", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1629   {/*60*/"offcore_requests_outstanding.demand.rfo", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1630   {/*60*/"offcore_requests_outstanding.any.read", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1631   {/*63*/"cache_lock_cycles.l1d", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1632   {/*63*/"cache_lock_cycles.l1d_l2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1633   {/*80*/"l1i.cycles_stalled", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1634   {/*85*/"itlb_misses.walk_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1635   {/*85*/"itlb_misses.pmh_busy_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1636   {/*87*/"ild_stall.lcp", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1637   {/*87*/"ild_stall.mru", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1638   {/*87*/"ild_stall.iq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1639   {/*87*/"ild_stall.regen", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1640   {/*87*/"ild_stall.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1641   {/*a2*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1642   {/*a2*/"resource_stalls.load", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1643   {/*a2*/"resource_stalls.rs_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1644   {/*a2*/"resource_stalls.store", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1645   {/*a2*/"resource_stalls.rob_full", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1646   {/*a2*/"resource_stalls.fpcw", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1647   {/*a2*/"resource_stalls.mxcsr", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1648   {/*a2*/"resource_stalls.other", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1649   {/*b0*/"offcore_requests_sq_full", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1650   {/*b3*/"snoopq_requests_outstanding.data", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1651   {/*b3*/"snoopq_requests_outstanding.invalidate", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1652   {/*b3*/"snoopq_requests_outstanding.code", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1653   //{/*c2*/"uops_retired.stalled_cycles",/*future, multibit*/           NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1654   {/*c3*/"machine_clears.cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1655   {/*d2*/"rat_stalls.flags", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1656   {/*d2*/"rat_stalls.registers", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1657   {/*d2*/"rat_stalls.rob_read_port", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1658   {/*d2*/"rat_stalls.scoreboard", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1659   {/*d2*/"rat_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1660   {/*d4*/"seg_rename_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1661   {/*f6*/"sq_full_stall_cycles", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1662   /* "Architectural" events: */
1663   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1664   PERF_EVENTS_SW_EVENT_DEFS
1665
1666   /* additional (hidden) aliases for convenience */
1667 #if 0
1668   USE_INTEL_REF_CYCLES (133),
1669 #endif
1670   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1671   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1672   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1673 };
1674
1675
1676 static Hwcentry intelSandyBridgeList[] = {
1677   /* see comments for "cycles" and "insts" for intelNehalemList */
1678   PERF_EVENTS_SW_EVENT_ALIASES
1679   USE_INTEL_REF_CYCLES (100)
1680   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1681   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1682
1683   // PEBS (sampling)
1684   {"l2m_latency", "mem_trans_retired.load_latency", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
1685
1686   // See file hwctable.README.sandybridge
1687   {"dch", "mem_load_uops_retired.l1_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
1688   {"dcm", "mem_load_uops_retired.l1_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, /*mem_load_uops_retired*/
1689   {"l2h", "mem_load_uops_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
1690   {"l2m", "mem_load_uops_retired.l2_miss", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE}, /*mem_load_uops_retired*/
1691   // Intel errata:  BT241 and BT243 says the mem_load_uops_retired.llc* counters may not be reliable on some CPU variants
1692   {"l3h", "mem_load_uops_retired.llc_hit", REGNO_ANY, STXT ("L3 Cache Hit w/o Snoop"), PRELOADS_6, 0, ABST_NONE}, // may undercount
1693   {"l3m", "longest_lat_cache.miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE},
1694
1695   /* dtlbm has not been confirmed via Intel white paper */
1696   {"dtlbm", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1697   {"dtlbm_stall", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses x 30: Estimated Stalls"), PRELOADS_6, 30, ABST_NONE},
1698   {"dtlbm", "dtlb_load_misses.demand_ld_walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1699   {"dtlbm_stall", "dtlb_load_misses.demand_ld_walk_completed", REGNO_ANY, STXT ("DTLB Misses x 30: Estimated Stalls"), PRELOADS_6, 30, ABST_NONE},
1700
1701   /* explicit definitions of (hidden) entries for proper counters */
1702   /*  Only counters that can be time converted, or are load-store need to be in this table */
1703   {/* 30a */"cpu_clk_unhalted.thread", /*15634344==6940930*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1704   //{/* 30a */"cpu_clk_unhalted.core",  /*6759307*/                     NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1705   {/*08.04*/"dtlb_load_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1706   {/*08.84*/"dtlb_load_misses.demand_ld_walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1707   {/*0d.03*/"int_misc.recovery_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1708   {/*0d.40*/"int_misc.rat_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1709   {/*0e.01*/"uops_issued.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1710   {/*0e.01*/"uops_issued.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1711   {/*14.01*/"arith.fpu_div_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1712   {/*3c.00*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1713   {/*48.01*/"l1d_pend_miss.pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1714   {/*49.04*/"dtlb_store_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1715   {/*59.20*/"partial_rat_stalls.flags_merge_uop", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1716   {/*59.20*/"partial_rat_stalls.flags_merge_uop_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1717   {/*59.40*/"partial_rat_stalls.slow_lea_window", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1718   //{/*59.80*/"partial_rat_stalls.mul_single_uop",                      NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1719   {/*5b.0c*/"resource_stalls2.all_fl_empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1720   {/*5b.0f*/"resource_stalls2.all_prf_control", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1721   {/*5b.40*/"resource_stalls2.bob_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1722   {/*5b.4f*/"resource_stalls2.ooo_rsrc", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1723   {/*5c.01*/"cpl_cycles.ring0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1724   {/*5c.02*/"cpl_cycles.ring123", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1725   {/*5c.xx*/"cpl_cycles.ring0_trans", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1726   {/*5c.xx*/"cpl_cycles.ring0_transition", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1727   {/*5e.01*/"rs_events.empty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1728   {/*60.01*/"offcore_requests_outstanding.cycles_with_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1729   {/*60.01*/"offcore_requests_outstanding.demand_data_rd_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1730   {/*60.04*/"offcore_requests_outstanding.cycles_with_demand_rfo", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1731   {/*60.04*/"offcore_requests_outstanding.demand_rfo_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1732   {/*60.08*/"offcore_requests_outstanding.cycles_with_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1733   {/*60.08*/"offcore_requests_outstanding.all_data_rd_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1734   {/*60.02*/"offcore_requests_outstanding.demand_code_rd_cycles", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1735   {/*63.01*/"lock_cycles.split_lock_uc_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1736   {/*63.02*/"lock_cycles.cache_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1737   {/*79.00*/"idq.empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1738   {/*79.04*/"idq.mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1739   {/*79.08*/"idq.dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1740   {/*79.10*/"idq.ms_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1741   {/*79.20*/"idq.ms_mite_uops_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1742   {/*79.20*/"idq.ms_mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1743   {/*79.30*/"idq.ms_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1744   {/*79.18*/"idq.all_dsb_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1745   {/*79.18*/"idq.all_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1746   {/*79.18*/"idq.all_dsb_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1747   {/*79.24*/"idq.all_mite_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1748   {/*79.24*/"idq.all_mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1749   {/*79.24*/"idq.all_mite_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1750   {/*79.3c*/"idq.mite_all_cycles", /* Linux, but not in docs? */ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1751   {/*80.04*/"icache.ifetch_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1752   {/*85.04*/"itlb_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1753   {/*87.01*/"ild_stall.lcp", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1754   {/*87.04*/"ild_stall.iq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1755   {/*9c.xx*/"idq_uops_not_delivered.cycles_0_uops_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1756   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1757   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_2_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1758   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_3_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1759   {/*9c.01*/"idq_uops_not_delivered.cycles_ge_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1760   {/*9c.01*/"idq_uops_not_delivered.cycles_fe_was_ok", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1761   {/*a1.01*/"uops_executed_port.port_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1762   {/*a1.02*/"uops_executed_port.port_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1763   {/*a1.04*/"uops_executed_port.port_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1764   {/*a1.08*/"uops_executed_port.port_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1765   {/*a1.10*/"uops_executed_port.port_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1766   {/*a1.20*/"uops_executed_port.port_5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1767   {/*a2.01*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1768   {/*a2.02*/"resource_stalls.lb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1769   {/*a2.04*/"resource_stalls.rs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1770   {/*a2.08*/"resource_stalls.sb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1771   {/*a2.0a*/"resource_stalls.lb_sb", /*sb-ep*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1772   {/*a2.0e*/"resource_stalls.mem_rs", /*sb-ep*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1773   {/*a2.10*/"resource_stalls.rob", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1774   {/*a2.20*/"resource_stalls.fcsw", /*sb*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1775   {/*a2.40*/"resource_stalls.mxcsr", /*sb*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1776   {/*a2.80*/"resource_stalls.other", /*sb*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1777   {/*a2.F0*/"resource_stalls.ooo_rsrc", /*sb-ep*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1778
1779   {/*a3.01*/"cycle_activity.cycles_l2_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1780   {/*??.??*/"cycle_activity.stalls_l2_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1781   {/*a3.02*/"cycle_activity.cycles_ldm_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1782   {/*??.??*/"cycle_activity.stalls_ldm_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1783   {/*a3.04*/"cycle_activity.cycles_no_execute", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1784   {/*a3.04*/"cycle_activity.cycles_no_dispatch", /*sandybridge*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1785   {/*a3.08*/"cycle_activity.cycles_l1d_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1786   {/*??.??*/"cycle_activity.stalls_l1d_pending", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1787
1788   {/*ab.02*/"dsb2mite_switches.penalty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1789   {/*b1.??*/"uops_executed.stall_cycles", /*? not in PRM*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1790   {/*b1.01*/"uops_dispatched.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1791   {/*b1.01*/"uops_executed.stall_cycles", /*F6M62*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1792   {/*b1.01*/"uops_executed.cycles_ge_1_uop_exec", /*F6M62,not doc'd*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1793   {/*b1.01*/"uops_executed.cycles_ge_2_uops_exec", /*F6M62,not doc'd*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1794   {/*b1.01*/"uops_executed.cycles_ge_3_uops_exec", /*F6M62,not doc'd*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1795   {/*b1.01*/"uops_executed.cycles_ge_4_uops_exec", /*F6M62,not doc'd*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1796
1797   {/*bf.05*/"l1d_blocks.bank_conflict_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1798   {/*c2.01*/"uops_retired.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1799   {/*c2.01*/"uops_retired.total_cycles", /*cmask==0x10*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1800   {/*c2.01*/"uops_retired.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1801   {/*c2.01*/"uops_retired.active_cycles", /*cmask==0x1*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1802 #if 0 // need to see documentation on the following before marking them as cycles
1803   uops_executed.cycles_ge_1_uop_exec[ / {0 | 1 | 2 | 3}], 1000003 (events)
1804   uops_executed.cycles_ge_2_uops_exec[ /
1805   {0 | 1 | 2 | 3}
1806   ], 1000003 (events)
1807   uops_executed.cycles_ge_3_uops_exec[ /
1808   {0 | 1 | 2 | 3}
1809   ], 1000003 (events)
1810   uops_executed.cycles_ge_4_uops_exec[ /
1811   {0 | 1 | 2 | 3}
1812   ], 1000003 (events)
1813 #endif
1814   {/*cd.01*/"mem_trans_retired.load_latency", /*PEBS*/ NULL, REGNO_ANY, NULL, PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1}, //non-standard overflow
1815
1816   /* "Architectural" events: */
1817   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1818   PERF_EVENTS_SW_EVENT_DEFS
1819
1820   /* additional (hidden) aliases for convenience */
1821 #if 0
1822   USE_INTEL_REF_CYCLES (100),
1823 #endif
1824   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1825   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1826   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1827 };
1828
1829
1830 static Hwcentry intelHaswellList[] = {
1831   /* see comments for "cycles" and "insts" for intelNehalemList */
1832   PERF_EVENTS_SW_EVENT_ALIASES
1833   USE_INTEL_REF_CYCLES (100)
1834   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1835   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1836
1837   // PEBS (sampling)
1838   {"l2m_latency", "mem_trans_retired.load_latency", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
1839
1840   {"dch", "mem_load_uops_retired.l1_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
1841   {"dcm", "mem_load_uops_retired.l1_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, //mem_load_uops_retired
1842   {"dcm", "0xd1~umask=0x08", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, //mem_load_uops_retired
1843   {"l2h", "mem_load_uops_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
1844   {"l2m", "mem_load_uops_retired.l2_miss", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE}, //mem_load_uops_retired
1845   {"l2m", "0xd1~umask=0x10", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE}, //mem_load_uops_retired
1846   {"l3h", "mem_load_uops_retired.l3_hit", REGNO_ANY, STXT ("L3 Cache Hit w/o Snoop"), PRELOADS_6, 0, ABST_NONE},
1847   {"l3m", "mem_load_uops_retired.l3_miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE}, //mem_load_uops_retired
1848   {"l3m", "0xd1~umask=0x20", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE}, //mem_load_uops_retired
1849
1850   /* dtlbm has not been confirmed via Intel white paper */
1851   {"dtlbm", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1852   {"dtlbm_stall", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses x 30: Estimated Stalls"), PRELOADS_6, 30, ABST_NONE},
1853
1854   /* explicit definitions of (hidden) entries for proper counters */
1855   /*  Only counters that can be time converted, or are load-store need to be in this table */
1856   {/* 30a */"cpu_clk_unhalted.thread", /*15634344==6940930*/ NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1857   //{/* 30a */"cpu_clk_unhalted.core",  /*6759307*/                     NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1858   {/*08.10*/"dtlb_load_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1859   {/*0d.03*/"int_misc.recovery_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1860   {/*0e.01*/"uops_issued.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1861   {/*0e.01*/"uops_issued.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1862   {/*3c.00*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1863   {/*48.01*/"l1d_pend_miss.pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1864   {/*49.04*/"dtlb_store_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1865   {/*5c.01*/"cpl_cycles.ring0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1866   {/*5c.02*/"cpl_cycles.ring123", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1867   {/*5c.xx*/"cpl_cycles.ring0_trans", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1868   {/*5e.01*/"rs_events.empty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1869   {/*60.01*/"offcore_requests_outstanding.cycles_with_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1870   {/*60.02*/"offcore_requests_outstanding.demand_code_rd_cycles", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1871   {/*60.04*/"offcore_requests_outstanding.demand_rfo_cycles", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1872   {/*60.08*/"offcore_requests_outstanding.cycles_with_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1873   {/*63.01*/"lock_cycles.split_lock_uc_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1874   {/*63.02*/"lock_cycles.cache_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1875   {/*79.00*/"idq.empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1876   {/*79.04*/"idq.mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1877   {/*79.08*/"idq.dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1878   {/*79.10*/"idq.ms_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1879   {/*79.20*/"idq.ms_mite_uops_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1880   {/*79.20*/"idq.ms_mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1881   {/*79.30*/"idq.ms_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1882   {/*79.18*/"idq.all_dsb_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1883   {/*79.18*/"idq.all_dsb_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1884   {/*79.24*/"idq.all_mite_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1885   {/*79.24*/"idq.all_mite_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1886   {/*80.04*/"icache.ifetch_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1887   {/*85.04*/"itlb_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1888   {/*87.01*/"ild_stall.lcp", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE}, // Intel SDM says these are stalls, not cycles
1889   {/*87.04*/"ild_stall.iq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1890   {/*9c.xx*/"idq_uops_not_delivered.cycles_0_uops_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1891   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1892   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_2_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1893   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_3_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1894   //  {/*9c.01*/"idq_uops_not_delivered.cycles_ge_1_uop_deliv.core",    NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1895   {/*9c.01*/"idq_uops_not_delivered.cycles_fe_was_ok", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1896
1897   {/*a1.01*/"uops_executed_port.port_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1898   {/*a1.02*/"uops_executed_port.port_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1899   {/*a1.04*/"uops_executed_port.port_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1900   {/*a1.08*/"uops_executed_port.port_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1901   {/*a1.10*/"uops_executed_port.port_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1902   {/*a1.20*/"uops_executed_port.port_5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1903   {/*a1.40*/"uops_executed_port.port_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1904   {/*a1.80*/"uops_executed_port.port_7", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1905   {/*a1.01*/"uops_executed_port.port_0_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1906   {/*a1.02*/"uops_executed_port.port_1_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1907   {/*a1.04*/"uops_executed_port.port_2_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1908   {/*a1.08*/"uops_executed_port.port_3_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1909   {/*a1.10*/"uops_executed_port.port_4_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1910   {/*a1.20*/"uops_executed_port.port_5_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1911   {/*a1.40*/"uops_executed_port.port_6_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1912   {/*a1.80*/"uops_executed_port.port_7_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1913
1914   {/*a2.01*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1915   {/*a2.04*/"resource_stalls.rs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1916   {/*a2.08*/"resource_stalls.sb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1917   {/*a2.10*/"resource_stalls.rob", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1918
1919   {/*a3.01*/"cycle_activity.cycles_l2_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1920   //  {/*a3.01*/"cycle_activity.cycles_l2_pending",                     NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1921   {/*a3.02*/"cycle_activity.cycles_ldm_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1922   //  {/*a3.05*/"cycle_activity.stalls_l2_pending",                     NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1923   {/*a3.08*/"cycle_activity.cycles_l1d_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1924   //  {/*a3.??*/"cycle_activity.cycles_no_execute",                     NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1925   //  {/*a3.??*/"cycle_activity.stalls_ldm_pending",/*?*/                       NULL, REGNO_ANY, NULL, PRELOAD_DEF,     1, ABST_NONE},
1926
1927   {/*ab.02*/"dsb2mite_switches.penalty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1928
1929   {/*b1.??*/"uops_executed.stall_cycles", /*? not in PRM*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1930   {/*b1.??*/"uops_executed.cycles_ge_1_uop_exec", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1931   {/*b1.??*/"uops_executed.cycles_ge_2_uops_exec", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1932   {/*b1.??*/"uops_executed.cycles_ge_3_uops_exec", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1933   {/*b1.??*/"uops_executed.cycles_ge_4_uops_exec", /*?*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1934
1935   {/*c2.01*/"uops_retired.stall_cycles", /*cmask==1 + INV*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1936   {/*c2.01*/"uops_retired.total_cycles", /*cmask==0x1*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1937   {/*c2.01*/"uops_retired.core_stall_cycles", /*PEBS Any==1*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1938
1939   {/*c3.01*/"machine_clears.cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1940
1941   {/*ca.1e*/"fp_assist.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1942
1943   {/*cd.01*/"mem_trans_retired.load_latency", /*PEBS*/ NULL, REGNO_ANY, NULL, PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1}, //non-standard overflow
1944
1945   /* "Architectural" events: */
1946   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1947   PERF_EVENTS_SW_EVENT_DEFS
1948
1949   /* additional (hidden) aliases for convenience */
1950 #if 0
1951   USE_INTEL_REF_CYCLES (100),
1952 #endif
1953   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
1954   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
1955   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
1956 };
1957
1958
1959 static Hwcentry intelBroadwellList[] = {
1960   /* see comments for "cycles" and "insts" for intelNehalemList */
1961   PERF_EVENTS_SW_EVENT_ALIASES
1962   USE_INTEL_REF_CYCLES (100)
1963   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
1964   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
1965
1966   // PEBS (sampling)
1967   {"l2m_latency", "mem_trans_retired.load_latency", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
1968   {/*cd.01*/"mem_trans_retired.load_latency", NULL, REGNO_ANY, NULL, PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
1969
1970   // aliases (the first set are PEBS, but on Intel the only precise counter we support is l2m_latency)
1971   {"dch", "mem_load_uops_retired.l1_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
1972   {"dcm", "mem_load_uops_retired.l1_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
1973   {"l2h", "mem_load_uops_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
1974   {"l2m", "mem_load_uops_retired.l2_miss", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE},
1975   {"l3h", "mem_load_uops_retired.l3_hit", REGNO_ANY, STXT ("L3 Cache Hits"), PRELOADS_6, 0, ABST_NONE},
1976   {"l3m", "mem_load_uops_retired.l3_miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE},
1977   {"dtlbm", "dtlb_load_misses.walk_completed", REGNO_ANY, STXT ("DTLB Misses"), PRELOADS_6, 0, ABST_NONE},
1978
1979   // counters that can be time converted (add FFCs if we decide to support them)
1980   // counters that are load-store (did not include any... do we want to?)
1981   {/*08.10*/"dtlb_load_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1982   {/*0d.03*/"int_misc.recovery_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1983   {/*0e.01*/"uops_issued.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1984   {/*0e.01*/"uops_issued.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1985   {/*14.01*/"arith.fpu_div_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1986   {/*3c.00*/"cpu_clk_unhalted.thread_p_any", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1987   {/*3c.00*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
1988   {/*3c.02*/"cpu_clk_thread_unhalted.one_thread_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1989   {/*48.01*/"l1d_pend_miss.pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1990   {/*48.01*/"l1d_pend_miss.pending_cycles_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1991   {/*49.10*/"dtlb_store_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1992   {/*4f.10*/"ept.walk_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1993   {/*5c.01*/"cpl_cycles.ring0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1994   {/*5c.01*/"cpl_cycles.ring0_trans", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1995   {/*5c.02*/"cpl_cycles.ring123", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1996   {/*5e.01*/"rs_events.empty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1997   {/*60.01*/"offcore_requests_outstanding.cycles_with_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1998   {/*60.02*/"offcore_requests_outstanding.demand_code_rd_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
1999   {/*60.04*/"offcore_requests_outstanding.demand_rfo_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2000   {/*60.08*/"offcore_requests_outstanding.cycles_with_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2001   {/*63.01*/"lock_cycles.split_lock_uc_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2002   {/*63.02*/"lock_cycles.cache_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2003   {/*79.02*/"idq.empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2004   {/*79.04*/"idq.mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2005   {/*79.08*/"idq.dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2006   {/*79.10*/"idq.ms_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2007   {/*79.18*/"idq.all_dsb_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2008   {/*79.18*/"idq.all_dsb_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2009   {/*79.24*/"idq.all_mite_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2010   {/*79.24*/"idq.all_mite_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2011   {/*79.30*/"idq.ms_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2012   {/*85.10*/"itlb_misses.walk_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2013   {/*9c.xx*/"idq_uops_not_delivered.cycles_0_uops_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2014   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2015   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_2_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2016   {/*9c.xx*/"idq_uops_not_delivered.cycles_le_3_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2017   {/*9c.01*/"idq_uops_not_delivered.cycles_fe_was_ok", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2018   {/*a1.01*/"uops_executed_port.port_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2019   {/*a1.02*/"uops_executed_port.port_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2020   {/*a1.04*/"uops_executed_port.port_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2021   {/*a1.08*/"uops_executed_port.port_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2022   {/*a1.10*/"uops_executed_port.port_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2023   {/*a1.20*/"uops_executed_port.port_5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2024   {/*a1.40*/"uops_executed_port.port_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2025   {/*a1.80*/"uops_executed_port.port_7", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2026   {/*a1.01*/"uops_executed_port.port_0_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2027   {/*a1.02*/"uops_executed_port.port_1_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2028   {/*a1.04*/"uops_executed_port.port_2_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2029   {/*a1.08*/"uops_executed_port.port_3_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2030   {/*a1.10*/"uops_executed_port.port_4_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2031   {/*a1.20*/"uops_executed_port.port_5_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2032   {/*a1.40*/"uops_executed_port.port_6_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2033   {/*a1.80*/"uops_executed_port.port_7_core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2034   {/*a2.01*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2035   {/*a2.04*/"resource_stalls.rs", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2036   {/*a2.08*/"resource_stalls.sb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2037   {/*a2.10*/"resource_stalls.rob", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2038   {/*a3.01*/"cycle_activity.cycles_l2_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2039   {/*a3.02*/"cycle_activity.cycles_ldm_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2040   {/*a3.04*/"cycle_activity.cycles_no_execute", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2041   {/*a3.08*/"cycle_activity.cycles_l1d_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2042   {/*a8.01*/"lsd.cycles_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2043   {/*a8.01*/"lsd.cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2044   {/*ab.02*/"dsb2mite_switches.penalty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2045   {/*b1.01*/"uops_executed.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2046   {/*c2.01*/"uops_retired.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2047   {/*c2.01*/"uops_retired.total_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2048   {/*c2.01*/"uops_retired.core_stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2049   {/*c3.01*/"machine_clears.cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2050   {/*ca.1e*/"fp_assist.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2051
2052   /* "Architectural" events: */
2053   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2054   PERF_EVENTS_SW_EVENT_DEFS
2055
2056   /* additional (hidden) aliases for convenience */
2057 #if 0
2058   USE_INTEL_REF_CYCLES (100),
2059 #endif
2060   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2061   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2062   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2063 };
2064
2065 static Hwcentry intelSkylakeList[] = {
2066   /* see comments for "cycles" and "insts" for intelNehalemList */
2067   PERF_EVENTS_SW_EVENT_ALIASES
2068   USE_INTEL_REF_CYCLES (25)
2069   {"cycles", "cpu_clk_unhalted.thread_p", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2070   {"insts", "inst_retired.any_p", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2071
2072   // PEBS (sampling)
2073   {"l2m_latency", "mem_trans_retired.load_latency", REGNO_ANY, STXT ("L2 Cache Miss Est. Latency"), PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
2074   {/*cd.01*/"mem_trans_retired.load_latency", NULL, REGNO_ANY, NULL, PRELOADS_4, 65, ABST_EXACT_PEBS_PLUS1},
2075
2076   // aliases (the first set are PEBS, but on Intel the only precise counter we support is l2m_latency)
2077   {"dch", "mem_load_retired.l1_hit", REGNO_ANY, STXT ("L1 D-cache Hits"), PRELOADS_7, 0, ABST_NONE},
2078   {"dcm", "mem_load_retired.l1_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
2079   {"l2h", "mem_load_retired.l2_hit", REGNO_ANY, STXT ("L2 Cache Hits"), PRELOADS_65, 0, ABST_NONE},
2080   {"l2m", "mem_load_retired.l2_miss", REGNO_ANY, STXT ("L2 Cache Misses"), PRELOADS_6, 0, ABST_NONE},
2081   {"l2m_stall", "cycle_activity.stalls_l2_miss", REGNO_ANY, STXT ("L2 Cache Miss Stall"), PRELOADS_7, 1, ABST_NONE}, // needs validation
2082   {"l3h", "mem_load_retired.l3_hit", REGNO_ANY, STXT ("L3 Cache Hits"), PRELOADS_6, 0, ABST_NONE},
2083   {"l3m", "mem_load_retired.l3_miss", REGNO_ANY, STXT ("L3 Cache Misses"), PRELOADS_5, 0, ABST_NONE},
2084   {"l3m_stall", "cycle_activity.stalls_l3_miss", REGNO_ANY, STXT ("L3 Cache Miss Stall"), PRELOADS_7, 1, ABST_NONE}, // needs validation
2085   {"dtlbm_stall", "dtlb_load_misses.walk_active", REGNO_ANY, STXT ("DTLB Miss Est Stall"), PRELOADS_7, 1, ABST_NONE, STXT ("Estimated time stalled on DTLB misses requiring a tablewalk.  Does not include time related to STLB hits.")}, // needs validation
2086   // PEBS mem_inst_retired.stlb_miss_loads for finding location of DTLB issues
2087   // what about: dtlb_load_misses.walk_completed, dtlb_load_misses.walk_pending, dtlb_load_misses.stlb_hit
2088
2089   {"fp_scalar", "fp_arith_inst_retired.scalar_double~umask=0x3", REGNO_ANY, STXT ("FP Scalar uOps"), PRELOADS_7, 0, ABST_NONE, STXT ("Floating-point scalar micro-ops that retired")},
2090   {"fp_vector", "fp_arith_inst_retired.128b_packed_double~umask=0x3c", REGNO_ANY, STXT ("FP Vector uOps"), /*needs test*/ PRELOADS_7, 0, ABST_NONE, STXT ("Floating-point vector micro-ops that retired")},
2091
2092   // counters that can be time converted (add FFCs if we decide to support them)
2093   // counters that are load-store (did not include any... do we want to?)
2094   {/*08.10*/"dtlb_load_misses.walk_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2095   {/*08.10*/"dtlb_load_misses.walk_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2096   {/*0d.01*/"int_misc.recovery_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2097   {/*0d.01*/"int_misc.recovery_cycles_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2098   {/*0d.80*/"int_misc.clear_resteer_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2099   {/*0e.01*/"uops_issued.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2100   {/*14.01*/"arith.divider_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2101   {/*3c.00*/"cpu_clk_unhalted.ring0_trans", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2102   {/*3c.00*/"cpu_clk_unhalted.thread_p_any", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2103   {/*3c.00*/"cpu_clk_unhalted.thread_p", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2104   {/*3c.00*/"cpu_clk_unhalted.core", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2105   {/*48.01*/"l1d_pend_miss.pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2106   {/*48.01*/"l1d_pend_miss.pending_cycles_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2107   {/*49.10*/"dtlb_store_misses.walk_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2108   {/*49.10*/"dtlb_store_misses.walk_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2109   {/*4f.10*/"ept.walk_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2110   {/*5e.01*/"rs_events.empty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2111   {/*60.01*/"offcore_requests_outstanding.cycles_with_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2112   {/*60.01*/"offcore_requests_outstanding.demand_data_rd_ge_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2113   {/*60.02*/"offcore_requests_outstanding.cycles_with_demand_code_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2114   {/*60.04*/"offcore_requests_outstanding.cycles_with_demand_rfo", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2115   {/*60.08*/"offcore_requests_outstanding.cycles_with_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2116   {/*60.10*/"offcore_requests_outstanding.cycles_with_l3_miss_demand_data_rd", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2117   {/*60.10*/"offcore_requests_outstanding.l3_miss_demand_data_rd_ge_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2118   {/*63.02*/"lock_cycles.cache_lock_duration", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2119   {/*79.04*/"idq.mite_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2120   {/*79.08*/"idq.dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2121   {/*79.10*/"idq.ms_dsb_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2122   {/*79.18*/"idq.all_dsb_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2123   {/*79.18*/"idq.all_dsb_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2124   {/*79.24*/"idq.all_mite_cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2125   {/*79.24*/"idq.all_mite_cycles_any_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2126   {/*79.30*/"idq.ms_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2127   {/*80.04*/"icache_16b.ifdata_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2128   {/*83.04*/"icache_64b.iftag_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2129   {/*85.10*/"itlb_misses.walk_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2130   {/*85.10*/"itlb_misses.walk_pending", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2131   {/*87.01*/"ild_stall.lcp", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2132   {/*9c.01*/"idq_uops_not_delivered.cycles_0_uops_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2133   {/*9c.01*/"idq_uops_not_delivered.cycles_le_1_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2134   {/*9c.01*/"idq_uops_not_delivered.cycles_le_2_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2135   {/*9c.01*/"idq_uops_not_delivered.cycles_le_3_uop_deliv.core", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2136   {/*9c.01*/"idq_uops_not_delivered.cycles_fe_was_ok", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2137   {/*a1.01*/"uops_dispatched_port.port_0", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2138   {/*a1.02*/"uops_dispatched_port.port_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2139   {/*a1.04*/"uops_dispatched_port.port_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2140   {/*a1.08*/"uops_dispatched_port.port_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2141   {/*a1.10*/"uops_dispatched_port.port_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2142   {/*a1.20*/"uops_dispatched_port.port_5", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2143   {/*a1.40*/"uops_dispatched_port.port_6", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2144   {/*a1.80*/"uops_dispatched_port.port_7", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2145   {/*a2.01*/"resource_stalls.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2146   {/*a2.08*/"resource_stalls.sb", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2147   {/*a3.01*/"cycle_activity.cycles_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2148   {/*a3.02*/"cycle_activity.cycles_l3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2149   {/*a3.04*/"cycle_activity.stalls_total", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2150   {/*a3.05*/"cycle_activity.stalls_l2_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2151   {/*a3.06*/"cycle_activity.stalls_l3_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2152   {/*a3.08*/"cycle_activity.cycles_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2153   {/*a3.0c*/"cycle_activity.stalls_l1d_miss", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2154   {/*a3.10*/"cycle_activity.cycles_mem_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2155   {/*a3.14*/"cycle_activity.stalls_mem_any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2156   {/*a6.01*/"exe_activity.exe_bound_0_ports", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2157   {/*a6.02*/"exe_activity.1_ports_util", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2158   {/*a6.04*/"exe_activity.2_ports_util", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2159   {/*a6.08*/"exe_activity.3_ports_util", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2160   {/*a6.10*/"exe_activity.4_ports_util", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2161   {/*a6.40*/"exe_activity.bound_on_stores", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2162   {/*a8.01*/"lsd.cycles_4_uops", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2163   {/*a8.01*/"lsd.cycles_active", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2164   {/*ab.02*/"dsb2mite_switches.penalty_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2165   {/*b1.01*/"uops_executed.cycles_ge_1_uop_exec", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2166   {/*b1.01*/"uops_executed.cycles_ge_2_uops_exec", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2167   {/*b1.01*/"uops_executed.cycles_ge_3_uops_exec", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2168   {/*b1.01*/"uops_executed.cycles_ge_4_uops_exec", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2169   {/*b1.01*/"uops_executed.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2170   {/*b1.02*/"uops_executed.core_cycles_ge_1", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2171   {/*b1.02*/"uops_executed.core_cycles_ge_2", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2172   {/*b1.02*/"uops_executed.core_cycles_ge_3", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2173   {/*b1.02*/"uops_executed.core_cycles_ge_4", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2174   {/*b1.02*/"uops_executed.core_cycles_none", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2175   {/*c0.1*/"inst_retired.total_cycles_ps", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2176   {/*c2.01*/"uops_retired.stall_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2177   {/*c2.01*/"uops_retired.total_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2178   {/*ca.1e*/"fp_assist.any", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2179
2180   /* "Architectural" events: */
2181   {/* FFC */"cpu_clk_unhalted.thread", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2182   {/* FFC */"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2183   PERF_EVENTS_SW_EVENT_DEFS
2184
2185   /* additional (hidden) aliases for convenience */
2186 #if 0
2187   USE_INTEL_REF_CYCLES (25),
2188 #endif
2189   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2190   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2191   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2192 };
2193
2194 static Hwcentry intelLinuxUnknown[] = {
2195   PERF_EVENTS_SW_EVENT_ALIASES
2196   //    USE_INTEL_REF_CYCLES(100) // freq is unknown
2197   {"cycles", "unhalted-core-cycles", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2198   {"cycles", "PERF_COUNT_HW_CPU_CYCLES", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2199   {"insts", "instruction-retired", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2200   {"insts", "PERF_COUNT_HW_INSTRUCTIONS", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2201
2202   {"dcm", "PERF_COUNT_HW_CACHE_MISSES.L1D", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE},
2203   {"llm", "llc-misses", REGNO_ANY, STXT ("Last-Level Cache Misses"), PRELOADS_5, 0, ABST_NONE},
2204   {"llm", "PERF_COUNT_HW_CACHE_MISSES.LL", REGNO_ANY, STXT ("Last-Level Cache Misses"), PRELOADS_5, 0, ABST_NONE},
2205
2206   {"br_msp", "branch-misses-retired", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE},
2207   {"br_msp", "PERF_COUNT_HW_BRANCH_MISSES", REGNO_ANY, STXT ("Branch Mispredict"), PRELOADS_6, 0, ABST_NONE},
2208   {"br_ins", "branch-instruction-retired", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE},
2209   {"br_ins", "PERF_COUNT_HW_BRANCH_INSTRUCTIONS", REGNO_ANY, STXT ("Branch Instructions"), PRELOADS_7, 0, ABST_NONE},
2210
2211   // counters that can be time converted (add FFCs if we decide to support them)
2212   // counters that are load-store (did not include any... do we want to?)
2213   /* "Architectural" events: */
2214   {/* FFC */"cpu_clk_unhalted.thread", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2215   {/* FFC */"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2216   PERF_EVENTS_SW_EVENT_DEFS
2217
2218   /* additional (hidden) aliases for convenience */
2219   {"cycles0", "unhalted-reference-cycles", 0, NULL, PRELOADS_6, -(25), ABST_NONE}, //YXXX -can't do with ref cycles #
2220   {"cycles0", "PERF_COUNT_HW_BUS_CYCLES", 0, NULL, PRELOADS_6, -(25), ABST_NONE}, //YXXX -can't do with ref cycles #
2221   {"cycles1", "unhalted-reference-cycles", 1, NULL, PRELOADS_65, -(25), ABST_NONE}, //YXXX - can't do with ref cycles #
2222   {"cycles1", "PERF_COUNT_HW_BUS_CYCLES", 1, NULL, PRELOADS_65, -(25), ABST_NONE}, //YXXX - can't do with ref cycles #
2223   {"insts0", "instruction-retired", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2224   {"insts0", "PERF_COUNT_HW_INSTRUCTIONS", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2225   {"insts1", "instruction-retired", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2226   {"insts1", "PERF_COUNT_HW_INSTRUCTIONS", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2227   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2228 };
2229
2230 static Hwcentry intelAtomList[] = {
2231   {"cycles", "cpu_clk_unhalted.core", /*6759307*/ REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
2232   {"cycles", "cpu_clk_unhalted.thread", /*6759307*/ REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_7, 1, ABST_NONE},
2233   {"insts", "instr_retired.any", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_7, 0, ABST_NONE},
2234
2235   /* explicit definitions of (hidden) entries for proper counters */
2236   /*  Only counters that can be time converted, or are load-store need to be in this table */
2237   /* XXXX add core2-related entries if appropriate */
2238   {/*30A*/"cpu_clk_unhalted.core", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
2239   {/*30A*/"cpu_clk_unhalted.thread", /*6759307*/ NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
2240   {/*0c*/"page_walks.cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2241   {/*14*/"cycles_div_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2242   {/*21*/"l2_ads", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2243   {/*22*/"l2_dbus_busy", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2244   {/*32*/"l2_no_req", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2245   {/*3c*/"cpu_clk_unhalted.core_p", NULL, REGNO_ANY, NULL, PRELOADS_7, 1, ABST_NONE},
2246   {/*3c*/"cpu_clk_unhalted.bus", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2247   {/*3c*/"cpu_clk_unhalted.no_other", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2248   {/*62*/"bus_drdy_clocks", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2249   {/*63*/"bus_lock_clocks", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2250   {/*64*/"bus_data_rcv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2251   {/*7a*/"bus_hit_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2252   {/*7b*/"bus_hitm_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2253   {/*7d*/"busq_empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2254   {/*7e*/"snoop_stall_drv", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2255   {/*7f*/"bus_io_wait", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2256   {/*c6*/"cycles_int_masked.cycles_int_masked", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2257   {/*c6*/"cycles_int_masked.cycles_int_pending_and_masked", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2258
2259   /* "Architectural" events: */
2260   {/*3c*/"unhalted-core-cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2261
2262   /* additional (hidden) aliases for convenience */
2263   {"cycles0", "cpu_clk_unhalted.core_p", 0, NULL, PRELOADS_75, 1, ABST_NONE},
2264   {"cycles1", "cpu_clk_unhalted.core_p", 1, NULL, PRELOADS_75, 1, ABST_NONE},
2265   {"insts0", "inst_retired.any_p", 0, NULL, PRELOADS_75, 0, ABST_NONE},
2266   {"insts1", "inst_retired.any_p", 1, NULL, PRELOADS_75, 0, ABST_NONE},
2267   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2268 };
2269
2270 static Hwcentry amd_opteron_10h_11h[] = {
2271   {"cycles", "BU_cpu_clk_unhalted", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2272   {"insts", "FR_retired_x86_instr_w_excp_intr", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2273   {"icr", "IC_fetch", REGNO_ANY, STXT ("L1 I-cache Refs"), PRELOADS_7, 0, ABST_NONE}, /* new */
2274   {"icm", "IC_miss", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_6, 0, ABST_NONE},
2275   {"l2itlbh", "IC_itlb_L1_miss_L2_hit", REGNO_ANY, STXT ("L2 ITLB Hits"), PRELOADS_6, 0, ABST_NONE}, /* new */
2276   {"l2itlbm", "IC_itlb_L1_miss_L2_miss", REGNO_ANY, STXT ("L2 ITLB Misses"), PRELOADS_5, 0, ABST_NONE}, /* new */
2277   {"l2ir", "BU_internal_L2_req~umask=0x1", REGNO_ANY, STXT ("L2 I-cache Refs"), PRELOADS_6, 0, ABST_NONE},
2278   {"l2im", "BU_fill_req_missed_L2~umask=0x1", REGNO_ANY, STXT ("L2 I-cache Misses"), PRELOADS_4, 0, ABST_NONE},
2279   {"dcr", "DC_access", REGNO_ANY, STXT ("L1 D-cache Refs"), PRELOADS_7, 0, ABST_NONE}, /* new */
2280   {"dcm", "DC_miss", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, /* new */
2281   {"l2dtlbh", "DC_dtlb_L1_miss_L2_hit", REGNO_ANY, STXT ("L2 DTLB Hits"), PRELOADS_6, 0, ABST_NONE}, /* new */
2282   {"l2dtlbm", "DC_dtlb_L1_miss_L2_miss", REGNO_ANY, STXT ("L2 DTLB Misses"), PRELOADS_5, 0, ABST_NONE}, /* new */
2283   {"l2dr", "BU_internal_L2_req~umask=0x2", REGNO_ANY, STXT ("L2 D-cache Refs"), PRELOADS_65, 0, ABST_NONE}, /* hwc_cache_load: 1.6x overcount on shanghai01 */
2284   {"l2dm", "BU_fill_req_missed_L2~umask=0x2", REGNO_ANY, STXT ("L2 D-cache Misses"), PRELOADS_6, 0, ABST_NONE}, /* new */
2285   {"fpadd", "FP_dispatched_fpu_ops~umask=0x1", REGNO_ANY, STXT ("FP Adds"), PRELOADS_7, 0, ABST_NONE},
2286   {"fpmul", "FP_dispatched_fpu_ops~umask=0x2", REGNO_ANY, STXT ("FP Muls"), PRELOADS_7, 0, ABST_NONE},
2287   {"fpustall", "FR_dispatch_stall_fpu_full", REGNO_ANY, STXT ("FPU Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
2288   {"memstall", "FR_dispatch_stall_ls_full", REGNO_ANY, STXT ("Memory Unit Stall Cycles"), PRELOADS_7, 1, ABST_NONE},
2289   // For PAPI mappings, see hwctable.README.family10h
2290   // For PAPI mappings, see hwctable.README.opteron
2291
2292   /* explicit definitions of (hidden) entries for proper counters */
2293   /*  Only counters that can be time converted, or are load-store need to be in this table */
2294   {"BU_cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2295   {"FP_cycles_no_fpu_ops_retired", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2296   {"FP_serialize_ops_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2297   {"FR_dispatch_stall_branch_abort_to_retire", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2298   {"FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2299   {"FR_dispatch_stall_fpu_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2300   {"FR_dispatch_stall_ls_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2301   {"FR_dispatch_stall_reorder_buffer_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2302   {"FR_dispatch_stall_resv_stations_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2303   {"FR_dispatch_stall_segment_load", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2304   {"FR_dispatch_stall_serialization", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2305   {"FR_dispatch_stall_waiting_all_quiet", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2306   {"FR_dispatch_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2307   {"FR_intr_masked_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2308   {"FR_intr_masked_while_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2309   {"FR_nothing_to_dispatch", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2310   {"IC_instr_fetch_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2311   {"LS_buffer_2_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2312   {"NB_mem_ctrlr_dram_cmd_slots_missed", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2313   {"NB_mem_ctrlr_turnaround", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_TBD},
2314
2315   /* additional (hidden) aliases, for convenience */
2316   {"cycles0", "BU_cpu_clk_unhalted", 0, NULL, PRELOADS_8, 1, ABST_NONE},
2317   {"cycles1", "BU_cpu_clk_unhalted", 1, NULL, PRELOADS_8, 1, ABST_NONE},
2318   {"insts0", "FR_retired_x86_instr_w_excp_intr", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2319   {"insts1", "FR_retired_x86_instr_w_excp_intr", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2320   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2321 };
2322
2323 static Hwcentry amd_15h[] = {
2324   {"cycles", "CU_cpu_clk_unhalted", REGNO_ANY, STXT ("CPU Cycles"), PRELOADS_75, 1, ABST_NONE},
2325   {"insts", "EX_retired_instr_w_excp_intr", REGNO_ANY, STXT ("Instructions Executed"), PRELOADS_75, 0, ABST_NONE},
2326   {"icr", "IC_fetch", REGNO_ANY, STXT ("L1 I-cache Refs"), PRELOADS_7, 0, ABST_NONE}, /* new */
2327   {"icm", "IC_miss", REGNO_ANY, STXT ("L1 I-cache Misses"), PRELOADS_6, 0, ABST_NONE},
2328   {"l2im", "IC_refill_from_system", REGNO_ANY, STXT ("L2 I-cache Misses"), PRELOADS_6, 0, ABST_NONE},
2329   {"dcr", "DC_access", REGNO_ANY, STXT ("L1 D-cache Refs"), PRELOADS_7, 0, ABST_NONE}, /* new */
2330   {"dcm", "DC_miss~umask=0x3", REGNO_ANY, STXT ("L1 D-cache Misses"), PRELOADS_65, 0, ABST_NONE}, /* new */
2331   {"l2dm", "DC_refill_from_system", REGNO_ANY, STXT ("L2 D-cache Misses"), PRELOADS_6, 0, ABST_NONE}, /* new */
2332   {"dtlbm", "DC_unified_tlb_miss~umask=0x7", REGNO_ANY, STXT ("L2 DTLB Misses"), PRELOADS_5, 0, ABST_NONE}, /* new */
2333   // For PAPI mappings, see hwctable.README.family15h
2334
2335   /* explicit definitions of (hidden) entries for proper counters */
2336   /*  Only counters that can be time converted, or are load-store need to be in this table */
2337   {/*001.xx*/"FP_scheduler_empty", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2338   {/*006.xx*/"FP_bottom_execute_uops_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2339   {/*023.xx*/"LS_ldq_stq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2340   {/*024.xx*/"LS_locked_operation", /*umask!=0*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2341   {/*069.xx*/"CU_mab_wait_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2342   {/*076.xx*/"CU_cpu_clk_unhalted", NULL, REGNO_ANY, NULL, PRELOADS_75, 1, ABST_NONE},
2343   {/*087.xx*/"IC_instr_fetch_stall", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2344   {/*0cd.xx*/"EX_intr_masked_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2345   {/*0ce.xx*/"EX_intr_masked_while_pending_cycles", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2346   {/*0d0.xx*/"DE_nothing_to_dispatch", /*future*/ NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2347   {/*0d1.xx*/"DE_dispatch_stalls", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2348   {/*0d3.xx*/"DE_dispatch_stall_serialization", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2349   {/*0d5.xx*/"DE_dispatch_stall_instr_retire_q_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2350   {/*0d6.xx*/"DE_dispatch_stall_int_scheduler_q_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2351   {/*0d7.xx*/"DE_dispatch_stall_fp_scheduler_q_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2352   {/*0d8.xx*/"DE_dispatch_stall_ldq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2353   {/*0d9.xx*/"DE_dispatch_stall_waiting_all_quiet", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2354   {/*1d8.xx*/"EX_dispatch_stall_stq_full", NULL, REGNO_ANY, NULL, PRELOAD_DEF, 1, ABST_NONE},
2355
2356   /* additional (hidden) aliases, for convenience */
2357   {"cycles0", "CU_cpu_clk_unhalted", 0, NULL, PRELOADS_8, 1, ABST_NONE},
2358   {"cycles1", "CU_cpu_clk_unhalted", 1, NULL, PRELOADS_8, 1, ABST_NONE},
2359   {"insts0", "EX_retired_instr_w_excp_intr", 0, NULL, PRELOADS_8, 0, ABST_NONE},
2360   {"insts1", "EX_retired_instr_w_excp_intr", 1, NULL, PRELOADS_8, 0, ABST_NONE},
2361   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2362 };
2363
2364 #define INIT_HWC(nm, mtr, cfg, ty) .name = (nm), .metric = (mtr), \
2365     .config = (cfg), .type = ty, .use_perf_event_type = 1, \
2366     .val = PRELOAD_DEF, .reg_num = REGNO_ANY
2367 #define HWE(nm, mtr, cfg) INIT_HWC(nm, mtr, cfg, PERF_TYPE_HARDWARE)
2368 #define SWE(nm, mtr, cfg) INIT_HWC(nm, mtr, cfg, PERF_TYPE_SOFTWARE)
2369 #define HWCE(nm, mtr, id, op, res) \
2370     INIT_HWC(nm, mtr, (id) | ((op) << 8) | ((res) << 16), PERF_TYPE_HW_CACHE)
2371
2372 static Hwcentry generic_list[] = {
2373 // Hardware event:
2374   { HWE("usr_time", STXT("User CPU"), PERF_COUNT_HW_CPU_CYCLES), .timecvt = 1,
2375     .int_name = "cycles" },
2376   { HWE("sys_time", STXT("System CPU"), PERF_COUNT_HW_CPU_CYCLES), .timecvt = 1,
2377     .int_name = "cycles~system=1~user=0" },
2378   { HWE("branch-instructions", STXT("Branch-instructions"),
2379         PERF_COUNT_HW_BRANCH_INSTRUCTIONS) },
2380   { HWE("branch-misses", STXT("Branch-misses"), PERF_COUNT_HW_BRANCH_MISSES) },
2381   { HWE("bus-cycles", STXT("Bus Cycles"), PERF_COUNT_HW_BUS_CYCLES),
2382           .timecvt = 1 },
2383   { HWE("cache-misses", STXT("Cache-misses"), PERF_COUNT_HW_CACHE_MISSES) },
2384   { HWE("cache-references", STXT("Cache-references"),
2385         PERF_COUNT_HW_CACHE_REFERENCES) },
2386   { HWE("cycles", STXT("CPU Cycles"), PERF_COUNT_HW_CPU_CYCLES), .timecvt = 1 },
2387   { HWE("insts", STXT("Instructions Executed"), PERF_COUNT_HW_INSTRUCTIONS),
2388           .int_name = "instructions" },
2389   { HWE("ref-cycles", STXT("Total Cycles"), PERF_COUNT_HW_REF_CPU_CYCLES),
2390           .timecvt = 1 },
2391   { HWE("stalled-cycles-backend", STXT("Stalled Cycles during issue."),
2392         PERF_COUNT_HW_STALLED_CYCLES_BACKEND), .timecvt = 1 },
2393   { HWE("stalled-cycles-frontend", STXT("Stalled Cycles during retirement."),
2394         PERF_COUNT_HW_STALLED_CYCLES_FRONTEND), .timecvt = 1 },
2395 // Software event:
2396   { SWE("alignment-faults", STXT("Alignment Faults"),
2397         PERF_COUNT_SW_ALIGNMENT_FAULTS) },
2398   { SWE("context-switches", STXT("Context Switches"),
2399         PERF_COUNT_SW_CONTEXT_SWITCHES) },
2400   { SWE("cpu-clock", STXT("CPU Clock"), PERF_COUNT_SW_CPU_CLOCK),
2401           .timecvt = 1 },
2402   { SWE("cpu-migrations", STXT("CPU Migrations"),
2403         PERF_COUNT_SW_CPU_MIGRATIONS) },
2404   { SWE("emulation-faults", STXT("Emulation Faults"),
2405         PERF_COUNT_SW_EMULATION_FAULTS) },
2406   { SWE("major-faults", STXT("Major Page Faults"),
2407         PERF_COUNT_SW_PAGE_FAULTS_MAJ) },
2408   { SWE("minor-faults", STXT("Minor Page Faults"),
2409         PERF_COUNT_SW_PAGE_FAULTS_MIN) },
2410   { SWE("page-faults", STXT("Page Faults"), PERF_COUNT_SW_PAGE_FAULTS) },
2411   { SWE("task-clock", STXT("Clock Count Specific"), PERF_COUNT_SW_TASK_CLOCK),
2412           .timecvt = 1 },
2413 // Hardware cache event
2414   { HWCE("L1-dcache-load-misses", STXT("L1 D-cache Load Misses"),
2415          PERF_COUNT_HW_CACHE_L1D,
2416          PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) },
2417   { HWCE("L1-dcache-loads", STXT("L1 D-cache Loads"),
2418          PERF_COUNT_HW_CACHE_L1D,
2419          PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },
2420   { HWCE("L1-dcache-store-misses", STXT("L1 D-cache Store Misses"),
2421          PERF_COUNT_HW_CACHE_L1D,
2422          PERF_COUNT_HW_CACHE_RESULT_MISS, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },
2423   { HWCE("L1-dcache-stores", STXT("L1 D-cache Store Stores"),
2424          PERF_COUNT_HW_CACHE_L1D,
2425          PERF_COUNT_HW_CACHE_OP_WRITE, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },
2426   { HWCE("L1-icache-load-misses", STXT("L1 Instructions Load Misses"),
2427          PERF_COUNT_HW_CACHE_L1I,
2428          PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) },
2429   { HWCE("L1-icache-load-misses", STXT("L1 Instructions Loads"),
2430          PERF_COUNT_HW_CACHE_L1I,
2431          PERF_COUNT_HW_CACHE_OP_READ,  PERF_COUNT_HW_CACHE_RESULT_ACCESS) },
2432   { HWCE("dTLB-load-misses", STXT("D-TLB Load Misses"),
2433          PERF_COUNT_HW_CACHE_DTLB,
2434          PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) },
2435   { HWCE("dTLB-loads", STXT("D-TLB Loads"),
2436          PERF_COUNT_HW_CACHE_DTLB,
2437          PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },
2438   { HWCE("iTLB-load-misses", STXT("The Instruction TLB Load Misses"),
2439          PERF_COUNT_HW_CACHE_ITLB,
2440          PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_MISS) },
2441   { HWCE("iTLB-loads", STXT("The Instruction TLB Loads"),
2442          PERF_COUNT_HW_CACHE_ITLB,
2443          PERF_COUNT_HW_CACHE_OP_READ, PERF_COUNT_HW_CACHE_RESULT_ACCESS) },
2444
2445   {NULL, NULL, 0, NULL, 0, 0, 0, 0, ABST_NONE}
2446 };
2447
2448 /* structure defining the counters for a CPU type */
2449 typedef struct
2450 {
2451   int cputag;
2452   Hwcentry *stdlist_table;
2453 #define MAX_DEFAULT_HWC_DEFS 4 // allows multiple defs to handle OS variations; extend as needed
2454   char *default_exp_p[MAX_DEFAULT_HWC_DEFS + 1]; // end of list MUST be marked with NULL
2455 } cpu_list_t;
2456
2457 /*  IMPORTANT NOTE:
2458  *
2459  *  Any default HWC string must consist of counter names separated by -TWO- commas,
2460  *  with a no trailing comma/value after the last counter name
2461  *
2462  *  Only aliased counters should be specified; non-aliased counters will
2463  *  not get the right overflow values set.
2464  *  If the string is not formatted that way, -h hi and -h lo will fail
2465  */
2466 static cpu_list_t cputabs[] = {
2467   {CPC_ULTRA1, usIlist, {NULL}}, /* bind will fail */
2468   {CPC_ULTRA2, usIlist, {NULL}}, /* bind will fail */
2469   {CPC_ULTRA3, usIIIlist, {"insts,,ecstall", 0}},
2470   {CPC_ULTRA3_PLUS, usIIIlist, {"insts,,ecstall", 0}},
2471   {CPC_ULTRA3_I, usIIIlist, {"insts,,ecstall", 0}},
2472   {CPC_ULTRA4_PLUS, usIVplist, {"insts,,ecstall", 0}},
2473   {CPC_ULTRA_T1, niagara1, {"insts", 0}},
2474   {CPC_ULTRA_T2, niagara2, {"insts,,+l2drm", 0}},
2475   {CPC_ULTRA_T2P, niagara2, {"insts,,+l2drm", 0}},
2476   {CPC_ULTRA_T3, niagara2, {"insts,,+l2drm", 0}},
2477   {CPC_SPARC_T4, sparc_t4, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2478   {CPC_SPARC_M4, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, // renamed to m5
2479   {CPC_SPARC_T5, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2480   {CPC_SPARC_M5, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2481   {CPC_SPARC_T6, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, // no such processor
2482   {CPC_SPARC_M6, sparc_t5_m6, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2483   {CPC_SPARC_M7, sparc_m7, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}}, // includes T7
2484   {CPC_SPARC_M8, sparc_m8, {"insts,,cycles,,c_stalls,,dcm", "c_stalls", 0}},
2485   {CPC_PENTIUM_PRO_MMX, pentiumIIlist, {"insts", 0}},
2486   {CPC_PENTIUM_PRO, pentiumIIIlist, {"insts", 0}},
2487   {CPC_PENTIUM_4, pentium4, {"insts", 0}},
2488   {CPC_PENTIUM_4_HT, pentium4, {"insts", 0}},
2489   {CPC_INTEL_CORE2, intelCore2list, {"insts,,cycles", 0}},
2490   {CPC_INTEL_NEHALEM, intelNehalemList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2491       "insts,,cycles,,l3m_stall,,dtlbm_stall", 0}},
2492   {CPC_INTEL_WESTMERE, intelNehalemList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2493       "insts,,cycles,,l3m_stall,,dtlbm_stall", 0}},
2494   {CPC_INTEL_SANDYBRIDGE, intelSandyBridgeList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2495       "insts,,cycles,,l3m,,dtlbm", 0}},
2496   {CPC_INTEL_IVYBRIDGE, intelSandyBridgeList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2497       "insts,,cycles,,l3m,,dtlbm", 0}},
2498   {CPC_INTEL_HASWELL, intelHaswellList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2499       "insts,,cycles,,l3m,,dtlbm", 0}},
2500   {CPC_INTEL_BROADWELL, intelBroadwellList, {"insts,,cycles,,+l2m_latency,,dtlbm",
2501       "insts,,cycles,,l3m,,dtlbm", 0}},
2502   {CPC_INTEL_SKYLAKE, intelSkylakeList, {"insts,,cycles,,+l2m_latency,,dtlbm_stall",
2503       "insts,,cycles,,l2m_stall,,dtlbm_stall", 0}},
2504   {CPC_INTEL_UNKNOWN, intelLinuxUnknown, {"cycles,,insts,,llm",
2505       "user_time,,system_time,,cycles,,insts,,llm", 0}},
2506   {CPC_INTEL_ATOM, intelAtomList, {"insts", 0}},
2507   {CPC_AMD_K8C, amd_opteron_10h_11h, {"insts,,cycles,,l2dm,,l2dtlbm", 0}},
2508   {CPC_AMD_FAM_10H, amd_opteron_10h_11h, {"insts,,cycles,,l2dm,,l2dtlbm", 0}},
2509   {CPC_AMD_FAM_11H, amd_opteron_10h_11h, {"insts,,cycles,,l2dm,,l2dtlbm", 0}},
2510   {CPC_AMD_FAM_15H, amd_15h, {"insts,,cycles", 0}},
2511   {CPC_SPARC64_V, usfuji_V_list, {"insts,,cycles", 0}},
2512   {CPC_SPARC64_VI, usfuji_VI_VII_list, {"insts,,cycles,,dcstall", 0}},
2513   {CPC_SPARC64_VII, usfuji_VI_VII_list, {"insts,,cycles,,dcstall", 0}},
2514   {CPC_SPARC64_X, usfuji_X_list, {"insts,,cycles,,dcstall", 0}},
2515   {CPC_SPARC64_XII, usfuji_XII_list, {"insts,,cycles,,dcstall", 0}},
2516   {CPC_KPROF, kproflist, {NULL}}, // OBSOLETE (To support 12.3 and earlier, TBR)
2517   {ARM_CPU_IMP_APM, generic_list, {"insts,,cycles", 0}},
2518   {CPC_AMD_Authentic, generic_list, {"insts,,cycles", 0}},
2519   {0, generic_list, {"insts,,cycles", 0}},
2520 };
2521
2522 /*---------------------------------------------------------------------------*/
2523 /* state variables */
2524 static int initialized;
2525 static int signals_disabled;
2526
2527 // Simple array list
2528 typedef struct
2529 {
2530   void** array;     // array of ptrs, last item set to null
2531   int sz;           // num live elements in array
2532   int max;          // array allocation size
2533 } ptr_list;
2534
2535 static void
2536 ptr_list_init (ptr_list *lst)
2537 {
2538   lst->sz = 0;
2539   lst->max = 0;
2540   lst->array = 0;
2541 }
2542
2543 static void
2544 ptr_list_add (ptr_list *lst, char* ptr)
2545 { // ptr must be freeable
2546   if (lst->sz >= lst->max - 1)
2547     {
2548       void * * new;
2549       int newmax = lst->max ? lst->max * 2 : 16;
2550       new = (void**) realloc (lst->array, newmax * sizeof (void*));
2551       if (!new) return; // failed, discard add
2552       lst->max = newmax;
2553       lst->array = new;
2554     }
2555   lst->array[lst->sz++] = ptr;
2556   lst->array[lst->sz] = NULL; // mark new end-of-list
2557 }
2558
2559 static void
2560 ptr_list_free (ptr_list *lst)
2561 { // includes shallow free of all elements
2562   if (lst->array)
2563     {
2564       for (int ii = 0; lst->array[ii]; ii++)
2565         free (lst->array[ii]);
2566       free (lst->array);
2567     }
2568   lst->sz = 0;
2569   lst->max = 0;
2570   lst->array = 0;
2571 }
2572
2573 // Capabilities of this machine (initialized by setup_cpc())
2574 static int cpcx_cpuver = CPUVER_UNDEFINED;
2575 static uint_t cpcx_npics;
2576 static const char *cpcx_cciname;
2577 static const char *cpcx_docref;
2578 static uint64_t cpcx_support_bitmask;
2579
2580 // cpcx_*[0]: collect lists
2581 // cpcx_*[1]: er_kernel lists
2582 // Each cpcx_*[] list is an array of ptrs with null ptr marking end of list
2583 static char **cpcx_attrs[2];
2584
2585 static Hwcentry **cpcx_std[2];
2586 static Hwcentry **cpcx_raw[2];
2587 static Hwcentry **cpcx_hidden[2];
2588
2589 static uint_t cpcx_max_concurrent[2];
2590 static char *cpcx_default_hwcs[2];
2591 static char *cpcx_orig_default_hwcs[2];
2592 static int cpcx_has_precise[2];
2593
2594 #define VALID_FOR_KERNEL(forKernel) ((forKernel)>=0 && (forKernel)<=1)
2595 #define IS_KERNEL(forKernel) ((forKernel)==1)
2596
2597 // used to build lists:
2598 static ptr_list unfiltered_attrs;
2599 static ptr_list unfiltered_raw;
2600
2601 /*---------------------------------------------------------------------------*/
2602 /* misc internal utilities */
2603
2604 /* compare 2 strings to either \0 or <termchar> */
2605 #define IS_EOL(currchar, termchar) ((currchar)==(termchar) || (currchar)==0)
2606
2607 static int
2608 is_same (const char * regname, const char * int_name, char termchar)
2609 {
2610   do
2611     {
2612       char a = *regname;
2613       char b = *int_name;
2614       if (IS_EOL (a, termchar))
2615         {
2616           if (IS_EOL (b, termchar))
2617             return 1; /* strings are the same up to terminating char */
2618           else
2619             break; /* strings differ */
2620         }
2621       if (a != b)
2622         break;      /* strings differ */
2623       regname++;
2624       int_name++;
2625     }
2626   while (1);
2627   return 0;
2628 }
2629
2630 static int
2631 is_numeric (const char *name, uint64_t *pval)
2632 {
2633   char *endptr;
2634   uint64_t val = strtoull (name, &endptr, 0);
2635   if (!*name || *endptr)
2636     return 0; /* name does not specify a numeric value */
2637   if (pval)
2638     *pval = val;
2639   return 1;
2640 }
2641
2642 static int
2643 is_visible_alias (Hwcentry* pctr)
2644 {
2645   if (!pctr)
2646     return 0;
2647   if (pctr->name && pctr->int_name && pctr->metric)
2648     return 1;
2649   return 0;
2650 }
2651
2652 static int
2653 is_hidden_alias (Hwcentry* pctr)
2654 {
2655   if (!pctr)
2656     return 0;
2657   if (pctr->name && pctr->int_name && pctr->metric == NULL)
2658     return 1;
2659   return 0;
2660 }
2661
2662 static int
2663 is_numeric_alias (Hwcentry* pctr)
2664 {
2665   int is_numeric_alias = 0;
2666   regno_t regno;
2667   char *nameOnly = NULL;
2668   hwcfuncs_parse_ctr (pctr->int_name, NULL, &nameOnly, NULL, NULL, &regno);
2669   if (is_numeric (nameOnly, NULL))
2670     is_numeric_alias = 1;
2671   free (nameOnly);
2672   return is_numeric_alias;
2673 }
2674
2675 /* print list of register to a buffer */
2676 /*
2677  *  style      e x a m p l e s
2678  *    0        NONE    2       {0|1|2|3}
2679  *    1        NONE    2       : 0, 1, 2, or 3
2680  *    2                        0 1 2 3     6
2681  */
2682 static char *
2683 get_regnolist (char *buf, size_t sz, const regno_t *reg_list, int style)
2684 {
2685   if (!buf || !sz)
2686     return "INTERNAL ERROR";
2687   buf[0] = 0;
2688   if (style == 2)
2689     {
2690       int ii;
2691       // width should be consistent with that in format_columns()
2692       // the format will accommodate cpcx_npics regs
2693       if (cpcx_npics < 1)
2694         return "INTERNAL ERROR";
2695       // clear out the buffer
2696       for (ii = 0; ii < sz; ii++)
2697         buf[ii] = '_';
2698       if (cpcx_npics <= 9)
2699         {
2700           // one char per reg, plus terminating null char
2701           if (cpcx_npics + 1 > sz)
2702             return "INTERNAL ERROR";
2703           buf[cpcx_npics] = '\0';
2704
2705           // fill buf with regnos
2706           for (ii = 0; ii < MAX_PICS; ii++)
2707             {
2708               regno_t regno = reg_list[ii];
2709               if (REG_LIST_EOL (regno))
2710                 break;
2711               if (regno < 0 || regno >= cpcx_npics)
2712                 return "INTERNAL ERROR";
2713               buf[regno] = '0' + regno;
2714             }
2715         }
2716       else
2717         {
2718           /* space between regs, which may be 1 or 2 digits each
2719            *   1 char  for reg 0
2720            *   2 chars for regs 1-9 each
2721            *   3 chars for regs 10- each
2722            *   1 char  for terminating null char
2723            */
2724           int nchars = 17 + 3 * (cpcx_npics - 9);
2725           if (nchars > sz)
2726             return "INTERNAL ERROR";
2727           buf[nchars - 1] = '\0';
2728
2729           // fill buf with regnos
2730           for (ii = 0; ii < MAX_PICS; ii++)
2731             {
2732               regno_t regno = reg_list[ii];
2733               if (REG_LIST_EOL (regno))
2734                 break;
2735               if (regno <= 9)
2736                 buf[2 * regno ] = '0' + regno;
2737               else
2738                 {
2739                   buf[3 * (regno - 9) + 17] = '0' + (regno / 10);
2740                   buf[3 * (regno - 9) + 18] = '0' + (regno % 10);
2741                 }
2742             }
2743         }
2744       return buf;
2745     }
2746   if (REG_LIST_IS_EMPTY (reg_list))
2747     {
2748       snprintf (buf, sz, GTXT ("NONE"));
2749       return buf;
2750     }
2751   else if (REG_LIST_EOL (reg_list[1]))
2752     {
2753       /* 1 item in list */
2754       snprintf (buf, sz, "%d", reg_list[0]);
2755       return buf;
2756     }
2757   else
2758     {
2759       /* 2 more items in list */
2760       int ii, num_regs;
2761       for (ii = 0; ii < MAX_PICS; ii++)
2762         {
2763           regno_t regno = reg_list[ii];
2764           if (REG_LIST_EOL (regno))
2765             break;
2766         }
2767       num_regs = ii;
2768       buf[0] = 0;
2769       for (ii = 0; ii < num_regs; ii++)
2770         {
2771           regno_t regno = reg_list[ii];
2772           if (style == 0)
2773             snprintf (buf + strlen (buf), sz - strlen (buf),
2774                       "%c%d", ii ? '|' : '{', regno);
2775           else
2776             {
2777               if (num_regs == 2)
2778                 snprintf (buf + strlen (buf), sz - strlen (buf),
2779                           "%d%s", regno, !ii ? " or " : "");
2780               else
2781                 {
2782                   /* 3 or more items in list */
2783                   if (ii < num_regs - 2)
2784                     snprintf (buf + strlen (buf), sz - strlen (buf),
2785                               "%d, ", regno);
2786                   else if (ii == num_regs - 2)
2787                     snprintf (buf + strlen (buf), sz - strlen (buf),
2788                               "%d, or ", regno);
2789                   else
2790                     snprintf (buf + strlen (buf), sz - strlen (buf),
2791                               "%d", regno);
2792                 }
2793             }
2794         }
2795       if (style == 0)
2796         snprintf (buf + strlen (buf), sz - strlen (buf), "}");
2797     }
2798   return buf;
2799 }
2800
2801 #if !HWC_DEBUG
2802 #define hwcentry_print(lvl,x1,x2)
2803 #else
2804
2805 /* print a Hwcentry */
2806 static void
2807 hwcentry_print (int lvl, const char * header, const Hwcentry *pentry)
2808 {
2809   char buf[1024];
2810   Tprintf (lvl, "%s '%s', '%s', %d, '%s', %d, %d, %d, %d, %d, %d, /",
2811            header,
2812            pentry->name ? pentry->name : "NULL",
2813            pentry->int_name ? pentry->int_name : "NULL",
2814            pentry->reg_num,
2815            pentry->metric ? pentry->metric : "NULL",
2816            pentry->lval, /* low-resolution/long run */
2817            pentry->val, /* normal */
2818            pentry->hval, /* high-resolution/short run */
2819            pentry->timecvt,
2820            pentry->memop, /* type of instruction that can trigger */
2821            pentry->sort_order);
2822   get_regnolist (buf, sizeof (buf), pentry->reg_list, 0);
2823   Tprintf (lvl, "%s\n", buf);
2824 }
2825 #endif
2826
2827 /* add <regno> to a Hwcentry's list */
2828 static void
2829 regno_add (Hwcentry * pctr, regno_t regno)
2830 {
2831   int jj;
2832   regno_t *reg_list;
2833   if (!pctr)
2834     {
2835       Tprintf (0, "hwctable: regno_add(): ERROR: pctr==NULL\n");
2836       return;
2837     }
2838   reg_list = pctr->reg_list;
2839   if (!reg_list)
2840     {
2841       /* create list */
2842       reg_list = (regno_t*) malloc (sizeof (regno_t*) * MAX_PICS);
2843       if (!reg_list)
2844         {
2845           hwcentry_print (DBG_LT0, "hwctable: regno_add: ERROR:"
2846                           " Out of memory: ", pctr);
2847           return;
2848         }
2849       /* initialize list */
2850       for (jj = 0; jj < MAX_PICS; jj++)
2851         reg_list[jj] = REGNO_ANY;
2852       pctr->reg_list = reg_list;
2853     }
2854   if (regno == REGNO_ANY)
2855     {
2856       /* add all counters up to cpcx_npics */
2857       for (jj = 0; jj < MAX_PICS && jj < cpcx_npics; jj++)
2858         reg_list[jj] = jj;
2859     }
2860   else
2861     {
2862       /* add <regno> to list of registers */
2863       for (jj = 0; jj < MAX_PICS; jj++)
2864         {
2865           if (reg_list[jj] == regno)
2866             {
2867               hwcentry_print (DBG_LT0, "hwctable: regno_add: WARNING: "
2868                               "Duplicate regno: ", pctr);
2869               break;
2870             }
2871           if (reg_list[jj] == REGNO_ANY)
2872             {
2873               reg_list[jj] = regno;
2874               break;
2875             }
2876         }
2877     }
2878   if (jj == MAX_PICS)
2879     hwcentry_print (DBG_LT0, "hwctable: regno_add: WARNING:"
2880                     " regno list is full:", pctr);
2881 }
2882
2883 /*---------------------------------------------------------------------------*/
2884 /* utilities for rawlist (list of raw counters with reglist[] filled in) */
2885
2886 /* search the 'raw' list of counters for <name> */
2887 static Hwcentry *
2888 ptrarray_find_by_name (Hwcentry** array, const char * name)
2889 {
2890   if (name == NULL)
2891     return NULL;
2892   Tprintf (DBG_LT3, "hwctable: array_find_by_name(%s):\n", name);
2893   for (int ii = 0; array && array[ii]; ii++)
2894     if (strcmp (array[ii]->name, name) == 0)
2895       return array[ii];
2896   return NULL; /* not found */
2897 }
2898
2899 /* add Hwcentry to the 'raw' list of counters */
2900 static Hwcentry *
2901 alloc_shallow_copy (const Hwcentry *pctr)
2902 {
2903   Hwcentry *node = (Hwcentry *) malloc (sizeof (Hwcentry));
2904   if (!node)
2905     return NULL; // fail
2906   *node = *pctr; /* shallow copy! */
2907   if (pctr->name)
2908     node->name = strdup (pctr->name);
2909   return node;
2910 }
2911
2912 /* add Hwcentry to the 'raw' list of counters */
2913 static Hwcentry *
2914 list_append_shallow_copy (ptr_list *list, const Hwcentry *pctr)
2915 {
2916   Hwcentry *node = alloc_shallow_copy (pctr);
2917   if (!node)
2918     return NULL; // fail
2919   ptr_list_add (list, (void*) node);
2920   return node;
2921 }
2922
2923 static Hwcentry *
2924 list_add (ptr_list *list, uint_t regno, const char *name)
2925 {
2926   Hwcentry *praw;
2927   praw = ptrarray_find_by_name ((Hwcentry**) list->array, name);
2928   if (!praw)
2929     {
2930       Hwcentry tmpctr = empty_ctr;
2931       tmpctr.name = (char *) name;
2932       praw = list_append_shallow_copy (list, &tmpctr);
2933     }
2934   if (praw)
2935     regno_add (praw, regno);
2936   return praw;
2937 }
2938
2939 /*---------------------------------------------------------------------------*/
2940 /* utilities for stdlist (table of aliased, hidden, & convenience, ctrs) */
2941
2942 /* find top level definition for <cpuid> */
2943 static cpu_list_t*
2944 cputabs_find_entry (int cpuid)
2945 {
2946   int i;
2947   /* now search for the appropriate table */
2948   for (i = 0;; i++)
2949     {
2950       if (cputabs[i].cputag == 0)
2951         break;
2952       if (cpuid == cputabs[i].cputag)
2953         return &cputabs[i];
2954     }
2955   Tprintf (0, "hwctable: cputabs_find_entry: WARNING: "
2956            "cpu_id = %d not defined.  No 'standard' counters are available\n",
2957            cpuid);
2958   return &cputabs[i];
2959 }
2960
2961 /* find Hwcentry table for <cpuid> */
2962 static Hwcentry*
2963 stdlist_get_table (int cpuid)
2964 {
2965   cpu_list_t* tmp = cputabs_find_entry (cpuid);
2966   if (tmp)
2967     return tmp->stdlist_table;
2968   return NULL;
2969 }
2970
2971 /* search the 'standard' list of counters for <name>,<regno> */
2972 /* note: <regno>=REGNO_ANY is a wildcard that matches any value. */
2973
2974 /* note: int_name==NULL is a wildcard */
2975 static const Hwcentry *
2976 ptrarray_find (const Hwcentry **array, const char *name, const char *int_name,
2977                int check_regno, regno_t regno)
2978 {
2979   const Hwcentry *pctr;
2980   if (!array)
2981     return NULL;
2982   for (int ii = 0; array[ii]; ii++)
2983     {
2984       pctr = array[ii];
2985       if (strcmp (pctr->name, name))
2986         continue;
2987       if (int_name && int_name[0] != 0 && pctr->int_name)
2988         {
2989           if (NULL == strstr (int_name, pctr->int_name))
2990             continue;
2991         }
2992       if (!check_regno)
2993         return pctr;
2994       else
2995         {
2996           /* duplicates aliases are allowed in table because of 6759307 */
2997           if (REG_LIST_IS_EMPTY (pctr->reg_list))
2998             {
2999               /* skip aliases that don't have a valid list of registers */
3000               hwcentry_print (1, "hwctable: stdlist_find_by_name:"
3001                               " WARNING: alias found, but event not supported by HW:",
3002                               pctr);
3003               continue;
3004             }
3005           if (!regno_is_valid (pctr, regno))
3006             {
3007               hwcentry_print (1, "hwctable: stdlist_find_by_name():"
3008                               " WARNING: alias found, but regno doesn't match:",
3009                               pctr);
3010               continue;
3011             }
3012           return pctr;
3013         }
3014     }
3015   return NULL;
3016 }
3017
3018 /* search the 'standard' list of counters for <name>,<regno> */
3019
3020 /* note: <regno>=REGNO_ANY is a wildcard that matches any value. */
3021 static const Hwcentry *
3022 static_table_find (const Hwcentry *table, const char *name, const char *int_name,
3023                    int check_regno, regno_t regno)
3024 {
3025   int sz;
3026   for (sz = 0; table && table[sz].name; sz++)
3027     ;
3028   if (!sz)
3029     return NULL;
3030   const Hwcentry ** list = calloc (sz + 1, sizeof (void*));
3031   if (!list)
3032     return NULL;
3033   for (int ii = 0; ii < sz; ii++)
3034     list[ii] = &table[ii];
3035   list[sz] = NULL;
3036   const Hwcentry *pctr = ptrarray_find (list, name, int_name, check_regno, regno);
3037   free (list);
3038   return pctr;
3039 }
3040
3041 #if !HWC_DEBUG
3042 #define stdlist_print(dbg_lvl,table)
3043 #else
3044
3045 /* print all Hwcentries in standard table.  Check for weird stuff */
3046 static void
3047 stdlist_print (int dbg_lvl, const Hwcentry* table)
3048 {
3049   const Hwcentry *pctr;
3050   if (!table)
3051     {
3052       Tprintf (0, "hwctable: stdlist_print: ERROR: "
3053                "table is invalid.\n");
3054       return;
3055     }
3056   for (pctr = table; pctr->name; pctr++)
3057     {
3058       int ii;
3059       hwcentry_print (dbg_lvl, "hwctable: stdlist: ", pctr);
3060       if (REG_LIST_IS_EMPTY (pctr->reg_list))
3061         {
3062           if (pctr->int_name || !pctr->metric)
3063             hwcentry_print (DBG_LT1, "hwctable: stdlist_print: WARNING: "
3064                             "no hardware event found for table entry", pctr);
3065           continue;
3066         }
3067       /* check if incorrect reg_num used in table */
3068       if (!regno_is_valid (pctr, pctr->reg_num))
3069         {
3070           hwcentry_print (DBG_LT0, "hwctable: stdlist_print: ERROR: "
3071                           "reg_num is not in table. ", pctr);
3072           continue;
3073         }
3074       for (ii = 0; ii < MAX_PICS; ii++)
3075         {
3076           regno_t regno = pctr->reg_list[ii];
3077           if (REG_LIST_EOL (regno))
3078             break;
3079         }
3080       if (ii > 1 && pctr->reg_num != REGNO_ANY)
3081         {
3082           /* several regnos were valid, but only one can be specified */
3083           if (pctr->metric || !pctr->int_name)
3084             {
3085               /* pctr is standard or a raw definition */
3086               /* (pctr is not an alias like cycles0) */
3087               hwcentry_print (DBG_LT0, "hwctable: stdlist_print: ERROR: "
3088                               "regno in table should have been REGNO_ANY. ",
3089                               pctr);
3090             }
3091         }
3092     }
3093 }
3094 #endif
3095
3096 /*---------------------------------------------------------------------------*/
3097 /* utilities for init */
3098
3099 /* try to bind counters to hw.  Return 0 on success, nonzero otherwise */
3100 static int
3101 test_hwcs (const Hwcentry* entries[], unsigned numctrs)
3102 {
3103   int rc = -1;
3104   hwc_event_t sample;
3105   int created = 0;
3106   hwcdrv_api_t *hwcdrv = get_hwcdrv ();
3107   Tprintf (DBG_LT2, "hwctable: test_hwcs()...\n");
3108   rc = hwcfuncs_bind_hwcentry (entries, numctrs);
3109   if (rc)
3110     {
3111       Tprintf (0, "hwctable: WARNING: test "
3112                "counters could not be created\n");
3113       goto end_test_hwcs;
3114     }
3115   created = 1;
3116   if (!signals_disabled)
3117     {
3118       (void) signal (HWCFUNCS_SIGNAL, SIG_IGN);
3119       signals_disabled = 1;
3120     }
3121   rc = hwcdrv->hwcdrv_start ();
3122   if (rc)
3123     {
3124       Tprintf (0, "hwctable: WARNING: test "
3125                "counters could not be started\n");
3126       goto end_test_hwcs;
3127     }
3128   rc = hwcdrv->hwcdrv_read_events (&sample, NULL);
3129   if (rc)
3130     Tprintf (0, "hwctable: WARNING: test sample failed\n");
3131   rc = 0;
3132 #if HWC_DEBUG
3133   {
3134     unsigned ii;
3135     Tprintf (DBG_LT1, "hwctable: test_hwcs(");
3136     for (ii = 0; ii < numctrs; ii++)
3137       Tprintf (DBG_LT1, "%s%s", ii ? "," : "", entries[ii]->name);
3138     Tprintf (DBG_LT1, ") PASS\n");
3139   }
3140 #endif
3141
3142 end_test_hwcs:
3143   if (created && hwcdrv->hwcdrv_free_counters ())
3144     Tprintf (0, "hwctable: WARNING: test counters could not be freed\n");
3145   return rc;
3146 }
3147
3148 #if !HWC_DEBUG
3149 #define check_tables()
3150 #else
3151
3152 /* check for typos in tables */
3153 static void
3154 check_tables ()
3155 {
3156   int i;
3157   /* now search the known table of counters */
3158   for (i = 0;; i++)
3159     {
3160       Hwcentry * pentry;
3161       int cputag = cputabs[i].cputag;
3162       if (cputag == 0)
3163         break;
3164       if (cputag == CPC_KPROF)
3165         continue;
3166       pentry = cputabs[i].stdlist_table;
3167       for (; pentry; pentry++)
3168         {
3169           if (!pentry->name)
3170             break;
3171           if (!pentry->int_name)
3172             {/* internal, only to supply ABST and timecvt */
3173               if (pentry->metric)
3174                 Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3175                          " internal && metric @%d, %s\n", cputag, pentry->name);
3176               if (pentry->reg_num != REGNO_ANY)
3177                 Tprintf (DBG_LT1, "hwctable: check_tables: WARNING:"
3178                          " internal && reg_num!=REGNO_ANY @%d, %s\n",
3179                          cputag, pentry->name);
3180               if (pentry->val != PRELOAD_DEF
3181                   && pentry->memop != ABST_EXACT_PEBS_PLUS1)
3182                 Tprintf (DBG_LT2, "hwctable: check_tables: INFO:"
3183                          " internal && custom val=%d @%d, %s\n",
3184                          pentry->val, cputag, pentry->name);
3185 #if 0
3186               if (!pentry->timecvt && pentry->memop == ABST_NONE)
3187                 Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3188                          " internal && not special! @%d, %s\n",
3189                          cputag, pentry->name);
3190 #endif
3191             }
3192           if (pentry->metric)
3193             { /* aliased */
3194               if (!pentry->int_name)
3195                 Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3196                          " aliased && !int_name @%d, %s\n", cputag, pentry->name);
3197 #if 0
3198               else if (!strcmp (pentry->name, pentry->int_name))
3199                 Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3200                          " name==int_name @%d, %s\n",
3201                          cputag, pentry->name);
3202 #endif
3203               if (pentry->reg_num != REGNO_ANY && pentry->reg_num != REGNO_INVALID)
3204                 Tprintf (DBG_LT1, "hwctable: check_tables: INFO:"
3205                          " aliased && custom reg_num==%d @%d, %s\n",
3206                          pentry->reg_num, cputag, pentry->name);
3207               if (pentry->reg_num == REGNO_INVALID)
3208                 Tprintf (DBG_LT2, "hwctable: check_tables: INFO:"
3209                          " aliased && reg_num==REGNO_INVALID @%d, %s\n",
3210                          cputag, pentry->name);
3211             }
3212           if (pentry->int_name && !pentry->metric)
3213             { /* convenience */
3214               if (!strcmp (pentry->name, pentry->int_name))
3215                   Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3216                            " convenience && name==int_name @%d, %s\n",
3217                            cputag, pentry->name);
3218               if (pentry->reg_num == REGNO_ANY)
3219                   Tprintf (DBG_LT0, "hwctable: check_tables: ERROR:"
3220                            " convenience && reg_num==REGNO_ANY @%d, %s\n",
3221                            cputag, pentry->name);
3222             }
3223         }
3224     }
3225 }
3226 #endif
3227
3228 static int try_a_counter ();
3229 static void hwc_process_raw_ctrs (int forKernel, Hwcentry ***pstd_out,
3230                                   Hwcentry ***praw_out, Hwcentry ***phidden_out,
3231                                   Hwcentry**static_tables,
3232                                   Hwcentry **raw_unfiltered_in);
3233
3234 /* internal call to initialize libs, ctr tables */
3235 static void
3236 setup_cpc_general (int skip_hwc_test)
3237 {
3238   const cpu_list_t* cputabs_entry;
3239   int rc = -1;
3240   Tprintf (DBG_LT2, "hwctable: setup_cpc()... \n");
3241   if (initialized)
3242     {
3243       Tprintf (0, "hwctable: WARNING: setup_cpc() has already been called\n");
3244       return;
3245     }
3246   initialized = 1;
3247   cpcx_cpuver = CPUVER_UNDEFINED;
3248   cpcx_cciname = NULL;
3249   cpcx_npics = 0;
3250   cpcx_docref = NULL;
3251   cpcx_support_bitmask = 0;
3252   for (int kk = 0; kk < 2; kk++)
3253     { // collect-0 and kernel-1
3254       cpcx_attrs[kk] = NULL;
3255       cpcx_std[kk] = NULL;
3256       cpcx_raw[kk] = NULL;
3257       cpcx_hidden[kk] = NULL;
3258       cpcx_max_concurrent[kk] = 0;
3259       cpcx_default_hwcs[kk] = NULL;
3260       cpcx_orig_default_hwcs[kk] = NULL;
3261       cpcx_has_precise[kk] = 0;
3262     }
3263   check_tables ();
3264   hwcdrv_api_t *hwcdrv = get_hwcdrv ();
3265   if (hwcdrv->hwcdrv_init_status)
3266     {
3267       Tprintf (0, "WARNING: setup_cpc_general() failed. init_status=%d \n",
3268                hwcdrv->hwcdrv_init_status);
3269       goto setup_cpc_wrapup;
3270     }
3271   hwcdrv->hwcdrv_get_info (&cpcx_cpuver, &cpcx_cciname, &cpcx_npics,
3272                            &cpcx_docref, &cpcx_support_bitmask);
3273
3274 #ifdef DISALLOW_USI_USII_6357446
3275   if (cpcx_cpuver == CPC_ULTRA1 || cpcx_cpuver == CPC_ULTRA2)
3276     {
3277       Tprintf (0, "hwctable: WARNING: setup_cpc(): cpu=%d"
3278                " US-I/US-II cannot provide profile interrupts\n", cpcx_cpuver);
3279       /* profiling interrupts don't work on US-I, US-II */
3280       hwcfuncs_int_logerr (GTXT ("UltraSPARC I and II cannot provide overflow interrupts\n"));
3281       goto setup_cpc_wrapup;
3282     }
3283 #endif
3284
3285 #ifdef DISALLOW_PENTIUM_PRO_MMX_7007575
3286   if (cpcx_cpuver == CPC_PENTIUM_PRO_MMX)
3287     {
3288       Tprintf (0, "hwctable: WARNING: setup_cpc(): cpu=%d"
3289                " `Pentium Pro with MMX, Pentium II' is not supported\n", cpcx_cpuver);
3290       hwcfuncs_int_logerr (GTXT ("libcpc cannot identify processor type\n"));
3291       goto setup_cpc_wrapup;
3292     }
3293 #endif
3294
3295   /* now search the known table of counters */
3296   cputabs_entry = cputabs_find_entry (cpcx_cpuver);
3297   if (cputabs_entry == NULL)
3298     {
3299       Tprintf (0, "hwctable: WARNING: setup_cpc(): cpu=%d"
3300                " could not be found in the tables\n", cpcx_cpuver);
3301       /* strange, should have at least selected "unknownlist" */
3302       hwcfuncs_int_logerr (GTXT ("Analyzer CPU table could not be found\n"));
3303       goto setup_cpc_wrapup;
3304     }
3305
3306   Hwcentry * valid_cpu_tables[2]; // [0]:static table of counters, [1]:static table of generic counters
3307   valid_cpu_tables[0] = cputabs_entry->stdlist_table;
3308   if (valid_cpu_tables[0] == NULL)
3309     {
3310       Tprintf (0, "hwctable: WARNING: setup_cpc(): "
3311                " valid_cpu_tables was NULL??\n");
3312       /* strange, someone put a NULL in the lookup table? */
3313       hwcfuncs_int_logerr (GTXT ("Analyzer CPU table is invalid\n"));
3314       goto setup_cpc_wrapup;
3315     }
3316   valid_cpu_tables[1] = papi_generic_list;
3317   Tprintf (DBG_LT2, "hwctable: setup_cpc(): getting descriptions \n");
3318   // populate cpcx_raw and cpcx_attr
3319   hwcdrv->hwcdrv_get_descriptions (hwc_cb, attrs_cb);
3320   for (int kk = 0; kk < 2; kk++)
3321     { // collect and er_kernel
3322       hwc_process_raw_ctrs (kk, &cpcx_std[kk], &cpcx_raw[kk], &cpcx_hidden[kk],
3323                             valid_cpu_tables, (Hwcentry**) unfiltered_raw.array);
3324       cpcx_has_precise[kk] = 0;
3325       for (int rr = 0; cpcx_raw[kk] && cpcx_raw[kk][rr]; rr++)
3326         {
3327           int memop = cpcx_raw[kk][rr]->memop;
3328           if (ABST_MEMSPACE_ENABLED (memop))
3329             {
3330               cpcx_has_precise[kk] = 1;
3331               break;
3332             }
3333         }
3334       cpcx_attrs[kk] = (char**) unfiltered_attrs.array;
3335       cpcx_max_concurrent[kk] = cpcx_npics;
3336     }
3337 #if 1 // 22897042 - DTrace cpc provider does not support profiling on multiple ctrs on some systems
3338   if ((cpcx_support_bitmask & HWCFUNCS_SUPPORT_OVERFLOW_CTR_ID) != HWCFUNCS_SUPPORT_OVERFLOW_CTR_ID)
3339     {
3340       // kernel profiling only supports one counter if overflowing counter can't be identified
3341       cpcx_max_concurrent[1] = cpcx_npics ? 1 : 0;
3342     }
3343 #endif
3344
3345   /* --- quick test of the cpc interface --- */
3346   if (skip_hwc_test)
3347     rc = 0;
3348   else
3349     rc = try_a_counter (0);
3350
3351   /* initialize the default counter string definition */
3352   for (int kk = 0; kk < 2; kk++)
3353     {
3354       char * default_exp = 0;
3355       int jj;
3356       for (jj = 0; (default_exp = cputabs_entry->default_exp_p[jj]); jj++)
3357         {
3358           int rc = hwc_lookup (kk, 0, default_exp, NULL, 0, NULL, NULL);
3359           if (rc > 0)
3360             break;
3361         }
3362       if (!default_exp)
3363         {
3364           char * fallback[3] = {NTXT ("insts,,cycles,,l3m"), NTXT ("insts,,cycles"), NTXT ("insts")};
3365           for (int ff = 0; ff < 3; ff++)
3366             {
3367               int rc = hwc_lookup (kk, 0, fallback[ff], NULL, 0, NULL, NULL);
3368               if (rc > 0)
3369                 {
3370                   default_exp = strdup (fallback[ff]);
3371                   break;
3372                 }
3373             }
3374         }
3375       cpcx_default_hwcs[kk] = default_exp;
3376       cpcx_orig_default_hwcs[kk] = default_exp;
3377     }
3378
3379 setup_cpc_wrapup:
3380   if (rc)
3381     {
3382       cpcx_npics = 0;
3383       /*
3384               ptr_list_free(&tmp_raw); // free stuff... YXXX
3385               ptr_list_free(&unfiltered_attrs);
3386        */
3387     }
3388   return;
3389 }
3390
3391 static void
3392 setup_cpcx ()
3393 {
3394   if (initialized)
3395     return;
3396   setup_cpc_general (0); // set up and include a hwc test run
3397 }
3398
3399 static void
3400 setup_cpc_skip_hwctest ()
3401 {
3402   if (initialized)
3403     return;
3404   setup_cpc_general (1); // set up but skip hwc test run
3405 }
3406
3407 static int
3408 try_a_counter (int forKernel)
3409 {
3410   if (!VALID_FOR_KERNEL (forKernel))
3411     return -1;
3412   int rc = -1;
3413   const Hwcentry * testevent;
3414   if (cpcx_std[forKernel] == NULL)
3415     {
3416       Tprintf (0, "hwctable: WARNING: cpcx_std not initialized");
3417       return 0; /* consider this an automatic PASS */
3418     }
3419   /* look for a valid table entry, only try valid_cpu_tables[0] */
3420   {
3421     testevent = cpcx_std[forKernel][0];
3422     if (!testevent || !testevent->name)
3423       {
3424         Tprintf (0, "hwctable: WARNING: no test metric"
3425                  " available to verify counters\n");
3426         return 0; /* consider this an automatic PASS */
3427       }
3428     if (REG_LIST_IS_EMPTY (testevent->reg_list))
3429       return 0; // weird
3430   }
3431   Hwcentry tmp_testevent;
3432   tmp_testevent = *testevent; /* shallow copy */
3433   if (tmp_testevent.int_name == NULL)
3434     {
3435       /* counter is defined in 'hidden' section of table, supply int_name */
3436       tmp_testevent.int_name = strdup (tmp_testevent.name);
3437     }
3438   Hwcentry * test_array[1] = {&tmp_testevent};
3439   rc = hwcfuncs_assign_regnos (test_array, 1); /* may modify test_array */
3440   if (rc)
3441     return rc;
3442   rc = test_hwcs ((const Hwcentry**) test_array, 1);
3443   if (rc == HWCFUNCS_ERROR_UNAVAIL)
3444     {
3445       // consider this a pass (allow HWC table to be printed)
3446       Tprintf (0, "hwctable: WARNING: "
3447                "cpc_bind_event() shows counters busy; allow to continue\n");
3448       return 0;
3449     }
3450   else if (rc)
3451     {
3452       // failed to start for some other reason
3453       Tprintf (0, "hwctable: WARNING: "
3454                "test of counter '%s' failed\n",
3455                testevent->name);
3456       return rc;
3457     }
3458   return 0;
3459 }
3460
3461 void
3462 hwc_update_val (Hwcentry *hwc)
3463 {
3464   if (hwc->ref_val == 0)
3465     hwc->ref_val = hwc->val; // save original reference
3466   int64_t newVal;
3467   hrtime_t min_time_nsec = hwc->min_time;
3468   if (min_time_nsec == HWCTIME_TBD)
3469     min_time_nsec = hwc->min_time_default;
3470   switch (min_time_nsec)
3471     {
3472     case 0: // disable time-based intervals
3473       // do not modify val
3474       return;
3475     case HWCTIME_ON:
3476     case HWCTIME_TBD:
3477       newVal = HWC_VAL_ON (hwc->ref_val);
3478       break;
3479     case HWCTIME_LO:
3480       newVal = HWC_VAL_LO (hwc->ref_val);
3481       break;
3482     case HWCTIME_HI:
3483       newVal = HWC_VAL_HI (hwc->ref_val);
3484       break;
3485     default:
3486       newVal = HWC_VAL_CUSTOM (hwc->ref_val, min_time_nsec);
3487       break;
3488     }
3489 #define MAX_INT_VAL (2*1000*1000*1000 + 1000100)// yuck, limited to signed int
3490   if (newVal >= MAX_INT_VAL)
3491     newVal = MAX_INT_VAL;
3492   hwc->val = newVal;
3493 }
3494
3495 /* convert value string to value and store result in hwc->val */
3496 /* This function moved here from collctrl.cc */
3497 /*
3498  * Keep the HWCTIME_* definitions in sync with those in
3499  * collctrl.cc Coll_Ctrl::add_hwcstring().
3500  */
3501 static int
3502 set_hwcval (Hwcentry *hwc, hrtime_t global_min_time_nsec, const char *valptr)
3503 {
3504   hwc->min_time_default = global_min_time_nsec;
3505   if (hwc->val == 1)
3506     {
3507       // An interval of 1 is used for certain types of count data.
3508       // (er_bit, er_generic, er_rock ...)
3509       // Hi and Lo do not apply.
3510       /* use the default */
3511     }
3512   else if (valptr == NULL || valptr[0] == 0 || strcmp (valptr, "auto") == 0)
3513     hwc->min_time = HWCTIME_TBD;
3514   else if (strcmp (valptr, "on") == 0)
3515     hwc->min_time = HWCTIME_ON;
3516   else if (strcmp (valptr, "lo") == 0 || strcmp (valptr, "low") == 0)
3517     hwc->min_time = HWCTIME_LO;
3518   else if (strcmp (valptr, "hi") == 0 || strcmp (valptr, "high") == 0
3519            || strcmp (valptr, "h") == 0)
3520     hwc->min_time = HWCTIME_HI;
3521   else
3522     {
3523       /* the remaining string should be a number > 0 */
3524       char *endchar = NULL;
3525       long long tmp = strtoll (valptr, &endchar, 0);
3526       int value = (int) tmp;
3527       if (*endchar != 0 || tmp <= 0 || value != tmp)
3528         {
3529           // also covers errno == ERANGE
3530           Tprintf (0, "hwctable: set_hwcval(): ERROR: "
3531                    "Invalid counter value %s for counter `%s'\n",
3532                    valptr, hwc->name);
3533           return -1;
3534         }
3535       if (tmp > UINT32_MAX / 2)
3536         {
3537           /* Roch B. says that we MUST do this check for er_kernel
3538              because some platforms deliver overflow interrupts without
3539              identifying which counter overflowed.  The only way to
3540              determine which counter overflowed is to have enough
3541              margin on 32 bit counters to make sure they don't
3542              wrap.
3543            */
3544           Tprintf (0, "hwctable: set_hwcval(): ERROR: "
3545                    "Counter value %s exceeds %lu\n",
3546                    valptr, (unsigned long) UINT32_MAX / 2);
3547           return -1;
3548         }
3549       /* set the value */
3550       if (value != 0)
3551         {
3552           if (hwc->ref_val == 0)
3553             hwc->ref_val = hwc->val; // save original reference
3554           hwc->val = value;
3555           hwc->min_time = 0; // turn off auto-adjust
3556         }
3557     }
3558   hwc_update_val (hwc);
3559   return 0;
3560 }
3561
3562 static char *
3563 canonical_name (const char *counter)
3564 {
3565   char *nameOnly = NULL;
3566   char *attrs = NULL;
3567   char tmpbuf[1024];
3568   tmpbuf[0] = 0;
3569   hwcfuncs_parse_ctr (counter, NULL, &nameOnly, &attrs, NULL, NULL);
3570   snprintf (tmpbuf + strlen (tmpbuf), sizeof (tmpbuf) - strlen (tmpbuf),
3571             "%s", nameOnly);
3572   if (attrs)
3573     {
3574       hwcfuncs_attr_t cpc2_attrs[HWCFUNCS_MAX_ATTRS];
3575       void * attr_mem;
3576       unsigned nattrs;
3577       int ii, jj;
3578
3579       /* extract attributes from counter */
3580       attr_mem = hwcfuncs_parse_attrs (counter, cpc2_attrs, HWCFUNCS_MAX_ATTRS,
3581                                        &nattrs, NULL);
3582       if (!attr_mem)
3583         {
3584           snprintf (tmpbuf + strlen (tmpbuf), sizeof (tmpbuf) - strlen (tmpbuf),
3585                     "~UNKNOWN");
3586           goto canonical_attrs_wrapup;
3587         }
3588
3589       /* sort the attributes */
3590       for (ii = 0; ii < (int) nattrs - 1; ii++)
3591         {
3592           for (jj = ii + 1; jj < nattrs; jj++)
3593             {
3594               int cmp = strcmp (cpc2_attrs[ii].ca_name,
3595                                 cpc2_attrs[jj].ca_name);
3596               if (cmp > 0)
3597                 {
3598                   hwcfuncs_attr_t tmp = cpc2_attrs[jj];
3599                   cpc2_attrs[jj] = cpc2_attrs[ii];
3600                   cpc2_attrs[ii] = tmp;
3601                 }
3602             }
3603         }
3604
3605       /* print attributes in canonical format */
3606       for (ii = 0; ii < nattrs; ii++)
3607         snprintf (tmpbuf + strlen (tmpbuf), sizeof (tmpbuf) - strlen (tmpbuf),
3608                   "~%s=0x%llx", cpc2_attrs[ii].ca_name, (long long) cpc2_attrs[ii].ca_val);
3609       free (attr_mem);
3610     }
3611 canonical_attrs_wrapup:
3612   free (nameOnly);
3613   free (attrs);
3614   return strdup (tmpbuf);
3615 }
3616
3617 /* process counter and value strings - put results in <*pret_ctr> */
3618
3619 /* Print errors to UEbuf for any failure that results in nonzero return */
3620 static int
3621 process_ctr_def (int forKernel, hrtime_t global_min_time_nsec,
3622                  const char *counter, const char *value, Hwcentry *pret_ctr,
3623                  char* UWbuf, size_t UWsz, char* UEbuf, size_t UEsz)
3624 {
3625   int rc = -1;
3626   char *nameOnly = NULL;
3627   char *attrs = NULL;
3628   char *regstr = NULL;
3629   int plus;
3630   regno_t regno;
3631   const Hwcentry *pfound = NULL;
3632   const char *uname = NULL;
3633   int disable_backtrack;
3634   UEbuf[0] = 0;
3635   UWbuf[0] = 0;
3636   Tprintf (DBG_LT3, "hwctable: process_ctr_def(): counter=%s value=%s \n",
3637            counter, value ? value : "NULL");
3638   hwcfuncs_parse_ctr (counter, &plus, &nameOnly, &attrs, &regstr, &regno);
3639
3640   /* search for the counter in the std and raw lists */
3641   {
3642     pfound = ptrarray_find ((const Hwcentry**) cpcx_std[forKernel], nameOnly, NULL, 1, regno);
3643     if (pfound)
3644       hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in stdlist:",
3645                       pfound);
3646   }
3647   if (!pfound)
3648     {
3649       pfound = ptrarray_find ((const Hwcentry**) cpcx_hidden[forKernel], nameOnly, NULL, 1, regno);
3650       if (pfound)
3651         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in stdlist(hidden):", pfound);
3652     }
3653   if (!pfound)
3654     {
3655       pfound = ptrarray_find_by_name (cpcx_raw[forKernel], nameOnly); /* (regno match checked later) */
3656       if (pfound)
3657         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in rawlist:", pfound);
3658     }
3659   if (!pfound)
3660     {
3661       pfound = ptrarray_find ((const Hwcentry**) cpcx_std[forKernel], nameOnly, NULL, 1, REGNO_ANY);
3662       if (pfound)
3663         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in stdlist but regno didn't match:", pfound);
3664     }
3665   if (!pfound)
3666     {
3667       pfound = ptrarray_find ((const Hwcentry**) cpcx_hidden[forKernel], nameOnly, NULL, 1, REGNO_ANY);
3668       if (pfound)
3669         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: found in stdlist(hidden) but regno didn't match:", pfound);
3670     }
3671   if (!pfound)
3672     {
3673       uint64_t val = 0;
3674       if (is_numeric (nameOnly, &val))
3675         {
3676           Hwcentry *tmp = alloc_shallow_copy (&empty_ctr); // Leaks?
3677           if (tmp)
3678             {
3679               tmp->name = strdup (nameOnly);
3680               regno_add (tmp, REGNO_ANY);
3681               pfound = tmp;
3682             }
3683         }
3684       if (pfound)
3685         hwcentry_print (DBG_LT1, "hwctable: process_ctr_def: counter specified by numeric value:", pfound);
3686     }
3687   if (!pfound)
3688     {
3689       snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3690                 GTXT ("Invalid HW counter name: %s\n"), nameOnly);
3691       snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3692                 GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
3693                 (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
3694       goto process_ctr_def_wrapup;
3695     }
3696
3697   /* counter found */
3698   *pret_ctr = *pfound; /* shallow copy */
3699   pret_ctr->int_name = NULL; /* so free doesn't try to free these pfound's ptrs */
3700   pret_ctr->name = NULL; /* so free doesn't try to free these pfound's ptrs */
3701
3702   /* update uname,memop */
3703   uname = counter;
3704   disable_backtrack = 0;
3705   if (plus != 0 || ABST_PLUS_BY_DEFAULT (pret_ctr->memop))
3706     {
3707       // attempt to process memoryspace profiling
3708       int message_printed = 0;
3709       if (cpcx_cpuver == CPUVER_GENERIC)
3710         {
3711           // accept plus, since we don't know what this CPU is
3712           snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3713                     GTXT ("`+' may not be correctly supported on `%s' because processor is not recognized."),
3714                     cpcx_cciname);
3715           pret_ctr->memop = ABST_LDST; // supply a backtracking data type - required for collector
3716         }
3717       else if (cpcx_cpuver == CPC_ULTRA1 || cpcx_cpuver == CPC_ULTRA2
3718                || cpcx_cpuver == CPC_ULTRA3 || cpcx_cpuver == CPC_ULTRA3_PLUS
3719                || cpcx_cpuver == CPC_ULTRA3_I || cpcx_cpuver == CPC_ULTRA4_PLUS
3720                || cpcx_cpuver == CPC_ULTRA4 || cpcx_cpuver == CPC_ULTRA_T1
3721                || cpcx_cpuver == CPC_ULTRA_T2 || cpcx_cpuver == CPC_ULTRA_T2P
3722                || cpcx_cpuver == CPC_ULTRA_T3)
3723         {
3724           if (!ABST_BACKTRACK_ENABLED (pret_ctr->memop))
3725             disable_backtrack = 1;
3726         }
3727       else if (cpcx_cpuver == CPC_SPARC_T4 || cpcx_cpuver == CPC_SPARC_T5
3728                || cpcx_cpuver == CPC_SPARC_T6 || cpcx_cpuver == CPC_SPARC_M4
3729                || cpcx_cpuver == CPC_SPARC_M5 || cpcx_cpuver == CPC_SPARC_M6
3730                || cpcx_cpuver == CPC_SPARC_M7 || cpcx_cpuver == CPC_SPARC_M8)
3731         {
3732           if (pret_ctr->memop != ABST_EXACT)
3733             disable_backtrack = 1;
3734         }
3735       else if (cpcx_cpuver == CPC_INTEL_NEHALEM || cpcx_cpuver == CPC_INTEL_WESTMERE
3736                || cpcx_cpuver == CPC_INTEL_SANDYBRIDGE
3737                || cpcx_cpuver == CPC_INTEL_IVYBRIDGE
3738                || cpcx_cpuver == CPC_INTEL_HASWELL
3739                || cpcx_cpuver == CPC_INTEL_BROADWELL
3740                || cpcx_cpuver == CPC_INTEL_SKYLAKE)
3741         {
3742           if (pret_ctr->memop != ABST_EXACT_PEBS_PLUS1)
3743             disable_backtrack = 1;
3744           else if (plus < 0)
3745             {
3746               // disabling memoryspace not supported for
3747               // remove specified -
3748               uname++;
3749               plus = 0;
3750               snprintf (UWbuf + strlen (UWbuf), UWsz - strlen (UWbuf),
3751                         GTXT ("Warning: `-' is not supported on `%s' -- memory reference backtracking will remain enabled for this counter\n"),
3752                         nameOnly);
3753             }
3754         }
3755       else
3756         {
3757           message_printed = 1;
3758           snprintf (UWbuf + strlen (UWbuf), UWsz - strlen (UWbuf),
3759                     GTXT ("Warning: `+' is not supported on `%s' -- memory reference backtracking will not be enabled for `%s'\n"),
3760                     cpcx_cciname, nameOnly);
3761           disable_backtrack = 1;
3762         }
3763       if (disable_backtrack)
3764         {
3765           if (plus != 0)
3766             uname++;    // remove specified + or -
3767           if (!message_printed && plus > 0)
3768             snprintf (UWbuf + strlen (UWbuf), UWsz - strlen (UWbuf),
3769                       GTXT ("Warning: `+' is not supported on `%s' -- memory reference backtracking will not be enabled for this counter\n"),
3770                       nameOnly);
3771         }
3772     }
3773   else
3774     disable_backtrack = 1;
3775   if (disable_backtrack || plus < 0)
3776     if (pret_ctr->memop != ABST_NOPC)
3777       pret_ctr->memop = ABST_NONE;
3778   if (pret_ctr->memop == ABST_NOPC)
3779     snprintf (UWbuf + strlen (UWbuf), UWsz - strlen (UWbuf),
3780               GTXT ("Warning: HW counter `%s' is not program-related -- callstacks will be not be recorded for this counter\n"),
3781               uname);
3782
3783   /* update reg_num */
3784   if (!regno_is_valid (pfound, regno))
3785     {
3786       char buf[1024];
3787       snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3788                 GTXT ("For counter `%s', %s is not a valid register; valid registers: %s\n"),
3789                 nameOnly, regstr ? regstr + 1 : "?",
3790                 get_regnolist (buf, sizeof (buf), pfound->reg_list, 1));
3791       goto process_ctr_def_wrapup;
3792     }
3793   if (pret_ctr->reg_num == REGNO_ANY)
3794     { /* table's regno is a wildcard */
3795       if (REG_LIST_EOL (pfound->reg_list[1]))
3796         {
3797           /* valid list only contains one regno, so use it */
3798           pret_ctr->reg_num = pfound->reg_list[0];
3799         }
3800       else
3801         pret_ctr->reg_num = regno;  /* use user's selection */
3802     }
3803
3804   /* update name and int_name */
3805   {
3806     // validate attributes
3807     if (attrs)
3808       {
3809         hwcfuncs_attr_t cpc2_attrs[HWCFUNCS_MAX_ATTRS];
3810         void * attr_mem;
3811         unsigned nattrs;
3812         char *errbuf;
3813         /* extract attributes from uname */
3814         attr_mem = hwcfuncs_parse_attrs (uname, cpc2_attrs, HWCFUNCS_MAX_ATTRS,
3815                                          &nattrs, &errbuf);
3816         if (!attr_mem)
3817           {
3818             snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3819                       "%s\n", errbuf);
3820             free (errbuf);
3821             goto process_ctr_def_wrapup;
3822           }
3823         /* make sure all attributes are valid */
3824         for (unsigned ii = 0; ii < nattrs; ii++)
3825           {
3826             if (!attr_is_valid (forKernel, cpc2_attrs[ii].ca_name))
3827               {
3828                 snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3829                           GTXT ("Invalid attribute specified for counter `%s': %s\n"),
3830                           nameOnly, cpc2_attrs[ii].ca_name);
3831                 snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3832                           GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
3833                           (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
3834                 free (attr_mem);
3835                 goto process_ctr_def_wrapup;
3836               }
3837             for (unsigned jj = ii + 1; jj < nattrs; jj++)
3838               {
3839                 if (strcmp (cpc2_attrs[ii].ca_name,
3840                             cpc2_attrs[jj].ca_name) == 0)
3841                   {
3842                     snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3843                               GTXT ("Duplicate attribute specified for counter `%s': %s\n"),
3844                               nameOnly, cpc2_attrs[ii].ca_name);
3845                     free (attr_mem);
3846                     goto process_ctr_def_wrapup;
3847                   }
3848               }
3849           }
3850         free (attr_mem);
3851       }
3852     pret_ctr->name = strdup (uname);
3853
3854     // assign int_name
3855     if (pfound->int_name)
3856       {
3857         // Counter is one of the following:
3858         // - aliased (e.g. cycles~system=1),
3859         // - convenience (e.g. cycles0~system=1),
3860         if (!attrs) // convert alias to internal name
3861           pret_ctr->int_name = strdup (pfound->int_name);
3862         else
3863           {
3864             // convert alias to internal name and
3865             // append user-supplied attributes
3866             size_t sz = strlen (pfound->int_name) + strlen (attrs) + 1;
3867             char *tbuf = calloc (sz, 1);
3868             if (tbuf)
3869               snprintf (tbuf, sz, "%s%s", pfound->int_name, attrs);
3870             pret_ctr->int_name = tbuf;
3871           }
3872       }
3873     else
3874       pret_ctr->int_name = strdup (uname);  // user-supplied name
3875   }
3876
3877   /* update val */
3878   if (set_hwcval (pret_ctr, global_min_time_nsec, value))
3879     {
3880       snprintf (UEbuf + strlen (UEbuf), UEsz - strlen (UEbuf),
3881                 GTXT ("Invalid interval for HW counter `%s': %s\n"),
3882                 nameOnly, value);
3883       goto process_ctr_def_wrapup;
3884     }
3885   hwcentry_print (DBG_LT2, "hwctable: process_ctr_def:", pret_ctr);
3886   rc = 0;
3887
3888 process_ctr_def_wrapup:
3889   free (regstr);
3890   free (attrs);
3891   free (nameOnly);
3892   return rc;
3893 }
3894
3895 /*---------------------------------------------------------------------------*/
3896
3897 /* external interfaces, see hwcentry.h for descriptions. */
3898
3899 extern int
3900 hwc_lookup (int forKernel, hrtime_t global_min_time_nsec, const char *instring,
3901             Hwcentry *caller_entries[], unsigned maxctrs, char **emsg, char **wmsg)
3902 {
3903   unsigned ii;
3904   char *instr_copy = NULL, *ss = NULL;
3905   unsigned numctrs = 0;
3906   int rc = 0;
3907   char *tokenptr[MAX_PICS * 2];
3908   unsigned numtokens = 0;
3909   char UEbuf[1024 * 5]; /* error message buffer; strdup of it is passed back to user  */
3910   char UWbuf[1024 * 5]; /* warning message buffer; strdup of it is passed back to user  */
3911   if (emsg)
3912     *emsg = NULL;
3913   if (wmsg)
3914     *wmsg = NULL;
3915   UEbuf[0] = 0;
3916   UWbuf[0] = 0;
3917
3918   // supply temporary result buffers as needed
3919   Hwcentry tmp_entry_table[MAX_PICS];
3920   Hwcentry * tmp_entries[MAX_PICS];
3921   Hwcentry **entries;
3922   if (caller_entries)
3923     entries = caller_entries;
3924   else
3925     {
3926       // user doesn't care about results; provide temporary storage for results
3927       for (ii = 0; ii < MAX_PICS; ii++)
3928         tmp_entries[ii] = &tmp_entry_table[ii];
3929       entries = tmp_entries;
3930       maxctrs = MAX_PICS;
3931     }
3932   Tprintf (DBG_LT1, "hwctable: hwc_lookup(%s)\n",
3933            instring ? instring : "NULL");
3934
3935   /* clear <entries> first - prevent seg faults in hwc_lookup_wrapup */
3936   for (ii = 0; ii < maxctrs; ii++)
3937     *entries[ii] = empty_ctr;
3938   if (!instring)
3939     {
3940       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3941                 GTXT ("No HW counters were specified."));
3942       rc = -1;
3943       goto hwc_lookup_wrapup;
3944     }
3945
3946   /* make sure tables are initialized */
3947   setup_cpc_skip_hwctest ();
3948   if (cpcx_npics == 0)
3949     {
3950       if (cpcx_cpuver < 0)
3951         {
3952           char buf[1024];
3953           *buf = 0;
3954           char *pch = hwcfuncs_errmsg_get (buf, sizeof (buf), 0); /* get first err msg, disable capture */
3955           if (*pch)
3956             snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3957                       GTXT ("HW counter profiling is not supported on this system: %s%s"),
3958                       pch, pch[strlen (pch) - 1] == '\n' ? "" : "\n");
3959           else
3960             snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3961                       GTXT ("HW counter profiling is not supported on this system\n"));
3962         }
3963       else
3964         snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3965                   GTXT ("HW counter profiling is not supported on '%s'\n"),
3966                   cpcx_cciname);
3967       rc = -1;
3968       goto hwc_lookup_wrapup;
3969     }
3970   ss = instr_copy = strdup (instring);
3971   while (*ss != 0 && (*ss == ' ' || *ss == '\t'))
3972     ss++;
3973   tokenptr[numtokens++] = ss;
3974   do
3975     {
3976       /* find end of previous token, replace w/ NULL, skip whitespace, set <tokenptr>, repeat */
3977       for (; *ss; ss++)
3978         {
3979           if (*ss == ',' || *ss == ' ' || *ss == '\t')
3980             {
3981               /* end of previous token found */
3982               *ss = 0; /* terminate the previous token */
3983               ss++;
3984               while (*ss != 0 && (*ss == ' ' || *ss == '\t'))
3985                 ss++;
3986               if (*ss)
3987                 tokenptr[numtokens++] = ss;
3988               break; // from for loop
3989             }
3990         }
3991     }
3992   while (*ss && numtokens < (MAX_PICS * 2));
3993
3994   if (*ss)
3995     {
3996       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3997                 GTXT ("The number of HW counters specified exceeds internal resources\n"));
3998       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
3999                 GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
4000                 (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
4001       rc = -1;
4002       goto hwc_lookup_wrapup;
4003     }
4004   Tprintf (DBG_LT3, "hwctable: hwc_lookup(): numtokens=%d\n", numtokens);
4005
4006   /* look up individual counters */
4007   {
4008     int fail = 0;
4009     for (ii = 0; ii < numtokens && numctrs < maxctrs; ii += 2)
4010       {
4011         const char *counter;
4012         const char *value;
4013         Hwcentry *pret_ctr = entries[numctrs];
4014
4015         /* assign the tokens to ctrnames, timeoutValues. */
4016         counter = tokenptr[ii];
4017         if (ii + 1 < numtokens)
4018           value = tokenptr[ii + 1];
4019         else
4020           value = 0;
4021         if (process_ctr_def (forKernel, global_min_time_nsec, counter, value, pret_ctr,
4022                              UWbuf + strlen (UWbuf),
4023                              sizeof (UWbuf) - strlen (UWbuf),
4024                              UEbuf + strlen (UEbuf),
4025                              sizeof (UEbuf) - strlen (UEbuf)))
4026           {
4027             /* could choose to set fail=1 and continue here,
4028                but errmsgs would be aggregated (messy) */
4029             rc = -1;
4030             goto hwc_lookup_wrapup;
4031           }
4032         numctrs++;
4033       }
4034     if (fail)
4035       {
4036         rc = -1;
4037         goto hwc_lookup_wrapup;
4038       }
4039   }
4040
4041   if (!numctrs)
4042     {
4043       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4044                 GTXT ("No HW counters were specified.\n"));
4045       rc = -1;
4046       goto hwc_lookup_wrapup;
4047     }
4048   if (numctrs > cpcx_max_concurrent[forKernel])
4049     {
4050       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4051                 GTXT ("The HW counter configuration could not be loaded: More than %d counters were specified\n"), cpcx_max_concurrent[forKernel]);
4052       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4053                 GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
4054                 (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
4055       rc = -1;
4056       goto hwc_lookup_wrapup;
4057     }
4058
4059 hwc_lookup_wrapup:
4060   free (instr_copy);
4061   if (wmsg && strlen (UWbuf))
4062     *wmsg = strdup (UWbuf);
4063   if (emsg && strlen (UEbuf))
4064     *emsg = strdup (UEbuf);
4065   if (rc == 0)
4066     rc = numctrs;
4067   return rc;
4068 }
4069
4070 extern char *
4071 hwc_validate_ctrs (int forKernel, Hwcentry *entries[], unsigned numctrs)
4072 {
4073   char UEbuf[1024 * 5];
4074   UEbuf[0] = 0;
4075
4076   /* search for obvious duplicates*/
4077   unsigned ii;
4078   for (ii = 0; ii < numctrs; ii++)
4079     {
4080       regno_t reg_a = entries[ii]->reg_num;
4081       if (reg_a != REGNO_ANY)
4082         {
4083           unsigned jj;
4084           for (jj = ii + 1; jj < numctrs; jj++)
4085             {
4086               int reg_b = entries[jj]->reg_num;
4087               if (reg_a == reg_b)
4088                 {
4089                   snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4090                             GTXT ("Only one HW counter is allowed per register.  The following counters use register %d: \n"),
4091                             reg_a);
4092                   for (jj = 0; jj < numctrs; jj++)
4093                     {
4094                       char buf[256];
4095                       int reg_b = entries[jj]->reg_num;
4096                       if (reg_a == reg_b)
4097                         snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4098                                   GTXT ("  %d. %s\n"), jj + 1,
4099                                   hwc_hwcentry_specd_string (buf, sizeof (buf),
4100                                                              entries[jj]));
4101                     }
4102                   return strdup (UEbuf);
4103                 }
4104             }
4105         }
4106     }
4107
4108   /* test counters */
4109   hwcfuncs_errmsg_get (NULL, 0, 1); /* enable errmsg capture */
4110   int hwc_rc = hwcfuncs_assign_regnos (entries, numctrs);
4111   if (!hwc_rc)
4112     hwc_rc = test_hwcs ((const Hwcentry**) entries, numctrs);
4113   if (hwc_rc)
4114     {
4115       if (cpcx_cpuver == CPC_PENTIUM_4_HT || cpcx_cpuver == CPC_PENTIUM_4)
4116         {
4117           snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4118                     GTXT ("HW counter profiling is disabled unless only one logical CPU per HyperThreaded processor is online (see psradm)\n"));
4119           return strdup (UEbuf);
4120         }
4121       char buf[1024];
4122       *buf = 0;
4123       char * pch = hwcfuncs_errmsg_get (buf, sizeof (buf), 0); /* get first err msg, disable capture */
4124       if (*pch)
4125         snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4126                   GTXT ("The HW counter configuration could not be loaded: %s%s"),
4127                   pch, pch[strlen (pch) - 1] == '\n' ? "" : "\n");
4128       else
4129         snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4130                   GTXT ("The HW counter configuration could not be loaded\n"));
4131       snprintf (UEbuf + strlen (UEbuf), sizeof (UEbuf) - strlen (UEbuf),
4132                 GTXT ("Run \"%s -h\" with no other arguments for more information on HW counters on this system.\n"),
4133                 (IS_KERNEL (forKernel) ? "er_kernel" : "collect"));
4134       return strdup (UEbuf);
4135     }
4136   return NULL;
4137 }
4138
4139 extern Hwcentry *
4140 hwc_post_lookup (Hwcentry * pret_ctr, char *counter, char * int_name, int cpuver)
4141 {
4142   const Hwcentry *pfound;
4143   regno_t regno;
4144   char *nameOnly = NULL;
4145   char *attrs = NULL;
4146
4147   /* fields in pret_ctr (name and int_name) should already be free */
4148   hwcfuncs_parse_ctr (counter, NULL, &nameOnly, &attrs, NULL, &regno);
4149
4150   /* look for it in the canonical list */
4151   pfound = static_table_find (stdlist_get_table (cpuver),
4152                               nameOnly, int_name, 0, REGNO_ANY);
4153   if (!pfound)  /* try the generic list */
4154     pfound = static_table_find (papi_generic_list,
4155                                 nameOnly, int_name, 0, REGNO_ANY);
4156   if (pfound)
4157     {
4158       /* in standard list */
4159       *pret_ctr = *pfound; /* shallow copy */
4160       if (pret_ctr->int_name)
4161         {
4162           // aliased counter
4163           pret_ctr->int_name = strdup (pret_ctr->int_name);
4164           if (pret_ctr->short_desc == NULL)
4165             {
4166               // look for short_desc of corresponding raw counter
4167               const Hwcentry *praw = static_table_find (stdlist_get_table (cpuver),
4168                                                         pret_ctr->int_name, NULL, 0, REGNO_ANY);
4169               if (praw && praw->short_desc)
4170                 pret_ctr->short_desc = strdup (praw->short_desc);
4171             }
4172         }
4173       else
4174         pret_ctr->int_name = strdup (counter);
4175       if (pret_ctr->reg_num == REGNO_ANY)
4176         pret_ctr->reg_num = regno;  /* table's regno is a wildcard */
4177     }
4178   else
4179     {
4180       /* not a standard counter */
4181       *pret_ctr = empty_ctr;
4182       pret_ctr->int_name = strdup (counter);
4183       pret_ctr->reg_num = regno;
4184     }
4185
4186   /* update the name */
4187   if (attrs)
4188     {
4189       pret_ctr->name = canonical_name (counter);
4190       if (pret_ctr->metric)
4191         {
4192           // metric text is supplied from a table. (User supplied HWC alias)
4193           // Append user-supplied attributes to metric name:
4194           size_t len = strlen (pret_ctr->metric) + strlen (attrs) + 4;
4195           char *pch = calloc (len, 1);
4196           if (pch)
4197             snprintf (pch, len, "%s (%s)", pret_ctr->metric, attrs);
4198           pret_ctr->metric = pch; // leaks
4199         }
4200     }
4201   else
4202     pret_ctr->name = strdup (nameOnly);
4203
4204   if (pfound)
4205     hwcentry_print (DBG_LT2, "hwctable: hwc_post_lookup: found: ", pret_ctr);
4206   else
4207     hwcentry_print (DBG_LT2, "hwctable: hwc_post_lookup: default: ", pret_ctr);
4208   free (attrs);
4209   free (nameOnly);
4210   return pret_ctr;
4211 }
4212
4213 static const char *
4214 hwc_on_lo_hi (const Hwcentry *pctr)
4215 {
4216   char* rate;
4217   {
4218     switch (pctr->min_time)
4219       {
4220       case (HWCTIME_LO):
4221         rate = NTXT ("lo");
4222         break;
4223       case (HWCTIME_ON):
4224         rate = NTXT ("on");
4225         break;
4226       case (HWCTIME_HI):
4227         rate = NTXT ("hi");
4228         break;
4229       case (0):
4230         rate = NULL; // null => use interval count
4231         break;
4232       default:
4233       case (HWCTIME_TBD):
4234         rate = NTXT ("on");
4235         break;
4236       }
4237   }
4238   return rate; //strdup( rate );
4239 }
4240
4241 extern char *
4242 hwc_rate_string (const Hwcentry *pctr, int force_numeric)
4243 {
4244   const char * rateString = hwc_on_lo_hi (pctr);
4245   char buf[128];
4246   if (!rateString || force_numeric)
4247     {
4248       snprintf (buf, sizeof (buf), NTXT ("%d"), pctr->val);
4249       rateString = buf;
4250     }
4251   return strdup (rateString);
4252 }
4253
4254 static char metricbuf[2048];
4255
4256 extern char *
4257 hwc_i18n_metric (const Hwcentry *pctr)
4258 {
4259   if (pctr->metric != NULL)
4260     snprintf (metricbuf, sizeof (metricbuf), NTXT ("%s"), PTXT (pctr->metric));
4261   else if (pctr->name != NULL)
4262     snprintf (metricbuf, sizeof (metricbuf), GTXT ("%s Events"), pctr->name);
4263   else if (pctr->int_name != NULL)
4264     snprintf (metricbuf, sizeof (metricbuf), GTXT ("%s Events"), pctr->int_name);
4265   else
4266     snprintf (metricbuf, sizeof (metricbuf), GTXT ("Undefined Events"));
4267   return metricbuf;
4268 }
4269
4270 /* return cpu version, should only be called when about to generate an experiment,
4271    not when reading back an experiment */
4272 #if 0 /* called by ... */
4273 . / perfan / collect / src / collect.cc : start : 245 : cpuver = hwc_get_cpc_cpuver ();
4274 . / ccr_components / Collector_Interface / collctrl.cc : constructor : 202 : cpcx_cpuver = hwc_get_cpc_cpuver ();
4275 . / perfan / dbe / src / Dbe.cc : 3041 : JApplication::cpuver = hwc_get_cpc_cpuver ();
4276 . / perfan / dbe / src / Dbe.cc : 3164 : JApplication::cpuver = hwc_get_cpc_cpuver ();
4277
4278 note:
4279 cpc_getcpuver () : only papi, ostest, this and hwprofile.c call it
4280 #endif
4281 int
4282 hwc_get_cpc_cpuver ()
4283 {
4284   setup_cpcx ();
4285   return cpcx_cpuver;
4286 }
4287
4288 extern char*
4289 hwc_get_cpuname (char *buf, size_t buflen)
4290 {
4291   setup_cpcx ();
4292   if (!buf || !buflen)
4293     return buf;
4294   buf[0] = 0;
4295   if (cpcx_cciname)
4296     {
4297       strncpy (buf, cpcx_cciname, buflen - 1);
4298       buf[buflen - 1] = 0;
4299     }
4300   return buf;
4301 }
4302
4303 extern char*
4304 hwc_get_docref (char *buf, size_t buflen)
4305 {
4306   setup_cpcx ();
4307   if (!buf || !buflen)
4308     return buf;
4309   buf[0] = 0;
4310   if (cpcx_docref)
4311     {
4312       strncpy (buf, cpcx_docref, buflen - 1);
4313       buf[buflen - 1] = 0;
4314     }
4315   return buf;
4316 }
4317
4318 //TBR:
4319
4320 extern char*
4321 hwc_get_default_cntrs ()
4322 {
4323   setup_cpcx ();
4324   if (cpcx_default_hwcs[0] != NULL)
4325     return strdup (cpcx_default_hwcs[0]); // TBR deprecate this
4326   return NULL;
4327 }
4328
4329 extern char*
4330 hwc_get_default_cntrs2 (int forKernel, int style)
4331 {
4332   setup_cpcx ();
4333   if (!VALID_FOR_KERNEL (forKernel))
4334     return NULL;
4335   char *cpcx_default = cpcx_default_hwcs[forKernel];
4336   if (cpcx_default == NULL || cpcx_npics == 0)
4337     return NULL;
4338   if (style == 1)
4339     return strdup (cpcx_default);
4340
4341   // style == 2
4342   // we will replace "," delimiters with " -h " (an extra 3 chars per HWC)
4343   char *s = (char *) malloc (strlen (cpcx_default) + 3 * cpcx_npics);
4344   if (s == NULL) return s;
4345   char *p = s;
4346   char *q = cpcx_default;
4347   int i;
4348   for (i = 0; i < cpcx_npics; i++)
4349     {
4350       int qlen = strlen (q);
4351       if (qlen == 0)
4352         {
4353           p[0] = '\0';
4354           break;
4355         }
4356       // add " -h " if not the first HWC
4357       if (i != 0)
4358         {
4359           p[0] = ' ';
4360           p[1] = '-';
4361           p[2] = 'h';
4362           p[3] = ' ';
4363           p += 4;
4364         }
4365
4366       // find second comma
4367       char *r = strchr (q, ',');
4368       if (r)
4369         r = strchr (r + 1, ',');
4370
4371       // we didn't find one, so the rest of the string is the last HWC
4372       if (r == NULL)
4373         {
4374           // EUGENE could check i==cpcx_npicx-1, but what if it isn't???
4375           strcpy (p, q);
4376           if (p[qlen - 1] == ',')
4377             qlen--;
4378           p[qlen] = '\0';
4379           break;
4380         }
4381
4382       // copy the HWC, trim trailing comma, add null char
4383       qlen = r - q - 1;
4384       strcpy (p, q);
4385       if (p[qlen - 1] == ',')
4386         qlen--;
4387       p += qlen;
4388       p[0] = '\0';
4389       q = r + 1;
4390     }
4391   return s;
4392 }
4393
4394 extern char*
4395 hwc_get_orig_default_cntrs (int forKernel)
4396 {
4397   setup_cpcx ();
4398   if (!VALID_FOR_KERNEL (forKernel))
4399     return NULL;
4400   if (cpcx_orig_default_hwcs[forKernel] != NULL)
4401     return strdup (cpcx_orig_default_hwcs[forKernel]);
4402   return NULL;
4403 }
4404
4405 extern const char *
4406 hwc_memop_string (ABST_type memop)
4407 {
4408   const char * s;
4409   switch (memop)
4410     {
4411     case ABST_NONE:
4412       s = "";
4413       break;
4414     case ABST_LOAD:
4415       s = GTXT ("load ");
4416       break;
4417     case ABST_STORE:
4418       s = GTXT ("store ");
4419       break;
4420     case ABST_LDST:
4421     case ABST_US_DTLBM:
4422     case ABST_LDST_SPARC64:
4423       s = GTXT ("load-store ");
4424       break;
4425     case ABST_EXACT_PEBS_PLUS1:
4426     case ABST_EXACT:
4427       s = GTXT ("memoryspace ");
4428       break;
4429     case ABST_COUNT:
4430       s = GTXT ("count ");
4431       break;
4432     case ABST_NOPC:
4433       s = GTXT ("not-program-related ");
4434       break;
4435     default:
4436       s = ""; // was "ABST_UNK", but that's meaningless to users
4437       break;
4438     }
4439   return s;
4440 }
4441
4442 static const char *
4443 timecvt_string (int timecvt)
4444 {
4445   if (timecvt > 0)
4446     return GTXT ("CPU-cycles");
4447   if (timecvt < 0)
4448     return GTXT ("ref-cycles");
4449   return GTXT ("events");
4450 }
4451
4452 int show_regs = 0;  // The register setting is available on Solaris only
4453
4454 /*
4455  * print the specified strings in aligned columns
4456  */
4457 static void
4458 format_columns (char *buf, int bufsiz, char *s1, char *s2, const char *s3,
4459                 const char *s4, char *s5, const char *s6)
4460 {
4461   // NULL strings are blanks
4462   char *blank = NTXT ("");
4463   if (s2 == NULL)
4464     s2 = blank;
4465   if (s3 == NULL)
4466     s3 = blank;
4467   if (s6 == NULL)
4468     s6 = blank;
4469
4470   // get the lengths and target widths
4471   // (s6 can be as wide as it likes)
4472   int l1 = strlen (s1), n1 = 10, l2 = strlen (s2), n2 = 13;
4473   int l3 = strlen (s3), n3 = 20, l4 = strlen (s4), n4 = 10, n5;
4474   char divide = ' ';
4475
4476   // adjust widths, stealing from one column to help a neighbor
4477   // There's a ragged boundary between s2 and s3.
4478   // So push this boundary to the right.
4479   n2 += n3 - l3;
4480   n3 -= n3 - l3;
4481
4482   // If s3 is empty, push the boundary over to s4.
4483   if (l3 == 0)
4484     {
4485       n2 += n4 - l4;
4486       n4 -= n4 - l4;
4487     }
4488
4489   // If there's enough room to fit s1 and s2, do so.
4490   if (n1 + n2 >= l1 + l2)
4491     {
4492       if (n1 < l1)
4493         {
4494           n2 -= l1 - n1;
4495           n1 += l1 - n1;
4496         }
4497       if (n2 < l2)
4498         {
4499           n1 -= l2 - n2;
4500           n2 += l2 - n2;
4501         }
4502     }
4503   else
4504     {
4505       // not enough room, so we need to divide the line
4506       n3 += 4 // 4-blank margin
4507               + n1 // 1st column
4508               + 1 // space between 1st and 2nd columns
4509               + n2 // 2nd column
4510               + 1; // space between 2nd and 3th columns
4511       divide = '\n';
4512
4513       // make 1st column large enough
4514       if (n1 < l1)
4515         n1 = l1;
4516
4517       // width of 2nd column no longer matters since we divided the line
4518       n2 = 0;
4519     }
4520
4521   if (show_regs)
4522     {
4523       // fifth column should be wide enough for regnolist
4524       //     see function get_regnolist()
4525       if (cpcx_npics < 10)
4526         n5 = cpcx_npics; // one char per regno
4527       else
4528         n5 = 16 + 3 * (cpcx_npics - 9); // spaces between regnos and some regnos are 2-char wide
4529       // ... and be wide enough for header "regs"
4530       if (n5 < 4)
4531         n5 = 4;
4532
4533       // print to buffer
4534       // (don't need a space before s4 since historical precedent to have a trailing space in s3)
4535       snprintf (buf, bufsiz, "%-*s %-*s%c%*s%*s %-*s %s",
4536                 n1, s1, n2, s2, divide, n3, s3, n4, s4, n5, s5, s6);
4537     }
4538   else
4539     snprintf (buf, bufsiz, "%-*s %-*s%c%*s%*s %s",
4540               n1, s1, n2, s2, divide, n3, s3, n4, s4, s6);
4541   for (int i = strlen (buf); i > 0; i--)
4542     if (buf[i] == ' ' || buf[i] == '\t')
4543       buf[i] = 0;
4544     else
4545       break;
4546 }
4547
4548 /* routine to return HW counter string formatted and i18n'd */
4549 static char *
4550 hwc_hwcentry_string_internal (char *buf, size_t buflen, const Hwcentry *ctr,
4551                               int show_short_desc)
4552 {
4553   char regnolist[256];
4554   if (!buf || !buflen)
4555     return buf;
4556   if (ctr == NULL)
4557     {
4558       snprintf (buf, buflen, GTXT ("HW counter not available"));
4559       return buf;
4560     }
4561   char *desc = NULL;
4562   if (show_short_desc)
4563     desc = ctr->short_desc;
4564   if (desc == NULL)
4565     desc = ctr->metric ? hwc_i18n_metric (ctr) : NULL;
4566   format_columns (buf, buflen, ctr->name, ctr->int_name,
4567                   hwc_memop_string (ctr->memop), timecvt_string (ctr->timecvt),
4568                   get_regnolist (regnolist, sizeof (regnolist), ctr->reg_list, 2),
4569                   desc);
4570   return buf;
4571 }
4572
4573 /* routine to return HW counter string formatted and i18n'd */
4574 extern char *
4575 hwc_hwcentry_string (char *buf, size_t buflen, const Hwcentry *ctr)
4576 {
4577   return hwc_hwcentry_string_internal (buf, buflen, ctr, 0);
4578 }
4579
4580 /* routine to return HW counter string formatted and i18n'd */
4581 extern char *
4582 hwc_hwcentry_specd_string (char *buf, size_t buflen, const Hwcentry *ctr)
4583 {
4584   const char *memop, *timecvt;
4585   char descstr[1024];
4586   if (!buf || !buflen)
4587     return buf;
4588   if (ctr == NULL)
4589     {
4590       snprintf (buf, buflen, GTXT ("HW counter not available"));
4591       return buf;
4592     }
4593   timecvt = timecvt_string (ctr->timecvt);
4594   if (ctr->memop)
4595     memop = hwc_memop_string (ctr->memop);
4596   else
4597     memop = "";
4598   if (ctr->metric != NULL)  /* a standard counter for a specific register */
4599     snprintf (descstr, sizeof (descstr), " (`%s'; %s%s)",
4600               hwc_i18n_metric (ctr), memop, timecvt);
4601   else  /* raw counter */
4602     snprintf (descstr, sizeof (descstr), " (%s%s)", memop, timecvt);
4603
4604   char *rateString = hwc_rate_string (ctr, 1);
4605   snprintf (buf, buflen, "%s,%s%s", ctr->name,
4606             rateString ? rateString : "", descstr);
4607   free (rateString);
4608   return buf;
4609 }
4610
4611 unsigned
4612 hwc_get_max_regs ()
4613 {
4614   setup_cpcx ();
4615   return cpcx_npics;
4616 }
4617
4618 unsigned
4619 hwc_get_max_concurrent (int forKernel)
4620 {
4621   setup_cpcx ();
4622   if (!VALID_FOR_KERNEL (forKernel))
4623     return 0;
4624   return cpcx_max_concurrent[forKernel];
4625 }
4626
4627 char**
4628 hwc_get_attrs (int forKernel)
4629 {
4630   setup_cpcx ();
4631   if (!VALID_FOR_KERNEL (forKernel))
4632     return NULL;
4633   return cpcx_attrs[forKernel];
4634 }
4635
4636 Hwcentry **
4637 hwc_get_std_ctrs (int forKernel)
4638 {
4639   setup_cpcx ();
4640   if (!VALID_FOR_KERNEL (forKernel))
4641     return NULL;
4642   return cpcx_std[forKernel];
4643 }
4644
4645 Hwcentry **
4646 hwc_get_raw_ctrs (int forKernel)
4647 {
4648   setup_cpcx ();
4649   if (!VALID_FOR_KERNEL (forKernel))
4650     return NULL;
4651   return cpcx_raw[forKernel];
4652 }
4653
4654 /* Call an action function for each attribute supported */
4655 unsigned
4656 hwc_scan_attrs (void (*action)(const char *attr, const char *desc))
4657 {
4658   setup_cpcx ();
4659   int cnt = 0;
4660   for (int ii = 0; cpcx_attrs[0] && cpcx_attrs[0][ii]; ii++, cnt++)
4661     {
4662       if (action)
4663         action (cpcx_attrs[0][ii], NULL);
4664     }
4665   if (!cnt && action)
4666     action (NULL, NULL);
4667   return cnt;
4668 }
4669
4670 unsigned
4671 hwc_scan_std_ctrs (void (*action)(const Hwcentry *))
4672 {
4673   setup_cpcx ();
4674   Tprintf (DBG_LT1, "hwctable: hwc_scan_standard_ctrs()...\n");
4675   int cnt = 0;
4676   for (int ii = 0; cpcx_std[0] && cpcx_std[0][ii]; ii++, cnt++)
4677     if (action)
4678       action (cpcx_std[0][ii]);
4679   if (!cnt && action)
4680     action (NULL);
4681   return cnt;
4682 }
4683
4684 /* Call an action function for each counter supported */
4685 /* action is called with NULL when all counters have been seen */
4686 unsigned
4687 hwc_scan_raw_ctrs (void (*action)(const Hwcentry *))
4688 {
4689   setup_cpcx ();
4690   Tprintf (DBG_LT1, "hwctable: hwc_scan_raw_ctrs()...\n");
4691   int cnt = 0;
4692   for (int ii = 0; cpcx_raw[0] && cpcx_raw[0][ii]; ii++, cnt++)
4693     if (action)
4694       action (cpcx_raw[0][ii]);
4695   if (!cnt && action)
4696     action (NULL);
4697   return cnt;
4698 }
4699
4700 static void
4701 hwc_usage_raw_overview_sparc (FILE *f_usage, int cpuver)
4702 {
4703   /* All these cpuver's use cputabs[]==sparc_t5_m6 anyhow. */
4704   if ((cpuver == CPC_SPARC_M5) || (cpuver == CPC_SPARC_M6)
4705       || (cpuver == CPC_SPARC_T5) || (cpuver == CPC_SPARC_T6))
4706     cpuver = CPC_SPARC_M4; // M4 was renamed to M5
4707
4708   /* While there are small differences between
4709    *     cputabs[]== sparc_t4
4710    *     cputabs[]== sparc_t5_m6
4711    * they are in HWCs we don't discuss in the overview anyhow.
4712    * So just lump them in with T4.
4713    */
4714   if (cpuver == CPC_SPARC_M4)
4715     cpuver = CPC_SPARC_T4;
4716
4717   /* Check for the cases we support. */
4718   if (cpuver != CPC_SPARC_T4 && cpuver != CPC_SPARC_M7 && cpuver != CPC_SPARC_M8)
4719     return;
4720   fprintf (f_usage, GTXT ("    While the above aliases represent the most useful hardware counters\n"
4721                           "    for this processor, a full list of raw (unaliased) counter names appears\n"
4722                           "    below.  First is an overview of some of these names.\n\n"));
4723   fprintf (f_usage, GTXT ("        == Cycles.\n"
4724                           "        Count active cycles with\n"
4725                           "            Cycles_user\n"
4726                           "        Set attributes to choose user, system, and/or hyperprivileged cycles.\n\n"));
4727   fprintf (f_usage, GTXT ("        == Instructions.\n"
4728                           "        Count instructions when they are committed with:\n"));
4729   fprintf (f_usage, NTXT ("            Instr_all\n"));
4730   if (cpuver != CPC_SPARC_M8)
4731     fprintf (f_usage, GTXT ("        It is the total of these counters:\n"));
4732   else
4733     fprintf (f_usage, GTXT ("        Some subsets of instructions can be counted separately:\n"));
4734   fprintf (f_usage, NTXT ("            Branches               %s\n"), GTXT ("branches"));
4735   fprintf (f_usage, NTXT ("            Instr_FGU_crypto       %s\n"), GTXT ("Floating Point and Graphics Unit"));
4736   fprintf (f_usage, NTXT ("            Instr_ld               %s\n"), GTXT ("loads"));
4737   fprintf (f_usage, NTXT ("            Instr_st               %s\n"), GTXT ("stores"));
4738   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4739            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_SPR_ring_ops")
4740            : NTXT ("SPR_ring_ops"),
4741            GTXT ("internal use of SPR ring"));
4742   fprintf (f_usage, NTXT ("            Instr_other            %s\n"), GTXT ("basic arithmetic and logical instructions"));
4743   if (cpuver != CPC_SPARC_M8)
4744     fprintf (f_usage, GTXT ("        Some subsets of these instructions can be counted separately:\n"));
4745   fprintf (f_usage, NTXT ("            Br_taken               %s\n"), GTXT ("Branches that are taken"));
4746   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4747            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_block_ld_st")
4748            : NTXT ("Block_ld_st"),
4749            GTXT ("block load/store"));
4750   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4751            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_atomic")
4752            : NTXT ("Atomics"),
4753            GTXT ("atomic instructions"));
4754   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4755            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_SW_prefetch")
4756            : NTXT ("SW_prefetch"),
4757            GTXT ("prefetches"));
4758   fprintf (f_usage, NTXT ("            %-19s    %s\n"),
4759            cpuver == CPC_SPARC_M7 ? NTXT ("Instr_SW_count")
4760            : NTXT ("Sw_count_intr"),
4761            GTXT ("SW Count instructions (counts special no-op assembler instructions)"));
4762   fprintf (f_usage, NTXT ("\n"));
4763
4764 #ifdef TMPLEN
4765   compilation error : we're trying to use a macro that's already defined
4766 #endif
4767 #define TMPLEN 32
4768           char s0[TMPLEN], s1[TMPLEN], s2[TMPLEN], s3[TMPLEN];
4769   if (cpuver == CPC_SPARC_M7)
4770     {
4771       snprintf (s0, TMPLEN, "Commit_0_cyc");
4772       snprintf (s1, TMPLEN, "Commit_1_cyc");
4773       snprintf (s2, TMPLEN, "Commit_2_cyc");
4774       snprintf (s3, TMPLEN, "Commit_1_or_2_cyc");
4775     }
4776   else
4777     {
4778       snprintf (s0, TMPLEN, "Commit_0");
4779       snprintf (s1, TMPLEN, "Commit_1");
4780       snprintf (s2, TMPLEN, "Commit_2");
4781       snprintf (s3, TMPLEN, "Commit_1_or_2");
4782     }
4783 #undef TMPLEN
4784   fprintf (f_usage, GTXT ("        == Commit.\n"
4785                           "        Instructions may be launched speculatively, executed out of order, etc.\n"));
4786   if (cpuver != CPC_SPARC_M8)
4787     {
4788       fprintf (f_usage, GTXT ("        We can count the number of cycles during which 0, 1, or 2 instructions are\n"
4789                               "        actually completed and their results committed:\n"));
4790       fprintf (f_usage, GTXT ("            %s\n"
4791                               "            %s\n"
4792                               "            %s\n"
4793                               "            %s\n"
4794                               "        %s is a useful way of identifying parts of your application with\n"
4795                               "        high-latency instructions.\n\n"),
4796                s0, s1, s2, s3, s0);
4797     }
4798   else
4799     {
4800       fprintf (f_usage, GTXT ("        We can count the number of cycles during which no instructions were\n"
4801                               "        able to commit results using:\n"));
4802       fprintf (f_usage, GTXT ("            %s\n"
4803                               "        %s is a useful way of identifying parts of your application with\n"
4804                               "        high-latency instructions.\n\n"),
4805                s0, s0);
4806     }
4807
4808   fprintf (f_usage, GTXT ("        == Cache/memory hierarchy.\n"));
4809   if (cpuver == CPC_SPARC_M7)
4810     {
4811       fprintf (f_usage, GTXT ("        In the cache hierarchy:\n"
4812                               "         * Each socket has memory and multiple SPARC core clusters (scc).\n"
4813                               "         * Each scc has an L3 cache and multiple L2 and L1 caches.\n"));
4814       fprintf (f_usage, GTXT ("        Loads can be counted by where they hit on socket:\n"));
4815       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4816                NTXT ("DC_hit"), GTXT ("hit own L1 data cache"));
4817       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4818                NTXT ("DC_miss_L2_hit"), GTXT ("hit own L2"));
4819       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4820                NTXT ("DC_miss_L3_hit"), GTXT ("hit own L3"));
4821       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4822                NTXT ("DC_miss_nbr_L2_hit"), GTXT ("hit neighbor L2  (same scc)"));
4823       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4824                NTXT ("DC_miss_nbr_scc_hit"), GTXT ("hit neighbor scc (same socket)"));
4825       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4826                NTXT ("DC_miss_nbr_scc_miss"), GTXT ("miss all caches  (same socket)"));
4827       fprintf (f_usage, GTXT ("        These loads can also be grouped:\n"));
4828       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4829                NTXT ("DC_miss"), GTXT ("all - DC_hit"));
4830       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4831                NTXT ("DC_miss_L2_miss"), GTXT ("all - DC_hit - DC_miss_L2_hit"));
4832       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4833                NTXT ("DC_miss_L3_miss"), GTXT ("DC_miss_nbr_scc_hit + DC_miss_nbr_scc_miss"));
4834       fprintf (f_usage, GTXT ("        Loads that miss all caches on this socket can be counted:\n"));
4835       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4836                NTXT ("DC_miss_remote_scc_hit"), GTXT ("hit cache on different socket"));
4837       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4838                NTXT ("DC_miss_local_mem_hit"), GTXT ("hit local memory (same socket)"));
4839       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4840                NTXT ("DC_miss_remote_mem_hit"), GTXT ("hit remote memory (off socket)"));
4841       fprintf (f_usage, GTXT ("        These events are for speculative loads, launched in anticipation\n"
4842                               "        of helping performance but whose results might not be committed.\n"));
4843 #if 0 // was: #if defined(linux).  See 22236226 - sparc-Linux: Support basic Memoryspace and Dataspace profiling (capture VADDR)
4844       /* 21869427 should not look like memoryspace profiling is supported on Linux */
4845       /* 21869424 desire memoryspace profiling on Linux */
4846       fprintf (f_usage, GTXT ("        To count only data-cache misses that commit, use:\n"));
4847       fprintf (f_usage, NTXT ("            DC_miss_commit\n"));
4848 #else
4849       fprintf (f_usage, GTXT ("        To count only data-cache misses that commit, or for memoryspace profiling,\n"
4850                               "        use the 'memoryspace' counter:\n"));
4851       fprintf (f_usage, NTXT ("            DC_miss_commit\n"));
4852 #endif
4853       fprintf (f_usage, NTXT ("\n"));
4854     }
4855   else if (cpuver == CPC_SPARC_M8)
4856     {
4857       fprintf (f_usage, GTXT ("        In the cache hierarchy:\n"
4858                               "         * Each processor has 4 memory controllers and 2 quad core clusters (QCC).\n"
4859                               "         * Each QCC contains 4 cache processor clusters (CPC).\n"
4860                               "         * Each CPC contains 4 cores.\n"
4861                               "         * Each core supports 8 hardware threads.\n"
4862                               "         * The L3 consists of 2 partitions with 1 QCC per partition.\n"
4863                               ));
4864       fprintf (f_usage, GTXT ("        Loads can be counted by where they hit on socket:\n"));
4865       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4866                NTXT ("DC_miss_L2_hit"), GTXT ("hit own L2"));
4867       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4868                NTXT ("DC_miss_L3_hit"), GTXT ("hit own L3"));
4869       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4870                NTXT ("DC_miss_L3_dirty_copyback"), GTXT ("hit own L3 but require copyback from L2D"));
4871       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4872                NTXT ("DC_miss_nbr_L3_hit"), GTXT ("hit neighbor L3 (same socket)"));
4873       fprintf (f_usage, GTXT ("        Loads that miss all caches on this socket can be counted:\n"));
4874       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4875                NTXT ("DC_miss_remote_L3_hit"), GTXT ("hit cache on different socket"));
4876       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4877                NTXT ("DC_miss_local_mem_hit"), GTXT ("hit local memory (same socket)"));
4878       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4879                NTXT ("DC_miss_remote_mem_hit"), GTXT ("hit remote memory (off socket)"));
4880       fprintf (f_usage, GTXT ("        These events are for speculative loads, launched in anticipation\n"
4881                               "        of helping performance but whose results might not be committed.\n"));
4882 #if 0 // was: #if defined(linux).  See 22236226 - sparc-Linux: Support basic Memoryspace and Dataspace profiling (capture VADDR)
4883       /* 21869427 should not look like memoryspace profiling is supported on Linux */
4884       /* 21869424 desire memoryspace profiling on Linux */
4885       fprintf (f_usage, GTXT ("        To count only data-cache misses that commit, use:\n"));
4886       fprintf (f_usage, NTXT ("            DC_miss_commit\n"));
4887 #else
4888       fprintf (f_usage, GTXT ("        To count only data-cache misses that commit, or for memoryspace profiling,\n"
4889                               "        use the 'memoryspace' counter:\n"));
4890       fprintf (f_usage, NTXT ("            DC_miss_commit\n"));
4891 #endif
4892       fprintf (f_usage, NTXT ("\n"));
4893     }
4894   else
4895     {
4896       fprintf (f_usage, GTXT ("        Total data-cache misses can be counted with:\n"));
4897       fprintf (f_usage, NTXT ("            DC_miss                DC_miss_nospec\n"));
4898       fprintf (f_usage, GTXT ("        They are the totals of misses that hit in L2/L3 cache, local memory, or\n"
4899                               "        remote memory:\n"));
4900       fprintf (f_usage, NTXT ("            DC_miss_L2_L3_hit      DC_miss_L2_L3_hit_nospec\n"));
4901       fprintf (f_usage, NTXT ("            DC_miss_local_hit      DC_miss_local_hit_nospec\n"));
4902       fprintf (f_usage, NTXT ("            DC_miss_remote_L3_hit  DC_miss_remote_L3_hit_nospec\n"));
4903       fprintf (f_usage, GTXT ("        The events in the left column include speculative operations.  Use the\n"
4904                               "        right-hand _nospec events to count only data accesses that commit\n"
4905                               "        or for memoryspace profiling.\n\n"));
4906     }
4907
4908   fprintf (f_usage, GTXT ("        == TLB misses.\n"
4909                           "        The Translation Lookaside Buffer (TLB) is a cache of virtual-to-physical\n"
4910                           "        page translations."));
4911   fprintf (f_usage, GTXT ("  If a virtual address (VA) is not represented in the\n"
4912                           "        TLB, an expensive hardware table walk (HWTW) must be conducted."));
4913   fprintf (f_usage, GTXT ("  If the\n"
4914                           "        page is still not found, a trap results.  There is a data TLB (DTLB) and\n"
4915                           "        an instruction TLB (ITLB).\n\n"));
4916   fprintf (f_usage, GTXT ("        TLB misses can be counted by:\n"));
4917   fprintf (f_usage, NTXT ("            %s\n"),
4918            cpuver == CPC_SPARC_M7 ?
4919            NTXT ("DTLB_HWTW_search            ITLB_HWTW_search") :
4920            cpuver == CPC_SPARC_M8 ?
4921            NTXT ("DTLB_HWTW                   ITLB_HWTW") :
4922            NTXT ("DTLB_miss_asynch            ITLB_miss_asynch"));
4923   fprintf (f_usage, GTXT ("        or broken down by page size:\n"));
4924   fprintf (f_usage, NTXT ("            %s"),
4925            cpuver == CPC_SPARC_M7 ?
4926            NTXT ("DTLB_HWTW_hit_8K            ITLB_HWTW_hit_8K\n"
4927                  "            DTLB_HWTW_hit_64K           ITLB_HWTW_hit_64K\n"
4928                  "            DTLB_HWTW_hit_4M            ITLB_HWTW_hit_4M\n") :
4929            NTXT ("DTLB_fill_8KB               ITLB_fill_8KB\n"
4930                  "            DTLB_fill_64KB              ITLB_fill_64KB\n"
4931                  "            DTLB_fill_4MB               ITLB_fill_4MB\n"));
4932   fprintf (f_usage, NTXT ("            %s\n\n"),
4933            cpuver == CPC_SPARC_M7 ?
4934            NTXT ("DTLB_HWTW_hit_256M          ITLB_HWTW_hit_256M\n"
4935                  "            DTLB_HWTW_hit_2G_16G        ITLB_HWTW_hit_2G_16G\n"
4936                  "            DTLB_HWTW_miss_trap         ITLB_HWTW_miss_trap") :
4937            cpuver == CPC_SPARC_M8 ?
4938            NTXT ("DTLB_HWTW_hit_256M          ITLB_HWTW_hit_256M\n"
4939                  "            DTLB_HWTW_hit_16G           ITLB_HWTW_hit_16G\n"
4940                  "            DTLB_HWTW_hit_1T            ITLB_HWTW_hit_1T") :
4941            NTXT ("DTLB_fill_256MB             ITLB_fill_256MB\n"
4942                  "            DTLB_fill_2GB               ITLB_fill_2GB\n"
4943                  "            DTLB_fill_trap              ITLB_fill_trap"));
4944   if (cpuver == CPC_SPARC_M8)
4945     {
4946       fprintf (f_usage, GTXT ("        TLB traps, which can require hundreds of cycles, can be counted with:\n"));
4947       fprintf (f_usage, NTXT ("            %s\n\n"),
4948                NTXT ("DTLB_fill_trap              ITLB_fill_trap"));
4949     }
4950
4951   fprintf (f_usage, GTXT ("        == Branch misprediction.\n"
4952                           "        Count branch mispredictions with:\n"
4953                           "            Br_mispred\n"
4954                           "        It is the total of:\n"
4955                           "            Br_dir_mispred         direction was mispredicted\n"
4956                           "            %s         target    was mispredicted\n"
4957                           "\n"), cpuver == CPC_SPARC_M7 ? NTXT ("Br_tgt_mispred") : NTXT ("Br_trg_mispred"));
4958
4959   fprintf (f_usage, GTXT ("        == RAW hazards.\n"
4960                           "        A read-after-write (RAW) delay occurs when we attempt to read a datum\n"
4961                           "        before an earlier write has had time to complete:\n"));
4962   if (cpuver == CPC_SPARC_M8)
4963     {
4964       fprintf (f_usage, NTXT ("            RAW_hit\n"));
4965       fprintf (f_usage, GTXT ("        RAW_hit events can be broken down into:\n"));
4966     }
4967   else
4968     {
4969       fprintf (f_usage, NTXT ("            RAW_hit_st_q~emask=0xf\n"));
4970       fprintf (f_usage, GTXT ("        The mask 0xf counts the total of all types such as:\n"));
4971     }
4972   fprintf (f_usage, NTXT ("            RAW_hit_st_buf         write is still in store buffer\n"
4973                           "            RAW_hit_st_q           write is still in store queue\n"
4974                           "\n"));
4975   if (cpuver == CPC_SPARC_M7)
4976     {
4977       fprintf (f_usage, GTXT ("        == Flush.\n"
4978                               "        One can count the number of times the pipeline must be flushed:\n"));
4979       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4980                NTXT ("Flush_L3_miss"), GTXT ("load missed L3 and >1 strand is active on the core"));
4981       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4982                NTXT ("Flush_br_mispred"), GTXT ("branch misprediction"));
4983       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4984                NTXT ("Flush_arch_exception"), GTXT ("SPARC exceptions and trap entry/return"));
4985       fprintf (f_usage, NTXT ("            %-22s %s\n"),
4986                NTXT ("Flush_other"), GTXT ("state change to/from halted/paused"));
4987       fprintf (f_usage, NTXT ("\n"));
4988     }
4989 }
4990
4991 static void
4992 hwc_usage_internal (int forKernel, FILE *f_usage, const char *cmd, const char *dataspace_msg, int show_syntax, int show_short_desc)
4993 {
4994   if (!VALID_FOR_KERNEL (forKernel))
4995     return;
4996   char cpuname[128];
4997   hwc_get_cpuname (cpuname, 128);
4998   Hwcentry** raw_ctrs = hwc_get_raw_ctrs (forKernel);
4999   int has_raw_ctrs = (raw_ctrs && raw_ctrs[0]);
5000   Hwcentry** std_ctrs = hwc_get_std_ctrs (forKernel);
5001   int has_std_ctrs = (std_ctrs && std_ctrs[0]);
5002   unsigned hwc_maxregs = hwc_get_max_concurrent (forKernel);
5003   int cpuver = hwc_get_cpc_cpuver ();
5004   if (hwc_maxregs != 0)
5005     {
5006       if (show_syntax)
5007         {
5008           fprintf (f_usage, GTXT ("\nSpecifying HW counters on `%s' (cpuver=%d):\n\n"), cpuname, cpuver);
5009           fprintf (f_usage, GTXT ("    -h {auto|lo|on|hi}\n"));
5010           fprintf (f_usage, GTXT ("\tturn on default set of HW counters at the specified rate\n"));
5011           if (hwc_maxregs == 1)
5012             {
5013               fprintf (f_usage, GTXT ("    -h <ctr_def>\n"));
5014               fprintf (f_usage, GTXT ("\tspecify HW counter profiling for one HW counter only\n"));
5015             }
5016           else
5017             {
5018               fprintf (f_usage, GTXT ("    -h <ctr_def> [-h <ctr_def>]...\n"));
5019               fprintf (f_usage, GTXT ("    -h <ctr_def>[,<ctr_def>]...\n"));
5020               fprintf (f_usage, GTXT ("\tspecify HW counter profiling for up to %u HW counters\n"), hwc_maxregs);
5021             }
5022           fprintf (f_usage, NTXT ("\n"));
5023         }
5024       else
5025         {
5026           fprintf (f_usage, GTXT ("\nSpecifying HW counters on `%s' (cpuver=%d)\n\n"), cpuname, cpuver);
5027           if (hwc_maxregs == 1)
5028             fprintf (f_usage, GTXT ("           Hardware counter profiling is supported for only one counter.\n"));
5029           else
5030             fprintf (f_usage, GTXT ("           Hardware counter profiling is supported for up to %u HW counters.\n"), hwc_maxregs);
5031         }
5032     }
5033   else
5034     {
5035       if (!IS_KERNEL (forKernel))
5036         { // EUGENE I don't see why we don't also use this for er_kernel
5037           char buf[1024];
5038           *buf = 0;
5039           char *pch = hwcfuncs_errmsg_get (buf, sizeof (buf), 0);
5040           if (*pch)
5041             fprintf (f_usage, GTXT ("HW counter profiling is not supported on this system: %s%s"),
5042                      pch, pch[strlen (pch) - 1] == '\n' ? "" : "\n");
5043           else
5044             fprintf (f_usage, GTXT ("HW counter profiling is not supported on this system\n"));
5045         }
5046       return;
5047     }
5048
5049   /* At this point, we know we have counters */
5050   char**hwc_attrs = hwc_get_attrs (forKernel);
5051   int has_attrs = (hwc_attrs && hwc_attrs[0]);
5052   if (show_syntax)
5053     {
5054       const char *reg_s = show_regs ? "[/<reg#>]" : "";
5055       const char *attr_s = has_attrs ? "[[~<attr>=<val>]...]" : "";
5056       fprintf (f_usage, GTXT ("    <ctr_def> == <ctr>%s%s,[<rate>]\n"), attr_s, reg_s);
5057       if (dataspace_msg)
5058         fprintf (f_usage, NTXT ("%s"), dataspace_msg);
5059       fprintf (f_usage, GTXT ("        <ctr>\n"));
5060       fprintf (f_usage, GTXT ("           counter name, "));
5061     }
5062   else
5063     fprintf (f_usage, GTXT ("           Counter name "));
5064   fprintf (f_usage, GTXT ("must be selected from the available counters\n"
5065                           "           listed below.  On most systems, if a counter is not listed\n"
5066                           "           below, it may still be specified by its numeric value.\n"));
5067   if (cpcx_has_precise[forKernel])
5068     {
5069       if (!forKernel)
5070         fprintf (f_usage, GTXT ("           Counters labeled as 'memoryspace' in the list below will\n"
5071                                 "           collect memoryspace data by default.\n"));
5072     }
5073   fprintf (f_usage, GTXT ("\n"));
5074   if (has_attrs)
5075     {
5076       if (show_syntax)
5077         {
5078           fprintf (f_usage, GTXT ("        ~<attr>=<val>\n"));
5079           fprintf (f_usage, GTXT ("           optional attribute where <val> can be in decimal or hex\n"
5080                                   "           format, and <attr> can be one of: \n"));
5081         }
5082       else
5083         fprintf (f_usage, GTXT ("           Optional attribute where <val> can be in decimal or hex\n"
5084                                 "           format, and <attr> can be one of: \n"));
5085       for (char **pattr = hwc_attrs; *pattr; pattr++)
5086         fprintf (f_usage, NTXT ("             `%s'\n"), *pattr);
5087       if (show_syntax)
5088         fprintf (f_usage, GTXT ("           Multiple attributes may be specified, and each must be preceded by a ~.\n\n"));
5089       else
5090         fprintf (f_usage, GTXT ("           Multiple attributes may be specified.\n\n"));
5091       if (IS_KERNEL (forKernel))
5092         fprintf (f_usage, GTXT ("           Other attributes may be supported by the chip, but are not supported by DTrace and will be ignored by er_kernel.\n\n"));
5093     }
5094
5095   if (show_syntax)
5096     {
5097       if (show_regs)
5098         fprintf (f_usage, GTXT ("        /<reg#>\n"
5099                                 "           forces use of a specific hardware register.  (Solaris only)\n"
5100                                 "           If not specified, %s will attempt to place the counter into the first\n"
5101                                 "           available register and as a result may be unable to place\n"
5102                                 "           subsequent counters due to register conflicts.\n"
5103                                 "           The / in front of the register number is required if a register is specified.\n\n"),
5104                  cmd);
5105
5106       fprintf (f_usage, GTXT ("        <rate> == {auto|lo|on|hi}\n"));
5107       fprintf (f_usage, GTXT ("           `auto'   (default) match the rate used by clock profiling.\n"));
5108       fprintf (f_usage, GTXT ("                    If clock profiling is disabled, use `on'.\n"));
5109       fprintf (f_usage, GTXT ("           `lo'     per-thread maximum rate of ~10 samples/second\n"));
5110       fprintf (f_usage, GTXT ("           `on'     per-thread maximum rate of ~100 samples/second\n"));
5111       fprintf (f_usage, GTXT ("           `hi'     per-thread maximum rate of ~1000 samples/second\n\n"));
5112       fprintf (f_usage, GTXT ("        <rate> == <interval>\n"
5113                               "           Fixed event interval value to trigger a sample.\n"
5114                               "           Smaller intervals imply more frequent samples.\n"
5115                               "           Example: when counting cycles on a 2 GHz processor,\n"
5116                               "           an interval of 2,000,003 implies ~1000 samples/sec\n"
5117                               "\n"
5118                               "           Use this feature with caution, because:\n"
5119                               "             (1) Frequent sampling increases overhead and may disturb \n"
5120                               "                 other applications on your system.\n"
5121                               "             (2) Event counts vary dramatically depending on the event \n"
5122                               "                 and depending on the application.\n"
5123                               "             (3) A fixed event interval disables any other gprofng\n"
5124                               "                 internal mechanisms that may limit event rates.\n"
5125                               "\n"
5126                               "           Guidelines:  Aim at <1000 events per second.  Start by \n"
5127                               "           collecting with the 'hi' option; in the experiment overview,\n"
5128                               "           notice how many events are recorded per second; divide by\n"
5129                               "           1000, and use that as your starting point.\n\n"));
5130
5131       fprintf (f_usage, GTXT ("        A comma ',' followed immediately by white space may be omitted.\n\n"));
5132     }
5133
5134   /* default counters */
5135   fprintf (f_usage, GTXT ("Default set of HW counters:\n\n"));
5136   char * defctrs = hwc_get_default_cntrs2 (forKernel, 1);
5137   if (defctrs == NULL)
5138     fprintf (f_usage, GTXT ("    No default HW counter set defined for this system.\n"));
5139   else if (strlen (defctrs) == 0)
5140     {
5141       char *s = hwc_get_orig_default_cntrs (forKernel);
5142       fprintf (f_usage, GTXT ("    The default HW counter set (%s) defined for %s cannot be loaded on this system.\n"),
5143                s, cpuname);
5144       free (s);
5145       free (defctrs);
5146     }
5147   else
5148     {
5149       char *defctrs2 = hwc_get_default_cntrs2 (forKernel, 2);
5150       fprintf (f_usage, GTXT ("    -h %s\n"), defctrs);
5151       free (defctrs2);
5152       free (defctrs);
5153     }
5154
5155   /* long listings */
5156   char tmp[1024];
5157   if (has_std_ctrs)
5158     {
5159       fprintf (f_usage, GTXT ("\nAliases for most useful HW counters:\n\n"));
5160       format_columns (tmp, 1024, "alias", "raw name", "type ", "units", "regs", "description");
5161       fprintf (f_usage, NTXT ("    %s\n\n"), tmp);
5162       for (Hwcentry **pctr = std_ctrs; *pctr; pctr++)
5163         {
5164           Hwcentry *ctr = *pctr;
5165           hwc_hwcentry_string_internal (tmp, sizeof (tmp), ctr, 0);
5166           fprintf (f_usage, NTXT ("    %s\n"), tmp);
5167         }
5168     }
5169   if (has_raw_ctrs)
5170     {
5171       fprintf (f_usage, GTXT ("\nRaw HW counters:\n\n"));
5172       hwc_usage_raw_overview_sparc (f_usage, cpuver);
5173       format_columns (tmp, 1024, "name", NULL, "type ", "units", "regs", "description");
5174       fprintf (f_usage, NTXT ("    %s\n\n"), tmp);
5175       for (Hwcentry **pctr = raw_ctrs; *pctr; pctr++)
5176         {
5177           Hwcentry *ctr = *pctr;
5178           hwc_hwcentry_string_internal (tmp, sizeof (tmp), ctr, show_short_desc);
5179           fprintf (f_usage, NTXT ("    %s\n"), tmp);
5180         }
5181     }
5182
5183   /* documentation notice */
5184   hwc_get_docref (tmp, 1024);
5185   if (strlen (tmp))
5186     fprintf (f_usage, NTXT ("\n%s\n"), tmp);
5187 }
5188
5189 /* Print a description of "-h" usage, largely common to collect and er_kernel. */
5190 void
5191 hwc_usage (int forKernel, const char *cmd, const char *dataspace_msg)
5192 {
5193   hwc_usage_internal (forKernel, stdout, cmd, dataspace_msg, 1, 0);
5194 }
5195
5196 void
5197 hwc_usage_f (int forKernel, FILE *f, const char *cmd, const char *dataspace_msg, int show_syntax, int show_short_desc)
5198 {
5199   hwc_usage_internal (forKernel, f, cmd, dataspace_msg, show_syntax, show_short_desc);
5200 }
5201
5202 /*---------------------------------------------------------------------------*/
5203 /* init functions */
5204
5205 static char* supported_pebs_counters[] = {
5206   "mem_inst_retired.latency_above_threshold",
5207   "mem_trans_retired.load_latency",
5208   "mem_trans_retired.precise_store",
5209   NULL
5210 };
5211
5212 /* callback, (see setup_cpc()) called for each valid regno/name combo */
5213
5214 /* builds rawlist,, creates and updates reg_list[] arrays in stdlist table */
5215 static void
5216 hwc_cb (uint_t cpc_regno, const char *name)
5217 {
5218   regno_t regno = cpc_regno; /* convert type */
5219   list_add (&unfiltered_raw, regno, name);
5220 }
5221
5222 /* input:
5223  *   forKernel: 1 - generate lists for er_kernel, 0 - generate lists for collect
5224  *
5225  *   raw_orig: HWCs as generated by hwc_cb()
5226  * output:
5227  *   pstd_out[], praw_out[]: malloc'd array of pointers to malloc'd hwcentry, or NULL
5228  */
5229 static void
5230 hwc_process_raw_ctrs (int forKernel, Hwcentry ***pstd_out,
5231                       Hwcentry ***praw_out, Hwcentry ***phidden_out,
5232                       Hwcentry**static_tables, Hwcentry **raw_unfiltered_in)
5233 {
5234   // set up output buffers
5235   ptr_list s_outbufs[3];
5236   ptr_list *std_out = &s_outbufs[0];
5237   ptr_list_init (std_out);
5238   ptr_list *raw_out = &s_outbufs[1];
5239   ptr_list_init (raw_out);
5240   ptr_list *hidden_out = &s_outbufs[2];
5241   ptr_list_init (hidden_out);
5242
5243 #define NUM_TABLES 3
5244   ptr_list table_copy[NUM_TABLES]; // copy of data from static tables. [0]std, [1]generic, and [2]hidden
5245   for (int tt = 0; tt < NUM_TABLES; tt++)
5246     ptr_list_init (&table_copy[tt]);
5247
5248   // copy records from std [0] and generic [1] static input tables into table_copy[0],[1],or[2]
5249   for (int tt = 0; tt < 2; tt++)
5250     for (Hwcentry *pctr = static_tables[tt]; pctr && pctr->name; pctr++)
5251       if (is_hidden_alias (pctr))
5252         list_append_shallow_copy (&table_copy[2], pctr); // hidden list
5253       else
5254         list_append_shallow_copy (&table_copy[tt], pctr);
5255
5256   // copy raw_unfiltered_in to raw_out
5257   for (int ii = 0; raw_unfiltered_in && raw_unfiltered_in[ii]; ii++)
5258     {
5259       Hwcentry *pctr = raw_unfiltered_in[ii];
5260       // filter out raw counters that don't work correctly
5261
5262 #ifdef WORKAROUND_6231196_NIAGARA1_NO_CTR_0
5263       if (cpcx_cpuver == CPC_ULTRA_T1)
5264         if (!regno_is_valid (pctr, 1))
5265           continue;   /* Niagara can not profile on register zero; skip this */
5266 #endif
5267       // remove specific PEBs counters when back end doesn't support sampling
5268       const char *name = pctr->name;
5269       if ((cpcx_support_bitmask & HWCFUNCS_SUPPORT_PEBS_SAMPLING) == 0 || forKernel)
5270         {
5271           int skip = 0;
5272           for (int ii = 0; supported_pebs_counters[ii]; ii++)
5273             if (strcmp (supported_pebs_counters[ii], name) == 0)
5274               {
5275                 skip = 1;
5276                 break;
5277               }
5278           if (skip)
5279             continue;
5280         }
5281
5282       Hwcentry *pnew = list_append_shallow_copy (raw_out, pctr);
5283 #ifdef WORKAROUND_6231196_NIAGARA1_NO_CTR_0
5284       if (cpcx_cpuver == CPC_ULTRA_T1)
5285         {
5286           free (pnew->reg_list);
5287           pnew->reg_list = NULL;
5288           regno_add (pnew, 1); // only allow register 1
5289         }
5290 #endif
5291     } // raw_unfiltered_in
5292
5293   // Scan raw counters to populate Hwcentry fields from matching static_tables entries
5294   // Also populate reg_list for aliases found in table_copy[]
5295   for (int uu = 0; uu < raw_out->sz; uu++)
5296     {
5297       Hwcentry *praw = (Hwcentry*) raw_out->array[uu];
5298       Hwcentry *pstd = NULL; // set if non-alias entry from std table matches
5299       char *name = praw->name;
5300       /* in the standard counter and generic lists,
5301          update reg_list for all matching items  */
5302       for (int tt = 0; tt < NUM_TABLES; tt++)
5303         { // std, generic, and hidden
5304           if (table_copy[tt].sz == 0)
5305             continue;
5306           Hwcentry **array = (Hwcentry**) table_copy[tt].array;
5307           for (int jj = 0; array[jj]; jj++)
5308             { // all table counters
5309               Hwcentry *pctr = array[jj];
5310               char *pname;
5311               if (pctr->int_name)
5312                 pname = pctr->int_name;
5313               else
5314                 pname = pctr->name;
5315               if (!is_same (name, pname, '~'))
5316                 continue;
5317
5318               /* truncated pname matches <name>... */
5319               // check to see if table entry applies only to specific register
5320               int specific_reg_num_only = 0;
5321               if (pctr->reg_num != REGNO_ANY)
5322                 {
5323                   // table entry applies only to specific register
5324                   if (!regno_is_valid (praw, pctr->reg_num))
5325                     continue;
5326                   specific_reg_num_only = 1;
5327                 }
5328
5329               // Match!
5330               // Update cpu_table_copy's supported registers
5331               if (specific_reg_num_only)
5332                 regno_add (pctr, pctr->reg_num);
5333               else
5334                 pctr->reg_list = praw->reg_list;
5335
5336               if (!is_visible_alias (pctr) && !is_hidden_alias (pctr))
5337                 {
5338                   // Note: we could expand criteria to also allow aliases to set default rates for raw HWCs
5339                   /* This is an 'internal' raw counter */
5340                   if (!pstd)
5341                     pstd = pctr; /* use info as a template when adding to raw list */
5342                   else
5343                     hwcentry_print (DBG_LT0, "hwctable: hwc_cb: Warning: "
5344                                     "counter %s appears in table more than once: ",
5345                                     pstd);
5346                 }
5347             }/* for table rows */
5348         }/* for std and generic tables */
5349
5350       if (pstd)
5351         {
5352           /* the main table had an entry that matched <name> exactly */
5353           /* Apply the main table entry as a template */
5354           *praw = *pstd;
5355         }
5356     }/* for (raw_out) */
5357
5358   // update std_out and hidden_out
5359   for (int tt = 0; tt < NUM_TABLES; tt++)
5360     {
5361       if (tt == 1 /*skip std_raw*/ || table_copy[tt].sz == 0)
5362         continue;
5363       Hwcentry *pctr;
5364       for (int ii = 0; (pctr = table_copy[tt].array[ii]); ii++)
5365         {
5366           // prune unsupported rows from std table
5367           if (!is_visible_alias (pctr) && !is_hidden_alias (pctr))
5368             continue; // only aliases
5369           if (REG_LIST_IS_EMPTY (pctr->reg_list))
5370             {
5371               if (is_numeric_alias (pctr))
5372                 {
5373 #if 1 //22844570 DTrace cpc provider does not accept numeric counter names
5374                   if (forKernel)
5375                     continue;
5376 #endif
5377                   regno_add (pctr, REGNO_ANY); // hwcs specified by number allowed on any register
5378                 }
5379               else
5380                 continue;
5381             }
5382
5383           ptr_list *dest = (tt == 0) ? std_out : hidden_out;
5384           Hwcentry *isInList;
5385           if (pctr->short_desc == NULL)
5386             {
5387               isInList = ptrarray_find_by_name ((Hwcentry**) raw_out->array, pctr->int_name);
5388               if (isInList)
5389                 pctr->short_desc = isInList->short_desc; // copy the raw counter's detailed description
5390             }
5391           isInList = ptrarray_find_by_name ((Hwcentry**) dest->array, pctr->name);
5392           if (isInList)
5393             hwcentry_print (DBG_LT0, "hwctable: hwc_cb: Warning: "
5394                             "counter %s appears in alias list more than once: ",
5395                             pctr);
5396           else
5397             list_append_shallow_copy (dest, pctr);
5398         }
5399     }
5400   for (int tt = 0; tt < NUM_TABLES; tt++)
5401     ptr_list_free (&table_copy[tt]);
5402
5403   if (forKernel)
5404     {
5405       // for er_kernel, use baseline value of PRELOAD_DEF_ERKERNEL instead of PRELOAD_DEF
5406       for (int tt = 0; tt < 3; tt++)
5407         { // std_out-0, raw_out-1, hidden_out-2
5408           Hwcentry** hwcs = (Hwcentry**) (s_outbufs[tt].array);
5409           for (int ii = 0; hwcs && hwcs[ii]; ii++)
5410             {
5411               Hwcentry *hwc = hwcs[ii];
5412               if (hwc->val == PRELOAD_DEF)
5413                 hwc->val = PRELOAD_DEF_ERKERNEL;
5414             }
5415         }
5416     }
5417   *pstd_out = (Hwcentry**) std_out->array;
5418   *praw_out = (Hwcentry**) raw_out->array;
5419   *phidden_out = (Hwcentry**) hidden_out->array;
5420 }
5421
5422 /* callback, (see setup_cpc()) called for each valid attribute */
5423 /* builds attrlist */
5424 static void
5425 attrs_cb (const char *attr)
5426 {
5427   Tprintf (DBG_LT3, "hwctable: attrs_cb(): %s\n", attr);
5428   if (strcmp (attr, "picnum") == 0)
5429     return;     /* don't make this attribute available to users */
5430   ptr_list_add (&unfiltered_attrs, (void*) strdup (attr));
5431 }
5432
5433 /* returns true if attribute is valid for this platform */
5434 static int
5435 attr_is_valid (int forKernel, const char *attr)
5436 {
5437   setup_cpcx ();
5438   if (!VALID_FOR_KERNEL (forKernel) || !cpcx_attrs[forKernel])
5439     return 0;
5440   for (int ii = 0; cpcx_attrs[forKernel][ii]; ii++)
5441     if (strcmp (attr, cpcx_attrs[forKernel][ii]) == 0)
5442       return 1;
5443   return 0;
5444 }