gdb/lm32-tdep.c

   1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
   2    Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009-2024 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "frame.h"
  22 #include "frame-unwind.h"
  23 #include "frame-base.h"
  24 #include "inferior.h"
  25 #include "dis-asm.h"
  26 #include "symfile.h"
  27 #include "remote.h"
  28 #include "gdbcore.h"
  29 #include "sim/sim-lm32.h"
  30 #include "arch-utils.h"
  31 #include "regcache.h"
  32 #include "trad-frame.h"
  33 #include "reggroups.h"
  34 #include <algorithm>
  35 #include "gdbarch.h"
  36
  37 /* Make cgen names unique to prevent ODR conflicts with other targets.  */
  38 #define GDB_CGEN_REMAP_PREFIX lm32
  39 #include "cgen-remap.h"
  40 #include "opcodes/lm32-desc.h"
  41
  42 /* Macros to extract fields from an instruction.  */
  43 #define LM32_OPCODE(insn)       ((insn >> 26) & 0x3f)
  44 #define LM32_REG0(insn)         ((insn >> 21) & 0x1f)
  45 #define LM32_REG1(insn)         ((insn >> 16) & 0x1f)
  46 #define LM32_REG2(insn)         ((insn >> 11) & 0x1f)
  47 #define LM32_IMM16(insn)        ((((long)insn & 0xffff) << 16) >> 16)
  48
  49 struct lm32_gdbarch_tdep : gdbarch_tdep_base
  50 {
  51   /* gdbarch target dependent data here.  Currently unused for LM32.  */
  52 };
  53
  54 struct lm32_frame_cache
  55 {
  56   /* The frame's base.  Used when constructing a frame ID.  */
  57   CORE_ADDR base;
  58   CORE_ADDR pc;
  59   /* Size of frame.  */
  60   int size;
  61   /* Table indicating the location of each and every register.  */
  62   trad_frame_saved_reg *saved_regs;
  63 };
  64
  65 /* Return whether a given register is in a given group.  */
  66
  67 static int
  68 lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  69                           const struct reggroup *group)
  70 {
  71   if (group == general_reggroup)
  72     return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
  73       || (regnum == SIM_LM32_PC_REGNUM);
  74   else if (group == system_reggroup)
  75     return ((regnum >= SIM_LM32_BA_REGNUM) && (regnum <= SIM_LM32_EA_REGNUM))
  76       || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
  77   return default_register_reggroup_p (gdbarch, regnum, group);
  78 }
  79
  80 /* Return a name that corresponds to the given register number.  */
  81
  82 static const char *
  83 lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
  84 {
  85   static const char *register_names[] = {
  86     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  87     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  88     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  89     "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
  90     "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
  91   };
  92
  93   static_assert (ARRAY_SIZE (register_names) == SIM_LM32_NUM_REGS);
  94   return register_names[reg_nr];
  95 }
  96
  97 /* Return type of register.  */
  98
  99 static struct type *
 100 lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
 101 {
 102   return builtin_type (gdbarch)->builtin_int32;
 103 }
 104
 105 /* Return non-zero if a register can't be written.  */
 106
 107 static int
 108 lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
 109 {
 110   return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
 111 }
 112
 113 /* Analyze a function's prologue.  */
 114
 115 static CORE_ADDR
 116 lm32_analyze_prologue (struct gdbarch *gdbarch,
 117                        CORE_ADDR pc, CORE_ADDR limit,
 118                        struct lm32_frame_cache *info)
 119 {
 120   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 121   unsigned long instruction;
 122
 123   /* Keep reading though instructions, until we come across an instruction
 124      that isn't likely to be part of the prologue.  */
 125   info->size = 0;
 126   for (; pc < limit; pc += 4)
 127     {
 128
 129       /* Read an instruction.  */
 130       instruction = read_memory_integer (pc, 4, byte_order);
 131
 132       if ((LM32_OPCODE (instruction) == OP_SW)
 133           && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
 134         {
 135           /* Any stack displaced store is likely part of the prologue.
 136              Record that the register is being saved, and the offset
 137              into the stack.  */
 138           info->saved_regs[LM32_REG1 (instruction)].set_addr (LM32_IMM16 (instruction));
 139         }
 140       else if ((LM32_OPCODE (instruction) == OP_ADDI)
 141                && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 142         {
 143           /* An add to the SP is likely to be part of the prologue.
 144              Adjust stack size by whatever the instruction adds to the sp.  */
 145           info->size -= LM32_IMM16 (instruction);
 146         }
 147       else if (                 /* add fp,fp,sp */
 148                 ((LM32_OPCODE (instruction) == OP_ADD)
 149                  && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
 150                  && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
 151                  && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 152                 /* mv fp,imm */
 153                 || ((LM32_OPCODE (instruction) == OP_ADDI)
 154                     && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
 155                     && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
 156         {
 157           /* Likely to be in the prologue for functions that require
 158              a frame pointer.  */
 159         }
 160       else
 161         {
 162           /* Any other instruction is likely not to be part of the
 163              prologue.  */
 164           break;
 165         }
 166     }
 167
 168   return pc;
 169 }
 170
 171 /* Return PC of first non prologue instruction, for the function at the
 172    specified address.  */
 173
 174 static CORE_ADDR
 175 lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 176 {
 177   CORE_ADDR func_addr, limit_pc;
 178   struct lm32_frame_cache frame_info;
 179   trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
 180
 181   /* See if we can determine the end of the prologue via the symbol table.
 182      If so, then return either PC, or the PC after the prologue, whichever
 183      is greater.  */
 184   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 185     {
 186       CORE_ADDR post_prologue_pc
 187         = skip_prologue_using_sal (gdbarch, func_addr);
 188       if (post_prologue_pc != 0)
 189         return std::max (pc, post_prologue_pc);
 190     }
 191
 192   /* Can't determine prologue from the symbol table, need to examine
 193      instructions.  */
 194
 195   /* Find an upper limit on the function prologue using the debug
 196      information.  If the debug information could not be used to provide
 197      that bound, then use an arbitrary large number as the upper bound.  */
 198   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 199   if (limit_pc == 0)
 200     limit_pc = pc + 100;        /* Magic.  */
 201
 202   frame_info.saved_regs = saved_regs;
 203   return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
 204 }
 205
 206 /* Create a breakpoint instruction.  */
 207 constexpr gdb_byte lm32_break_insn[4] = { OP_RAISE << 2, 0, 0, 2 };
 208
 209 typedef BP_MANIPULATION (lm32_break_insn) lm32_breakpoint;
 210
 211
 212 /* Setup registers and stack for faking a call to a function in the
 213    inferior.  */
 214
 215 static CORE_ADDR
 216 lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 217                       struct regcache *regcache, CORE_ADDR bp_addr,
 218                       int nargs, struct value **args, CORE_ADDR sp,
 219                       function_call_return_method return_method,
 220                       CORE_ADDR struct_addr)
 221 {
 222   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 223   int first_arg_reg = SIM_LM32_R1_REGNUM;
 224   int num_arg_regs = 8;
 225   int i;
 226
 227   /* Set the return address.  */
 228   regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
 229
 230   /* If we're returning a large struct, a pointer to the address to
 231      store it at is passed as a first hidden parameter.  */
 232   if (return_method == return_method_struct)
 233     {
 234       regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
 235       first_arg_reg++;
 236       num_arg_regs--;
 237       sp -= 4;
 238     }
 239
 240   /* Setup parameters.  */
 241   for (i = 0; i < nargs; i++)
 242     {
 243       struct value *arg = args[i];
 244       struct type *arg_type = check_typedef (arg->type ());
 245       gdb_byte *contents;
 246       ULONGEST val;
 247
 248       /* Promote small integer types to int.  */
 249       switch (arg_type->code ())
 250         {
 251         case TYPE_CODE_INT:
 252         case TYPE_CODE_BOOL:
 253         case TYPE_CODE_CHAR:
 254         case TYPE_CODE_RANGE:
 255         case TYPE_CODE_ENUM:
 256           if (arg_type->length () < 4)
 257             {
 258               arg_type = builtin_type (gdbarch)->builtin_int32;
 259               arg = value_cast (arg_type, arg);
 260             }
 261           break;
 262         }
 263
 264       /* FIXME: Handle structures.  */
 265
 266       contents = (gdb_byte *) arg->contents ().data ();
 267       val = extract_unsigned_integer (contents, arg_type->length (),
 268                                       byte_order);
 269
 270       /* First num_arg_regs parameters are passed by registers,
 271          and the rest are passed on the stack.  */
 272       if (i < num_arg_regs)
 273         regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
 274       else
 275         {
 276           write_memory_unsigned_integer (sp, arg_type->length (), byte_order,
 277                                          val);
 278           sp -= 4;
 279         }
 280     }
 281
 282   /* Update stack pointer.  */
 283   regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
 284
 285   /* Return adjusted stack pointer.  */
 286   return sp;
 287 }
 288
 289 /* Extract return value after calling a function in the inferior.  */
 290
 291 static void
 292 lm32_extract_return_value (struct type *type, struct regcache *regcache,
 293                            gdb_byte *valbuf)
 294 {
 295   struct gdbarch *gdbarch = regcache->arch ();
 296   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 297   ULONGEST l;
 298   CORE_ADDR return_buffer;
 299
 300   if (type->code () != TYPE_CODE_STRUCT
 301       && type->code () != TYPE_CODE_UNION
 302       && type->code () != TYPE_CODE_ARRAY && type->length () <= 4)
 303     {
 304       /* Return value is returned in a single register.  */
 305       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 306       store_unsigned_integer (valbuf, type->length (), byte_order, l);
 307     }
 308   else if ((type->code () == TYPE_CODE_INT) && (type->length () == 8))
 309     {
 310       /* 64-bit values are returned in a register pair.  */
 311       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 312       memcpy (valbuf, &l, 4);
 313       regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
 314       memcpy (valbuf + 4, &l, 4);
 315     }
 316   else
 317     {
 318       /* Aggregate types greater than a single register are returned
 319          in memory.  FIXME: Unless they are only 2 regs?.  */
 320       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 321       return_buffer = l;
 322       read_memory (return_buffer, valbuf, type->length ());
 323     }
 324 }
 325
 326 /* Write into appropriate registers a function return value of type
 327    TYPE, given in virtual format.  */
 328 static void
 329 lm32_store_return_value (struct type *type, struct regcache *regcache,
 330                          const gdb_byte *valbuf)
 331 {
 332   struct gdbarch *gdbarch = regcache->arch ();
 333   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 334   ULONGEST val;
 335   int len = type->length ();
 336
 337   if (len <= 4)
 338     {
 339       val = extract_unsigned_integer (valbuf, len, byte_order);
 340       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 341     }
 342   else if (len <= 8)
 343     {
 344       val = extract_unsigned_integer (valbuf, 4, byte_order);
 345       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 346       val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
 347       regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
 348     }
 349   else
 350     error (_("lm32_store_return_value: type length too large."));
 351 }
 352
 353 /* Determine whether a functions return value is in a register or memory.  */
 354 static enum return_value_convention
 355 lm32_return_value (struct gdbarch *gdbarch, struct value *function,
 356                    struct type *valtype, struct regcache *regcache,
 357                    gdb_byte *readbuf, const gdb_byte *writebuf)
 358 {
 359   enum type_code code = valtype->code ();
 360
 361   if (code == TYPE_CODE_STRUCT
 362       || code == TYPE_CODE_UNION
 363       || code == TYPE_CODE_ARRAY || valtype->length () > 8)
 364     return RETURN_VALUE_STRUCT_CONVENTION;
 365
 366   if (readbuf)
 367     lm32_extract_return_value (valtype, regcache, readbuf);
 368   if (writebuf)
 369     lm32_store_return_value (valtype, regcache, writebuf);
 370
 371   return RETURN_VALUE_REGISTER_CONVENTION;
 372 }
 373
 374 /* Put here the code to store, into fi->saved_regs, the addresses of
 375    the saved registers of frame described by FRAME_INFO.  This
 376    includes special registers such as pc and fp saved in special ways
 377    in the stack frame.  sp is even more special: the address we return
 378    for it IS the sp for the next frame.  */
 379
 380 static struct lm32_frame_cache *
 381 lm32_frame_cache (const frame_info_ptr &this_frame, void **this_prologue_cache)
 382 {
 383   CORE_ADDR current_pc;
 384   ULONGEST prev_sp;
 385   ULONGEST this_base;
 386   struct lm32_frame_cache *info;
 387   int i;
 388
 389   if ((*this_prologue_cache))
 390     return (struct lm32_frame_cache *) (*this_prologue_cache);
 391
 392   info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
 393   (*this_prologue_cache) = info;
 394   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
 395
 396   info->pc = get_frame_func (this_frame);
 397   current_pc = get_frame_pc (this_frame);
 398   lm32_analyze_prologue (get_frame_arch (this_frame),
 399                          info->pc, current_pc, info);
 400
 401   /* Compute the frame's base, and the previous frame's SP.  */
 402   this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 403   prev_sp = this_base + info->size;
 404   info->base = this_base;
 405
 406   /* Convert callee save offsets into addresses.  */
 407   for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
 408     {
 409       if (info->saved_regs[i].is_addr ())
 410         info->saved_regs[i].set_addr (this_base + info->saved_regs[i].addr ());
 411     }
 412
 413   /* The call instruction moves the caller's PC in the callee's RA register.
 414      Since this is an unwind, do the reverse.  Copy the location of RA register
 415      into PC (the address / regnum) so that a request for PC will be
 416      converted into a request for the RA register.  */
 417   info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
 418
 419   /* The previous frame's SP needed to be computed.  Save the computed
 420      value.  */
 421   info->saved_regs[SIM_LM32_SP_REGNUM].set_value (prev_sp);
 422
 423   return info;
 424 }
 425
 426 static void
 427 lm32_frame_this_id (const frame_info_ptr &this_frame, void **this_cache,
 428                     struct frame_id *this_id)
 429 {
 430   struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
 431
 432   /* This marks the outermost frame.  */
 433   if (cache->base == 0)
 434     return;
 435
 436   (*this_id) = frame_id_build (cache->base, cache->pc);
 437 }
 438
 439 static struct value *
 440 lm32_frame_prev_register (const frame_info_ptr &this_frame,
 441                           void **this_prologue_cache, int regnum)
 442 {
 443   struct lm32_frame_cache *info;
 444
 445   info = lm32_frame_cache (this_frame, this_prologue_cache);
 446   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
 447 }
 448
 449 static const struct frame_unwind lm32_frame_unwind = {
 450   "lm32 prologue",
 451   NORMAL_FRAME,
 452   default_frame_unwind_stop_reason,
 453   lm32_frame_this_id,
 454   lm32_frame_prev_register,
 455   NULL,
 456   default_frame_sniffer
 457 };
 458
 459 static CORE_ADDR
 460 lm32_frame_base_address (const frame_info_ptr &this_frame, void **this_cache)
 461 {
 462   struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
 463
 464   return info->base;
 465 }
 466
 467 static const struct frame_base lm32_frame_base = {
 468   &lm32_frame_unwind,
 469   lm32_frame_base_address,
 470   lm32_frame_base_address,
 471   lm32_frame_base_address
 472 };
 473
 474 static CORE_ADDR
 475 lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 476 {
 477   /* Align to the size of an instruction (so that they can safely be
 478      pushed onto the stack.  */
 479   return sp & ~3;
 480 }
 481
 482 static struct gdbarch *
 483 lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 484 {
 485   /* If there is already a candidate, use it.  */
 486   arches = gdbarch_list_lookup_by_info (arches, &info);
 487   if (arches != NULL)
 488     return arches->gdbarch;
 489
 490   /* None found, create a new architecture from the information provided.  */
 491   gdbarch *gdbarch
 492     = gdbarch_alloc (&info, gdbarch_tdep_up (new lm32_gdbarch_tdep));
 493
 494   /* Type sizes.  */
 495   set_gdbarch_short_bit (gdbarch, 16);
 496   set_gdbarch_int_bit (gdbarch, 32);
 497   set_gdbarch_long_bit (gdbarch, 32);
 498   set_gdbarch_long_long_bit (gdbarch, 64);
 499   set_gdbarch_float_bit (gdbarch, 32);
 500   set_gdbarch_double_bit (gdbarch, 64);
 501   set_gdbarch_long_double_bit (gdbarch, 64);
 502   set_gdbarch_ptr_bit (gdbarch, 32);
 503
 504   /* Register info.  */
 505   set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
 506   set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
 507   set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
 508   set_gdbarch_register_name (gdbarch, lm32_register_name);
 509   set_gdbarch_register_type (gdbarch, lm32_register_type);
 510   set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
 511
 512   /* Frame info.  */
 513   set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
 514   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 515   set_gdbarch_decr_pc_after_break (gdbarch, 0);
 516   set_gdbarch_frame_args_skip (gdbarch, 0);
 517
 518   /* Frame unwinding.  */
 519   set_gdbarch_frame_align (gdbarch, lm32_frame_align);
 520   frame_base_set_default (gdbarch, &lm32_frame_base);
 521   frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
 522
 523   /* Breakpoints.  */
 524   set_gdbarch_breakpoint_kind_from_pc (gdbarch, lm32_breakpoint::kind_from_pc);
 525   set_gdbarch_sw_breakpoint_from_kind (gdbarch, lm32_breakpoint::bp_from_kind);
 526   set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
 527
 528   /* Calling functions in the inferior.  */
 529   set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
 530   set_gdbarch_return_value (gdbarch, lm32_return_value);
 531
 532   set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
 533
 534   return gdbarch;
 535 }
 536
 537 void _initialize_lm32_tdep ();
 538 void
 539 _initialize_lm32_tdep ()
 540 {
 541   gdbarch_register (bfd_arch_lm32, lm32_gdbarch_init);
 542 }