1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
3 Copyright (C) 2002-2024 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
22 #include "arch-utils.h"
25 #include "frame-unwind.h"
26 #include "frame-base.h"
27 #include "trad-frame.h"
29 #include "sim-regno.h"
30 #include "sim/sim-frv.h"
41 /* Make cgen names unique to prevent ODR conflicts with other targets. */
42 #define GDB_CGEN_REMAP_PREFIX frv
43 #include "cgen-remap.h"
44 #include "opcodes/frv-desc.h"
46 struct frv_unwind_cache
/* was struct frame_extra_info */
48 /* The previous frame's inner-most stack address. Used as this
49 frame ID's stack_addr. */
52 /* The frame's base, optionally used by the high-level debug info. */
55 /* Table indicating the location of each and every register. */
56 trad_frame_saved_reg
*saved_regs
;
59 /* A structure describing a particular variant of the FRV.
60 We allocate and initialize one of these structures when we create
61 the gdbarch object for a variant.
63 At the moment, all the FR variants we support differ only in which
64 registers are present; the portable code of GDB knows that
65 registers whose names are the empty string don't exist, so the
66 `register_names' array captures all the per-variant information we
69 in the future, if we need to have per-variant maps for raw size,
70 virtual type, etc., we should replace register_names with an array
71 of structures, each of which gives all the necessary info for one
72 register. Don't stick parallel arrays in here --- that's so
74 struct frv_gdbarch_tdep
: gdbarch_tdep_base
76 /* Which ABI is in use? */
77 enum frv_abi frv_abi
{};
79 /* How many general-purpose registers does this variant have? */
82 /* How many floating-point registers does this variant have? */
85 /* How many hardware watchpoints can it support? */
86 int num_hw_watchpoints
= 0;
88 /* How many hardware breakpoints can it support? */
89 int num_hw_breakpoints
= 0;
92 const char **register_names
= nullptr;
95 using frv_gdbarch_tdep_up
= std::unique_ptr
<frv_gdbarch_tdep
>;
97 /* Return the FR-V ABI associated with GDBARCH. */
99 frv_abi (struct gdbarch
*gdbarch
)
101 frv_gdbarch_tdep
*tdep
= gdbarch_tdep
<frv_gdbarch_tdep
> (gdbarch
);
102 return tdep
->frv_abi
;
105 /* Fetch the interpreter and executable loadmap addresses (for shared
106 library support) for the FDPIC ABI. Return 0 if successful, -1 if
107 not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */
109 frv_fdpic_loadmap_addresses (struct gdbarch
*gdbarch
, CORE_ADDR
*interp_addr
,
110 CORE_ADDR
*exec_addr
)
112 if (frv_abi (gdbarch
) != FRV_ABI_FDPIC
)
116 regcache
*regcache
= get_thread_regcache (inferior_thread ());
118 if (interp_addr
!= NULL
)
121 regcache_cooked_read_unsigned (regcache
,
122 fdpic_loadmap_interp_regnum
, &val
);
125 if (exec_addr
!= NULL
)
128 regcache_cooked_read_unsigned (regcache
,
129 fdpic_loadmap_exec_regnum
, &val
);
136 /* Allocate a new variant structure, and set up default values for all
138 static frv_gdbarch_tdep_up
143 frv_gdbarch_tdep_up
var (new frv_gdbarch_tdep
);
145 var
->frv_abi
= FRV_ABI_EABI
;
148 var
->num_hw_watchpoints
= 0;
149 var
->num_hw_breakpoints
= 0;
151 /* By default, don't supply any general-purpose or floating-point
154 = (const char **) xmalloc ((frv_num_regs
+ frv_num_pseudo_regs
)
155 * sizeof (const char *));
156 for (r
= 0; r
< frv_num_regs
+ frv_num_pseudo_regs
; r
++)
157 var
->register_names
[r
] = "";
159 /* Do, however, supply default names for the known special-purpose
162 var
->register_names
[pc_regnum
] = "pc";
163 var
->register_names
[lr_regnum
] = "lr";
164 var
->register_names
[lcr_regnum
] = "lcr";
166 var
->register_names
[psr_regnum
] = "psr";
167 var
->register_names
[ccr_regnum
] = "ccr";
168 var
->register_names
[cccr_regnum
] = "cccr";
169 var
->register_names
[tbr_regnum
] = "tbr";
171 /* Debug registers. */
172 var
->register_names
[brr_regnum
] = "brr";
173 var
->register_names
[dbar0_regnum
] = "dbar0";
174 var
->register_names
[dbar1_regnum
] = "dbar1";
175 var
->register_names
[dbar2_regnum
] = "dbar2";
176 var
->register_names
[dbar3_regnum
] = "dbar3";
178 /* iacc0 (Only found on MB93405.) */
179 var
->register_names
[iacc0h_regnum
] = "iacc0h";
180 var
->register_names
[iacc0l_regnum
] = "iacc0l";
181 var
->register_names
[iacc0_regnum
] = "iacc0";
183 /* fsr0 (Found on FR555 and FR501.) */
184 var
->register_names
[fsr0_regnum
] = "fsr0";
186 /* acc0 - acc7. The architecture provides for the possibility of many
187 more (up to 64 total), but we don't want to make that big of a hole
188 in the G packet. If we need more in the future, we'll add them
190 for (r
= acc0_regnum
; r
<= acc7_regnum
; r
++)
191 var
->register_names
[r
]
192 = xstrprintf ("acc%d", r
- acc0_regnum
).release ();
194 /* accg0 - accg7: These are one byte registers. The remote protocol
195 provides the raw values packed four into a slot. accg0123 and
196 accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
197 We don't provide names for accg0123 and accg4567 since the user will
198 likely not want to see these raw values. */
200 for (r
= accg0_regnum
; r
<= accg7_regnum
; r
++)
201 var
->register_names
[r
]
202 = xstrprintf ("accg%d", r
- accg0_regnum
).release ();
206 var
->register_names
[msr0_regnum
] = "msr0";
207 var
->register_names
[msr1_regnum
] = "msr1";
209 /* gner and fner registers. */
210 var
->register_names
[gner0_regnum
] = "gner0";
211 var
->register_names
[gner1_regnum
] = "gner1";
212 var
->register_names
[fner0_regnum
] = "fner0";
213 var
->register_names
[fner1_regnum
] = "fner1";
219 /* Indicate that the variant VAR has NUM_GPRS general-purpose
220 registers, and fill in the names array appropriately. */
222 set_variant_num_gprs (frv_gdbarch_tdep
*var
, int num_gprs
)
226 var
->num_gprs
= num_gprs
;
228 for (r
= 0; r
< num_gprs
; ++r
)
232 xsnprintf (buf
, sizeof (buf
), "gr%d", r
);
233 var
->register_names
[first_gpr_regnum
+ r
] = xstrdup (buf
);
238 /* Indicate that the variant VAR has NUM_FPRS floating-point
239 registers, and fill in the names array appropriately. */
241 set_variant_num_fprs (frv_gdbarch_tdep
*var
, int num_fprs
)
245 var
->num_fprs
= num_fprs
;
247 for (r
= 0; r
< num_fprs
; ++r
)
251 xsnprintf (buf
, sizeof (buf
), "fr%d", r
);
252 var
->register_names
[first_fpr_regnum
+ r
] = xstrdup (buf
);
257 set_variant_abi_fdpic (frv_gdbarch_tdep
*var
)
259 var
->frv_abi
= FRV_ABI_FDPIC
;
260 var
->register_names
[fdpic_loadmap_exec_regnum
] = xstrdup ("loadmap_exec");
261 var
->register_names
[fdpic_loadmap_interp_regnum
]
262 = xstrdup ("loadmap_interp");
266 set_variant_scratch_registers (frv_gdbarch_tdep
*var
)
268 var
->register_names
[scr0_regnum
] = xstrdup ("scr0");
269 var
->register_names
[scr1_regnum
] = xstrdup ("scr1");
270 var
->register_names
[scr2_regnum
] = xstrdup ("scr2");
271 var
->register_names
[scr3_regnum
] = xstrdup ("scr3");
275 frv_register_name (struct gdbarch
*gdbarch
, int reg
)
277 frv_gdbarch_tdep
*tdep
= gdbarch_tdep
<frv_gdbarch_tdep
> (gdbarch
);
278 return tdep
->register_names
[reg
];
283 frv_register_type (struct gdbarch
*gdbarch
, int reg
)
285 if (reg
>= first_fpr_regnum
&& reg
<= last_fpr_regnum
)
286 return builtin_type (gdbarch
)->builtin_float
;
287 else if (reg
== iacc0_regnum
)
288 return builtin_type (gdbarch
)->builtin_int64
;
290 return builtin_type (gdbarch
)->builtin_int32
;
293 static enum register_status
294 frv_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
295 int reg
, gdb_byte
*buffer
)
297 enum register_status status
;
299 if (reg
== iacc0_regnum
)
301 status
= regcache
->raw_read (iacc0h_regnum
, buffer
);
302 if (status
== REG_VALID
)
303 status
= regcache
->raw_read (iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
305 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
307 /* The accg raw registers have four values in each slot with the
308 lowest register number occupying the first byte. */
310 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
311 int byte_num
= (reg
- accg0_regnum
) % 4;
314 status
= regcache
->raw_read (raw_regnum
, buf
);
315 if (status
== REG_VALID
)
317 memset (buffer
, 0, 4);
318 /* FR-V is big endian, so put the requested byte in the
319 first byte of the buffer allocated to hold the
321 buffer
[0] = buf
[byte_num
];
325 gdb_assert_not_reached ("invalid pseudo register number");
331 frv_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
332 int reg
, const gdb_byte
*buffer
)
334 if (reg
== iacc0_regnum
)
336 regcache
->raw_write (iacc0h_regnum
, buffer
);
337 regcache
->raw_write (iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
339 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
341 /* The accg raw registers have four values in each slot with the
342 lowest register number occupying the first byte. */
344 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
345 int byte_num
= (reg
- accg0_regnum
) % 4;
348 regcache
->raw_read (raw_regnum
, buf
);
349 buf
[byte_num
] = ((bfd_byte
*) buffer
)[0];
350 regcache
->raw_write (raw_regnum
, buf
);
355 frv_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
357 static const int spr_map
[] =
359 H_SPR_PSR
, /* psr_regnum */
360 H_SPR_CCR
, /* ccr_regnum */
361 H_SPR_CCCR
, /* cccr_regnum */
362 -1, /* fdpic_loadmap_exec_regnum */
363 -1, /* fdpic_loadmap_interp_regnum */
365 H_SPR_TBR
, /* tbr_regnum */
366 H_SPR_BRR
, /* brr_regnum */
367 H_SPR_DBAR0
, /* dbar0_regnum */
368 H_SPR_DBAR1
, /* dbar1_regnum */
369 H_SPR_DBAR2
, /* dbar2_regnum */
370 H_SPR_DBAR3
, /* dbar3_regnum */
371 H_SPR_SCR0
, /* scr0_regnum */
372 H_SPR_SCR1
, /* scr1_regnum */
373 H_SPR_SCR2
, /* scr2_regnum */
374 H_SPR_SCR3
, /* scr3_regnum */
375 H_SPR_LR
, /* lr_regnum */
376 H_SPR_LCR
, /* lcr_regnum */
377 H_SPR_IACC0H
, /* iacc0h_regnum */
378 H_SPR_IACC0L
, /* iacc0l_regnum */
379 H_SPR_FSR0
, /* fsr0_regnum */
380 /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */
381 -1, /* acc0_regnum */
382 -1, /* acc1_regnum */
383 -1, /* acc2_regnum */
384 -1, /* acc3_regnum */
385 -1, /* acc4_regnum */
386 -1, /* acc5_regnum */
387 -1, /* acc6_regnum */
388 -1, /* acc7_regnum */
389 -1, /* acc0123_regnum */
390 -1, /* acc4567_regnum */
391 H_SPR_MSR0
, /* msr0_regnum */
392 H_SPR_MSR1
, /* msr1_regnum */
393 H_SPR_GNER0
, /* gner0_regnum */
394 H_SPR_GNER1
, /* gner1_regnum */
395 H_SPR_FNER0
, /* fner0_regnum */
396 H_SPR_FNER1
, /* fner1_regnum */
399 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
401 if (first_gpr_regnum
<= reg
&& reg
<= last_gpr_regnum
)
402 return reg
- first_gpr_regnum
+ SIM_FRV_GR0_REGNUM
;
403 else if (first_fpr_regnum
<= reg
&& reg
<= last_fpr_regnum
)
404 return reg
- first_fpr_regnum
+ SIM_FRV_FR0_REGNUM
;
405 else if (pc_regnum
== reg
)
406 return SIM_FRV_PC_REGNUM
;
407 else if (reg
>= first_spr_regnum
408 && reg
< first_spr_regnum
+ sizeof (spr_map
) / sizeof (spr_map
[0]))
410 int spr_reg_offset
= spr_map
[reg
- first_spr_regnum
];
412 if (spr_reg_offset
< 0)
413 return SIM_REGNO_DOES_NOT_EXIST
;
415 return SIM_FRV_SPR0_REGNUM
+ spr_reg_offset
;
418 internal_error (_("Bad register number %d"), reg
);
421 constexpr gdb_byte frv_break_insn
[] = {0xc0, 0x70, 0x00, 0x01};
423 typedef BP_MANIPULATION (frv_break_insn
) frv_breakpoint
;
425 /* Define the maximum number of instructions which may be packed into a
426 bundle (VLIW instruction). */
427 static const int max_instrs_per_bundle
= 8;
429 /* Define the size (in bytes) of an FR-V instruction. */
430 static const int frv_instr_size
= 4;
432 /* Adjust a breakpoint's address to account for the FR-V architecture's
433 constraint that a break instruction must not appear as any but the
434 first instruction in the bundle. */
436 frv_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
438 int count
= max_instrs_per_bundle
;
439 CORE_ADDR addr
= bpaddr
- frv_instr_size
;
440 CORE_ADDR func_start
= get_pc_function_start (bpaddr
);
442 /* Find the end of the previous packing sequence. This will be indicated
443 by either attempting to access some inaccessible memory or by finding
444 an instruction word whose packing bit is set to one. */
445 while (count
-- > 0 && addr
>= func_start
)
447 gdb_byte instr
[frv_instr_size
];
450 status
= target_read_memory (addr
, instr
, sizeof instr
);
455 /* This is a big endian architecture, so byte zero will have most
456 significant byte. The most significant bit of this byte is the
461 addr
-= frv_instr_size
;
465 bpaddr
= addr
+ frv_instr_size
;
471 /* Return true if REG is a caller-saves ("scratch") register,
474 is_caller_saves_reg (int reg
)
476 return ((4 <= reg
&& reg
<= 7)
477 || (14 <= reg
&& reg
<= 15)
478 || (32 <= reg
&& reg
<= 47));
482 /* Return true if REG is a callee-saves register, false otherwise. */
484 is_callee_saves_reg (int reg
)
486 return ((16 <= reg
&& reg
<= 31)
487 || (48 <= reg
&& reg
<= 63));
491 /* Return true if REG is an argument register, false otherwise. */
493 is_argument_reg (int reg
)
495 return (8 <= reg
&& reg
<= 13);
498 /* Scan an FR-V prologue, starting at PC, until frame->PC.
499 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
500 We assume FRAME's saved_regs array has already been allocated and cleared.
501 Return the first PC value after the prologue.
503 Note that, for unoptimized code, we almost don't need this function
504 at all; all arguments and locals live on the stack, so we just need
505 the FP to find everything. The catch: structures passed by value
506 have their addresses living in registers; they're never spilled to
507 the stack. So if you ever want to be able to get to these
508 arguments in any frame but the top, you'll need to do this serious
509 prologue analysis. */
511 frv_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
512 const frame_info_ptr
&this_frame
,
513 struct frv_unwind_cache
*info
)
515 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
517 /* When writing out instruction bitpatterns, we use the following
518 letters to label instruction fields:
519 P - The parallel bit. We don't use this.
520 J - The register number of GRj in the instruction description.
521 K - The register number of GRk in the instruction description.
522 I - The register number of GRi.
523 S - a signed immediate offset.
524 U - an unsigned immediate offset.
526 The dots below the numbers indicate where hex digit boundaries
527 fall, to make it easier to check the numbers. */
529 /* Non-zero iff we've seen the instruction that initializes the
530 frame pointer for this function's frame. */
533 /* If fp_set is non_zero, then this is the distance from
534 the stack pointer to frame pointer: fp = sp + fp_offset. */
537 /* Total size of frame prior to any alloca operations. */
540 /* Flag indicating if lr has been saved on the stack. */
541 int lr_saved_on_stack
= 0;
543 /* The number of the general-purpose register we saved the return
544 address ("link register") in, or -1 if we haven't moved it yet. */
545 int lr_save_reg
= -1;
547 /* Offset (from sp) at which lr has been saved on the stack. */
549 int lr_sp_offset
= 0;
551 /* If gr_saved[i] is non-zero, then we've noticed that general
552 register i has been saved at gr_sp_offset[i] from the stack
555 int gr_sp_offset
[64];
557 /* The address of the most recently scanned prologue instruction. */
558 CORE_ADDR last_prologue_pc
;
560 /* The address of the next instruction. */
563 /* The upper bound to of the pc values to scan. */
566 memset (gr_saved
, 0, sizeof (gr_saved
));
568 last_prologue_pc
= pc
;
570 /* Try to compute an upper limit (on how far to scan) based on the
572 lim_pc
= skip_prologue_using_sal (gdbarch
, pc
);
573 /* If there's no line number info, lim_pc will be 0. In that case,
574 set the limit to be 100 instructions away from pc. Hopefully, this
575 will be far enough away to account for the entire prologue. Don't
576 worry about overshooting the end of the function. The scan loop
577 below contains some checks to avoid scanning unreasonably far. */
581 /* If we have a frame, we don't want to scan past the frame's pc. This
582 will catch those cases where the pc is in the prologue. */
585 CORE_ADDR frame_pc
= get_frame_pc (this_frame
);
586 if (frame_pc
< lim_pc
)
590 /* Scan the prologue. */
593 gdb_byte buf
[frv_instr_size
];
596 if (target_read_memory (pc
, buf
, sizeof buf
) != 0)
598 op
= extract_signed_integer (buf
, byte_order
);
602 /* The tests in this chain of ifs should be in order of
603 decreasing selectivity, so that more particular patterns get
604 to fire before less particular patterns. */
606 /* Some sort of control transfer instruction: stop scanning prologue.
607 Integer Conditional Branch:
608 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
609 Floating-point / media Conditional Branch:
610 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
611 LCR Conditional Branch to LR
612 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
613 Integer conditional Branches to LR
614 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
615 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
616 Floating-point/Media Branches to LR
617 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
618 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
620 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
621 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
623 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
625 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
626 Integer Conditional Trap
627 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
628 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
629 Floating-point /media Conditional Trap
630 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
631 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
633 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
635 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
636 if ((op
& 0x01d80000) == 0x00180000 /* Conditional branches and Call */
637 || (op
& 0x01f80000) == 0x00300000 /* Jump and Link */
638 || (op
& 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
639 || (op
& 0x01f80000) == 0x00700000) /* Trap immediate */
641 /* Stop scanning; not in prologue any longer. */
645 /* Loading something from memory into fp probably means that
646 we're in the epilogue. Stop scanning the prologue.
648 X 000010 0000010 XXXXXX 000100 XXXXXX
650 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
651 else if ((op
& 0x7ffc0fc0) == 0x04080100
652 || (op
& 0x7ffc0000) == 0x04c80000)
657 /* Setting the FP from the SP:
659 P 000010 0100010 000001 000000000000 = 0x04881000
660 0 111111 1111111 111111 111111111111 = 0x7fffffff
662 We treat this as part of the prologue. */
663 else if ((op
& 0x7fffffff) == 0x04881000)
667 last_prologue_pc
= next_pc
;
670 /* Move the link register to the scratch register grJ, before saving:
672 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
673 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
675 We treat this as part of the prologue. */
676 else if ((op
& 0x7fffffc0) == 0x080d01c0)
678 int gr_j
= op
& 0x3f;
680 /* If we're moving it to a scratch register, that's fine. */
681 if (is_caller_saves_reg (gr_j
))
684 last_prologue_pc
= next_pc
;
688 /* To save multiple callee-saves registers on the stack, at
692 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
693 0 000000 1111111 111111 111111 111111 = 0x01ffffff
696 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
697 0 000000 1111111 111111 111111 111111 = 0x01ffffff
699 We treat this as part of the prologue, and record the register's
700 saved address in the frame structure. */
701 else if ((op
& 0x01ffffff) == 0x000c10c0
702 || (op
& 0x01ffffff) == 0x000c1100)
704 int gr_k
= ((op
>> 25) & 0x3f);
705 int ope
= ((op
>> 6) & 0x3f);
709 /* Is it an std or an stq? */
715 /* Is it really a callee-saves register? */
716 if (is_callee_saves_reg (gr_k
))
718 for (i
= 0; i
< count
; i
++)
720 gr_saved
[gr_k
+ i
] = 1;
721 gr_sp_offset
[gr_k
+ i
] = 4 * i
;
723 last_prologue_pc
= next_pc
;
727 /* Adjusting the stack pointer. (The stack pointer is GR1.)
729 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
730 0 111111 1111111 111111 000000000000 = 0x7ffff000
732 We treat this as part of the prologue. */
733 else if ((op
& 0x7ffff000) == 0x02401000)
737 /* Sign-extend the twelve-bit field.
738 (Isn't there a better way to do this?) */
739 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
742 last_prologue_pc
= pc
;
746 /* If the prologue is being adjusted again, we've
747 likely gone too far; i.e. we're probably in the
753 /* Setting the FP to a constant distance from the SP:
755 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
756 0 111111 1111111 111111 000000000000 = 0x7ffff000
758 We treat this as part of the prologue. */
759 else if ((op
& 0x7ffff000) == 0x04401000)
761 /* Sign-extend the twelve-bit field.
762 (Isn't there a better way to do this?) */
763 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
766 last_prologue_pc
= pc
;
769 /* To spill an argument register to a scratch register:
771 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
772 0 000000 1111111 000000 111111111111 = 0x01fc0fff
774 For the time being, we treat this as a prologue instruction,
775 assuming that GRi is an argument register. This one's kind
776 of suspicious, because it seems like it could be part of a
777 legitimate body instruction. But we only come here when the
778 source info wasn't helpful, so we have to do the best we can.
779 Hopefully once GCC and GDB agree on how to emit line number
780 info for prologues, then this code will never come into play. */
781 else if ((op
& 0x01fc0fff) == 0x00880000)
783 int gr_i
= ((op
>> 12) & 0x3f);
785 /* Make sure that the source is an arg register; if it is, we'll
786 treat it as a prologue instruction. */
787 if (is_argument_reg (gr_i
))
788 last_prologue_pc
= next_pc
;
791 /* To spill 16-bit values to the stack:
793 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
794 0 000000 1111111 111111 000000000000 = 0x01fff000
796 And for 8-bit values, we use STB instructions.
798 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
799 0 000000 1111111 111111 000000000000 = 0x01fff000
801 We check that GRk is really an argument register, and treat
802 all such as part of the prologue. */
803 else if ( (op
& 0x01fff000) == 0x01442000
804 || (op
& 0x01fff000) == 0x01402000)
806 int gr_k
= ((op
>> 25) & 0x3f);
808 /* Make sure that GRk is really an argument register; treat
809 it as a prologue instruction if so. */
810 if (is_argument_reg (gr_k
))
811 last_prologue_pc
= next_pc
;
814 /* To save multiple callee-saves register on the stack, at a
818 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
819 0 000000 1111111 111111 000000000000 = 0x01fff000
822 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
823 0 000000 1111111 111111 000000000000 = 0x01fff000
825 We treat this as part of the prologue, and record the register's
826 saved address in the frame structure. */
827 else if ((op
& 0x01fff000) == 0x014c1000
828 || (op
& 0x01fff000) == 0x01501000)
830 int gr_k
= ((op
>> 25) & 0x3f);
834 /* Is it a stdi or a stqi? */
835 if ((op
& 0x01fff000) == 0x014c1000)
840 /* Is it really a callee-saves register? */
841 if (is_callee_saves_reg (gr_k
))
843 /* Sign-extend the twelve-bit field.
844 (Isn't there a better way to do this?) */
845 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
847 for (i
= 0; i
< count
; i
++)
849 gr_saved
[gr_k
+ i
] = 1;
850 gr_sp_offset
[gr_k
+ i
] = s
+ (4 * i
);
852 last_prologue_pc
= next_pc
;
856 /* Storing any kind of integer register at any constant offset
857 from any other register.
860 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
861 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
864 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
865 0 000000 1111111 000000 000000000000 = 0x01fc0000
867 These could be almost anything, but a lot of prologue
868 instructions fall into this pattern, so let's decode the
869 instruction once, and then work at a higher level. */
870 else if (((op
& 0x01fc0fff) == 0x000c0080)
871 || ((op
& 0x01fc0000) == 0x01480000))
873 int gr_k
= ((op
>> 25) & 0x3f);
874 int gr_i
= ((op
>> 12) & 0x3f);
877 /* Are we storing with gr0 as an offset, or using an
879 if ((op
& 0x01fc0fff) == 0x000c0080)
882 offset
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
884 /* If the address isn't relative to the SP or FP, it's not a
885 prologue instruction. */
886 if (gr_i
!= sp_regnum
&& gr_i
!= fp_regnum
)
888 /* Do nothing; not a prologue instruction. */
891 /* Saving the old FP in the new frame (relative to the SP). */
892 else if (gr_k
== fp_regnum
&& gr_i
== sp_regnum
)
894 gr_saved
[fp_regnum
] = 1;
895 gr_sp_offset
[fp_regnum
] = offset
;
896 last_prologue_pc
= next_pc
;
899 /* Saving callee-saves register(s) on the stack, relative to
901 else if (gr_i
== sp_regnum
902 && is_callee_saves_reg (gr_k
))
905 if (gr_i
== sp_regnum
)
906 gr_sp_offset
[gr_k
] = offset
;
908 gr_sp_offset
[gr_k
] = offset
+ fp_offset
;
909 last_prologue_pc
= next_pc
;
912 /* Saving the scratch register holding the return address. */
913 else if (lr_save_reg
!= -1
914 && gr_k
== lr_save_reg
)
916 lr_saved_on_stack
= 1;
917 if (gr_i
== sp_regnum
)
918 lr_sp_offset
= offset
;
920 lr_sp_offset
= offset
+ fp_offset
;
921 last_prologue_pc
= next_pc
;
924 /* Spilling int-sized arguments to the stack. */
925 else if (is_argument_reg (gr_k
))
926 last_prologue_pc
= next_pc
;
931 if (this_frame
&& info
)
936 /* If we know the relationship between the stack and frame
937 pointers, record the addresses of the registers we noticed.
938 Note that we have to do this as a separate step at the end,
939 because instructions may save relative to the SP, but we need
940 their addresses relative to the FP. */
942 this_base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
944 this_base
= get_frame_register_unsigned (this_frame
, sp_regnum
);
946 for (i
= 0; i
< 64; i
++)
948 info
->saved_regs
[i
].set_addr (this_base
- fp_offset
951 info
->prev_sp
= this_base
- fp_offset
+ framesize
;
952 info
->base
= this_base
;
954 /* If LR was saved on the stack, record its location. */
955 if (lr_saved_on_stack
)
956 info
->saved_regs
[lr_regnum
].set_addr (this_base
- fp_offset
959 /* The call instruction moves the caller's PC in the callee's LR.
960 Since this is an unwind, do the reverse. Copy the location of LR
961 into PC (the address / regnum) so that a request for PC will be
962 converted into a request for the LR. */
963 info
->saved_regs
[pc_regnum
] = info
->saved_regs
[lr_regnum
];
965 /* Save the previous frame's computed SP value. */
966 info
->saved_regs
[sp_regnum
].set_value (info
->prev_sp
);
969 return last_prologue_pc
;
974 frv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
976 CORE_ADDR func_addr
, func_end
, new_pc
;
980 /* If the line table has entry for a line *within* the function
981 (i.e., not in the prologue, and not past the end), then that's
983 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
985 struct symtab_and_line sal
;
987 sal
= find_pc_line (func_addr
, 0);
989 if (sal
.line
!= 0 && sal
.end
< func_end
)
995 /* The FR-V prologue is at least five instructions long (twenty bytes).
996 If we didn't find a real source location past that, then
997 do a full analysis of the prologue. */
998 if (new_pc
< pc
+ 20)
999 new_pc
= frv_analyze_prologue (gdbarch
, pc
, 0, 0);
1005 /* Examine the instruction pointed to by PC. If it corresponds to
1006 a call to __main, return the address of the next instruction.
1007 Otherwise, return PC. */
1010 frv_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1012 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1015 CORE_ADDR orig_pc
= pc
;
1017 if (target_read_memory (pc
, buf
, 4))
1019 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1021 /* In PIC code, GR15 may be loaded from some offset off of FP prior
1022 to the call instruction.
1024 Skip over this instruction if present. It won't be present in
1025 non-PIC code, and even in PIC code, it might not be present.
1026 (This is due to the fact that GR15, the FDPIC register, already
1027 contains the correct value.)
1029 The general form of the LDI is given first, followed by the
1030 specific instruction with the GRi and GRk filled in as FP and
1033 ldi @(GRi, d12), GRk
1034 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000
1035 0 000000 1111111 000000 000000000000 = 0x01fc0000
1037 ldi @(FP, d12), GR15
1038 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000
1039 0 001111 1111111 000010 000000000000 = 0x7ffff000
1042 if ((op
& 0x7ffff000) == 0x1ec82000)
1045 if (target_read_memory (pc
, buf
, 4))
1047 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1050 /* The format of an FRV CALL instruction is as follows:
1053 P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000
1054 0 000000 1111111 000000000000000000 = 0x01fc0000
1057 where label24 is constructed by concatenating the H bits with the
1058 L bits. The call target is PC + (4 * sign_ext(label24)). */
1060 if ((op
& 0x01fc0000) == 0x003c0000)
1063 CORE_ADDR call_dest
;
1064 struct bound_minimal_symbol s
;
1066 displ
= ((op
& 0xfe000000) >> 7) | (op
& 0x0003ffff);
1067 if ((displ
& 0x00800000) != 0)
1068 displ
|= ~((LONGEST
) 0x00ffffff);
1070 call_dest
= pc
+ 4 * displ
;
1071 s
= lookup_minimal_symbol_by_pc (call_dest
);
1073 if (s
.minsym
!= NULL
1074 && s
.minsym
->linkage_name () != NULL
1075 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1085 static struct frv_unwind_cache
*
1086 frv_frame_unwind_cache (const frame_info_ptr
&this_frame
,
1087 void **this_prologue_cache
)
1089 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1090 struct frv_unwind_cache
*info
;
1092 if ((*this_prologue_cache
))
1093 return (struct frv_unwind_cache
*) (*this_prologue_cache
);
1095 info
= FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache
);
1096 (*this_prologue_cache
) = info
;
1097 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1099 /* Prologue analysis does the rest... */
1100 frv_analyze_prologue (gdbarch
,
1101 get_frame_func (this_frame
), this_frame
, info
);
1107 frv_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1110 struct gdbarch
*gdbarch
= regcache
->arch ();
1111 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1112 int len
= type
->length ();
1117 regcache_cooked_read_unsigned (regcache
, 8, &gpr8_val
);
1118 store_unsigned_integer (valbuf
, len
, byte_order
, gpr8_val
);
1124 regcache_cooked_read_unsigned (regcache
, 8, ®val
);
1125 store_unsigned_integer (valbuf
, 4, byte_order
, regval
);
1126 regcache_cooked_read_unsigned (regcache
, 9, ®val
);
1127 store_unsigned_integer ((bfd_byte
*) valbuf
+ 4, 4, byte_order
, regval
);
1130 internal_error (_("Illegal return value length: %d"), len
);
1134 frv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1136 /* Require dword alignment. */
1137 return align_down (sp
, 8);
1141 find_func_descr (struct gdbarch
*gdbarch
, CORE_ADDR entry_point
)
1143 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1146 CORE_ADDR start_addr
;
1148 /* If we can't find the function in the symbol table, then we assume
1149 that the function address is already in descriptor form. */
1150 if (!find_pc_partial_function (entry_point
, NULL
, &start_addr
, NULL
)
1151 || entry_point
!= start_addr
)
1154 descr
= frv_fdpic_find_canonical_descriptor (entry_point
);
1159 /* Construct a non-canonical descriptor from space allocated on
1162 descr
= value_as_long (value_allocate_space_in_inferior (8));
1163 store_unsigned_integer (valbuf
, 4, byte_order
, entry_point
);
1164 write_memory (descr
, valbuf
, 4);
1165 store_unsigned_integer (valbuf
, 4, byte_order
,
1166 frv_fdpic_find_global_pointer (entry_point
));
1167 write_memory (descr
+ 4, valbuf
, 4);
1172 frv_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1173 struct target_ops
*targ
)
1175 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1176 CORE_ADDR entry_point
;
1177 CORE_ADDR got_address
;
1179 entry_point
= get_target_memory_unsigned (targ
, addr
, 4, byte_order
);
1180 got_address
= get_target_memory_unsigned (targ
, addr
+ 4, 4, byte_order
);
1182 if (got_address
== frv_fdpic_find_global_pointer (entry_point
))
1189 frv_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1190 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1191 int nargs
, struct value
**args
, CORE_ADDR sp
,
1192 function_call_return_method return_method
,
1193 CORE_ADDR struct_addr
)
1195 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1198 const gdb_byte
*val
;
1201 struct type
*arg_type
;
1203 enum type_code typecode
;
1207 enum frv_abi abi
= frv_abi (gdbarch
);
1208 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1211 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1212 nargs
, (int) sp
, struct_return
, struct_addr
);
1216 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1217 stack_space
+= align_up (args
[argnum
]->type ()->length (), 4);
1219 stack_space
-= (6 * 4);
1220 if (stack_space
> 0)
1223 /* Make sure stack is dword aligned. */
1224 sp
= align_down (sp
, 8);
1230 if (return_method
== return_method_struct
)
1231 regcache_cooked_write_unsigned (regcache
, struct_return_regnum
,
1234 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1237 arg_type
= check_typedef (arg
->type ());
1238 len
= arg_type
->length ();
1239 typecode
= arg_type
->code ();
1241 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
1243 store_unsigned_integer (valbuf
, 4, byte_order
,
1245 typecode
= TYPE_CODE_PTR
;
1249 else if (abi
== FRV_ABI_FDPIC
1251 && typecode
== TYPE_CODE_PTR
1252 && arg_type
->target_type ()->code () == TYPE_CODE_FUNC
)
1254 /* The FDPIC ABI requires function descriptors to be passed instead
1256 CORE_ADDR addr
= extract_unsigned_integer
1257 (arg
->contents ().data (), 4, byte_order
);
1258 addr
= find_func_descr (gdbarch
, addr
);
1259 store_unsigned_integer (valbuf
, 4, byte_order
, addr
);
1260 typecode
= TYPE_CODE_PTR
;
1266 val
= arg
->contents ().data ();
1271 int partial_len
= (len
< 4 ? len
: 4);
1275 regval
= extract_unsigned_integer (val
, partial_len
, byte_order
);
1277 printf(" Argnum %d data %x -> reg %d\n",
1278 argnum
, (int) regval
, argreg
);
1280 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1286 printf(" Argnum %d data %x -> offset %d (%x)\n",
1287 argnum
, *((int *)val
), stack_offset
,
1288 (int) (sp
+ stack_offset
));
1290 write_memory (sp
+ stack_offset
, val
, partial_len
);
1291 stack_offset
+= align_up (partial_len
, 4);
1298 /* Set the return address. For the frv, the return breakpoint is
1299 always at BP_ADDR. */
1300 regcache_cooked_write_unsigned (regcache
, lr_regnum
, bp_addr
);
1302 if (abi
== FRV_ABI_FDPIC
)
1304 /* Set the GOT register for the FDPIC ABI. */
1305 regcache_cooked_write_unsigned
1306 (regcache
, first_gpr_regnum
+ 15,
1307 frv_fdpic_find_global_pointer (func_addr
));
1310 /* Finally, update the SP register. */
1311 regcache_cooked_write_unsigned (regcache
, sp_regnum
, sp
);
1317 frv_store_return_value (struct type
*type
, struct regcache
*regcache
,
1318 const gdb_byte
*valbuf
)
1320 int len
= type
->length ();
1325 memset (val
, 0, sizeof (val
));
1326 memcpy (val
+ (4 - len
), valbuf
, len
);
1327 regcache
->cooked_write (8, val
);
1331 regcache
->cooked_write (8, valbuf
);
1332 regcache
->cooked_write (9, (bfd_byte
*) valbuf
+ 4);
1335 internal_error (_("Don't know how to return a %d-byte value."), len
);
1338 static enum return_value_convention
1339 frv_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1340 struct type
*valtype
, struct regcache
*regcache
,
1341 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1343 int struct_return
= valtype
->code () == TYPE_CODE_STRUCT
1344 || valtype
->code () == TYPE_CODE_UNION
1345 || valtype
->code () == TYPE_CODE_ARRAY
;
1347 if (writebuf
!= NULL
)
1349 gdb_assert (!struct_return
);
1350 frv_store_return_value (valtype
, regcache
, writebuf
);
1353 if (readbuf
!= NULL
)
1355 gdb_assert (!struct_return
);
1356 frv_extract_return_value (valtype
, regcache
, readbuf
);
1360 return RETURN_VALUE_STRUCT_CONVENTION
;
1362 return RETURN_VALUE_REGISTER_CONVENTION
;
1365 /* Given a GDB frame, determine the address of the calling function's
1366 frame. This will be used to create a new GDB frame struct. */
1369 frv_frame_this_id (const frame_info_ptr
&this_frame
,
1370 void **this_prologue_cache
, struct frame_id
*this_id
)
1372 struct frv_unwind_cache
*info
1373 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1376 struct bound_minimal_symbol msym_stack
;
1379 /* The FUNC is easy. */
1380 func
= get_frame_func (this_frame
);
1382 /* Check if the stack is empty. */
1383 msym_stack
= lookup_minimal_symbol ("_stack", NULL
, NULL
);
1384 if (msym_stack
.minsym
&& info
->base
== msym_stack
.value_address ())
1387 /* Hopefully the prologue analysis either correctly determined the
1388 frame's base (which is the SP from the previous frame), or set
1389 that base to "NULL". */
1390 base
= info
->prev_sp
;
1394 id
= frame_id_build (base
, func
);
1398 static struct value
*
1399 frv_frame_prev_register (const frame_info_ptr
&this_frame
,
1400 void **this_prologue_cache
, int regnum
)
1402 struct frv_unwind_cache
*info
1403 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1404 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1407 static const struct frame_unwind frv_frame_unwind
= {
1410 default_frame_unwind_stop_reason
,
1412 frv_frame_prev_register
,
1414 default_frame_sniffer
1418 frv_frame_base_address (const frame_info_ptr
&this_frame
, void **this_cache
)
1420 struct frv_unwind_cache
*info
1421 = frv_frame_unwind_cache (this_frame
, this_cache
);
1425 static const struct frame_base frv_frame_base
= {
1427 frv_frame_base_address
,
1428 frv_frame_base_address
,
1429 frv_frame_base_address
1432 static struct gdbarch
*
1433 frv_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1437 /* Check to see if we've already built an appropriate architecture
1438 object for this executable. */
1439 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1441 return arches
->gdbarch
;
1443 /* Select the right tdep structure for this variant. */
1444 gdbarch
*gdbarch
= gdbarch_alloc (&info
, new_variant ());
1445 frv_gdbarch_tdep
*var
= gdbarch_tdep
<frv_gdbarch_tdep
> (gdbarch
);
1447 switch (info
.bfd_arch_info
->mach
)
1450 case bfd_mach_frvsimple
:
1451 case bfd_mach_fr300
:
1452 case bfd_mach_fr500
:
1453 case bfd_mach_frvtomcat
:
1454 case bfd_mach_fr550
:
1455 set_variant_num_gprs (var
, 64);
1456 set_variant_num_fprs (var
, 64);
1459 case bfd_mach_fr400
:
1460 case bfd_mach_fr450
:
1461 set_variant_num_gprs (var
, 32);
1462 set_variant_num_fprs (var
, 32);
1466 /* Never heard of this variant. */
1470 /* Extract the ELF flags, if available. */
1471 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
1472 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
1474 if (elf_flags
& EF_FRV_FDPIC
)
1475 set_variant_abi_fdpic (var
);
1477 if (elf_flags
& EF_FRV_CPU_FR450
)
1478 set_variant_scratch_registers (var
);
1480 set_gdbarch_short_bit (gdbarch
, 16);
1481 set_gdbarch_int_bit (gdbarch
, 32);
1482 set_gdbarch_long_bit (gdbarch
, 32);
1483 set_gdbarch_long_long_bit (gdbarch
, 64);
1484 set_gdbarch_float_bit (gdbarch
, 32);
1485 set_gdbarch_double_bit (gdbarch
, 64);
1486 set_gdbarch_long_double_bit (gdbarch
, 64);
1487 set_gdbarch_ptr_bit (gdbarch
, 32);
1489 set_gdbarch_num_regs (gdbarch
, frv_num_regs
);
1490 set_gdbarch_num_pseudo_regs (gdbarch
, frv_num_pseudo_regs
);
1492 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
1493 set_gdbarch_deprecated_fp_regnum (gdbarch
, fp_regnum
);
1494 set_gdbarch_pc_regnum (gdbarch
, pc_regnum
);
1496 set_gdbarch_register_name (gdbarch
, frv_register_name
);
1497 set_gdbarch_register_type (gdbarch
, frv_register_type
);
1498 set_gdbarch_register_sim_regno (gdbarch
, frv_register_sim_regno
);
1500 set_gdbarch_pseudo_register_read (gdbarch
, frv_pseudo_register_read
);
1501 set_gdbarch_deprecated_pseudo_register_write (gdbarch
,
1502 frv_pseudo_register_write
);
1504 set_gdbarch_skip_prologue (gdbarch
, frv_skip_prologue
);
1505 set_gdbarch_skip_main_prologue (gdbarch
, frv_skip_main_prologue
);
1506 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, frv_breakpoint::kind_from_pc
);
1507 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, frv_breakpoint::bp_from_kind
);
1508 set_gdbarch_adjust_breakpoint_address
1509 (gdbarch
, frv_adjust_breakpoint_address
);
1511 set_gdbarch_return_value (gdbarch
, frv_return_value
);
1514 set_gdbarch_frame_align (gdbarch
, frv_frame_align
);
1515 frame_base_set_default (gdbarch
, &frv_frame_base
);
1516 /* We set the sniffer lower down after the OSABI hooks have been
1519 /* Settings for calling functions in the inferior. */
1520 set_gdbarch_push_dummy_call (gdbarch
, frv_push_dummy_call
);
1522 /* Settings that should be unnecessary. */
1523 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1525 /* Hardware watchpoint / breakpoint support. */
1526 switch (info
.bfd_arch_info
->mach
)
1529 case bfd_mach_frvsimple
:
1530 case bfd_mach_fr300
:
1531 case bfd_mach_fr500
:
1532 case bfd_mach_frvtomcat
:
1533 /* fr500-style hardware debugging support. */
1534 var
->num_hw_watchpoints
= 4;
1535 var
->num_hw_breakpoints
= 4;
1538 case bfd_mach_fr400
:
1539 case bfd_mach_fr450
:
1540 /* fr400-style hardware debugging support. */
1541 var
->num_hw_watchpoints
= 2;
1542 var
->num_hw_breakpoints
= 4;
1546 /* Otherwise, assume we don't have hardware debugging support. */
1547 var
->num_hw_watchpoints
= 0;
1548 var
->num_hw_breakpoints
= 0;
1552 if (frv_abi (gdbarch
) == FRV_ABI_FDPIC
)
1553 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
1554 frv_convert_from_func_ptr_addr
);
1556 set_gdbarch_so_ops (gdbarch
, &frv_so_ops
);
1558 /* Hook in ABI-specific overrides, if they have been registered. */
1559 gdbarch_init_osabi (info
, gdbarch
);
1561 /* Set the fallback (prologue based) frame sniffer. */
1562 frame_unwind_append_unwinder (gdbarch
, &frv_frame_unwind
);
1564 /* Enable TLS support. */
1565 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1566 frv_fetch_objfile_link_map
);
1571 void _initialize_frv_tdep ();
1573 _initialize_frv_tdep ()
1575 gdbarch_register (bfd_arch_frv
, frv_gdbarch_init
);