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[binutils-gdb.git] / gdb / csky-tdep.c
blob5f0fd3d7170d536eb82a3256586aa0b4f6983ee1
1 /* Target-dependent code for the CSKY architecture, for GDB.
2
3 Copyright (C) 2010-2024 Free Software Foundation, Inc.
4
5 Contributed by C-SKY Microsystems and Mentor Graphics.
6
7 This file is part of GDB.
8
9 This program is free software; you can redistribute it and/or modify
10 it under the terms of the GNU General Public License as published by
11 the Free Software Foundation; either version 3 of the License, or
12 (at your option) any later version.
13
14 This program is distributed in the hope that it will be useful,
15 but WITHOUT ANY WARRANTY; without even the implied warranty of
16 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 GNU General Public License for more details.
18
19 You should have received a copy of the GNU General Public License
20 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21
22 #include "gdbsupport/gdb_assert.h"
23 #include "frame.h"
24 #include "inferior.h"
25 #include "symtab.h"
26 #include "value.h"
27 #include "gdbcmd.h"
28 #include "language.h"
29 #include "gdbcore.h"
30 #include "symfile.h"
31 #include "objfiles.h"
32 #include "gdbtypes.h"
33 #include "target.h"
34 #include "arch-utils.h"
35 #include "regcache.h"
36 #include "osabi.h"
37 #include "block.h"
38 #include "reggroups.h"
39 #include "elf/csky.h"
40 #include "elf-bfd.h"
41 #include "symcat.h"
42 #include "sim-regno.h"
43 #include "dis-asm.h"
44 #include "frame-unwind.h"
45 #include "frame-base.h"
46 #include "trad-frame.h"
47 #include "infcall.h"
48 #include "floatformat.h"
49 #include "remote.h"
50 #include "target-descriptions.h"
51 #include "dwarf2/frame.h"
52 #include "user-regs.h"
53 #include "valprint.h"
54 #include "csky-tdep.h"
55 #include "regset.h"
56 #include "opcode/csky.h"
57 #include <algorithm>
58 #include <vector>
59
60 /* Control debugging information emitted in this file. */
61
62 static bool csky_debug = false;
63
64 static const reggroup *cr_reggroup;
65 static const reggroup *fr_reggroup;
66 static const reggroup *vr_reggroup;
67 static const reggroup *mmu_reggroup;
68 static const reggroup *prof_reggroup;
69
70 static const char *csky_supported_tdesc_feature_names[] = {
71 (const char *)"org.gnu.csky.abiv2.gpr",
72 (const char *)"org.gnu.csky.abiv2.fpu",
73 (const char *)"org.gnu.csky.abiv2.cr",
74 (const char *)"org.gnu.csky.abiv2.fvcr",
75 (const char *)"org.gnu.csky.abiv2.mmu",
76 (const char *)"org.gnu.csky.abiv2.tee",
77 (const char *)"org.gnu.csky.abiv2.fpu2",
78 (const char *)"org.gnu.csky.abiv2.bank0",
79 (const char *)"org.gnu.csky.abiv2.bank1",
80 (const char *)"org.gnu.csky.abiv2.bank2",
81 (const char *)"org.gnu.csky.abiv2.bank3",
82 (const char *)"org.gnu.csky.abiv2.bank4",
83 (const char *)"org.gnu.csky.abiv2.bank5",
84 (const char *)"org.gnu.csky.abiv2.bank6",
85 (const char *)"org.gnu.csky.abiv2.bank7",
86 (const char *)"org.gnu.csky.abiv2.bank8",
87 (const char *)"org.gnu.csky.abiv2.bank9",
88 (const char *)"org.gnu.csky.abiv2.bank10",
89 (const char *)"org.gnu.csky.abiv2.bank11",
90 (const char *)"org.gnu.csky.abiv2.bank12",
91 (const char *)"org.gnu.csky.abiv2.bank13",
92 (const char *)"org.gnu.csky.abiv2.bank14",
93 (const char *)"org.gnu.csky.abiv2.bank15",
94 (const char *)"org.gnu.csky.abiv2.bank16",
95 (const char *)"org.gnu.csky.abiv2.bank17",
96 (const char *)"org.gnu.csky.abiv2.bank18",
97 (const char *)"org.gnu.csky.abiv2.bank19",
98 (const char *)"org.gnu.csky.abiv2.bank20",
99 (const char *)"org.gnu.csky.abiv2.bank21",
100 (const char *)"org.gnu.csky.abiv2.bank22",
101 (const char *)"org.gnu.csky.abiv2.bank23",
102 (const char *)"org.gnu.csky.abiv2.bank24",
103 (const char *)"org.gnu.csky.abiv2.bank25",
104 (const char *)"org.gnu.csky.abiv2.bank26",
105 (const char *)"org.gnu.csky.abiv2.bank27",
106 (const char *)"org.gnu.csky.abiv2.bank28",
107 (const char *)"org.gnu.csky.abiv2.bank29",
108 (const char *)"org.gnu.csky.abiv2.bank30",
109 (const char *)"org.gnu.csky.abiv2.bank31"
110 };
111
112 struct csky_supported_tdesc_register
113 {
114 char name[16];
115 int num;
116 };
117
118 static const struct csky_supported_tdesc_register csky_supported_gpr_regs[] = {
119 {"r0", 0},
120 {"r1", 1},
121 {"r2", 2},
122 {"r3", 3},
123 {"r4", 4},
124 {"r5", 5},
125 {"r6", 6},
126 {"r7", 7},
127 {"r8", 8},
128 {"r9", 9},
129 {"r10", 10},
130 {"r11", 11},
131 {"r12", 12},
132 {"r13", 13},
133 {"r14", 14},
134 {"r15", 15},
135 {"r16", 16},
136 {"r17", 17},
137 {"r18", 18},
138 {"r19", 19},
139 {"r20", 20},
140 {"r21", 21},
141 {"r22", 22},
142 {"r23", 23},
143 {"r24", 24},
144 {"r25", 25},
145 {"r26", 26},
146 {"r27", 27},
147 {"r28", 28},
148 {"r28", 28},
149 {"r29", 29},
150 {"r30", 30},
151 {"r31", 31},
152 {"hi", CSKY_HI_REGNUM},
153 {"lo", CSKY_LO_REGNUM},
154 {"pc", CSKY_PC_REGNUM}
155 };
156
157 static const struct csky_supported_tdesc_register csky_supported_fpu_regs[] = {
158 /* fr0~fr15. */
159 {"fr0", CSKY_FR0_REGNUM + 0},
160 {"fr1", CSKY_FR0_REGNUM + 1},
161 {"fr2", CSKY_FR0_REGNUM + 2},
162 {"fr3", CSKY_FR0_REGNUM + 3},
163 {"fr4", CSKY_FR0_REGNUM + 4},
164 {"fr5", CSKY_FR0_REGNUM + 5},
165 {"fr6", CSKY_FR0_REGNUM + 6},
166 {"fr7", CSKY_FR0_REGNUM + 7},
167 {"fr8", CSKY_FR0_REGNUM + 8},
168 {"fr9", CSKY_FR0_REGNUM + 9},
169 {"fr10", CSKY_FR0_REGNUM + 10},
170 {"fr11", CSKY_FR0_REGNUM + 11},
171 {"fr12", CSKY_FR0_REGNUM + 12},
172 {"fr13", CSKY_FR0_REGNUM + 13},
173 {"fr14", CSKY_FR0_REGNUM + 14},
174 {"fr15", CSKY_FR0_REGNUM + 15},
175 /* fr16~fr31. */
176 {"fr16", CSKY_FR16_REGNUM + 0},
177 {"fr17", CSKY_FR16_REGNUM + 1},
178 {"fr18", CSKY_FR16_REGNUM + 2},
179 {"fr19", CSKY_FR16_REGNUM + 3},
180 {"fr20", CSKY_FR16_REGNUM + 4},
181 {"fr21", CSKY_FR16_REGNUM + 5},
182 {"fr22", CSKY_FR16_REGNUM + 6},
183 {"fr23", CSKY_FR16_REGNUM + 7},
184 {"fr24", CSKY_FR16_REGNUM + 8},
185 {"fr25", CSKY_FR16_REGNUM + 9},
186 {"fr26", CSKY_FR16_REGNUM + 10},
187 {"fr27", CSKY_FR16_REGNUM + 11},
188 {"fr28", CSKY_FR16_REGNUM + 12},
189 {"fr29", CSKY_FR16_REGNUM + 13},
190 {"fr30", CSKY_FR16_REGNUM + 14},
191 {"fr31", CSKY_FR16_REGNUM + 15},
192 /* vr0~vr15. */
193 {"vr0", CSKY_VR0_REGNUM + 0},
194 {"vr1", CSKY_VR0_REGNUM + 1},
195 {"vr2", CSKY_VR0_REGNUM + 2},
196 {"vr3", CSKY_VR0_REGNUM + 3},
197 {"vr4", CSKY_VR0_REGNUM + 4},
198 {"vr5", CSKY_VR0_REGNUM + 5},
199 {"vr6", CSKY_VR0_REGNUM + 6},
200 {"vr7", CSKY_VR0_REGNUM + 7},
201 {"vr8", CSKY_VR0_REGNUM + 8},
202 {"vr9", CSKY_VR0_REGNUM + 9},
203 {"vr10", CSKY_VR0_REGNUM + 10},
204 {"vr11", CSKY_VR0_REGNUM + 11},
205 {"vr12", CSKY_VR0_REGNUM + 12},
206 {"vr13", CSKY_VR0_REGNUM + 13},
207 {"vr14", CSKY_VR0_REGNUM + 14},
208 {"vr15", CSKY_VR0_REGNUM + 15},
209 /* fpu control registers. */
210 {"fcr", CSKY_FCR_REGNUM + 0},
211 {"fid", CSKY_FCR_REGNUM + 1},
212 {"fesr", CSKY_FCR_REGNUM + 2},
213 };
214
215 static const struct csky_supported_tdesc_register csky_supported_ar_regs[] = {
216 {"ar0", CSKY_AR0_REGNUM + 0},
217 {"ar1", CSKY_AR0_REGNUM + 1},
218 {"ar2", CSKY_AR0_REGNUM + 2},
219 {"ar3", CSKY_AR0_REGNUM + 3},
220 {"ar4", CSKY_AR0_REGNUM + 4},
221 {"ar5", CSKY_AR0_REGNUM + 5},
222 {"ar6", CSKY_AR0_REGNUM + 6},
223 {"ar7", CSKY_AR0_REGNUM + 7},
224 {"ar8", CSKY_AR0_REGNUM + 8},
225 {"ar9", CSKY_AR0_REGNUM + 9},
226 {"ar10", CSKY_AR0_REGNUM + 10},
227 {"ar11", CSKY_AR0_REGNUM + 11},
228 {"ar12", CSKY_AR0_REGNUM + 12},
229 {"ar13", CSKY_AR0_REGNUM + 13},
230 {"ar14", CSKY_AR0_REGNUM + 14},
231 {"ar15", CSKY_AR0_REGNUM + 15},
232 };
233
234 static const struct csky_supported_tdesc_register csky_supported_bank0_regs[] = {
235 {"cr0", CSKY_CR0_REGNUM + 0},
236 {"cr1", CSKY_CR0_REGNUM + 1},
237 {"cr2", CSKY_CR0_REGNUM + 2},
238 {"cr3", CSKY_CR0_REGNUM + 3},
239 {"cr4", CSKY_CR0_REGNUM + 4},
240 {"cr5", CSKY_CR0_REGNUM + 5},
241 {"cr6", CSKY_CR0_REGNUM + 6},
242 {"cr7", CSKY_CR0_REGNUM + 7},
243 {"cr8", CSKY_CR0_REGNUM + 8},
244 {"cr9", CSKY_CR0_REGNUM + 9},
245 {"cr10", CSKY_CR0_REGNUM + 10},
246 {"cr11", CSKY_CR0_REGNUM + 11},
247 {"cr12", CSKY_CR0_REGNUM + 12},
248 {"cr13", CSKY_CR0_REGNUM + 13},
249 {"cr14", CSKY_CR0_REGNUM + 14},
250 {"cr15", CSKY_CR0_REGNUM + 15},
251 {"cr16", CSKY_CR0_REGNUM + 16},
252 {"cr17", CSKY_CR0_REGNUM + 17},
253 {"cr18", CSKY_CR0_REGNUM + 18},
254 {"cr19", CSKY_CR0_REGNUM + 19},
255 {"cr20", CSKY_CR0_REGNUM + 20},
256 {"cr21", CSKY_CR0_REGNUM + 21},
257 {"cr22", CSKY_CR0_REGNUM + 22},
258 {"cr23", CSKY_CR0_REGNUM + 23},
259 {"cr24", CSKY_CR0_REGNUM + 24},
260 {"cr25", CSKY_CR0_REGNUM + 25},
261 {"cr26", CSKY_CR0_REGNUM + 26},
262 {"cr27", CSKY_CR0_REGNUM + 27},
263 {"cr28", CSKY_CR0_REGNUM + 28},
264 {"cr29", CSKY_CR0_REGNUM + 29},
265 {"cr30", CSKY_CR0_REGNUM + 30},
266 {"cr31", CSKY_CR0_REGNUM + 31}
267 };
268
269 static const struct csky_supported_tdesc_register csky_supported_mmu_regs[] = {
270 {"mcr0", 128},
271 {"mcr2", 129},
272 {"mcr3", 130},
273 {"mcr4", 131},
274 {"mcr6", 132},
275 {"mcr8", 133},
276 {"mcr29", 134},
277 {"mcr30", 135},
278 {"mcr31", 136}
279 };
280
281 static const struct csky_supported_tdesc_register csky_supported_bank15_regs[] = {
282 {"cp15cp1", 253},
283 {"cp15cp5", 254},
284 {"cp15cp7", 255},
285 {"cp15cp9", 256},
286 {"cp15cp10", 257},
287 {"cp15cp11", 258},
288 {"cp15cp12", 259},
289 {"cp15cp13", 260},
290 {"cp15cp14", 261},
291 {"cp15cp15", 262},
292 {"cp15cp16", 263},
293 {"cp15cp17", 264},
294 {"cp15cp18", 265},
295 {"cp15cp19", 266},
296 {"cp15cp20", 267},
297 {"cp15cp21", 268},
298 {"cp15cp22", 269},
299 {"cp15cp23", 270},
300 {"cp15cp24", 271},
301 {"cp15cp25", 272},
302 {"cp15cp26", 273},
303 {"cp15cp27", 274},
304 {"cp15cp28", 275},
305 };
306
307 static const struct csky_supported_tdesc_register csky_supported_alias_regs[] = {
308 /* Alias register names for Bank0. */
309 {"psr", CSKY_CR0_REGNUM + 0},
310 {"vbr", CSKY_CR0_REGNUM + 1},
311 {"epsr", CSKY_CR0_REGNUM + 2},
312 {"fpsr", CSKY_CR0_REGNUM + 3},
313 {"epc", CSKY_CR0_REGNUM + 4},
314 {"fpc", CSKY_CR0_REGNUM + 5},
315 {"ss0", CSKY_CR0_REGNUM + 6},
316 {"ss1", CSKY_CR0_REGNUM + 7},
317 {"ss2", CSKY_CR0_REGNUM + 8},
318 {"ss3", CSKY_CR0_REGNUM + 9},
319 {"ss4", CSKY_CR0_REGNUM + 10},
320 {"gcr", CSKY_CR0_REGNUM + 11},
321 {"gsr", CSKY_CR0_REGNUM + 12},
322 {"cpuid", CSKY_CR0_REGNUM + 13},
323 {"ccr", CSKY_CR0_REGNUM + 18},
324 {"capr", CSKY_CR0_REGNUM + 19},
325 {"pacr", CSKY_CR0_REGNUM + 20},
326 {"prsr", CSKY_CR0_REGNUM + 21},
327 {"chr", CSKY_CR0_REGNUM + 31},
328 /* Alias register names for MMU. */
329 {"mir", 128},
330 {"mel0", 129},
331 {"mel1", 130},
332 {"meh", 131},
333 {"mpr", 132},
334 {"mcir", 133},
335 {"mpgd", 134},
336 {"msa0", 135},
337 {"msa1", 136},
338 /* Alias register names for Bank1. */
339 {"ebr", 190},
340 {"errlc", 195},
341 {"erraddr", 196},
342 {"errsts", 197},
343 {"errinj", 198},
344 {"usp", 203},
345 {"int_sp", 204},
346 {"itcmcr", 211},
347 {"dtcmcr", 212},
348 {"cindex", 215},
349 {"cdata0", 216},
350 {"cdata1", 217},
351 {"cdata2", 218},
352 {"cins", 220},
353 /* Alias register names for Bank3. */
354 {"sepsr", 221},
355 {"t_wssr", 221},
356 {"sevbr", 222},
357 {"t_wrcr", 222},
358 {"seepsr", 223},
359 {"seepc", 225},
360 {"nsssp", 227},
361 {"t_usp", 228},
362 {"dcr", 229},
363 {"t_pcr", 230},
364 };
365
366 /* Functions declaration. */
367
368 static const char *
369 csky_pseudo_register_name (struct gdbarch *gdbarch, int regno);
370
371 /* Get csky supported registers's count for tdesc xml. */
372
373 static int
374 csky_get_supported_tdesc_registers_count()
375 {
376 int count = 0;
377 count += ARRAY_SIZE (csky_supported_gpr_regs);
378 count += ARRAY_SIZE (csky_supported_fpu_regs);
379 count += ARRAY_SIZE (csky_supported_ar_regs);
380 count += ARRAY_SIZE (csky_supported_bank0_regs);
381 count += ARRAY_SIZE (csky_supported_mmu_regs);
382 count += ARRAY_SIZE (csky_supported_bank15_regs);
383 count += ARRAY_SIZE (csky_supported_alias_regs);
384 /* Bank1~Bank14, Bank16~Bank31. */
385 count += 32 * (14 + 16);
386 return count;
387 }
388
389 /* Return a supported register according to index. */
390
391 static const struct csky_supported_tdesc_register *
392 csky_get_supported_register_by_index (int index)
393 {
394 static struct csky_supported_tdesc_register tdesc_reg;
395 int count = 0;
396 int multi, remain;
397 int count_gpr = ARRAY_SIZE (csky_supported_gpr_regs);
398 int count_fpu = ARRAY_SIZE (csky_supported_fpu_regs);
399 int count_ar = ARRAY_SIZE (csky_supported_ar_regs);
400 int count_bank0 = ARRAY_SIZE (csky_supported_bank0_regs);
401 int count_mmu = ARRAY_SIZE (csky_supported_mmu_regs);
402 int count_bank15 = ARRAY_SIZE (csky_supported_bank15_regs);
403 int count_alias = ARRAY_SIZE (csky_supported_alias_regs);
404
405 count = count_gpr;
406 if (index < count)
407 return &csky_supported_gpr_regs[index];
408 if (index < (count + count_fpu))
409 return &csky_supported_fpu_regs[index - count];
410 count += count_fpu;
411 if (index < (count + count_ar))
412 return &csky_supported_ar_regs[index - count];
413 count += count_ar;
414 if (index < (count + count_bank0))
415 return &csky_supported_bank0_regs[index - count];
416 count += count_bank0;
417 if (index < (count + count_mmu))
418 return &csky_supported_mmu_regs[index - count];
419 count += count_mmu;
420 if (index < (count + count_bank15))
421 return &csky_supported_bank15_regs[index - count];
422 count += count_bank15;
423 if (index < (count + count_alias))
424 return &csky_supported_alias_regs[index - count];
425 count += count_alias;
426 index -= count;
427 multi = index / 32;
428 remain = index % 32;
429 switch (multi)
430 {
431 case 0: /* Bank1. */
432 {
433 sprintf (tdesc_reg.name, "cp1cr%d", remain);
434 tdesc_reg.num = 189 + remain;
435 }
436 break;
437 case 1: /* Bank2. */
438 {
439 sprintf (tdesc_reg.name, "cp2cr%d", remain);
440 tdesc_reg.num = 276 + remain;
441 }
442 break;
443 case 2: /* Bank3. */
444 {
445 sprintf (tdesc_reg.name, "cp3cr%d", remain);
446 tdesc_reg.num = 221 + remain;
447 }
448 break;
449 case 3: /* Bank4. */
450 case 4: /* Bank5. */
451 case 5: /* Bank6. */
452 case 6: /* Bank7. */
453 case 7: /* Bank8. */
454 case 8: /* Bank9. */
455 case 9: /* Bank10. */
456 case 10: /* Bank11. */
457 case 11: /* Bank12. */
458 case 12: /* Bank13. */
459 case 13: /* Bank14. */
460 {
461 /* Regitsers in Bank4~14 have continuous regno with start 308. */
462 sprintf (tdesc_reg.name, "cp%dcr%d", (multi + 1), remain);
463 tdesc_reg.num = 308 + ((multi - 3) * 32) + remain;
464 }
465 break;
466 case 14: /* Bank16. */
467 case 15: /* Bank17. */
468 case 16: /* Bank18. */
469 case 17: /* Bank19. */
470 case 18: /* Bank20. */
471 case 19: /* Bank21. */
472 case 20: /* Bank22. */
473 case 21: /* Bank23. */
474 case 22: /* Bank24. */
475 case 23: /* Bank25. */
476 case 24: /* Bank26. */
477 case 25: /* Bank27. */
478 case 26: /* Bank28. */
479 case 27: /* Bank29. */
480 case 28: /* Bank30. */
481 case 29: /* Bank31. */
482 {
483 /* Regitsers in Bank16~31 have continuous regno with start 660. */
484 sprintf (tdesc_reg.name, "cp%dcr%d", (multi + 2), remain);
485 tdesc_reg.num = 660 + ((multi - 14) * 32) + remain;
486 }
487 break;
488 default:
489 return NULL;
490 }
491 return &tdesc_reg;
492 }
493
494 /* Convenience function to print debug messages in prologue analysis. */
495
496 static void
497 print_savedreg_msg (int regno, int offsets[], bool print_continuing)
498 {
499 gdb_printf (gdb_stdlog, "csky: r%d saved at offset 0x%x\n",
500 regno, offsets[regno]);
501 if (print_continuing)
502 gdb_printf (gdb_stdlog, "csky: continuing\n");
503 }
504
505 /* Check whether the instruction at ADDR is 16-bit or not. */
506
507 static int
508 csky_pc_is_csky16 (struct gdbarch *gdbarch, CORE_ADDR addr)
509 {
510 gdb_byte target_mem[2];
511 int status;
512 unsigned int insn;
513 int ret = 1;
514 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
515
516 status = target_read_memory (addr, target_mem, 2);
517 /* Assume a 16-bit instruction if we can't read memory. */
518 if (status)
519 return 1;
520
521 /* Get instruction from memory. */
522 insn = extract_unsigned_integer (target_mem, 2, byte_order);
523 if ((insn & CSKY_32_INSN_MASK) == CSKY_32_INSN_MASK)
524 ret = 0;
525 else if (insn == CSKY_BKPT_INSN)
526 {
527 /* Check for 32-bit bkpt instruction which is all 0. */
528 status = target_read_memory (addr + 2, target_mem, 2);
529 if (status)
530 return 1;
531
532 insn = extract_unsigned_integer (target_mem, 2, byte_order);
533 if (insn == CSKY_BKPT_INSN)
534 ret = 0;
535 }
536 return ret;
537 }
538
539 /* Get one instruction at ADDR and store it in INSN. Return 2 for
540 a 16-bit instruction or 4 for a 32-bit instruction. */
541
542 static int
543 csky_get_insn (struct gdbarch *gdbarch, CORE_ADDR addr, unsigned int *insn)
544 {
545 gdb_byte target_mem[2];
546 unsigned int insn_type;
547 int status;
548 int insn_len = 2;
549 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
550
551 status = target_read_memory (addr, target_mem, 2);
552 if (status)
553 memory_error (TARGET_XFER_E_IO, addr);
554
555 insn_type = extract_unsigned_integer (target_mem, 2, byte_order);
556 if (CSKY_32_INSN_MASK == (insn_type & CSKY_32_INSN_MASK))
557 {
558 status = target_read_memory (addr + 2, target_mem, 2);
559 if (status)
560 memory_error (TARGET_XFER_E_IO, addr);
561 insn_type = ((insn_type << 16)
562 | extract_unsigned_integer (target_mem, 2, byte_order));
563 insn_len = 4;
564 }
565 *insn = insn_type;
566 return insn_len;
567 }
568
569 /* Implement the read_pc gdbarch method. */
570
571 static CORE_ADDR
572 csky_read_pc (readable_regcache *regcache)
573 {
574 ULONGEST pc;
575 regcache->cooked_read (CSKY_PC_REGNUM, &pc);
576 return pc;
577 }
578
579 /* Implement the write_pc gdbarch method. */
580
581 static void
582 csky_write_pc (regcache *regcache, CORE_ADDR val)
583 {
584 regcache_cooked_write_unsigned (regcache, CSKY_PC_REGNUM, val);
585 }
586
587 /* C-Sky ABI register names. */
588
589 static const char * const csky_register_names[] =
590 {
591 /* General registers 0 - 31. */
592 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
593 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
594 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
595 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
596
597 /* DSP hilo registers 36 and 37. */
598 "", "", "", "", "hi", "lo", "", "",
599
600 /* FPU/VPU general registers 40 - 71. */
601 "fr0", "fr1", "fr2", "fr3", "fr4", "fr5", "fr6", "fr7",
602 "fr8", "fr9", "fr10", "fr11", "fr12", "fr13", "fr14", "fr15",
603 "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
604 "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
605
606 /* Program counter 72. */
607 "pc",
608
609 /* Optional registers (ar) 73 - 88. */
610 "ar0", "ar1", "ar2", "ar3", "ar4", "ar5", "ar6", "ar7",
611 "ar8", "ar9", "ar10", "ar11", "ar12", "ar13", "ar14", "ar15",
612
613 /* Control registers (cr) 89 - 119. */
614 "psr", "vbr", "epsr", "fpsr", "epc", "fpc", "ss0", "ss1",
615 "ss2", "ss3", "ss4", "gcr", "gsr", "cr13", "cr14", "cr15",
616 "cr16", "cr17", "cr18", "cr19", "cr20", "cr21", "cr22", "cr23",
617 "cr24", "cr25", "cr26", "cr27", "cr28", "cr29", "cr30", "cr31",
618
619 /* FPU/VPU control registers 121 ~ 123. */
620 /* User sp 127. */
621 "fid", "fcr", "fesr", "", "", "", "usp",
622
623 /* MMU control registers: 128 - 136. */
624 "mcr0", "mcr2", "mcr3", "mcr4", "mcr6", "mcr8", "mcr29", "mcr30",
625 "mcr31", "", "", "",
626
627 /* Profiling control registers 140 - 143. */
628 /* Profiling software general registers 144 - 157. */
629 "profcr0", "profcr1", "profcr2", "profcr3", "profsgr0", "profsgr1",
630 "profsgr2", "profsgr3", "profsgr4", "profsgr5", "profsgr6", "profsgr7",
631 "profsgr8", "profsgr9", "profsgr10","profsgr11","profsgr12", "profsgr13",
632 "", "",
633
634 /* Profiling architecture general registers 160 - 174. */
635 "profagr0", "profagr1", "profagr2", "profagr3", "profagr4", "profagr5",
636 "profagr6", "profagr7", "profagr8", "profagr9", "profagr10","profagr11",
637 "profagr12","profagr13","profagr14", "",
638
639 /* Profiling extension general registers 176 - 188. */
640 "profxgr0", "profxgr1", "profxgr2", "profxgr3", "profxgr4", "profxgr5",
641 "profxgr6", "profxgr7", "profxgr8", "profxgr9", "profxgr10","profxgr11",
642 "profxgr12",
643
644 /* Control registers in bank1. */
645 "", "", "", "", "", "", "", "",
646 "", "", "", "", "", "", "", "",
647 "cp1cr16", "cp1cr17", "cp1cr18", "cp1cr19", "cp1cr20", "", "", "",
648 "", "", "", "", "", "", "", "",
649
650 /* Control registers in bank3 (ICE). */
651 "sepsr", "sevbr", "seepsr", "", "seepc", "", "nsssp", "seusp",
652 "sedcr", "", "", "", "", "", "", "",
653 "", "", "", "", "", "", "", "",
654 "", "", "", "", "", "", "", ""
655 };
656
657 /* Implement the register_name gdbarch method. */
658
659 static const char *
660 csky_register_name (struct gdbarch *gdbarch, int reg_nr)
661 {
662 if (reg_nr >= gdbarch_num_regs (gdbarch))
663 return csky_pseudo_register_name (gdbarch, reg_nr);
664
665 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
666 return tdesc_register_name (gdbarch, reg_nr);
667
668 return csky_register_names[reg_nr];
669 }
670
671 /* Construct vector type for vrx registers. */
672
673 static struct type *
674 csky_vector_type (struct gdbarch *gdbarch)
675 {
676 const struct builtin_type *bt = builtin_type (gdbarch);
677
678 struct type *t;
679
680 t = arch_composite_type (gdbarch, "__gdb_builtin_type_vec128i",
681 TYPE_CODE_UNION);
682
683 append_composite_type_field (t, "u32",
684 init_vector_type (bt->builtin_int32, 4));
685 append_composite_type_field (t, "u16",
686 init_vector_type (bt->builtin_int16, 8));
687 append_composite_type_field (t, "u8",
688 init_vector_type (bt->builtin_int8, 16));
689
690 t->set_is_vector (true);
691 t->set_name ("builtin_type_vec128i");
692
693 return t;
694 }
695
696 /* Return the GDB type object for the "standard" data type
697 of data in register N. */
698
699 static struct type *
700 csky_register_type (struct gdbarch *gdbarch, int reg_nr)
701 {
702 int num_regs = gdbarch_num_regs (gdbarch);
703 csky_gdbarch_tdep *tdep
704 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
705
706 if (tdep->fv_pseudo_registers_count)
707 {
708 if ((reg_nr >= num_regs)
709 && (reg_nr < (num_regs + tdep->fv_pseudo_registers_count)))
710 return builtin_type (gdbarch)->builtin_int32;
711 }
712
713 /* Vector register has 128 bits, and only in ck810. Just return
714 csky_vector_type(), not check tdesc_has_registers(), is in case
715 of some GDB stub does not describe type for Vector registers
716 in the target-description-xml. */
717 if ((reg_nr >= CSKY_VR0_REGNUM) && (reg_nr <= CSKY_VR0_REGNUM + 15))
718 return csky_vector_type (gdbarch);
719
720 /* If type has been described in tdesc-xml, use it. */
721 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
722 {
723 struct type *tdesc_t = tdesc_register_type (gdbarch, reg_nr);
724 if (tdesc_t)
725 return tdesc_t;
726 }
727
728 /* PC, EPC, FPC is a text pointer. */
729 if ((reg_nr == CSKY_PC_REGNUM) || (reg_nr == CSKY_EPC_REGNUM)
730 || (reg_nr == CSKY_FPC_REGNUM))
731 return builtin_type (gdbarch)->builtin_func_ptr;
732
733 /* VBR is a data pointer. */
734 if (reg_nr == CSKY_VBR_REGNUM)
735 return builtin_type (gdbarch)->builtin_data_ptr;
736
737 /* Float register has 64 bits, and only in ck810. */
738 if ((reg_nr >=CSKY_FR0_REGNUM) && (reg_nr <= CSKY_FR0_REGNUM + 15))
739 {
740 type_allocator alloc (gdbarch);
741 return init_float_type (alloc, 64, "builtin_type_csky_ext",
742 floatformats_ieee_double);
743 }
744
745 /* Profiling general register has 48 bits, we use 64bit. */
746 if ((reg_nr >= CSKY_PROFGR_REGNUM) && (reg_nr <= CSKY_PROFGR_REGNUM + 44))
747 return builtin_type (gdbarch)->builtin_uint64;
748
749 if (reg_nr == CSKY_SP_REGNUM)
750 return builtin_type (gdbarch)->builtin_data_ptr;
751
752 /* Others are 32 bits. */
753 return builtin_type (gdbarch)->builtin_int32;
754 }
755
756 /* Data structure to marshall items in a dummy stack frame when
757 calling a function in the inferior. */
758
759 struct csky_stack_item
760 {
761 csky_stack_item (int len_, const gdb_byte *data_)
762 : len (len_), data (data_)
763 {}
764
765 int len;
766 const gdb_byte *data;
767 };
768
769 /* Implement the push_dummy_call gdbarch method. */
770
771 static CORE_ADDR
772 csky_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
773 struct regcache *regcache, CORE_ADDR bp_addr,
774 int nargs, struct value **args, CORE_ADDR sp,
775 function_call_return_method return_method,
776 CORE_ADDR struct_addr)
777 {
778 int argnum;
779 int argreg = CSKY_ABI_A0_REGNUM;
780 int last_arg_regnum = CSKY_ABI_LAST_ARG_REGNUM;
781 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
782 std::vector<csky_stack_item> stack_items;
783
784 /* Set the return address. For CSKY, the return breakpoint is
785 always at BP_ADDR. */
786 regcache_cooked_write_unsigned (regcache, CSKY_LR_REGNUM, bp_addr);
787
788 /* The struct_return pointer occupies the first parameter
789 passing register. */
790 if (return_method == return_method_struct)
791 {
792 if (csky_debug)
793 {
794 gdb_printf (gdb_stdlog,
795 "csky: struct return in %s = %s\n",
796 gdbarch_register_name (gdbarch, argreg),
797 paddress (gdbarch, struct_addr));
798 }
799 regcache_cooked_write_unsigned (regcache, argreg, struct_addr);
800 argreg++;
801 }
802
803 /* Put parameters into argument registers in REGCACHE.
804 In ABI argument registers are r0 through r3. */
805 for (argnum = 0; argnum < nargs; argnum++)
806 {
807 int len;
808 struct type *arg_type;
809 const gdb_byte *val;
810
811 arg_type = check_typedef (args[argnum]->type ());
812 len = arg_type->length ();
813 val = args[argnum]->contents ().data ();
814
815 /* Copy the argument to argument registers or the dummy stack.
816 Large arguments are split between registers and stack.
817
818 If len < 4, there is no need to worry about endianness since
819 the arguments will always be stored in the low address. */
820 if (len < 4)
821 {
822 CORE_ADDR regval
823 = extract_unsigned_integer (val, len, byte_order);
824 regcache_cooked_write_unsigned (regcache, argreg, regval);
825 argreg++;
826 }
827 else
828 {
829 while (len > 0)
830 {
831 int partial_len = len < 4 ? len : 4;
832 if (argreg <= last_arg_regnum)
833 {
834 /* The argument is passed in an argument register. */
835 CORE_ADDR regval
836 = extract_unsigned_integer (val, partial_len,
837 byte_order);
838 if (byte_order == BFD_ENDIAN_BIG)
839 regval <<= (4 - partial_len) * 8;
840
841 /* Put regval into register in REGCACHE. */
842 regcache_cooked_write_unsigned (regcache, argreg,
843 regval);
844 argreg++;
845 }
846 else
847 {
848 /* The argument should be pushed onto the dummy stack. */
849 stack_items.emplace_back (4, val);
850 }
851 len -= partial_len;
852 val += partial_len;
853 }
854 }
855 }
856
857 /* Transfer the dummy stack frame to the target. */
858 std::vector<csky_stack_item>::reverse_iterator iter;
859 for (iter = stack_items.rbegin (); iter != stack_items.rend (); ++iter)
860 {
861 sp -= iter->len;
862 write_memory (sp, iter->data, iter->len);
863 }
864
865 /* Finally, update the SP register. */
866 regcache_cooked_write_unsigned (regcache, CSKY_SP_REGNUM, sp);
867 return sp;
868 }
869
870 /* Implement the return_value gdbarch method. */
871
872 static enum return_value_convention
873 csky_return_value (struct gdbarch *gdbarch, struct value *function,
874 struct type *valtype, struct regcache *regcache,
875 gdb_byte *readbuf, const gdb_byte *writebuf)
876 {
877 CORE_ADDR regval;
878 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
879 int len = valtype->length ();
880 unsigned int ret_regnum = CSKY_RET_REGNUM;
881
882 /* Csky abi specifies that return values larger than 8 bytes
883 are put on the stack. */
884 if (len > 8)
885 return RETURN_VALUE_STRUCT_CONVENTION;
886 else
887 {
888 if (readbuf != NULL)
889 {
890 ULONGEST tmp;
891 /* By using store_unsigned_integer we avoid having to do
892 anything special for small big-endian values. */
893 regcache->cooked_read (ret_regnum, &tmp);
894 store_unsigned_integer (readbuf, (len > 4 ? 4 : len),
895 byte_order, tmp);
896 if (len > 4)
897 {
898 regcache->cooked_read (ret_regnum + 1, &tmp);
899 store_unsigned_integer (readbuf + 4, 4, byte_order, tmp);
900 }
901 }
902 if (writebuf != NULL)
903 {
904 regval = extract_unsigned_integer (writebuf, len > 4 ? 4 : len,
905 byte_order);
906 regcache_cooked_write_unsigned (regcache, ret_regnum, regval);
907 if (len > 4)
908 {
909 regval = extract_unsigned_integer ((gdb_byte *) writebuf + 4,
910 4, byte_order);
911 regcache_cooked_write_unsigned (regcache, ret_regnum + 1,
912 regval);
913 }
914
915 }
916 return RETURN_VALUE_REGISTER_CONVENTION;
917 }
918 }
919
920 /* Implement the frame_align gdbarch method.
921
922 Adjust the address downward (direction of stack growth) so that it
923 is correctly aligned for a new stack frame. */
924
925 static CORE_ADDR
926 csky_frame_align (struct gdbarch *gdbarch, CORE_ADDR addr)
927 {
928 return align_down (addr, 4);
929 }
930
931 /* Unwind cache used for gdbarch fallback unwinder. */
932
933 struct csky_unwind_cache
934 {
935 /* The stack pointer at the time this frame was created; i.e. the
936 caller's stack pointer when this function was called. It is used
937 to identify this frame. */
938 CORE_ADDR prev_sp;
939
940 /* The frame base for this frame is just prev_sp - frame size.
941 FRAMESIZE is the distance from the frame pointer to the
942 initial stack pointer. */
943 int framesize;
944
945 /* The register used to hold the frame pointer for this frame. */
946 int framereg;
947
948 /* Saved register offsets. */
949 trad_frame_saved_reg *saved_regs;
950 };
951
952 /* Do prologue analysis, returning the PC of the first instruction
953 after the function prologue. */
954
955 static CORE_ADDR
956 csky_analyze_prologue (struct gdbarch *gdbarch,
957 CORE_ADDR start_pc,
958 CORE_ADDR limit_pc,
959 CORE_ADDR end_pc,
960 const frame_info_ptr &this_frame,
961 struct csky_unwind_cache *this_cache,
962 lr_type_t lr_type)
963 {
964 CORE_ADDR addr;
965 unsigned int insn, rn;
966 int framesize = 0;
967 int stacksize = 0;
968 int register_offsets[CSKY_NUM_GREGS_SAVED_GREGS];
969 int insn_len;
970 /* For adjusting fp. */
971 int is_fp_saved = 0;
972 int adjust_fp = 0;
973
974 /* REGISTER_OFFSETS will contain offsets from the top of the frame
975 (NOT the frame pointer) for the various saved registers, or -1
976 if the register is not saved. */
977 for (rn = 0; rn < CSKY_NUM_GREGS_SAVED_GREGS; rn++)
978 register_offsets[rn] = -1;
979
980 /* Analyze the prologue. Things we determine from analyzing the
981 prologue include the size of the frame and which registers are
982 saved (and where). */
983 if (csky_debug)
984 {
985 gdb_printf (gdb_stdlog,
986 "csky: Scanning prologue: start_pc = 0x%x,"
987 "limit_pc = 0x%x\n", (unsigned int) start_pc,
988 (unsigned int) limit_pc);
989 }
990
991 /* Default to 16 bit instruction. */
992 insn_len = 2;
993 stacksize = 0;
994 for (addr = start_pc; addr < limit_pc; addr += insn_len)
995 {
996 /* Get next insn. */
997 insn_len = csky_get_insn (gdbarch, addr, &insn);
998
999 /* Check if 32 bit. */
1000 if (insn_len == 4)
1001 {
1002 /* subi32 sp,sp oimm12. */
1003 if (CSKY_32_IS_SUBI0 (insn))
1004 {
1005 /* Got oimm12. */
1006 int offset = CSKY_32_SUBI_IMM (insn);
1007 if (csky_debug)
1008 {
1009 gdb_printf (gdb_stdlog,
1010 "csky: got subi sp,%d; continuing\n",
1011 offset);
1012 }
1013 stacksize += offset;
1014 continue;
1015 }
1016 /* stm32 ry-rz,(sp). */
1017 else if (CSKY_32_IS_STMx0 (insn))
1018 {
1019 /* Spill register(s). */
1020 int start_register;
1021 int reg_count;
1022 int offset;
1023
1024 /* BIG WARNING! The CKCore ABI does not restrict functions
1025 to taking only one stack allocation. Therefore, when
1026 we save a register, we record the offset of where it was
1027 saved relative to the current stacksize. This will
1028 then give an offset from the SP upon entry to our
1029 function. Remember, stacksize is NOT constant until
1030 we're done scanning the prologue. */
1031 start_register = CSKY_32_STM_VAL_REGNUM (insn);
1032 reg_count = CSKY_32_STM_SIZE (insn);
1033 if (csky_debug)
1034 {
1035 gdb_printf (gdb_stdlog,
1036 "csky: got stm r%d-r%d,(sp)\n",
1037 start_register,
1038 start_register + reg_count);
1039 }
1040
1041 for (rn = start_register, offset = 0;
1042 rn <= start_register + reg_count;
1043 rn++, offset += 4)
1044 {
1045 register_offsets[rn] = stacksize - offset;
1046 if (csky_debug)
1047 {
1048 gdb_printf (gdb_stdlog,
1049 "csky: r%d saved at 0x%x"
1050 " (offset %d)\n",
1051 rn, register_offsets[rn],
1052 offset);
1053 }
1054 }
1055 if (csky_debug)
1056 gdb_printf (gdb_stdlog, "csky: continuing\n");
1057 continue;
1058 }
1059 /* stw ry,(sp,disp). */
1060 else if (CSKY_32_IS_STWx0 (insn))
1061 {
1062 /* Spill register: see note for IS_STM above. */
1063 int disp;
1064
1065 rn = CSKY_32_ST_VAL_REGNUM (insn);
1066 disp = CSKY_32_ST_OFFSET (insn);
1067 register_offsets[rn] = stacksize - disp;
1068 if (csky_debug)
1069 print_savedreg_msg (rn, register_offsets, true);
1070 continue;
1071 }
1072 else if (CSKY_32_IS_MOV_FP_SP (insn))
1073 {
1074 /* SP is saved to FP reg, means code afer prologue may
1075 modify SP. */
1076 is_fp_saved = 1;
1077 adjust_fp = stacksize;
1078 continue;
1079 }
1080 else if (CSKY_32_IS_MFCR_EPSR (insn))
1081 {
1082 unsigned int insn2;
1083 addr += 4;
1084 int mfcr_regnum = insn & 0x1f;
1085 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1086 if (insn_len == 2)
1087 {
1088 int stw_regnum = (insn2 >> 5) & 0x7;
1089 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1090 {
1091 int offset;
1092
1093 /* CSKY_EPSR_REGNUM. */
1094 rn = CSKY_NUM_GREGS;
1095 offset = CSKY_16_STWx0_OFFSET (insn2);
1096 register_offsets[rn] = stacksize - offset;
1097 if (csky_debug)
1098 print_savedreg_msg (rn, register_offsets, true);
1099 continue;
1100 }
1101 break;
1102 }
1103 else
1104 {
1105 /* INSN_LEN == 4. */
1106 int stw_regnum = (insn2 >> 21) & 0x1f;
1107 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1108 {
1109 int offset;
1110
1111 /* CSKY_EPSR_REGNUM. */
1112 rn = CSKY_NUM_GREGS;
1113 offset = CSKY_32_ST_OFFSET (insn2);
1114 register_offsets[rn] = framesize - offset;
1115 if (csky_debug)
1116 print_savedreg_msg (rn, register_offsets, true);
1117 continue;
1118 }
1119 break;
1120 }
1121 }
1122 else if (CSKY_32_IS_MFCR_FPSR (insn))
1123 {
1124 unsigned int insn2;
1125 addr += 4;
1126 int mfcr_regnum = insn & 0x1f;
1127 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1128 if (insn_len == 2)
1129 {
1130 int stw_regnum = (insn2 >> 5) & 0x7;
1131 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum
1132 == stw_regnum))
1133 {
1134 int offset;
1135
1136 /* CSKY_FPSR_REGNUM. */
1137 rn = CSKY_NUM_GREGS + 1;
1138 offset = CSKY_16_STWx0_OFFSET (insn2);
1139 register_offsets[rn] = stacksize - offset;
1140 if (csky_debug)
1141 print_savedreg_msg (rn, register_offsets, true);
1142 continue;
1143 }
1144 break;
1145 }
1146 else
1147 {
1148 /* INSN_LEN == 4. */
1149 int stw_regnum = (insn2 >> 21) & 0x1f;
1150 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1151 {
1152 int offset;
1153
1154 /* CSKY_FPSR_REGNUM. */
1155 rn = CSKY_NUM_GREGS + 1;
1156 offset = CSKY_32_ST_OFFSET (insn2);
1157 register_offsets[rn] = framesize - offset;
1158 if (csky_debug)
1159 print_savedreg_msg (rn, register_offsets, true);
1160 continue;
1161 }
1162 break;
1163 }
1164 }
1165 else if (CSKY_32_IS_MFCR_EPC (insn))
1166 {
1167 unsigned int insn2;
1168 addr += 4;
1169 int mfcr_regnum = insn & 0x1f;
1170 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1171 if (insn_len == 2)
1172 {
1173 int stw_regnum = (insn2 >> 5) & 0x7;
1174 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1175 {
1176 int offset;
1177
1178 /* CSKY_EPC_REGNUM. */
1179 rn = CSKY_NUM_GREGS + 2;
1180 offset = CSKY_16_STWx0_OFFSET (insn2);
1181 register_offsets[rn] = stacksize - offset;
1182 if (csky_debug)
1183 print_savedreg_msg (rn, register_offsets, true);
1184 continue;
1185 }
1186 break;
1187 }
1188 else
1189 {
1190 /* INSN_LEN == 4. */
1191 int stw_regnum = (insn2 >> 21) & 0x1f;
1192 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1193 {
1194 int offset;
1195
1196 /* CSKY_EPC_REGNUM. */
1197 rn = CSKY_NUM_GREGS + 2;
1198 offset = CSKY_32_ST_OFFSET (insn2);
1199 register_offsets[rn] = framesize - offset;
1200 if (csky_debug)
1201 print_savedreg_msg (rn, register_offsets, true);
1202 continue;
1203 }
1204 break;
1205 }
1206 }
1207 else if (CSKY_32_IS_MFCR_FPC (insn))
1208 {
1209 unsigned int insn2;
1210 addr += 4;
1211 int mfcr_regnum = insn & 0x1f;
1212 insn_len = csky_get_insn (gdbarch, addr, &insn2);
1213 if (insn_len == 2)
1214 {
1215 int stw_regnum = (insn2 >> 5) & 0x7;
1216 if (CSKY_16_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1217 {
1218 int offset;
1219
1220 /* CSKY_FPC_REGNUM. */
1221 rn = CSKY_NUM_GREGS + 3;
1222 offset = CSKY_16_STWx0_OFFSET (insn2);
1223 register_offsets[rn] = stacksize - offset;
1224 if (csky_debug)
1225 print_savedreg_msg (rn, register_offsets, true);
1226 continue;
1227 }
1228 break;
1229 }
1230 else
1231 {
1232 /* INSN_LEN == 4. */
1233 int stw_regnum = (insn2 >> 21) & 0x1f;
1234 if (CSKY_32_IS_STWx0 (insn2) && (mfcr_regnum == stw_regnum))
1235 {
1236 int offset;
1237
1238 /* CSKY_FPC_REGNUM. */
1239 rn = CSKY_NUM_GREGS + 3;
1240 offset = CSKY_32_ST_OFFSET (insn2);
1241 register_offsets[rn] = framesize - offset;
1242 if (csky_debug)
1243 print_savedreg_msg (rn, register_offsets, true);
1244 continue;
1245 }
1246 break;
1247 }
1248 }
1249 else if (CSKY_32_IS_PUSH (insn))
1250 {
1251 /* Push for 32_bit. */
1252 if (CSKY_32_IS_PUSH_R29 (insn))
1253 {
1254 stacksize += 4;
1255 register_offsets[29] = stacksize;
1256 if (csky_debug)
1257 print_savedreg_msg (29, register_offsets, false);
1258 }
1259 if (CSKY_32_PUSH_LIST2 (insn))
1260 {
1261 int num = CSKY_32_PUSH_LIST2 (insn);
1262 int tmp = 0;
1263 stacksize += num * 4;
1264 if (csky_debug)
1265 {
1266 gdb_printf (gdb_stdlog,
1267 "csky: push regs_array: r16-r%d\n",
1268 16 + num - 1);
1269 }
1270 for (rn = 16; rn <= 16 + num - 1; rn++)
1271 {
1272 register_offsets[rn] = stacksize - tmp;
1273 if (csky_debug)
1274 {
1275 gdb_printf (gdb_stdlog,
1276 "csky: r%d saved at 0x%x"
1277 " (offset %d)\n", rn,
1278 register_offsets[rn], tmp);
1279 }
1280 tmp += 4;
1281 }
1282 }
1283 if (CSKY_32_IS_PUSH_R15 (insn))
1284 {
1285 stacksize += 4;
1286 register_offsets[15] = stacksize;
1287 if (csky_debug)
1288 print_savedreg_msg (15, register_offsets, false);
1289 }
1290 if (CSKY_32_PUSH_LIST1 (insn))
1291 {
1292 int num = CSKY_32_PUSH_LIST1 (insn);
1293 int tmp = 0;
1294 stacksize += num * 4;
1295 if (csky_debug)
1296 {
1297 gdb_printf (gdb_stdlog,
1298 "csky: push regs_array: r4-r%d\n",
1299 4 + num - 1);
1300 }
1301 for (rn = 4; rn <= 4 + num - 1; rn++)
1302 {
1303 register_offsets[rn] = stacksize - tmp;
1304 if (csky_debug)
1305 {
1306 gdb_printf (gdb_stdlog,
1307 "csky: r%d saved at 0x%x"
1308 " (offset %d)\n", rn,
1309 register_offsets[rn], tmp);
1310 }
1311 tmp += 4;
1312 }
1313 }
1314
1315 framesize = stacksize;
1316 if (csky_debug)
1317 gdb_printf (gdb_stdlog, "csky: continuing\n");
1318 continue;
1319 }
1320 else if (CSKY_32_IS_LRW4 (insn) || CSKY_32_IS_MOVI4 (insn)
1321 || CSKY_32_IS_MOVIH4 (insn) || CSKY_32_IS_BMASKI4 (insn))
1322 {
1323 int adjust = 0;
1324 int offset = 0;
1325 unsigned int insn2;
1326
1327 if (csky_debug)
1328 {
1329 gdb_printf (gdb_stdlog,
1330 "csky: looking at large frame\n");
1331 }
1332 if (CSKY_32_IS_LRW4 (insn))
1333 {
1334 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1335 int literal_addr = (addr + ((insn & 0xffff) << 2))
1336 & 0xfffffffc;
1337 adjust = read_memory_unsigned_integer (literal_addr, 4,
1338 byte_order);
1339 }
1340 else if (CSKY_32_IS_MOVI4 (insn))
1341 adjust = (insn & 0xffff);
1342 else if (CSKY_32_IS_MOVIH4 (insn))
1343 adjust = (insn & 0xffff) << 16;
1344 else
1345 {
1346 /* CSKY_32_IS_BMASKI4 (insn). */
1347 adjust = (1 << (((insn & 0x3e00000) >> 21) + 1)) - 1;
1348 }
1349
1350 if (csky_debug)
1351 {
1352 gdb_printf (gdb_stdlog,
1353 "csky: base stacksize=0x%x\n", adjust);
1354
1355 /* May have zero or more insns which modify r4. */
1356 gdb_printf (gdb_stdlog,
1357 "csky: looking for r4 adjusters...\n");
1358 }
1359
1360 offset = 4;
1361 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1362 while (CSKY_IS_R4_ADJUSTER (insn2))
1363 {
1364 if (CSKY_32_IS_ADDI4 (insn2))
1365 {
1366 int imm = (insn2 & 0xfff) + 1;
1367 adjust += imm;
1368 if (csky_debug)
1369 {
1370 gdb_printf (gdb_stdlog,
1371 "csky: addi r4,%d\n", imm);
1372 }
1373 }
1374 else if (CSKY_32_IS_SUBI4 (insn2))
1375 {
1376 int imm = (insn2 & 0xfff) + 1;
1377 adjust -= imm;
1378 if (csky_debug)
1379 {
1380 gdb_printf (gdb_stdlog,
1381 "csky: subi r4,%d\n", imm);
1382 }
1383 }
1384 else if (CSKY_32_IS_NOR4 (insn2))
1385 {
1386 adjust = ~adjust;
1387 if (csky_debug)
1388 {
1389 gdb_printf (gdb_stdlog,
1390 "csky: nor r4,r4,r4\n");
1391 }
1392 }
1393 else if (CSKY_32_IS_ROTLI4 (insn2))
1394 {
1395 int imm = ((insn2 >> 21) & 0x1f);
1396 int temp = adjust >> (32 - imm);
1397 adjust <<= imm;
1398 adjust |= temp;
1399 if (csky_debug)
1400 {
1401 gdb_printf (gdb_stdlog,
1402 "csky: rotli r4,r4,%d\n", imm);
1403 }
1404 }
1405 else if (CSKY_32_IS_LISI4 (insn2))
1406 {
1407 int imm = ((insn2 >> 21) & 0x1f);
1408 adjust <<= imm;
1409 if (csky_debug)
1410 {
1411 gdb_printf (gdb_stdlog,
1412 "csky: lsli r4,r4,%d\n", imm);
1413 }
1414 }
1415 else if (CSKY_32_IS_BSETI4 (insn2))
1416 {
1417 int imm = ((insn2 >> 21) & 0x1f);
1418 adjust |= (1 << imm);
1419 if (csky_debug)
1420 {
1421 gdb_printf (gdb_stdlog,
1422 "csky: bseti r4,r4 %d\n", imm);
1423 }
1424 }
1425 else if (CSKY_32_IS_BCLRI4 (insn2))
1426 {
1427 int imm = ((insn2 >> 21) & 0x1f);
1428 adjust &= ~(1 << imm);
1429 if (csky_debug)
1430 {
1431 gdb_printf (gdb_stdlog,
1432 "csky: bclri r4,r4 %d\n", imm);
1433 }
1434 }
1435 else if (CSKY_32_IS_IXH4 (insn2))
1436 {
1437 adjust *= 3;
1438 if (csky_debug)
1439 {
1440 gdb_printf (gdb_stdlog,
1441 "csky: ixh r4,r4,r4\n");
1442 }
1443 }
1444 else if (CSKY_32_IS_IXW4 (insn2))
1445 {
1446 adjust *= 5;
1447 if (csky_debug)
1448 {
1449 gdb_printf (gdb_stdlog,
1450 "csky: ixw r4,r4,r4\n");
1451 }
1452 }
1453 else if (CSKY_16_IS_ADDI4 (insn2))
1454 {
1455 int imm = (insn2 & 0xff) + 1;
1456 adjust += imm;
1457 if (csky_debug)
1458 {
1459 gdb_printf (gdb_stdlog,
1460 "csky: addi r4,%d\n", imm);
1461 }
1462 }
1463 else if (CSKY_16_IS_SUBI4 (insn2))
1464 {
1465 int imm = (insn2 & 0xff) + 1;
1466 adjust -= imm;
1467 if (csky_debug)
1468 {
1469 gdb_printf (gdb_stdlog,
1470 "csky: subi r4,%d\n", imm);
1471 }
1472 }
1473 else if (CSKY_16_IS_NOR4 (insn2))
1474 {
1475 adjust = ~adjust;
1476 if (csky_debug)
1477 {
1478 gdb_printf (gdb_stdlog,
1479 "csky: nor r4,r4\n");
1480 }
1481 }
1482 else if (CSKY_16_IS_BSETI4 (insn2))
1483 {
1484 int imm = (insn2 & 0x1f);
1485 adjust |= (1 << imm);
1486 if (csky_debug)
1487 {
1488 gdb_printf (gdb_stdlog,
1489 "csky: bseti r4, %d\n", imm);
1490 }
1491 }
1492 else if (CSKY_16_IS_BCLRI4 (insn2))
1493 {
1494 int imm = (insn2 & 0x1f);
1495 adjust &= ~(1 << imm);
1496 if (csky_debug)
1497 {
1498 gdb_printf (gdb_stdlog,
1499 "csky: bclri r4, %d\n", imm);
1500 }
1501 }
1502 else if (CSKY_16_IS_LSLI4 (insn2))
1503 {
1504 int imm = (insn2 & 0x1f);
1505 adjust <<= imm;
1506 if (csky_debug)
1507 {
1508 gdb_printf (gdb_stdlog,
1509 "csky: lsli r4,r4, %d\n", imm);
1510 }
1511 }
1512
1513 offset += insn_len;
1514 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1515 };
1516
1517 if (csky_debug)
1518 {
1519 gdb_printf (gdb_stdlog, "csky: done looking for"
1520 " r4 adjusters\n");
1521 }
1522
1523 /* If the next insn adjusts the stack pointer, we keep
1524 everything; if not, we scrap it and we've found the
1525 end of the prologue. */
1526 if (CSKY_IS_SUBU4 (insn2))
1527 {
1528 addr += offset;
1529 stacksize += adjust;
1530 if (csky_debug)
1531 {
1532 gdb_printf (gdb_stdlog,
1533 "csky: found stack adjustment of"
1534 " 0x%x bytes.\n", adjust);
1535 gdb_printf (gdb_stdlog,
1536 "csky: skipping to new address %s\n",
1537 core_addr_to_string_nz (addr));
1538 gdb_printf (gdb_stdlog,
1539 "csky: continuing\n");
1540 }
1541 continue;
1542 }
1543
1544 /* None of these instructions are prologue, so don't touch
1545 anything. */
1546 if (csky_debug)
1547 {
1548 gdb_printf (gdb_stdlog,
1549 "csky: no subu sp,sp,r4; NOT altering"
1550 " stacksize.\n");
1551 }
1552 break;
1553 }
1554 }
1555 else
1556 {
1557 /* insn_len != 4. */
1558
1559 /* subi.sp sp,disp. */
1560 if (CSKY_16_IS_SUBI0 (insn))
1561 {
1562 int offset = CSKY_16_SUBI_IMM (insn);
1563 if (csky_debug)
1564 {
1565 gdb_printf (gdb_stdlog,
1566 "csky: got subi r0,%d; continuing\n",
1567 offset);
1568 }
1569 stacksize += offset;
1570 continue;
1571 }
1572 /* stw.16 rz,(sp,disp). */
1573 else if (CSKY_16_IS_STWx0 (insn))
1574 {
1575 /* Spill register: see note for IS_STM above. */
1576 int disp;
1577
1578 rn = CSKY_16_ST_VAL_REGNUM (insn);
1579 disp = CSKY_16_ST_OFFSET (insn);
1580 register_offsets[rn] = stacksize - disp;
1581 if (csky_debug)
1582 print_savedreg_msg (rn, register_offsets, true);
1583 continue;
1584 }
1585 else if (CSKY_16_IS_MOV_FP_SP (insn))
1586 {
1587 /* SP is saved to FP reg, means prologue may modify SP. */
1588 is_fp_saved = 1;
1589 adjust_fp = stacksize;
1590 continue;
1591 }
1592 else if (CSKY_16_IS_PUSH (insn))
1593 {
1594 /* Push for 16_bit. */
1595 int offset = 0;
1596 if (CSKY_16_IS_PUSH_R15 (insn))
1597 {
1598 stacksize += 4;
1599 register_offsets[15] = stacksize;
1600 if (csky_debug)
1601 print_savedreg_msg (15, register_offsets, false);
1602 offset += 4;
1603 }
1604 if (CSKY_16_PUSH_LIST1 (insn))
1605 {
1606 int num = CSKY_16_PUSH_LIST1 (insn);
1607 int tmp = 0;
1608 stacksize += num * 4;
1609 offset += num * 4;
1610 if (csky_debug)
1611 {
1612 gdb_printf (gdb_stdlog,
1613 "csky: push regs_array: r4-r%d\n",
1614 4 + num - 1);
1615 }
1616 for (rn = 4; rn <= 4 + num - 1; rn++)
1617 {
1618 register_offsets[rn] = stacksize - tmp;
1619 if (csky_debug)
1620 {
1621 gdb_printf (gdb_stdlog,
1622 "csky: r%d saved at 0x%x"
1623 " (offset %d)\n", rn,
1624 register_offsets[rn], offset);
1625 }
1626 tmp += 4;
1627 }
1628 }
1629
1630 framesize = stacksize;
1631 if (csky_debug)
1632 gdb_printf (gdb_stdlog, "csky: continuing\n");
1633 continue;
1634 }
1635 else if (CSKY_16_IS_LRW4 (insn) || CSKY_16_IS_MOVI4 (insn))
1636 {
1637 int adjust = 0;
1638 unsigned int insn2;
1639
1640 if (csky_debug)
1641 {
1642 gdb_printf (gdb_stdlog,
1643 "csky: looking at large frame\n");
1644 }
1645 if (CSKY_16_IS_LRW4 (insn))
1646 {
1647 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1648 int offset = ((insn & 0x300) >> 3) | (insn & 0x1f);
1649 int literal_addr = (addr + ( offset << 2)) & 0xfffffffc;
1650 adjust = read_memory_unsigned_integer (literal_addr, 4,
1651 byte_order);
1652 }
1653 else
1654 {
1655 /* CSKY_16_IS_MOVI4 (insn). */
1656 adjust = (insn & 0xff);
1657 }
1658
1659 if (csky_debug)
1660 {
1661 gdb_printf (gdb_stdlog,
1662 "csky: base stacksize=0x%x\n", adjust);
1663 }
1664
1665 /* May have zero or more instructions which modify r4. */
1666 if (csky_debug)
1667 {
1668 gdb_printf (gdb_stdlog,
1669 "csky: looking for r4 adjusters...\n");
1670 }
1671 int offset = 2;
1672 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1673 while (CSKY_IS_R4_ADJUSTER (insn2))
1674 {
1675 if (CSKY_32_IS_ADDI4 (insn2))
1676 {
1677 int imm = (insn2 & 0xfff) + 1;
1678 adjust += imm;
1679 if (csky_debug)
1680 {
1681 gdb_printf (gdb_stdlog,
1682 "csky: addi r4,%d\n", imm);
1683 }
1684 }
1685 else if (CSKY_32_IS_SUBI4 (insn2))
1686 {
1687 int imm = (insn2 & 0xfff) + 1;
1688 adjust -= imm;
1689 if (csky_debug)
1690 {
1691 gdb_printf (gdb_stdlog,
1692 "csky: subi r4,%d\n", imm);
1693 }
1694 }
1695 else if (CSKY_32_IS_NOR4 (insn2))
1696 {
1697 adjust = ~adjust;
1698 if (csky_debug)
1699 {
1700 gdb_printf (gdb_stdlog,
1701 "csky: nor r4,r4,r4\n");
1702 }
1703 }
1704 else if (CSKY_32_IS_ROTLI4 (insn2))
1705 {
1706 int imm = ((insn2 >> 21) & 0x1f);
1707 int temp = adjust >> (32 - imm);
1708 adjust <<= imm;
1709 adjust |= temp;
1710 if (csky_debug)
1711 {
1712 gdb_printf (gdb_stdlog,
1713 "csky: rotli r4,r4,%d\n", imm);
1714 }
1715 }
1716 else if (CSKY_32_IS_LISI4 (insn2))
1717 {
1718 int imm = ((insn2 >> 21) & 0x1f);
1719 adjust <<= imm;
1720 if (csky_debug)
1721 {
1722 gdb_printf (gdb_stdlog,
1723 "csky: lsli r4,r4,%d\n", imm);
1724 }
1725 }
1726 else if (CSKY_32_IS_BSETI4 (insn2))
1727 {
1728 int imm = ((insn2 >> 21) & 0x1f);
1729 adjust |= (1 << imm);
1730 if (csky_debug)
1731 {
1732 gdb_printf (gdb_stdlog,
1733 "csky: bseti r4,r4 %d\n", imm);
1734 }
1735 }
1736 else if (CSKY_32_IS_BCLRI4 (insn2))
1737 {
1738 int imm = ((insn2 >> 21) & 0x1f);
1739 adjust &= ~(1 << imm);
1740 if (csky_debug)
1741 {
1742 gdb_printf (gdb_stdlog,
1743 "csky: bclri r4,r4 %d\n", imm);
1744 }
1745 }
1746 else if (CSKY_32_IS_IXH4 (insn2))
1747 {
1748 adjust *= 3;
1749 if (csky_debug)
1750 {
1751 gdb_printf (gdb_stdlog,
1752 "csky: ixh r4,r4,r4\n");
1753 }
1754 }
1755 else if (CSKY_32_IS_IXW4 (insn2))
1756 {
1757 adjust *= 5;
1758 if (csky_debug)
1759 {
1760 gdb_printf (gdb_stdlog,
1761 "csky: ixw r4,r4,r4\n");
1762 }
1763 }
1764 else if (CSKY_16_IS_ADDI4 (insn2))
1765 {
1766 int imm = (insn2 & 0xff) + 1;
1767 adjust += imm;
1768 if (csky_debug)
1769 {
1770 gdb_printf (gdb_stdlog,
1771 "csky: addi r4,%d\n", imm);
1772 }
1773 }
1774 else if (CSKY_16_IS_SUBI4 (insn2))
1775 {
1776 int imm = (insn2 & 0xff) + 1;
1777 adjust -= imm;
1778 if (csky_debug)
1779 {
1780 gdb_printf (gdb_stdlog,
1781 "csky: subi r4,%d\n", imm);
1782 }
1783 }
1784 else if (CSKY_16_IS_NOR4 (insn2))
1785 {
1786 adjust = ~adjust;
1787 if (csky_debug)
1788 {
1789 gdb_printf (gdb_stdlog,
1790 "csky: nor r4,r4\n");
1791 }
1792 }
1793 else if (CSKY_16_IS_BSETI4 (insn2))
1794 {
1795 int imm = (insn2 & 0x1f);
1796 adjust |= (1 << imm);
1797 if (csky_debug)
1798 {
1799 gdb_printf (gdb_stdlog,
1800 "csky: bseti r4, %d\n", imm);
1801 }
1802 }
1803 else if (CSKY_16_IS_BCLRI4 (insn2))
1804 {
1805 int imm = (insn2 & 0x1f);
1806 adjust &= ~(1 << imm);
1807 if (csky_debug)
1808 {
1809 gdb_printf (gdb_stdlog,
1810 "csky: bclri r4, %d\n", imm);
1811 }
1812 }
1813 else if (CSKY_16_IS_LSLI4 (insn2))
1814 {
1815 int imm = (insn2 & 0x1f);
1816 adjust <<= imm;
1817 if (csky_debug)
1818 {
1819 gdb_printf (gdb_stdlog,
1820 "csky: lsli r4,r4, %d\n", imm);
1821 }
1822 }
1823
1824 offset += insn_len;
1825 insn_len = csky_get_insn (gdbarch, addr + offset, &insn2);
1826 };
1827
1828 if (csky_debug)
1829 {
1830 gdb_printf (gdb_stdlog, "csky: "
1831 "done looking for r4 adjusters\n");
1832 }
1833
1834 /* If the next instruction adjusts the stack pointer, we keep
1835 everything; if not, we scrap it and we've found the end
1836 of the prologue. */
1837 if (CSKY_IS_SUBU4 (insn2))
1838 {
1839 addr += offset;
1840 stacksize += adjust;
1841 if (csky_debug)
1842 {
1843 gdb_printf (gdb_stdlog, "csky: "
1844 "found stack adjustment of 0x%x"
1845 " bytes.\n", adjust);
1846 gdb_printf (gdb_stdlog, "csky: "
1847 "skipping to new address %s\n",
1848 core_addr_to_string_nz (addr));
1849 gdb_printf (gdb_stdlog, "csky: continuing\n");
1850 }
1851 continue;
1852 }
1853
1854 /* None of these instructions are prologue, so don't touch
1855 anything. */
1856 if (csky_debug)
1857 {
1858 gdb_printf (gdb_stdlog, "csky: no subu sp,r4; "
1859 "NOT altering stacksize.\n");
1860 }
1861 break;
1862 }
1863 }
1864
1865 /* This is not a prologue instruction, so stop here. */
1866 if (csky_debug)
1867 {
1868 gdb_printf (gdb_stdlog, "csky: insn is not a prologue"
1869 " insn -- ending scan\n");
1870 }
1871 break;
1872 }
1873
1874 if (this_cache)
1875 {
1876 CORE_ADDR unwound_fp;
1877 enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1878 this_cache->framesize = framesize;
1879
1880 if (is_fp_saved)
1881 {
1882 this_cache->framereg = CSKY_FP_REGNUM;
1883 unwound_fp = get_frame_register_unsigned (this_frame,
1884 this_cache->framereg);
1885 this_cache->prev_sp = unwound_fp + adjust_fp;
1886 }
1887 else
1888 {
1889 this_cache->framereg = CSKY_SP_REGNUM;
1890 unwound_fp = get_frame_register_unsigned (this_frame,
1891 this_cache->framereg);
1892 this_cache->prev_sp = unwound_fp + stacksize;
1893 }
1894
1895 /* Note where saved registers are stored. The offsets in
1896 REGISTER_OFFSETS are computed relative to the top of the frame. */
1897 for (rn = 0; rn < CSKY_NUM_GREGS; rn++)
1898 {
1899 if (register_offsets[rn] >= 0)
1900 {
1901 this_cache->saved_regs[rn].set_addr (this_cache->prev_sp
1902 - register_offsets[rn]);
1903 if (csky_debug)
1904 {
1905 CORE_ADDR rn_value = read_memory_unsigned_integer (
1906 this_cache->saved_regs[rn].addr (), 4, byte_order);
1907 gdb_printf (gdb_stdlog, "Saved register %s "
1908 "stored at 0x%08lx, value=0x%08lx\n",
1909 csky_register_names[rn],
1910 (unsigned long)
1911 this_cache->saved_regs[rn].addr (),
1912 (unsigned long) rn_value);
1913 }
1914 }
1915 }
1916 if (lr_type == LR_TYPE_EPC)
1917 {
1918 /* rte || epc . */
1919 this_cache->saved_regs[CSKY_PC_REGNUM]
1920 = this_cache->saved_regs[CSKY_EPC_REGNUM];
1921 }
1922 else if (lr_type == LR_TYPE_FPC)
1923 {
1924 /* rfi || fpc . */
1925 this_cache->saved_regs[CSKY_PC_REGNUM]
1926 = this_cache->saved_regs[CSKY_FPC_REGNUM];
1927 }
1928 else
1929 {
1930 this_cache->saved_regs[CSKY_PC_REGNUM]
1931 = this_cache->saved_regs[CSKY_LR_REGNUM];
1932 }
1933 }
1934
1935 return addr;
1936 }
1937
1938 /* Detect whether PC is at a point where the stack frame has been
1939 destroyed. */
1940
1941 static int
1942 csky_stack_frame_destroyed_p (struct gdbarch *gdbarch, CORE_ADDR pc)
1943 {
1944 unsigned int insn;
1945 CORE_ADDR addr;
1946 CORE_ADDR func_start, func_end;
1947
1948 if (!find_pc_partial_function (pc, NULL, &func_start, &func_end))
1949 return 0;
1950
1951 bool fp_saved = false;
1952 int insn_len;
1953 for (addr = func_start; addr < func_end; addr += insn_len)
1954 {
1955 /* Get next insn. */
1956 insn_len = csky_get_insn (gdbarch, addr, &insn);
1957
1958 if (insn_len == 2)
1959 {
1960 /* Is sp is saved to fp. */
1961 if (CSKY_16_IS_MOV_FP_SP (insn))
1962 fp_saved = true;
1963 /* If sp was saved to fp and now being restored from
1964 fp then it indicates the start of epilog. */
1965 else if (fp_saved && CSKY_16_IS_MOV_SP_FP (insn))
1966 return pc >= addr;
1967 }
1968 }
1969 return 0;
1970 }
1971
1972 /* Implement the skip_prologue gdbarch hook. */
1973
1974 static CORE_ADDR
1975 csky_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
1976 {
1977 CORE_ADDR func_addr, func_end;
1978 const int default_search_limit = 128;
1979
1980 /* See if we can find the end of the prologue using the symbol table. */
1981 if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
1982 {
1983 CORE_ADDR post_prologue_pc
1984 = skip_prologue_using_sal (gdbarch, func_addr);
1985
1986 if (post_prologue_pc != 0)
1987 return std::max (pc, post_prologue_pc);
1988 }
1989 else
1990 func_end = pc + default_search_limit;
1991
1992 /* Find the end of prologue. Default lr_type. */
1993 return csky_analyze_prologue (gdbarch, pc, func_end, func_end,
1994 NULL, NULL, LR_TYPE_R15);
1995 }
1996
1997 /* Implement the breakpoint_kind_from_pc gdbarch method. */
1998
1999 static int
2000 csky_breakpoint_kind_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr)
2001 {
2002 if (csky_pc_is_csky16 (gdbarch, *pcptr))
2003 return CSKY_INSN_SIZE16;
2004 else
2005 return CSKY_INSN_SIZE32;
2006 }
2007
2008 /* Implement the sw_breakpoint_from_kind gdbarch method. */
2009
2010 static const gdb_byte *
2011 csky_sw_breakpoint_from_kind (struct gdbarch *gdbarch, int kind, int *size)
2012 {
2013 *size = kind;
2014 if (kind == CSKY_INSN_SIZE16)
2015 {
2016 static gdb_byte csky_16_breakpoint[] = { 0, 0 };
2017 return csky_16_breakpoint;
2018 }
2019 else
2020 {
2021 static gdb_byte csky_32_breakpoint[] = { 0, 0, 0, 0 };
2022 return csky_32_breakpoint;
2023 }
2024 }
2025
2026 /* Determine link register type. */
2027
2028 static lr_type_t
2029 csky_analyze_lr_type (struct gdbarch *gdbarch,
2030 CORE_ADDR start_pc, CORE_ADDR end_pc)
2031 {
2032 CORE_ADDR addr;
2033 unsigned int insn, insn_len;
2034 insn_len = 2;
2035
2036 for (addr = start_pc; addr < end_pc; addr += insn_len)
2037 {
2038 insn_len = csky_get_insn (gdbarch, addr, &insn);
2039 if (insn_len == 4)
2040 {
2041 if (CSKY_32_IS_MFCR_EPSR (insn) || CSKY_32_IS_MFCR_EPC (insn)
2042 || CSKY_32_IS_RTE (insn))
2043 return LR_TYPE_EPC;
2044 }
2045 else if (CSKY_32_IS_MFCR_FPSR (insn) || CSKY_32_IS_MFCR_FPC (insn)
2046 || CSKY_32_IS_RFI (insn))
2047 return LR_TYPE_FPC;
2048 else if (CSKY_32_IS_JMP (insn) || CSKY_32_IS_BR (insn)
2049 || CSKY_32_IS_JMPIX (insn) || CSKY_32_IS_JMPI (insn))
2050 return LR_TYPE_R15;
2051 else
2052 {
2053 /* 16 bit instruction. */
2054 if (CSKY_16_IS_JMP (insn) || CSKY_16_IS_BR (insn)
2055 || CSKY_16_IS_JMPIX (insn))
2056 return LR_TYPE_R15;
2057 }
2058 }
2059 return LR_TYPE_R15;
2060 }
2061
2062 /* Heuristic unwinder. */
2063
2064 static struct csky_unwind_cache *
2065 csky_frame_unwind_cache (const frame_info_ptr &this_frame)
2066 {
2067 CORE_ADDR prologue_start, prologue_end, func_end, prev_pc, block_addr;
2068 struct csky_unwind_cache *cache;
2069 const struct block *bl;
2070 unsigned long func_size = 0;
2071 struct gdbarch *gdbarch = get_frame_arch (this_frame);
2072 unsigned int sp_regnum = CSKY_SP_REGNUM;
2073
2074 /* Default lr type is r15. */
2075 lr_type_t lr_type = LR_TYPE_R15;
2076
2077 cache = FRAME_OBSTACK_ZALLOC (struct csky_unwind_cache);
2078 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2079
2080 /* Assume there is no frame until proven otherwise. */
2081 cache->framereg = sp_regnum;
2082
2083 cache->framesize = 0;
2084
2085 prev_pc = get_frame_pc (this_frame);
2086 block_addr = get_frame_address_in_block (this_frame);
2087 if (find_pc_partial_function (block_addr, NULL, &prologue_start,
2088 &func_end) == 0)
2089 /* We couldn't find a function containing block_addr, so bail out
2090 and hope for the best. */
2091 return cache;
2092
2093 /* Get the (function) symbol matching prologue_start. */
2094 bl = block_for_pc (prologue_start);
2095 if (bl != NULL)
2096 func_size = bl->end () - bl->start ();
2097 else
2098 {
2099 struct bound_minimal_symbol msymbol
2100 = lookup_minimal_symbol_by_pc (prologue_start);
2101 if (msymbol.minsym != NULL)
2102 func_size = msymbol.minsym->size ();
2103 }
2104
2105 /* If FUNC_SIZE is 0 we may have a special-case use of lr
2106 e.g. exception or interrupt. */
2107 if (func_size == 0)
2108 lr_type = csky_analyze_lr_type (gdbarch, prologue_start, func_end);
2109
2110 prologue_end = std::min (func_end, prev_pc);
2111
2112 /* Analyze the function prologue. */
2113 csky_analyze_prologue (gdbarch, prologue_start, prologue_end,
2114 func_end, this_frame, cache, lr_type);
2115
2116 /* gdbarch_sp_regnum contains the value and not the address. */
2117 cache->saved_regs[sp_regnum].set_value (cache->prev_sp);
2118 return cache;
2119 }
2120
2121 /* Implement the this_id function for the normal unwinder. */
2122
2123 static void
2124 csky_frame_this_id (const frame_info_ptr &this_frame,
2125 void **this_prologue_cache, struct frame_id *this_id)
2126 {
2127 struct csky_unwind_cache *cache;
2128 struct frame_id id;
2129
2130 if (*this_prologue_cache == NULL)
2131 *this_prologue_cache = csky_frame_unwind_cache (this_frame);
2132 cache = (struct csky_unwind_cache *) *this_prologue_cache;
2133
2134 /* This marks the outermost frame. */
2135 if (cache->prev_sp == 0)
2136 return;
2137
2138 id = frame_id_build (cache->prev_sp, get_frame_func (this_frame));
2139 *this_id = id;
2140 }
2141
2142 /* Implement the prev_register function for the normal unwinder. */
2143
2144 static struct value *
2145 csky_frame_prev_register (const frame_info_ptr &this_frame,
2146 void **this_prologue_cache, int regnum)
2147 {
2148 struct csky_unwind_cache *cache;
2149
2150 if (*this_prologue_cache == NULL)
2151 *this_prologue_cache = csky_frame_unwind_cache (this_frame);
2152 cache = (struct csky_unwind_cache *) *this_prologue_cache;
2153
2154 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2155 regnum);
2156 }
2157
2158 /* Data structures for the normal prologue-analysis-based
2159 unwinder. */
2160
2161 static const struct frame_unwind csky_unwind_cache = {
2162 "cski prologue",
2163 NORMAL_FRAME,
2164 default_frame_unwind_stop_reason,
2165 csky_frame_this_id,
2166 csky_frame_prev_register,
2167 NULL,
2168 default_frame_sniffer,
2169 NULL,
2170 NULL
2171 };
2172
2173 static CORE_ADDR
2174 csky_check_long_branch (const frame_info_ptr &frame, CORE_ADDR pc)
2175 {
2176 gdb_byte buf[8];
2177 struct gdbarch *gdbarch = get_frame_arch (frame);
2178 enum bfd_endian byte_order_for_code
2179 = gdbarch_byte_order_for_code (gdbarch);
2180
2181 if (target_read_memory (pc, buf, 8) == 0)
2182 {
2183 unsigned int data0
2184 = extract_unsigned_integer (buf, 4, byte_order_for_code);
2185 unsigned int data1
2186 = extract_unsigned_integer (buf + 4, 4, byte_order_for_code);
2187
2188 /* Case: jmpi [pc+4] : 0xeac00001
2189 .long addr */
2190 if (data0 == CSKY_JMPI_PC_4)
2191 return data1;
2192
2193 /* Case: lrw t1, [pc+8] : 0xea8d0002
2194 jmp t1 : 0x7834
2195 nop : 0x6c03
2196 .long addr */
2197 if ((data0 == CSKY_LRW_T1_PC_8) && (data1 == CSKY_JMP_T1_VS_NOP))
2198 {
2199 if (target_read_memory (pc + 8, buf, 4) == 0)
2200 return extract_unsigned_integer (buf, 4, byte_order_for_code);
2201 }
2202
2203 return 0;
2204 }
2205
2206 return 0;
2207 }
2208
2209 static int
2210 csky_stub_unwind_sniffer (const struct frame_unwind *self,
2211 const frame_info_ptr &this_frame,
2212 void **this_prologue_cache)
2213 {
2214 CORE_ADDR addr_in_block, pc;
2215 gdb_byte dummy[4];
2216 const char *name;
2217 CORE_ADDR start_addr;
2218
2219 /* Get pc */
2220 addr_in_block = get_frame_address_in_block (this_frame);
2221 pc = get_frame_pc (this_frame);
2222
2223 if (in_plt_section (addr_in_block)
2224 || target_read_memory (pc, dummy, 4) != 0)
2225 return 1;
2226
2227 /* Find the starting address and name of the function containing the PC. */
2228 if (find_pc_partial_function (pc, &name, &start_addr, NULL) == 0)
2229 {
2230 start_addr = csky_check_long_branch (this_frame, pc);
2231 /* if not long branch, return 0. */
2232 if (start_addr != 0)
2233 return 1;
2234
2235 return 0;
2236 }
2237
2238 return 0;
2239 }
2240
2241 static struct csky_unwind_cache *
2242 csky_make_stub_cache (const frame_info_ptr &this_frame)
2243 {
2244 struct csky_unwind_cache *cache;
2245
2246 cache = FRAME_OBSTACK_ZALLOC (struct csky_unwind_cache);
2247 cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
2248 cache->prev_sp = get_frame_register_unsigned (this_frame, CSKY_SP_REGNUM);
2249
2250 return cache;
2251 }
2252
2253 static void
2254 csky_stub_this_id (const frame_info_ptr &this_frame,
2255 void **this_cache,
2256 struct frame_id *this_id)
2257 {
2258 struct csky_unwind_cache *cache;
2259
2260 if (*this_cache == NULL)
2261 *this_cache = csky_make_stub_cache (this_frame);
2262 cache = (struct csky_unwind_cache *) *this_cache;
2263
2264 /* Our frame ID for a stub frame is the current SP and LR. */
2265 *this_id = frame_id_build (cache->prev_sp, get_frame_pc (this_frame));
2266 }
2267
2268 static struct value *
2269 csky_stub_prev_register (const frame_info_ptr &this_frame,
2270 void **this_cache,
2271 int prev_regnum)
2272 {
2273 struct csky_unwind_cache *cache;
2274
2275 if (*this_cache == NULL)
2276 *this_cache = csky_make_stub_cache (this_frame);
2277 cache = (struct csky_unwind_cache *) *this_cache;
2278
2279 /* If we are asked to unwind the PC, then return the LR. */
2280 if (prev_regnum == CSKY_PC_REGNUM)
2281 {
2282 CORE_ADDR lr;
2283
2284 lr = frame_unwind_register_unsigned (this_frame, CSKY_LR_REGNUM);
2285 return frame_unwind_got_constant (this_frame, prev_regnum, lr);
2286 }
2287
2288 if (prev_regnum == CSKY_SP_REGNUM)
2289 return frame_unwind_got_constant (this_frame, prev_regnum, cache->prev_sp);
2290
2291 return trad_frame_get_prev_register (this_frame, cache->saved_regs,
2292 prev_regnum);
2293 }
2294
2295 static frame_unwind csky_stub_unwind = {
2296 "csky stub",
2297 NORMAL_FRAME,
2298 default_frame_unwind_stop_reason,
2299 csky_stub_this_id,
2300 csky_stub_prev_register,
2301 NULL,
2302 csky_stub_unwind_sniffer
2303 };
2304
2305 /* Implement the this_base, this_locals, and this_args hooks
2306 for the normal unwinder. */
2307
2308 static CORE_ADDR
2309 csky_frame_base_address (const frame_info_ptr &this_frame, void **this_cache)
2310 {
2311 struct csky_unwind_cache *cache;
2312
2313 if (*this_cache == NULL)
2314 *this_cache = csky_frame_unwind_cache (this_frame);
2315 cache = (struct csky_unwind_cache *) *this_cache;
2316
2317 return cache->prev_sp - cache->framesize;
2318 }
2319
2320 static const struct frame_base csky_frame_base = {
2321 &csky_unwind_cache,
2322 csky_frame_base_address,
2323 csky_frame_base_address,
2324 csky_frame_base_address
2325 };
2326
2327 /* Initialize register access method. */
2328
2329 static void
2330 csky_dwarf2_frame_init_reg (struct gdbarch *gdbarch, int regnum,
2331 struct dwarf2_frame_state_reg *reg,
2332 const frame_info_ptr &this_frame)
2333 {
2334 if (regnum == gdbarch_pc_regnum (gdbarch))
2335 reg->how = DWARF2_FRAME_REG_RA;
2336 else if (regnum == gdbarch_sp_regnum (gdbarch))
2337 reg->how = DWARF2_FRAME_REG_CFA;
2338 }
2339
2340 /* Create csky register groups. */
2341
2342 static void
2343 csky_init_reggroup ()
2344 {
2345 cr_reggroup = reggroup_new ("cr", USER_REGGROUP);
2346 fr_reggroup = reggroup_new ("fr", USER_REGGROUP);
2347 vr_reggroup = reggroup_new ("vr", USER_REGGROUP);
2348 mmu_reggroup = reggroup_new ("mmu", USER_REGGROUP);
2349 prof_reggroup = reggroup_new ("profiling", USER_REGGROUP);
2350 }
2351
2352 /* Add register groups into reggroup list. */
2353
2354 static void
2355 csky_add_reggroups (struct gdbarch *gdbarch)
2356 {
2357 reggroup_add (gdbarch, cr_reggroup);
2358 reggroup_add (gdbarch, fr_reggroup);
2359 reggroup_add (gdbarch, vr_reggroup);
2360 reggroup_add (gdbarch, mmu_reggroup);
2361 reggroup_add (gdbarch, prof_reggroup);
2362 }
2363
2364 /* Return the groups that a CSKY register can be categorised into. */
2365
2366 static int
2367 csky_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
2368 const struct reggroup *reggroup)
2369 {
2370 int raw_p;
2371
2372 if (gdbarch_register_name (gdbarch, regnum)[0] == '\0')
2373 return 0;
2374
2375 if (reggroup == all_reggroup)
2376 return 1;
2377
2378 raw_p = regnum < gdbarch_num_regs (gdbarch);
2379 if (reggroup == save_reggroup || reggroup == restore_reggroup)
2380 return raw_p;
2381
2382 if ((((regnum >= CSKY_R0_REGNUM) && (regnum <= CSKY_R0_REGNUM + 31))
2383 || (regnum == CSKY_PC_REGNUM)
2384 || (regnum == CSKY_EPC_REGNUM)
2385 || (regnum == CSKY_CR0_REGNUM)
2386 || (regnum == CSKY_EPSR_REGNUM))
2387 && (reggroup == general_reggroup))
2388 return 1;
2389
2390 if (((regnum == CSKY_PC_REGNUM)
2391 || ((regnum >= CSKY_CR0_REGNUM)
2392 && (regnum <= CSKY_CR0_REGNUM + 30)))
2393 && (reggroup == cr_reggroup))
2394 return 2;
2395
2396 if ((((regnum >= CSKY_VR0_REGNUM) && (regnum <= CSKY_VR0_REGNUM + 15))
2397 || ((regnum >= CSKY_FCR_REGNUM)
2398 && (regnum <= CSKY_FCR_REGNUM + 2)))
2399 && (reggroup == vr_reggroup))
2400 return 3;
2401
2402 if (((regnum >= CSKY_MMU_REGNUM) && (regnum <= CSKY_MMU_REGNUM + 8))
2403 && (reggroup == mmu_reggroup))
2404 return 4;
2405
2406 if (((regnum >= CSKY_PROFCR_REGNUM)
2407 && (regnum <= CSKY_PROFCR_REGNUM + 48))
2408 && (reggroup == prof_reggroup))
2409 return 5;
2410
2411 if ((((regnum >= CSKY_FR0_REGNUM) && (regnum <= CSKY_FR0_REGNUM + 15))
2412 || ((regnum >= CSKY_FCR_REGNUM) && (regnum <= CSKY_FCR_REGNUM + 2)))
2413 && (reggroup == fr_reggroup))
2414 return 6;
2415
2416 if (tdesc_has_registers (gdbarch_target_desc (gdbarch)))
2417 {
2418 if (tdesc_register_in_reggroup_p (gdbarch, regnum, reggroup) > 0)
2419 return 7;
2420 }
2421
2422 return 0;
2423 }
2424
2425 /* Implement the dwarf2_reg_to_regnum gdbarch method. */
2426
2427 static int
2428 csky_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int dw_reg)
2429 {
2430 /* For GPRs. */
2431 if (dw_reg >= CSKY_R0_REGNUM && dw_reg <= CSKY_R0_REGNUM + 31)
2432 return dw_reg;
2433
2434 /* For Hi, Lo, PC. */
2435 if (dw_reg == CSKY_HI_REGNUM || dw_reg == CSKY_LO_REGNUM
2436 || dw_reg == CSKY_PC_REGNUM)
2437 return dw_reg;
2438
2439 /* For Float and Vector pseudo registers. */
2440 if (dw_reg >= FV_PSEUDO_REGNO_FIRST && dw_reg <= FV_PSEUDO_REGNO_LAST)
2441 {
2442 char name_buf[4];
2443
2444 xsnprintf (name_buf, sizeof (name_buf), "s%d",
2445 dw_reg - FV_PSEUDO_REGNO_FIRST);
2446 return user_reg_map_name_to_regnum (gdbarch, name_buf,
2447 strlen (name_buf));
2448 }
2449
2450 /* Others, unknown. */
2451 return -1;
2452 }
2453
2454 /* Check whether xml has discribled the essential regs. */
2455
2456 static int
2457 csky_essential_reg_check (const struct csky_supported_tdesc_register *reg)
2458 {
2459 if ((strcmp (reg->name , "pc") == 0)
2460 && (reg->num == CSKY_PC_REGNUM))
2461 return CSKY_TDESC_REGS_PC_NUMBERED;
2462 else if ((strcmp (reg->name , "r14") == 0)
2463 && (reg->num == CSKY_SP_REGNUM))
2464 return CSKY_TDESC_REGS_SP_NUMBERED;
2465 else if ((strcmp (reg->name , "r15") == 0)
2466 && (reg->num == CSKY_LR_REGNUM))
2467 return CSKY_TDESC_REGS_LR_NUMBERED;
2468 else
2469 return 0;
2470 }
2471
2472 /* Check whether xml has discribled the fr0~fr15 regs. */
2473
2474 static int
2475 csky_fr0_fr15_reg_check (const struct csky_supported_tdesc_register *reg) {
2476 int i = 0;
2477 for (i = 0; i < 16; i++)
2478 {
2479 if ((strcmp (reg->name, csky_supported_fpu_regs[i].name) == 0)
2480 && (csky_supported_fpu_regs[i].num == reg->num))
2481 return (1 << i);
2482 }
2483
2484 return 0;
2485 };
2486
2487 /* Check whether xml has discribled the fr16~fr31 regs. */
2488
2489 static int
2490 csky_fr16_fr31_reg_check (const struct csky_supported_tdesc_register *reg) {
2491 int i = 0;
2492 for (i = 0; i < 16; i++)
2493 {
2494 if ((strcmp (reg->name, csky_supported_fpu_regs[i + 16].name) == 0)
2495 && (csky_supported_fpu_regs[i + 16].num == reg->num))
2496 return (1 << i);
2497 }
2498
2499 return 0;
2500 };
2501
2502 /* Check whether xml has discribled the vr0~vr15 regs. */
2503
2504 static int
2505 csky_vr0_vr15_reg_check (const struct csky_supported_tdesc_register *reg) {
2506 int i = 0;
2507 for (i = 0; i < 16; i++)
2508 {
2509 if ((strcmp (reg->name, csky_supported_fpu_regs[i + 32].name) == 0)
2510 && (csky_supported_fpu_regs[i + 32].num == reg->num))
2511 return (1 << i);
2512 }
2513
2514 return 0;
2515 };
2516
2517 /* Return pseudo reg's name. */
2518
2519 static const char *
2520 csky_pseudo_register_name (struct gdbarch *gdbarch, int regno)
2521 {
2522 int num_regs = gdbarch_num_regs (gdbarch);
2523 csky_gdbarch_tdep *tdep
2524 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2525
2526 regno -= num_regs;
2527
2528 if (tdep->fv_pseudo_registers_count)
2529 {
2530 static const char *const fv_pseudo_names[] = {
2531 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
2532 "s8", "s9", "s10", "s11", "s12", "s13", "s14", "s15",
2533 "s16", "s17", "s18", "s19", "s20", "s21", "s22", "s23",
2534 "s24", "s25", "s26", "s27", "s28", "s29", "s30", "s31",
2535 "s32", "s33", "s34", "s35", "s36", "s37", "s38", "s39",
2536 "s40", "s41", "s42", "s43", "s44", "s45", "s46", "s47",
2537 "s48", "s49", "s50", "s51", "s52", "s53", "s54", "s55",
2538 "s56", "s57", "s58", "s59", "s60", "s61", "s62", "s63",
2539 "s64", "s65", "s66", "s67", "s68", "s69", "s70", "s71",
2540 "s72", "s73", "s74", "s75", "s76", "s77", "s78", "s79",
2541 "s80", "s81", "s82", "s83", "s84", "s85", "s86", "s87",
2542 "s88", "s89", "s90", "s91", "s92", "s93", "s94", "s95",
2543 "s96", "s97", "s98", "s99", "s100", "s101", "s102", "s103",
2544 "s104", "s105", "s106", "s107", "s108", "s109", "s110", "s111",
2545 "s112", "s113", "s114", "s115", "s116", "s117", "s118", "s119",
2546 "s120", "s121", "s122", "s123", "s124", "s125", "s126", "s127",
2547 };
2548
2549 if (regno < tdep->fv_pseudo_registers_count)
2550 {
2551 if ((regno < 64) && ((regno % 4) >= 2) && !tdep->has_vr0)
2552 return "";
2553 else if ((regno >= 64) && ((regno % 4) >= 2))
2554 return "";
2555 else
2556 return fv_pseudo_names[regno];
2557 }
2558 }
2559
2560 return "";
2561 }
2562
2563 /* Read for csky pseudo regs. */
2564
2565 static enum register_status
2566 csky_pseudo_register_read (struct gdbarch *gdbarch,
2567 struct readable_regcache *regcache,
2568 int regnum, gdb_byte *buf)
2569 {
2570 int num_regs = gdbarch_num_regs (gdbarch);
2571 csky_gdbarch_tdep *tdep
2572 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2573
2574 regnum -= num_regs;
2575
2576 if (regnum < tdep->fv_pseudo_registers_count)
2577 {
2578 enum register_status status;
2579 int gdb_regnum = 0;
2580 int offset = 0;
2581 gdb_byte reg_buf[16];
2582
2583 /* Ensure getting s0~s63 from vrx if tdep->has_vr0 is true. */
2584 if (tdep->has_vr0)
2585 {
2586 if (regnum < 64)
2587 {
2588 gdb_regnum = CSKY_VR0_REGNUM + (regnum / 4);
2589 offset = (regnum % 4) * 4;
2590 }
2591 else
2592 {
2593 gdb_regnum = CSKY_FR16_REGNUM + ((regnum - 64) / 4);
2594 if ((regnum % 4) >= 2)
2595 return REG_UNAVAILABLE;
2596 offset = (regnum % 2) * 4;
2597 }
2598 }
2599 else
2600 {
2601 gdb_regnum = CSKY_FR0_REGNUM + (regnum / 4);
2602 if ((regnum % 4) >= 2)
2603 return REG_UNAVAILABLE;
2604 offset = (regnum % 2) * 4;
2605 }
2606
2607 status = regcache->raw_read (gdb_regnum, reg_buf);
2608 if (status == REG_VALID)
2609 memcpy (buf, reg_buf + offset, 4);
2610 return status;
2611 }
2612
2613 return REG_UNKNOWN;
2614 }
2615
2616 /* Write for csky pseudo regs. */
2617
2618 static void
2619 csky_pseudo_register_write (struct gdbarch *gdbarch, struct regcache *regcache,
2620 int regnum, const gdb_byte *buf)
2621 {
2622 int num_regs = gdbarch_num_regs (gdbarch);
2623 csky_gdbarch_tdep *tdep
2624 = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2625
2626 regnum -= num_regs;
2627
2628 if (regnum < tdep->fv_pseudo_registers_count)
2629 {
2630 gdb_byte reg_buf[16];
2631 int gdb_regnum = 0;
2632 int offset = 0;
2633
2634 if (tdep->has_vr0)
2635 {
2636 if (regnum < 64)
2637 {
2638 gdb_regnum = CSKY_VR0_REGNUM + (regnum / 4);
2639 offset = (regnum % 4) * 4;
2640 }
2641 else
2642 {
2643 gdb_regnum = CSKY_FR16_REGNUM + ((regnum - 64) / 4);
2644 if ((regnum % 4) >= 2)
2645 return;
2646 offset = (regnum % 2) * 4;
2647 }
2648 }
2649 else
2650 {
2651 gdb_regnum = CSKY_FR0_REGNUM + (regnum / 4);
2652 if ((regnum % 4) >= 2)
2653 return;
2654 offset = (regnum % 2) * 4;
2655 }
2656
2657 regcache->raw_read (gdb_regnum, reg_buf);
2658 memcpy (reg_buf + offset, buf, 4);
2659 regcache->raw_write (gdb_regnum, reg_buf);
2660 return;
2661 }
2662
2663 return;
2664 }
2665
2666 /* Initialize the current architecture based on INFO. If possible,
2667 re-use an architecture from ARCHES, which is a list of
2668 architectures already created during this debugging session.
2669
2670 Called at program startup, when reading a core file, and when
2671 reading a binary file. */
2672
2673 static struct gdbarch *
2674 csky_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
2675 {
2676 /* Analyze info.abfd. */
2677 unsigned int fpu_abi = 0;
2678 unsigned int vdsp_version = 0;
2679 unsigned int fpu_hardfp = 0;
2680 /* Analyze info.target_desc */
2681 int num_regs = 0;
2682 int has_fr0 = 0;
2683 int has_fr16 = 0;
2684 int has_vr0 = 0;
2685 tdesc_arch_data_up tdesc_data;
2686
2687 if (tdesc_has_registers (info.target_desc))
2688 {
2689 int valid_p = 0;
2690 int numbered = 0;
2691 int index = 0;
2692 int i = 0;
2693 int feature_names_count = ARRAY_SIZE (csky_supported_tdesc_feature_names);
2694 int support_tdesc_regs_count
2695 = csky_get_supported_tdesc_registers_count();
2696 const struct csky_supported_tdesc_register *tdesc_reg;
2697 const struct tdesc_feature *feature;
2698
2699 tdesc_data = tdesc_data_alloc ();
2700 for (index = 0; index < feature_names_count; index ++)
2701 {
2702 feature = tdesc_find_feature (info.target_desc,
2703 csky_supported_tdesc_feature_names[index]);
2704 if (feature != NULL)
2705 {
2706 for (i = 0; i < support_tdesc_regs_count; i++)
2707 {
2708 tdesc_reg = csky_get_supported_register_by_index (i);
2709 if (!tdesc_reg)
2710 break;
2711 numbered = tdesc_numbered_register (feature, tdesc_data.get(),
2712 tdesc_reg->num,
2713 tdesc_reg->name);
2714 if (numbered) {
2715 valid_p |= csky_essential_reg_check (tdesc_reg);
2716 has_fr0 |= csky_fr0_fr15_reg_check (tdesc_reg);
2717 has_fr16 |= csky_fr16_fr31_reg_check (tdesc_reg);
2718 has_vr0 |= csky_vr0_vr15_reg_check (tdesc_reg);
2719 if (num_regs < tdesc_reg->num)
2720 num_regs = tdesc_reg->num;
2721 }
2722 }
2723 }
2724 }
2725 if (valid_p != CSKY_TDESC_REGS_ESSENTIAL_VALUE)
2726 return NULL;
2727 }
2728
2729 /* When the type of bfd file is srec(or any files are not elf),
2730 the E_FLAGS will be not credible. */
2731 if (info.abfd != NULL && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
2732 {
2733 /* Get FPU, VDSP build options. */
2734 fpu_abi = bfd_elf_get_obj_attr_int (info.abfd,
2735 OBJ_ATTR_PROC,
2736 Tag_CSKY_FPU_ABI);
2737 vdsp_version = bfd_elf_get_obj_attr_int (info.abfd,
2738 OBJ_ATTR_PROC,
2739 Tag_CSKY_VDSP_VERSION);
2740 fpu_hardfp = bfd_elf_get_obj_attr_int (info.abfd,
2741 OBJ_ATTR_PROC,
2742 Tag_CSKY_FPU_HARDFP);
2743 }
2744
2745 /* Find a candidate among the list of pre-declared architectures. */
2746 for (arches = gdbarch_list_lookup_by_info (arches, &info);
2747 arches != NULL;
2748 arches = gdbarch_list_lookup_by_info (arches->next, &info))
2749 {
2750 csky_gdbarch_tdep *tdep
2751 = gdbarch_tdep<csky_gdbarch_tdep> (arches->gdbarch);
2752 if (fpu_abi != tdep->fpu_abi)
2753 continue;
2754 if (vdsp_version != tdep->vdsp_version)
2755 continue;
2756 if (fpu_hardfp != tdep->fpu_hardfp)
2757 continue;
2758
2759 /* Found a match. */
2760 return arches->gdbarch;
2761 }
2762
2763 /* None found, create a new architecture from the information
2764 provided. */
2765 gdbarch *gdbarch
2766 = gdbarch_alloc (&info, gdbarch_tdep_up (new csky_gdbarch_tdep));
2767 csky_gdbarch_tdep *tdep = gdbarch_tdep<csky_gdbarch_tdep> (gdbarch);
2768
2769 tdep->fpu_abi = fpu_abi;
2770 tdep->vdsp_version = vdsp_version;
2771 tdep->fpu_hardfp = fpu_hardfp;
2772
2773 if (tdesc_data != NULL)
2774 {
2775 if ((has_vr0 == CSKY_FULL16_ONEHOT_VALUE)
2776 && (has_fr16 == CSKY_FULL16_ONEHOT_VALUE))
2777 {
2778 tdep->has_vr0 = 1;
2779 tdep->fv_pseudo_registers_count = 128;
2780 }
2781 else if ((has_vr0 == CSKY_FULL16_ONEHOT_VALUE)
2782 && (has_fr16 != CSKY_FULL16_ONEHOT_VALUE))
2783 {
2784 tdep->has_vr0 = 1;
2785 tdep->fv_pseudo_registers_count = 64;
2786 }
2787 else if ((has_fr0 == CSKY_FULL16_ONEHOT_VALUE)
2788 && (has_vr0 != CSKY_FULL16_ONEHOT_VALUE))
2789 {
2790 tdep->has_vr0 = 0;
2791 tdep->fv_pseudo_registers_count = 64;
2792 }
2793 else
2794 {
2795 tdep->has_vr0 = 0;
2796 tdep->fv_pseudo_registers_count = 0;
2797 }
2798 }
2799 else
2800 {
2801 tdep->has_vr0 = 1;
2802 tdep->fv_pseudo_registers_count = 64;
2803 }
2804
2805 /* Target data types. */
2806 set_gdbarch_ptr_bit (gdbarch, 32);
2807 set_gdbarch_addr_bit (gdbarch, 32);
2808 set_gdbarch_short_bit (gdbarch, 16);
2809 set_gdbarch_int_bit (gdbarch, 32);
2810 set_gdbarch_long_bit (gdbarch, 32);
2811 set_gdbarch_long_long_bit (gdbarch, 64);
2812 set_gdbarch_float_bit (gdbarch, 32);
2813 set_gdbarch_double_bit (gdbarch, 64);
2814 set_gdbarch_float_format (gdbarch, floatformats_ieee_single);
2815 set_gdbarch_double_format (gdbarch, floatformats_ieee_double);
2816
2817 /* Information about the target architecture. */
2818 set_gdbarch_return_value (gdbarch, csky_return_value);
2819 set_gdbarch_breakpoint_kind_from_pc (gdbarch, csky_breakpoint_kind_from_pc);
2820 set_gdbarch_sw_breakpoint_from_kind (gdbarch, csky_sw_breakpoint_from_kind);
2821
2822 /* Register architecture. */
2823 set_gdbarch_num_regs (gdbarch, CSKY_NUM_REGS);
2824 set_gdbarch_pc_regnum (gdbarch, CSKY_PC_REGNUM);
2825 set_gdbarch_sp_regnum (gdbarch, CSKY_SP_REGNUM);
2826 set_gdbarch_register_name (gdbarch, csky_register_name);
2827 set_gdbarch_register_type (gdbarch, csky_register_type);
2828 set_gdbarch_read_pc (gdbarch, csky_read_pc);
2829 set_gdbarch_write_pc (gdbarch, csky_write_pc);
2830 csky_add_reggroups (gdbarch);
2831 set_gdbarch_register_reggroup_p (gdbarch, csky_register_reggroup_p);
2832 set_gdbarch_stab_reg_to_regnum (gdbarch, csky_dwarf_reg_to_regnum);
2833 set_gdbarch_dwarf2_reg_to_regnum (gdbarch, csky_dwarf_reg_to_regnum);
2834 dwarf2_frame_set_init_reg (gdbarch, csky_dwarf2_frame_init_reg);
2835
2836 /* Functions to analyze frames. */
2837 frame_base_set_default (gdbarch, &csky_frame_base);
2838 set_gdbarch_skip_prologue (gdbarch, csky_skip_prologue);
2839 set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
2840 set_gdbarch_frame_align (gdbarch, csky_frame_align);
2841 set_gdbarch_stack_frame_destroyed_p (gdbarch, csky_stack_frame_destroyed_p);
2842
2843 /* Functions handling dummy frames. */
2844 set_gdbarch_push_dummy_call (gdbarch, csky_push_dummy_call);
2845
2846 /* Frame unwinders. Use DWARF debug info if available,
2847 otherwise use our own unwinder. */
2848 dwarf2_append_unwinders (gdbarch);
2849 frame_unwind_append_unwinder (gdbarch, &csky_stub_unwind);
2850 frame_unwind_append_unwinder (gdbarch, &csky_unwind_cache);
2851
2852 /* Hook in ABI-specific overrides, if they have been registered. */
2853 gdbarch_init_osabi (info, gdbarch);
2854
2855 /* Support simple overlay manager. */
2856 set_gdbarch_overlay_update (gdbarch, simple_overlay_update);
2857 set_gdbarch_char_signed (gdbarch, 0);
2858
2859 if (tdesc_data != nullptr)
2860 {
2861 set_gdbarch_num_regs (gdbarch, (num_regs + 1));
2862 tdesc_use_registers (gdbarch, info.target_desc, std::move (tdesc_data));
2863 set_gdbarch_register_type (gdbarch, csky_register_type);
2864 set_gdbarch_register_reggroup_p (gdbarch,
2865 csky_register_reggroup_p);
2866 }
2867
2868 if (tdep->fv_pseudo_registers_count)
2869 {
2870 set_gdbarch_num_pseudo_regs (gdbarch,
2871 tdep->fv_pseudo_registers_count);
2872 set_gdbarch_pseudo_register_read (gdbarch,
2873 csky_pseudo_register_read);
2874 set_gdbarch_deprecated_pseudo_register_write
2875 (gdbarch, csky_pseudo_register_write);
2876 set_tdesc_pseudo_register_name (gdbarch, csky_pseudo_register_name);
2877 }
2878
2879 return gdbarch;
2880 }
2881
2882 void _initialize_csky_tdep ();
2883 void
2884 _initialize_csky_tdep ()
2885 {
2886
2887 gdbarch_register (bfd_arch_csky, csky_gdbarch_init);
2888
2889 csky_init_reggroup ();
2890
2891 /* Allow debugging this file's internals. */
2892 add_setshow_boolean_cmd ("csky", class_maintenance, &csky_debug,
2893 _("Set C-Sky debugging."),
2894 _("Show C-Sky debugging."),
2895 _("When on, C-Sky specific debugging is enabled."),
2896 NULL,
2897 NULL,
2898 &setdebuglist, &showdebuglist);
2899 }
The GNU Binutils are a collection of binary tools.