gdb/aarch64-linux-nat.c

   1 /* Native-dependent code for GNU/Linux AArch64.
   2
   3    Copyright (C) 2011-2024 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #include "inferior.h"
  23 #include "gdbcore.h"
  24 #include "regcache.h"
  25 #include "linux-nat.h"
  26 #include "target-descriptions.h"
  27 #include "auxv.h"
  28 #include "gdbcmd.h"
  29 #include "aarch64-nat.h"
  30 #include "aarch64-tdep.h"
  31 #include "aarch64-linux-tdep.h"
  32 #include "aarch32-linux-nat.h"
  33 #include "aarch32-tdep.h"
  34 #include "arch/arm.h"
  35 #include "nat/aarch64-linux.h"
  36 #include "nat/aarch64-linux-hw-point.h"
  37 #include "nat/aarch64-scalable-linux-ptrace.h"
  38
  39 #include "elf/external.h"
  40 #include "elf/common.h"
  41
  42 #include "nat/gdb_ptrace.h"
  43 #include <sys/utsname.h>
  44 #include <asm/ptrace.h>
  45
  46 #include "gregset.h"
  47 #include "linux-tdep.h"
  48 #include "arm-tdep.h"
  49
  50 /* Defines ps_err_e, struct ps_prochandle.  */
  51 #include "gdb_proc_service.h"
  52 #include "arch-utils.h"
  53
  54 #include "arch/aarch64-mte-linux.h"
  55
  56 #include "nat/aarch64-mte-linux-ptrace.h"
  57 #include "arch/aarch64-scalable-linux.h"
  58
  59 #include <string.h>
  60
  61 #ifndef TRAP_HWBKPT
  62 #define TRAP_HWBKPT 0x0004
  63 #endif
  64
  65 class aarch64_linux_nat_target final
  66   : public aarch64_nat_target<linux_nat_target>
  67 {
  68 public:
  69   /* Add our register access methods.  */
  70   void fetch_registers (struct regcache *, int) override;
  71   void store_registers (struct regcache *, int) override;
  72
  73   const struct target_desc *read_description () override;
  74
  75   /* Add our hardware breakpoint and watchpoint implementation.  */
  76   bool stopped_by_watchpoint () override;
  77   bool stopped_data_address (CORE_ADDR *) override;
  78
  79   int can_do_single_step () override;
  80
  81   /* Override the GNU/Linux inferior startup hook.  */
  82   void post_startup_inferior (ptid_t) override;
  83
  84   /* Override the GNU/Linux post attach hook.  */
  85   void post_attach (int pid) override;
  86
  87   /* These three defer to common nat/ code.  */
  88   void low_new_thread (struct lwp_info *lp) override
  89   { aarch64_linux_new_thread (lp); }
  90   void low_delete_thread (struct arch_lwp_info *lp) override
  91   { aarch64_linux_delete_thread (lp); }
  92   void low_prepare_to_resume (struct lwp_info *lp) override
  93   { aarch64_linux_prepare_to_resume (lp); }
  94
  95   void low_new_fork (struct lwp_info *parent, pid_t child_pid) override;
  96   void low_forget_process (pid_t pid) override;
  97
  98   /* Add our siginfo layout converter.  */
  99   bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction)
 100     override;
 101
 102   struct gdbarch *thread_architecture (ptid_t) override;
 103
 104   bool supports_memory_tagging () override;
 105
 106   /* Read memory allocation tags from memory via PTRACE.  */
 107   bool fetch_memtags (CORE_ADDR address, size_t len,
 108                       gdb::byte_vector &tags, int type) override;
 109
 110   /* Write allocation tags to memory via PTRACE.  */
 111   bool store_memtags (CORE_ADDR address, size_t len,
 112                       const gdb::byte_vector &tags, int type) override;
 113   /* Check if an address is tagged.  */
 114   bool is_address_tagged (gdbarch *gdbarch, CORE_ADDR address) override;
 115 };
 116
 117 static aarch64_linux_nat_target the_aarch64_linux_nat_target;
 118
 119 /* Called whenever GDB is no longer debugging process PID.  It deletes
 120    data structures that keep track of debug register state.  */
 121
 122 void
 123 aarch64_linux_nat_target::low_forget_process (pid_t pid)
 124 {
 125   aarch64_remove_debug_reg_state (pid);
 126 }
 127
 128 /* Fill GDB's register array with the general-purpose register values
 129    from the current thread.  */
 130
 131 static void
 132 fetch_gregs_from_thread (struct regcache *regcache)
 133 {
 134   int ret, tid;
 135   struct gdbarch *gdbarch = regcache->arch ();
 136   elf_gregset_t regs;
 137   struct iovec iovec;
 138
 139   /* Make sure REGS can hold all registers contents on both aarch64
 140      and arm.  */
 141   static_assert (sizeof (regs) >= 18 * 4);
 142
 143   tid = regcache->ptid ().lwp ();
 144
 145   iovec.iov_base = &regs;
 146   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 147     iovec.iov_len = 18 * 4;
 148   else
 149     iovec.iov_len = sizeof (regs);
 150
 151   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
 152   if (ret < 0)
 153     perror_with_name (_("Unable to fetch general registers"));
 154
 155   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 156     aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1);
 157   else
 158     {
 159       int regno;
 160
 161       for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
 162         regcache->raw_supply (regno, &regs[regno - AARCH64_X0_REGNUM]);
 163     }
 164 }
 165
 166 /* Store to the current thread the valid general-purpose register
 167    values in the GDB's register array.  */
 168
 169 static void
 170 store_gregs_to_thread (const struct regcache *regcache)
 171 {
 172   int ret, tid;
 173   elf_gregset_t regs;
 174   struct iovec iovec;
 175   struct gdbarch *gdbarch = regcache->arch ();
 176
 177   /* Make sure REGS can hold all registers contents on both aarch64
 178      and arm.  */
 179   static_assert (sizeof (regs) >= 18 * 4);
 180   tid = regcache->ptid ().lwp ();
 181
 182   iovec.iov_base = &regs;
 183   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 184     iovec.iov_len = 18 * 4;
 185   else
 186     iovec.iov_len = sizeof (regs);
 187
 188   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
 189   if (ret < 0)
 190     perror_with_name (_("Unable to fetch general registers"));
 191
 192   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 193     aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1);
 194   else
 195     {
 196       int regno;
 197
 198       for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
 199         if (REG_VALID == regcache->get_register_status (regno))
 200           regcache->raw_collect (regno, &regs[regno - AARCH64_X0_REGNUM]);
 201     }
 202
 203   ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
 204   if (ret < 0)
 205     perror_with_name (_("Unable to store general registers"));
 206 }
 207
 208 /* Fill GDB's register array with the fp/simd register values
 209    from the current thread.  */
 210
 211 static void
 212 fetch_fpregs_from_thread (struct regcache *regcache)
 213 {
 214   int ret, tid;
 215   elf_fpregset_t regs;
 216   struct iovec iovec;
 217   struct gdbarch *gdbarch = regcache->arch ();
 218
 219   /* Make sure REGS can hold all VFP registers contents on both aarch64
 220      and arm.  */
 221   static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
 222
 223   tid = regcache->ptid ().lwp ();
 224
 225   iovec.iov_base = &regs;
 226
 227   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 228     {
 229       iovec.iov_len = ARM_VFP3_REGS_SIZE;
 230
 231       ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 232       if (ret < 0)
 233         perror_with_name (_("Unable to fetch VFP registers"));
 234
 235       aarch32_vfp_regcache_supply (regcache, (gdb_byte *) &regs, 32);
 236     }
 237   else
 238     {
 239       int regno;
 240
 241       iovec.iov_len = sizeof (regs);
 242
 243       ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
 244       if (ret < 0)
 245         perror_with_name (_("Unable to fetch vFP/SIMD registers"));
 246
 247       for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
 248         regcache->raw_supply (regno, &regs.vregs[regno - AARCH64_V0_REGNUM]);
 249
 250       regcache->raw_supply (AARCH64_FPSR_REGNUM, &regs.fpsr);
 251       regcache->raw_supply (AARCH64_FPCR_REGNUM, &regs.fpcr);
 252     }
 253 }
 254
 255 /* Store to the current thread the valid fp/simd register
 256    values in the GDB's register array.  */
 257
 258 static void
 259 store_fpregs_to_thread (const struct regcache *regcache)
 260 {
 261   int ret, tid;
 262   elf_fpregset_t regs;
 263   struct iovec iovec;
 264   struct gdbarch *gdbarch = regcache->arch ();
 265
 266   /* Make sure REGS can hold all VFP registers contents on both aarch64
 267      and arm.  */
 268   static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
 269   tid = regcache->ptid ().lwp ();
 270
 271   iovec.iov_base = &regs;
 272
 273   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 274     {
 275       iovec.iov_len = ARM_VFP3_REGS_SIZE;
 276
 277       ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 278       if (ret < 0)
 279         perror_with_name (_("Unable to fetch VFP registers"));
 280
 281       aarch32_vfp_regcache_collect (regcache, (gdb_byte *) &regs, 32);
 282     }
 283   else
 284     {
 285       int regno;
 286
 287       iovec.iov_len = sizeof (regs);
 288
 289       ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
 290       if (ret < 0)
 291         perror_with_name (_("Unable to fetch FP/SIMD registers"));
 292
 293       for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
 294         if (REG_VALID == regcache->get_register_status (regno))
 295           regcache->raw_collect
 296             (regno, (char *) &regs.vregs[regno - AARCH64_V0_REGNUM]);
 297
 298       if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM))
 299         regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) &regs.fpsr);
 300       if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM))
 301         regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) &regs.fpcr);
 302     }
 303
 304   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 305     {
 306       ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec);
 307       if (ret < 0)
 308         perror_with_name (_("Unable to store VFP registers"));
 309     }
 310   else
 311     {
 312       ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
 313       if (ret < 0)
 314         perror_with_name (_("Unable to store FP/SIMD registers"));
 315     }
 316 }
 317
 318 /* Fill GDB's REGCACHE with the valid SVE register values from the thread
 319    associated with REGCACHE.
 320
 321    This function handles reading data from SVE or SSVE states, depending
 322    on which state is active at the moment.  */
 323
 324 static void
 325 fetch_sveregs_from_thread (struct regcache *regcache)
 326 {
 327   /* Fetch SVE state from the thread and copy it into the register cache.  */
 328   aarch64_sve_regs_copy_to_reg_buf (regcache->ptid ().lwp (), regcache);
 329 }
 330
 331 /* Store the valid SVE register values from GDB's REGCACHE to the thread
 332    associated with REGCACHE.
 333
 334    This function handles writing data to SVE or SSVE states, depending
 335    on which state is active at the moment.  */
 336
 337 static void
 338 store_sveregs_to_thread (struct regcache *regcache)
 339 {
 340   /* Fetch SVE state from the register cache and update the thread TID with
 341      it.  */
 342   aarch64_sve_regs_copy_from_reg_buf (regcache->ptid ().lwp (), regcache);
 343 }
 344
 345 /* Fill GDB's REGCACHE with the ZA register set contents from the
 346    thread associated with REGCACHE.  If there is no active ZA register state,
 347    make the ZA register contents zero.  */
 348
 349 static void
 350 fetch_za_from_thread (struct regcache *regcache)
 351 {
 352   aarch64_gdbarch_tdep *tdep
 353     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 354
 355   /* Read ZA state from the thread to the register cache.  */
 356   aarch64_za_regs_copy_to_reg_buf (regcache->ptid ().lwp (),
 357                                    regcache,
 358                                    tdep->sme_za_regnum,
 359                                    tdep->sme_svg_regnum,
 360                                    tdep->sme_svcr_regnum);
 361 }
 362
 363 /* Store the NT_ARM_ZA register set contents from GDB's REGCACHE to the thread
 364    associated with REGCACHE.  */
 365
 366 static void
 367 store_za_to_thread (struct regcache *regcache)
 368 {
 369   aarch64_gdbarch_tdep *tdep
 370     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 371
 372   /* Write ZA state from the register cache to the thread.  */
 373   aarch64_za_regs_copy_from_reg_buf (regcache->ptid ().lwp (),
 374                                      regcache,
 375                                      tdep->sme_za_regnum,
 376                                      tdep->sme_svg_regnum,
 377                                      tdep->sme_svcr_regnum);
 378 }
 379
 380 /* Fill GDB's REGCACHE with the ZT register set contents from the
 381    thread associated with REGCACHE.  If there is no active ZA register state,
 382    make the ZT register contents zero.  */
 383
 384 static void
 385 fetch_zt_from_thread (struct regcache *regcache)
 386 {
 387   aarch64_gdbarch_tdep *tdep
 388     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 389
 390   /* Read ZT state from the thread to the register cache.  */
 391   aarch64_zt_regs_copy_to_reg_buf (regcache->ptid ().lwp (),
 392                                    regcache,
 393                                    tdep->sme2_zt0_regnum);
 394 }
 395
 396 /* Store the NT_ARM_ZT register set contents from GDB's REGCACHE to the
 397    thread associated with REGCACHE.  */
 398
 399 static void
 400 store_zt_to_thread (struct regcache *regcache)
 401 {
 402   aarch64_gdbarch_tdep *tdep
 403     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 404
 405   /* Write ZT state from the register cache to the thread.  */
 406   aarch64_zt_regs_copy_from_reg_buf (regcache->ptid ().lwp (),
 407                                      regcache,
 408                                      tdep->sme2_zt0_regnum);
 409 }
 410
 411 /* Fill GDB's register array with the pointer authentication mask values from
 412    the current thread.  */
 413
 414 static void
 415 fetch_pauth_masks_from_thread (struct regcache *regcache)
 416 {
 417   aarch64_gdbarch_tdep *tdep
 418     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 419   int ret;
 420   struct iovec iovec;
 421   uint64_t pauth_regset[2] = {0, 0};
 422   int tid = regcache->ptid ().lwp ();
 423
 424   iovec.iov_base = &pauth_regset;
 425   iovec.iov_len = sizeof (pauth_regset);
 426
 427   ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec);
 428   if (ret != 0)
 429     perror_with_name (_("unable to fetch pauth registers"));
 430
 431   regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base),
 432                         &pauth_regset[0]);
 433   regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base),
 434                         &pauth_regset[1]);
 435 }
 436
 437 /* Fill GDB's register array with the MTE register values from
 438    the current thread.  */
 439
 440 static void
 441 fetch_mteregs_from_thread (struct regcache *regcache)
 442 {
 443   aarch64_gdbarch_tdep *tdep
 444     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 445   int regno = tdep->mte_reg_base;
 446
 447   gdb_assert (regno != -1);
 448
 449   uint64_t tag_ctl = 0;
 450   struct iovec iovec;
 451
 452   iovec.iov_base = &tag_ctl;
 453   iovec.iov_len = sizeof (tag_ctl);
 454
 455   int tid = get_ptrace_pid (regcache->ptid ());
 456   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
 457       perror_with_name (_("unable to fetch MTE registers"));
 458
 459   regcache->raw_supply (regno, &tag_ctl);
 460 }
 461
 462 /* Store to the current thread the valid MTE register set in the GDB's
 463    register array.  */
 464
 465 static void
 466 store_mteregs_to_thread (struct regcache *regcache)
 467 {
 468   aarch64_gdbarch_tdep *tdep
 469     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 470   int regno = tdep->mte_reg_base;
 471
 472   gdb_assert (regno != -1);
 473
 474   uint64_t tag_ctl = 0;
 475
 476   if (REG_VALID != regcache->get_register_status (regno))
 477     return;
 478
 479   regcache->raw_collect (regno, (char *) &tag_ctl);
 480
 481   struct iovec iovec;
 482
 483   iovec.iov_base = &tag_ctl;
 484   iovec.iov_len = sizeof (tag_ctl);
 485
 486   int tid = get_ptrace_pid (regcache->ptid ());
 487   if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
 488     perror_with_name (_("unable to store MTE registers"));
 489 }
 490
 491 /* Fill GDB's register array with the TLS register values from
 492    the current thread.  */
 493
 494 static void
 495 fetch_tlsregs_from_thread (struct regcache *regcache)
 496 {
 497   aarch64_gdbarch_tdep *tdep
 498     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 499   int regno = tdep->tls_regnum_base;
 500
 501   gdb_assert (regno != -1);
 502   gdb_assert (tdep->tls_register_count > 0);
 503
 504   uint64_t tpidrs[tdep->tls_register_count];
 505   memset(tpidrs, 0, sizeof(tpidrs));
 506
 507   struct iovec iovec;
 508   iovec.iov_base = tpidrs;
 509   iovec.iov_len = sizeof (tpidrs);
 510
 511   int tid = get_ptrace_pid (regcache->ptid ());
 512   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
 513       perror_with_name (_("unable to fetch TLS registers"));
 514
 515   for (int i = 0; i < tdep->tls_register_count; i++)
 516     regcache->raw_supply (regno + i, &tpidrs[i]);
 517 }
 518
 519 /* Store to the current thread the valid TLS register set in GDB's
 520    register array.  */
 521
 522 static void
 523 store_tlsregs_to_thread (struct regcache *regcache)
 524 {
 525   aarch64_gdbarch_tdep *tdep
 526     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 527   int regno = tdep->tls_regnum_base;
 528
 529   gdb_assert (regno != -1);
 530   gdb_assert (tdep->tls_register_count > 0);
 531
 532   uint64_t tpidrs[tdep->tls_register_count];
 533   memset(tpidrs, 0, sizeof(tpidrs));
 534
 535   for (int i = 0; i < tdep->tls_register_count; i++)
 536     {
 537       if (REG_VALID != regcache->get_register_status (regno + i))
 538         continue;
 539
 540       regcache->raw_collect (regno + i, (char *) &tpidrs[i]);
 541     }
 542
 543   struct iovec iovec;
 544   iovec.iov_base = &tpidrs;
 545   iovec.iov_len = sizeof (tpidrs);
 546
 547   int tid = get_ptrace_pid (regcache->ptid ());
 548   if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
 549     perror_with_name (_("unable to store TLS register"));
 550 }
 551
 552 /* The AArch64 version of the "fetch_registers" target_ops method.  Fetch
 553    REGNO from the target and place the result into REGCACHE.  */
 554
 555 static void
 556 aarch64_fetch_registers (struct regcache *regcache, int regno)
 557 {
 558   aarch64_gdbarch_tdep *tdep
 559     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 560
 561   /* Do we need to fetch all registers?  */
 562   if (regno == -1)
 563     {
 564       fetch_gregs_from_thread (regcache);
 565
 566       /* We attempt to fetch SVE registers if there is support for either
 567          SVE or SME (due to the SSVE state of SME).  */
 568       if (tdep->has_sve () || tdep->has_sme ())
 569         fetch_sveregs_from_thread (regcache);
 570       else
 571         fetch_fpregs_from_thread (regcache);
 572
 573       if (tdep->has_pauth ())
 574         fetch_pauth_masks_from_thread (regcache);
 575
 576       if (tdep->has_mte ())
 577         fetch_mteregs_from_thread (regcache);
 578
 579       if (tdep->has_tls ())
 580         fetch_tlsregs_from_thread (regcache);
 581
 582       if (tdep->has_sme ())
 583         fetch_za_from_thread (regcache);
 584
 585       if (tdep->has_sme2 ())
 586         fetch_zt_from_thread (regcache);
 587     }
 588   /* General purpose register?  */
 589   else if (regno < AARCH64_V0_REGNUM)
 590     fetch_gregs_from_thread (regcache);
 591   /* SVE register?  */
 592   else if ((tdep->has_sve () || tdep->has_sme ())
 593            && regno <= AARCH64_SVE_VG_REGNUM)
 594     fetch_sveregs_from_thread (regcache);
 595   /* FPSIMD register?  */
 596   else if (regno <= AARCH64_FPCR_REGNUM)
 597     fetch_fpregs_from_thread (regcache);
 598   /* PAuth register?  */
 599   else if (tdep->has_pauth ()
 600            && (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
 601                || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)))
 602     fetch_pauth_masks_from_thread (regcache);
 603   /* SME register?  */
 604   else if (tdep->has_sme () && regno >= tdep->sme_reg_base
 605            && regno < tdep->sme_reg_base + 3)
 606     fetch_za_from_thread (regcache);
 607   /* SME2 register?  */
 608   else if (tdep->has_sme2 () && regno == tdep->sme2_zt0_regnum)
 609     fetch_zt_from_thread (regcache);
 610   /* MTE register?  */
 611   else if (tdep->has_mte ()
 612            && (regno == tdep->mte_reg_base))
 613     fetch_mteregs_from_thread (regcache);
 614   /* TLS register?  */
 615   else if (tdep->has_tls ()
 616            && regno >= tdep->tls_regnum_base
 617            && regno < tdep->tls_regnum_base + tdep->tls_register_count)
 618     fetch_tlsregs_from_thread (regcache);
 619 }
 620
 621 /* A version of the "fetch_registers" target_ops method used when running
 622    32-bit ARM code on an AArch64 target.  Fetch REGNO from the target and
 623    place the result into REGCACHE.  */
 624
 625 static void
 626 aarch32_fetch_registers (struct regcache *regcache, int regno)
 627 {
 628   arm_gdbarch_tdep *tdep
 629     = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ());
 630
 631   if (regno == -1)
 632     {
 633       fetch_gregs_from_thread (regcache);
 634       if (tdep->vfp_register_count > 0)
 635         fetch_fpregs_from_thread (regcache);
 636     }
 637   else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
 638     fetch_gregs_from_thread (regcache);
 639   else if (tdep->vfp_register_count > 0
 640            && regno >= ARM_D0_REGNUM
 641            && (regno < ARM_D0_REGNUM + tdep->vfp_register_count
 642                || regno == ARM_FPSCR_REGNUM))
 643     fetch_fpregs_from_thread (regcache);
 644 }
 645
 646 /* Implement the "fetch_registers" target_ops method.  */
 647
 648 void
 649 aarch64_linux_nat_target::fetch_registers (struct regcache *regcache,
 650                                            int regno)
 651 {
 652   if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
 653     aarch32_fetch_registers (regcache, regno);
 654   else
 655     aarch64_fetch_registers (regcache, regno);
 656 }
 657
 658 /* The AArch64 version of the "store_registers" target_ops method.  Copy
 659    the value of register REGNO from REGCACHE into the the target.  */
 660
 661 static void
 662 aarch64_store_registers (struct regcache *regcache, int regno)
 663 {
 664   aarch64_gdbarch_tdep *tdep
 665     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 666
 667   /* Do we need to store all registers?  */
 668   if (regno == -1)
 669     {
 670       store_gregs_to_thread (regcache);
 671
 672       /* We attempt to store SVE registers if there is support for either
 673          SVE or SME (due to the SSVE state of SME).  */
 674       if (tdep->has_sve () || tdep->has_sme ())
 675         store_sveregs_to_thread (regcache);
 676       else
 677         store_fpregs_to_thread (regcache);
 678
 679       if (tdep->has_mte ())
 680         store_mteregs_to_thread (regcache);
 681
 682       if (tdep->has_tls ())
 683         store_tlsregs_to_thread (regcache);
 684
 685       if (tdep->has_sme ())
 686         store_za_to_thread (regcache);
 687
 688       if (tdep->has_sme2 ())
 689         store_zt_to_thread (regcache);
 690     }
 691   /* General purpose register?  */
 692   else if (regno < AARCH64_V0_REGNUM)
 693     store_gregs_to_thread (regcache);
 694   /* SVE register?  */
 695   else if ((tdep->has_sve () || tdep->has_sme ())
 696            && regno <= AARCH64_SVE_VG_REGNUM)
 697     store_sveregs_to_thread (regcache);
 698   /* FPSIMD register?  */
 699   else if (regno <= AARCH64_FPCR_REGNUM)
 700     store_fpregs_to_thread (regcache);
 701   /* SME register?  */
 702   else if (tdep->has_sme () && regno >= tdep->sme_reg_base
 703            && regno < tdep->sme_reg_base + 3)
 704     store_za_to_thread (regcache);
 705   else if (tdep->has_sme2 () && regno == tdep->sme2_zt0_regnum)
 706     store_zt_to_thread (regcache);
 707   /* MTE register?  */
 708   else if (tdep->has_mte ()
 709            && (regno == tdep->mte_reg_base))
 710     store_mteregs_to_thread (regcache);
 711   /* TLS register?  */
 712   else if (tdep->has_tls ()
 713            && regno >= tdep->tls_regnum_base
 714            && regno < tdep->tls_regnum_base + tdep->tls_register_count)
 715     store_tlsregs_to_thread (regcache);
 716
 717   /* PAuth registers are read-only.  */
 718 }
 719
 720 /* A version of the "store_registers" target_ops method used when running
 721    32-bit ARM code on an AArch64 target.  Copy the value of register REGNO
 722    from REGCACHE into the the target.  */
 723
 724 static void
 725 aarch32_store_registers (struct regcache *regcache, int regno)
 726 {
 727   arm_gdbarch_tdep *tdep
 728     = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ());
 729
 730   if (regno == -1)
 731     {
 732       store_gregs_to_thread (regcache);
 733       if (tdep->vfp_register_count > 0)
 734         store_fpregs_to_thread (regcache);
 735     }
 736   else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
 737     store_gregs_to_thread (regcache);
 738   else if (tdep->vfp_register_count > 0
 739            && regno >= ARM_D0_REGNUM
 740            && (regno < ARM_D0_REGNUM + tdep->vfp_register_count
 741                || regno == ARM_FPSCR_REGNUM))
 742     store_fpregs_to_thread (regcache);
 743 }
 744
 745 /* Implement the "store_registers" target_ops method.  */
 746
 747 void
 748 aarch64_linux_nat_target::store_registers (struct regcache *regcache,
 749                                            int regno)
 750 {
 751   if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
 752     aarch32_store_registers (regcache, regno);
 753   else
 754     aarch64_store_registers (regcache, regno);
 755 }
 756
 757 /* Fill register REGNO (if it is a general-purpose register) in
 758    *GREGSETPS with the value in GDB's register array.  If REGNO is -1,
 759    do this for all registers.  */
 760
 761 void
 762 fill_gregset (const struct regcache *regcache,
 763               gdb_gregset_t *gregsetp, int regno)
 764 {
 765   regcache_collect_regset (&aarch64_linux_gregset, regcache,
 766                            regno, (gdb_byte *) gregsetp,
 767                            AARCH64_LINUX_SIZEOF_GREGSET);
 768 }
 769
 770 /* Fill GDB's register array with the general-purpose register values
 771    in *GREGSETP.  */
 772
 773 void
 774 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
 775 {
 776   regcache_supply_regset (&aarch64_linux_gregset, regcache, -1,
 777                           (const gdb_byte *) gregsetp,
 778                           AARCH64_LINUX_SIZEOF_GREGSET);
 779 }
 780
 781 /* Fill register REGNO (if it is a floating-point register) in
 782    *FPREGSETP with the value in GDB's register array.  If REGNO is -1,
 783    do this for all registers.  */
 784
 785 void
 786 fill_fpregset (const struct regcache *regcache,
 787                gdb_fpregset_t *fpregsetp, int regno)
 788 {
 789   regcache_collect_regset (&aarch64_linux_fpregset, regcache,
 790                            regno, (gdb_byte *) fpregsetp,
 791                            AARCH64_LINUX_SIZEOF_FPREGSET);
 792 }
 793
 794 /* Fill GDB's register array with the floating-point register values
 795    in *FPREGSETP.  */
 796
 797 void
 798 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
 799 {
 800   regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1,
 801                           (const gdb_byte *) fpregsetp,
 802                           AARCH64_LINUX_SIZEOF_FPREGSET);
 803 }
 804
 805 /* linux_nat_new_fork hook.   */
 806
 807 void
 808 aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent,
 809                                         pid_t child_pid)
 810 {
 811   pid_t parent_pid;
 812   struct aarch64_debug_reg_state *parent_state;
 813   struct aarch64_debug_reg_state *child_state;
 814
 815   /* NULL means no watchpoint has ever been set in the parent.  In
 816      that case, there's nothing to do.  */
 817   if (parent->arch_private == NULL)
 818     return;
 819
 820   /* GDB core assumes the child inherits the watchpoints/hw
 821      breakpoints of the parent, and will remove them all from the
 822      forked off process.  Copy the debug registers mirrors into the
 823      new process so that all breakpoints and watchpoints can be
 824      removed together.  */
 825
 826   parent_pid = parent->ptid.pid ();
 827   parent_state = aarch64_get_debug_reg_state (parent_pid);
 828   child_state = aarch64_get_debug_reg_state (child_pid);
 829   *child_state = *parent_state;
 830 }
 831 \f
 832
 833 /* Called by libthread_db.  Returns a pointer to the thread local
 834    storage (or its descriptor).  */
 835
 836 ps_err_e
 837 ps_get_thread_area (struct ps_prochandle *ph,
 838                     lwpid_t lwpid, int idx, void **base)
 839 {
 840   gdbarch *arch = current_inferior ()->arch ();
 841   int is_64bit_p = (gdbarch_bfd_arch_info (arch)->bits_per_word == 64);
 842
 843   return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p);
 844 }
 845 \f
 846
 847 /* Implement the virtual inf_ptrace_target::post_startup_inferior method.  */
 848
 849 void
 850 aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid)
 851 {
 852   low_forget_process (ptid.pid ());
 853   aarch64_linux_get_debug_reg_capacity (ptid.pid ());
 854   linux_nat_target::post_startup_inferior (ptid);
 855 }
 856
 857 /* Implement the "post_attach" target_ops method.  */
 858
 859 void
 860 aarch64_linux_nat_target::post_attach (int pid)
 861 {
 862   low_forget_process (pid);
 863   /* Set the hardware debug register capacity.  If
 864      aarch64_linux_get_debug_reg_capacity is not called
 865      (as it is in aarch64_linux_child_post_startup_inferior) then
 866      software watchpoints will be used instead of hardware
 867      watchpoints when attaching to a target.  */
 868   aarch64_linux_get_debug_reg_capacity (pid);
 869   linux_nat_target::post_attach (pid);
 870 }
 871
 872 /* Implement the "read_description" target_ops method.  */
 873
 874 const struct target_desc *
 875 aarch64_linux_nat_target::read_description ()
 876 {
 877   int ret, tid;
 878   gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
 879   struct iovec iovec;
 880
 881   if (inferior_ptid == null_ptid)
 882     return this->beneath ()->read_description ();
 883
 884   tid = inferior_ptid.pid ();
 885
 886   iovec.iov_base = regbuf;
 887   iovec.iov_len = ARM_VFP3_REGS_SIZE;
 888
 889   ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 890   if (ret == 0)
 891     return aarch32_read_description (false);
 892
 893   CORE_ADDR hwcap = linux_get_hwcap ();
 894   CORE_ADDR hwcap2 = linux_get_hwcap2 ();
 895
 896   aarch64_features features;
 897   /* SVE/SSVE check.  Reading VQ may return either the regular vector length
 898      or the streaming vector length, depending on whether streaming mode is
 899      active or not.  */
 900   features.vq = aarch64_sve_get_vq (tid);
 901   features.pauth = hwcap & AARCH64_HWCAP_PACA;
 902   features.mte = hwcap2 & HWCAP2_MTE;
 903   features.tls = aarch64_tls_register_count (tid);
 904   /* SME feature check.  */
 905   features.svq = aarch64_za_get_svq (tid);
 906
 907   /* Check for SME2 support.  */
 908   if ((hwcap2 & HWCAP2_SME2) || (hwcap2 & HWCAP2_SME2P1))
 909     features.sme2 = supports_zt_registers (tid);
 910
 911   return aarch64_read_description (features);
 912 }
 913
 914 /* Convert a native/host siginfo object, into/from the siginfo in the
 915    layout of the inferiors' architecture.  Returns true if any
 916    conversion was done; false otherwise.  If DIRECTION is 1, then copy
 917    from INF to NATIVE.  If DIRECTION is 0, copy from NATIVE to
 918    INF.  */
 919
 920 bool
 921 aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf,
 922                                              int direction)
 923 {
 924   struct gdbarch *gdbarch = get_frame_arch (get_current_frame ());
 925
 926   /* Is the inferior 32-bit?  If so, then do fixup the siginfo
 927      object.  */
 928   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 929     {
 930       if (direction == 0)
 931         aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf,
 932                                              native);
 933       else
 934         aarch64_siginfo_from_compat_siginfo (native,
 935                                              (struct compat_siginfo *) inf);
 936
 937       return true;
 938     }
 939
 940   return false;
 941 }
 942
 943 /* Implement the "stopped_data_address" target_ops method.  */
 944
 945 bool
 946 aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
 947 {
 948   siginfo_t siginfo;
 949   struct aarch64_debug_reg_state *state;
 950
 951   if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
 952     return false;
 953
 954   /* This must be a hardware breakpoint.  */
 955   if (siginfo.si_signo != SIGTRAP
 956       || (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
 957     return false;
 958
 959   /* Make sure to ignore the top byte, otherwise we may not recognize a
 960      hardware watchpoint hit.  The stopped data addresses coming from the
 961      kernel can potentially be tagged addresses.  */
 962   struct gdbarch *gdbarch = thread_architecture (inferior_ptid);
 963   const CORE_ADDR addr_trap
 964     = gdbarch_remove_non_address_bits (gdbarch, (CORE_ADDR) siginfo.si_addr);
 965
 966   /* Check if the address matches any watched address.  */
 967   state = aarch64_get_debug_reg_state (inferior_ptid.pid ());
 968   return aarch64_stopped_data_address (state, addr_trap, addr_p);
 969 }
 970
 971 /* Implement the "stopped_by_watchpoint" target_ops method.  */
 972
 973 bool
 974 aarch64_linux_nat_target::stopped_by_watchpoint ()
 975 {
 976   return stopped_data_address (nullptr);
 977 }
 978
 979 /* Implement the "can_do_single_step" target_ops method.  */
 980
 981 int
 982 aarch64_linux_nat_target::can_do_single_step ()
 983 {
 984   return 1;
 985 }
 986
 987 /* Implement the "thread_architecture" target_ops method.
 988
 989    Returns the gdbarch for the thread identified by PTID.  If the thread in
 990    question is a 32-bit ARM thread, then the architecture returned will be
 991    that of the process itself.
 992
 993    If the thread is an AArch64 thread then we need to check the current
 994    vector length; if the vector length has changed then we need to lookup a
 995    new gdbarch that matches the new vector length.  */
 996
 997 struct gdbarch *
 998 aarch64_linux_nat_target::thread_architecture (ptid_t ptid)
 999 {
1000   /* Find the current gdbarch the same way as process_stratum_target.  */
1001   inferior *inf = find_inferior_ptid (this, ptid);
1002   gdb_assert (inf != NULL);
1003
1004   /* If this is a 32-bit architecture, then this is ARM, not AArch64.
1005      There's no SVE vectors here, so just return the inferior
1006      architecture.  */
1007   if (gdbarch_bfd_arch_info (inf->arch ())->bits_per_word == 32)
1008     return inf->arch ();
1009
1010   /* Only return the inferior's gdbarch if both vq and svq match the ones in
1011      the tdep.  */
1012   aarch64_gdbarch_tdep *tdep
1013     = gdbarch_tdep<aarch64_gdbarch_tdep> (inf->arch ());
1014   uint64_t vq = aarch64_sve_get_vq (ptid.lwp ());
1015   uint64_t svq = aarch64_za_get_svq (ptid.lwp ());
1016   if (vq == tdep->vq && svq == tdep->sme_svq)
1017     return inf->arch ();
1018
1019   /* We reach here if any vector length for the thread is different from its
1020      value at process start.  Lookup gdbarch via info (potentially creating a
1021      new one) by using a target description that corresponds to the new vq/svq
1022      value and the current architecture features.  */
1023
1024   const struct target_desc *tdesc = gdbarch_target_desc (inf->arch ());
1025   aarch64_features features = aarch64_features_from_target_desc (tdesc);
1026   features.vq = vq;
1027   features.svq = svq;
1028
1029   /* Check for the SME2 feature.  */
1030   features.sme2 = supports_zt_registers (ptid.lwp ());
1031
1032   struct gdbarch_info info;
1033   info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64);
1034   info.target_desc = aarch64_read_description (features);
1035   return gdbarch_find_by_info (info);
1036 }
1037
1038 /* Implement the "supports_memory_tagging" target_ops method.  */
1039
1040 bool
1041 aarch64_linux_nat_target::supports_memory_tagging ()
1042 {
1043   return (linux_get_hwcap2 () & HWCAP2_MTE) != 0;
1044 }
1045
1046 /* Implement the "fetch_memtags" target_ops method.  */
1047
1048 bool
1049 aarch64_linux_nat_target::fetch_memtags (CORE_ADDR address, size_t len,
1050                                          gdb::byte_vector &tags, int type)
1051 {
1052   int tid = get_ptrace_pid (inferior_ptid);
1053
1054   /* Allocation tags?  */
1055   if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
1056     return aarch64_mte_fetch_memtags (tid, address, len, tags);
1057
1058   return false;
1059 }
1060
1061 /* Implement the "store_memtags" target_ops method.  */
1062
1063 bool
1064 aarch64_linux_nat_target::store_memtags (CORE_ADDR address, size_t len,
1065                                          const gdb::byte_vector &tags, int type)
1066 {
1067   int tid = get_ptrace_pid (inferior_ptid);
1068
1069   /* Allocation tags?  */
1070   if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
1071     return aarch64_mte_store_memtags (tid, address, len, tags);
1072
1073   return false;
1074 }
1075
1076 bool
1077 aarch64_linux_nat_target::is_address_tagged (gdbarch *gdbarch, CORE_ADDR address)
1078 {
1079   /* Here we take a detour going to linux-tdep layer to read the smaps file,
1080      because currently there isn't a better way to get that information to
1081      check if a given address is tagged or not.
1082
1083      In the future, if this check is made, for instance, available via PTRACE,
1084      it will be possible to drop the smaps path in favor of a PTRACE one for
1085      this check.  */
1086   return gdbarch_tagged_address_p (gdbarch, address);
1087 }
1088
1089 void _initialize_aarch64_linux_nat ();
1090 void
1091 _initialize_aarch64_linux_nat ()
1092 {
1093   aarch64_initialize_hw_point ();
1094
1095   /* Register the target.  */
1096   linux_target = &the_aarch64_linux_nat_target;
1097   add_inf_child_target (&the_aarch64_linux_nat_target);
1098 }