opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2024 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 typedef struct instr_info instr_info;
  43
  44 static bool dofloat (instr_info *, int);
  45 static int putop (instr_info *, const char *, int);
  46 static void oappend_with_style (instr_info *, const char *,
  47                                 enum disassembler_style);
  48
  49 static bool OP_E (instr_info *, int, int);
  50 static bool OP_E_memory (instr_info *, int, int);
  51 static bool OP_indirE (instr_info *, int, int);
  52 static bool OP_G (instr_info *, int, int);
  53 static bool OP_ST (instr_info *, int, int);
  54 static bool OP_STi (instr_info *, int, int);
  55 static bool OP_Skip_MODRM (instr_info *, int, int);
  56 static bool OP_REG (instr_info *, int, int);
  57 static bool OP_IMREG (instr_info *, int, int);
  58 static bool OP_I (instr_info *, int, int);
  59 static bool OP_I64 (instr_info *, int, int);
  60 static bool OP_sI (instr_info *, int, int);
  61 static bool OP_J (instr_info *, int, int);
  62 static bool OP_SEG (instr_info *, int, int);
  63 static bool OP_DIR (instr_info *, int, int);
  64 static bool OP_OFF (instr_info *, int, int);
  65 static bool OP_OFF64 (instr_info *, int, int);
  66 static bool OP_ESreg (instr_info *, int, int);
  67 static bool OP_DSreg (instr_info *, int, int);
  68 static bool OP_C (instr_info *, int, int);
  69 static bool OP_D (instr_info *, int, int);
  70 static bool OP_T (instr_info *, int, int);
  71 static bool OP_MMX (instr_info *, int, int);
  72 static bool OP_XMM (instr_info *, int, int);
  73 static bool OP_EM (instr_info *, int, int);
  74 static bool OP_EX (instr_info *, int, int);
  75 static bool OP_EMC (instr_info *, int,int);
  76 static bool OP_MXC (instr_info *, int,int);
  77 static bool OP_R (instr_info *, int, int);
  78 static bool OP_M (instr_info *, int, int);
  79 static bool OP_VEX (instr_info *, int, int);
  80 static bool OP_VexR (instr_info *, int, int);
  81 static bool OP_VexW (instr_info *, int, int);
  82 static bool OP_Rounding (instr_info *, int, int);
  83 static bool OP_REG_VexI4 (instr_info *, int, int);
  84 static bool OP_VexI4 (instr_info *, int, int);
  85 static bool OP_0f07 (instr_info *, int, int);
  86 static bool OP_Monitor (instr_info *, int, int);
  87 static bool OP_Mwait (instr_info *, int, int);
  88
  89 static bool PCLMUL_Fixup (instr_info *, int, int);
  90 static bool VPCMP_Fixup (instr_info *, int, int);
  91 static bool VPCOM_Fixup (instr_info *, int, int);
  92 static bool NOP_Fixup (instr_info *, int, int);
  93 static bool OP_3DNowSuffix (instr_info *, int, int);
  94 static bool CMP_Fixup (instr_info *, int, int);
  95 static bool REP_Fixup (instr_info *, int, int);
  96 static bool SEP_Fixup (instr_info *, int, int);
  97 static bool BND_Fixup (instr_info *, int, int);
  98 static bool NOTRACK_Fixup (instr_info *, int, int);
  99 static bool HLE_Fixup1 (instr_info *, int, int);
 100 static bool HLE_Fixup2 (instr_info *, int, int);
 101 static bool HLE_Fixup3 (instr_info *, int, int);
 102 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
 103 static bool XMM_Fixup (instr_info *, int, int);
 104 static bool FXSAVE_Fixup (instr_info *, int, int);
 105 static bool MOVSXD_Fixup (instr_info *, int, int);
 106 static bool DistinctDest_Fixup (instr_info *, int, int);
 107 static bool PREFETCHI_Fixup (instr_info *, int, int);
 108 static bool PUSH2_POP2_Fixup (instr_info *, int, int);
 109 static bool JMPABS_Fixup (instr_info *, int, int);
 110
 111 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
 112                                                 enum disassembler_style,
 113                                                 const char *, ...);
 114
 115 /* This character is used to encode style information within the output
 116    buffers.  See oappend_insert_style for more details.  */
 117 #define STYLE_MARKER_CHAR '\002'
 118
 119 /* The maximum operand buffer size.  */
 120 #define MAX_OPERAND_BUFFER_SIZE 128
 121
 122 enum address_mode
 123 {
 124   mode_16bit,
 125   mode_32bit,
 126   mode_64bit
 127 };
 128
 129 static const char *prefix_name (enum address_mode, uint8_t, int);
 130
 131 enum x86_64_isa
 132 {
 133   amd64 = 1,
 134   intel64
 135 };
 136
 137 enum evex_type
 138 {
 139   evex_default = 0,
 140   evex_from_legacy,
 141   evex_from_vex,
 142 };
 143
 144 struct instr_info
 145 {
 146   enum address_mode address_mode;
 147
 148   /* Flags for the prefixes for the current instruction.  See below.  */
 149   int prefixes;
 150
 151   /* REX prefix the current instruction.  See below.  */
 152   uint8_t rex;
 153   /* Bits of REX we've already used.  */
 154   uint8_t rex_used;
 155
 156   /* Record W R4 X4 B4 bits for rex2.  */
 157   unsigned char rex2;
 158   /* Bits of rex2 we've already used.  */
 159   unsigned char rex2_used;
 160   unsigned char rex2_payload;
 161
 162   bool need_modrm;
 163   unsigned char need_vex;
 164   bool has_sib;
 165
 166   /* Flags for ins->prefixes which we somehow handled when printing the
 167      current instruction.  */
 168   int used_prefixes;
 169
 170   /* Flags for EVEX bits which we somehow handled when printing the
 171      current instruction.  */
 172   int evex_used;
 173
 174   char obuf[MAX_OPERAND_BUFFER_SIZE];
 175   char *obufp;
 176   char *mnemonicendp;
 177   const uint8_t *start_codep;
 178   uint8_t *codep;
 179   const uint8_t *end_codep;
 180   unsigned char nr_prefixes;
 181   signed char last_lock_prefix;
 182   signed char last_repz_prefix;
 183   signed char last_repnz_prefix;
 184   signed char last_data_prefix;
 185   signed char last_addr_prefix;
 186   signed char last_rex_prefix;
 187   signed char last_rex2_prefix;
 188   signed char last_seg_prefix;
 189   signed char fwait_prefix;
 190   /* The active segment register prefix.  */
 191   unsigned char active_seg_prefix;
 192
 193 #define MAX_CODE_LENGTH 15
 194   /* We can up to 14 ins->prefixes since the maximum instruction length is
 195      15bytes.  */
 196   uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
 197   disassemble_info *info;
 198
 199   struct
 200   {
 201     int mod;
 202     int reg;
 203     int rm;
 204   }
 205   modrm;
 206
 207   struct
 208   {
 209     int scale;
 210     int index;
 211     int base;
 212   }
 213   sib;
 214
 215   struct
 216   {
 217     int register_specifier;
 218     int length;
 219     int prefix;
 220     int mask_register_specifier;
 221     int ll;
 222     bool w;
 223     bool evex;
 224     bool v;
 225     bool zeroing;
 226     bool b;
 227     bool no_broadcast;
 228   }
 229   vex;
 230
 231 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b.  */
 232 #define nd b
 233
 234   enum evex_type evex_type;
 235
 236   /* Remember if the current op is a jump instruction.  */
 237   bool op_is_jump;
 238
 239   bool two_source_ops;
 240
 241   /* Record whether EVEX masking is used incorrectly.  */
 242   bool illegal_masking;
 243
 244   /* Record whether the modrm byte has been skipped.  */
 245   bool has_skipped_modrm;
 246
 247   unsigned char op_ad;
 248   signed char op_index[MAX_OPERANDS];
 249   bool op_riprel[MAX_OPERANDS];
 250   char *op_out[MAX_OPERANDS];
 251   bfd_vma op_address[MAX_OPERANDS];
 252   bfd_vma start_pc;
 253
 254   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 255    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 256    *   section of the "Virtual 8086 Mode" chapter.)
 257    * 'pc' should be the address of this instruction, it will
 258    *   be used to print the target address if this is a relative jump or call
 259    * The function returns the length of this instruction in bytes.
 260    */
 261   char intel_syntax;
 262   bool intel_mnemonic;
 263   char open_char;
 264   char close_char;
 265   char separator_char;
 266   char scale_char;
 267
 268   enum x86_64_isa isa64;
 269 };
 270
 271 struct dis_private {
 272   bfd_vma insn_start;
 273   int orig_sizeflag;
 274
 275   /* Indexes first byte not fetched.  */
 276   unsigned int fetched;
 277   uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
 278 };
 279
 280 /* Mark parts used in the REX prefix.  When we are testing for
 281    empty prefix (for 8bit register REX extension), just mask it
 282    out.  Otherwise test for REX bit is excuse for existence of REX
 283    only in case value is nonzero.  */
 284 #define USED_REX(value)                                 \
 285   {                                                     \
 286     if (value)                                          \
 287       {                                                 \
 288         if (ins->rex & value)                           \
 289           ins->rex_used |= (value) | REX_OPCODE;        \
 290         if (ins->rex2 & value)                          \
 291           {                                             \
 292             ins->rex2_used |= (value);                  \
 293             ins->rex_used |= REX_OPCODE;                \
 294           }                                             \
 295       }                                                 \
 296     else                                                \
 297       ins->rex_used |= REX_OPCODE;                      \
 298   }
 299
 300
 301 #define EVEX_b_used 1
 302 #define EVEX_len_used 2
 303
 304
 305 /* {rex2} is not printed when the REX2_SPECIAL is set.  */
 306 #define REX2_SPECIAL 16
 307
 308 /* Flags stored in PREFIXES.  */
 309 #define PREFIX_REPZ 1
 310 #define PREFIX_REPNZ 2
 311 #define PREFIX_CS 4
 312 #define PREFIX_SS 8
 313 #define PREFIX_DS 0x10
 314 #define PREFIX_ES 0x20
 315 #define PREFIX_FS 0x40
 316 #define PREFIX_GS 0x80
 317 #define PREFIX_LOCK 0x100
 318 #define PREFIX_DATA 0x200
 319 #define PREFIX_ADDR 0x400
 320 #define PREFIX_FWAIT 0x800
 321 #define PREFIX_REX2 0x1000
 322 #define PREFIX_NP_OR_DATA 0x2000
 323 #define NO_PREFIX   0x4000
 324
 325 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 326    to ADDR (exclusive) are valid.  Returns true for success, false
 327    on error.  */
 328 static bool
 329 fetch_code (struct disassemble_info *info, const uint8_t *until)
 330 {
 331   int status = -1;
 332   struct dis_private *priv = info->private_data;
 333   bfd_vma start = priv->insn_start + priv->fetched;
 334   uint8_t *fetch_end = priv->the_buffer + priv->fetched;
 335   ptrdiff_t needed = until - fetch_end;
 336
 337   if (needed <= 0)
 338     return true;
 339
 340   if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
 341     status = (*info->read_memory_func) (start, fetch_end, needed, info);
 342   if (status != 0)
 343     {
 344       /* If we did manage to read at least one byte, then
 345          print_insn_i386 will do something sensible.  Otherwise, print
 346          an error.  We do that here because this is where we know
 347          STATUS.  */
 348       if (!priv->fetched)
 349         (*info->memory_error_func) (status, start, info);
 350       return false;
 351     }
 352
 353   priv->fetched += needed;
 354   return true;
 355 }
 356
 357 static bool
 358 fetch_modrm (instr_info *ins)
 359 {
 360   if (!fetch_code (ins->info, ins->codep + 1))
 361     return false;
 362
 363   ins->modrm.mod = (*ins->codep >> 6) & 3;
 364   ins->modrm.reg = (*ins->codep >> 3) & 7;
 365   ins->modrm.rm = *ins->codep & 7;
 366
 367   return true;
 368 }
 369
 370 static int
 371 fetch_error (const instr_info *ins)
 372 {
 373   /* Getting here means we tried for data but didn't get it.  That
 374      means we have an incomplete instruction of some sort.  Just
 375      print the first byte as a prefix or a .byte pseudo-op.  */
 376   const struct dis_private *priv = ins->info->private_data;
 377   const char *name = NULL;
 378
 379   if (ins->codep <= priv->the_buffer)
 380     return -1;
 381
 382   if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
 383     name = prefix_name (ins->address_mode, priv->the_buffer[0],
 384                         priv->orig_sizeflag);
 385   if (name != NULL)
 386     i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
 387   else
 388     {
 389       /* Just print the first byte as a .byte instruction.  */
 390       i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
 391       i386_dis_printf (ins->info, dis_style_immediate, "%#x",
 392                        (unsigned int) priv->the_buffer[0]);
 393     }
 394
 395   return 1;
 396 }
 397
 398 /* Possible values for prefix requirement.  */
 399 #define PREFIX_IGNORED_SHIFT    16
 400 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 401 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 402 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 403 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 404 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 405 #define PREFIX_REX2_ILLEGAL     (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
 406
 407 /* Opcode prefixes.  */
 408 #define PREFIX_OPCODE           (PREFIX_REPZ \
 409                                  | PREFIX_REPNZ \
 410                                  | PREFIX_DATA)
 411
 412 /* Prefixes ignored.  */
 413 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 414                                  | PREFIX_IGNORED_REPNZ \
 415                                  | PREFIX_IGNORED_DATA)
 416
 417 #define XX { NULL, 0 }
 418 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 419
 420 #define Eb { OP_E, b_mode }
 421 #define Ebnd { OP_E, bnd_mode }
 422 #define EbS { OP_E, b_swap_mode }
 423 #define EbndS { OP_E, bnd_swap_mode }
 424 #define Ev { OP_E, v_mode }
 425 #define Eva { OP_E, va_mode }
 426 #define Ev_bnd { OP_E, v_bnd_mode }
 427 #define EvS { OP_E, v_swap_mode }
 428 #define Ed { OP_E, d_mode }
 429 #define Edq { OP_E, dq_mode }
 430 #define Edb { OP_E, db_mode }
 431 #define Edw { OP_E, dw_mode }
 432 #define Eq { OP_E, q_mode }
 433 #define indirEv { OP_indirE, indir_v_mode }
 434 #define indirEp { OP_indirE, f_mode }
 435 #define stackEv { OP_E, stack_v_mode }
 436 #define Em { OP_E, m_mode }
 437 #define Ew { OP_E, w_mode }
 438 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 439 #define Ma { OP_M, a_mode }
 440 #define Mb { OP_M, b_mode }
 441 #define Md { OP_M, d_mode }
 442 #define Mdq { OP_M, dq_mode }
 443 #define Mo { OP_M, o_mode }
 444 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 445 #define Mq { OP_M, q_mode }
 446 #define Mv { OP_M, v_mode }
 447 #define Mv_bnd { OP_M, v_bndmk_mode }
 448 #define Mw { OP_M, w_mode }
 449 #define Mx { OP_M, x_mode }
 450 #define Mxmm { OP_M, xmm_mode }
 451 #define Mymm { OP_M, ymm_mode }
 452 #define Gb { OP_G, b_mode }
 453 #define Gbnd { OP_G, bnd_mode }
 454 #define Gv { OP_G, v_mode }
 455 #define Gd { OP_G, d_mode }
 456 #define Gdq { OP_G, dq_mode }
 457 #define Gq { OP_G, q_mode }
 458 #define Gm { OP_G, m_mode }
 459 #define Gva { OP_G, va_mode }
 460 #define Gw { OP_G, w_mode }
 461 #define Ib { OP_I, b_mode }
 462 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 463 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 464 #define Iv { OP_I, v_mode }
 465 #define sIv { OP_sI, v_mode }
 466 #define Iv64 { OP_I64, v_mode }
 467 #define Id { OP_I, d_mode }
 468 #define Iw { OP_I, w_mode }
 469 #define I1 { OP_I, const_1_mode }
 470 #define Jb { OP_J, b_mode }
 471 #define Jv { OP_J, v_mode }
 472 #define Jdqw { OP_J, dqw_mode }
 473 #define Cm { OP_C, m_mode }
 474 #define Dm { OP_D, m_mode }
 475 #define Td { OP_T, d_mode }
 476 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 477
 478 #define RMeAX { OP_REG, eAX_reg }
 479 #define RMeBX { OP_REG, eBX_reg }
 480 #define RMeCX { OP_REG, eCX_reg }
 481 #define RMeDX { OP_REG, eDX_reg }
 482 #define RMeSP { OP_REG, eSP_reg }
 483 #define RMeBP { OP_REG, eBP_reg }
 484 #define RMeSI { OP_REG, eSI_reg }
 485 #define RMeDI { OP_REG, eDI_reg }
 486 #define RMrAX { OP_REG, rAX_reg }
 487 #define RMrBX { OP_REG, rBX_reg }
 488 #define RMrCX { OP_REG, rCX_reg }
 489 #define RMrDX { OP_REG, rDX_reg }
 490 #define RMrSP { OP_REG, rSP_reg }
 491 #define RMrBP { OP_REG, rBP_reg }
 492 #define RMrSI { OP_REG, rSI_reg }
 493 #define RMrDI { OP_REG, rDI_reg }
 494 #define RMAL { OP_REG, al_reg }
 495 #define RMCL { OP_REG, cl_reg }
 496 #define RMDL { OP_REG, dl_reg }
 497 #define RMBL { OP_REG, bl_reg }
 498 #define RMAH { OP_REG, ah_reg }
 499 #define RMCH { OP_REG, ch_reg }
 500 #define RMDH { OP_REG, dh_reg }
 501 #define RMBH { OP_REG, bh_reg }
 502 #define RMAX { OP_REG, ax_reg }
 503 #define RMDX { OP_REG, dx_reg }
 504
 505 #define eAX { OP_IMREG, eAX_reg }
 506 #define AL { OP_IMREG, al_reg }
 507 #define CL { OP_IMREG, cl_reg }
 508 #define zAX { OP_IMREG, z_mode_ax_reg }
 509 #define indirDX { OP_IMREG, indir_dx_reg }
 510
 511 #define Sw { OP_SEG, w_mode }
 512 #define Sv { OP_SEG, v_mode }
 513 #define Ap { OP_DIR, 0 }
 514 #define Ob { OP_OFF64, b_mode }
 515 #define Ov { OP_OFF64, v_mode }
 516 #define Xb { OP_DSreg, eSI_reg }
 517 #define Xv { OP_DSreg, eSI_reg }
 518 #define Xz { OP_DSreg, eSI_reg }
 519 #define Yb { OP_ESreg, eDI_reg }
 520 #define Yv { OP_ESreg, eDI_reg }
 521 #define DSBX { OP_DSreg, eBX_reg }
 522
 523 #define es { OP_REG, es_reg }
 524 #define ss { OP_REG, ss_reg }
 525 #define cs { OP_REG, cs_reg }
 526 #define ds { OP_REG, ds_reg }
 527 #define fs { OP_REG, fs_reg }
 528 #define gs { OP_REG, gs_reg }
 529
 530 #define MX { OP_MMX, 0 }
 531 #define XM { OP_XMM, 0 }
 532 #define XMScalar { OP_XMM, scalar_mode }
 533 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 534 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 535 #define XMM { OP_XMM, xmm_mode }
 536 #define TMM { OP_XMM, tmm_mode }
 537 #define XMxmmq { OP_XMM, xmmq_mode }
 538 #define EM { OP_EM, v_mode }
 539 #define EMS { OP_EM, v_swap_mode }
 540 #define EMd { OP_EM, d_mode }
 541 #define EMx { OP_EM, x_mode }
 542 #define EXbwUnit { OP_EX, bw_unit_mode }
 543 #define EXb { OP_EX, b_mode }
 544 #define EXw { OP_EX, w_mode }
 545 #define EXd { OP_EX, d_mode }
 546 #define EXdS { OP_EX, d_swap_mode }
 547 #define EXwS { OP_EX, w_swap_mode }
 548 #define EXq { OP_EX, q_mode }
 549 #define EXqS { OP_EX, q_swap_mode }
 550 #define EXdq { OP_EX, dq_mode }
 551 #define EXx { OP_EX, x_mode }
 552 #define EXxh { OP_EX, xh_mode }
 553 #define EXxS { OP_EX, x_swap_mode }
 554 #define EXxmm { OP_EX, xmm_mode }
 555 #define EXymm { OP_EX, ymm_mode }
 556 #define EXxmmq { OP_EX, xmmq_mode }
 557 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 558 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 559 #define EXxmmdw { OP_EX, xmmdw_mode }
 560 #define EXxmmqd { OP_EX, xmmqd_mode }
 561 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 562 #define EXymmq { OP_EX, ymmq_mode }
 563 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 564 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 565 #define Rd { OP_R, d_mode }
 566 #define Rdq { OP_R, dq_mode }
 567 #define Rq { OP_R, q_mode }
 568 #define Nq { OP_R, q_mm_mode }
 569 #define Ux { OP_R, x_mode }
 570 #define Uxmm { OP_R, xmm_mode }
 571 #define Rxmmq { OP_R, xmmq_mode }
 572 #define Rymm { OP_R, ymm_mode }
 573 #define Rtmm { OP_R, tmm_mode }
 574 #define EMCq { OP_EMC, q_mode }
 575 #define MXC { OP_MXC, 0 }
 576 #define OPSUF { OP_3DNowSuffix, 0 }
 577 #define SEP { SEP_Fixup, 0 }
 578 #define CMP { CMP_Fixup, 0 }
 579 #define XMM0 { XMM_Fixup, 0 }
 580 #define FXSAVE { FXSAVE_Fixup, 0 }
 581
 582 #define Vex { OP_VEX, x_mode }
 583 #define VexW { OP_VexW, x_mode }
 584 #define VexScalar { OP_VEX, scalar_mode }
 585 #define VexScalarR { OP_VexR, scalar_mode }
 586 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 587 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 588 #define VexGdq { OP_VEX, dq_mode }
 589 #define VexGb { OP_VEX, b_mode }
 590 #define VexGv { OP_VEX, v_mode }
 591 #define VexTmm { OP_VEX, tmm_mode }
 592 #define XMVexI4 { OP_REG_VexI4, x_mode }
 593 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 594 #define VexI4 { OP_VexI4, 0 }
 595 #define PCLMUL { PCLMUL_Fixup, 0 }
 596 #define VPCMP { VPCMP_Fixup, 0 }
 597 #define VPCOM { VPCOM_Fixup, 0 }
 598
 599 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 600 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 601 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 602
 603 #define MaskG { OP_G, mask_mode }
 604 #define MaskE { OP_E, mask_mode }
 605 #define MaskR { OP_R, mask_mode }
 606 #define MaskBDE { OP_E, mask_bd_mode }
 607 #define MaskVex { OP_VEX, mask_mode }
 608
 609 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 610 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 611
 612 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 613
 614 /* Used handle "rep" prefix for string instructions.  */
 615 #define Xbr { REP_Fixup, eSI_reg }
 616 #define Xvr { REP_Fixup, eSI_reg }
 617 #define Ybr { REP_Fixup, eDI_reg }
 618 #define Yvr { REP_Fixup, eDI_reg }
 619 #define Yzr { REP_Fixup, eDI_reg }
 620 #define indirDXr { REP_Fixup, indir_dx_reg }
 621 #define ALr { REP_Fixup, al_reg }
 622 #define eAXr { REP_Fixup, eAX_reg }
 623
 624 /* Used handle HLE prefix for lockable instructions.  */
 625 #define Ebh1 { HLE_Fixup1, b_mode }
 626 #define Evh1 { HLE_Fixup1, v_mode }
 627 #define Ebh2 { HLE_Fixup2, b_mode }
 628 #define Evh2 { HLE_Fixup2, v_mode }
 629 #define Ebh3 { HLE_Fixup3, b_mode }
 630 #define Evh3 { HLE_Fixup3, v_mode }
 631
 632 #define BND { BND_Fixup, 0 }
 633 #define NOTRACK { NOTRACK_Fixup, 0 }
 634
 635 #define cond_jump_flag { NULL, cond_jump_mode }
 636 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 637
 638 /* bits in sizeflag */
 639 #define SUFFIX_ALWAYS 4
 640 #define AFLAG 2
 641 #define DFLAG 1
 642
 643 enum
 644 {
 645   /* byte operand */
 646   b_mode = 1,
 647   /* byte operand with operand swapped */
 648   b_swap_mode,
 649   /* byte operand, sign extend like 'T' suffix */
 650   b_T_mode,
 651   /* operand size depends on prefixes */
 652   v_mode,
 653   /* operand size depends on prefixes with operand swapped */
 654   v_swap_mode,
 655   /* operand size depends on address prefix */
 656   va_mode,
 657   /* word operand */
 658   w_mode,
 659   /* double word operand  */
 660   d_mode,
 661   /* word operand with operand swapped  */
 662   w_swap_mode,
 663   /* double word operand with operand swapped */
 664   d_swap_mode,
 665   /* quad word operand */
 666   q_mode,
 667   /* 8-byte MM operand */
 668   q_mm_mode,
 669   /* quad word operand with operand swapped */
 670   q_swap_mode,
 671   /* ten-byte operand */
 672   t_mode,
 673   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 674      broadcast enabled.  */
 675   x_mode,
 676   /* Similar to x_mode, but with different EVEX mem shifts.  */
 677   evex_x_gscat_mode,
 678   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 679   bw_unit_mode,
 680   /* Similar to x_mode, but with disabled broadcast.  */
 681   evex_x_nobcst_mode,
 682   /* Similar to x_mode, but with operands swapped and disabled broadcast
 683      in EVEX.  */
 684   x_swap_mode,
 685   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 686      broadcast of 16bit enabled.  */
 687   xh_mode,
 688   /* 16-byte XMM operand */
 689   xmm_mode,
 690   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 691      memory operand (depending on vector length).  Broadcast isn't
 692      allowed.  */
 693   xmmq_mode,
 694   /* Same as xmmq_mode, but broadcast is allowed.  */
 695   evex_half_bcst_xmmq_mode,
 696   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 697      memory operand (depending on vector length).  16bit broadcast.  */
 698   evex_half_bcst_xmmqh_mode,
 699   /* 16-byte XMM, word, double word or quad word operand.  */
 700   xmmdw_mode,
 701   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 702   xmmqd_mode,
 703   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 704      16bit broadcast.  */
 705   evex_half_bcst_xmmqdh_mode,
 706   /* 32-byte YMM operand */
 707   ymm_mode,
 708   /* quad word, ymmword or zmmword memory operand.  */
 709   ymmq_mode,
 710   /* TMM operand */
 711   tmm_mode,
 712   /* d_mode in 32bit, q_mode in 64bit mode.  */
 713   m_mode,
 714   /* pair of v_mode operands */
 715   a_mode,
 716   cond_jump_mode,
 717   loop_jcxz_mode,
 718   movsxd_mode,
 719   v_bnd_mode,
 720   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 721   v_bndmk_mode,
 722   /* operand size depends on REX.W / VEX.W.  */
 723   dq_mode,
 724   /* Displacements like v_mode without considering Intel64 ISA.  */
 725   dqw_mode,
 726   /* bounds operand */
 727   bnd_mode,
 728   /* bounds operand with operand swapped */
 729   bnd_swap_mode,
 730   /* 4- or 6-byte pointer operand */
 731   f_mode,
 732   const_1_mode,
 733   /* v_mode for indirect branch opcodes.  */
 734   indir_v_mode,
 735   /* v_mode for stack-related opcodes.  */
 736   stack_v_mode,
 737   /* non-quad operand size depends on prefixes */
 738   z_mode,
 739   /* 16-byte operand */
 740   o_mode,
 741   /* registers like d_mode, memory like b_mode.  */
 742   db_mode,
 743   /* registers like d_mode, memory like w_mode.  */
 744   dw_mode,
 745
 746   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 747   vex_vsib_d_w_dq_mode,
 748   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 749   vex_vsib_q_w_dq_mode,
 750   /* mandatory non-vector SIB.  */
 751   vex_sibmem_mode,
 752
 753   /* scalar, ignore vector length.  */
 754   scalar_mode,
 755
 756   /* Static rounding.  */
 757   evex_rounding_mode,
 758   /* Static rounding, 64-bit mode only.  */
 759   evex_rounding_64_mode,
 760   /* Supress all exceptions.  */
 761   evex_sae_mode,
 762
 763   /* Mask register operand.  */
 764   mask_mode,
 765   /* Mask register operand.  */
 766   mask_bd_mode,
 767
 768   es_reg,
 769   cs_reg,
 770   ss_reg,
 771   ds_reg,
 772   fs_reg,
 773   gs_reg,
 774
 775   eAX_reg,
 776   eCX_reg,
 777   eDX_reg,
 778   eBX_reg,
 779   eSP_reg,
 780   eBP_reg,
 781   eSI_reg,
 782   eDI_reg,
 783
 784   al_reg,
 785   cl_reg,
 786   dl_reg,
 787   bl_reg,
 788   ah_reg,
 789   ch_reg,
 790   dh_reg,
 791   bh_reg,
 792
 793   ax_reg,
 794   cx_reg,
 795   dx_reg,
 796   bx_reg,
 797   sp_reg,
 798   bp_reg,
 799   si_reg,
 800   di_reg,
 801
 802   rAX_reg,
 803   rCX_reg,
 804   rDX_reg,
 805   rBX_reg,
 806   rSP_reg,
 807   rBP_reg,
 808   rSI_reg,
 809   rDI_reg,
 810
 811   z_mode_ax_reg,
 812   indir_dx_reg
 813 };
 814
 815 enum
 816 {
 817   FLOATCODE = 1,
 818   USE_REG_TABLE,
 819   USE_MOD_TABLE,
 820   USE_RM_TABLE,
 821   USE_PREFIX_TABLE,
 822   USE_X86_64_TABLE,
 823   USE_X86_64_EVEX_FROM_VEX_TABLE,
 824   USE_X86_64_EVEX_PFX_TABLE,
 825   USE_X86_64_EVEX_W_TABLE,
 826   USE_X86_64_EVEX_MEM_W_TABLE,
 827   USE_3BYTE_TABLE,
 828   USE_XOP_8F_TABLE,
 829   USE_VEX_C4_TABLE,
 830   USE_VEX_C5_TABLE,
 831   USE_VEX_LEN_TABLE,
 832   USE_VEX_W_TABLE,
 833   USE_EVEX_TABLE,
 834   USE_EVEX_LEN_TABLE
 835 };
 836
 837 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 838
 839 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 840 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 841 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 842 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 843 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 844 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 845 #define X86_64_EVEX_FROM_VEX_TABLE(I) \
 846   DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
 847 #define X86_64_EVEX_PFX_TABLE(I) DIS386 (USE_X86_64_EVEX_PFX_TABLE, (I))
 848 #define X86_64_EVEX_W_TABLE(I) DIS386 (USE_X86_64_EVEX_W_TABLE, (I))
 849 #define X86_64_EVEX_MEM_W_TABLE(I) DIS386 (USE_X86_64_EVEX_MEM_W_TABLE, (I))
 850 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 851 #define XOP_8F_TABLE()          DIS386 (USE_XOP_8F_TABLE, 0)
 852 #define VEX_C4_TABLE()          DIS386 (USE_VEX_C4_TABLE, 0)
 853 #define VEX_C5_TABLE()          DIS386 (USE_VEX_C5_TABLE, 0)
 854 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 855 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 856 #define EVEX_TABLE()            DIS386 (USE_EVEX_TABLE, 0)
 857 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 858
 859 enum
 860 {
 861   REG_80 = 0,
 862   REG_81,
 863   REG_83,
 864   REG_8F,
 865   REG_C0,
 866   REG_C1,
 867   REG_C6,
 868   REG_C7,
 869   REG_D0,
 870   REG_D1,
 871   REG_D2,
 872   REG_D3,
 873   REG_F6,
 874   REG_F7,
 875   REG_FE,
 876   REG_FF,
 877   REG_0F00,
 878   REG_0F01,
 879   REG_0F0D,
 880   REG_0F18,
 881   REG_0F1C_P_0_MOD_0,
 882   REG_0F1E_P_1_MOD_3,
 883   REG_0F38D8_PREFIX_1,
 884   REG_0F3A0F_P_1,
 885   REG_0F71,
 886   REG_0F72,
 887   REG_0F73,
 888   REG_0FA6,
 889   REG_0FA7,
 890   REG_0FAE,
 891   REG_0FBA,
 892   REG_0FC7,
 893   REG_VEX_0F71,
 894   REG_VEX_0F72,
 895   REG_VEX_0F73,
 896   REG_VEX_0FAE,
 897   REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
 898   REG_VEX_0F38F3_L_0_P_0,
 899   REG_VEX_MAP7_F8_L_0_W_0,
 900
 901   REG_XOP_09_01_L_0,
 902   REG_XOP_09_02_L_0,
 903   REG_XOP_09_12_L_0,
 904   REG_XOP_0A_12_L_0,
 905
 906   REG_EVEX_0F71,
 907   REG_EVEX_0F72,
 908   REG_EVEX_0F73,
 909   REG_EVEX_0F38C6_L_2,
 910   REG_EVEX_0F38C7_L_2,
 911   REG_EVEX_MAP4_80,
 912   REG_EVEX_MAP4_81,
 913   REG_EVEX_MAP4_83,
 914   REG_EVEX_MAP4_8F,
 915   REG_EVEX_MAP4_F6,
 916   REG_EVEX_MAP4_F7,
 917   REG_EVEX_MAP4_FE,
 918   REG_EVEX_MAP4_FF,
 919 };
 920
 921 enum
 922 {
 923   MOD_62_32BIT = 0,
 924   MOD_C4_32BIT,
 925   MOD_C5_32BIT,
 926   MOD_0F01_REG_0,
 927   MOD_0F01_REG_1,
 928   MOD_0F01_REG_2,
 929   MOD_0F01_REG_3,
 930   MOD_0F01_REG_5,
 931   MOD_0F01_REG_7,
 932   MOD_0F12_PREFIX_0,
 933   MOD_0F16_PREFIX_0,
 934   MOD_0F18_REG_0,
 935   MOD_0F18_REG_1,
 936   MOD_0F18_REG_2,
 937   MOD_0F18_REG_3,
 938   MOD_0F18_REG_6,
 939   MOD_0F18_REG_7,
 940   MOD_0F1A_PREFIX_0,
 941   MOD_0F1B_PREFIX_0,
 942   MOD_0F1B_PREFIX_1,
 943   MOD_0F1C_PREFIX_0,
 944   MOD_0F1E_PREFIX_1,
 945   MOD_0FAE_REG_0,
 946   MOD_0FAE_REG_1,
 947   MOD_0FAE_REG_2,
 948   MOD_0FAE_REG_3,
 949   MOD_0FAE_REG_4,
 950   MOD_0FAE_REG_5,
 951   MOD_0FAE_REG_6,
 952   MOD_0FAE_REG_7,
 953   MOD_0FC7_REG_6,
 954   MOD_0FC7_REG_7,
 955   MOD_0F38DC_PREFIX_1,
 956   MOD_0F38F8,
 957
 958   MOD_VEX_0F3849_X86_64_L_0_W_0,
 959
 960   MOD_EVEX_MAP4_F8_P_1,
 961   MOD_EVEX_MAP4_F8_P_3,
 962 };
 963
 964 enum
 965 {
 966   RM_C6_REG_7 = 0,
 967   RM_C7_REG_7,
 968   RM_0F01_REG_0,
 969   RM_0F01_REG_1,
 970   RM_0F01_REG_2,
 971   RM_0F01_REG_3,
 972   RM_0F01_REG_5_MOD_3,
 973   RM_0F01_REG_7_MOD_3,
 974   RM_0F1E_P_1_MOD_3_REG_7,
 975   RM_0FAE_REG_6_MOD_3_P_0,
 976   RM_0FAE_REG_7_MOD_3,
 977   RM_0F3A0F_P_1_R_0,
 978
 979   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
 980   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
 981 };
 982
 983 enum
 984 {
 985   PREFIX_90 = 0,
 986   PREFIX_0F00_REG_6_X86_64,
 987   PREFIX_0F01_REG_0_MOD_3_RM_6,
 988   PREFIX_0F01_REG_0_MOD_3_RM_7,
 989   PREFIX_0F01_REG_1_RM_2,
 990   PREFIX_0F01_REG_1_RM_4,
 991   PREFIX_0F01_REG_1_RM_5,
 992   PREFIX_0F01_REG_1_RM_6,
 993   PREFIX_0F01_REG_1_RM_7,
 994   PREFIX_0F01_REG_3_RM_1,
 995   PREFIX_0F01_REG_5_MOD_0,
 996   PREFIX_0F01_REG_5_MOD_3_RM_0,
 997   PREFIX_0F01_REG_5_MOD_3_RM_1,
 998   PREFIX_0F01_REG_5_MOD_3_RM_2,
 999   PREFIX_0F01_REG_5_MOD_3_RM_4,
1000   PREFIX_0F01_REG_5_MOD_3_RM_5,
1001   PREFIX_0F01_REG_5_MOD_3_RM_6,
1002   PREFIX_0F01_REG_5_MOD_3_RM_7,
1003   PREFIX_0F01_REG_7_MOD_3_RM_2,
1004   PREFIX_0F01_REG_7_MOD_3_RM_5,
1005   PREFIX_0F01_REG_7_MOD_3_RM_6,
1006   PREFIX_0F01_REG_7_MOD_3_RM_7,
1007   PREFIX_0F09,
1008   PREFIX_0F10,
1009   PREFIX_0F11,
1010   PREFIX_0F12,
1011   PREFIX_0F16,
1012   PREFIX_0F18_REG_6_MOD_0_X86_64,
1013   PREFIX_0F18_REG_7_MOD_0_X86_64,
1014   PREFIX_0F1A,
1015   PREFIX_0F1B,
1016   PREFIX_0F1C,
1017   PREFIX_0F1E,
1018   PREFIX_0F2A,
1019   PREFIX_0F2B,
1020   PREFIX_0F2C,
1021   PREFIX_0F2D,
1022   PREFIX_0F2E,
1023   PREFIX_0F2F,
1024   PREFIX_0F51,
1025   PREFIX_0F52,
1026   PREFIX_0F53,
1027   PREFIX_0F58,
1028   PREFIX_0F59,
1029   PREFIX_0F5A,
1030   PREFIX_0F5B,
1031   PREFIX_0F5C,
1032   PREFIX_0F5D,
1033   PREFIX_0F5E,
1034   PREFIX_0F5F,
1035   PREFIX_0F60,
1036   PREFIX_0F61,
1037   PREFIX_0F62,
1038   PREFIX_0F6F,
1039   PREFIX_0F70,
1040   PREFIX_0F78,
1041   PREFIX_0F79,
1042   PREFIX_0F7C,
1043   PREFIX_0F7D,
1044   PREFIX_0F7E,
1045   PREFIX_0F7F,
1046   PREFIX_0FAE_REG_0_MOD_3,
1047   PREFIX_0FAE_REG_1_MOD_3,
1048   PREFIX_0FAE_REG_2_MOD_3,
1049   PREFIX_0FAE_REG_3_MOD_3,
1050   PREFIX_0FAE_REG_4_MOD_0,
1051   PREFIX_0FAE_REG_4_MOD_3,
1052   PREFIX_0FAE_REG_5_MOD_3,
1053   PREFIX_0FAE_REG_6_MOD_0,
1054   PREFIX_0FAE_REG_6_MOD_3,
1055   PREFIX_0FAE_REG_7_MOD_0,
1056   PREFIX_0FB8,
1057   PREFIX_0FBC,
1058   PREFIX_0FBD,
1059   PREFIX_0FC2,
1060   PREFIX_0FC7_REG_6_MOD_0,
1061   PREFIX_0FC7_REG_6_MOD_3,
1062   PREFIX_0FC7_REG_7_MOD_3,
1063   PREFIX_0FD0,
1064   PREFIX_0FD6,
1065   PREFIX_0FE6,
1066   PREFIX_0FE7,
1067   PREFIX_0FF0,
1068   PREFIX_0FF7,
1069   PREFIX_0F38D8,
1070   PREFIX_0F38DC,
1071   PREFIX_0F38DD,
1072   PREFIX_0F38DE,
1073   PREFIX_0F38DF,
1074   PREFIX_0F38F0,
1075   PREFIX_0F38F1,
1076   PREFIX_0F38F6,
1077   PREFIX_0F38F8_M_0,
1078   PREFIX_0F38F8_M_1_X86_64,
1079   PREFIX_0F38FA,
1080   PREFIX_0F38FB,
1081   PREFIX_0F38FC,
1082   PREFIX_0F3A0F,
1083   PREFIX_VEX_0F12,
1084   PREFIX_VEX_0F16,
1085   PREFIX_VEX_0F2A,
1086   PREFIX_VEX_0F2C,
1087   PREFIX_VEX_0F2D,
1088   PREFIX_VEX_0F41_L_1_W_0,
1089   PREFIX_VEX_0F41_L_1_W_1,
1090   PREFIX_VEX_0F42_L_1_W_0,
1091   PREFIX_VEX_0F42_L_1_W_1,
1092   PREFIX_VEX_0F44_L_0_W_0,
1093   PREFIX_VEX_0F44_L_0_W_1,
1094   PREFIX_VEX_0F45_L_1_W_0,
1095   PREFIX_VEX_0F45_L_1_W_1,
1096   PREFIX_VEX_0F46_L_1_W_0,
1097   PREFIX_VEX_0F46_L_1_W_1,
1098   PREFIX_VEX_0F47_L_1_W_0,
1099   PREFIX_VEX_0F47_L_1_W_1,
1100   PREFIX_VEX_0F4A_L_1_W_0,
1101   PREFIX_VEX_0F4A_L_1_W_1,
1102   PREFIX_VEX_0F4B_L_1_W_0,
1103   PREFIX_VEX_0F4B_L_1_W_1,
1104   PREFIX_VEX_0F6F,
1105   PREFIX_VEX_0F70,
1106   PREFIX_VEX_0F7E,
1107   PREFIX_VEX_0F7F,
1108   PREFIX_VEX_0F90_L_0_W_0,
1109   PREFIX_VEX_0F90_L_0_W_1,
1110   PREFIX_VEX_0F91_L_0_W_0,
1111   PREFIX_VEX_0F91_L_0_W_1,
1112   PREFIX_VEX_0F92_L_0_W_0,
1113   PREFIX_VEX_0F92_L_0_W_1,
1114   PREFIX_VEX_0F93_L_0_W_0,
1115   PREFIX_VEX_0F93_L_0_W_1,
1116   PREFIX_VEX_0F98_L_0_W_0,
1117   PREFIX_VEX_0F98_L_0_W_1,
1118   PREFIX_VEX_0F99_L_0_W_0,
1119   PREFIX_VEX_0F99_L_0_W_1,
1120   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1121   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1122   PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1123   PREFIX_VEX_0F3850_W_0,
1124   PREFIX_VEX_0F3851_W_0,
1125   PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1126   PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1127   PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1128   PREFIX_VEX_0F3872,
1129   PREFIX_VEX_0F38B0_W_0,
1130   PREFIX_VEX_0F38B1_W_0,
1131   PREFIX_VEX_0F38D2_W_0,
1132   PREFIX_VEX_0F38D3_W_0,
1133   PREFIX_VEX_0F38CB,
1134   PREFIX_VEX_0F38CC,
1135   PREFIX_VEX_0F38CD,
1136   PREFIX_VEX_0F38DA_W_0,
1137   PREFIX_VEX_0F38F2_L_0,
1138   PREFIX_VEX_0F38F3_L_0,
1139   PREFIX_VEX_0F38F5_L_0,
1140   PREFIX_VEX_0F38F6_L_0,
1141   PREFIX_VEX_0F38F7_L_0,
1142   PREFIX_VEX_0F3AF0_L_0,
1143   PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1144
1145   PREFIX_EVEX_0F5B,
1146   PREFIX_EVEX_0F6F,
1147   PREFIX_EVEX_0F70,
1148   PREFIX_EVEX_0F78,
1149   PREFIX_EVEX_0F79,
1150   PREFIX_EVEX_0F7A,
1151   PREFIX_EVEX_0F7B,
1152   PREFIX_EVEX_0F7E,
1153   PREFIX_EVEX_0F7F,
1154   PREFIX_EVEX_0FC2,
1155   PREFIX_EVEX_0FE6,
1156   PREFIX_EVEX_0F3810,
1157   PREFIX_EVEX_0F3811,
1158   PREFIX_EVEX_0F3812,
1159   PREFIX_EVEX_0F3813,
1160   PREFIX_EVEX_0F3814,
1161   PREFIX_EVEX_0F3815,
1162   PREFIX_EVEX_0F3820,
1163   PREFIX_EVEX_0F3821,
1164   PREFIX_EVEX_0F3822,
1165   PREFIX_EVEX_0F3823,
1166   PREFIX_EVEX_0F3824,
1167   PREFIX_EVEX_0F3825,
1168   PREFIX_EVEX_0F3826,
1169   PREFIX_EVEX_0F3827,
1170   PREFIX_EVEX_0F3828,
1171   PREFIX_EVEX_0F3829,
1172   PREFIX_EVEX_0F382A,
1173   PREFIX_EVEX_0F3830,
1174   PREFIX_EVEX_0F3831,
1175   PREFIX_EVEX_0F3832,
1176   PREFIX_EVEX_0F3833,
1177   PREFIX_EVEX_0F3834,
1178   PREFIX_EVEX_0F3835,
1179   PREFIX_EVEX_0F3838,
1180   PREFIX_EVEX_0F3839,
1181   PREFIX_EVEX_0F383A,
1182   PREFIX_EVEX_0F3852,
1183   PREFIX_EVEX_0F3853,
1184   PREFIX_EVEX_0F3868,
1185   PREFIX_EVEX_0F3872,
1186   PREFIX_EVEX_0F389A,
1187   PREFIX_EVEX_0F389B,
1188   PREFIX_EVEX_0F38AA,
1189   PREFIX_EVEX_0F38AB,
1190
1191   PREFIX_EVEX_0F3A08,
1192   PREFIX_EVEX_0F3A0A,
1193   PREFIX_EVEX_0F3A26,
1194   PREFIX_EVEX_0F3A27,
1195   PREFIX_EVEX_0F3A56,
1196   PREFIX_EVEX_0F3A57,
1197   PREFIX_EVEX_0F3A66,
1198   PREFIX_EVEX_0F3A67,
1199   PREFIX_EVEX_0F3AC2,
1200
1201   PREFIX_EVEX_MAP4_D8,
1202   PREFIX_EVEX_MAP4_DA,
1203   PREFIX_EVEX_MAP4_DB,
1204   PREFIX_EVEX_MAP4_DC,
1205   PREFIX_EVEX_MAP4_DD,
1206   PREFIX_EVEX_MAP4_DE,
1207   PREFIX_EVEX_MAP4_DF,
1208   PREFIX_EVEX_MAP4_F0,
1209   PREFIX_EVEX_MAP4_F1,
1210   PREFIX_EVEX_MAP4_F2,
1211   PREFIX_EVEX_MAP4_F8,
1212
1213   PREFIX_EVEX_MAP5_10,
1214   PREFIX_EVEX_MAP5_11,
1215   PREFIX_EVEX_MAP5_1D,
1216   PREFIX_EVEX_MAP5_2A,
1217   PREFIX_EVEX_MAP5_2C,
1218   PREFIX_EVEX_MAP5_2D,
1219   PREFIX_EVEX_MAP5_2E,
1220   PREFIX_EVEX_MAP5_2F,
1221   PREFIX_EVEX_MAP5_51,
1222   PREFIX_EVEX_MAP5_58,
1223   PREFIX_EVEX_MAP5_59,
1224   PREFIX_EVEX_MAP5_5A,
1225   PREFIX_EVEX_MAP5_5B,
1226   PREFIX_EVEX_MAP5_5C,
1227   PREFIX_EVEX_MAP5_5D,
1228   PREFIX_EVEX_MAP5_5E,
1229   PREFIX_EVEX_MAP5_5F,
1230   PREFIX_EVEX_MAP5_78,
1231   PREFIX_EVEX_MAP5_79,
1232   PREFIX_EVEX_MAP5_7A,
1233   PREFIX_EVEX_MAP5_7B,
1234   PREFIX_EVEX_MAP5_7C,
1235   PREFIX_EVEX_MAP5_7D,
1236
1237   PREFIX_EVEX_MAP6_13,
1238   PREFIX_EVEX_MAP6_56,
1239   PREFIX_EVEX_MAP6_57,
1240   PREFIX_EVEX_MAP6_D6,
1241   PREFIX_EVEX_MAP6_D7,
1242 };
1243
1244 enum
1245 {
1246   X86_64_06 = 0,
1247   X86_64_07,
1248   X86_64_0E,
1249   X86_64_16,
1250   X86_64_17,
1251   X86_64_1E,
1252   X86_64_1F,
1253   X86_64_27,
1254   X86_64_2F,
1255   X86_64_37,
1256   X86_64_3F,
1257   X86_64_60,
1258   X86_64_61,
1259   X86_64_62,
1260   X86_64_63,
1261   X86_64_6D,
1262   X86_64_6F,
1263   X86_64_82,
1264   X86_64_9A,
1265   X86_64_C2,
1266   X86_64_C3,
1267   X86_64_C4,
1268   X86_64_C5,
1269   X86_64_CE,
1270   X86_64_D4,
1271   X86_64_D5,
1272   X86_64_E8,
1273   X86_64_E9,
1274   X86_64_EA,
1275   X86_64_0F00_REG_6,
1276   X86_64_0F01_REG_0,
1277   X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1278   X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1279   X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1280   X86_64_0F01_REG_1,
1281   X86_64_0F01_REG_1_RM_2_PREFIX_1,
1282   X86_64_0F01_REG_1_RM_2_PREFIX_3,
1283   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1284   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1285   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1286   X86_64_0F01_REG_2,
1287   X86_64_0F01_REG_3,
1288   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1289   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1290   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1291   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1292   X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1293   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1294   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1295   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1296   X86_64_0F18_REG_6_MOD_0,
1297   X86_64_0F18_REG_7_MOD_0,
1298   X86_64_0F24,
1299   X86_64_0F26,
1300   X86_64_0F38F8_M_1,
1301   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1302
1303   X86_64_VEX_0F3849,
1304   X86_64_VEX_0F384B,
1305   X86_64_VEX_0F385C,
1306   X86_64_VEX_0F385E,
1307   X86_64_VEX_0F386C,
1308   X86_64_VEX_0F38E0,
1309   X86_64_VEX_0F38E1,
1310   X86_64_VEX_0F38E2,
1311   X86_64_VEX_0F38E3,
1312   X86_64_VEX_0F38E4,
1313   X86_64_VEX_0F38E5,
1314   X86_64_VEX_0F38E6,
1315   X86_64_VEX_0F38E7,
1316   X86_64_VEX_0F38E8,
1317   X86_64_VEX_0F38E9,
1318   X86_64_VEX_0F38EA,
1319   X86_64_VEX_0F38EB,
1320   X86_64_VEX_0F38EC,
1321   X86_64_VEX_0F38ED,
1322   X86_64_VEX_0F38EE,
1323   X86_64_VEX_0F38EF,
1324
1325   X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1326 };
1327
1328 enum
1329 {
1330   THREE_BYTE_0F38 = 0,
1331   THREE_BYTE_0F3A
1332 };
1333
1334 enum
1335 {
1336   XOP_08 = 0,
1337   XOP_09,
1338   XOP_0A
1339 };
1340
1341 enum
1342 {
1343   VEX_0F = 0,
1344   VEX_0F38,
1345   VEX_0F3A,
1346   VEX_MAP7,
1347 };
1348
1349 enum
1350 {
1351   EVEX_0F = 0,
1352   EVEX_0F38,
1353   EVEX_0F3A,
1354   EVEX_MAP4,
1355   EVEX_MAP5,
1356   EVEX_MAP6,
1357   EVEX_MAP7,
1358 };
1359
1360 enum
1361 {
1362   VEX_LEN_0F12_P_0 = 0,
1363   VEX_LEN_0F12_P_2,
1364   VEX_LEN_0F13,
1365   VEX_LEN_0F16_P_0,
1366   VEX_LEN_0F16_P_2,
1367   VEX_LEN_0F17,
1368   VEX_LEN_0F41,
1369   VEX_LEN_0F42,
1370   VEX_LEN_0F44,
1371   VEX_LEN_0F45,
1372   VEX_LEN_0F46,
1373   VEX_LEN_0F47,
1374   VEX_LEN_0F4A,
1375   VEX_LEN_0F4B,
1376   VEX_LEN_0F6E,
1377   VEX_LEN_0F77,
1378   VEX_LEN_0F7E_P_1,
1379   VEX_LEN_0F7E_P_2,
1380   VEX_LEN_0F90,
1381   VEX_LEN_0F91,
1382   VEX_LEN_0F92,
1383   VEX_LEN_0F93,
1384   VEX_LEN_0F98,
1385   VEX_LEN_0F99,
1386   VEX_LEN_0FAE_R_2,
1387   VEX_LEN_0FAE_R_3,
1388   VEX_LEN_0FC4,
1389   VEX_LEN_0FD6,
1390   VEX_LEN_0F3816,
1391   VEX_LEN_0F3819,
1392   VEX_LEN_0F381A,
1393   VEX_LEN_0F3836,
1394   VEX_LEN_0F3841,
1395   VEX_LEN_0F3849_X86_64,
1396   VEX_LEN_0F384B_X86_64,
1397   VEX_LEN_0F385A,
1398   VEX_LEN_0F385C_X86_64,
1399   VEX_LEN_0F385E_X86_64,
1400   VEX_LEN_0F386C_X86_64,
1401   VEX_LEN_0F38CB_P_3_W_0,
1402   VEX_LEN_0F38CC_P_3_W_0,
1403   VEX_LEN_0F38CD_P_3_W_0,
1404   VEX_LEN_0F38DA_W_0_P_0,
1405   VEX_LEN_0F38DA_W_0_P_2,
1406   VEX_LEN_0F38DB,
1407   VEX_LEN_0F38F2,
1408   VEX_LEN_0F38F3,
1409   VEX_LEN_0F38F5,
1410   VEX_LEN_0F38F6,
1411   VEX_LEN_0F38F7,
1412   VEX_LEN_0F3A00,
1413   VEX_LEN_0F3A01,
1414   VEX_LEN_0F3A06,
1415   VEX_LEN_0F3A14,
1416   VEX_LEN_0F3A15,
1417   VEX_LEN_0F3A16,
1418   VEX_LEN_0F3A17,
1419   VEX_LEN_0F3A18,
1420   VEX_LEN_0F3A19,
1421   VEX_LEN_0F3A20,
1422   VEX_LEN_0F3A21,
1423   VEX_LEN_0F3A22,
1424   VEX_LEN_0F3A30,
1425   VEX_LEN_0F3A31,
1426   VEX_LEN_0F3A32,
1427   VEX_LEN_0F3A33,
1428   VEX_LEN_0F3A38,
1429   VEX_LEN_0F3A39,
1430   VEX_LEN_0F3A41,
1431   VEX_LEN_0F3A46,
1432   VEX_LEN_0F3A60,
1433   VEX_LEN_0F3A61,
1434   VEX_LEN_0F3A62,
1435   VEX_LEN_0F3A63,
1436   VEX_LEN_0F3ADE_W_0,
1437   VEX_LEN_0F3ADF,
1438   VEX_LEN_0F3AF0,
1439   VEX_LEN_MAP7_F8,
1440   VEX_LEN_XOP_08_85,
1441   VEX_LEN_XOP_08_86,
1442   VEX_LEN_XOP_08_87,
1443   VEX_LEN_XOP_08_8E,
1444   VEX_LEN_XOP_08_8F,
1445   VEX_LEN_XOP_08_95,
1446   VEX_LEN_XOP_08_96,
1447   VEX_LEN_XOP_08_97,
1448   VEX_LEN_XOP_08_9E,
1449   VEX_LEN_XOP_08_9F,
1450   VEX_LEN_XOP_08_A3,
1451   VEX_LEN_XOP_08_A6,
1452   VEX_LEN_XOP_08_B6,
1453   VEX_LEN_XOP_08_C0,
1454   VEX_LEN_XOP_08_C1,
1455   VEX_LEN_XOP_08_C2,
1456   VEX_LEN_XOP_08_C3,
1457   VEX_LEN_XOP_08_CC,
1458   VEX_LEN_XOP_08_CD,
1459   VEX_LEN_XOP_08_CE,
1460   VEX_LEN_XOP_08_CF,
1461   VEX_LEN_XOP_08_EC,
1462   VEX_LEN_XOP_08_ED,
1463   VEX_LEN_XOP_08_EE,
1464   VEX_LEN_XOP_08_EF,
1465   VEX_LEN_XOP_09_01,
1466   VEX_LEN_XOP_09_02,
1467   VEX_LEN_XOP_09_12,
1468   VEX_LEN_XOP_09_82_W_0,
1469   VEX_LEN_XOP_09_83_W_0,
1470   VEX_LEN_XOP_09_90,
1471   VEX_LEN_XOP_09_91,
1472   VEX_LEN_XOP_09_92,
1473   VEX_LEN_XOP_09_93,
1474   VEX_LEN_XOP_09_94,
1475   VEX_LEN_XOP_09_95,
1476   VEX_LEN_XOP_09_96,
1477   VEX_LEN_XOP_09_97,
1478   VEX_LEN_XOP_09_98,
1479   VEX_LEN_XOP_09_99,
1480   VEX_LEN_XOP_09_9A,
1481   VEX_LEN_XOP_09_9B,
1482   VEX_LEN_XOP_09_C1,
1483   VEX_LEN_XOP_09_C2,
1484   VEX_LEN_XOP_09_C3,
1485   VEX_LEN_XOP_09_C6,
1486   VEX_LEN_XOP_09_C7,
1487   VEX_LEN_XOP_09_CB,
1488   VEX_LEN_XOP_09_D1,
1489   VEX_LEN_XOP_09_D2,
1490   VEX_LEN_XOP_09_D3,
1491   VEX_LEN_XOP_09_D6,
1492   VEX_LEN_XOP_09_D7,
1493   VEX_LEN_XOP_09_DB,
1494   VEX_LEN_XOP_09_E1,
1495   VEX_LEN_XOP_09_E2,
1496   VEX_LEN_XOP_09_E3,
1497   VEX_LEN_XOP_0A_12,
1498 };
1499
1500 enum
1501 {
1502   EVEX_LEN_0F3816 = 0,
1503   EVEX_LEN_0F3819,
1504   EVEX_LEN_0F381A,
1505   EVEX_LEN_0F381B,
1506   EVEX_LEN_0F3836,
1507   EVEX_LEN_0F385A,
1508   EVEX_LEN_0F385B,
1509   EVEX_LEN_0F38C6,
1510   EVEX_LEN_0F38C7,
1511   EVEX_LEN_0F3A00,
1512   EVEX_LEN_0F3A01,
1513   EVEX_LEN_0F3A18,
1514   EVEX_LEN_0F3A19,
1515   EVEX_LEN_0F3A1A,
1516   EVEX_LEN_0F3A1B,
1517   EVEX_LEN_0F3A23,
1518   EVEX_LEN_0F3A38,
1519   EVEX_LEN_0F3A39,
1520   EVEX_LEN_0F3A3A,
1521   EVEX_LEN_0F3A3B,
1522   EVEX_LEN_0F3A43
1523 };
1524
1525 enum
1526 {
1527   VEX_W_0F41_L_1 = 0,
1528   VEX_W_0F42_L_1,
1529   VEX_W_0F44_L_0,
1530   VEX_W_0F45_L_1,
1531   VEX_W_0F46_L_1,
1532   VEX_W_0F47_L_1,
1533   VEX_W_0F4A_L_1,
1534   VEX_W_0F4B_L_1,
1535   VEX_W_0F90_L_0,
1536   VEX_W_0F91_L_0,
1537   VEX_W_0F92_L_0,
1538   VEX_W_0F93_L_0,
1539   VEX_W_0F98_L_0,
1540   VEX_W_0F99_L_0,
1541   VEX_W_0F380C,
1542   VEX_W_0F380D,
1543   VEX_W_0F380E,
1544   VEX_W_0F380F,
1545   VEX_W_0F3813,
1546   VEX_W_0F3816_L_1,
1547   VEX_W_0F3818,
1548   VEX_W_0F3819_L_1,
1549   VEX_W_0F381A_L_1,
1550   VEX_W_0F382C,
1551   VEX_W_0F382D,
1552   VEX_W_0F382E,
1553   VEX_W_0F382F,
1554   VEX_W_0F3836,
1555   VEX_W_0F3846,
1556   VEX_W_0F3849_X86_64_L_0,
1557   VEX_W_0F384B_X86_64_L_0,
1558   VEX_W_0F3850,
1559   VEX_W_0F3851,
1560   VEX_W_0F3852,
1561   VEX_W_0F3853,
1562   VEX_W_0F3858,
1563   VEX_W_0F3859,
1564   VEX_W_0F385A_L_0,
1565   VEX_W_0F385C_X86_64_L_0,
1566   VEX_W_0F385E_X86_64_L_0,
1567   VEX_W_0F386C_X86_64_L_0,
1568   VEX_W_0F3872_P_1,
1569   VEX_W_0F3878,
1570   VEX_W_0F3879,
1571   VEX_W_0F38B0,
1572   VEX_W_0F38B1,
1573   VEX_W_0F38B4,
1574   VEX_W_0F38B5,
1575   VEX_W_0F38CB_P_3,
1576   VEX_W_0F38CC_P_3,
1577   VEX_W_0F38CD_P_3,
1578   VEX_W_0F38CF,
1579   VEX_W_0F38D2,
1580   VEX_W_0F38D3,
1581   VEX_W_0F38DA,
1582   VEX_W_0F3A00_L_1,
1583   VEX_W_0F3A01_L_1,
1584   VEX_W_0F3A02,
1585   VEX_W_0F3A04,
1586   VEX_W_0F3A05,
1587   VEX_W_0F3A06_L_1,
1588   VEX_W_0F3A18_L_1,
1589   VEX_W_0F3A19_L_1,
1590   VEX_W_0F3A1D,
1591   VEX_W_0F3A38_L_1,
1592   VEX_W_0F3A39_L_1,
1593   VEX_W_0F3A46_L_1,
1594   VEX_W_0F3A4A,
1595   VEX_W_0F3A4B,
1596   VEX_W_0F3A4C,
1597   VEX_W_0F3ACE,
1598   VEX_W_0F3ACF,
1599   VEX_W_0F3ADE,
1600   VEX_W_MAP7_F8_L_0,
1601
1602   VEX_W_XOP_08_85_L_0,
1603   VEX_W_XOP_08_86_L_0,
1604   VEX_W_XOP_08_87_L_0,
1605   VEX_W_XOP_08_8E_L_0,
1606   VEX_W_XOP_08_8F_L_0,
1607   VEX_W_XOP_08_95_L_0,
1608   VEX_W_XOP_08_96_L_0,
1609   VEX_W_XOP_08_97_L_0,
1610   VEX_W_XOP_08_9E_L_0,
1611   VEX_W_XOP_08_9F_L_0,
1612   VEX_W_XOP_08_A6_L_0,
1613   VEX_W_XOP_08_B6_L_0,
1614   VEX_W_XOP_08_C0_L_0,
1615   VEX_W_XOP_08_C1_L_0,
1616   VEX_W_XOP_08_C2_L_0,
1617   VEX_W_XOP_08_C3_L_0,
1618   VEX_W_XOP_08_CC_L_0,
1619   VEX_W_XOP_08_CD_L_0,
1620   VEX_W_XOP_08_CE_L_0,
1621   VEX_W_XOP_08_CF_L_0,
1622   VEX_W_XOP_08_EC_L_0,
1623   VEX_W_XOP_08_ED_L_0,
1624   VEX_W_XOP_08_EE_L_0,
1625   VEX_W_XOP_08_EF_L_0,
1626
1627   VEX_W_XOP_09_80,
1628   VEX_W_XOP_09_81,
1629   VEX_W_XOP_09_82,
1630   VEX_W_XOP_09_83,
1631   VEX_W_XOP_09_C1_L_0,
1632   VEX_W_XOP_09_C2_L_0,
1633   VEX_W_XOP_09_C3_L_0,
1634   VEX_W_XOP_09_C6_L_0,
1635   VEX_W_XOP_09_C7_L_0,
1636   VEX_W_XOP_09_CB_L_0,
1637   VEX_W_XOP_09_D1_L_0,
1638   VEX_W_XOP_09_D2_L_0,
1639   VEX_W_XOP_09_D3_L_0,
1640   VEX_W_XOP_09_D6_L_0,
1641   VEX_W_XOP_09_D7_L_0,
1642   VEX_W_XOP_09_DB_L_0,
1643   VEX_W_XOP_09_E1_L_0,
1644   VEX_W_XOP_09_E2_L_0,
1645   VEX_W_XOP_09_E3_L_0,
1646
1647   EVEX_W_0F5B_P_0,
1648   EVEX_W_0F62,
1649   EVEX_W_0F66,
1650   EVEX_W_0F6A,
1651   EVEX_W_0F6B,
1652   EVEX_W_0F6C,
1653   EVEX_W_0F6D,
1654   EVEX_W_0F6F_P_1,
1655   EVEX_W_0F6F_P_2,
1656   EVEX_W_0F6F_P_3,
1657   EVEX_W_0F70_P_2,
1658   EVEX_W_0F72_R_2,
1659   EVEX_W_0F72_R_6,
1660   EVEX_W_0F73_R_2,
1661   EVEX_W_0F73_R_6,
1662   EVEX_W_0F76,
1663   EVEX_W_0F78_P_0,
1664   EVEX_W_0F78_P_2,
1665   EVEX_W_0F79_P_0,
1666   EVEX_W_0F79_P_2,
1667   EVEX_W_0F7A_P_1,
1668   EVEX_W_0F7A_P_2,
1669   EVEX_W_0F7A_P_3,
1670   EVEX_W_0F7B_P_2,
1671   EVEX_W_0F7E_P_1,
1672   EVEX_W_0F7F_P_1,
1673   EVEX_W_0F7F_P_2,
1674   EVEX_W_0F7F_P_3,
1675   EVEX_W_0FD2,
1676   EVEX_W_0FD3,
1677   EVEX_W_0FD4,
1678   EVEX_W_0FD6,
1679   EVEX_W_0FE6_P_1,
1680   EVEX_W_0FE7,
1681   EVEX_W_0FF2,
1682   EVEX_W_0FF3,
1683   EVEX_W_0FF4,
1684   EVEX_W_0FFA,
1685   EVEX_W_0FFB,
1686   EVEX_W_0FFE,
1687
1688   EVEX_W_0F3810_P_1,
1689   EVEX_W_0F3810_P_2,
1690   EVEX_W_0F3811_P_1,
1691   EVEX_W_0F3811_P_2,
1692   EVEX_W_0F3812_P_1,
1693   EVEX_W_0F3812_P_2,
1694   EVEX_W_0F3813_P_1,
1695   EVEX_W_0F3814_P_1,
1696   EVEX_W_0F3815_P_1,
1697   EVEX_W_0F3819_L_n,
1698   EVEX_W_0F381A_L_n,
1699   EVEX_W_0F381B_L_2,
1700   EVEX_W_0F381E,
1701   EVEX_W_0F381F,
1702   EVEX_W_0F3820_P_1,
1703   EVEX_W_0F3821_P_1,
1704   EVEX_W_0F3822_P_1,
1705   EVEX_W_0F3823_P_1,
1706   EVEX_W_0F3824_P_1,
1707   EVEX_W_0F3825_P_1,
1708   EVEX_W_0F3825_P_2,
1709   EVEX_W_0F3828_P_2,
1710   EVEX_W_0F3829_P_2,
1711   EVEX_W_0F382A_P_1,
1712   EVEX_W_0F382A_P_2,
1713   EVEX_W_0F382B,
1714   EVEX_W_0F3830_P_1,
1715   EVEX_W_0F3831_P_1,
1716   EVEX_W_0F3832_P_1,
1717   EVEX_W_0F3833_P_1,
1718   EVEX_W_0F3834_P_1,
1719   EVEX_W_0F3835_P_1,
1720   EVEX_W_0F3835_P_2,
1721   EVEX_W_0F3837,
1722   EVEX_W_0F383A_P_1,
1723   EVEX_W_0F3859,
1724   EVEX_W_0F385A_L_n,
1725   EVEX_W_0F385B_L_2,
1726   EVEX_W_0F3870,
1727   EVEX_W_0F3872_P_2,
1728   EVEX_W_0F387A,
1729   EVEX_W_0F387B,
1730   EVEX_W_0F3883,
1731
1732   EVEX_W_0F3A18_L_n,
1733   EVEX_W_0F3A19_L_n,
1734   EVEX_W_0F3A1A_L_2,
1735   EVEX_W_0F3A1B_L_2,
1736   EVEX_W_0F3A21,
1737   EVEX_W_0F3A23_L_n,
1738   EVEX_W_0F3A38_L_n,
1739   EVEX_W_0F3A39_L_n,
1740   EVEX_W_0F3A3A_L_2,
1741   EVEX_W_0F3A3B_L_2,
1742   EVEX_W_0F3A42,
1743   EVEX_W_0F3A43_L_n,
1744   EVEX_W_0F3A70,
1745   EVEX_W_0F3A72,
1746
1747   EVEX_W_MAP4_8F_R_0,
1748   EVEX_W_MAP4_FF_R_6,
1749
1750   EVEX_W_MAP5_5B_P_0,
1751   EVEX_W_MAP5_7A_P_3,
1752 };
1753
1754 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1755
1756 struct dis386 {
1757   const char *name;
1758   struct
1759     {
1760       op_rtn rtn;
1761       int bytemode;
1762     } op[MAX_OPERANDS];
1763   unsigned int prefix_requirement;
1764 };
1765
1766 /* Upper case letters in the instruction names here are macros.
1767    'A' => print 'b' if no (suitable) register operand or suffix_always is true
1768    'B' => print 'b' if suffix_always is true
1769    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1770           size prefix
1771    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1772           suffix_always is true
1773    'E' => print 'e' if 32-bit form of jcxz
1774    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1775    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1776    'H' => print ",pt" or ",pn" branch hint
1777    'I' unused.
1778    'J' unused.
1779    'K' => print 'd' or 'q' if rex prefix is present.
1780    'L' => print 'l' or 'q' if suffix_always is true
1781    'M' => print 'r' if intel_mnemonic is false.
1782    'N' => print 'n' if instruction has no wait "prefix"
1783    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1784    'P' => behave as 'T' except with register operand outside of suffix_always
1785           mode
1786    'Q' => print 'w', 'l' or 'q' if no (suitable) register operand or
1787           suffix_always is true
1788    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1789    'S' => print 'w', 'l' or 'q' if suffix_always is true
1790    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1791           prefix or if suffix_always is true.
1792    'U' unused.
1793    'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1794    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1795    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1796    'Y' => no output, mark EVEX.aaa != 0 as bad.
1797    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1798    '!' => change condition from true to false or from false to true.
1799    '%' => add 1 upper case letter to the macro.
1800    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1801           prefix or suffix_always is true (lcall/ljmp).
1802    '@' => in 64bit mode for Intel64 ISA or if instruction
1803           has no operand sizing prefix, print 'q' if suffix_always is true or
1804           nothing otherwise; behave as 'P' in all other cases
1805
1806    2 upper case letter macros:
1807    "XY" => print 'x' or 'y' if suffix_always is true or no register
1808            operands and no broadcast.
1809    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1810            register operands and no broadcast.
1811    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1812    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1813    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1814    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1815    "XV" => print "{vex} " pseudo prefix
1816    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1817            is used by an EVEX-encoded (AVX512VL) instruction.
1818    "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1819    "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1820    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1821            being false, or no operand at all in 64bit mode, or if suffix_always
1822            is true.
1823    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1824    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1825    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1826    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1827    "BW" => print 'b' or 'w' depending on the VEX.W bit
1828    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1829            an operand size prefix, or suffix_always is true.  print
1830            'q' if rex prefix is present.
1831
1832    Many of the above letters print nothing in Intel mode.  See "putop"
1833    for the details.
1834
1835    Braces '{' and '}', and vertical bars '|', indicate alternative
1836    mnemonic strings for AT&T and Intel.  */
1837
1838 static const struct dis386 dis386[] = {
1839   /* 00 */
1840   { "addB",             { Ebh1, Gb }, 0 },
1841   { "addS",             { Evh1, Gv }, 0 },
1842   { "addB",             { Gb, EbS }, 0 },
1843   { "addS",             { Gv, EvS }, 0 },
1844   { "addB",             { AL, Ib }, 0 },
1845   { "addS",             { eAX, Iv }, 0 },
1846   { X86_64_TABLE (X86_64_06) },
1847   { X86_64_TABLE (X86_64_07) },
1848   /* 08 */
1849   { "orB",              { Ebh1, Gb }, 0 },
1850   { "orS",              { Evh1, Gv }, 0 },
1851   { "orB",              { Gb, EbS }, 0 },
1852   { "orS",              { Gv, EvS }, 0 },
1853   { "orB",              { AL, Ib }, 0 },
1854   { "orS",              { eAX, Iv }, 0 },
1855   { X86_64_TABLE (X86_64_0E) },
1856   { Bad_Opcode },       /* 0x0f extended opcode escape */
1857   /* 10 */
1858   { "adcB",             { Ebh1, Gb }, 0 },
1859   { "adcS",             { Evh1, Gv }, 0 },
1860   { "adcB",             { Gb, EbS }, 0 },
1861   { "adcS",             { Gv, EvS }, 0 },
1862   { "adcB",             { AL, Ib }, 0 },
1863   { "adcS",             { eAX, Iv }, 0 },
1864   { X86_64_TABLE (X86_64_16) },
1865   { X86_64_TABLE (X86_64_17) },
1866   /* 18 */
1867   { "sbbB",             { Ebh1, Gb }, 0 },
1868   { "sbbS",             { Evh1, Gv }, 0 },
1869   { "sbbB",             { Gb, EbS }, 0 },
1870   { "sbbS",             { Gv, EvS }, 0 },
1871   { "sbbB",             { AL, Ib }, 0 },
1872   { "sbbS",             { eAX, Iv }, 0 },
1873   { X86_64_TABLE (X86_64_1E) },
1874   { X86_64_TABLE (X86_64_1F) },
1875   /* 20 */
1876   { "andB",             { Ebh1, Gb }, 0 },
1877   { "andS",             { Evh1, Gv }, 0 },
1878   { "andB",             { Gb, EbS }, 0 },
1879   { "andS",             { Gv, EvS }, 0 },
1880   { "andB",             { AL, Ib }, 0 },
1881   { "andS",             { eAX, Iv }, 0 },
1882   { Bad_Opcode },       /* SEG ES prefix */
1883   { X86_64_TABLE (X86_64_27) },
1884   /* 28 */
1885   { "subB",             { Ebh1, Gb }, 0 },
1886   { "subS",             { Evh1, Gv }, 0 },
1887   { "subB",             { Gb, EbS }, 0 },
1888   { "subS",             { Gv, EvS }, 0 },
1889   { "subB",             { AL, Ib }, 0 },
1890   { "subS",             { eAX, Iv }, 0 },
1891   { Bad_Opcode },       /* SEG CS prefix */
1892   { X86_64_TABLE (X86_64_2F) },
1893   /* 30 */
1894   { "xorB",             { Ebh1, Gb }, 0 },
1895   { "xorS",             { Evh1, Gv }, 0 },
1896   { "xorB",             { Gb, EbS }, 0 },
1897   { "xorS",             { Gv, EvS }, 0 },
1898   { "xorB",             { AL, Ib }, 0 },
1899   { "xorS",             { eAX, Iv }, 0 },
1900   { Bad_Opcode },       /* SEG SS prefix */
1901   { X86_64_TABLE (X86_64_37) },
1902   /* 38 */
1903   { "cmpB",             { Eb, Gb }, 0 },
1904   { "cmpS",             { Ev, Gv }, 0 },
1905   { "cmpB",             { Gb, EbS }, 0 },
1906   { "cmpS",             { Gv, EvS }, 0 },
1907   { "cmpB",             { AL, Ib }, 0 },
1908   { "cmpS",             { eAX, Iv }, 0 },
1909   { Bad_Opcode },       /* SEG DS prefix */
1910   { X86_64_TABLE (X86_64_3F) },
1911   /* 40 */
1912   { "inc{S|}",          { RMeAX }, 0 },
1913   { "inc{S|}",          { RMeCX }, 0 },
1914   { "inc{S|}",          { RMeDX }, 0 },
1915   { "inc{S|}",          { RMeBX }, 0 },
1916   { "inc{S|}",          { RMeSP }, 0 },
1917   { "inc{S|}",          { RMeBP }, 0 },
1918   { "inc{S|}",          { RMeSI }, 0 },
1919   { "inc{S|}",          { RMeDI }, 0 },
1920   /* 48 */
1921   { "dec{S|}",          { RMeAX }, 0 },
1922   { "dec{S|}",          { RMeCX }, 0 },
1923   { "dec{S|}",          { RMeDX }, 0 },
1924   { "dec{S|}",          { RMeBX }, 0 },
1925   { "dec{S|}",          { RMeSP }, 0 },
1926   { "dec{S|}",          { RMeBP }, 0 },
1927   { "dec{S|}",          { RMeSI }, 0 },
1928   { "dec{S|}",          { RMeDI }, 0 },
1929   /* 50 */
1930   { "push!P",           { RMrAX }, 0 },
1931   { "push!P",           { RMrCX }, 0 },
1932   { "push!P",           { RMrDX }, 0 },
1933   { "push!P",           { RMrBX }, 0 },
1934   { "push!P",           { RMrSP }, 0 },
1935   { "push!P",           { RMrBP }, 0 },
1936   { "push!P",           { RMrSI }, 0 },
1937   { "push!P",           { RMrDI }, 0 },
1938   /* 58 */
1939   { "pop!P",            { RMrAX }, 0 },
1940   { "pop!P",            { RMrCX }, 0 },
1941   { "pop!P",            { RMrDX }, 0 },
1942   { "pop!P",            { RMrBX }, 0 },
1943   { "pop!P",            { RMrSP }, 0 },
1944   { "pop!P",            { RMrBP }, 0 },
1945   { "pop!P",            { RMrSI }, 0 },
1946   { "pop!P",            { RMrDI }, 0 },
1947   /* 60 */
1948   { X86_64_TABLE (X86_64_60) },
1949   { X86_64_TABLE (X86_64_61) },
1950   { X86_64_TABLE (X86_64_62) },
1951   { X86_64_TABLE (X86_64_63) },
1952   { Bad_Opcode },       /* seg fs */
1953   { Bad_Opcode },       /* seg gs */
1954   { Bad_Opcode },       /* op size prefix */
1955   { Bad_Opcode },       /* adr size prefix */
1956   /* 68 */
1957   { "pushP",            { sIv }, 0 },
1958   { "imulS",            { Gv, Ev, Iv }, 0 },
1959   { "pushP",            { sIbT }, 0 },
1960   { "imulS",            { Gv, Ev, sIb }, 0 },
1961   { "ins{b|}",          { Ybr, indirDX }, 0 },
1962   { X86_64_TABLE (X86_64_6D) },
1963   { "outs{b|}",         { indirDXr, Xb }, 0 },
1964   { X86_64_TABLE (X86_64_6F) },
1965   /* 70 */
1966   { "joH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1967   { "jnoH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1968   { "jbH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1969   { "jaeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1970   { "jeH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1971   { "jneH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1972   { "jbeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1973   { "jaH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1974   /* 78 */
1975   { "jsH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1976   { "jnsH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1977   { "jpH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1978   { "jnpH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1979   { "jlH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1980   { "jgeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1981   { "jleH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1982   { "jgH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1983   /* 80 */
1984   { REG_TABLE (REG_80) },
1985   { REG_TABLE (REG_81) },
1986   { X86_64_TABLE (X86_64_82) },
1987   { REG_TABLE (REG_83) },
1988   { "testB",            { Eb, Gb }, 0 },
1989   { "testS",            { Ev, Gv }, 0 },
1990   { "xchgB",            { Ebh2, Gb }, 0 },
1991   { "xchgS",            { Evh2, Gv }, 0 },
1992   /* 88 */
1993   { "movB",             { Ebh3, Gb }, 0 },
1994   { "movS",             { Evh3, Gv }, 0 },
1995   { "movB",             { Gb, EbS }, 0 },
1996   { "movS",             { Gv, EvS }, 0 },
1997   { "movD",             { Sv, Sw }, 0 },
1998   { "leaS",             { Gv, M }, 0 },
1999   { "movD",             { Sw, Sv }, 0 },
2000   { REG_TABLE (REG_8F) },
2001   /* 90 */
2002   { PREFIX_TABLE (PREFIX_90) },
2003   { "xchgS",            { RMeCX, eAX }, 0 },
2004   { "xchgS",            { RMeDX, eAX }, 0 },
2005   { "xchgS",            { RMeBX, eAX }, 0 },
2006   { "xchgS",            { RMeSP, eAX }, 0 },
2007   { "xchgS",            { RMeBP, eAX }, 0 },
2008   { "xchgS",            { RMeSI, eAX }, 0 },
2009   { "xchgS",            { RMeDI, eAX }, 0 },
2010   /* 98 */
2011   { "cW{t|}R",          { XX }, 0 },
2012   { "cR{t|}O",          { XX }, 0 },
2013   { X86_64_TABLE (X86_64_9A) },
2014   { Bad_Opcode },       /* fwait */
2015   { "pushfP",           { XX }, 0 },
2016   { "popfP",            { XX }, 0 },
2017   { "sahf",             { XX }, 0 },
2018   { "lahf",             { XX }, 0 },
2019   /* a0 */
2020   { "mov%LB",           { AL, Ob }, PREFIX_REX2_ILLEGAL },
2021   { "mov%LS",           { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2022   { "mov%LB",           { Ob, AL }, PREFIX_REX2_ILLEGAL },
2023   { "mov%LS",           { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2024   { "movs{b|}",         { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2025   { "movs{R|}",         { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2026   { "cmps{b|}",         { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2027   { "cmps{R|}",         { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2028   /* a8 */
2029   { "testB",            { AL, Ib }, PREFIX_REX2_ILLEGAL },
2030   { "testS",            { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2031   { "stosB",            { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2032   { "stosS",            { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2033   { "lodsB",            { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2034   { "lodsS",            { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2035   { "scasB",            { AL, Yb }, PREFIX_REX2_ILLEGAL },
2036   { "scasS",            { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2037   /* b0 */
2038   { "movB",             { RMAL, Ib }, 0 },
2039   { "movB",             { RMCL, Ib }, 0 },
2040   { "movB",             { RMDL, Ib }, 0 },
2041   { "movB",             { RMBL, Ib }, 0 },
2042   { "movB",             { RMAH, Ib }, 0 },
2043   { "movB",             { RMCH, Ib }, 0 },
2044   { "movB",             { RMDH, Ib }, 0 },
2045   { "movB",             { RMBH, Ib }, 0 },
2046   /* b8 */
2047   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2048   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2049   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2050   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2051   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2052   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2053   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2054   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2055   /* c0 */
2056   { REG_TABLE (REG_C0) },
2057   { REG_TABLE (REG_C1) },
2058   { X86_64_TABLE (X86_64_C2) },
2059   { X86_64_TABLE (X86_64_C3) },
2060   { X86_64_TABLE (X86_64_C4) },
2061   { X86_64_TABLE (X86_64_C5) },
2062   { REG_TABLE (REG_C6) },
2063   { REG_TABLE (REG_C7) },
2064   /* c8 */
2065   { "enterP",           { Iw, Ib }, 0 },
2066   { "leaveP",           { XX }, 0 },
2067   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2068   { "{l|}ret{|f}%LP",   { XX }, 0 },
2069   { "int3",             { XX }, 0 },
2070   { "int",              { Ib }, 0 },
2071   { X86_64_TABLE (X86_64_CE) },
2072   { "iret%LP",          { XX }, 0 },
2073   /* d0 */
2074   { REG_TABLE (REG_D0) },
2075   { REG_TABLE (REG_D1) },
2076   { REG_TABLE (REG_D2) },
2077   { REG_TABLE (REG_D3) },
2078   { X86_64_TABLE (X86_64_D4) },
2079   { X86_64_TABLE (X86_64_D5) },
2080   { Bad_Opcode },
2081   { "xlat",             { DSBX }, 0 },
2082   /* d8 */
2083   { FLOAT },
2084   { FLOAT },
2085   { FLOAT },
2086   { FLOAT },
2087   { FLOAT },
2088   { FLOAT },
2089   { FLOAT },
2090   { FLOAT },
2091   /* e0 */
2092   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2093   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2094   { "loopFH",           { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2095   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2096   { "inB",              { AL, Ib }, PREFIX_REX2_ILLEGAL },
2097   { "inG",              { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2098   { "outB",             { Ib, AL }, PREFIX_REX2_ILLEGAL },
2099   { "outG",             { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2100   /* e8 */
2101   { X86_64_TABLE (X86_64_E8) },
2102   { X86_64_TABLE (X86_64_E9) },
2103   { X86_64_TABLE (X86_64_EA) },
2104   { "jmp",              { Jb, BND }, PREFIX_REX2_ILLEGAL },
2105   { "inB",              { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2106   { "inG",              { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2107   { "outB",             { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2108   { "outG",             { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2109   /* f0 */
2110   { Bad_Opcode },       /* lock prefix */
2111   { "int1",             { XX }, 0 },
2112   { Bad_Opcode },       /* repne */
2113   { Bad_Opcode },       /* repz */
2114   { "hlt",              { XX }, 0 },
2115   { "cmc",              { XX }, 0 },
2116   { REG_TABLE (REG_F6) },
2117   { REG_TABLE (REG_F7) },
2118   /* f8 */
2119   { "clc",              { XX }, 0 },
2120   { "stc",              { XX }, 0 },
2121   { "cli",              { XX }, 0 },
2122   { "sti",              { XX }, 0 },
2123   { "cld",              { XX }, 0 },
2124   { "std",              { XX }, 0 },
2125   { REG_TABLE (REG_FE) },
2126   { REG_TABLE (REG_FF) },
2127 };
2128
2129 static const struct dis386 dis386_twobyte[] = {
2130   /* 00 */
2131   { REG_TABLE (REG_0F00 ) },
2132   { REG_TABLE (REG_0F01 ) },
2133   { "larS",             { Gv, Sv }, 0 },
2134   { "lslS",             { Gv, Sv }, 0 },
2135   { Bad_Opcode },
2136   { "syscall",          { XX }, 0 },
2137   { "clts",             { XX }, 0 },
2138   { "sysret%LQ",                { XX }, 0 },
2139   /* 08 */
2140   { "invd",             { XX }, 0 },
2141   { PREFIX_TABLE (PREFIX_0F09) },
2142   { Bad_Opcode },
2143   { "ud2",              { XX }, 0 },
2144   { Bad_Opcode },
2145   { REG_TABLE (REG_0F0D) },
2146   { "femms",            { XX }, 0 },
2147   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2148   /* 10 */
2149   { PREFIX_TABLE (PREFIX_0F10) },
2150   { PREFIX_TABLE (PREFIX_0F11) },
2151   { PREFIX_TABLE (PREFIX_0F12) },
2152   { "movlpX",           { Mq, XM }, PREFIX_OPCODE },
2153   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2154   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2155   { PREFIX_TABLE (PREFIX_0F16) },
2156   { "movhpX",           { Mq, XM }, PREFIX_OPCODE },
2157   /* 18 */
2158   { REG_TABLE (REG_0F18) },
2159   { "nopQ",             { Ev }, 0 },
2160   { PREFIX_TABLE (PREFIX_0F1A) },
2161   { PREFIX_TABLE (PREFIX_0F1B) },
2162   { PREFIX_TABLE (PREFIX_0F1C) },
2163   { "nopQ",             { Ev }, 0 },
2164   { PREFIX_TABLE (PREFIX_0F1E) },
2165   { "nopQ",             { Ev }, 0 },
2166   /* 20 */
2167   { "movZ",             { Em, Cm }, 0 },
2168   { "movZ",             { Em, Dm }, 0 },
2169   { "movZ",             { Cm, Em }, 0 },
2170   { "movZ",             { Dm, Em }, 0 },
2171   { X86_64_TABLE (X86_64_0F24) },
2172   { Bad_Opcode },
2173   { X86_64_TABLE (X86_64_0F26) },
2174   { Bad_Opcode },
2175   /* 28 */
2176   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2177   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2178   { PREFIX_TABLE (PREFIX_0F2A) },
2179   { PREFIX_TABLE (PREFIX_0F2B) },
2180   { PREFIX_TABLE (PREFIX_0F2C) },
2181   { PREFIX_TABLE (PREFIX_0F2D) },
2182   { PREFIX_TABLE (PREFIX_0F2E) },
2183   { PREFIX_TABLE (PREFIX_0F2F) },
2184   /* 30 */
2185   { "wrmsr",            { XX }, PREFIX_REX2_ILLEGAL },
2186   { "rdtsc",            { XX }, PREFIX_REX2_ILLEGAL },
2187   { "rdmsr",            { XX }, PREFIX_REX2_ILLEGAL },
2188   { "rdpmc",            { XX }, PREFIX_REX2_ILLEGAL },
2189   { "sysenter",         { SEP }, PREFIX_REX2_ILLEGAL },
2190   { "sysexit%LQ",       { SEP }, PREFIX_REX2_ILLEGAL },
2191   { Bad_Opcode },
2192   { "getsec",           { XX }, 0 },
2193   /* 38 */
2194   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2195   { Bad_Opcode },
2196   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2197   { Bad_Opcode },
2198   { Bad_Opcode },
2199   { Bad_Opcode },
2200   { Bad_Opcode },
2201   { Bad_Opcode },
2202   /* 40 */
2203   { "cmovoS",           { Gv, Ev }, 0 },
2204   { "cmovnoS",          { Gv, Ev }, 0 },
2205   { "cmovbS",           { Gv, Ev }, 0 },
2206   { "cmovaeS",          { Gv, Ev }, 0 },
2207   { "cmoveS",           { Gv, Ev }, 0 },
2208   { "cmovneS",          { Gv, Ev }, 0 },
2209   { "cmovbeS",          { Gv, Ev }, 0 },
2210   { "cmovaS",           { Gv, Ev }, 0 },
2211   /* 48 */
2212   { "cmovsS",           { Gv, Ev }, 0 },
2213   { "cmovnsS",          { Gv, Ev }, 0 },
2214   { "cmovpS",           { Gv, Ev }, 0 },
2215   { "cmovnpS",          { Gv, Ev }, 0 },
2216   { "cmovlS",           { Gv, Ev }, 0 },
2217   { "cmovgeS",          { Gv, Ev }, 0 },
2218   { "cmovleS",          { Gv, Ev }, 0 },
2219   { "cmovgS",           { Gv, Ev }, 0 },
2220   /* 50 */
2221   { "movmskpX",         { Gdq, Ux }, PREFIX_OPCODE },
2222   { PREFIX_TABLE (PREFIX_0F51) },
2223   { PREFIX_TABLE (PREFIX_0F52) },
2224   { PREFIX_TABLE (PREFIX_0F53) },
2225   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2226   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2227   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2228   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2229   /* 58 */
2230   { PREFIX_TABLE (PREFIX_0F58) },
2231   { PREFIX_TABLE (PREFIX_0F59) },
2232   { PREFIX_TABLE (PREFIX_0F5A) },
2233   { PREFIX_TABLE (PREFIX_0F5B) },
2234   { PREFIX_TABLE (PREFIX_0F5C) },
2235   { PREFIX_TABLE (PREFIX_0F5D) },
2236   { PREFIX_TABLE (PREFIX_0F5E) },
2237   { PREFIX_TABLE (PREFIX_0F5F) },
2238   /* 60 */
2239   { PREFIX_TABLE (PREFIX_0F60) },
2240   { PREFIX_TABLE (PREFIX_0F61) },
2241   { PREFIX_TABLE (PREFIX_0F62) },
2242   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2243   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2244   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2245   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2246   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2247   /* 68 */
2248   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2249   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2250   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2251   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2252   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2253   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2254   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2255   { PREFIX_TABLE (PREFIX_0F6F) },
2256   /* 70 */
2257   { PREFIX_TABLE (PREFIX_0F70) },
2258   { REG_TABLE (REG_0F71) },
2259   { REG_TABLE (REG_0F72) },
2260   { REG_TABLE (REG_0F73) },
2261   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2262   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2263   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2264   { "emms",             { XX }, PREFIX_OPCODE },
2265   /* 78 */
2266   { PREFIX_TABLE (PREFIX_0F78) },
2267   { PREFIX_TABLE (PREFIX_0F79) },
2268   { Bad_Opcode },
2269   { Bad_Opcode },
2270   { PREFIX_TABLE (PREFIX_0F7C) },
2271   { PREFIX_TABLE (PREFIX_0F7D) },
2272   { PREFIX_TABLE (PREFIX_0F7E) },
2273   { PREFIX_TABLE (PREFIX_0F7F) },
2274   /* 80 */
2275   { "joH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2276   { "jnoH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2277   { "jbH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2278   { "jaeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2279   { "jeH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2280   { "jneH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2281   { "jbeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2282   { "jaH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2283   /* 88 */
2284   { "jsH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2285   { "jnsH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2286   { "jpH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2287   { "jnpH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2288   { "jlH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2289   { "jgeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2290   { "jleH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2291   { "jgH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2292   /* 90 */
2293   { "seto",             { Eb }, 0 },
2294   { "setno",            { Eb }, 0 },
2295   { "setb",             { Eb }, 0 },
2296   { "setae",            { Eb }, 0 },
2297   { "sete",             { Eb }, 0 },
2298   { "setne",            { Eb }, 0 },
2299   { "setbe",            { Eb }, 0 },
2300   { "seta",             { Eb }, 0 },
2301   /* 98 */
2302   { "sets",             { Eb }, 0 },
2303   { "setns",            { Eb }, 0 },
2304   { "setp",             { Eb }, 0 },
2305   { "setnp",            { Eb }, 0 },
2306   { "setl",             { Eb }, 0 },
2307   { "setge",            { Eb }, 0 },
2308   { "setle",            { Eb }, 0 },
2309   { "setg",             { Eb }, 0 },
2310   /* a0 */
2311   { "pushP",            { fs }, 0 },
2312   { "popP",             { fs }, 0 },
2313   { "cpuid",            { XX }, 0 },
2314   { "btS",              { Ev, Gv }, 0 },
2315   { "shldS",            { Ev, Gv, Ib }, 0 },
2316   { "shldS",            { Ev, Gv, CL }, 0 },
2317   { REG_TABLE (REG_0FA6) },
2318   { REG_TABLE (REG_0FA7) },
2319   /* a8 */
2320   { "pushP",            { gs }, 0 },
2321   { "popP",             { gs }, 0 },
2322   { "rsm",              { XX }, 0 },
2323   { "btsS",             { Evh1, Gv }, 0 },
2324   { "shrdS",            { Ev, Gv, Ib }, 0 },
2325   { "shrdS",            { Ev, Gv, CL }, 0 },
2326   { REG_TABLE (REG_0FAE) },
2327   { "imulS",            { Gv, Ev }, 0 },
2328   /* b0 */
2329   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2330   { "cmpxchgS",         { Evh1, Gv }, 0 },
2331   { "lssS",             { Gv, Mp }, 0 },
2332   { "btrS",             { Evh1, Gv }, 0 },
2333   { "lfsS",             { Gv, Mp }, 0 },
2334   { "lgsS",             { Gv, Mp }, 0 },
2335   { "movz{bR|x}",       { Gv, Eb }, 0 },
2336   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2337   /* b8 */
2338   { PREFIX_TABLE (PREFIX_0FB8) },
2339   { "ud1S",             { Gv, Ev }, 0 },
2340   { REG_TABLE (REG_0FBA) },
2341   { "btcS",             { Evh1, Gv }, 0 },
2342   { PREFIX_TABLE (PREFIX_0FBC) },
2343   { PREFIX_TABLE (PREFIX_0FBD) },
2344   { "movs{bR|x}",       { Gv, Eb }, 0 },
2345   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2346   /* c0 */
2347   { "xaddB",            { Ebh1, Gb }, 0 },
2348   { "xaddS",            { Evh1, Gv }, 0 },
2349   { PREFIX_TABLE (PREFIX_0FC2) },
2350   { "movntiS",          { Mdq, Gdq }, PREFIX_OPCODE },
2351   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2352   { "pextrw",           { Gd, Nq, Ib }, PREFIX_OPCODE },
2353   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2354   { REG_TABLE (REG_0FC7) },
2355   /* c8 */
2356   { "bswap",            { RMeAX }, 0 },
2357   { "bswap",            { RMeCX }, 0 },
2358   { "bswap",            { RMeDX }, 0 },
2359   { "bswap",            { RMeBX }, 0 },
2360   { "bswap",            { RMeSP }, 0 },
2361   { "bswap",            { RMeBP }, 0 },
2362   { "bswap",            { RMeSI }, 0 },
2363   { "bswap",            { RMeDI }, 0 },
2364   /* d0 */
2365   { PREFIX_TABLE (PREFIX_0FD0) },
2366   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2367   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2368   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2369   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2370   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2371   { PREFIX_TABLE (PREFIX_0FD6) },
2372   { "pmovmskb",         { Gdq, Nq }, PREFIX_OPCODE },
2373   /* d8 */
2374   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2375   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2376   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2377   { "pand",             { MX, EM }, PREFIX_OPCODE },
2378   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2379   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2380   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2381   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2382   /* e0 */
2383   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2384   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2385   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2386   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2387   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2388   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2389   { PREFIX_TABLE (PREFIX_0FE6) },
2390   { PREFIX_TABLE (PREFIX_0FE7) },
2391   /* e8 */
2392   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2393   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2394   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2395   { "por",              { MX, EM }, PREFIX_OPCODE },
2396   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2397   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2398   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2399   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2400   /* f0 */
2401   { PREFIX_TABLE (PREFIX_0FF0) },
2402   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2403   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2404   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2405   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2406   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2407   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2408   { PREFIX_TABLE (PREFIX_0FF7) },
2409   /* f8 */
2410   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2411   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2412   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2413   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2414   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2415   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2416   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2417   { "ud0S",             { Gv, Ev }, 0 },
2418 };
2419
2420 static const bool onebyte_has_modrm[256] = {
2421   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2422   /*       -------------------------------        */
2423   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2424   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2425   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2426   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2427   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2428   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2429   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2430   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2431   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2432   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2433   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2434   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2435   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2436   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2437   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2438   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2439   /*       -------------------------------        */
2440   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2441 };
2442
2443 static const bool twobyte_has_modrm[256] = {
2444   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2445   /*       -------------------------------        */
2446   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2447   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2448   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2449   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2450   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2451   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2452   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2453   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2454   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2455   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2456   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2457   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2458   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2459   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2460   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2461   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2462   /*       -------------------------------        */
2463   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2464 };
2465
2466
2467 struct op
2468   {
2469     const char *name;
2470     unsigned int len;
2471   };
2472
2473 /* If we are accessing mod/rm/reg without need_modrm set, then the
2474    values are stale.  Hitting this abort likely indicates that you
2475    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2476 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2477
2478 static const char intel_index16[][6] = {
2479   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2480 };
2481
2482 static const char att_names64[][8] = {
2483   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2484   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2485   "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2486   "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2487 };
2488 static const char att_names32[][8] = {
2489   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2490   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2491   "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2492   "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2493 };
2494 static const char att_names16[][8] = {
2495   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2496   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2497   "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2498   "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2499 };
2500 static const char att_names8[][8] = {
2501   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2502 };
2503 static const char att_names8rex[][8] = {
2504   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2505   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2506   "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2507   "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2508 };
2509 static const char att_names_seg[][4] = {
2510   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2511 };
2512 static const char att_index64[] = "%riz";
2513 static const char att_index32[] = "%eiz";
2514 static const char att_index16[][8] = {
2515   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2516 };
2517
2518 static const char att_names_mm[][8] = {
2519   "%mm0", "%mm1", "%mm2", "%mm3",
2520   "%mm4", "%mm5", "%mm6", "%mm7"
2521 };
2522
2523 static const char att_names_bnd[][8] = {
2524   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2525 };
2526
2527 static const char att_names_xmm[][8] = {
2528   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2529   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2530   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2531   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2532   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2533   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2534   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2535   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2536 };
2537
2538 static const char att_names_ymm[][8] = {
2539   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2540   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2541   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2542   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2543   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2544   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2545   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2546   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2547 };
2548
2549 static const char att_names_zmm[][8] = {
2550   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2551   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2552   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2553   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2554   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2555   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2556   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2557   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2558 };
2559
2560 static const char att_names_tmm[][8] = {
2561   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2562   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2563 };
2564
2565 static const char att_names_mask[][8] = {
2566   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2567 };
2568
2569 static const char *const names_rounding[] =
2570 {
2571   "{rn-",
2572   "{rd-",
2573   "{ru-",
2574   "{rz-"
2575 };
2576
2577 static const struct dis386 reg_table[][8] = {
2578   /* REG_80 */
2579   {
2580     { "addA",   { Ebh1, Ib }, 0 },
2581     { "orA",    { Ebh1, Ib }, 0 },
2582     { "adcA",   { Ebh1, Ib }, 0 },
2583     { "sbbA",   { Ebh1, Ib }, 0 },
2584     { "andA",   { Ebh1, Ib }, 0 },
2585     { "subA",   { Ebh1, Ib }, 0 },
2586     { "xorA",   { Ebh1, Ib }, 0 },
2587     { "cmpA",   { Eb, Ib }, 0 },
2588   },
2589   /* REG_81 */
2590   {
2591     { "addQ",   { Evh1, Iv }, 0 },
2592     { "orQ",    { Evh1, Iv }, 0 },
2593     { "adcQ",   { Evh1, Iv }, 0 },
2594     { "sbbQ",   { Evh1, Iv }, 0 },
2595     { "andQ",   { Evh1, Iv }, 0 },
2596     { "subQ",   { Evh1, Iv }, 0 },
2597     { "xorQ",   { Evh1, Iv }, 0 },
2598     { "cmpQ",   { Ev, Iv }, 0 },
2599   },
2600   /* REG_83 */
2601   {
2602     { "addQ",   { Evh1, sIb }, 0 },
2603     { "orQ",    { Evh1, sIb }, 0 },
2604     { "adcQ",   { Evh1, sIb }, 0 },
2605     { "sbbQ",   { Evh1, sIb }, 0 },
2606     { "andQ",   { Evh1, sIb }, 0 },
2607     { "subQ",   { Evh1, sIb }, 0 },
2608     { "xorQ",   { Evh1, sIb }, 0 },
2609     { "cmpQ",   { Ev, sIb }, 0 },
2610   },
2611   /* REG_8F */
2612   {
2613     { "pop{P|}", { stackEv }, 0 },
2614     { XOP_8F_TABLE () },
2615     { Bad_Opcode },
2616     { Bad_Opcode },
2617     { Bad_Opcode },
2618     { XOP_8F_TABLE () },
2619   },
2620   /* REG_C0 */
2621   {
2622     { "rolA",   { VexGb, Eb, Ib }, NO_PREFIX },
2623     { "rorA",   { VexGb, Eb, Ib }, NO_PREFIX },
2624     { "rclA",   { VexGb, Eb, Ib }, NO_PREFIX },
2625     { "rcrA",   { VexGb, Eb, Ib }, NO_PREFIX },
2626     { "shlA",   { VexGb, Eb, Ib }, NO_PREFIX },
2627     { "shrA",   { VexGb, Eb, Ib }, NO_PREFIX },
2628     { "shlA",   { VexGb, Eb, Ib }, NO_PREFIX },
2629     { "sarA",   { VexGb, Eb, Ib }, NO_PREFIX },
2630   },
2631   /* REG_C1 */
2632   {
2633     { "rolQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2634     { "rorQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2635     { "rclQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2636     { "rcrQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2637     { "shlQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2638     { "shrQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2639     { "shlQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2640     { "sarQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2641   },
2642   /* REG_C6 */
2643   {
2644     { "movA",   { Ebh3, Ib }, 0 },
2645     { Bad_Opcode },
2646     { Bad_Opcode },
2647     { Bad_Opcode },
2648     { Bad_Opcode },
2649     { Bad_Opcode },
2650     { Bad_Opcode },
2651     { RM_TABLE (RM_C6_REG_7) },
2652   },
2653   /* REG_C7 */
2654   {
2655     { "movQ",   { Evh3, Iv }, 0 },
2656     { Bad_Opcode },
2657     { Bad_Opcode },
2658     { Bad_Opcode },
2659     { Bad_Opcode },
2660     { Bad_Opcode },
2661     { Bad_Opcode },
2662     { RM_TABLE (RM_C7_REG_7) },
2663   },
2664   /* REG_D0 */
2665   {
2666     { "rolA",   { VexGb, Eb, I1 }, NO_PREFIX },
2667     { "rorA",   { VexGb, Eb, I1 }, NO_PREFIX },
2668     { "rclA",   { VexGb, Eb, I1 }, NO_PREFIX },
2669     { "rcrA",   { VexGb, Eb, I1 }, NO_PREFIX },
2670     { "shlA",   { VexGb, Eb, I1 }, NO_PREFIX },
2671     { "shrA",   { VexGb, Eb, I1 }, NO_PREFIX },
2672     { "shlA",   { VexGb, Eb, I1 }, NO_PREFIX },
2673     { "sarA",   { VexGb, Eb, I1 }, NO_PREFIX },
2674   },
2675   /* REG_D1 */
2676   {
2677     { "rolQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2678     { "rorQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2679     { "rclQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2680     { "rcrQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2681     { "shlQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2682     { "shrQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2683     { "shlQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2684     { "sarQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2685   },
2686   /* REG_D2 */
2687   {
2688     { "rolA",   { VexGb, Eb, CL }, NO_PREFIX },
2689     { "rorA",   { VexGb, Eb, CL }, NO_PREFIX },
2690     { "rclA",   { VexGb, Eb, CL }, NO_PREFIX },
2691     { "rcrA",   { VexGb, Eb, CL }, NO_PREFIX },
2692     { "shlA",   { VexGb, Eb, CL }, NO_PREFIX },
2693     { "shrA",   { VexGb, Eb, CL }, NO_PREFIX },
2694     { "shlA",   { VexGb, Eb, CL }, NO_PREFIX },
2695     { "sarA",   { VexGb, Eb, CL }, NO_PREFIX },
2696   },
2697   /* REG_D3 */
2698   {
2699     { "rolQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2700     { "rorQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2701     { "rclQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2702     { "rcrQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2703     { "shlQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2704     { "shrQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2705     { "shlQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2706     { "sarQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2707   },
2708   /* REG_F6 */
2709   {
2710     { "testA",  { Eb, Ib }, 0 },
2711     { "testA",  { Eb, Ib }, 0 },
2712     { "notA",   { Ebh1 }, 0 },
2713     { "negA",   { Ebh1 }, 0 },
2714     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2715     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2716     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2717     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2718   },
2719   /* REG_F7 */
2720   {
2721     { "testQ",  { Ev, Iv }, 0 },
2722     { "testQ",  { Ev, Iv }, 0 },
2723     { "notQ",   { Evh1 }, 0 },
2724     { "negQ",   { Evh1 }, 0 },
2725     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2726     { "imulQ",  { Ev }, 0 },
2727     { "divQ",   { Ev }, 0 },
2728     { "idivQ",  { Ev }, 0 },
2729   },
2730   /* REG_FE */
2731   {
2732     { "incA",   { Ebh1 }, 0 },
2733     { "decA",   { Ebh1 }, 0 },
2734   },
2735   /* REG_FF */
2736   {
2737     { "incQ",   { Evh1 }, 0 },
2738     { "decQ",   { Evh1 }, 0 },
2739     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2740     { "{l|}call^", { indirEp }, 0 },
2741     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2742     { "{l|}jmp^", { indirEp }, 0 },
2743     { "push{P|}", { stackEv }, 0 },
2744     { Bad_Opcode },
2745   },
2746   /* REG_0F00 */
2747   {
2748     { "sldtD",  { Sv }, 0 },
2749     { "strD",   { Sv }, 0 },
2750     { "lldtD",  { Sv }, 0 },
2751     { "ltrD",   { Sv }, 0 },
2752     { "verrD",  { Sv }, 0 },
2753     { "verwD",  { Sv }, 0 },
2754     { X86_64_TABLE (X86_64_0F00_REG_6) },
2755     { Bad_Opcode },
2756   },
2757   /* REG_0F01 */
2758   {
2759     { MOD_TABLE (MOD_0F01_REG_0) },
2760     { MOD_TABLE (MOD_0F01_REG_1) },
2761     { MOD_TABLE (MOD_0F01_REG_2) },
2762     { MOD_TABLE (MOD_0F01_REG_3) },
2763     { "smswD",  { Sv }, 0 },
2764     { MOD_TABLE (MOD_0F01_REG_5) },
2765     { "lmsw",   { Ew }, 0 },
2766     { MOD_TABLE (MOD_0F01_REG_7) },
2767   },
2768   /* REG_0F0D */
2769   {
2770     { "prefetch",       { Mb }, 0 },
2771     { "prefetchw",      { Mb }, 0 },
2772     { "prefetchwt1",    { Mb }, 0 },
2773     { "prefetch",       { Mb }, 0 },
2774     { "prefetch",       { Mb }, 0 },
2775     { "prefetch",       { Mb }, 0 },
2776     { "prefetch",       { Mb }, 0 },
2777     { "prefetch",       { Mb }, 0 },
2778   },
2779   /* REG_0F18 */
2780   {
2781     { MOD_TABLE (MOD_0F18_REG_0) },
2782     { MOD_TABLE (MOD_0F18_REG_1) },
2783     { MOD_TABLE (MOD_0F18_REG_2) },
2784     { MOD_TABLE (MOD_0F18_REG_3) },
2785     { "nopQ",           { Ev }, 0 },
2786     { "nopQ",           { Ev }, 0 },
2787     { MOD_TABLE (MOD_0F18_REG_6) },
2788     { MOD_TABLE (MOD_0F18_REG_7) },
2789   },
2790   /* REG_0F1C_P_0_MOD_0 */
2791   {
2792     { "cldemote",       { Mb }, 0 },
2793     { "nopQ",           { Ev }, 0 },
2794     { "nopQ",           { Ev }, 0 },
2795     { "nopQ",           { Ev }, 0 },
2796     { "nopQ",           { Ev }, 0 },
2797     { "nopQ",           { Ev }, 0 },
2798     { "nopQ",           { Ev }, 0 },
2799     { "nopQ",           { Ev }, 0 },
2800   },
2801   /* REG_0F1E_P_1_MOD_3 */
2802   {
2803     { "nopQ",           { Ev }, PREFIX_IGNORED },
2804     { "rdsspK",         { Edq }, 0 },
2805     { "nopQ",           { Ev }, PREFIX_IGNORED },
2806     { "nopQ",           { Ev }, PREFIX_IGNORED },
2807     { "nopQ",           { Ev }, PREFIX_IGNORED },
2808     { "nopQ",           { Ev }, PREFIX_IGNORED },
2809     { "nopQ",           { Ev }, PREFIX_IGNORED },
2810     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2811   },
2812   /* REG_0F38D8_PREFIX_1 */
2813   {
2814     { "aesencwide128kl",        { M }, 0 },
2815     { "aesdecwide128kl",        { M }, 0 },
2816     { "aesencwide256kl",        { M }, 0 },
2817     { "aesdecwide256kl",        { M }, 0 },
2818   },
2819   /* REG_0F3A0F_P_1 */
2820   {
2821     { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2822   },
2823   /* REG_0F71 */
2824   {
2825     { Bad_Opcode },
2826     { Bad_Opcode },
2827     { "psrlw",          { Nq, Ib }, PREFIX_OPCODE },
2828     { Bad_Opcode },
2829     { "psraw",          { Nq, Ib }, PREFIX_OPCODE },
2830     { Bad_Opcode },
2831     { "psllw",          { Nq, Ib }, PREFIX_OPCODE },
2832   },
2833   /* REG_0F72 */
2834   {
2835     { Bad_Opcode },
2836     { Bad_Opcode },
2837     { "psrld",          { Nq, Ib }, PREFIX_OPCODE },
2838     { Bad_Opcode },
2839     { "psrad",          { Nq, Ib }, PREFIX_OPCODE },
2840     { Bad_Opcode },
2841     { "pslld",          { Nq, Ib }, PREFIX_OPCODE },
2842   },
2843   /* REG_0F73 */
2844   {
2845     { Bad_Opcode },
2846     { Bad_Opcode },
2847     { "psrlq",          { Nq, Ib }, PREFIX_OPCODE },
2848     { "psrldq",         { Ux, Ib }, PREFIX_DATA },
2849     { Bad_Opcode },
2850     { Bad_Opcode },
2851     { "psllq",          { Nq, Ib }, PREFIX_OPCODE },
2852     { "pslldq",         { Ux, Ib }, PREFIX_DATA },
2853   },
2854   /* REG_0FA6 */
2855   {
2856     { "montmul",        { { OP_0f07, 0 } }, 0 },
2857     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2858     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2859   },
2860   /* REG_0FA7 */
2861   {
2862     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2863     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2864     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2865     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2866     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2867     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2868   },
2869   /* REG_0FAE */
2870   {
2871     { MOD_TABLE (MOD_0FAE_REG_0) },
2872     { MOD_TABLE (MOD_0FAE_REG_1) },
2873     { MOD_TABLE (MOD_0FAE_REG_2) },
2874     { MOD_TABLE (MOD_0FAE_REG_3) },
2875     { MOD_TABLE (MOD_0FAE_REG_4) },
2876     { MOD_TABLE (MOD_0FAE_REG_5) },
2877     { MOD_TABLE (MOD_0FAE_REG_6) },
2878     { MOD_TABLE (MOD_0FAE_REG_7) },
2879   },
2880   /* REG_0FBA */
2881   {
2882     { Bad_Opcode },
2883     { Bad_Opcode },
2884     { Bad_Opcode },
2885     { Bad_Opcode },
2886     { "btQ",    { Ev, Ib }, 0 },
2887     { "btsQ",   { Evh1, Ib }, 0 },
2888     { "btrQ",   { Evh1, Ib }, 0 },
2889     { "btcQ",   { Evh1, Ib }, 0 },
2890   },
2891   /* REG_0FC7 */
2892   {
2893     { Bad_Opcode },
2894     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2895     { Bad_Opcode },
2896     { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2897     { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2898     { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2899     { MOD_TABLE (MOD_0FC7_REG_6) },
2900     { MOD_TABLE (MOD_0FC7_REG_7) },
2901   },
2902   /* REG_VEX_0F71 */
2903   {
2904     { Bad_Opcode },
2905     { Bad_Opcode },
2906     { "vpsrlw",         { Vex, Ux, Ib }, PREFIX_DATA },
2907     { Bad_Opcode },
2908     { "vpsraw",         { Vex, Ux, Ib }, PREFIX_DATA },
2909     { Bad_Opcode },
2910     { "vpsllw",         { Vex, Ux, Ib }, PREFIX_DATA },
2911   },
2912   /* REG_VEX_0F72 */
2913   {
2914     { Bad_Opcode },
2915     { Bad_Opcode },
2916     { "vpsrld",         { Vex, Ux, Ib }, PREFIX_DATA },
2917     { Bad_Opcode },
2918     { "vpsrad",         { Vex, Ux, Ib }, PREFIX_DATA },
2919     { Bad_Opcode },
2920     { "vpslld",         { Vex, Ux, Ib }, PREFIX_DATA },
2921   },
2922   /* REG_VEX_0F73 */
2923   {
2924     { Bad_Opcode },
2925     { Bad_Opcode },
2926     { "vpsrlq",         { Vex, Ux, Ib }, PREFIX_DATA },
2927     { "vpsrldq",        { Vex, Ux, Ib }, PREFIX_DATA },
2928     { Bad_Opcode },
2929     { Bad_Opcode },
2930     { "vpsllq",         { Vex, Ux, Ib }, PREFIX_DATA },
2931     { "vpslldq",        { Vex, Ux, Ib }, PREFIX_DATA },
2932   },
2933   /* REG_VEX_0FAE */
2934   {
2935     { Bad_Opcode },
2936     { Bad_Opcode },
2937     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
2938     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
2939   },
2940   /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2941   {
2942     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2943   },
2944   /* REG_VEX_0F38F3_L_0_P_0 */
2945   {
2946     { Bad_Opcode },
2947     { "blsrS",          { VexGdq, Edq }, 0 },
2948     { "blsmskS",        { VexGdq, Edq }, 0 },
2949     { "blsiS",          { VexGdq, Edq }, 0 },
2950   },
2951   /* REG_VEX_MAP7_F8_L_0_W_0 */
2952   {
2953     { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
2954   },
2955   /* REG_XOP_09_01_L_0 */
2956   {
2957     { Bad_Opcode },
2958     { "blcfill",        { VexGdq, Edq }, 0 },
2959     { "blsfill",        { VexGdq, Edq }, 0 },
2960     { "blcs",   { VexGdq, Edq }, 0 },
2961     { "tzmsk",  { VexGdq, Edq }, 0 },
2962     { "blcic",  { VexGdq, Edq }, 0 },
2963     { "blsic",  { VexGdq, Edq }, 0 },
2964     { "t1mskc", { VexGdq, Edq }, 0 },
2965   },
2966   /* REG_XOP_09_02_L_0 */
2967   {
2968     { Bad_Opcode },
2969     { "blcmsk", { VexGdq, Edq }, 0 },
2970     { Bad_Opcode },
2971     { Bad_Opcode },
2972     { Bad_Opcode },
2973     { Bad_Opcode },
2974     { "blci",   { VexGdq, Edq }, 0 },
2975   },
2976   /* REG_XOP_09_12_L_0 */
2977   {
2978     { "llwpcb", { Rdq }, 0 },
2979     { "slwpcb", { Rdq }, 0 },
2980   },
2981   /* REG_XOP_0A_12_L_0 */
2982   {
2983     { "lwpins", { VexGdq, Ed, Id }, 0 },
2984     { "lwpval", { VexGdq, Ed, Id }, 0 },
2985   },
2986
2987 #include "i386-dis-evex-reg.h"
2988 };
2989
2990 static const struct dis386 prefix_table[][4] = {
2991   /* PREFIX_90 */
2992   {
2993     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2994     { "pause", { XX }, 0 },
2995     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2996     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2997   },
2998
2999   /* PREFIX_0F00_REG_6_X86_64 */
3000   {
3001     { Bad_Opcode },
3002     { Bad_Opcode },
3003     { Bad_Opcode },
3004     { "lkgsD", { Sv }, 0 },
3005   },
3006
3007   /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3008   {
3009     { "wrmsrns",        { Skip_MODRM }, 0 },
3010     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3011     { Bad_Opcode },
3012     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3013   },
3014
3015   /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3016   {
3017     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3018   },
3019
3020   /* PREFIX_0F01_REG_1_RM_2 */
3021   {
3022     { "clac",           { Skip_MODRM }, 0 },
3023     { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3024     { Bad_Opcode },
3025     { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3026   },
3027
3028   /* PREFIX_0F01_REG_1_RM_4 */
3029   {
3030     { Bad_Opcode },
3031     { Bad_Opcode },
3032     { "tdcall",         { Skip_MODRM }, 0 },
3033     { Bad_Opcode },
3034   },
3035
3036   /* PREFIX_0F01_REG_1_RM_5 */
3037   {
3038     { Bad_Opcode },
3039     { Bad_Opcode },
3040     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3041     { Bad_Opcode },
3042   },
3043
3044   /* PREFIX_0F01_REG_1_RM_6 */
3045   {
3046     { Bad_Opcode },
3047     { Bad_Opcode },
3048     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3049     { Bad_Opcode },
3050   },
3051
3052   /* PREFIX_0F01_REG_1_RM_7 */
3053   {
3054     { "encls",          { Skip_MODRM }, 0 },
3055     { Bad_Opcode },
3056     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3057     { Bad_Opcode },
3058   },
3059
3060   /* PREFIX_0F01_REG_3_RM_1 */
3061   {
3062     { "vmmcall",        { Skip_MODRM }, 0 },
3063     { "vmgexit",        { Skip_MODRM }, 0 },
3064     { Bad_Opcode },
3065     { "vmgexit",        { Skip_MODRM }, 0 },
3066   },
3067
3068   /* PREFIX_0F01_REG_5_MOD_0 */
3069   {
3070     { Bad_Opcode },
3071     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3072   },
3073
3074   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3075   {
3076     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3077     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3078     { Bad_Opcode },
3079     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3080   },
3081
3082   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3083   {
3084     { Bad_Opcode },
3085     { Bad_Opcode },
3086     { Bad_Opcode },
3087     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3088   },
3089
3090   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3091   {
3092     { Bad_Opcode },
3093     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3094   },
3095
3096   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3097   {
3098     { Bad_Opcode },
3099     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3100   },
3101
3102   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3103   {
3104     { Bad_Opcode },
3105     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3106   },
3107
3108   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3109   {
3110     { "rdpkru", { Skip_MODRM }, 0 },
3111     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3112   },
3113
3114   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3115   {
3116     { "wrpkru", { Skip_MODRM }, 0 },
3117     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3118   },
3119
3120   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3121   {
3122     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3123     { "mcommit",        { Skip_MODRM }, 0 },
3124   },
3125
3126   /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3127   {
3128     { "rdpru", { Skip_MODRM }, 0 },
3129     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3130   },
3131
3132   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3133   {
3134     { "invlpgb",        { Skip_MODRM }, 0 },
3135     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3136     { Bad_Opcode },
3137     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3138   },
3139
3140   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3141   {
3142     { "tlbsync",        { Skip_MODRM }, 0 },
3143     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3144     { Bad_Opcode },
3145     { "pvalidate",      { Skip_MODRM }, 0 },
3146   },
3147
3148   /* PREFIX_0F09 */
3149   {
3150     { "wbinvd",   { XX }, 0 },
3151     { "wbnoinvd", { XX }, 0 },
3152   },
3153
3154   /* PREFIX_0F10 */
3155   {
3156     { "%XEVmovupX",     { XM, EXEvexXNoBcst }, 0 },
3157     { "%XEVmovs%XS",    { XMScalar, VexScalarR, EXd }, 0 },
3158     { "%XEVmovupX",     { XM, EXEvexXNoBcst }, 0 },
3159     { "%XEVmovs%XD",    { XMScalar, VexScalarR, EXq }, 0 },
3160   },
3161
3162   /* PREFIX_0F11 */
3163   {
3164     { "%XEVmovupX",     { EXxS, XM }, 0 },
3165     { "%XEVmovs%XS",    { EXdS, VexScalarR, XMScalar }, 0 },
3166     { "%XEVmovupX",     { EXxS, XM }, 0 },
3167     { "%XEVmovs%XD",    { EXqS, VexScalarR, XMScalar }, 0 },
3168   },
3169
3170   /* PREFIX_0F12 */
3171   {
3172     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3173     { "movsldup",       { XM, EXx }, 0 },
3174     { "%XEVmovlpYX",    { XM, Vex, Mq }, 0 },
3175     { "movddup",        { XM, EXq }, 0 },
3176   },
3177
3178   /* PREFIX_0F16 */
3179   {
3180     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3181     { "movshdup",       { XM, EXx }, 0 },
3182     { "%XEVmovhpYX",    { XM, Vex, Mq }, 0 },
3183   },
3184
3185   /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3186   {
3187     { "prefetchit1",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3188     { "nopQ",           { Ev }, 0 },
3189     { "nopQ",           { Ev }, 0 },
3190     { "nopQ",           { Ev }, 0 },
3191   },
3192
3193   /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3194   {
3195     { "prefetchit0",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3196     { "nopQ",           { Ev }, 0 },
3197     { "nopQ",           { Ev }, 0 },
3198     { "nopQ",           { Ev }, 0 },
3199   },
3200
3201   /* PREFIX_0F1A */
3202   {
3203     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3204     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3205     { "bndmov", { Gbnd, Ebnd }, 0 },
3206     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3207   },
3208
3209   /* PREFIX_0F1B */
3210   {
3211     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3212     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3213     { "bndmov", { EbndS, Gbnd }, 0 },
3214     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3215   },
3216
3217   /* PREFIX_0F1C */
3218   {
3219     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3220     { "nopQ",   { Ev }, PREFIX_IGNORED },
3221     { "nopQ",   { Ev }, 0 },
3222     { "nopQ",   { Ev }, PREFIX_IGNORED },
3223   },
3224
3225   /* PREFIX_0F1E */
3226   {
3227     { "nopQ",   { Ev }, 0 },
3228     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3229     { "nopQ",   { Ev }, 0 },
3230     { NULL,     { XX }, PREFIX_IGNORED },
3231   },
3232
3233   /* PREFIX_0F2A */
3234   {
3235     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3236     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3237     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3238     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3239   },
3240
3241   /* PREFIX_0F2B */
3242   {
3243     { "movntps", { Mx, XM }, 0 },
3244     { "movntss", { Md, XM }, 0 },
3245     { "movntpd", { Mx, XM }, 0 },
3246     { "movntsd", { Mq, XM }, 0 },
3247   },
3248
3249   /* PREFIX_0F2C */
3250   {
3251     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3252     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3253     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3254     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3255   },
3256
3257   /* PREFIX_0F2D */
3258   {
3259     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3260     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3261     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3262     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3263   },
3264
3265   /* PREFIX_0F2E */
3266   {
3267     { "%XEVucomisYX",   { XMScalar, EXd, EXxEVexS }, 0 },
3268     { Bad_Opcode },
3269     { "%XEVucomisYX",   { XMScalar, EXq, EXxEVexS }, 0 },
3270   },
3271
3272   /* PREFIX_0F2F */
3273   {
3274     { "%XEVcomisYX",    { XMScalar, EXd, EXxEVexS }, 0 },
3275     { Bad_Opcode },
3276     { "%XEVcomisYX",    { XMScalar, EXq, EXxEVexS }, 0 },
3277   },
3278
3279   /* PREFIX_0F51 */
3280   {
3281     { "%XEVsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3282     { "%XEVsqrts%XS",   { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3283     { "%XEVsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3284     { "%XEVsqrts%XD",   { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3285   },
3286
3287   /* PREFIX_0F52 */
3288   {
3289     { "Vrsqrtps",       { XM, EXx }, 0 },
3290     { "Vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3291   },
3292
3293   /* PREFIX_0F53 */
3294   {
3295     { "Vrcpps",         { XM, EXx }, 0 },
3296     { "Vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3297   },
3298
3299   /* PREFIX_0F58 */
3300   {
3301     { "%XEVaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3302     { "%XEVadds%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3303     { "%XEVaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3304     { "%XEVadds%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3305   },
3306
3307   /* PREFIX_0F59 */
3308   {
3309     { "%XEVmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3310     { "%XEVmuls%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3311     { "%XEVmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3312     { "%XEVmuls%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3313   },
3314
3315   /* PREFIX_0F5A */
3316   {
3317     { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3318     { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3319     { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3320     { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3321   },
3322
3323   /* PREFIX_0F5B */
3324   {
3325     { "Vcvtdq2ps",      { XM, EXx }, 0 },
3326     { "Vcvttps2dq",     { XM, EXx }, 0 },
3327     { "Vcvtps2dq",      { XM, EXx }, 0 },
3328   },
3329
3330   /* PREFIX_0F5C */
3331   {
3332     { "%XEVsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3333     { "%XEVsubs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3334     { "%XEVsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3335     { "%XEVsubs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3336   },
3337
3338   /* PREFIX_0F5D */
3339   {
3340     { "%XEVminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3341     { "%XEVmins%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3342     { "%XEVminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3343     { "%XEVmins%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3344   },
3345
3346   /* PREFIX_0F5E */
3347   {
3348     { "%XEVdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3349     { "%XEVdivs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3350     { "%XEVdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3351     { "%XEVdivs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3352   },
3353
3354   /* PREFIX_0F5F */
3355   {
3356     { "%XEVmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3357     { "%XEVmaxs%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3358     { "%XEVmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3359     { "%XEVmaxs%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3360   },
3361
3362   /* PREFIX_0F60 */
3363   {
3364     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3365     { Bad_Opcode },
3366     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3367   },
3368
3369   /* PREFIX_0F61 */
3370   {
3371     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3372     { Bad_Opcode },
3373     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3374   },
3375
3376   /* PREFIX_0F62 */
3377   {
3378     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3379     { Bad_Opcode },
3380     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3381   },
3382
3383   /* PREFIX_0F6F */
3384   {
3385     { "movq",   { MX, EM }, PREFIX_OPCODE },
3386     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3387     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3388   },
3389
3390   /* PREFIX_0F70 */
3391   {
3392     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3393     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3394     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3395     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3396   },
3397
3398   /* PREFIX_0F78 */
3399   {
3400     {"vmread",  { Em, Gm }, 0 },
3401     { Bad_Opcode },
3402     {"extrq",   { Uxmm, Ib, Ib }, 0 },
3403     {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3404   },
3405
3406   /* PREFIX_0F79 */
3407   {
3408     {"vmwrite", { Gm, Em }, 0 },
3409     { Bad_Opcode },
3410     {"extrq",   { XM, Uxmm }, 0 },
3411     {"insertq", { XM, Uxmm }, 0 },
3412   },
3413
3414   /* PREFIX_0F7C */
3415   {
3416     { Bad_Opcode },
3417     { Bad_Opcode },
3418     { "Vhaddpd",        { XM, Vex, EXx }, 0 },
3419     { "Vhaddps",        { XM, Vex, EXx }, 0 },
3420   },
3421
3422   /* PREFIX_0F7D */
3423   {
3424     { Bad_Opcode },
3425     { Bad_Opcode },
3426     { "Vhsubpd",        { XM, Vex, EXx }, 0 },
3427     { "Vhsubps",        { XM, Vex, EXx }, 0 },
3428   },
3429
3430   /* PREFIX_0F7E */
3431   {
3432     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3433     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3434     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3435   },
3436
3437   /* PREFIX_0F7F */
3438   {
3439     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3440     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3441     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3442   },
3443
3444   /* PREFIX_0FAE_REG_0_MOD_3 */
3445   {
3446     { Bad_Opcode },
3447     { "rdfsbase", { Ev }, 0 },
3448   },
3449
3450   /* PREFIX_0FAE_REG_1_MOD_3 */
3451   {
3452     { Bad_Opcode },
3453     { "rdgsbase", { Ev }, 0 },
3454   },
3455
3456   /* PREFIX_0FAE_REG_2_MOD_3 */
3457   {
3458     { Bad_Opcode },
3459     { "wrfsbase", { Ev }, 0 },
3460   },
3461
3462   /* PREFIX_0FAE_REG_3_MOD_3 */
3463   {
3464     { Bad_Opcode },
3465     { "wrgsbase", { Ev }, 0 },
3466   },
3467
3468   /* PREFIX_0FAE_REG_4_MOD_0 */
3469   {
3470     { "xsave",  { FXSAVE }, PREFIX_REX2_ILLEGAL },
3471     { "ptwrite{%LQ|}", { Edq }, 0 },
3472   },
3473
3474   /* PREFIX_0FAE_REG_4_MOD_3 */
3475   {
3476     { Bad_Opcode },
3477     { "ptwrite{%LQ|}", { Edq }, 0 },
3478   },
3479
3480   /* PREFIX_0FAE_REG_5_MOD_3 */
3481   {
3482     { "lfence",         { Skip_MODRM }, 0 },
3483     { "incsspK",        { Edq }, PREFIX_OPCODE },
3484   },
3485
3486   /* PREFIX_0FAE_REG_6_MOD_0 */
3487   {
3488     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3489     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3490     { "clwb",   { Mb }, PREFIX_OPCODE },
3491   },
3492
3493   /* PREFIX_0FAE_REG_6_MOD_3 */
3494   {
3495     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3496     { "umonitor",       { Eva }, PREFIX_OPCODE },
3497     { "tpause", { Edq }, PREFIX_OPCODE },
3498     { "umwait", { Edq }, PREFIX_OPCODE },
3499   },
3500
3501   /* PREFIX_0FAE_REG_7_MOD_0 */
3502   {
3503     { "clflush",        { Mb }, 0 },
3504     { Bad_Opcode },
3505     { "clflushopt",     { Mb }, 0 },
3506   },
3507
3508   /* PREFIX_0FB8 */
3509   {
3510     { Bad_Opcode },
3511     { "popcntS", { Gv, Ev }, 0 },
3512   },
3513
3514   /* PREFIX_0FBC */
3515   {
3516     { "bsfS",   { Gv, Ev }, 0 },
3517     { "tzcntS", { Gv, Ev }, 0 },
3518     { "bsfS",   { Gv, Ev }, 0 },
3519   },
3520
3521   /* PREFIX_0FBD */
3522   {
3523     { "bsrS",   { Gv, Ev }, 0 },
3524     { "lzcntS", { Gv, Ev }, 0 },
3525     { "bsrS",   { Gv, Ev }, 0 },
3526   },
3527
3528   /* PREFIX_0FC2 */
3529   {
3530     { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3531     { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3532     { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3533     { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3534   },
3535
3536   /* PREFIX_0FC7_REG_6_MOD_0 */
3537   {
3538     { "vmptrld",{ Mq }, 0 },
3539     { "vmxon",  { Mq }, 0 },
3540     { "vmclear",{ Mq }, 0 },
3541   },
3542
3543   /* PREFIX_0FC7_REG_6_MOD_3 */
3544   {
3545     { "rdrand", { Ev }, 0 },
3546     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3547     { "rdrand", { Ev }, 0 }
3548   },
3549
3550   /* PREFIX_0FC7_REG_7_MOD_3 */
3551   {
3552     { "rdseed", { Ev }, 0 },
3553     { "rdpid",  { Em }, 0 },
3554     { "rdseed", { Ev }, 0 },
3555   },
3556
3557   /* PREFIX_0FD0 */
3558   {
3559     { Bad_Opcode },
3560     { Bad_Opcode },
3561     { "VaddsubpX",      { XM, Vex, EXx }, 0 },
3562     { "VaddsubpX",      { XM, Vex, EXx }, 0 },
3563   },
3564
3565   /* PREFIX_0FD6 */
3566   {
3567     { Bad_Opcode },
3568     { "movq2dq",{ XM, Nq }, 0 },
3569     { "movq",   { EXqS, XM }, 0 },
3570     { "movdq2q",{ MX, Ux }, 0 },
3571   },
3572
3573   /* PREFIX_0FE6 */
3574   {
3575     { Bad_Opcode },
3576     { "Vcvtdq2pd",      { XM, EXxmmq }, 0 },
3577     { "Vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3578     { "Vcvtpd2dq%XY",   { XMM, EXx }, 0 },
3579   },
3580
3581   /* PREFIX_0FE7 */
3582   {
3583     { "movntq",         { Mq, MX }, 0 },
3584     { Bad_Opcode },
3585     { "movntdq",        { Mx, XM }, 0 },
3586   },
3587
3588   /* PREFIX_0FF0 */
3589   {
3590     { Bad_Opcode },
3591     { Bad_Opcode },
3592     { Bad_Opcode },
3593     { "Vlddqu",         { XM, M }, 0 },
3594   },
3595
3596   /* PREFIX_0FF7 */
3597   {
3598     { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3599     { Bad_Opcode },
3600     { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3601   },
3602
3603   /* PREFIX_0F38D8 */
3604   {
3605     { Bad_Opcode },
3606     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3607   },
3608
3609   /* PREFIX_0F38DC */
3610   {
3611     { Bad_Opcode },
3612     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3613     { "aesenc", { XM, EXx }, 0 },
3614   },
3615
3616   /* PREFIX_0F38DD */
3617   {
3618     { Bad_Opcode },
3619     { "aesdec128kl", { XM, M }, 0 },
3620     { "aesenclast", { XM, EXx }, 0 },
3621   },
3622
3623   /* PREFIX_0F38DE */
3624   {
3625     { Bad_Opcode },
3626     { "aesenc256kl", { XM, M }, 0 },
3627     { "aesdec", { XM, EXx }, 0 },
3628   },
3629
3630   /* PREFIX_0F38DF */
3631   {
3632     { Bad_Opcode },
3633     { "aesdec256kl", { XM, M }, 0 },
3634     { "aesdeclast", { XM, EXx }, 0 },
3635   },
3636
3637   /* PREFIX_0F38F0 */
3638   {
3639     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3640     { Bad_Opcode },
3641     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3642     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3643   },
3644
3645   /* PREFIX_0F38F1 */
3646   {
3647     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3648     { Bad_Opcode },
3649     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3650     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3651   },
3652
3653   /* PREFIX_0F38F6 */
3654   {
3655     { "wrssK",  { M, Gdq }, 0 },
3656     { "adoxL",  { VexGdq, Gdq, Edq }, 0 },
3657     { "adcxL",  { VexGdq, Gdq, Edq }, 0 },
3658     { Bad_Opcode },
3659   },
3660
3661   /* PREFIX_0F38F8_M_0 */
3662   {
3663     { Bad_Opcode },
3664     { "enqcmds", { Gva, M }, 0 },
3665     { "movdir64b", { Gva, M }, 0 },
3666     { "enqcmd", { Gva, M }, 0 },
3667   },
3668
3669   /* PREFIX_0F38F8_M_1_X86_64 */
3670   {
3671     { Bad_Opcode },
3672     { "uwrmsr",         { Gq, Rq }, 0 },
3673     { Bad_Opcode },
3674     { "urdmsr",         { Rq, Gq }, 0 },
3675   },
3676
3677   /* PREFIX_0F38FA */
3678   {
3679     { Bad_Opcode },
3680     { "encodekey128", { Gd, Rd }, 0 },
3681   },
3682
3683   /* PREFIX_0F38FB */
3684   {
3685     { Bad_Opcode },
3686     { "encodekey256", { Gd, Rd }, 0 },
3687   },
3688
3689   /* PREFIX_0F38FC */
3690   {
3691     { "aadd",   { Mdq, Gdq }, 0 },
3692     { "axor",   { Mdq, Gdq }, 0 },
3693     { "aand",   { Mdq, Gdq }, 0 },
3694     { "aor",    { Mdq, Gdq }, 0 },
3695   },
3696
3697   /* PREFIX_0F3A0F */
3698   {
3699     { Bad_Opcode },
3700     { REG_TABLE (REG_0F3A0F_P_1) },
3701   },
3702
3703   /* PREFIX_VEX_0F12 */
3704   {
3705     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3706     { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3707     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3708     { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3709   },
3710
3711   /* PREFIX_VEX_0F16 */
3712   {
3713     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3714     { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3715     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3716   },
3717
3718   /* PREFIX_VEX_0F2A */
3719   {
3720     { Bad_Opcode },
3721     { "%XEvcvtsi2ssY{%LQ|}",    { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3722     { Bad_Opcode },
3723     { "%XEvcvtsi2sdY{%LQ|}",    { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3724   },
3725
3726   /* PREFIX_VEX_0F2C */
3727   {
3728     { Bad_Opcode },
3729     { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3730     { Bad_Opcode },
3731     { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3732   },
3733
3734   /* PREFIX_VEX_0F2D */
3735   {
3736     { Bad_Opcode },
3737     { "%XEvcvtss2si",   { Gdq, EXd, EXxEVexR }, 0 },
3738     { Bad_Opcode },
3739     { "%XEvcvtsd2si",   { Gdq, EXq, EXxEVexR }, 0 },
3740   },
3741
3742   /* PREFIX_VEX_0F41_L_1_W_0 */
3743   {
3744     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
3745     { Bad_Opcode },
3746     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
3747   },
3748
3749   /* PREFIX_VEX_0F41_L_1_W_1 */
3750   {
3751     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
3752     { Bad_Opcode },
3753     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
3754   },
3755
3756   /* PREFIX_VEX_0F42_L_1_W_0 */
3757   {
3758     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
3759     { Bad_Opcode },
3760     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
3761   },
3762
3763   /* PREFIX_VEX_0F42_L_1_W_1 */
3764   {
3765     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
3766     { Bad_Opcode },
3767     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
3768   },
3769
3770   /* PREFIX_VEX_0F44_L_0_W_0 */
3771   {
3772     { "knotw",          { MaskG, MaskR }, 0 },
3773     { Bad_Opcode },
3774     { "knotb",          { MaskG, MaskR }, 0 },
3775   },
3776
3777   /* PREFIX_VEX_0F44_L_0_W_1 */
3778   {
3779     { "knotq",          { MaskG, MaskR }, 0 },
3780     { Bad_Opcode },
3781     { "knotd",          { MaskG, MaskR }, 0 },
3782   },
3783
3784   /* PREFIX_VEX_0F45_L_1_W_0 */
3785   {
3786     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
3787     { Bad_Opcode },
3788     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
3789   },
3790
3791   /* PREFIX_VEX_0F45_L_1_W_1 */
3792   {
3793     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
3794     { Bad_Opcode },
3795     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
3796   },
3797
3798   /* PREFIX_VEX_0F46_L_1_W_0 */
3799   {
3800     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
3801     { Bad_Opcode },
3802     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
3803   },
3804
3805   /* PREFIX_VEX_0F46_L_1_W_1 */
3806   {
3807     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
3808     { Bad_Opcode },
3809     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
3810   },
3811
3812   /* PREFIX_VEX_0F47_L_1_W_0 */
3813   {
3814     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
3815     { Bad_Opcode },
3816     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
3817   },
3818
3819   /* PREFIX_VEX_0F47_L_1_W_1 */
3820   {
3821     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
3822     { Bad_Opcode },
3823     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
3824   },
3825
3826   /* PREFIX_VEX_0F4A_L_1_W_0 */
3827   {
3828     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
3829     { Bad_Opcode },
3830     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
3831   },
3832
3833   /* PREFIX_VEX_0F4A_L_1_W_1 */
3834   {
3835     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
3836     { Bad_Opcode },
3837     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
3838   },
3839
3840   /* PREFIX_VEX_0F4B_L_1_W_0 */
3841   {
3842     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
3843     { Bad_Opcode },
3844     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
3845   },
3846
3847   /* PREFIX_VEX_0F4B_L_1_W_1 */
3848   {
3849     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
3850   },
3851
3852   /* PREFIX_VEX_0F6F */
3853   {
3854     { Bad_Opcode },
3855     { "vmovdqu",        { XM, EXx }, 0 },
3856     { "vmovdqa",        { XM, EXx }, 0 },
3857   },
3858
3859   /* PREFIX_VEX_0F70 */
3860   {
3861     { Bad_Opcode },
3862     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3863     { "vpshufd",        { XM, EXx, Ib }, 0 },
3864     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3865   },
3866
3867   /* PREFIX_VEX_0F7E */
3868   {
3869     { Bad_Opcode },
3870     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3871     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3872   },
3873
3874   /* PREFIX_VEX_0F7F */
3875   {
3876     { Bad_Opcode },
3877     { "vmovdqu",        { EXxS, XM }, 0 },
3878     { "vmovdqa",        { EXxS, XM }, 0 },
3879   },
3880
3881   /* PREFIX_VEX_0F90_L_0_W_0 */
3882   {
3883     { "kmovw",          { MaskG, MaskE }, 0 },
3884     { Bad_Opcode },
3885     { "kmovb",          { MaskG, MaskBDE }, 0 },
3886   },
3887
3888   /* PREFIX_VEX_0F90_L_0_W_1 */
3889   {
3890     { "kmovq",          { MaskG, MaskE }, 0 },
3891     { Bad_Opcode },
3892     { "kmovd",          { MaskG, MaskBDE }, 0 },
3893   },
3894
3895   /* PREFIX_VEX_0F91_L_0_W_0 */
3896   {
3897     { "kmovw",          { Mw, MaskG }, 0 },
3898     { Bad_Opcode },
3899     { "kmovb",          { Mb, MaskG }, 0 },
3900   },
3901
3902   /* PREFIX_VEX_0F91_L_0_W_1 */
3903   {
3904     { "kmovq",          { Mq, MaskG }, 0 },
3905     { Bad_Opcode },
3906     { "kmovd",          { Md, MaskG }, 0 },
3907   },
3908
3909   /* PREFIX_VEX_0F92_L_0_W_0 */
3910   {
3911     { "kmovw",          { MaskG, Rdq }, 0 },
3912     { Bad_Opcode },
3913     { "kmovb",          { MaskG, Rdq }, 0 },
3914     { "kmovd",          { MaskG, Rdq }, 0 },
3915   },
3916
3917   /* PREFIX_VEX_0F92_L_0_W_1 */
3918   {
3919     { Bad_Opcode },
3920     { Bad_Opcode },
3921     { Bad_Opcode },
3922     { "kmovK",          { MaskG, Rdq }, 0 },
3923   },
3924
3925   /* PREFIX_VEX_0F93_L_0_W_0 */
3926   {
3927     { "kmovw",          { Gdq, MaskR }, 0 },
3928     { Bad_Opcode },
3929     { "kmovb",          { Gdq, MaskR }, 0 },
3930     { "kmovd",          { Gdq, MaskR }, 0 },
3931   },
3932
3933   /* PREFIX_VEX_0F93_L_0_W_1 */
3934   {
3935     { Bad_Opcode },
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { "kmovK",          { Gdq, MaskR }, 0 },
3939   },
3940
3941   /* PREFIX_VEX_0F98_L_0_W_0 */
3942   {
3943     { "kortestw", { MaskG, MaskR }, 0 },
3944     { Bad_Opcode },
3945     { "kortestb", { MaskG, MaskR }, 0 },
3946   },
3947
3948   /* PREFIX_VEX_0F98_L_0_W_1 */
3949   {
3950     { "kortestq", { MaskG, MaskR }, 0 },
3951     { Bad_Opcode },
3952     { "kortestd", { MaskG, MaskR }, 0 },
3953   },
3954
3955   /* PREFIX_VEX_0F99_L_0_W_0 */
3956   {
3957     { "ktestw", { MaskG, MaskR }, 0 },
3958     { Bad_Opcode },
3959     { "ktestb", { MaskG, MaskR }, 0 },
3960   },
3961
3962   /* PREFIX_VEX_0F99_L_0_W_1 */
3963   {
3964     { "ktestq", { MaskG, MaskR }, 0 },
3965     { Bad_Opcode },
3966     { "ktestd", { MaskG, MaskR }, 0 },
3967   },
3968
3969   /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
3970   {
3971     { "ldtilecfg", { M }, 0 },
3972     { Bad_Opcode },
3973     { "sttilecfg", { M }, 0 },
3974   },
3975
3976   /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
3977   {
3978     { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
3979     { Bad_Opcode },
3980     { Bad_Opcode },
3981     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
3982   },
3983
3984   /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
3985   {
3986     { Bad_Opcode },
3987     { "tilestored",     { MVexSIBMEM, TMM }, 0 },
3988     { "tileloaddt1",    { TMM, MVexSIBMEM }, 0 },
3989     { "tileloadd",      { TMM, MVexSIBMEM }, 0 },
3990   },
3991
3992   /* PREFIX_VEX_0F3850_W_0 */
3993   {
3994     { "vpdpbuud",       { XM, Vex, EXx }, 0 },
3995     { "vpdpbsud",       { XM, Vex, EXx }, 0 },
3996     { "%XVvpdpbusd",    { XM, Vex, EXx }, 0 },
3997     { "vpdpbssd",       { XM, Vex, EXx }, 0 },
3998   },
3999
4000   /* PREFIX_VEX_0F3851_W_0 */
4001   {
4002     { "vpdpbuuds",      { XM, Vex, EXx }, 0 },
4003     { "vpdpbsuds",      { XM, Vex, EXx }, 0 },
4004     { "%XVvpdpbusds",   { XM, Vex, EXx }, 0 },
4005     { "vpdpbssds",      { XM, Vex, EXx }, 0 },
4006   },
4007   /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4008   {
4009     { Bad_Opcode },
4010     { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4011     { Bad_Opcode },
4012     { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4013   },
4014
4015   /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4016   {
4017     { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4018     { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4019     { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4020     { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4021   },
4022
4023   /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4024   {
4025     { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4026     { Bad_Opcode },
4027     { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4028   },
4029
4030   /* PREFIX_VEX_0F3872 */
4031   {
4032     { Bad_Opcode },
4033     { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4034   },
4035
4036   /* PREFIX_VEX_0F38B0_W_0 */
4037   {
4038     { "vcvtneoph2ps", { XM, Mx }, 0 },
4039     { "vcvtneebf162ps", { XM, Mx }, 0 },
4040     { "vcvtneeph2ps", { XM, Mx }, 0 },
4041     { "vcvtneobf162ps", { XM, Mx }, 0 },
4042   },
4043
4044   /* PREFIX_VEX_0F38B1_W_0 */
4045   {
4046     { Bad_Opcode },
4047     { "vbcstnebf162ps", { XM, Mw }, 0 },
4048     { "vbcstnesh2ps", { XM, Mw }, 0 },
4049   },
4050
4051   /* PREFIX_VEX_0F38D2_W_0 */
4052   {
4053     { "vpdpwuud",       { XM, Vex, EXx }, 0 },
4054     { "vpdpwsud",       { XM, Vex, EXx }, 0 },
4055     { "vpdpwusd",       { XM, Vex, EXx }, 0 },
4056   },
4057
4058   /* PREFIX_VEX_0F38D3_W_0 */
4059   {
4060     { "vpdpwuuds",      { XM, Vex, EXx }, 0 },
4061     { "vpdpwsuds",      { XM, Vex, EXx }, 0 },
4062     { "vpdpwusds",      { XM, Vex, EXx }, 0 },
4063   },
4064
4065   /* PREFIX_VEX_0F38CB */
4066   {
4067     { Bad_Opcode },
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4071   },
4072
4073   /* PREFIX_VEX_0F38CC */
4074   {
4075     { Bad_Opcode },
4076     { Bad_Opcode },
4077     { Bad_Opcode },
4078     { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4079   },
4080
4081   /* PREFIX_VEX_0F38CD */
4082   {
4083     { Bad_Opcode },
4084     { Bad_Opcode },
4085     { Bad_Opcode },
4086     { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4087   },
4088
4089   /* PREFIX_VEX_0F38DA_W_0 */
4090   {
4091     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4092     { "vsm4key4", { XM, Vex, EXx }, 0 },
4093     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4094     { "vsm4rnds4", { XM, Vex, EXx }, 0 },
4095   },
4096
4097   /* PREFIX_VEX_0F38F2_L_0 */
4098   {
4099     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
4100   },
4101
4102   /* PREFIX_VEX_0F38F3_L_0 */
4103   {
4104     { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4105   },
4106
4107   /* PREFIX_VEX_0F38F5_L_0 */
4108   {
4109     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4110     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4111     { Bad_Opcode },
4112     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4113   },
4114
4115   /* PREFIX_VEX_0F38F6_L_0 */
4116   {
4117     { Bad_Opcode },
4118     { Bad_Opcode },
4119     { Bad_Opcode },
4120     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4121   },
4122
4123   /* PREFIX_VEX_0F38F7_L_0 */
4124   {
4125     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4126     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4127     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4128     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4129   },
4130
4131   /* PREFIX_VEX_0F3AF0_L_0 */
4132   {
4133     { Bad_Opcode },
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4137   },
4138
4139   /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4140   {
4141     { Bad_Opcode },
4142     { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4143     { Bad_Opcode },
4144     { "urdmsr", { Rq, Id }, 0 },
4145   },
4146
4147 #include "i386-dis-evex-prefix.h"
4148 };
4149
4150 static const struct dis386 x86_64_table[][2] = {
4151   /* X86_64_06 */
4152   {
4153     { "pushP", { es }, 0 },
4154   },
4155
4156   /* X86_64_07 */
4157   {
4158     { "popP", { es }, 0 },
4159   },
4160
4161   /* X86_64_0E */
4162   {
4163     { "pushP", { cs }, 0 },
4164   },
4165
4166   /* X86_64_16 */
4167   {
4168     { "pushP", { ss }, 0 },
4169   },
4170
4171   /* X86_64_17 */
4172   {
4173     { "popP", { ss }, 0 },
4174   },
4175
4176   /* X86_64_1E */
4177   {
4178     { "pushP", { ds }, 0 },
4179   },
4180
4181   /* X86_64_1F */
4182   {
4183     { "popP", { ds }, 0 },
4184   },
4185
4186   /* X86_64_27 */
4187   {
4188     { "daa", { XX }, 0 },
4189   },
4190
4191   /* X86_64_2F */
4192   {
4193     { "das", { XX }, 0 },
4194   },
4195
4196   /* X86_64_37 */
4197   {
4198     { "aaa", { XX }, 0 },
4199   },
4200
4201   /* X86_64_3F */
4202   {
4203     { "aas", { XX }, 0 },
4204   },
4205
4206   /* X86_64_60 */
4207   {
4208     { "pushaP", { XX }, 0 },
4209   },
4210
4211   /* X86_64_61 */
4212   {
4213     { "popaP", { XX }, 0 },
4214   },
4215
4216   /* X86_64_62 */
4217   {
4218     { MOD_TABLE (MOD_62_32BIT) },
4219     { EVEX_TABLE () },
4220   },
4221
4222   /* X86_64_63 */
4223   {
4224     { "arplS", { Sv, Gv }, 0 },
4225     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4226   },
4227
4228   /* X86_64_6D */
4229   {
4230     { "ins{R|}", { Yzr, indirDX }, 0 },
4231     { "ins{G|}", { Yzr, indirDX }, 0 },
4232   },
4233
4234   /* X86_64_6F */
4235   {
4236     { "outs{R|}", { indirDXr, Xz }, 0 },
4237     { "outs{G|}", { indirDXr, Xz }, 0 },
4238   },
4239
4240   /* X86_64_82 */
4241   {
4242     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4243     { REG_TABLE (REG_80) },
4244   },
4245
4246   /* X86_64_9A */
4247   {
4248     { "{l|}call{P|}", { Ap }, 0 },
4249   },
4250
4251   /* X86_64_C2 */
4252   {
4253     { "retP",           { Iw, BND }, 0 },
4254     { "ret@",           { Iw, BND }, 0 },
4255   },
4256
4257   /* X86_64_C3 */
4258   {
4259     { "retP",           { BND }, 0 },
4260     { "ret@",           { BND }, 0 },
4261   },
4262
4263   /* X86_64_C4 */
4264   {
4265     { MOD_TABLE (MOD_C4_32BIT) },
4266     { VEX_C4_TABLE () },
4267   },
4268
4269   /* X86_64_C5 */
4270   {
4271     { MOD_TABLE (MOD_C5_32BIT) },
4272     { VEX_C5_TABLE () },
4273   },
4274
4275   /* X86_64_CE */
4276   {
4277     { "into", { XX }, 0 },
4278   },
4279
4280   /* X86_64_D4 */
4281   {
4282     { "aam", { Ib }, 0 },
4283   },
4284
4285   /* X86_64_D5 */
4286   {
4287     { "aad", { Ib }, 0 },
4288   },
4289
4290   /* X86_64_E8 */
4291   {
4292     { "callP",          { Jv, BND }, 0 },
4293     { "call@",          { Jv, BND }, PREFIX_REX2_ILLEGAL }
4294   },
4295
4296   /* X86_64_E9 */
4297   {
4298     { "jmpP",           { Jv, BND }, 0 },
4299     { "jmp@",           { Jv, BND }, PREFIX_REX2_ILLEGAL }
4300   },
4301
4302   /* X86_64_EA */
4303   {
4304     { "{l|}jmp{P|}", { Ap }, 0 },
4305   },
4306
4307   /* X86_64_0F00_REG_6 */
4308   {
4309     { Bad_Opcode },
4310     { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4311   },
4312
4313   /* X86_64_0F01_REG_0 */
4314   {
4315     { "sgdt{Q|Q}", { M }, 0 },
4316     { "sgdt", { M }, 0 },
4317   },
4318
4319   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4320   {
4321     { Bad_Opcode },
4322     { "wrmsrlist",      { Skip_MODRM }, 0 },
4323   },
4324
4325   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4326   {
4327     { Bad_Opcode },
4328     { "rdmsrlist",      { Skip_MODRM }, 0 },
4329   },
4330
4331   /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4332   {
4333     { Bad_Opcode },
4334     { "pbndkb",         { Skip_MODRM }, 0 },
4335   },
4336
4337   /* X86_64_0F01_REG_1 */
4338   {
4339     { "sidt{Q|Q}", { M }, 0 },
4340     { "sidt", { M }, 0 },
4341   },
4342
4343   /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4344   {
4345     { Bad_Opcode },
4346     { "eretu",          { Skip_MODRM }, 0 },
4347   },
4348
4349   /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4350   {
4351     { Bad_Opcode },
4352     { "erets",          { Skip_MODRM }, 0 },
4353   },
4354
4355   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4356   {
4357     { Bad_Opcode },
4358     { "seamret",        { Skip_MODRM }, 0 },
4359   },
4360
4361   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4362   {
4363     { Bad_Opcode },
4364     { "seamops",        { Skip_MODRM }, 0 },
4365   },
4366
4367   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4368   {
4369     { Bad_Opcode },
4370     { "seamcall",       { Skip_MODRM }, 0 },
4371   },
4372
4373   /* X86_64_0F01_REG_2 */
4374   {
4375     { "lgdt{Q|Q}", { M }, 0 },
4376     { "lgdt", { M }, 0 },
4377   },
4378
4379   /* X86_64_0F01_REG_3 */
4380   {
4381     { "lidt{Q|Q}", { M }, 0 },
4382     { "lidt", { M }, 0 },
4383   },
4384
4385   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4386   {
4387     { Bad_Opcode },
4388     { "uiret",  { Skip_MODRM }, 0 },
4389   },
4390
4391   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4392   {
4393     { Bad_Opcode },
4394     { "testui", { Skip_MODRM }, 0 },
4395   },
4396
4397   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4398   {
4399     { Bad_Opcode },
4400     { "clui",   { Skip_MODRM }, 0 },
4401   },
4402
4403   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4404   {
4405     { Bad_Opcode },
4406     { "stui",   { Skip_MODRM }, 0 },
4407   },
4408
4409   /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4410   {
4411     { Bad_Opcode },
4412     { "rmpquery", { Skip_MODRM }, 0 },
4413   },
4414
4415   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4416   {
4417     { Bad_Opcode },
4418     { "rmpadjust",      { Skip_MODRM }, 0 },
4419   },
4420
4421   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4422   {
4423     { Bad_Opcode },
4424     { "rmpupdate",      { Skip_MODRM }, 0 },
4425   },
4426
4427   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4428   {
4429     { Bad_Opcode },
4430     { "psmash", { Skip_MODRM }, 0 },
4431   },
4432
4433   /* X86_64_0F18_REG_6_MOD_0 */
4434   {
4435     { "nopQ",           { Ev }, 0 },
4436     { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4437   },
4438
4439   /* X86_64_0F18_REG_7_MOD_0 */
4440   {
4441     { "nopQ",           { Ev }, 0 },
4442     { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4443   },
4444
4445   {
4446     /* X86_64_0F24 */
4447     { "movZ",           { Em, Td }, 0 },
4448   },
4449
4450   {
4451     /* X86_64_0F26 */
4452     { "movZ",           { Td, Em }, 0 },
4453   },
4454
4455   {
4456     /* X86_64_0F38F8_M_1 */
4457     { Bad_Opcode },
4458     { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4459   },
4460
4461   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4462   {
4463     { Bad_Opcode },
4464     { "senduipi",       { Eq }, 0 },
4465   },
4466
4467   /* X86_64_VEX_0F3849 */
4468   {
4469     { Bad_Opcode },
4470     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4471   },
4472
4473   /* X86_64_VEX_0F384B */
4474   {
4475     { Bad_Opcode },
4476     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4477   },
4478
4479   /* X86_64_VEX_0F385C */
4480   {
4481     { Bad_Opcode },
4482     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4483   },
4484
4485   /* X86_64_VEX_0F385E */
4486   {
4487     { Bad_Opcode },
4488     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4489   },
4490
4491   /* X86_64_VEX_0F386C */
4492   {
4493     { Bad_Opcode },
4494     { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4495   },
4496
4497   /* X86_64_VEX_0F38E0 */
4498   {
4499     { Bad_Opcode },
4500     { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4501   },
4502
4503   /* X86_64_VEX_0F38E1 */
4504   {
4505     { Bad_Opcode },
4506     { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4507   },
4508
4509   /* X86_64_VEX_0F38E2 */
4510   {
4511     { Bad_Opcode },
4512     { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4513   },
4514
4515   /* X86_64_VEX_0F38E3 */
4516   {
4517     { Bad_Opcode },
4518     { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4519   },
4520
4521   /* X86_64_VEX_0F38E4 */
4522   {
4523     { Bad_Opcode },
4524     { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4525   },
4526
4527   /* X86_64_VEX_0F38E5 */
4528   {
4529     { Bad_Opcode },
4530     { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4531   },
4532
4533   /* X86_64_VEX_0F38E6 */
4534   {
4535     { Bad_Opcode },
4536     { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4537   },
4538
4539   /* X86_64_VEX_0F38E7 */
4540   {
4541     { Bad_Opcode },
4542     { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4543   },
4544
4545   /* X86_64_VEX_0F38E8 */
4546   {
4547     { Bad_Opcode },
4548     { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4549   },
4550
4551   /* X86_64_VEX_0F38E9 */
4552   {
4553     { Bad_Opcode },
4554     { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4555   },
4556
4557   /* X86_64_VEX_0F38EA */
4558   {
4559     { Bad_Opcode },
4560     { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4561   },
4562
4563   /* X86_64_VEX_0F38EB */
4564   {
4565     { Bad_Opcode },
4566     { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4567   },
4568
4569   /* X86_64_VEX_0F38EC */
4570   {
4571     { Bad_Opcode },
4572     { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4573   },
4574
4575   /* X86_64_VEX_0F38ED */
4576   {
4577     { Bad_Opcode },
4578     { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4579   },
4580
4581   /* X86_64_VEX_0F38EE */
4582   {
4583     { Bad_Opcode },
4584     { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4585   },
4586
4587   /* X86_64_VEX_0F38EF */
4588   {
4589     { Bad_Opcode },
4590     { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4591   },
4592
4593   /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4594   {
4595     { Bad_Opcode },
4596     { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4597   },
4598 };
4599
4600 static const struct dis386 three_byte_table[][256] = {
4601
4602   /* THREE_BYTE_0F38 */
4603   {
4604     /* 00 */
4605     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4606     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4607     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4608     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4609     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4610     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4611     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4612     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4613     /* 08 */
4614     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4615     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4616     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4617     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4618     { Bad_Opcode },
4619     { Bad_Opcode },
4620     { Bad_Opcode },
4621     { Bad_Opcode },
4622     /* 10 */
4623     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4624     { Bad_Opcode },
4625     { Bad_Opcode },
4626     { Bad_Opcode },
4627     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4628     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4629     { Bad_Opcode },
4630     { "ptest",  { XM, EXx }, PREFIX_DATA },
4631     /* 18 */
4632     { Bad_Opcode },
4633     { Bad_Opcode },
4634     { Bad_Opcode },
4635     { Bad_Opcode },
4636     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4637     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4638     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4639     { Bad_Opcode },
4640     /* 20 */
4641     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4642     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4643     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4644     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4645     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4646     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4647     { Bad_Opcode },
4648     { Bad_Opcode },
4649     /* 28 */
4650     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4651     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4652     { "movntdqa", { XM, Mx }, PREFIX_DATA },
4653     { "packusdw", { XM, EXx }, PREFIX_DATA },
4654     { Bad_Opcode },
4655     { Bad_Opcode },
4656     { Bad_Opcode },
4657     { Bad_Opcode },
4658     /* 30 */
4659     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4660     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4661     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4662     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4663     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4664     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4665     { Bad_Opcode },
4666     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4667     /* 38 */
4668     { "pminsb", { XM, EXx }, PREFIX_DATA },
4669     { "pminsd", { XM, EXx }, PREFIX_DATA },
4670     { "pminuw", { XM, EXx }, PREFIX_DATA },
4671     { "pminud", { XM, EXx }, PREFIX_DATA },
4672     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4673     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4674     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4675     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4676     /* 40 */
4677     { "pmulld", { XM, EXx }, PREFIX_DATA },
4678     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4679     { Bad_Opcode },
4680     { Bad_Opcode },
4681     { Bad_Opcode },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     /* 48 */
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     { Bad_Opcode },
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     /* 50 */
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     { Bad_Opcode },
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     /* 58 */
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     { Bad_Opcode },
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     /* 60 */
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     { Bad_Opcode },
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     /* 68 */
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     { Bad_Opcode },
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     /* 70 */
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     { Bad_Opcode },
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     /* 78 */
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     { Bad_Opcode },
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     /* 80 */
4749     { "invept", { Gm, Mo }, PREFIX_DATA },
4750     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4751     { "invpcid", { Gm, M }, PREFIX_DATA },
4752     { Bad_Opcode },
4753     { Bad_Opcode },
4754     { Bad_Opcode },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     /* 88 */
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     { Bad_Opcode },
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     /* 90 */
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     { Bad_Opcode },
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     /* 98 */
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     { Bad_Opcode },
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     /* a0 */
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     { Bad_Opcode },
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     /* a8 */
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     { Bad_Opcode },
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     /* b0 */
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     { Bad_Opcode },
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     /* b8 */
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     { Bad_Opcode },
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     /* c0 */
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     { Bad_Opcode },
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     /* c8 */
4830     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4831     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4832     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4833     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4834     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4835     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4836     { Bad_Opcode },
4837     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4838     /* d0 */
4839     { Bad_Opcode },
4840     { Bad_Opcode },
4841     { Bad_Opcode },
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     /* d8 */
4848     { PREFIX_TABLE (PREFIX_0F38D8) },
4849     { Bad_Opcode },
4850     { Bad_Opcode },
4851     { "aesimc", { XM, EXx }, PREFIX_DATA },
4852     { PREFIX_TABLE (PREFIX_0F38DC) },
4853     { PREFIX_TABLE (PREFIX_0F38DD) },
4854     { PREFIX_TABLE (PREFIX_0F38DE) },
4855     { PREFIX_TABLE (PREFIX_0F38DF) },
4856     /* e0 */
4857     { Bad_Opcode },
4858     { Bad_Opcode },
4859     { Bad_Opcode },
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     /* e8 */
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     { Bad_Opcode },
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     /* f0 */
4875     { PREFIX_TABLE (PREFIX_0F38F0) },
4876     { PREFIX_TABLE (PREFIX_0F38F1) },
4877     { Bad_Opcode },
4878     { Bad_Opcode },
4879     { Bad_Opcode },
4880     { "wrussK",         { M, Gdq }, PREFIX_DATA },
4881     { PREFIX_TABLE (PREFIX_0F38F6) },
4882     { Bad_Opcode },
4883     /* f8 */
4884     { MOD_TABLE (MOD_0F38F8) },
4885     { "movdiri",        { Mdq, Gdq }, PREFIX_OPCODE },
4886     { PREFIX_TABLE (PREFIX_0F38FA) },
4887     { PREFIX_TABLE (PREFIX_0F38FB) },
4888     { PREFIX_TABLE (PREFIX_0F38FC) },
4889     { Bad_Opcode },
4890     { Bad_Opcode },
4891     { Bad_Opcode },
4892   },
4893   /* THREE_BYTE_0F3A */
4894   {
4895     /* 00 */
4896     { Bad_Opcode },
4897     { Bad_Opcode },
4898     { Bad_Opcode },
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     /* 08 */
4905     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4906     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4907     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4908     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4909     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4910     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4911     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4912     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4913     /* 10 */
4914     { Bad_Opcode },
4915     { Bad_Opcode },
4916     { Bad_Opcode },
4917     { Bad_Opcode },
4918     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4919     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4920     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4921     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4922     /* 18 */
4923     { Bad_Opcode },
4924     { Bad_Opcode },
4925     { Bad_Opcode },
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     /* 20 */
4932     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4933     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4934     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4935     { Bad_Opcode },
4936     { Bad_Opcode },
4937     { Bad_Opcode },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     /* 28 */
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     { Bad_Opcode },
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     /* 30 */
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     { Bad_Opcode },
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     /* 38 */
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     { Bad_Opcode },
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     /* 40 */
4968     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4969     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4970     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4971     { Bad_Opcode },
4972     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4973     { Bad_Opcode },
4974     { Bad_Opcode },
4975     { Bad_Opcode },
4976     /* 48 */
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     { Bad_Opcode },
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     /* 50 */
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     { Bad_Opcode },
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     /* 58 */
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     { Bad_Opcode },
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     /* 60 */
5004     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5005     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5006     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
5007     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
5008     { Bad_Opcode },
5009     { Bad_Opcode },
5010     { Bad_Opcode },
5011     { Bad_Opcode },
5012     /* 68 */
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     { Bad_Opcode },
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     /* 70 */
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     { Bad_Opcode },
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     /* 78 */
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     { Bad_Opcode },
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     /* 80 */
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     { Bad_Opcode },
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     /* 88 */
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     { Bad_Opcode },
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     /* 90 */
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     { Bad_Opcode },
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     /* 98 */
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     { Bad_Opcode },
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     /* a0 */
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     { Bad_Opcode },
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     /* a8 */
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     { Bad_Opcode },
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     /* b0 */
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     { Bad_Opcode },
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     /* b8 */
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     { Bad_Opcode },
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     /* c0 */
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     { Bad_Opcode },
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     /* c8 */
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     { Bad_Opcode },
5124     { Bad_Opcode },
5125     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5126     { Bad_Opcode },
5127     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5128     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5129     /* d0 */
5130     { Bad_Opcode },
5131     { Bad_Opcode },
5132     { Bad_Opcode },
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     /* d8 */
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     { Bad_Opcode },
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5147     /* e0 */
5148     { Bad_Opcode },
5149     { Bad_Opcode },
5150     { Bad_Opcode },
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     /* e8 */
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     { Bad_Opcode },
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     /* f0 */
5166     { PREFIX_TABLE (PREFIX_0F3A0F) },
5167     { Bad_Opcode },
5168     { Bad_Opcode },
5169     { Bad_Opcode },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     /* f8 */
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     { Bad_Opcode },
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183   },
5184 };
5185
5186 static const struct dis386 xop_table[][256] = {
5187   /* XOP_08 */
5188   {
5189     /* 00 */
5190     { Bad_Opcode },
5191     { Bad_Opcode },
5192     { Bad_Opcode },
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     /* 08 */
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     { Bad_Opcode },
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     /* 10 */
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     { Bad_Opcode },
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     /* 18 */
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     { Bad_Opcode },
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     /* 20 */
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     { Bad_Opcode },
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     /* 28 */
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     { Bad_Opcode },
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     /* 30 */
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     { Bad_Opcode },
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     /* 38 */
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     { Bad_Opcode },
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     /* 40 */
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     { Bad_Opcode },
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     /* 48 */
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     { Bad_Opcode },
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     /* 50 */
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     { Bad_Opcode },
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     /* 58 */
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     { Bad_Opcode },
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     /* 60 */
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     { Bad_Opcode },
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     /* 68 */
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     { Bad_Opcode },
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     /* 70 */
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     { Bad_Opcode },
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     /* 78 */
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     { Bad_Opcode },
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     /* 80 */
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     { Bad_Opcode },
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5340     { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5341     { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5342     /* 88 */
5343     { Bad_Opcode },
5344     { Bad_Opcode },
5345     { Bad_Opcode },
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5350     { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5351     /* 90 */
5352     { Bad_Opcode },
5353     { Bad_Opcode },
5354     { Bad_Opcode },
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5358     { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5359     { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5360     /* 98 */
5361     { Bad_Opcode },
5362     { Bad_Opcode },
5363     { Bad_Opcode },
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5368     { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5369     /* a0 */
5370     { Bad_Opcode },
5371     { Bad_Opcode },
5372     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5373     { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5374     { Bad_Opcode },
5375     { Bad_Opcode },
5376     { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5377     { Bad_Opcode },
5378     /* a8 */
5379     { Bad_Opcode },
5380     { Bad_Opcode },
5381     { Bad_Opcode },
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     /* b0 */
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     { Bad_Opcode },
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5395     { Bad_Opcode },
5396     /* b8 */
5397     { Bad_Opcode },
5398     { Bad_Opcode },
5399     { Bad_Opcode },
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     /* c0 */
5406     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5407     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5408     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5409     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5410     { Bad_Opcode },
5411     { Bad_Opcode },
5412     { Bad_Opcode },
5413     { Bad_Opcode },
5414     /* c8 */
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     { Bad_Opcode },
5418     { Bad_Opcode },
5419     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5420     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5421     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5422     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5423     /* d0 */
5424     { Bad_Opcode },
5425     { Bad_Opcode },
5426     { Bad_Opcode },
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     /* d8 */
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     { Bad_Opcode },
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     /* e0 */
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     { Bad_Opcode },
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     /* e8 */
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     { Bad_Opcode },
5454     { Bad_Opcode },
5455     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5456     { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5457     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5458     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5459     /* f0 */
5460     { Bad_Opcode },
5461     { Bad_Opcode },
5462     { Bad_Opcode },
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     /* f8 */
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     { Bad_Opcode },
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477   },
5478   /* XOP_09 */
5479   {
5480     /* 00 */
5481     { Bad_Opcode },
5482     { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5483     { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5484     { Bad_Opcode },
5485     { Bad_Opcode },
5486     { Bad_Opcode },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     /* 08 */
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     { Bad_Opcode },
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     /* 10 */
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { Bad_Opcode },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     /* 18 */
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     { Bad_Opcode },
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     /* 20 */
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     { Bad_Opcode },
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     /* 28 */
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     { Bad_Opcode },
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     /* 30 */
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     { Bad_Opcode },
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     /* 38 */
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     { Bad_Opcode },
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     /* 40 */
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     { Bad_Opcode },
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     /* 48 */
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     { Bad_Opcode },
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     /* 50 */
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     { Bad_Opcode },
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     /* 58 */
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     { Bad_Opcode },
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     /* 60 */
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     { Bad_Opcode },
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     /* 68 */
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     { Bad_Opcode },
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     /* 70 */
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     { Bad_Opcode },
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     /* 78 */
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     { Bad_Opcode },
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     /* 80 */
5625     { VEX_W_TABLE (VEX_W_XOP_09_80) },
5626     { VEX_W_TABLE (VEX_W_XOP_09_81) },
5627     { VEX_W_TABLE (VEX_W_XOP_09_82) },
5628     { VEX_W_TABLE (VEX_W_XOP_09_83) },
5629     { Bad_Opcode },
5630     { Bad_Opcode },
5631     { Bad_Opcode },
5632     { Bad_Opcode },
5633     /* 88 */
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     { Bad_Opcode },
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     /* 90 */
5643     { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5644     { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5645     { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5646     { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5647     { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5648     { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5649     { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5650     { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5651     /* 98 */
5652     { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5653     { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5654     { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5655     { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5656     { Bad_Opcode },
5657     { Bad_Opcode },
5658     { Bad_Opcode },
5659     { Bad_Opcode },
5660     /* a0 */
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     { Bad_Opcode },
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     /* a8 */
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     { Bad_Opcode },
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     /* b0 */
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     { Bad_Opcode },
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     /* b8 */
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     { Bad_Opcode },
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     /* c0 */
5697     { Bad_Opcode },
5698     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5699     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5700     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5701     { Bad_Opcode },
5702     { Bad_Opcode },
5703     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5704     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5705     /* c8 */
5706     { Bad_Opcode },
5707     { Bad_Opcode },
5708     { Bad_Opcode },
5709     { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { Bad_Opcode },
5713     { Bad_Opcode },
5714     /* d0 */
5715     { Bad_Opcode },
5716     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5717     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5718     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5719     { Bad_Opcode },
5720     { Bad_Opcode },
5721     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5722     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5723     /* d8 */
5724     { Bad_Opcode },
5725     { Bad_Opcode },
5726     { Bad_Opcode },
5727     { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { Bad_Opcode },
5731     { Bad_Opcode },
5732     /* e0 */
5733     { Bad_Opcode },
5734     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5735     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5736     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5737     { Bad_Opcode },
5738     { Bad_Opcode },
5739     { Bad_Opcode },
5740     { Bad_Opcode },
5741     /* e8 */
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     { Bad_Opcode },
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     /* f0 */
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     { Bad_Opcode },
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     /* f8 */
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     { Bad_Opcode },
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768   },
5769   /* XOP_0A */
5770   {
5771     /* 00 */
5772     { Bad_Opcode },
5773     { Bad_Opcode },
5774     { Bad_Opcode },
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     /* 08 */
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     { Bad_Opcode },
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     /* 10 */
5790     { "bextrS", { Gdq, Edq, Id }, 0 },
5791     { Bad_Opcode },
5792     { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
5793     { Bad_Opcode },
5794     { Bad_Opcode },
5795     { Bad_Opcode },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     /* 18 */
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     { Bad_Opcode },
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     /* 20 */
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     { Bad_Opcode },
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     /* 28 */
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     { Bad_Opcode },
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     /* 30 */
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     { Bad_Opcode },
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     /* 38 */
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     { Bad_Opcode },
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     /* 40 */
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     { Bad_Opcode },
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     /* 48 */
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     { Bad_Opcode },
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     /* 50 */
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     { Bad_Opcode },
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     /* 58 */
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     { Bad_Opcode },
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     /* 60 */
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     { Bad_Opcode },
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     /* 68 */
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     { Bad_Opcode },
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     /* 70 */
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     { Bad_Opcode },
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     /* 78 */
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     { Bad_Opcode },
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     /* 80 */
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     { Bad_Opcode },
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     /* 88 */
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     { Bad_Opcode },
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     /* 90 */
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     { Bad_Opcode },
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     /* 98 */
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     { Bad_Opcode },
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     /* a0 */
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     { Bad_Opcode },
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     /* a8 */
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     { Bad_Opcode },
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     /* b0 */
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     { Bad_Opcode },
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     /* b8 */
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     { Bad_Opcode },
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     /* c0 */
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     { Bad_Opcode },
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     /* c8 */
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     { Bad_Opcode },
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     /* d0 */
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     { Bad_Opcode },
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     /* d8 */
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     { Bad_Opcode },
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     /* e0 */
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     { Bad_Opcode },
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     /* e8 */
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     { Bad_Opcode },
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     /* f0 */
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     { Bad_Opcode },
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     /* f8 */
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     { Bad_Opcode },
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059   },
6060 };
6061
6062 static const struct dis386 vex_table[][256] = {
6063   /* VEX_0F */
6064   {
6065     /* 00 */
6066     { Bad_Opcode },
6067     { Bad_Opcode },
6068     { Bad_Opcode },
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     /* 08 */
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     { Bad_Opcode },
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     /* 10 */
6084     { PREFIX_TABLE (PREFIX_0F10) },
6085     { PREFIX_TABLE (PREFIX_0F11) },
6086     { PREFIX_TABLE (PREFIX_VEX_0F12) },
6087     { VEX_LEN_TABLE (VEX_LEN_0F13) },
6088     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6089     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6090     { PREFIX_TABLE (PREFIX_VEX_0F16) },
6091     { VEX_LEN_TABLE (VEX_LEN_0F17) },
6092     /* 18 */
6093     { Bad_Opcode },
6094     { Bad_Opcode },
6095     { Bad_Opcode },
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     /* 20 */
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     { Bad_Opcode },
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     /* 28 */
6111     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
6112     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
6113     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6114     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
6115     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6116     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6117     { PREFIX_TABLE (PREFIX_0F2E) },
6118     { PREFIX_TABLE (PREFIX_0F2F) },
6119     /* 30 */
6120     { Bad_Opcode },
6121     { Bad_Opcode },
6122     { Bad_Opcode },
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     /* 38 */
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     { Bad_Opcode },
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     /* 40 */
6138     { Bad_Opcode },
6139     { VEX_LEN_TABLE (VEX_LEN_0F41) },
6140     { VEX_LEN_TABLE (VEX_LEN_0F42) },
6141     { Bad_Opcode },
6142     { VEX_LEN_TABLE (VEX_LEN_0F44) },
6143     { VEX_LEN_TABLE (VEX_LEN_0F45) },
6144     { VEX_LEN_TABLE (VEX_LEN_0F46) },
6145     { VEX_LEN_TABLE (VEX_LEN_0F47) },
6146     /* 48 */
6147     { Bad_Opcode },
6148     { Bad_Opcode },
6149     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6150     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6151     { Bad_Opcode },
6152     { Bad_Opcode },
6153     { Bad_Opcode },
6154     { Bad_Opcode },
6155     /* 50 */
6156     { "vmovmskpX",      { Gdq, Ux }, PREFIX_OPCODE },
6157     { PREFIX_TABLE (PREFIX_0F51) },
6158     { PREFIX_TABLE (PREFIX_0F52) },
6159     { PREFIX_TABLE (PREFIX_0F53) },
6160     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6161     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
6162     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
6163     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6164     /* 58 */
6165     { PREFIX_TABLE (PREFIX_0F58) },
6166     { PREFIX_TABLE (PREFIX_0F59) },
6167     { PREFIX_TABLE (PREFIX_0F5A) },
6168     { PREFIX_TABLE (PREFIX_0F5B) },
6169     { PREFIX_TABLE (PREFIX_0F5C) },
6170     { PREFIX_TABLE (PREFIX_0F5D) },
6171     { PREFIX_TABLE (PREFIX_0F5E) },
6172     { PREFIX_TABLE (PREFIX_0F5F) },
6173     /* 60 */
6174     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
6175     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
6176     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
6177     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
6178     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
6179     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
6180     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
6181     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
6182     /* 68 */
6183     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
6184     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6185     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6186     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6187     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6188     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6189     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6190     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6191     /* 70 */
6192     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6193     { REG_TABLE (REG_VEX_0F71) },
6194     { REG_TABLE (REG_VEX_0F72) },
6195     { REG_TABLE (REG_VEX_0F73) },
6196     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6197     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6198     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6199     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6200     /* 78 */
6201     { Bad_Opcode },
6202     { Bad_Opcode },
6203     { Bad_Opcode },
6204     { Bad_Opcode },
6205     { PREFIX_TABLE (PREFIX_0F7C) },
6206     { PREFIX_TABLE (PREFIX_0F7D) },
6207     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6208     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6209     /* 80 */
6210     { Bad_Opcode },
6211     { Bad_Opcode },
6212     { Bad_Opcode },
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     /* 88 */
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     { Bad_Opcode },
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     /* 90 */
6228     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6229     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6230     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6231     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6232     { Bad_Opcode },
6233     { Bad_Opcode },
6234     { Bad_Opcode },
6235     { Bad_Opcode },
6236     /* 98 */
6237     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6238     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6239     { Bad_Opcode },
6240     { Bad_Opcode },
6241     { Bad_Opcode },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     /* a0 */
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     { Bad_Opcode },
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     /* a8 */
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     { Bad_Opcode },
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { REG_TABLE (REG_VEX_0FAE) },
6262     { Bad_Opcode },
6263     /* b0 */
6264     { Bad_Opcode },
6265     { Bad_Opcode },
6266     { Bad_Opcode },
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     /* b8 */
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     { Bad_Opcode },
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     /* c0 */
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     { PREFIX_TABLE (PREFIX_0FC2) },
6285     { Bad_Opcode },
6286     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6287     { "vpextrw",        { Gd, Uxmm, Ib }, PREFIX_DATA },
6288     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6289     { Bad_Opcode },
6290     /* c8 */
6291     { Bad_Opcode },
6292     { Bad_Opcode },
6293     { Bad_Opcode },
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     /* d0 */
6300     { PREFIX_TABLE (PREFIX_0FD0) },
6301     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6302     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6303     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6304     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6305     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6306     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6307     { "vpmovmskb",      { Gdq, Ux }, PREFIX_DATA },
6308     /* d8 */
6309     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6310     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6311     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6312     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6313     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6314     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6315     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6316     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6317     /* e0 */
6318     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6319     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6320     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6321     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6322     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6323     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6324     { PREFIX_TABLE (PREFIX_0FE6) },
6325     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
6326     /* e8 */
6327     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6328     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6329     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6330     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6331     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6332     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6333     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6334     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6335     /* f0 */
6336     { PREFIX_TABLE (PREFIX_0FF0) },
6337     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6338     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6339     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6340     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6341     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6342     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6343     { "vmaskmovdqu",    { XM, Uxmm }, PREFIX_DATA },
6344     /* f8 */
6345     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6346     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6347     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6348     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6349     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6350     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6351     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6352     { Bad_Opcode },
6353   },
6354   /* VEX_0F38 */
6355   {
6356     /* 00 */
6357     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6358     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6359     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6360     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6361     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6362     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6363     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6364     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6365     /* 08 */
6366     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6367     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6368     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6369     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6370     { VEX_W_TABLE (VEX_W_0F380C) },
6371     { VEX_W_TABLE (VEX_W_0F380D) },
6372     { VEX_W_TABLE (VEX_W_0F380E) },
6373     { VEX_W_TABLE (VEX_W_0F380F) },
6374     /* 10 */
6375     { Bad_Opcode },
6376     { Bad_Opcode },
6377     { Bad_Opcode },
6378     { VEX_W_TABLE (VEX_W_0F3813) },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6382     { "vptest",         { XM, EXx }, PREFIX_DATA },
6383     /* 18 */
6384     { VEX_W_TABLE (VEX_W_0F3818) },
6385     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6386     { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6387     { Bad_Opcode },
6388     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6389     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6390     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6391     { Bad_Opcode },
6392     /* 20 */
6393     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6394     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6395     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6396     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6397     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6398     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6399     { Bad_Opcode },
6400     { Bad_Opcode },
6401     /* 28 */
6402     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6403     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6404     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
6405     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6406     { VEX_W_TABLE (VEX_W_0F382C) },
6407     { VEX_W_TABLE (VEX_W_0F382D) },
6408     { VEX_W_TABLE (VEX_W_0F382E) },
6409     { VEX_W_TABLE (VEX_W_0F382F) },
6410     /* 30 */
6411     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6412     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6413     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6414     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6415     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6416     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6417     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6418     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6419     /* 38 */
6420     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6421     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6422     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6423     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6424     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6425     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6426     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6427     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6428     /* 40 */
6429     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6430     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6431     { Bad_Opcode },
6432     { Bad_Opcode },
6433     { Bad_Opcode },
6434     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6435     { VEX_W_TABLE (VEX_W_0F3846) },
6436     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6437     /* 48 */
6438     { Bad_Opcode },
6439     { X86_64_TABLE (X86_64_VEX_0F3849) },
6440     { Bad_Opcode },
6441     { X86_64_TABLE (X86_64_VEX_0F384B) },
6442     { Bad_Opcode },
6443     { Bad_Opcode },
6444     { Bad_Opcode },
6445     { Bad_Opcode },
6446     /* 50 */
6447     { VEX_W_TABLE (VEX_W_0F3850) },
6448     { VEX_W_TABLE (VEX_W_0F3851) },
6449     { VEX_W_TABLE (VEX_W_0F3852) },
6450     { VEX_W_TABLE (VEX_W_0F3853) },
6451     { Bad_Opcode },
6452     { Bad_Opcode },
6453     { Bad_Opcode },
6454     { Bad_Opcode },
6455     /* 58 */
6456     { VEX_W_TABLE (VEX_W_0F3858) },
6457     { VEX_W_TABLE (VEX_W_0F3859) },
6458     { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6459     { Bad_Opcode },
6460     { X86_64_TABLE (X86_64_VEX_0F385C) },
6461     { Bad_Opcode },
6462     { X86_64_TABLE (X86_64_VEX_0F385E) },
6463     { Bad_Opcode },
6464     /* 60 */
6465     { Bad_Opcode },
6466     { Bad_Opcode },
6467     { Bad_Opcode },
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     /* 68 */
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     { Bad_Opcode },
6477     { Bad_Opcode },
6478     { X86_64_TABLE (X86_64_VEX_0F386C) },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { Bad_Opcode },
6482     /* 70 */
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { Bad_Opcode },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     /* 78 */
6492     { VEX_W_TABLE (VEX_W_0F3878) },
6493     { VEX_W_TABLE (VEX_W_0F3879) },
6494     { Bad_Opcode },
6495     { Bad_Opcode },
6496     { Bad_Opcode },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     /* 80 */
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     { Bad_Opcode },
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     /* 88 */
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     { Bad_Opcode },
6513     { Bad_Opcode },
6514     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
6515     { Bad_Opcode },
6516     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
6517     { Bad_Opcode },
6518     /* 90 */
6519     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6520     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6521     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6522     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6523     { Bad_Opcode },
6524     { Bad_Opcode },
6525     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6526     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6527     /* 98 */
6528     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6529     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6530     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6531     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6532     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6533     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6534     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6535     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6536     /* a0 */
6537     { Bad_Opcode },
6538     { Bad_Opcode },
6539     { Bad_Opcode },
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6544     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6545     /* a8 */
6546     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6547     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6548     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6549     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6550     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6551     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6552     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6553     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6554     /* b0 */
6555     { VEX_W_TABLE (VEX_W_0F38B0) },
6556     { VEX_W_TABLE (VEX_W_0F38B1) },
6557     { Bad_Opcode },
6558     { Bad_Opcode },
6559     { VEX_W_TABLE (VEX_W_0F38B4) },
6560     { VEX_W_TABLE (VEX_W_0F38B5) },
6561     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6562     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6563     /* b8 */
6564     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6565     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6566     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6567     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6568     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6569     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6570     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6571     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6572     /* c0 */
6573     { Bad_Opcode },
6574     { Bad_Opcode },
6575     { Bad_Opcode },
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     /* c8 */
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     { Bad_Opcode },
6585     { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6586     { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6587     { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6588     { Bad_Opcode },
6589     { VEX_W_TABLE (VEX_W_0F38CF) },
6590     /* d0 */
6591     { Bad_Opcode },
6592     { Bad_Opcode },
6593     { VEX_W_TABLE (VEX_W_0F38D2) },
6594     { VEX_W_TABLE (VEX_W_0F38D3) },
6595     { Bad_Opcode },
6596     { Bad_Opcode },
6597     { Bad_Opcode },
6598     { Bad_Opcode },
6599     /* d8 */
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     { VEX_W_TABLE (VEX_W_0F38DA) },
6603     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6604     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6605     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6606     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6607     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6608     /* e0 */
6609     { X86_64_TABLE (X86_64_VEX_0F38E0) },
6610     { X86_64_TABLE (X86_64_VEX_0F38E1) },
6611     { X86_64_TABLE (X86_64_VEX_0F38E2) },
6612     { X86_64_TABLE (X86_64_VEX_0F38E3) },
6613     { X86_64_TABLE (X86_64_VEX_0F38E4) },
6614     { X86_64_TABLE (X86_64_VEX_0F38E5) },
6615     { X86_64_TABLE (X86_64_VEX_0F38E6) },
6616     { X86_64_TABLE (X86_64_VEX_0F38E7) },
6617     /* e8 */
6618     { X86_64_TABLE (X86_64_VEX_0F38E8) },
6619     { X86_64_TABLE (X86_64_VEX_0F38E9) },
6620     { X86_64_TABLE (X86_64_VEX_0F38EA) },
6621     { X86_64_TABLE (X86_64_VEX_0F38EB) },
6622     { X86_64_TABLE (X86_64_VEX_0F38EC) },
6623     { X86_64_TABLE (X86_64_VEX_0F38ED) },
6624     { X86_64_TABLE (X86_64_VEX_0F38EE) },
6625     { X86_64_TABLE (X86_64_VEX_0F38EF) },
6626     /* f0 */
6627     { Bad_Opcode },
6628     { Bad_Opcode },
6629     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6630     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6633     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6634     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6635     /* f8 */
6636     { Bad_Opcode },
6637     { Bad_Opcode },
6638     { Bad_Opcode },
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644   },
6645   /* VEX_0F3A */
6646   {
6647     /* 00 */
6648     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6649     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6650     { VEX_W_TABLE (VEX_W_0F3A02) },
6651     { Bad_Opcode },
6652     { VEX_W_TABLE (VEX_W_0F3A04) },
6653     { VEX_W_TABLE (VEX_W_0F3A05) },
6654     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6655     { Bad_Opcode },
6656     /* 08 */
6657     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6658     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6659     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6660     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6661     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6662     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6663     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6664     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6665     /* 10 */
6666     { Bad_Opcode },
6667     { Bad_Opcode },
6668     { Bad_Opcode },
6669     { Bad_Opcode },
6670     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6671     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6672     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6673     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6674     /* 18 */
6675     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6676     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6677     { Bad_Opcode },
6678     { Bad_Opcode },
6679     { Bad_Opcode },
6680     { VEX_W_TABLE (VEX_W_0F3A1D) },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     /* 20 */
6684     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6685     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6686     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6687     { Bad_Opcode },
6688     { Bad_Opcode },
6689     { Bad_Opcode },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     /* 28 */
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     { Bad_Opcode },
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     /* 30 */
6702     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6703     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6704     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6705     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6706     { Bad_Opcode },
6707     { Bad_Opcode },
6708     { Bad_Opcode },
6709     { Bad_Opcode },
6710     /* 38 */
6711     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6712     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6713     { Bad_Opcode },
6714     { Bad_Opcode },
6715     { Bad_Opcode },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     /* 40 */
6720     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6721     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6722     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6723     { Bad_Opcode },
6724     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6725     { Bad_Opcode },
6726     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6727     { Bad_Opcode },
6728     /* 48 */
6729     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6730     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6731     { VEX_W_TABLE (VEX_W_0F3A4A) },
6732     { VEX_W_TABLE (VEX_W_0F3A4B) },
6733     { VEX_W_TABLE (VEX_W_0F3A4C) },
6734     { Bad_Opcode },
6735     { Bad_Opcode },
6736     { Bad_Opcode },
6737     /* 50 */
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     { Bad_Opcode },
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     /* 58 */
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     { Bad_Opcode },
6750     { Bad_Opcode },
6751     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6752     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6753     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6754     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6755     /* 60 */
6756     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6757     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6758     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6759     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6760     { Bad_Opcode },
6761     { Bad_Opcode },
6762     { Bad_Opcode },
6763     { Bad_Opcode },
6764     /* 68 */
6765     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6766     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6767     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6768     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6769     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6770     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6771     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6772     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6773     /* 70 */
6774     { Bad_Opcode },
6775     { Bad_Opcode },
6776     { Bad_Opcode },
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     /* 78 */
6783     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6784     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6785     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6786     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6787     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6788     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6789     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6790     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6791     /* 80 */
6792     { Bad_Opcode },
6793     { Bad_Opcode },
6794     { Bad_Opcode },
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     /* 88 */
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     { Bad_Opcode },
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     /* 90 */
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     { Bad_Opcode },
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     /* 98 */
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     { Bad_Opcode },
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     /* a0 */
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     { Bad_Opcode },
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     /* a8 */
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     { Bad_Opcode },
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     /* b0 */
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     { Bad_Opcode },
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     /* b8 */
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     { Bad_Opcode },
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     /* c0 */
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     { Bad_Opcode },
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     /* c8 */
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     { Bad_Opcode },
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { VEX_W_TABLE (VEX_W_0F3ACE) },
6880     { VEX_W_TABLE (VEX_W_0F3ACF) },
6881     /* d0 */
6882     { Bad_Opcode },
6883     { Bad_Opcode },
6884     { Bad_Opcode },
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     /* d8 */
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     { Bad_Opcode },
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { VEX_W_TABLE (VEX_W_0F3ADE) },
6898     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6899     /* e0 */
6900     { Bad_Opcode },
6901     { Bad_Opcode },
6902     { Bad_Opcode },
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     /* e8 */
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     { Bad_Opcode },
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     /* f0 */
6918     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6919     { Bad_Opcode },
6920     { Bad_Opcode },
6921     { Bad_Opcode },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     /* f8 */
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     { Bad_Opcode },
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935   },
6936 };
6937
6938 #include "i386-dis-evex.h"
6939
6940 static const struct dis386 vex_len_table[][2] = {
6941   /* VEX_LEN_0F12_P_0 */
6942   {
6943     { MOD_TABLE (MOD_0F12_PREFIX_0) },
6944   },
6945
6946   /* VEX_LEN_0F12_P_2 */
6947   {
6948     { "%XEVmovlpYX",    { XM, Vex, Mq }, 0 },
6949   },
6950
6951   /* VEX_LEN_0F13 */
6952   {
6953     { "%XEVmovlpYX",    { Mq, XM }, PREFIX_OPCODE },
6954   },
6955
6956   /* VEX_LEN_0F16_P_0 */
6957   {
6958     { MOD_TABLE (MOD_0F16_PREFIX_0) },
6959   },
6960
6961   /* VEX_LEN_0F16_P_2 */
6962   {
6963     { "%XEVmovhpYX",    { XM, Vex, Mq }, 0 },
6964   },
6965
6966   /* VEX_LEN_0F17 */
6967   {
6968     { "%XEVmovhpYX",    { Mq, XM }, PREFIX_OPCODE },
6969   },
6970
6971   /* VEX_LEN_0F41 */
6972   {
6973     { Bad_Opcode },
6974     { VEX_W_TABLE (VEX_W_0F41_L_1) },
6975   },
6976
6977   /* VEX_LEN_0F42 */
6978   {
6979     { Bad_Opcode },
6980     { VEX_W_TABLE (VEX_W_0F42_L_1) },
6981   },
6982
6983   /* VEX_LEN_0F44 */
6984   {
6985     { VEX_W_TABLE (VEX_W_0F44_L_0) },
6986   },
6987
6988   /* VEX_LEN_0F45 */
6989   {
6990     { Bad_Opcode },
6991     { VEX_W_TABLE (VEX_W_0F45_L_1) },
6992   },
6993
6994   /* VEX_LEN_0F46 */
6995   {
6996     { Bad_Opcode },
6997     { VEX_W_TABLE (VEX_W_0F46_L_1) },
6998   },
6999
7000   /* VEX_LEN_0F47 */
7001   {
7002     { Bad_Opcode },
7003     { VEX_W_TABLE (VEX_W_0F47_L_1) },
7004   },
7005
7006   /* VEX_LEN_0F4A */
7007   {
7008     { Bad_Opcode },
7009     { VEX_W_TABLE (VEX_W_0F4A_L_1) },
7010   },
7011
7012   /* VEX_LEN_0F4B */
7013   {
7014     { Bad_Opcode },
7015     { VEX_W_TABLE (VEX_W_0F4B_L_1) },
7016   },
7017
7018   /* VEX_LEN_0F6E */
7019   {
7020     { "%XEvmovYK",      { XMScalar, Edq }, PREFIX_DATA },
7021   },
7022
7023   /* VEX_LEN_0F77 */
7024   {
7025     { "vzeroupper",     { XX }, 0 },
7026     { "vzeroall",       { XX }, 0 },
7027   },
7028
7029   /* VEX_LEN_0F7E_P_1 */
7030   {
7031     { "%XEvmovqY",      { XMScalar, EXq }, 0 },
7032   },
7033
7034   /* VEX_LEN_0F7E_P_2 */
7035   {
7036     { "%XEvmovK",       { Edq, XMScalar }, 0 },
7037   },
7038
7039   /* VEX_LEN_0F90 */
7040   {
7041     { VEX_W_TABLE (VEX_W_0F90_L_0) },
7042   },
7043
7044   /* VEX_LEN_0F91 */
7045   {
7046     { VEX_W_TABLE (VEX_W_0F91_L_0) },
7047   },
7048
7049   /* VEX_LEN_0F92 */
7050   {
7051     { VEX_W_TABLE (VEX_W_0F92_L_0) },
7052   },
7053
7054   /* VEX_LEN_0F93 */
7055   {
7056     { VEX_W_TABLE (VEX_W_0F93_L_0) },
7057   },
7058
7059   /* VEX_LEN_0F98 */
7060   {
7061     { VEX_W_TABLE (VEX_W_0F98_L_0) },
7062   },
7063
7064   /* VEX_LEN_0F99 */
7065   {
7066     { VEX_W_TABLE (VEX_W_0F99_L_0) },
7067   },
7068
7069   /* VEX_LEN_0FAE_R_2 */
7070   {
7071     { "vldmxcsr",       { Md }, 0 },
7072   },
7073
7074   /* VEX_LEN_0FAE_R_3 */
7075   {
7076     { "vstmxcsr",       { Md }, 0 },
7077   },
7078
7079   /* VEX_LEN_0FC4 */
7080   {
7081     { "%XEvpinsrwY",    { XM, Vex, Edw, Ib }, PREFIX_DATA },
7082   },
7083
7084   /* VEX_LEN_0FD6 */
7085   {
7086     { "%XEvmovqY",      { EXqS, XMScalar }, PREFIX_DATA },
7087   },
7088
7089   /* VEX_LEN_0F3816 */
7090   {
7091     { Bad_Opcode },
7092     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7093   },
7094
7095   /* VEX_LEN_0F3819 */
7096   {
7097     { Bad_Opcode },
7098     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7099   },
7100
7101   /* VEX_LEN_0F381A */
7102   {
7103     { Bad_Opcode },
7104     { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7105   },
7106
7107   /* VEX_LEN_0F3836 */
7108   {
7109     { Bad_Opcode },
7110     { VEX_W_TABLE (VEX_W_0F3836) },
7111   },
7112
7113   /* VEX_LEN_0F3841 */
7114   {
7115     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
7116   },
7117
7118   /* VEX_LEN_0F3849_X86_64 */
7119   {
7120     { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7121   },
7122
7123   /* VEX_LEN_0F384B_X86_64 */
7124   {
7125     { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7126   },
7127
7128   /* VEX_LEN_0F385A */
7129   {
7130     { Bad_Opcode },
7131     { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7132   },
7133
7134   /* VEX_LEN_0F385C_X86_64 */
7135   {
7136     { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7137   },
7138
7139   /* VEX_LEN_0F385E_X86_64 */
7140   {
7141     { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7142   },
7143
7144   /* VEX_LEN_0F386C_X86_64 */
7145   {
7146     { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7147   },
7148
7149   /* VEX_LEN_0F38CB_P_3_W_0 */
7150   {
7151     { Bad_Opcode },
7152     { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7153   },
7154
7155   /* VEX_LEN_0F38CC_P_3_W_0 */
7156   {
7157     { Bad_Opcode },
7158     { "vsha512msg1", { XM, Rxmmq }, 0 },
7159   },
7160
7161   /* VEX_LEN_0F38CD_P_3_W_0 */
7162   {
7163     { Bad_Opcode },
7164     { "vsha512msg2", { XM, Rymm }, 0 },
7165   },
7166
7167   /* VEX_LEN_0F38DA_W_0_P_0 */
7168   {
7169     { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7170   },
7171
7172   /* VEX_LEN_0F38DA_W_0_P_2 */
7173   {
7174     { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7175   },
7176
7177   /* VEX_LEN_0F38DB */
7178   {
7179     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7180   },
7181
7182   /* VEX_LEN_0F38F2 */
7183   {
7184     { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7185   },
7186
7187   /* VEX_LEN_0F38F3 */
7188   {
7189     { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7190   },
7191
7192   /* VEX_LEN_0F38F5 */
7193   {
7194     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7195   },
7196
7197   /* VEX_LEN_0F38F6 */
7198   {
7199     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7200   },
7201
7202   /* VEX_LEN_0F38F7 */
7203   {
7204     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7205   },
7206
7207   /* VEX_LEN_0F3A00 */
7208   {
7209     { Bad_Opcode },
7210     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7211   },
7212
7213   /* VEX_LEN_0F3A01 */
7214   {
7215     { Bad_Opcode },
7216     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7217   },
7218
7219   /* VEX_LEN_0F3A06 */
7220   {
7221     { Bad_Opcode },
7222     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7223   },
7224
7225   /* VEX_LEN_0F3A14 */
7226   {
7227     { "%XEvpextrb",     { Edb, XM, Ib }, PREFIX_DATA },
7228   },
7229
7230   /* VEX_LEN_0F3A15 */
7231   {
7232     { "%XEvpextrw",     { Edw, XM, Ib }, PREFIX_DATA },
7233   },
7234
7235   /* VEX_LEN_0F3A16  */
7236   {
7237     { "%XEvpextrK",     { Edq, XM, Ib }, PREFIX_DATA },
7238   },
7239
7240   /* VEX_LEN_0F3A17 */
7241   {
7242     { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7243   },
7244
7245   /* VEX_LEN_0F3A18 */
7246   {
7247     { Bad_Opcode },
7248     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7249   },
7250
7251   /* VEX_LEN_0F3A19 */
7252   {
7253     { Bad_Opcode },
7254     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7255   },
7256
7257   /* VEX_LEN_0F3A20 */
7258   {
7259     { "%XEvpinsrbY",    { XM, Vex, Edb, Ib }, PREFIX_DATA },
7260   },
7261
7262   /* VEX_LEN_0F3A21 */
7263   {
7264     { "%XEvinsertpsY",  { XM, Vex, EXd, Ib }, PREFIX_DATA },
7265   },
7266
7267   /* VEX_LEN_0F3A22 */
7268   {
7269     { "%XEvpinsrYK",    { XM, Vex, Edq, Ib }, PREFIX_DATA },
7270   },
7271
7272   /* VEX_LEN_0F3A30 */
7273   {
7274     { "kshiftr%BW",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7275   },
7276
7277   /* VEX_LEN_0F3A31 */
7278   {
7279     { "kshiftr%DQ",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7280   },
7281
7282   /* VEX_LEN_0F3A32 */
7283   {
7284     { "kshiftl%BW",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7285   },
7286
7287   /* VEX_LEN_0F3A33 */
7288   {
7289     { "kshiftl%DQ",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7290   },
7291
7292   /* VEX_LEN_0F3A38 */
7293   {
7294     { Bad_Opcode },
7295     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7296   },
7297
7298   /* VEX_LEN_0F3A39 */
7299   {
7300     { Bad_Opcode },
7301     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7302   },
7303
7304   /* VEX_LEN_0F3A41 */
7305   {
7306     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7307   },
7308
7309   /* VEX_LEN_0F3A46 */
7310   {
7311     { Bad_Opcode },
7312     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7313   },
7314
7315   /* VEX_LEN_0F3A60 */
7316   {
7317     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7318   },
7319
7320   /* VEX_LEN_0F3A61 */
7321   {
7322     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7323   },
7324
7325   /* VEX_LEN_0F3A62 */
7326   {
7327     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7328   },
7329
7330   /* VEX_LEN_0F3A63 */
7331   {
7332     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7333   },
7334
7335   /* VEX_LEN_0F3ADE_W_0 */
7336   {
7337     { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7338   },
7339
7340   /* VEX_LEN_0F3ADF */
7341   {
7342     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7343   },
7344
7345   /* VEX_LEN_0F3AF0 */
7346   {
7347     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7348   },
7349
7350   /* VEX_LEN_MAP7_F8 */
7351   {
7352     { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7353   },
7354
7355   /* VEX_LEN_XOP_08_85 */
7356   {
7357     { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7358   },
7359
7360   /* VEX_LEN_XOP_08_86 */
7361   {
7362     { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7363   },
7364
7365   /* VEX_LEN_XOP_08_87 */
7366   {
7367     { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7368   },
7369
7370   /* VEX_LEN_XOP_08_8E */
7371   {
7372     { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7373   },
7374
7375   /* VEX_LEN_XOP_08_8F */
7376   {
7377     { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7378   },
7379
7380   /* VEX_LEN_XOP_08_95 */
7381   {
7382     { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7383   },
7384
7385   /* VEX_LEN_XOP_08_96 */
7386   {
7387     { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7388   },
7389
7390   /* VEX_LEN_XOP_08_97 */
7391   {
7392     { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7393   },
7394
7395   /* VEX_LEN_XOP_08_9E */
7396   {
7397     { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7398   },
7399
7400   /* VEX_LEN_XOP_08_9F */
7401   {
7402     { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7403   },
7404
7405   /* VEX_LEN_XOP_08_A3 */
7406   {
7407     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7408   },
7409
7410   /* VEX_LEN_XOP_08_A6 */
7411   {
7412     { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7413   },
7414
7415   /* VEX_LEN_XOP_08_B6 */
7416   {
7417     { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7418   },
7419
7420   /* VEX_LEN_XOP_08_C0 */
7421   {
7422     { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7423   },
7424
7425   /* VEX_LEN_XOP_08_C1 */
7426   {
7427     { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7428   },
7429
7430   /* VEX_LEN_XOP_08_C2 */
7431   {
7432     { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7433   },
7434
7435   /* VEX_LEN_XOP_08_C3 */
7436   {
7437     { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7438   },
7439
7440   /* VEX_LEN_XOP_08_CC */
7441   {
7442     { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7443   },
7444
7445   /* VEX_LEN_XOP_08_CD */
7446   {
7447     { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7448   },
7449
7450   /* VEX_LEN_XOP_08_CE */
7451   {
7452     { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7453   },
7454
7455   /* VEX_LEN_XOP_08_CF */
7456   {
7457     { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7458   },
7459
7460   /* VEX_LEN_XOP_08_EC */
7461   {
7462     { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7463   },
7464
7465   /* VEX_LEN_XOP_08_ED */
7466   {
7467     { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7468   },
7469
7470   /* VEX_LEN_XOP_08_EE */
7471   {
7472     { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7473   },
7474
7475   /* VEX_LEN_XOP_08_EF */
7476   {
7477     { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7478   },
7479
7480   /* VEX_LEN_XOP_09_01 */
7481   {
7482     { REG_TABLE (REG_XOP_09_01_L_0) },
7483   },
7484
7485   /* VEX_LEN_XOP_09_02 */
7486   {
7487     { REG_TABLE (REG_XOP_09_02_L_0) },
7488   },
7489
7490   /* VEX_LEN_XOP_09_12 */
7491   {
7492     { REG_TABLE (REG_XOP_09_12_L_0) },
7493   },
7494
7495   /* VEX_LEN_XOP_09_82_W_0 */
7496   {
7497     { "vfrczss",        { XM, EXd }, 0 },
7498   },
7499
7500   /* VEX_LEN_XOP_09_83_W_0 */
7501   {
7502     { "vfrczsd",        { XM, EXq }, 0 },
7503   },
7504
7505   /* VEX_LEN_XOP_09_90 */
7506   {
7507     { "vprotb",         { XM, EXx, VexW }, 0 },
7508   },
7509
7510   /* VEX_LEN_XOP_09_91 */
7511   {
7512     { "vprotw",         { XM, EXx, VexW }, 0 },
7513   },
7514
7515   /* VEX_LEN_XOP_09_92 */
7516   {
7517     { "vprotd",         { XM, EXx, VexW }, 0 },
7518   },
7519
7520   /* VEX_LEN_XOP_09_93 */
7521   {
7522     { "vprotq",         { XM, EXx, VexW }, 0 },
7523   },
7524
7525   /* VEX_LEN_XOP_09_94 */
7526   {
7527     { "vpshlb",         { XM, EXx, VexW }, 0 },
7528   },
7529
7530   /* VEX_LEN_XOP_09_95 */
7531   {
7532     { "vpshlw",         { XM, EXx, VexW }, 0 },
7533   },
7534
7535   /* VEX_LEN_XOP_09_96 */
7536   {
7537     { "vpshld",         { XM, EXx, VexW }, 0 },
7538   },
7539
7540   /* VEX_LEN_XOP_09_97 */
7541   {
7542     { "vpshlq",         { XM, EXx, VexW }, 0 },
7543   },
7544
7545   /* VEX_LEN_XOP_09_98 */
7546   {
7547     { "vpshab",         { XM, EXx, VexW }, 0 },
7548   },
7549
7550   /* VEX_LEN_XOP_09_99 */
7551   {
7552     { "vpshaw",         { XM, EXx, VexW }, 0 },
7553   },
7554
7555   /* VEX_LEN_XOP_09_9A */
7556   {
7557     { "vpshad",         { XM, EXx, VexW }, 0 },
7558   },
7559
7560   /* VEX_LEN_XOP_09_9B */
7561   {
7562     { "vpshaq",         { XM, EXx, VexW }, 0 },
7563   },
7564
7565   /* VEX_LEN_XOP_09_C1 */
7566   {
7567     { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7568   },
7569
7570   /* VEX_LEN_XOP_09_C2 */
7571   {
7572     { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7573   },
7574
7575   /* VEX_LEN_XOP_09_C3 */
7576   {
7577     { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7578   },
7579
7580   /* VEX_LEN_XOP_09_C6 */
7581   {
7582     { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7583   },
7584
7585   /* VEX_LEN_XOP_09_C7 */
7586   {
7587     { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7588   },
7589
7590   /* VEX_LEN_XOP_09_CB */
7591   {
7592     { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7593   },
7594
7595   /* VEX_LEN_XOP_09_D1 */
7596   {
7597     { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7598   },
7599
7600   /* VEX_LEN_XOP_09_D2 */
7601   {
7602     { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7603   },
7604
7605   /* VEX_LEN_XOP_09_D3 */
7606   {
7607     { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7608   },
7609
7610   /* VEX_LEN_XOP_09_D6 */
7611   {
7612     { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7613   },
7614
7615   /* VEX_LEN_XOP_09_D7 */
7616   {
7617     { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7618   },
7619
7620   /* VEX_LEN_XOP_09_DB */
7621   {
7622     { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7623   },
7624
7625   /* VEX_LEN_XOP_09_E1 */
7626   {
7627     { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7628   },
7629
7630   /* VEX_LEN_XOP_09_E2 */
7631   {
7632     { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7633   },
7634
7635   /* VEX_LEN_XOP_09_E3 */
7636   {
7637     { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7638   },
7639
7640   /* VEX_LEN_XOP_0A_12 */
7641   {
7642     { REG_TABLE (REG_XOP_0A_12_L_0) },
7643   },
7644 };
7645
7646 #include "i386-dis-evex-len.h"
7647
7648 static const struct dis386 vex_w_table[][2] = {
7649   {
7650     /* VEX_W_0F41_L_1_M_1 */
7651     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7652     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7653   },
7654   {
7655     /* VEX_W_0F42_L_1_M_1 */
7656     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7657     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7658   },
7659   {
7660     /* VEX_W_0F44_L_0_M_1 */
7661     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7662     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7663   },
7664   {
7665     /* VEX_W_0F45_L_1_M_1 */
7666     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7667     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7668   },
7669   {
7670     /* VEX_W_0F46_L_1_M_1 */
7671     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7672     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7673   },
7674   {
7675     /* VEX_W_0F47_L_1_M_1 */
7676     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7677     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7678   },
7679   {
7680     /* VEX_W_0F4A_L_1_M_1 */
7681     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7682     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7683   },
7684   {
7685     /* VEX_W_0F4B_L_1_M_1 */
7686     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7687     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7688   },
7689   {
7690     /* VEX_W_0F90_L_0 */
7691     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7692     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7693   },
7694   {
7695     /* VEX_W_0F91_L_0_M_0 */
7696     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7697     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7698   },
7699   {
7700     /* VEX_W_0F92_L_0_M_1 */
7701     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7702     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7703   },
7704   {
7705     /* VEX_W_0F93_L_0_M_1 */
7706     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7707     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7708   },
7709   {
7710     /* VEX_W_0F98_L_0_M_1 */
7711     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7712     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7713   },
7714   {
7715     /* VEX_W_0F99_L_0_M_1 */
7716     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7717     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7718   },
7719   {
7720     /* VEX_W_0F380C  */
7721     { "%XEvpermilps",   { XM, Vex, EXx }, PREFIX_DATA },
7722   },
7723   {
7724     /* VEX_W_0F380D  */
7725     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7726   },
7727   {
7728     /* VEX_W_0F380E  */
7729     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7730   },
7731   {
7732     /* VEX_W_0F380F  */
7733     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7734   },
7735   {
7736     /* VEX_W_0F3813 */
7737     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7738   },
7739   {
7740     /* VEX_W_0F3816_L_1  */
7741     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7742   },
7743   {
7744     /* VEX_W_0F3818 */
7745     { "%XEvbroadcastss",        { XM, EXd }, PREFIX_DATA },
7746   },
7747   {
7748     /* VEX_W_0F3819_L_1 */
7749     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7750   },
7751   {
7752     /* VEX_W_0F381A_L_1 */
7753     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7754   },
7755   {
7756     /* VEX_W_0F382C */
7757     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7758   },
7759   {
7760     /* VEX_W_0F382D */
7761     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7762   },
7763   {
7764     /* VEX_W_0F382E */
7765     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7766   },
7767   {
7768     /* VEX_W_0F382F */
7769     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7770   },
7771   {
7772     /* VEX_W_0F3836  */
7773     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7774   },
7775   {
7776     /* VEX_W_0F3846 */
7777     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7778   },
7779   {
7780     /* VEX_W_0F3849_X86_64_L_0 */
7781     { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7782   },
7783   {
7784     /* VEX_W_0F384B_X86_64_L_0 */
7785     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
7786   },
7787   {
7788     /* VEX_W_0F3850 */
7789     { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7790   },
7791   {
7792     /* VEX_W_0F3851 */
7793     { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7794   },
7795   {
7796     /* VEX_W_0F3852 */
7797     { "%XVvpdpwssd",    { XM, Vex, EXx }, PREFIX_DATA },
7798   },
7799   {
7800     /* VEX_W_0F3853 */
7801     { "%XVvpdpwssds",   { XM, Vex, EXx }, PREFIX_DATA },
7802   },
7803   {
7804     /* VEX_W_0F3858 */
7805     { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7806   },
7807   {
7808     /* VEX_W_0F3859 */
7809     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7810   },
7811   {
7812     /* VEX_W_0F385A_L_0 */
7813     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7814   },
7815   {
7816     /* VEX_W_0F385C_X86_64_L_0 */
7817     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
7818   },
7819   {
7820     /* VEX_W_0F385E_X86_64_L_0 */
7821     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
7822   },
7823   {
7824     /* VEX_W_0F386C_X86_64_L_0 */
7825     { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
7826   },
7827   {
7828     /* VEX_W_0F3872_P_1 */
7829     { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7830   },
7831   {
7832     /* VEX_W_0F3878 */
7833     { "%XEvpbroadcastb",        { XM, EXb }, PREFIX_DATA },
7834   },
7835   {
7836     /* VEX_W_0F3879 */
7837     { "%XEvpbroadcastw",        { XM, EXw }, PREFIX_DATA },
7838   },
7839   {
7840     /* VEX_W_0F38B0 */
7841     { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7842   },
7843   {
7844     /* VEX_W_0F38B1 */
7845     { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7846   },
7847   {
7848     /* VEX_W_0F38B4 */
7849     { Bad_Opcode },
7850     { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7851   },
7852   {
7853     /* VEX_W_0F38B5 */
7854     { Bad_Opcode },
7855     { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7856   },
7857   {
7858     /* VEX_W_0F38CB_P_3 */
7859     { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
7860   },
7861   {
7862     /* VEX_W_0F38CC_P_3 */
7863     { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
7864   },
7865   {
7866     /* VEX_W_0F38CD_P_3 */
7867     { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
7868   },
7869   {
7870     /* VEX_W_0F38CF */
7871     { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7872   },
7873   {
7874     /* VEX_W_0F38D2 */
7875     { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
7876   },
7877   {
7878     /* VEX_W_0F38D3 */
7879     { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
7880   },
7881   {
7882     /* VEX_W_0F38DA */
7883     { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
7884   },
7885   {
7886     /* VEX_W_0F3A00_L_1 */
7887     { Bad_Opcode },
7888     { "%XEvpermq",              { XM, EXx, Ib }, PREFIX_DATA },
7889   },
7890   {
7891     /* VEX_W_0F3A01_L_1 */
7892     { Bad_Opcode },
7893     { "%XEvpermpd",     { XM, EXx, Ib }, PREFIX_DATA },
7894   },
7895   {
7896     /* VEX_W_0F3A02 */
7897     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7898   },
7899   {
7900     /* VEX_W_0F3A04 */
7901     { "%XEvpermilps",   { XM, EXx, Ib }, PREFIX_DATA },
7902   },
7903   {
7904     /* VEX_W_0F3A05 */
7905     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7906   },
7907   {
7908     /* VEX_W_0F3A06_L_1 */
7909     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7910   },
7911   {
7912     /* VEX_W_0F3A18_L_1 */
7913     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7914   },
7915   {
7916     /* VEX_W_0F3A19_L_1 */
7917     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7918   },
7919   {
7920     /* VEX_W_0F3A1D */
7921     { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7922   },
7923   {
7924     /* VEX_W_0F3A38_L_1 */
7925     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7926   },
7927   {
7928     /* VEX_W_0F3A39_L_1 */
7929     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7930   },
7931   {
7932     /* VEX_W_0F3A46_L_1 */
7933     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7934   },
7935   {
7936     /* VEX_W_0F3A4A */
7937     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7938   },
7939   {
7940     /* VEX_W_0F3A4B */
7941     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7942   },
7943   {
7944     /* VEX_W_0F3A4C */
7945     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7946   },
7947   {
7948     /* VEX_W_0F3ACE */
7949     { Bad_Opcode },
7950     { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7951   },
7952   {
7953     /* VEX_W_0F3ACF */
7954     { Bad_Opcode },
7955     { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7956   },
7957   {
7958     /* VEX_W_0F3ADE */
7959     { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
7960   },
7961   {
7962     /* VEX_W_MAP7_F8_L_0 */
7963     { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
7964   },
7965   /* VEX_W_XOP_08_85_L_0 */
7966   {
7967     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7968   },
7969   /* VEX_W_XOP_08_86_L_0 */
7970   {
7971     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7972   },
7973   /* VEX_W_XOP_08_87_L_0 */
7974   {
7975     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7976   },
7977   /* VEX_W_XOP_08_8E_L_0 */
7978   {
7979     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7980   },
7981   /* VEX_W_XOP_08_8F_L_0 */
7982   {
7983     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7984   },
7985   /* VEX_W_XOP_08_95_L_0 */
7986   {
7987     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7988   },
7989   /* VEX_W_XOP_08_96_L_0 */
7990   {
7991     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7992   },
7993   /* VEX_W_XOP_08_97_L_0 */
7994   {
7995     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7996   },
7997   /* VEX_W_XOP_08_9E_L_0 */
7998   {
7999     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
8000   },
8001   /* VEX_W_XOP_08_9F_L_0 */
8002   {
8003     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
8004   },
8005   /* VEX_W_XOP_08_A6_L_0 */
8006   {
8007     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
8008   },
8009   /* VEX_W_XOP_08_B6_L_0 */
8010   {
8011     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
8012   },
8013   /* VEX_W_XOP_08_C0_L_0 */
8014   {
8015     { "vprotb",         { XM, EXx, Ib }, 0 },
8016   },
8017   /* VEX_W_XOP_08_C1_L_0 */
8018   {
8019     { "vprotw",         { XM, EXx, Ib }, 0 },
8020   },
8021   /* VEX_W_XOP_08_C2_L_0 */
8022   {
8023     { "vprotd",         { XM, EXx, Ib }, 0 },
8024   },
8025   /* VEX_W_XOP_08_C3_L_0 */
8026   {
8027     { "vprotq",         { XM, EXx, Ib }, 0 },
8028   },
8029   /* VEX_W_XOP_08_CC_L_0 */
8030   {
8031      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
8032   },
8033   /* VEX_W_XOP_08_CD_L_0 */
8034   {
8035      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
8036   },
8037   /* VEX_W_XOP_08_CE_L_0 */
8038   {
8039      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
8040   },
8041   /* VEX_W_XOP_08_CF_L_0 */
8042   {
8043      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
8044   },
8045   /* VEX_W_XOP_08_EC_L_0 */
8046   {
8047      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
8048   },
8049   /* VEX_W_XOP_08_ED_L_0 */
8050   {
8051      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
8052   },
8053   /* VEX_W_XOP_08_EE_L_0 */
8054   {
8055      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
8056   },
8057   /* VEX_W_XOP_08_EF_L_0 */
8058   {
8059      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
8060   },
8061   /* VEX_W_XOP_09_80 */
8062   {
8063     { "vfrczps",        { XM, EXx }, 0 },
8064   },
8065   /* VEX_W_XOP_09_81 */
8066   {
8067     { "vfrczpd",        { XM, EXx }, 0 },
8068   },
8069   /* VEX_W_XOP_09_82 */
8070   {
8071     { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
8072   },
8073   /* VEX_W_XOP_09_83 */
8074   {
8075     { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
8076   },
8077   /* VEX_W_XOP_09_C1_L_0 */
8078   {
8079     { "vphaddbw",       { XM, EXxmm }, 0 },
8080   },
8081   /* VEX_W_XOP_09_C2_L_0 */
8082   {
8083     { "vphaddbd",       { XM, EXxmm }, 0 },
8084   },
8085   /* VEX_W_XOP_09_C3_L_0 */
8086   {
8087     { "vphaddbq",       { XM, EXxmm }, 0 },
8088   },
8089   /* VEX_W_XOP_09_C6_L_0 */
8090   {
8091     { "vphaddwd",       { XM, EXxmm }, 0 },
8092   },
8093   /* VEX_W_XOP_09_C7_L_0 */
8094   {
8095     { "vphaddwq",       { XM, EXxmm }, 0 },
8096   },
8097   /* VEX_W_XOP_09_CB_L_0 */
8098   {
8099     { "vphadddq",       { XM, EXxmm }, 0 },
8100   },
8101   /* VEX_W_XOP_09_D1_L_0 */
8102   {
8103     { "vphaddubw",      { XM, EXxmm }, 0 },
8104   },
8105   /* VEX_W_XOP_09_D2_L_0 */
8106   {
8107     { "vphaddubd",      { XM, EXxmm }, 0 },
8108   },
8109   /* VEX_W_XOP_09_D3_L_0 */
8110   {
8111     { "vphaddubq",      { XM, EXxmm }, 0 },
8112   },
8113   /* VEX_W_XOP_09_D6_L_0 */
8114   {
8115     { "vphadduwd",      { XM, EXxmm }, 0 },
8116   },
8117   /* VEX_W_XOP_09_D7_L_0 */
8118   {
8119     { "vphadduwq",      { XM, EXxmm }, 0 },
8120   },
8121   /* VEX_W_XOP_09_DB_L_0 */
8122   {
8123     { "vphaddudq",      { XM, EXxmm }, 0 },
8124   },
8125   /* VEX_W_XOP_09_E1_L_0 */
8126   {
8127     { "vphsubbw",       { XM, EXxmm }, 0 },
8128   },
8129   /* VEX_W_XOP_09_E2_L_0 */
8130   {
8131     { "vphsubwd",       { XM, EXxmm }, 0 },
8132   },
8133   /* VEX_W_XOP_09_E3_L_0 */
8134   {
8135     { "vphsubdq",       { XM, EXxmm }, 0 },
8136   },
8137
8138 #include "i386-dis-evex-w.h"
8139 };
8140
8141 static const struct dis386 mod_table[][2] = {
8142   {
8143     /* MOD_62_32BIT */
8144     { "bound{S|}",      { Gv, Ma }, 0 },
8145     { EVEX_TABLE () },
8146   },
8147   {
8148     /* MOD_C4_32BIT */
8149     { "lesS",           { Gv, Mp }, 0 },
8150     { VEX_C4_TABLE () },
8151   },
8152   {
8153     /* MOD_C5_32BIT */
8154     { "ldsS",           { Gv, Mp }, 0 },
8155     { VEX_C5_TABLE () },
8156   },
8157   {
8158     /* MOD_0F01_REG_0 */
8159     { X86_64_TABLE (X86_64_0F01_REG_0) },
8160     { RM_TABLE (RM_0F01_REG_0) },
8161   },
8162   {
8163     /* MOD_0F01_REG_1 */
8164     { X86_64_TABLE (X86_64_0F01_REG_1) },
8165     { RM_TABLE (RM_0F01_REG_1) },
8166   },
8167   {
8168     /* MOD_0F01_REG_2 */
8169     { X86_64_TABLE (X86_64_0F01_REG_2) },
8170     { RM_TABLE (RM_0F01_REG_2) },
8171   },
8172   {
8173     /* MOD_0F01_REG_3 */
8174     { X86_64_TABLE (X86_64_0F01_REG_3) },
8175     { RM_TABLE (RM_0F01_REG_3) },
8176   },
8177   {
8178     /* MOD_0F01_REG_5 */
8179     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8180     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8181   },
8182   {
8183     /* MOD_0F01_REG_7 */
8184     { "invlpg",         { Mb }, 0 },
8185     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8186   },
8187   {
8188     /* MOD_0F12_PREFIX_0 */
8189     { "%XEVmovlpYX",    { XM, Vex, EXq }, 0 },
8190     { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8191   },
8192   {
8193     /* MOD_0F16_PREFIX_0 */
8194     { "%XEVmovhpYX",    { XM, Vex, EXq }, 0 },
8195     { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8196   },
8197   {
8198     /* MOD_0F18_REG_0 */
8199     { "prefetchnta",    { Mb }, 0 },
8200     { "nopQ",           { Ev }, 0 },
8201   },
8202   {
8203     /* MOD_0F18_REG_1 */
8204     { "prefetcht0",     { Mb }, 0 },
8205     { "nopQ",           { Ev }, 0 },
8206   },
8207   {
8208     /* MOD_0F18_REG_2 */
8209     { "prefetcht1",     { Mb }, 0 },
8210     { "nopQ",           { Ev }, 0 },
8211   },
8212   {
8213     /* MOD_0F18_REG_3 */
8214     { "prefetcht2",     { Mb }, 0 },
8215     { "nopQ",           { Ev }, 0 },
8216   },
8217   {
8218     /* MOD_0F18_REG_6 */
8219     { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8220     { "nopQ",           { Ev }, 0 },
8221   },
8222   {
8223     /* MOD_0F18_REG_7 */
8224     { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8225     { "nopQ",           { Ev }, 0 },
8226   },
8227   {
8228     /* MOD_0F1A_PREFIX_0 */
8229     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8230     { "nopQ",           { Ev }, 0 },
8231   },
8232   {
8233     /* MOD_0F1B_PREFIX_0 */
8234     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8235     { "nopQ",           { Ev }, 0 },
8236   },
8237   {
8238     /* MOD_0F1B_PREFIX_1 */
8239     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8240     { "nopQ",           { Ev }, PREFIX_IGNORED },
8241   },
8242   {
8243     /* MOD_0F1C_PREFIX_0 */
8244     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8245     { "nopQ",           { Ev }, 0 },
8246   },
8247   {
8248     /* MOD_0F1E_PREFIX_1 */
8249     { "nopQ",           { Ev }, PREFIX_IGNORED },
8250     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8251   },
8252   {
8253     /* MOD_0FAE_REG_0 */
8254     { "fxsave",         { FXSAVE }, 0 },
8255     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8256   },
8257   {
8258     /* MOD_0FAE_REG_1 */
8259     { "fxrstor",        { FXSAVE }, 0 },
8260     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8261   },
8262   {
8263     /* MOD_0FAE_REG_2 */
8264     { "ldmxcsr",        { Md }, 0 },
8265     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8266   },
8267   {
8268     /* MOD_0FAE_REG_3 */
8269     { "stmxcsr",        { Md }, 0 },
8270     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8271   },
8272   {
8273     /* MOD_0FAE_REG_4 */
8274     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8275     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8276   },
8277   {
8278     /* MOD_0FAE_REG_5 */
8279     { "xrstor",         { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8280     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8281   },
8282   {
8283     /* MOD_0FAE_REG_6 */
8284     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8285     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8286   },
8287   {
8288     /* MOD_0FAE_REG_7 */
8289     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8290     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8291   },
8292   {
8293     /* MOD_0FC7_REG_6 */
8294     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8295     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8296   },
8297   {
8298     /* MOD_0FC7_REG_7 */
8299     { "vmptrst",        { Mq }, 0 },
8300     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8301   },
8302   {
8303     /* MOD_0F38DC_PREFIX_1 */
8304     { "aesenc128kl",    { XM, M }, 0 },
8305     { "loadiwkey",      { XM, EXx }, 0 },
8306   },
8307   /* MOD_0F38F8 */
8308   {
8309     { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8310     { X86_64_TABLE (X86_64_0F38F8_M_1) },
8311   },
8312   {
8313     /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8314     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8315     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8316   },
8317
8318 #include "i386-dis-evex-mod.h"
8319 };
8320
8321 static const struct dis386 rm_table[][8] = {
8322   {
8323     /* RM_C6_REG_7 */
8324     { "xabort",         { Skip_MODRM, Ib }, 0 },
8325   },
8326   {
8327     /* RM_C7_REG_7 */
8328     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8329   },
8330   {
8331     /* RM_0F01_REG_0 */
8332     { "enclv",          { Skip_MODRM }, 0 },
8333     { "vmcall",         { Skip_MODRM }, 0 },
8334     { "vmlaunch",       { Skip_MODRM }, 0 },
8335     { "vmresume",       { Skip_MODRM }, 0 },
8336     { "vmxoff",         { Skip_MODRM }, 0 },
8337     { "pconfig",        { Skip_MODRM }, 0 },
8338     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8339     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8340   },
8341   {
8342     /* RM_0F01_REG_1 */
8343     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8344     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8345     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8346     { "stac",           { Skip_MODRM }, 0 },
8347     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8348     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8349     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8350     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8351   },
8352   {
8353     /* RM_0F01_REG_2 */
8354     { "xgetbv",         { Skip_MODRM }, 0 },
8355     { "xsetbv",         { Skip_MODRM }, 0 },
8356     { Bad_Opcode },
8357     { Bad_Opcode },
8358     { "vmfunc",         { Skip_MODRM }, 0 },
8359     { "xend",           { Skip_MODRM }, 0 },
8360     { "xtest",          { Skip_MODRM }, 0 },
8361     { "enclu",          { Skip_MODRM }, 0 },
8362   },
8363   {
8364     /* RM_0F01_REG_3 */
8365     { "vmrun",          { Skip_MODRM }, 0 },
8366     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8367     { "vmload",         { Skip_MODRM }, 0 },
8368     { "vmsave",         { Skip_MODRM }, 0 },
8369     { "stgi",           { Skip_MODRM }, 0 },
8370     { "clgi",           { Skip_MODRM }, 0 },
8371     { "skinit",         { Skip_MODRM }, 0 },
8372     { "invlpga",        { Skip_MODRM }, 0 },
8373   },
8374   {
8375     /* RM_0F01_REG_5_MOD_3 */
8376     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8377     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8378     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8379     { Bad_Opcode },
8380     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8381     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8382     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8383     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8384   },
8385   {
8386     /* RM_0F01_REG_7_MOD_3 */
8387     { "swapgs",         { Skip_MODRM }, 0  },
8388     { "rdtscp",         { Skip_MODRM }, 0  },
8389     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8390     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8391     { "clzero",         { Skip_MODRM }, 0  },
8392     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8393     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8394     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8395   },
8396   {
8397     /* RM_0F1E_P_1_MOD_3_REG_7 */
8398     { "nopQ",           { Ev }, PREFIX_IGNORED },
8399     { "nopQ",           { Ev }, PREFIX_IGNORED },
8400     { "endbr64",        { Skip_MODRM }, 0 },
8401     { "endbr32",        { Skip_MODRM }, 0 },
8402     { "nopQ",           { Ev }, PREFIX_IGNORED },
8403     { "nopQ",           { Ev }, PREFIX_IGNORED },
8404     { "nopQ",           { Ev }, PREFIX_IGNORED },
8405     { "nopQ",           { Ev }, PREFIX_IGNORED },
8406   },
8407   {
8408     /* RM_0FAE_REG_6_MOD_3 */
8409     { "mfence",         { Skip_MODRM }, 0 },
8410   },
8411   {
8412     /* RM_0FAE_REG_7_MOD_3 */
8413     { "sfence",         { Skip_MODRM }, 0 },
8414   },
8415   {
8416     /* RM_0F3A0F_P_1_R_0 */
8417     { "hreset",         { Skip_MODRM, Ib }, 0 },
8418   },
8419   {
8420     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8421     { "tilerelease",    { Skip_MODRM }, 0 },
8422   },
8423   {
8424     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8425     { "tilezero",       { TMM, Skip_MODRM }, 0 },
8426   },
8427 };
8428
8429 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8430
8431 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8432    in conflict with actual prefix opcodes.  */
8433 #define REP_PREFIX      0x01
8434 #define XACQUIRE_PREFIX 0x02
8435 #define XRELEASE_PREFIX 0x03
8436 #define BND_PREFIX      0x04
8437 #define NOTRACK_PREFIX  0x05
8438
8439 static enum {
8440   ckp_okay,
8441   ckp_bogus,
8442   ckp_fetch_error,
8443 }
8444 ckprefix (instr_info *ins)
8445 {
8446   int i, length;
8447   uint8_t newrex;
8448
8449   i = 0;
8450   length = 0;
8451   /* The maximum instruction length is 15bytes.  */
8452   while (length < MAX_CODE_LENGTH - 1)
8453     {
8454       if (!fetch_code (ins->info, ins->codep + 1))
8455         return ckp_fetch_error;
8456       newrex = 0;
8457       switch (*ins->codep)
8458         {
8459         /* REX prefixes family.  */
8460         case 0x40:
8461         case 0x41:
8462         case 0x42:
8463         case 0x43:
8464         case 0x44:
8465         case 0x45:
8466         case 0x46:
8467         case 0x47:
8468         case 0x48:
8469         case 0x49:
8470         case 0x4a:
8471         case 0x4b:
8472         case 0x4c:
8473         case 0x4d:
8474         case 0x4e:
8475         case 0x4f:
8476           if (ins->address_mode == mode_64bit)
8477             newrex = *ins->codep;
8478           else
8479             return ckp_okay;
8480           ins->last_rex_prefix = i;
8481           break;
8482         /* REX2 must be the last prefix. */
8483         case REX2_OPCODE:
8484           if (ins->address_mode == mode_64bit)
8485             {
8486               if (ins->last_rex_prefix >= 0)
8487                 return ckp_bogus;
8488
8489               ins->codep++;
8490               if (!fetch_code (ins->info, ins->codep + 1))
8491                 return ckp_fetch_error;
8492               ins->rex2_payload = *ins->codep;
8493               ins->rex2 = ins->rex2_payload >> 4;
8494               ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8495               ins->codep++;
8496               ins->last_rex2_prefix = i;
8497               ins->all_prefixes[i] = REX2_OPCODE;
8498             }
8499           return ckp_okay;
8500         case 0xf3:
8501           ins->prefixes |= PREFIX_REPZ;
8502           ins->last_repz_prefix = i;
8503           break;
8504         case 0xf2:
8505           ins->prefixes |= PREFIX_REPNZ;
8506           ins->last_repnz_prefix = i;
8507           break;
8508         case 0xf0:
8509           ins->prefixes |= PREFIX_LOCK;
8510           ins->last_lock_prefix = i;
8511           break;
8512         case 0x2e:
8513           ins->prefixes |= PREFIX_CS;
8514           ins->last_seg_prefix = i;
8515           if (ins->address_mode != mode_64bit)
8516             ins->active_seg_prefix = PREFIX_CS;
8517           break;
8518         case 0x36:
8519           ins->prefixes |= PREFIX_SS;
8520           ins->last_seg_prefix = i;
8521           if (ins->address_mode != mode_64bit)
8522             ins->active_seg_prefix = PREFIX_SS;
8523           break;
8524         case 0x3e:
8525           ins->prefixes |= PREFIX_DS;
8526           ins->last_seg_prefix = i;
8527           if (ins->address_mode != mode_64bit)
8528             ins->active_seg_prefix = PREFIX_DS;
8529           break;
8530         case 0x26:
8531           ins->prefixes |= PREFIX_ES;
8532           ins->last_seg_prefix = i;
8533           if (ins->address_mode != mode_64bit)
8534             ins->active_seg_prefix = PREFIX_ES;
8535           break;
8536         case 0x64:
8537           ins->prefixes |= PREFIX_FS;
8538           ins->last_seg_prefix = i;
8539           ins->active_seg_prefix = PREFIX_FS;
8540           break;
8541         case 0x65:
8542           ins->prefixes |= PREFIX_GS;
8543           ins->last_seg_prefix = i;
8544           ins->active_seg_prefix = PREFIX_GS;
8545           break;
8546         case 0x66:
8547           ins->prefixes |= PREFIX_DATA;
8548           ins->last_data_prefix = i;
8549           break;
8550         case 0x67:
8551           ins->prefixes |= PREFIX_ADDR;
8552           ins->last_addr_prefix = i;
8553           break;
8554         case FWAIT_OPCODE:
8555           /* fwait is really an instruction.  If there are prefixes
8556              before the fwait, they belong to the fwait, *not* to the
8557              following instruction.  */
8558           ins->fwait_prefix = i;
8559           if (ins->prefixes || ins->rex)
8560             {
8561               ins->prefixes |= PREFIX_FWAIT;
8562               ins->codep++;
8563               /* This ensures that the previous REX prefixes are noticed
8564                  as unused prefixes, as in the return case below.  */
8565               return ins->rex ? ckp_bogus : ckp_okay;
8566             }
8567           ins->prefixes = PREFIX_FWAIT;
8568           break;
8569         default:
8570           return ckp_okay;
8571         }
8572       /* Rex is ignored when followed by another prefix.  */
8573       if (ins->rex)
8574         return ckp_bogus;
8575       if (*ins->codep != FWAIT_OPCODE)
8576         ins->all_prefixes[i++] = *ins->codep;
8577       ins->rex = newrex;
8578       ins->codep++;
8579       length++;
8580     }
8581   return ckp_bogus;
8582 }
8583
8584 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8585    prefix byte.  */
8586
8587 static const char *
8588 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8589 {
8590   static const char *rexes [16] =
8591     {
8592       "rex",            /* 0x40 */
8593       "rex.B",          /* 0x41 */
8594       "rex.X",          /* 0x42 */
8595       "rex.XB",         /* 0x43 */
8596       "rex.R",          /* 0x44 */
8597       "rex.RB",         /* 0x45 */
8598       "rex.RX",         /* 0x46 */
8599       "rex.RXB",        /* 0x47 */
8600       "rex.W",          /* 0x48 */
8601       "rex.WB",         /* 0x49 */
8602       "rex.WX",         /* 0x4a */
8603       "rex.WXB",        /* 0x4b */
8604       "rex.WR",         /* 0x4c */
8605       "rex.WRB",        /* 0x4d */
8606       "rex.WRX",        /* 0x4e */
8607       "rex.WRXB",       /* 0x4f */
8608     };
8609
8610   switch (pref)
8611     {
8612     /* REX prefixes family.  */
8613     case 0x40:
8614     case 0x41:
8615     case 0x42:
8616     case 0x43:
8617     case 0x44:
8618     case 0x45:
8619     case 0x46:
8620     case 0x47:
8621     case 0x48:
8622     case 0x49:
8623     case 0x4a:
8624     case 0x4b:
8625     case 0x4c:
8626     case 0x4d:
8627     case 0x4e:
8628     case 0x4f:
8629       return rexes [pref - 0x40];
8630     case 0xf3:
8631       return "repz";
8632     case 0xf2:
8633       return "repnz";
8634     case 0xf0:
8635       return "lock";
8636     case 0x2e:
8637       return "cs";
8638     case 0x36:
8639       return "ss";
8640     case 0x3e:
8641       return "ds";
8642     case 0x26:
8643       return "es";
8644     case 0x64:
8645       return "fs";
8646     case 0x65:
8647       return "gs";
8648     case 0x66:
8649       return (sizeflag & DFLAG) ? "data16" : "data32";
8650     case 0x67:
8651       if (mode == mode_64bit)
8652         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8653       else
8654         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8655     case FWAIT_OPCODE:
8656       return "fwait";
8657     case REP_PREFIX:
8658       return "rep";
8659     case XACQUIRE_PREFIX:
8660       return "xacquire";
8661     case XRELEASE_PREFIX:
8662       return "xrelease";
8663     case BND_PREFIX:
8664       return "bnd";
8665     case NOTRACK_PREFIX:
8666       return "notrack";
8667     case REX2_OPCODE:
8668       return "rex2";
8669     default:
8670       return NULL;
8671     }
8672 }
8673
8674 void
8675 print_i386_disassembler_options (FILE *stream)
8676 {
8677   fprintf (stream, _("\n\
8678 The following i386/x86-64 specific disassembler options are supported for use\n\
8679 with the -M switch (multiple options should be separated by commas):\n"));
8680
8681   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8682   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8683   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8684   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8685   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8686   fprintf (stream, _("  att-mnemonic  (AT&T syntax only)\n"
8687                      "              Display instruction with AT&T mnemonic\n"));
8688   fprintf (stream, _("  intel-mnemonic  (AT&T syntax only)\n"
8689                      "              Display instruction with Intel mnemonic\n"));
8690   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8691   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8692   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8693   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8694   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8695   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8696   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8697   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8698 }
8699
8700 /* Bad opcode.  */
8701 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8702
8703 /* Fetch error indicator.  */
8704 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
8705
8706 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
8707
8708 /* Get a pointer to struct dis386 with a valid name.  */
8709
8710 static const struct dis386 *
8711 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8712 {
8713   int vindex, vex_table_index;
8714
8715   if (dp->name != NULL)
8716     return dp;
8717
8718   switch (dp->op[0].bytemode)
8719     {
8720     case USE_REG_TABLE:
8721       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8722       break;
8723
8724     case USE_MOD_TABLE:
8725       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8726       dp = &mod_table[dp->op[1].bytemode][vindex];
8727       break;
8728
8729     case USE_RM_TABLE:
8730       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8731       break;
8732
8733     case USE_PREFIX_TABLE:
8734     use_prefix_table:
8735       if (ins->need_vex)
8736         {
8737           /* The prefix in VEX is implicit.  */
8738           switch (ins->vex.prefix)
8739             {
8740             case 0:
8741               vindex = 0;
8742               break;
8743             case REPE_PREFIX_OPCODE:
8744               vindex = 1;
8745               break;
8746             case DATA_PREFIX_OPCODE:
8747               vindex = 2;
8748               break;
8749             case REPNE_PREFIX_OPCODE:
8750               vindex = 3;
8751               break;
8752             default:
8753               abort ();
8754               break;
8755             }
8756         }
8757       else
8758         {
8759           int last_prefix = -1;
8760           int prefix = 0;
8761           vindex = 0;
8762           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8763              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8764              last one wins.  */
8765           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8766             {
8767               if (ins->last_repz_prefix > ins->last_repnz_prefix)
8768                 {
8769                   vindex = 1;
8770                   prefix = PREFIX_REPZ;
8771                   last_prefix = ins->last_repz_prefix;
8772                 }
8773               else
8774                 {
8775                   vindex = 3;
8776                   prefix = PREFIX_REPNZ;
8777                   last_prefix = ins->last_repnz_prefix;
8778                 }
8779
8780               /* Check if prefix should be ignored.  */
8781               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8782                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8783                    & prefix) != 0
8784                   && !prefix_table[dp->op[1].bytemode][vindex].name)
8785                 vindex = 0;
8786             }
8787
8788           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8789             {
8790               vindex = 2;
8791               prefix = PREFIX_DATA;
8792               last_prefix = ins->last_data_prefix;
8793             }
8794
8795           if (vindex != 0)
8796             {
8797               ins->used_prefixes |= prefix;
8798               ins->all_prefixes[last_prefix] = 0;
8799             }
8800         }
8801       dp = &prefix_table[dp->op[1].bytemode][vindex];
8802       break;
8803
8804     case USE_X86_64_EVEX_FROM_VEX_TABLE:
8805     case USE_X86_64_EVEX_PFX_TABLE:
8806     case USE_X86_64_EVEX_W_TABLE:
8807     case USE_X86_64_EVEX_MEM_W_TABLE:
8808       ins->evex_type = evex_from_vex;
8809       /* EVEX from VEX instructions are 64-bit only and require that EVEX.z,
8810          EVEX.L'L, EVEX.b, and the lower 2 bits of EVEX.aaa must be 0.  */
8811       if (ins->address_mode != mode_64bit
8812           || (ins->vex.mask_register_specifier & 0x3) != 0
8813           || ins->vex.ll != 0
8814           || ins->vex.zeroing != 0
8815           || ins->vex.b)
8816         return &bad_opcode;
8817
8818       if (dp->op[0].bytemode == USE_X86_64_EVEX_PFX_TABLE)
8819         goto use_prefix_table;
8820       if (dp->op[0].bytemode == USE_X86_64_EVEX_W_TABLE)
8821         goto use_vex_w_table;
8822       if (dp->op[0].bytemode == USE_X86_64_EVEX_MEM_W_TABLE)
8823         {
8824           if (ins->modrm.mod == 3)
8825             return &bad_opcode;
8826           goto use_vex_w_table;
8827         }
8828
8829       /* Fall through.  */
8830     case USE_X86_64_TABLE:
8831       vindex = ins->address_mode == mode_64bit ? 1 : 0;
8832       dp = &x86_64_table[dp->op[1].bytemode][vindex];
8833       break;
8834
8835     case USE_3BYTE_TABLE:
8836       if (ins->last_rex2_prefix >= 0)
8837         return &err_opcode;
8838       if (!fetch_code (ins->info, ins->codep + 2))
8839         return &err_opcode;
8840       vindex = *ins->codep++;
8841       dp = &three_byte_table[dp->op[1].bytemode][vindex];
8842       ins->end_codep = ins->codep;
8843       if (!fetch_modrm (ins))
8844         return &err_opcode;
8845       break;
8846
8847     case USE_VEX_LEN_TABLE:
8848       if (!ins->need_vex)
8849         abort ();
8850
8851       switch (ins->vex.length)
8852         {
8853         case 128:
8854           vindex = 0;
8855           break;
8856         case 512:
8857           /* This allows re-using in particular table entries where only
8858              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
8859           if (ins->vex.evex)
8860             {
8861         case 256:
8862               vindex = 1;
8863               break;
8864             }
8865         /* Fall through.  */
8866         default:
8867           abort ();
8868           break;
8869         }
8870
8871       dp = &vex_len_table[dp->op[1].bytemode][vindex];
8872       break;
8873
8874     case USE_EVEX_LEN_TABLE:
8875       if (!ins->vex.evex)
8876         abort ();
8877
8878       switch (ins->vex.length)
8879         {
8880         case 128:
8881           vindex = 0;
8882           break;
8883         case 256:
8884           vindex = 1;
8885           break;
8886         case 512:
8887           vindex = 2;
8888           break;
8889         default:
8890           abort ();
8891           break;
8892         }
8893
8894       dp = &evex_len_table[dp->op[1].bytemode][vindex];
8895       break;
8896
8897     case USE_XOP_8F_TABLE:
8898       if (!fetch_code (ins->info, ins->codep + 3))
8899         return &err_opcode;
8900       ins->rex = ~(*ins->codep >> 5) & 0x7;
8901
8902       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
8903       switch ((*ins->codep & 0x1f))
8904         {
8905         default:
8906           dp = &bad_opcode;
8907           return dp;
8908         case 0x8:
8909           vex_table_index = XOP_08;
8910           break;
8911         case 0x9:
8912           vex_table_index = XOP_09;
8913           break;
8914         case 0xa:
8915           vex_table_index = XOP_0A;
8916           break;
8917         }
8918       ins->codep++;
8919       ins->vex.w = *ins->codep & 0x80;
8920       if (ins->vex.w && ins->address_mode == mode_64bit)
8921         ins->rex |= REX_W;
8922
8923       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8924       if (ins->address_mode != mode_64bit)
8925         {
8926           /* In 16/32-bit mode REX_B is silently ignored.  */
8927           ins->rex &= ~REX_B;
8928         }
8929
8930       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8931       switch ((*ins->codep & 0x3))
8932         {
8933         case 0:
8934           break;
8935         case 1:
8936           ins->vex.prefix = DATA_PREFIX_OPCODE;
8937           break;
8938         case 2:
8939           ins->vex.prefix = REPE_PREFIX_OPCODE;
8940           break;
8941         case 3:
8942           ins->vex.prefix = REPNE_PREFIX_OPCODE;
8943           break;
8944         }
8945       ins->need_vex = 3;
8946       ins->codep++;
8947       vindex = *ins->codep++;
8948       dp = &xop_table[vex_table_index][vindex];
8949
8950       ins->end_codep = ins->codep;
8951       if (!fetch_modrm (ins))
8952         return &err_opcode;
8953
8954       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
8955          having to decode the bits for every otherwise valid encoding.  */
8956       if (ins->vex.prefix)
8957         return &bad_opcode;
8958       break;
8959
8960     case USE_VEX_C4_TABLE:
8961       /* VEX prefix.  */
8962       if (!fetch_code (ins->info, ins->codep + 3))
8963         return &err_opcode;
8964       ins->rex = ~(*ins->codep >> 5) & 0x7;
8965       switch ((*ins->codep & 0x1f))
8966         {
8967         default:
8968           dp = &bad_opcode;
8969           return dp;
8970         case 0x1:
8971           vex_table_index = VEX_0F;
8972           break;
8973         case 0x2:
8974           vex_table_index = VEX_0F38;
8975           break;
8976         case 0x3:
8977           vex_table_index = VEX_0F3A;
8978           break;
8979         case 0x7:
8980           vex_table_index = VEX_MAP7;
8981           break;
8982         }
8983       ins->codep++;
8984       ins->vex.w = *ins->codep & 0x80;
8985       if (ins->address_mode == mode_64bit)
8986         {
8987           if (ins->vex.w)
8988             ins->rex |= REX_W;
8989         }
8990       else
8991         {
8992           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
8993              is ignored, other REX bits are 0 and the highest bit in
8994              VEX.vvvv is also ignored (but we mustn't clear it here).  */
8995           ins->rex = 0;
8996         }
8997       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8998       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8999       switch ((*ins->codep & 0x3))
9000         {
9001         case 0:
9002           break;
9003         case 1:
9004           ins->vex.prefix = DATA_PREFIX_OPCODE;
9005           break;
9006         case 2:
9007           ins->vex.prefix = REPE_PREFIX_OPCODE;
9008           break;
9009         case 3:
9010           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9011           break;
9012         }
9013       ins->need_vex = 3;
9014       ins->codep++;
9015       vindex = *ins->codep++;
9016       if (vex_table_index != VEX_MAP7)
9017         dp = &vex_table[vex_table_index][vindex];
9018       else if (vindex == 0xf8)
9019         dp = &map7_f8_opcode;
9020       else
9021         dp = &bad_opcode;
9022       ins->end_codep = ins->codep;
9023       /* There is no MODRM byte for VEX0F 77.  */
9024       if ((vex_table_index != VEX_0F || vindex != 0x77)
9025           && !fetch_modrm (ins))
9026         return &err_opcode;
9027       break;
9028
9029     case USE_VEX_C5_TABLE:
9030       /* VEX prefix.  */
9031       if (!fetch_code (ins->info, ins->codep + 2))
9032         return &err_opcode;
9033       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9034
9035       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9036          VEX.vvvv is 1.  */
9037       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9038       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9039       switch ((*ins->codep & 0x3))
9040         {
9041         case 0:
9042           break;
9043         case 1:
9044           ins->vex.prefix = DATA_PREFIX_OPCODE;
9045           break;
9046         case 2:
9047           ins->vex.prefix = REPE_PREFIX_OPCODE;
9048           break;
9049         case 3:
9050           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9051           break;
9052         }
9053       ins->need_vex = 2;
9054       ins->codep++;
9055       vindex = *ins->codep++;
9056       dp = &vex_table[VEX_0F][vindex];
9057       ins->end_codep = ins->codep;
9058       /* There is no MODRM byte for VEX 77.  */
9059       if (vindex != 0x77 && !fetch_modrm (ins))
9060         return &err_opcode;
9061       break;
9062
9063     case USE_VEX_W_TABLE:
9064     use_vex_w_table:
9065       if (!ins->need_vex)
9066         abort ();
9067
9068       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9069       break;
9070
9071     case USE_EVEX_TABLE:
9072       ins->two_source_ops = false;
9073       /* EVEX prefix.  */
9074       ins->vex.evex = true;
9075       if (!fetch_code (ins->info, ins->codep + 4))
9076         return &err_opcode;
9077       /* The first byte after 0x62.  */
9078       if (*ins->codep & 0x8)
9079         ins->rex2 |= REX_B;
9080       if (!(*ins->codep & 0x10))
9081         ins->rex2 |= REX_R;
9082
9083       ins->rex = ~(*ins->codep >> 5) & 0x7;
9084       switch (*ins->codep & 0x7)
9085         {
9086         default:
9087           return &bad_opcode;
9088         case 0x1:
9089           vex_table_index = EVEX_0F;
9090           break;
9091         case 0x2:
9092           vex_table_index = EVEX_0F38;
9093           break;
9094         case 0x3:
9095           vex_table_index = EVEX_0F3A;
9096           break;
9097         case 0x4:
9098           vex_table_index = EVEX_MAP4;
9099           ins->evex_type = evex_from_legacy;
9100           if (ins->address_mode != mode_64bit)
9101             return &bad_opcode;
9102           break;
9103         case 0x5:
9104           vex_table_index = EVEX_MAP5;
9105           break;
9106         case 0x6:
9107           vex_table_index = EVEX_MAP6;
9108           break;
9109         case 0x7:
9110           vex_table_index = EVEX_MAP7;
9111           break;
9112         }
9113
9114       /* The second byte after 0x62.  */
9115       ins->codep++;
9116       ins->vex.w = *ins->codep & 0x80;
9117       if (ins->vex.w && ins->address_mode == mode_64bit)
9118         ins->rex |= REX_W;
9119
9120       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9121
9122       if (!(*ins->codep & 0x4))
9123         ins->rex2 |= REX_X;
9124
9125       switch ((*ins->codep & 0x3))
9126         {
9127         case 0:
9128           break;
9129         case 1:
9130           ins->vex.prefix = DATA_PREFIX_OPCODE;
9131           break;
9132         case 2:
9133           ins->vex.prefix = REPE_PREFIX_OPCODE;
9134           break;
9135         case 3:
9136           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9137           break;
9138         }
9139
9140       /* The third byte after 0x62.  */
9141       ins->codep++;
9142
9143       /* Remember the static rounding bits.  */
9144       ins->vex.ll = (*ins->codep >> 5) & 3;
9145       ins->vex.b = *ins->codep & 0x10;
9146
9147       ins->vex.v = *ins->codep & 0x8;
9148       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9149       ins->vex.zeroing = *ins->codep & 0x80;
9150
9151       if (ins->address_mode != mode_64bit)
9152         {
9153           /* Report bad for !evex_default and when two fixed values of evex
9154              change..  */
9155           if (ins->evex_type != evex_default
9156               || (ins->rex2 & (REX_B | REX_X)))
9157             return &bad_opcode;
9158           /* In 16/32-bit mode silently ignore following bits.  */
9159           ins->rex &= ~REX_B;
9160           ins->rex2 &= ~REX_R;
9161         }
9162
9163       /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
9164          all bits of EVEX.vvvv and EVEX.V' must be 1.  */
9165       if (ins->evex_type == evex_from_legacy && !ins->vex.nd
9166           && (ins->vex.register_specifier || !ins->vex.v))
9167         return &bad_opcode;
9168
9169       ins->need_vex = 4;
9170
9171       /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
9172          lower 2 bits of EVEX.aaa must be 0.  */
9173       if (ins->evex_type == evex_from_legacy
9174           && ((ins->vex.mask_register_specifier & 0x3) != 0
9175               || ins->vex.ll != 0
9176               || ins->vex.zeroing != 0))
9177         return &bad_opcode;
9178
9179       ins->codep++;
9180       vindex = *ins->codep++;
9181       if (vex_table_index != EVEX_MAP7)
9182         dp = &evex_table[vex_table_index][vindex];
9183       else if (vindex == 0xf8)
9184         dp = &map7_f8_opcode;
9185       else
9186         dp = &bad_opcode;
9187       ins->end_codep = ins->codep;
9188       if (!fetch_modrm (ins))
9189         return &err_opcode;
9190
9191       /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9192          which has the same encoding as vex.length == 128 and they can share
9193          the same processing with vex.length in OP_VEX.  */
9194       if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9195         ins->vex.length = 512;
9196       else
9197         {
9198           switch (ins->vex.ll)
9199             {
9200             case 0x0:
9201               ins->vex.length = 128;
9202               break;
9203             case 0x1:
9204               ins->vex.length = 256;
9205               break;
9206             case 0x2:
9207               ins->vex.length = 512;
9208               break;
9209             default:
9210               return &bad_opcode;
9211             }
9212         }
9213       break;
9214
9215     case 0:
9216       dp = &bad_opcode;
9217       break;
9218
9219     default:
9220       abort ();
9221     }
9222
9223   if (dp->name != NULL)
9224     return dp;
9225   else
9226     return get_valid_dis386 (dp, ins);
9227 }
9228
9229 static bool
9230 get_sib (instr_info *ins, int sizeflag)
9231 {
9232   /* If modrm.mod == 3, operand must be register.  */
9233   if (ins->need_modrm
9234       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9235       && ins->modrm.mod != 3
9236       && ins->modrm.rm == 4)
9237     {
9238       if (!fetch_code (ins->info, ins->codep + 2))
9239         return false;
9240       ins->sib.index = (ins->codep[1] >> 3) & 7;
9241       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9242       ins->sib.base = ins->codep[1] & 7;
9243       ins->has_sib = true;
9244     }
9245   else
9246     ins->has_sib = false;
9247
9248   return true;
9249 }
9250
9251 /* Like oappend_with_style (below) but always with text style.  */
9252
9253 static void
9254 oappend (instr_info *ins, const char *s)
9255 {
9256   oappend_with_style (ins, s, dis_style_text);
9257 }
9258
9259 /* Like oappend (above), but S is a string starting with '%'.  In
9260    Intel syntax, the '%' is elided.  */
9261
9262 static void
9263 oappend_register (instr_info *ins, const char *s)
9264 {
9265   oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9266 }
9267
9268 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9269    STYLE is the default style to use in the fprintf_styled_func calls,
9270    however, FMT might include embedded style markers (see oappend_style),
9271    these embedded markers are not printed, but instead change the style
9272    used in the next fprintf_styled_func call.  */
9273
9274 static void ATTRIBUTE_PRINTF_3
9275 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9276                  const char *fmt, ...)
9277 {
9278   va_list ap;
9279   enum disassembler_style curr_style = style;
9280   const char *start, *curr;
9281   char staging_area[40];
9282
9283   va_start (ap, fmt);
9284   /* In particular print_insn()'s processing of op_txt[] can hand rather long
9285      strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9286      with the staging area.  */
9287   if (strcmp (fmt, "%s"))
9288     {
9289       int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9290
9291       va_end (ap);
9292
9293       if (res < 0)
9294         return;
9295
9296       if ((size_t) res >= sizeof (staging_area))
9297         abort ();
9298
9299       start = curr = staging_area;
9300     }
9301   else
9302     {
9303       start = curr = va_arg (ap, const char *);
9304       va_end (ap);
9305     }
9306
9307   do
9308     {
9309       if (*curr == '\0'
9310           || (*curr == STYLE_MARKER_CHAR
9311               && ISXDIGIT (*(curr + 1))
9312               && *(curr + 2) == STYLE_MARKER_CHAR))
9313         {
9314           /* Output content between our START position and CURR.  */
9315           int len = curr - start;
9316           int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9317                                                 "%.*s", len, start);
9318           if (n < 0)
9319             break;
9320
9321           if (*curr == '\0')
9322             break;
9323
9324           /* Skip over the initial STYLE_MARKER_CHAR.  */
9325           ++curr;
9326
9327           /* Update the CURR_STYLE.  As there are less than 16 styles, it
9328              is possible, that if the input is corrupted in some way, that
9329              we might set CURR_STYLE to an invalid value.  Don't worry
9330              though, we check for this situation.  */
9331           if (*curr >= '0' && *curr <= '9')
9332             curr_style = (enum disassembler_style) (*curr - '0');
9333           else if (*curr >= 'a' && *curr <= 'f')
9334             curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9335           else
9336             curr_style = dis_style_text;
9337
9338           /* Check for an invalid style having been selected.  This should
9339              never happen, but it doesn't hurt to be a little paranoid.  */
9340           if (curr_style > dis_style_comment_start)
9341             curr_style = dis_style_text;
9342
9343           /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9344           curr += 2;
9345
9346           /* Reset the START to after the style marker.  */
9347           start = curr;
9348         }
9349       else
9350         ++curr;
9351     }
9352   while (true);
9353 }
9354
9355 static int
9356 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9357 {
9358   const struct dis386 *dp;
9359   int i;
9360   int ret;
9361   char *op_txt[MAX_OPERANDS];
9362   int needcomma;
9363   bool intel_swap_2_3;
9364   int sizeflag, orig_sizeflag;
9365   const char *p;
9366   struct dis_private priv;
9367   int prefix_length;
9368   int op_count;
9369   instr_info ins = {
9370     .info = info,
9371     .intel_syntax = intel_syntax >= 0
9372                     ? intel_syntax
9373                     : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9374     .intel_mnemonic = !SYSV386_COMPAT,
9375     .op_index[0 ... MAX_OPERANDS - 1] = -1,
9376     .start_pc = pc,
9377     .start_codep = priv.the_buffer,
9378     .codep = priv.the_buffer,
9379     .obufp = ins.obuf,
9380     .last_lock_prefix = -1,
9381     .last_repz_prefix = -1,
9382     .last_repnz_prefix = -1,
9383     .last_data_prefix = -1,
9384     .last_addr_prefix = -1,
9385     .last_rex_prefix = -1,
9386     .last_rex2_prefix = -1,
9387     .last_seg_prefix = -1,
9388     .fwait_prefix = -1,
9389   };
9390   char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9391
9392   priv.orig_sizeflag = AFLAG | DFLAG;
9393   if ((info->mach & bfd_mach_i386_i386) != 0)
9394     ins.address_mode = mode_32bit;
9395   else if (info->mach == bfd_mach_i386_i8086)
9396     {
9397       ins.address_mode = mode_16bit;
9398       priv.orig_sizeflag = 0;
9399     }
9400   else
9401     ins.address_mode = mode_64bit;
9402
9403   for (p = info->disassembler_options; p != NULL;)
9404     {
9405       if (startswith (p, "amd64"))
9406         ins.isa64 = amd64;
9407       else if (startswith (p, "intel64"))
9408         ins.isa64 = intel64;
9409       else if (startswith (p, "x86-64"))
9410         {
9411           ins.address_mode = mode_64bit;
9412           priv.orig_sizeflag |= AFLAG | DFLAG;
9413         }
9414       else if (startswith (p, "i386"))
9415         {
9416           ins.address_mode = mode_32bit;
9417           priv.orig_sizeflag |= AFLAG | DFLAG;
9418         }
9419       else if (startswith (p, "i8086"))
9420         {
9421           ins.address_mode = mode_16bit;
9422           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9423         }
9424       else if (startswith (p, "intel"))
9425         {
9426           if (startswith (p + 5, "-mnemonic"))
9427             ins.intel_mnemonic = true;
9428           else
9429             ins.intel_syntax = 1;
9430         }
9431       else if (startswith (p, "att"))
9432         {
9433           ins.intel_syntax = 0;
9434           if (startswith (p + 3, "-mnemonic"))
9435             ins.intel_mnemonic = false;
9436         }
9437       else if (startswith (p, "addr"))
9438         {
9439           if (ins.address_mode == mode_64bit)
9440             {
9441               if (p[4] == '3' && p[5] == '2')
9442                 priv.orig_sizeflag &= ~AFLAG;
9443               else if (p[4] == '6' && p[5] == '4')
9444                 priv.orig_sizeflag |= AFLAG;
9445             }
9446           else
9447             {
9448               if (p[4] == '1' && p[5] == '6')
9449                 priv.orig_sizeflag &= ~AFLAG;
9450               else if (p[4] == '3' && p[5] == '2')
9451                 priv.orig_sizeflag |= AFLAG;
9452             }
9453         }
9454       else if (startswith (p, "data"))
9455         {
9456           if (p[4] == '1' && p[5] == '6')
9457             priv.orig_sizeflag &= ~DFLAG;
9458           else if (p[4] == '3' && p[5] == '2')
9459             priv.orig_sizeflag |= DFLAG;
9460         }
9461       else if (startswith (p, "suffix"))
9462         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9463
9464       p = strchr (p, ',');
9465       if (p != NULL)
9466         p++;
9467     }
9468
9469   if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9470     {
9471       i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9472       return -1;
9473     }
9474
9475   if (ins.intel_syntax)
9476     {
9477       ins.open_char = '[';
9478       ins.close_char = ']';
9479       ins.separator_char = '+';
9480       ins.scale_char = '*';
9481     }
9482   else
9483     {
9484       ins.open_char = '(';
9485       ins.close_char =  ')';
9486       ins.separator_char = ',';
9487       ins.scale_char = ',';
9488     }
9489
9490   /* The output looks better if we put 7 bytes on a line, since that
9491      puts most long word instructions on a single line.  */
9492   info->bytes_per_line = 7;
9493
9494   info->private_data = &priv;
9495   priv.fetched = 0;
9496   priv.insn_start = pc;
9497
9498   for (i = 0; i < MAX_OPERANDS; ++i)
9499     {
9500       op_out[i][0] = 0;
9501       ins.op_out[i] = op_out[i];
9502     }
9503
9504   sizeflag = priv.orig_sizeflag;
9505
9506   switch (ckprefix (&ins))
9507     {
9508     case ckp_okay:
9509       break;
9510
9511     case ckp_bogus:
9512       /* Too many prefixes or unused REX prefixes.  */
9513       for (i = 0;
9514            i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9515            i++)
9516         i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9517                          (i == 0 ? "" : " "),
9518                          prefix_name (ins.address_mode, ins.all_prefixes[i],
9519                                       sizeflag));
9520       ret = i;
9521       goto out;
9522
9523     case ckp_fetch_error:
9524       goto fetch_error_out;
9525     }
9526
9527   ins.nr_prefixes = ins.codep - ins.start_codep;
9528
9529   if (!fetch_code (info, ins.codep + 1))
9530     {
9531     fetch_error_out:
9532       ret = fetch_error (&ins);
9533       goto out;
9534     }
9535
9536   ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9537
9538   if ((ins.prefixes & PREFIX_FWAIT)
9539       && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9540     {
9541       /* Handle ins.prefixes before fwait.  */
9542       for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9543            i++)
9544         i386_dis_printf (info, dis_style_mnemonic, "%s ",
9545                          prefix_name (ins.address_mode, ins.all_prefixes[i],
9546                                       sizeflag));
9547       i386_dis_printf (info, dis_style_mnemonic, "fwait");
9548       ret = i + 1;
9549       goto out;
9550     }
9551
9552   /* REX2.M in rex2 prefix represents map0 or map1.  */
9553   if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9554     {
9555       if (!ins.rex2)
9556         {
9557           ins.codep++;
9558           if (!fetch_code (info, ins.codep + 1))
9559             goto fetch_error_out;
9560         }
9561
9562       dp = &dis386_twobyte[*ins.codep];
9563       ins.need_modrm = twobyte_has_modrm[*ins.codep];
9564     }
9565   else
9566     {
9567       dp = &dis386[*ins.codep];
9568       ins.need_modrm = onebyte_has_modrm[*ins.codep];
9569     }
9570   ins.codep++;
9571
9572   /* Save sizeflag for printing the extra ins.prefixes later before updating
9573      it for mnemonic and operand processing.  The prefix names depend
9574      only on the address mode.  */
9575   orig_sizeflag = sizeflag;
9576   if (ins.prefixes & PREFIX_ADDR)
9577     sizeflag ^= AFLAG;
9578   if ((ins.prefixes & PREFIX_DATA))
9579     sizeflag ^= DFLAG;
9580
9581   ins.end_codep = ins.codep;
9582   if (ins.need_modrm && !fetch_modrm (&ins))
9583     goto fetch_error_out;
9584
9585   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9586     {
9587       if (!get_sib (&ins, sizeflag)
9588           || !dofloat (&ins, sizeflag))
9589         goto fetch_error_out;
9590     }
9591   else
9592     {
9593       dp = get_valid_dis386 (dp, &ins);
9594       if (dp == &err_opcode)
9595         goto fetch_error_out;
9596
9597       /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9598          is interpreted as the operand size override.  */
9599       if (ins.evex_type == evex_from_legacy
9600           && ins.vex.prefix == DATA_PREFIX_OPCODE)
9601         sizeflag ^= DFLAG;
9602
9603       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9604         {
9605           if (!get_sib (&ins, sizeflag))
9606             goto fetch_error_out;
9607           for (i = 0; i < MAX_OPERANDS; ++i)
9608             {
9609               ins.obufp = ins.op_out[i];
9610               ins.op_ad = MAX_OPERANDS - 1 - i;
9611               if (dp->op[i].rtn
9612                   && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9613                 goto fetch_error_out;
9614               /* For EVEX instruction after the last operand masking
9615                  should be printed.  */
9616               if (i == 0 && ins.vex.evex)
9617                 {
9618                   /* Don't print {%k0}.  */
9619                   if (ins.vex.mask_register_specifier)
9620                     {
9621                       const char *reg_name
9622                         = att_names_mask[ins.vex.mask_register_specifier];
9623
9624                       oappend (&ins, "{");
9625                       oappend_register (&ins, reg_name);
9626                       oappend (&ins, "}");
9627
9628                       if (ins.vex.zeroing)
9629                         oappend (&ins, "{z}");
9630                     }
9631                   else if (ins.vex.zeroing)
9632                     {
9633                       oappend (&ins, "{bad}");
9634                       continue;
9635                     }
9636
9637                   /* Instructions with a mask register destination allow for
9638                      zeroing-masking only (if any masking at all), which is
9639                      _not_ expressed by EVEX.z.  */
9640                   if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9641                     ins.illegal_masking = true;
9642
9643                   /* S/G insns require a mask and don't allow
9644                      zeroing-masking.  */
9645                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9646                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9647                       && (ins.vex.mask_register_specifier == 0
9648                           || ins.vex.zeroing))
9649                     ins.illegal_masking = true;
9650
9651                   if (ins.illegal_masking)
9652                     oappend (&ins, "/(bad)");
9653                 }
9654             }
9655
9656           /* Check whether rounding control was enabled for an insn not
9657              supporting it, when evex.b is not treated as evex.nd.  */
9658           if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9659               && !(ins.evex_used & EVEX_b_used))
9660             {
9661               for (i = 0; i < MAX_OPERANDS; ++i)
9662                 {
9663                   ins.obufp = ins.op_out[i];
9664                   if (*ins.obufp)
9665                     continue;
9666                   oappend (&ins, names_rounding[ins.vex.ll]);
9667                   oappend (&ins, "bad}");
9668                   break;
9669                 }
9670             }
9671         }
9672     }
9673
9674   /* Clear instruction information.  */
9675   info->insn_info_valid = 0;
9676   info->branch_delay_insns = 0;
9677   info->data_size = 0;
9678   info->insn_type = dis_noninsn;
9679   info->target = 0;
9680   info->target2 = 0;
9681
9682   /* Reset jump operation indicator.  */
9683   ins.op_is_jump = false;
9684   {
9685     int jump_detection = 0;
9686
9687     /* Extract flags.  */
9688     for (i = 0; i < MAX_OPERANDS; ++i)
9689       {
9690         if ((dp->op[i].rtn == OP_J)
9691             || (dp->op[i].rtn == OP_indirE))
9692           jump_detection |= 1;
9693         else if ((dp->op[i].rtn == BND_Fixup)
9694                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9695           jump_detection |= 2;
9696         else if ((dp->op[i].bytemode == cond_jump_mode)
9697                  || (dp->op[i].bytemode == loop_jcxz_mode))
9698           jump_detection |= 4;
9699       }
9700
9701     /* Determine if this is a jump or branch.  */
9702     if ((jump_detection & 0x3) == 0x3)
9703       {
9704         ins.op_is_jump = true;
9705         if (jump_detection & 0x4)
9706           info->insn_type = dis_condbranch;
9707         else
9708           info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9709             ? dis_jsr : dis_branch;
9710       }
9711   }
9712
9713   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9714      are all 0s in inverted form.  */
9715   if (ins.need_vex && ins.vex.register_specifier != 0)
9716     {
9717       i386_dis_printf (info, dis_style_text, "(bad)");
9718       ret = ins.end_codep - priv.the_buffer;
9719       goto out;
9720     }
9721
9722   if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
9723       && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
9724     {
9725       i386_dis_printf (info, dis_style_text, "(bad)");
9726       ret = ins.end_codep - priv.the_buffer;
9727       goto out;
9728     }
9729
9730   switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
9731     {
9732     case PREFIX_DATA:
9733       /* If only the data prefix is marked as mandatory, its absence renders
9734          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9735       if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9736         {
9737           i386_dis_printf (info, dis_style_text, "(bad)");
9738           ret = ins.end_codep - priv.the_buffer;
9739           goto out;
9740         }
9741       ins.used_prefixes |= PREFIX_DATA;
9742       /* Fall through.  */
9743     case PREFIX_OPCODE:
9744       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9745          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9746          used by putop and MMX/SSE operand and may be overridden by the
9747          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9748          separately.  */
9749       if (((ins.need_vex
9750             ? ins.vex.prefix == REPE_PREFIX_OPCODE
9751               || ins.vex.prefix == REPNE_PREFIX_OPCODE
9752             : (ins.prefixes
9753                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9754            && (ins.used_prefixes
9755                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9756           || (((ins.need_vex
9757                 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9758                 : ((ins.prefixes
9759                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9760                    == PREFIX_DATA))
9761                && (ins.used_prefixes & PREFIX_DATA) == 0))
9762           || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9763               && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9764         {
9765           i386_dis_printf (info, dis_style_text, "(bad)");
9766           ret = ins.end_codep - priv.the_buffer;
9767           goto out;
9768         }
9769       break;
9770
9771     case PREFIX_IGNORED:
9772       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9773          origins in all_prefixes.  */
9774       ins.used_prefixes &= ~PREFIX_OPCODE;
9775       if (ins.last_data_prefix >= 0)
9776         ins.all_prefixes[ins.last_data_prefix] = 0x66;
9777       if (ins.last_repz_prefix >= 0)
9778         ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9779       if (ins.last_repnz_prefix >= 0)
9780         ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9781       break;
9782
9783     case PREFIX_NP_OR_DATA:
9784       if (ins.vex.prefix == REPE_PREFIX_OPCODE
9785           || ins.vex.prefix == REPNE_PREFIX_OPCODE)
9786         {
9787           i386_dis_printf (info, dis_style_text, "(bad)");
9788           ret = ins.end_codep - priv.the_buffer;
9789           goto out;
9790         }
9791       break;
9792
9793     case NO_PREFIX:
9794       if (ins.vex.prefix)
9795         {
9796           i386_dis_printf (info, dis_style_text, "(bad)");
9797           ret = ins.end_codep - priv.the_buffer;
9798           goto out;
9799         }
9800       break;
9801     }
9802
9803   /* Check if the REX prefix is used.  */
9804   if ((ins.rex ^ ins.rex_used) == 0
9805       && !ins.need_vex && ins.last_rex_prefix >= 0)
9806     ins.all_prefixes[ins.last_rex_prefix] = 0;
9807
9808   /* Check if the REX2 prefix is used.  */
9809   if (ins.last_rex2_prefix >= 0
9810       && ((ins.rex2 & REX2_SPECIAL)
9811           || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
9812               && (ins.rex ^ ins.rex_used) == 0
9813               && (ins.rex2 & 7))))
9814     ins.all_prefixes[ins.last_rex2_prefix] = 0;
9815
9816   /* Check if the SEG prefix is used.  */
9817   if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9818                        | PREFIX_FS | PREFIX_GS)) != 0
9819       && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9820     ins.all_prefixes[ins.last_seg_prefix] = 0;
9821
9822   /* Check if the ADDR prefix is used.  */
9823   if ((ins.prefixes & PREFIX_ADDR) != 0
9824       && (ins.used_prefixes & PREFIX_ADDR) != 0)
9825     ins.all_prefixes[ins.last_addr_prefix] = 0;
9826
9827   /* Check if the DATA prefix is used.  */
9828   if ((ins.prefixes & PREFIX_DATA) != 0
9829       && (ins.used_prefixes & PREFIX_DATA) != 0
9830       && !ins.need_vex)
9831     ins.all_prefixes[ins.last_data_prefix] = 0;
9832
9833   /* Print the extra ins.prefixes.  */
9834   prefix_length = 0;
9835   for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9836     if (ins.all_prefixes[i])
9837       {
9838         const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
9839                                         orig_sizeflag);
9840
9841         if (name == NULL)
9842           abort ();
9843         prefix_length += strlen (name) + 1;
9844         if (ins.all_prefixes[i] == REX2_OPCODE)
9845           i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
9846                            (unsigned int) ins.rex2_payload);
9847         else
9848           i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
9849       }
9850
9851   /* Check maximum code length.  */
9852   if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9853     {
9854       i386_dis_printf (info, dis_style_text, "(bad)");
9855       ret = MAX_CODE_LENGTH;
9856       goto out;
9857     }
9858
9859   /* Calculate the number of operands this instruction has.  */
9860   op_count = 0;
9861   for (i = 0; i < MAX_OPERANDS; ++i)
9862     if (*ins.op_out[i] != '\0')
9863       ++op_count;
9864
9865   /* Calculate the number of spaces to print after the mnemonic.  */
9866   ins.obufp = ins.mnemonicendp;
9867   if (op_count > 0)
9868     {
9869       i = strlen (ins.obuf) + prefix_length;
9870       if (i < 7)
9871         i = 7 - i;
9872       else
9873         i = 1;
9874     }
9875   else
9876     i = 0;
9877
9878   /* Print the instruction mnemonic along with any trailing whitespace.  */
9879   i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9880
9881   /* The enter and bound instructions are printed with operands in the same
9882      order as the intel book; everything else is printed in reverse order.  */
9883   intel_swap_2_3 = false;
9884   if (ins.intel_syntax || ins.two_source_ops)
9885     {
9886       for (i = 0; i < MAX_OPERANDS; ++i)
9887         op_txt[i] = ins.op_out[i];
9888
9889       if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9890           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9891         {
9892           op_txt[2] = ins.op_out[3];
9893           op_txt[3] = ins.op_out[2];
9894           intel_swap_2_3 = true;
9895         }
9896
9897       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9898         {
9899           bool riprel;
9900
9901           ins.op_ad = ins.op_index[i];
9902           ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9903           ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9904           riprel = ins.op_riprel[i];
9905           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9906           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9907         }
9908     }
9909   else
9910     {
9911       for (i = 0; i < MAX_OPERANDS; ++i)
9912         op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9913     }
9914
9915   needcomma = 0;
9916   for (i = 0; i < MAX_OPERANDS; ++i)
9917     if (*op_txt[i])
9918       {
9919         /* In Intel syntax embedded rounding / SAE are not separate operands.
9920            Instead they're attached to the prior register operand.  Simply
9921            suppress emission of the comma to achieve that effect.  */
9922         switch (i & -(ins.intel_syntax && dp))
9923           {
9924           case 2:
9925             if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9926               needcomma = 0;
9927             break;
9928           case 3:
9929             if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9930               needcomma = 0;
9931             break;
9932           }
9933         if (needcomma)
9934           i386_dis_printf (info, dis_style_text, ",");
9935         if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9936           {
9937             bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9938
9939             if (ins.op_is_jump)
9940               {
9941                 info->insn_info_valid = 1;
9942                 info->branch_delay_insns = 0;
9943                 info->data_size = 0;
9944                 info->target = target;
9945                 info->target2 = 0;
9946               }
9947             (*info->print_address_func) (target, info);
9948           }
9949         else
9950           i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
9951         needcomma = 1;
9952       }
9953
9954   for (i = 0; i < MAX_OPERANDS; i++)
9955     if (ins.op_index[i] != -1 && ins.op_riprel[i])
9956       {
9957         i386_dis_printf (info, dis_style_comment_start, "        # ");
9958         (*info->print_address_func)
9959           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9960                      + ins.op_address[ins.op_index[i]]),
9961           info);
9962         break;
9963       }
9964   ret = ins.codep - priv.the_buffer;
9965  out:
9966   info->private_data = NULL;
9967   return ret;
9968 }
9969
9970 /* Here for backwards compatibility.  When gdb stops using
9971    print_insn_i386_att and print_insn_i386_intel these functions can
9972    disappear, and print_insn_i386 be merged into print_insn.  */
9973 int
9974 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9975 {
9976   return print_insn (pc, info, 0);
9977 }
9978
9979 int
9980 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9981 {
9982   return print_insn (pc, info, 1);
9983 }
9984
9985 int
9986 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9987 {
9988   return print_insn (pc, info, -1);
9989 }
9990
9991 static const char *float_mem[] = {
9992   /* d8 */
9993   "fadd{s|}",
9994   "fmul{s|}",
9995   "fcom{s|}",
9996   "fcomp{s|}",
9997   "fsub{s|}",
9998   "fsubr{s|}",
9999   "fdiv{s|}",
10000   "fdivr{s|}",
10001   /* d9 */
10002   "fld{s|}",
10003   "(bad)",
10004   "fst{s|}",
10005   "fstp{s|}",
10006   "fldenv{C|C}",
10007   "fldcw",
10008   "fNstenv{C|C}",
10009   "fNstcw",
10010   /* da */
10011   "fiadd{l|}",
10012   "fimul{l|}",
10013   "ficom{l|}",
10014   "ficomp{l|}",
10015   "fisub{l|}",
10016   "fisubr{l|}",
10017   "fidiv{l|}",
10018   "fidivr{l|}",
10019   /* db */
10020   "fild{l|}",
10021   "fisttp{l|}",
10022   "fist{l|}",
10023   "fistp{l|}",
10024   "(bad)",
10025   "fld{t|}",
10026   "(bad)",
10027   "fstp{t|}",
10028   /* dc */
10029   "fadd{l|}",
10030   "fmul{l|}",
10031   "fcom{l|}",
10032   "fcomp{l|}",
10033   "fsub{l|}",
10034   "fsubr{l|}",
10035   "fdiv{l|}",
10036   "fdivr{l|}",
10037   /* dd */
10038   "fld{l|}",
10039   "fisttp{ll|}",
10040   "fst{l||}",
10041   "fstp{l|}",
10042   "frstor{C|C}",
10043   "(bad)",
10044   "fNsave{C|C}",
10045   "fNstsw",
10046   /* de */
10047   "fiadd{s|}",
10048   "fimul{s|}",
10049   "ficom{s|}",
10050   "ficomp{s|}",
10051   "fisub{s|}",
10052   "fisubr{s|}",
10053   "fidiv{s|}",
10054   "fidivr{s|}",
10055   /* df */
10056   "fild{s|}",
10057   "fisttp{s|}",
10058   "fist{s|}",
10059   "fistp{s|}",
10060   "fbld",
10061   "fild{ll|}",
10062   "fbstp",
10063   "fistp{ll|}",
10064 };
10065
10066 static const unsigned char float_mem_mode[] = {
10067   /* d8 */
10068   d_mode,
10069   d_mode,
10070   d_mode,
10071   d_mode,
10072   d_mode,
10073   d_mode,
10074   d_mode,
10075   d_mode,
10076   /* d9 */
10077   d_mode,
10078   0,
10079   d_mode,
10080   d_mode,
10081   0,
10082   w_mode,
10083   0,
10084   w_mode,
10085   /* da */
10086   d_mode,
10087   d_mode,
10088   d_mode,
10089   d_mode,
10090   d_mode,
10091   d_mode,
10092   d_mode,
10093   d_mode,
10094   /* db */
10095   d_mode,
10096   d_mode,
10097   d_mode,
10098   d_mode,
10099   0,
10100   t_mode,
10101   0,
10102   t_mode,
10103   /* dc */
10104   q_mode,
10105   q_mode,
10106   q_mode,
10107   q_mode,
10108   q_mode,
10109   q_mode,
10110   q_mode,
10111   q_mode,
10112   /* dd */
10113   q_mode,
10114   q_mode,
10115   q_mode,
10116   q_mode,
10117   0,
10118   0,
10119   0,
10120   w_mode,
10121   /* de */
10122   w_mode,
10123   w_mode,
10124   w_mode,
10125   w_mode,
10126   w_mode,
10127   w_mode,
10128   w_mode,
10129   w_mode,
10130   /* df */
10131   w_mode,
10132   w_mode,
10133   w_mode,
10134   w_mode,
10135   t_mode,
10136   q_mode,
10137   t_mode,
10138   q_mode
10139 };
10140
10141 #define ST { OP_ST, 0 }
10142 #define STi { OP_STi, 0 }
10143
10144 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10145 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10146 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10147 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10148 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10149 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10150 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10151 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10152 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10153
10154 static const struct dis386 float_reg[][8] = {
10155   /* d8 */
10156   {
10157     { "fadd",   { ST, STi }, 0 },
10158     { "fmul",   { ST, STi }, 0 },
10159     { "fcom",   { STi }, 0 },
10160     { "fcomp",  { STi }, 0 },
10161     { "fsub",   { ST, STi }, 0 },
10162     { "fsubr",  { ST, STi }, 0 },
10163     { "fdiv",   { ST, STi }, 0 },
10164     { "fdivr",  { ST, STi }, 0 },
10165   },
10166   /* d9 */
10167   {
10168     { "fld",    { STi }, 0 },
10169     { "fxch",   { STi }, 0 },
10170     { FGRPd9_2 },
10171     { Bad_Opcode },
10172     { FGRPd9_4 },
10173     { FGRPd9_5 },
10174     { FGRPd9_6 },
10175     { FGRPd9_7 },
10176   },
10177   /* da */
10178   {
10179     { "fcmovb", { ST, STi }, 0 },
10180     { "fcmove", { ST, STi }, 0 },
10181     { "fcmovbe",{ ST, STi }, 0 },
10182     { "fcmovu", { ST, STi }, 0 },
10183     { Bad_Opcode },
10184     { FGRPda_5 },
10185     { Bad_Opcode },
10186     { Bad_Opcode },
10187   },
10188   /* db */
10189   {
10190     { "fcmovnb",{ ST, STi }, 0 },
10191     { "fcmovne",{ ST, STi }, 0 },
10192     { "fcmovnbe",{ ST, STi }, 0 },
10193     { "fcmovnu",{ ST, STi }, 0 },
10194     { FGRPdb_4 },
10195     { "fucomi", { ST, STi }, 0 },
10196     { "fcomi",  { ST, STi }, 0 },
10197     { Bad_Opcode },
10198   },
10199   /* dc */
10200   {
10201     { "fadd",   { STi, ST }, 0 },
10202     { "fmul",   { STi, ST }, 0 },
10203     { Bad_Opcode },
10204     { Bad_Opcode },
10205     { "fsub{!M|r}",     { STi, ST }, 0 },
10206     { "fsub{M|}",       { STi, ST }, 0 },
10207     { "fdiv{!M|r}",     { STi, ST }, 0 },
10208     { "fdiv{M|}",       { STi, ST }, 0 },
10209   },
10210   /* dd */
10211   {
10212     { "ffree",  { STi }, 0 },
10213     { Bad_Opcode },
10214     { "fst",    { STi }, 0 },
10215     { "fstp",   { STi }, 0 },
10216     { "fucom",  { STi }, 0 },
10217     { "fucomp", { STi }, 0 },
10218     { Bad_Opcode },
10219     { Bad_Opcode },
10220   },
10221   /* de */
10222   {
10223     { "faddp",  { STi, ST }, 0 },
10224     { "fmulp",  { STi, ST }, 0 },
10225     { Bad_Opcode },
10226     { FGRPde_3 },
10227     { "fsub{!M|r}p",    { STi, ST }, 0 },
10228     { "fsub{M|}p",      { STi, ST }, 0 },
10229     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10230     { "fdiv{M|}p",      { STi, ST }, 0 },
10231   },
10232   /* df */
10233   {
10234     { "ffreep", { STi }, 0 },
10235     { Bad_Opcode },
10236     { Bad_Opcode },
10237     { Bad_Opcode },
10238     { FGRPdf_4 },
10239     { "fucomip", { ST, STi }, 0 },
10240     { "fcomip", { ST, STi }, 0 },
10241     { Bad_Opcode },
10242   },
10243 };
10244
10245 static const char *const fgrps[][8] = {
10246   /* Bad opcode 0 */
10247   {
10248     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10249   },
10250
10251   /* d9_2  1 */
10252   {
10253     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10254   },
10255
10256   /* d9_4  2 */
10257   {
10258     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10259   },
10260
10261   /* d9_5  3 */
10262   {
10263     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10264   },
10265
10266   /* d9_6  4 */
10267   {
10268     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10269   },
10270
10271   /* d9_7  5 */
10272   {
10273     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10274   },
10275
10276   /* da_5  6 */
10277   {
10278     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10279   },
10280
10281   /* db_4  7 */
10282   {
10283     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10284     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10285   },
10286
10287   /* de_3  8 */
10288   {
10289     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10290   },
10291
10292   /* df_4  9 */
10293   {
10294     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10295   },
10296 };
10297
10298 static void
10299 swap_operand (instr_info *ins)
10300 {
10301   ins->mnemonicendp[0] = '.';
10302   ins->mnemonicendp[1] = 's';
10303   ins->mnemonicendp[2] = '\0';
10304   ins->mnemonicendp += 2;
10305 }
10306
10307 static bool
10308 dofloat (instr_info *ins, int sizeflag)
10309 {
10310   const struct dis386 *dp;
10311   unsigned char floatop = ins->codep[-1];
10312
10313   if (ins->modrm.mod != 3)
10314     {
10315       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10316
10317       putop (ins, float_mem[fp_indx], sizeflag);
10318       ins->obufp = ins->op_out[0];
10319       ins->op_ad = 2;
10320       return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10321     }
10322   /* Skip mod/rm byte.  */
10323   MODRM_CHECK;
10324   ins->codep++;
10325
10326   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10327   if (dp->name == NULL)
10328     {
10329       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10330
10331       /* Instruction fnstsw is only one with strange arg.  */
10332       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10333         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10334     }
10335   else
10336     {
10337       putop (ins, dp->name, sizeflag);
10338
10339       ins->obufp = ins->op_out[0];
10340       ins->op_ad = 2;
10341       if (dp->op[0].rtn
10342           && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10343         return false;
10344
10345       ins->obufp = ins->op_out[1];
10346       ins->op_ad = 1;
10347       if (dp->op[1].rtn
10348           && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10349         return false;
10350     }
10351   return true;
10352 }
10353
10354 static bool
10355 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10356        int sizeflag ATTRIBUTE_UNUSED)
10357 {
10358   oappend_register (ins, "%st");
10359   return true;
10360 }
10361
10362 static bool
10363 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10364         int sizeflag ATTRIBUTE_UNUSED)
10365 {
10366   char scratch[8];
10367   int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10368
10369   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10370     abort ();
10371   oappend_register (ins, scratch);
10372   return true;
10373 }
10374
10375 /* Capital letters in template are macros.  */
10376 static int
10377 putop (instr_info *ins, const char *in_template, int sizeflag)
10378 {
10379   const char *p;
10380   int alt = 0;
10381   int cond = 1;
10382   unsigned int l = 0, len = 0;
10383   char last[4];
10384
10385   for (p = in_template; *p; p++)
10386     {
10387       if (len > l)
10388         {
10389           if (l >= sizeof (last) || !ISUPPER (*p))
10390             abort ();
10391           last[l++] = *p;
10392           continue;
10393         }
10394       switch (*p)
10395         {
10396         default:
10397           *ins->obufp++ = *p;
10398           break;
10399         case '%':
10400           len++;
10401           break;
10402         case '!':
10403           cond = 0;
10404           break;
10405         case '{':
10406           if (ins->intel_syntax)
10407             {
10408               while (*++p != '|')
10409                 if (*p == '}' || *p == '\0')
10410                   abort ();
10411               alt = 1;
10412             }
10413           break;
10414         case '|':
10415           while (*++p != '}')
10416             {
10417               if (*p == '\0')
10418                 abort ();
10419             }
10420           break;
10421         case '}':
10422           alt = 0;
10423           break;
10424         case 'A':
10425           if (ins->intel_syntax)
10426             break;
10427           if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10428               || (sizeflag & SUFFIX_ALWAYS))
10429             *ins->obufp++ = 'b';
10430           break;
10431         case 'B':
10432           if (l == 0)
10433             {
10434             case_B:
10435               if (ins->intel_syntax)
10436                 break;
10437               if (sizeflag & SUFFIX_ALWAYS)
10438                 *ins->obufp++ = 'b';
10439             }
10440           else if (l == 1 && last[0] == 'L')
10441             {
10442               if (ins->address_mode == mode_64bit
10443                   && !(ins->prefixes & PREFIX_ADDR))
10444                 {
10445                   *ins->obufp++ = 'a';
10446                   *ins->obufp++ = 'b';
10447                   *ins->obufp++ = 's';
10448                 }
10449
10450               goto case_B;
10451             }
10452           else
10453             abort ();
10454           break;
10455         case 'C':
10456           if (ins->intel_syntax && !alt)
10457             break;
10458           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10459             {
10460               if (sizeflag & DFLAG)
10461                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10462               else
10463                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10464               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10465             }
10466           break;
10467         case 'D':
10468           if (l == 1)
10469             {
10470               switch (last[0])
10471               {
10472               case 'X':
10473                 if (!ins->vex.evex || ins->vex.w)
10474                   *ins->obufp++ = 'd';
10475                 else
10476                   oappend (ins, "{bad}");
10477                 break;
10478               default:
10479                 abort ();
10480               }
10481               break;
10482             }
10483           if (l)
10484             abort ();
10485           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10486             break;
10487           USED_REX (REX_W);
10488           if (ins->modrm.mod == 3)
10489             {
10490               if (ins->rex & REX_W)
10491                 *ins->obufp++ = 'q';
10492               else
10493                 {
10494                   if (sizeflag & DFLAG)
10495                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10496                   else
10497                     *ins->obufp++ = 'w';
10498                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10499                 }
10500             }
10501           else
10502             *ins->obufp++ = 'w';
10503           break;
10504         case 'E':
10505           if (l == 1)
10506             {
10507               switch (last[0])
10508                 {
10509                 case 'X':
10510                   if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10511                       || (ins->rex2 & 7)
10512                       || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10513                       || !ins->vex.v || ins->vex.mask_register_specifier)
10514                     break;
10515                   /* AVX512 extends a number of V*D insns to also have V*Q variants,
10516                      merely distinguished by EVEX.W.  Look for a use of the
10517                      respective macro.  */
10518                   if (ins->vex.w)
10519                     {
10520                       const char *pct = strchr (p + 1, '%');
10521
10522                       if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10523                         break;
10524                     }
10525                   *ins->obufp++ = '{';
10526                   *ins->obufp++ = 'e';
10527                   *ins->obufp++ = 'v';
10528                   *ins->obufp++ = 'e';
10529                   *ins->obufp++ = 'x';
10530                   *ins->obufp++ = '}';
10531                   *ins->obufp++ = ' ';
10532                   break;
10533                 default:
10534                   abort ();
10535                 }
10536                 break;
10537             }
10538           /* For jcxz/jecxz */
10539           if (ins->address_mode == mode_64bit)
10540             {
10541               if (sizeflag & AFLAG)
10542                 *ins->obufp++ = 'r';
10543               else
10544                 *ins->obufp++ = 'e';
10545             }
10546           else
10547             if (sizeflag & AFLAG)
10548               *ins->obufp++ = 'e';
10549           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10550           break;
10551         case 'F':
10552           if (l == 0)
10553             {
10554               if (ins->intel_syntax)
10555                 break;
10556               if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10557                 {
10558                   if (sizeflag & AFLAG)
10559                     *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10560                   else
10561                     *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10562                   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10563                 }
10564             }
10565           else if (l == 1 && last[0] == 'C')
10566             break;
10567           else
10568             abort ();
10569           break;
10570         case 'G':
10571           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10572                                     && !(sizeflag & SUFFIX_ALWAYS)))
10573             break;
10574           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10575             *ins->obufp++ = 'l';
10576           else
10577             *ins->obufp++ = 'w';
10578           if (!(ins->rex & REX_W))
10579             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10580           break;
10581         case 'H':
10582           if (l == 0)
10583             {
10584               if (ins->intel_syntax)
10585                 break;
10586               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10587                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10588                 {
10589                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10590                   *ins->obufp++ = ',';
10591                   *ins->obufp++ = 'p';
10592
10593                   /* Set active_seg_prefix even if not set in 64-bit mode
10594                      because here it is a valid branch hint. */
10595                   if (ins->prefixes & PREFIX_DS)
10596                     {
10597                       ins->active_seg_prefix = PREFIX_DS;
10598                       *ins->obufp++ = 't';
10599                     }
10600                   else
10601                     {
10602                       ins->active_seg_prefix = PREFIX_CS;
10603                       *ins->obufp++ = 'n';
10604                     }
10605                 }
10606             }
10607           else if (l == 1 && last[0] == 'X')
10608             {
10609               if (!ins->vex.w)
10610                 *ins->obufp++ = 'h';
10611               else
10612                 oappend (ins, "{bad}");
10613             }
10614           else
10615             abort ();
10616           break;
10617         case 'K':
10618           USED_REX (REX_W);
10619           if (ins->rex & REX_W)
10620             *ins->obufp++ = 'q';
10621           else
10622             *ins->obufp++ = 'd';
10623           break;
10624         case 'L':
10625           if (ins->intel_syntax)
10626             break;
10627           if (sizeflag & SUFFIX_ALWAYS)
10628             {
10629               if (ins->rex & REX_W)
10630                 *ins->obufp++ = 'q';
10631               else
10632                 *ins->obufp++ = 'l';
10633             }
10634           break;
10635         case 'M':
10636           if (ins->intel_mnemonic != cond)
10637             *ins->obufp++ = 'r';
10638           break;
10639         case 'N':
10640           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10641             *ins->obufp++ = 'n';
10642           else
10643             ins->used_prefixes |= PREFIX_FWAIT;
10644           break;
10645         case 'O':
10646           USED_REX (REX_W);
10647           if (ins->rex & REX_W)
10648             *ins->obufp++ = 'o';
10649           else if (ins->intel_syntax && (sizeflag & DFLAG))
10650             *ins->obufp++ = 'q';
10651           else
10652             *ins->obufp++ = 'd';
10653           if (!(ins->rex & REX_W))
10654             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10655           break;
10656         case '@':
10657           if (ins->address_mode == mode_64bit
10658               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10659                   || !(ins->prefixes & PREFIX_DATA)))
10660             {
10661               if (sizeflag & SUFFIX_ALWAYS)
10662                 *ins->obufp++ = 'q';
10663               break;
10664             }
10665           /* Fall through.  */
10666         case 'P':
10667           if (l == 0)
10668             {
10669               if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
10670                 {
10671                   /* For pushp and popp, p is printed and do not print {rex2}
10672                      for them.  */
10673                   *ins->obufp++ = 'p';
10674                   ins->rex2 |= REX2_SPECIAL;
10675                   break;
10676                 }
10677
10678               /* For "!P" print nothing else in Intel syntax.  */
10679               if (!cond && ins->intel_syntax)
10680                 break;
10681
10682               if ((ins->modrm.mod == 3 || !cond)
10683                   && !(sizeflag & SUFFIX_ALWAYS))
10684                 break;
10685           /* Fall through.  */
10686         case 'T':
10687               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10688                   || ((sizeflag & SUFFIX_ALWAYS)
10689                       && ins->address_mode != mode_64bit))
10690                 {
10691                   *ins->obufp++ = (sizeflag & DFLAG)
10692                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10693                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10694                 }
10695               else if (sizeflag & SUFFIX_ALWAYS)
10696                 *ins->obufp++ = 'q';
10697             }
10698           else if (l == 1 && last[0] == 'L')
10699             {
10700               if ((ins->prefixes & PREFIX_DATA)
10701                   || (ins->rex & REX_W)
10702                   || (sizeflag & SUFFIX_ALWAYS))
10703                 {
10704                   USED_REX (REX_W);
10705                   if (ins->rex & REX_W)
10706                     *ins->obufp++ = 'q';
10707                   else
10708                     {
10709                       if (sizeflag & DFLAG)
10710                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10711                       else
10712                         *ins->obufp++ = 'w';
10713                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10714                     }
10715                 }
10716             }
10717           else
10718             abort ();
10719           break;
10720         case 'Q':
10721           if (l == 0)
10722             {
10723               if (ins->intel_syntax && !alt)
10724                 break;
10725               USED_REX (REX_W);
10726               if ((ins->need_modrm && ins->modrm.mod != 3 && !ins->vex.nd)
10727                   || (sizeflag & SUFFIX_ALWAYS))
10728                 {
10729                   if (ins->rex & REX_W)
10730                     *ins->obufp++ = 'q';
10731                   else
10732                     {
10733                       if (sizeflag & DFLAG)
10734                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10735                       else
10736                         *ins->obufp++ = 'w';
10737                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10738                     }
10739                 }
10740             }
10741           else if (l == 1 && last[0] == 'D')
10742             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10743           else if (l == 1 && last[0] == 'L')
10744             {
10745               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10746                        : ins->address_mode != mode_64bit)
10747                 break;
10748               if ((ins->rex & REX_W))
10749                 {
10750                   USED_REX (REX_W);
10751                   *ins->obufp++ = 'q';
10752                 }
10753               else if ((ins->address_mode == mode_64bit && cond)
10754                       || (sizeflag & SUFFIX_ALWAYS))
10755                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10756             }
10757           else
10758             abort ();
10759           break;
10760         case 'R':
10761           USED_REX (REX_W);
10762           if (ins->rex & REX_W)
10763             *ins->obufp++ = 'q';
10764           else if (sizeflag & DFLAG)
10765             {
10766               if (ins->intel_syntax)
10767                   *ins->obufp++ = 'd';
10768               else
10769                   *ins->obufp++ = 'l';
10770             }
10771           else
10772             *ins->obufp++ = 'w';
10773           if (ins->intel_syntax && !p[1]
10774               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10775             *ins->obufp++ = 'e';
10776           if (!(ins->rex & REX_W))
10777             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10778           break;
10779         case 'S':
10780           if (l == 0)
10781             {
10782             case_S:
10783               if (ins->intel_syntax)
10784                 break;
10785               if (sizeflag & SUFFIX_ALWAYS)
10786                 {
10787                   if (ins->rex & REX_W)
10788                     *ins->obufp++ = 'q';
10789                   else
10790                     {
10791                       if (sizeflag & DFLAG)
10792                         *ins->obufp++ = 'l';
10793                       else
10794                         *ins->obufp++ = 'w';
10795                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10796                     }
10797                 }
10798               break;
10799             }
10800           if (l != 1)
10801             abort ();
10802           switch (last[0])
10803             {
10804             case 'L':
10805               if (ins->address_mode == mode_64bit
10806                   && !(ins->prefixes & PREFIX_ADDR))
10807                 {
10808                   *ins->obufp++ = 'a';
10809                   *ins->obufp++ = 'b';
10810                   *ins->obufp++ = 's';
10811                 }
10812
10813               goto case_S;
10814             case 'X':
10815               if (!ins->vex.evex || !ins->vex.w)
10816                 *ins->obufp++ = 's';
10817               else
10818                 oappend (ins, "{bad}");
10819               break;
10820             default:
10821               abort ();
10822             }
10823           break;
10824         case 'V':
10825           if (l == 0)
10826             {
10827               if (ins->need_vex)
10828                 *ins->obufp++ = 'v';
10829             }
10830           else if (l == 1)
10831             {
10832               switch (last[0])
10833                 {
10834                 case 'X':
10835                   if (ins->vex.evex)
10836                     break;
10837                   *ins->obufp++ = '{';
10838                   *ins->obufp++ = 'v';
10839                   *ins->obufp++ = 'e';
10840                   *ins->obufp++ = 'x';
10841                   *ins->obufp++ = '}';
10842                   *ins->obufp++ = ' ';
10843                   break;
10844                 case 'L':
10845                   if (ins->rex & REX_W)
10846                     {
10847                       *ins->obufp++ = 'a';
10848                       *ins->obufp++ = 'b';
10849                       *ins->obufp++ = 's';
10850                     }
10851                   goto case_S;
10852                 default:
10853                   abort ();
10854                 }
10855             }
10856           else
10857             abort ();
10858           break;
10859         case 'W':
10860           if (l == 0)
10861             {
10862               /* operand size flag for cwtl, cbtw */
10863               USED_REX (REX_W);
10864               if (ins->rex & REX_W)
10865                 {
10866                   if (ins->intel_syntax)
10867                     *ins->obufp++ = 'd';
10868                   else
10869                     *ins->obufp++ = 'l';
10870                 }
10871               else if (sizeflag & DFLAG)
10872                 *ins->obufp++ = 'w';
10873               else
10874                 *ins->obufp++ = 'b';
10875               if (!(ins->rex & REX_W))
10876                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10877             }
10878           else if (l == 1)
10879             {
10880               if (!ins->need_vex)
10881                 abort ();
10882               if (last[0] == 'X')
10883                 *ins->obufp++ = ins->vex.w ? 'd': 's';
10884               else if (last[0] == 'B')
10885                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10886               else
10887                 abort ();
10888             }
10889           else
10890             abort ();
10891           break;
10892         case 'X':
10893           if (l != 0)
10894             abort ();
10895           if (ins->need_vex
10896               ? ins->vex.prefix == DATA_PREFIX_OPCODE
10897               : ins->prefixes & PREFIX_DATA)
10898             {
10899               *ins->obufp++ = 'd';
10900               ins->used_prefixes |= PREFIX_DATA;
10901             }
10902           else
10903             *ins->obufp++ = 's';
10904           break;
10905         case 'Y':
10906           if (l == 0)
10907             {
10908               if (ins->vex.mask_register_specifier)
10909                 ins->illegal_masking = true;
10910             }
10911           else if (l == 1 && last[0] == 'X')
10912             {
10913               if (!ins->need_vex)
10914                 break;
10915               if (ins->intel_syntax
10916                   || ((ins->modrm.mod == 3 || ins->vex.b)
10917                       && !(sizeflag & SUFFIX_ALWAYS)))
10918                 break;
10919               switch (ins->vex.length)
10920                 {
10921                 case 128:
10922                   *ins->obufp++ = 'x';
10923                   break;
10924                 case 256:
10925                   *ins->obufp++ = 'y';
10926                   break;
10927                 case 512:
10928                   if (!ins->vex.evex)
10929                 default:
10930                     abort ();
10931                 }
10932             }
10933           else
10934             abort ();
10935           break;
10936         case 'Z':
10937           if (l == 0)
10938             {
10939               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10940               ins->modrm.mod = 3;
10941               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10942                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10943             }
10944           else if (l == 1 && last[0] == 'X')
10945             {
10946               if (!ins->vex.evex)
10947                 abort ();
10948               if (ins->intel_syntax
10949                   || ((ins->modrm.mod == 3 || ins->vex.b)
10950                       && !(sizeflag & SUFFIX_ALWAYS)))
10951                 break;
10952               switch (ins->vex.length)
10953                 {
10954                 case 128:
10955                   *ins->obufp++ = 'x';
10956                   break;
10957                 case 256:
10958                   *ins->obufp++ = 'y';
10959                   break;
10960                 case 512:
10961                   *ins->obufp++ = 'z';
10962                   break;
10963                 default:
10964                   abort ();
10965                 }
10966             }
10967           else
10968             abort ();
10969           break;
10970         case '^':
10971           if (ins->intel_syntax)
10972             break;
10973           if (ins->isa64 == intel64 && (ins->rex & REX_W))
10974             {
10975               USED_REX (REX_W);
10976               *ins->obufp++ = 'q';
10977               break;
10978             }
10979           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10980             {
10981               if (sizeflag & DFLAG)
10982                 *ins->obufp++ = 'l';
10983               else
10984                 *ins->obufp++ = 'w';
10985               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10986             }
10987           break;
10988         }
10989
10990       if (len == l)
10991         len = l = 0;
10992     }
10993   *ins->obufp = 0;
10994   ins->mnemonicendp = ins->obufp;
10995   return 0;
10996 }
10997
10998 /* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
10999    the buffer pointed to by INS->obufp has space.  A style marker is made
11000    from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
11001    digit, followed by another STYLE_MARKER_CHAR.  This function assumes
11002    that the number of styles is not greater than 16.  */
11003
11004 static void
11005 oappend_insert_style (instr_info *ins, enum disassembler_style style)
11006 {
11007   unsigned num = (unsigned) style;
11008
11009   /* We currently assume that STYLE can be encoded as a single hex
11010      character.  If more styles are added then this might start to fail,
11011      and we'll need to expand this code.  */
11012   if (num > 0xf)
11013     abort ();
11014
11015   *ins->obufp++ = STYLE_MARKER_CHAR;
11016   *ins->obufp++ = (num < 10 ? ('0' + num)
11017                    : ((num < 16) ? ('a' + (num - 10)) : '0'));
11018   *ins->obufp++ = STYLE_MARKER_CHAR;
11019
11020   /* This final null character is not strictly necessary, after inserting a
11021      style marker we should always be inserting some additional content.
11022      However, having the buffer null terminated doesn't cost much, and make
11023      it easier to debug what's going on.  Also, if we do ever forget to add
11024      any additional content after this style marker, then the buffer will
11025      still be well formed.  */
11026   *ins->obufp = '\0';
11027 }
11028
11029 static void
11030 oappend_with_style (instr_info *ins, const char *s,
11031                     enum disassembler_style style)
11032 {
11033   oappend_insert_style (ins, style);
11034   ins->obufp = stpcpy (ins->obufp, s);
11035 }
11036
11037 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11038    the style for the character as STYLE.  */
11039
11040 static void
11041 oappend_char_with_style (instr_info *ins, const char c,
11042                          enum disassembler_style style)
11043 {
11044   oappend_insert_style (ins, style);
11045   *ins->obufp++ = c;
11046   *ins->obufp = '\0';
11047 }
11048
11049 /* Like oappend_char_with_style, but always uses dis_style_text.  */
11050
11051 static void
11052 oappend_char (instr_info *ins, const char c)
11053 {
11054   oappend_char_with_style (ins, c, dis_style_text);
11055 }
11056
11057 static void
11058 append_seg (instr_info *ins)
11059 {
11060   /* Only print the active segment register.  */
11061   if (!ins->active_seg_prefix)
11062     return;
11063
11064   ins->used_prefixes |= ins->active_seg_prefix;
11065   switch (ins->active_seg_prefix)
11066     {
11067     case PREFIX_CS:
11068       oappend_register (ins, att_names_seg[1]);
11069       break;
11070     case PREFIX_DS:
11071       oappend_register (ins, att_names_seg[3]);
11072       break;
11073     case PREFIX_SS:
11074       oappend_register (ins, att_names_seg[2]);
11075       break;
11076     case PREFIX_ES:
11077       oappend_register (ins, att_names_seg[0]);
11078       break;
11079     case PREFIX_FS:
11080       oappend_register (ins, att_names_seg[4]);
11081       break;
11082     case PREFIX_GS:
11083       oappend_register (ins, att_names_seg[5]);
11084       break;
11085     default:
11086       break;
11087     }
11088   oappend_char (ins, ':');
11089 }
11090
11091 static void
11092 print_operand_value (instr_info *ins, bfd_vma disp,
11093                      enum disassembler_style style)
11094 {
11095   char tmp[30];
11096
11097   if (ins->address_mode != mode_64bit)
11098     disp &= 0xffffffff;
11099   sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11100   oappend_with_style (ins, tmp, style);
11101 }
11102
11103 /* Like oappend, but called for immediate operands.  */
11104
11105 static void
11106 oappend_immediate (instr_info *ins, bfd_vma imm)
11107 {
11108   if (!ins->intel_syntax)
11109     oappend_char_with_style (ins, '$', dis_style_immediate);
11110   print_operand_value (ins, imm, dis_style_immediate);
11111 }
11112
11113 /* Put DISP in BUF as signed hex number.  */
11114
11115 static void
11116 print_displacement (instr_info *ins, bfd_signed_vma val)
11117 {
11118   char tmp[30];
11119
11120   if (val < 0)
11121     {
11122       oappend_char_with_style (ins, '-', dis_style_address_offset);
11123       val = (bfd_vma) 0 - val;
11124
11125       /* Check for possible overflow.  */
11126       if (val < 0)
11127         {
11128           switch (ins->address_mode)
11129             {
11130             case mode_64bit:
11131               oappend_with_style (ins, "0x8000000000000000",
11132                                   dis_style_address_offset);
11133               break;
11134             case mode_32bit:
11135               oappend_with_style (ins, "0x80000000",
11136                                   dis_style_address_offset);
11137               break;
11138             case mode_16bit:
11139               oappend_with_style (ins, "0x8000",
11140                                   dis_style_address_offset);
11141               break;
11142             }
11143           return;
11144         }
11145     }
11146
11147   sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11148   oappend_with_style (ins, tmp, dis_style_address_offset);
11149 }
11150
11151 static void
11152 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11153 {
11154   /* Check if there is a broadcast, when evex.b is not treated as evex.nd.  */
11155   if (ins->vex.b && ins->evex_type == evex_default)
11156     {
11157       if (!ins->vex.no_broadcast)
11158         switch (bytemode)
11159           {
11160           case x_mode:
11161           case evex_half_bcst_xmmq_mode:
11162             if (ins->vex.w)
11163               oappend (ins, "QWORD BCST ");
11164             else
11165               oappend (ins, "DWORD BCST ");
11166             break;
11167           case xh_mode:
11168           case evex_half_bcst_xmmqh_mode:
11169           case evex_half_bcst_xmmqdh_mode:
11170             oappend (ins, "WORD BCST ");
11171             break;
11172           default:
11173             ins->vex.no_broadcast = true;
11174             break;
11175           }
11176       return;
11177     }
11178   switch (bytemode)
11179     {
11180     case b_mode:
11181     case b_swap_mode:
11182     case db_mode:
11183       oappend (ins, "BYTE PTR ");
11184       break;
11185     case w_mode:
11186     case w_swap_mode:
11187     case dw_mode:
11188       oappend (ins, "WORD PTR ");
11189       break;
11190     case indir_v_mode:
11191       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11192         {
11193           oappend (ins, "QWORD PTR ");
11194           break;
11195         }
11196       /* Fall through.  */
11197     case stack_v_mode:
11198       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11199                                               || (ins->rex & REX_W)))
11200         {
11201           oappend (ins, "QWORD PTR ");
11202           break;
11203         }
11204       /* Fall through.  */
11205     case v_mode:
11206     case v_swap_mode:
11207     case dq_mode:
11208       USED_REX (REX_W);
11209       if (ins->rex & REX_W)
11210         oappend (ins, "QWORD PTR ");
11211       else if (bytemode == dq_mode)
11212         oappend (ins, "DWORD PTR ");
11213       else
11214         {
11215           if (sizeflag & DFLAG)
11216             oappend (ins, "DWORD PTR ");
11217           else
11218             oappend (ins, "WORD PTR ");
11219           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11220         }
11221       break;
11222     case z_mode:
11223       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11224         *ins->obufp++ = 'D';
11225       oappend (ins, "WORD PTR ");
11226       if (!(ins->rex & REX_W))
11227         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11228       break;
11229     case a_mode:
11230       if (sizeflag & DFLAG)
11231         oappend (ins, "QWORD PTR ");
11232       else
11233         oappend (ins, "DWORD PTR ");
11234       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11235       break;
11236     case movsxd_mode:
11237       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11238         oappend (ins, "WORD PTR ");
11239       else
11240         oappend (ins, "DWORD PTR ");
11241       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11242       break;
11243     case d_mode:
11244     case d_swap_mode:
11245       oappend (ins, "DWORD PTR ");
11246       break;
11247     case q_mode:
11248     case q_swap_mode:
11249       oappend (ins, "QWORD PTR ");
11250       break;
11251     case m_mode:
11252       if (ins->address_mode == mode_64bit)
11253         oappend (ins, "QWORD PTR ");
11254       else
11255         oappend (ins, "DWORD PTR ");
11256       break;
11257     case f_mode:
11258       if (sizeflag & DFLAG)
11259         oappend (ins, "FWORD PTR ");
11260       else
11261         oappend (ins, "DWORD PTR ");
11262       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11263       break;
11264     case t_mode:
11265       oappend (ins, "TBYTE PTR ");
11266       break;
11267     case x_mode:
11268     case xh_mode:
11269     case x_swap_mode:
11270     case evex_x_gscat_mode:
11271     case evex_x_nobcst_mode:
11272     case bw_unit_mode:
11273       if (ins->need_vex)
11274         {
11275           switch (ins->vex.length)
11276             {
11277             case 128:
11278               oappend (ins, "XMMWORD PTR ");
11279               break;
11280             case 256:
11281               oappend (ins, "YMMWORD PTR ");
11282               break;
11283             case 512:
11284               oappend (ins, "ZMMWORD PTR ");
11285               break;
11286             default:
11287               abort ();
11288             }
11289         }
11290       else
11291         oappend (ins, "XMMWORD PTR ");
11292       break;
11293     case xmm_mode:
11294       oappend (ins, "XMMWORD PTR ");
11295       break;
11296     case ymm_mode:
11297       oappend (ins, "YMMWORD PTR ");
11298       break;
11299     case xmmq_mode:
11300     case evex_half_bcst_xmmqh_mode:
11301     case evex_half_bcst_xmmq_mode:
11302       switch (ins->vex.length)
11303         {
11304         case 0:
11305         case 128:
11306           oappend (ins, "QWORD PTR ");
11307           break;
11308         case 256:
11309           oappend (ins, "XMMWORD PTR ");
11310           break;
11311         case 512:
11312           oappend (ins, "YMMWORD PTR ");
11313           break;
11314         default:
11315           abort ();
11316         }
11317       break;
11318     case xmmdw_mode:
11319       if (!ins->need_vex)
11320         abort ();
11321
11322       switch (ins->vex.length)
11323         {
11324         case 128:
11325           oappend (ins, "WORD PTR ");
11326           break;
11327         case 256:
11328           oappend (ins, "DWORD PTR ");
11329           break;
11330         case 512:
11331           oappend (ins, "QWORD PTR ");
11332           break;
11333         default:
11334           abort ();
11335         }
11336       break;
11337     case xmmqd_mode:
11338     case evex_half_bcst_xmmqdh_mode:
11339       if (!ins->need_vex)
11340         abort ();
11341
11342       switch (ins->vex.length)
11343         {
11344         case 128:
11345           oappend (ins, "DWORD PTR ");
11346           break;
11347         case 256:
11348           oappend (ins, "QWORD PTR ");
11349           break;
11350         case 512:
11351           oappend (ins, "XMMWORD PTR ");
11352           break;
11353         default:
11354           abort ();
11355         }
11356       break;
11357     case ymmq_mode:
11358       if (!ins->need_vex)
11359         abort ();
11360
11361       switch (ins->vex.length)
11362         {
11363         case 128:
11364           oappend (ins, "QWORD PTR ");
11365           break;
11366         case 256:
11367           oappend (ins, "YMMWORD PTR ");
11368           break;
11369         case 512:
11370           oappend (ins, "ZMMWORD PTR ");
11371           break;
11372         default:
11373           abort ();
11374         }
11375       break;
11376     case o_mode:
11377       oappend (ins, "OWORD PTR ");
11378       break;
11379     case vex_vsib_d_w_dq_mode:
11380     case vex_vsib_q_w_dq_mode:
11381       if (!ins->need_vex)
11382         abort ();
11383       if (ins->vex.w)
11384         oappend (ins, "QWORD PTR ");
11385       else
11386         oappend (ins, "DWORD PTR ");
11387       break;
11388     case mask_bd_mode:
11389       if (!ins->need_vex || ins->vex.length != 128)
11390         abort ();
11391       if (ins->vex.w)
11392         oappend (ins, "DWORD PTR ");
11393       else
11394         oappend (ins, "BYTE PTR ");
11395       break;
11396     case mask_mode:
11397       if (!ins->need_vex)
11398         abort ();
11399       if (ins->vex.w)
11400         oappend (ins, "QWORD PTR ");
11401       else
11402         oappend (ins, "WORD PTR ");
11403       break;
11404     case v_bnd_mode:
11405     case v_bndmk_mode:
11406     default:
11407       break;
11408     }
11409 }
11410
11411 static void
11412 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11413                 int bytemode, int sizeflag)
11414 {
11415   const char (*names)[8];
11416
11417   /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11418      as the consumer will inspect it only for the destination operand.  */
11419   if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11420     ins->illegal_masking = true;
11421
11422   USED_REX (rexmask);
11423   if (ins->rex & rexmask)
11424     reg += 8;
11425   if (ins->rex2 & rexmask)
11426     reg += 16;
11427
11428   switch (bytemode)
11429     {
11430     case b_mode:
11431     case b_swap_mode:
11432       if (reg & 4)
11433         USED_REX (0);
11434       if (ins->rex || ins->rex2)
11435         names = att_names8rex;
11436       else
11437         names = att_names8;
11438       break;
11439     case w_mode:
11440       names = att_names16;
11441       break;
11442     case d_mode:
11443     case dw_mode:
11444     case db_mode:
11445       names = att_names32;
11446       break;
11447     case q_mode:
11448       names = att_names64;
11449       break;
11450     case m_mode:
11451     case v_bnd_mode:
11452       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11453       break;
11454     case bnd_mode:
11455     case bnd_swap_mode:
11456       if (reg > 0x3)
11457         {
11458           oappend (ins, "(bad)");
11459           return;
11460         }
11461       names = att_names_bnd;
11462       break;
11463     case indir_v_mode:
11464       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11465         {
11466           names = att_names64;
11467           break;
11468         }
11469       /* Fall through.  */
11470     case stack_v_mode:
11471       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11472                                               || (ins->rex & REX_W)))
11473         {
11474           names = att_names64;
11475           break;
11476         }
11477       bytemode = v_mode;
11478       /* Fall through.  */
11479     case v_mode:
11480     case v_swap_mode:
11481     case dq_mode:
11482       USED_REX (REX_W);
11483       if (ins->rex & REX_W)
11484         names = att_names64;
11485       else if (bytemode != v_mode && bytemode != v_swap_mode)
11486         names = att_names32;
11487       else
11488         {
11489           if (sizeflag & DFLAG)
11490             names = att_names32;
11491           else
11492             names = att_names16;
11493           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11494         }
11495       break;
11496     case movsxd_mode:
11497       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11498         names = att_names16;
11499       else
11500         names = att_names32;
11501       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11502       break;
11503     case va_mode:
11504       names = (ins->address_mode == mode_64bit
11505                ? att_names64 : att_names32);
11506       if (!(ins->prefixes & PREFIX_ADDR))
11507         names = (ins->address_mode == mode_16bit
11508                      ? att_names16 : names);
11509       else
11510         {
11511           /* Remove "addr16/addr32".  */
11512           ins->all_prefixes[ins->last_addr_prefix] = 0;
11513           names = (ins->address_mode != mode_32bit
11514                        ? att_names32 : att_names16);
11515           ins->used_prefixes |= PREFIX_ADDR;
11516         }
11517       break;
11518     case mask_bd_mode:
11519     case mask_mode:
11520       if (reg > 0x7)
11521         {
11522           oappend (ins, "(bad)");
11523           return;
11524         }
11525       names = att_names_mask;
11526       break;
11527     case 0:
11528       return;
11529     default:
11530       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11531       return;
11532     }
11533   oappend_register (ins, names[reg]);
11534 }
11535
11536 static bool
11537 get8s (instr_info *ins, bfd_vma *res)
11538 {
11539   if (!fetch_code (ins->info, ins->codep + 1))
11540     return false;
11541   *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11542   return true;
11543 }
11544
11545 static bool
11546 get16 (instr_info *ins, bfd_vma *res)
11547 {
11548   if (!fetch_code (ins->info, ins->codep + 2))
11549     return false;
11550   *res = *ins->codep++;
11551   *res |= (bfd_vma) *ins->codep++ << 8;
11552   return true;
11553 }
11554
11555 static bool
11556 get16s (instr_info *ins, bfd_vma *res)
11557 {
11558   if (!get16 (ins, res))
11559     return false;
11560   *res = (*res ^ 0x8000) - 0x8000;
11561   return true;
11562 }
11563
11564 static bool
11565 get32 (instr_info *ins, bfd_vma *res)
11566 {
11567   if (!fetch_code (ins->info, ins->codep + 4))
11568     return false;
11569   *res = *ins->codep++;
11570   *res |= (bfd_vma) *ins->codep++ << 8;
11571   *res |= (bfd_vma) *ins->codep++ << 16;
11572   *res |= (bfd_vma) *ins->codep++ << 24;
11573   return true;
11574 }
11575
11576 static bool
11577 get32s (instr_info *ins, bfd_vma *res)
11578 {
11579   if (!get32 (ins, res))
11580     return false;
11581
11582   *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11583
11584   return true;
11585 }
11586
11587 static bool
11588 get64 (instr_info *ins, uint64_t *res)
11589 {
11590   unsigned int a;
11591   unsigned int b;
11592
11593   if (!fetch_code (ins->info, ins->codep + 8))
11594     return false;
11595   a = *ins->codep++;
11596   a |= (unsigned int) *ins->codep++ << 8;
11597   a |= (unsigned int) *ins->codep++ << 16;
11598   a |= (unsigned int) *ins->codep++ << 24;
11599   b = *ins->codep++;
11600   b |= (unsigned int) *ins->codep++ << 8;
11601   b |= (unsigned int) *ins->codep++ << 16;
11602   b |= (unsigned int) *ins->codep++ << 24;
11603   *res = a + ((uint64_t) b << 32);
11604   return true;
11605 }
11606
11607 static void
11608 set_op (instr_info *ins, bfd_vma op, bool riprel)
11609 {
11610   ins->op_index[ins->op_ad] = ins->op_ad;
11611   if (ins->address_mode == mode_64bit)
11612     ins->op_address[ins->op_ad] = op;
11613   else /* Mask to get a 32-bit address.  */
11614     ins->op_address[ins->op_ad] = op & 0xffffffff;
11615   ins->op_riprel[ins->op_ad] = riprel;
11616 }
11617
11618 static bool
11619 BadOp (instr_info *ins)
11620 {
11621   /* Throw away prefixes and 1st. opcode byte.  */
11622   struct dis_private *priv = ins->info->private_data;
11623
11624   ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
11625   ins->obufp = stpcpy (ins->obufp, "(bad)");
11626   return true;
11627 }
11628
11629 static bool
11630 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
11631                int sizeflag ATTRIBUTE_UNUSED)
11632 {
11633   if (ins->modrm.mod != 3)
11634     return BadOp (ins);
11635
11636   /* Skip mod/rm byte.  */
11637   MODRM_CHECK;
11638   ins->codep++;
11639   ins->has_skipped_modrm = true;
11640   return true;
11641 }
11642
11643 static bool
11644 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11645 {
11646   int add = (ins->rex & REX_B) ? 8 : 0;
11647   int riprel = 0;
11648   int shift;
11649
11650   add += (ins->rex2 & REX_B) ? 16 : 0;
11651
11652   /* Handles EVEX other than APX EVEX-promoted instructions.  */
11653   if (ins->vex.evex && ins->evex_type == evex_default)
11654     {
11655
11656       /* Zeroing-masking is invalid for memory destinations. Set the flag
11657          uniformly, as the consumer will inspect it only for the destination
11658          operand.  */
11659       if (ins->vex.zeroing)
11660         ins->illegal_masking = true;
11661
11662       switch (bytemode)
11663         {
11664         case dw_mode:
11665         case w_mode:
11666         case w_swap_mode:
11667           shift = 1;
11668           break;
11669         case db_mode:
11670         case b_mode:
11671           shift = 0;
11672           break;
11673         case dq_mode:
11674           if (ins->address_mode != mode_64bit)
11675             {
11676         case d_mode:
11677         case d_swap_mode:
11678               shift = 2;
11679               break;
11680             }
11681             /* fall through */
11682         case vex_vsib_d_w_dq_mode:
11683         case vex_vsib_q_w_dq_mode:
11684         case evex_x_gscat_mode:
11685           shift = ins->vex.w ? 3 : 2;
11686           break;
11687         case xh_mode:
11688         case evex_half_bcst_xmmqh_mode:
11689         case evex_half_bcst_xmmqdh_mode:
11690           if (ins->vex.b)
11691             {
11692               shift = ins->vex.w ? 2 : 1;
11693               break;
11694             }
11695           /* Fall through.  */
11696         case x_mode:
11697         case evex_half_bcst_xmmq_mode:
11698           if (ins->vex.b)
11699             {
11700               shift = ins->vex.w ? 3 : 2;
11701               break;
11702             }
11703           /* Fall through.  */
11704         case xmmqd_mode:
11705         case xmmdw_mode:
11706         case xmmq_mode:
11707         case ymmq_mode:
11708         case evex_x_nobcst_mode:
11709         case x_swap_mode:
11710           switch (ins->vex.length)
11711             {
11712             case 128:
11713               shift = 4;
11714               break;
11715             case 256:
11716               shift = 5;
11717               break;
11718             case 512:
11719               shift = 6;
11720               break;
11721             default:
11722               abort ();
11723             }
11724           /* Make necessary corrections to shift for modes that need it.  */
11725           if (bytemode == xmmq_mode
11726               || bytemode == evex_half_bcst_xmmqh_mode
11727               || bytemode == evex_half_bcst_xmmq_mode
11728               || (bytemode == ymmq_mode && ins->vex.length == 128))
11729             shift -= 1;
11730           else if (bytemode == xmmqd_mode
11731                    || bytemode == evex_half_bcst_xmmqdh_mode)
11732             shift -= 2;
11733           else if (bytemode == xmmdw_mode)
11734             shift -= 3;
11735           break;
11736         case ymm_mode:
11737           shift = 5;
11738           break;
11739         case xmm_mode:
11740           shift = 4;
11741           break;
11742         case q_mode:
11743         case q_swap_mode:
11744           shift = 3;
11745           break;
11746         case bw_unit_mode:
11747           shift = ins->vex.w ? 1 : 0;
11748           break;
11749         default:
11750           abort ();
11751         }
11752     }
11753   else
11754     shift = 0;
11755
11756   USED_REX (REX_B);
11757   if (ins->intel_syntax)
11758     intel_operand_size (ins, bytemode, sizeflag);
11759   append_seg (ins);
11760
11761   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11762     {
11763       /* 32/64 bit address mode */
11764       bfd_vma disp = 0;
11765       int havedisp;
11766       int havebase;
11767       int needindex;
11768       int needaddr32;
11769       int base, rbase;
11770       int vindex = 0;
11771       int scale = 0;
11772       int addr32flag = !((sizeflag & AFLAG)
11773                          || bytemode == v_bnd_mode
11774                          || bytemode == v_bndmk_mode
11775                          || bytemode == bnd_mode
11776                          || bytemode == bnd_swap_mode);
11777       bool check_gather = false;
11778       const char (*indexes)[8] = NULL;
11779
11780       havebase = 1;
11781       base = ins->modrm.rm;
11782
11783       if (base == 4)
11784         {
11785           vindex = ins->sib.index;
11786           USED_REX (REX_X);
11787           if (ins->rex & REX_X)
11788             vindex += 8;
11789           switch (bytemode)
11790             {
11791             case vex_vsib_d_w_dq_mode:
11792             case vex_vsib_q_w_dq_mode:
11793               if (!ins->need_vex)
11794                 abort ();
11795               if (ins->vex.evex)
11796                 {
11797                   /* S/G EVEX insns require EVEX.X4 not to be set.  */
11798                   if (ins->rex2 & REX_X)
11799                     {
11800                       oappend (ins, "(bad)");
11801                       return true;
11802                     }
11803
11804                   if (!ins->vex.v)
11805                     vindex += 16;
11806                   check_gather = ins->obufp == ins->op_out[1];
11807                 }
11808
11809               switch (ins->vex.length)
11810                 {
11811                 case 128:
11812                   indexes = att_names_xmm;
11813                   break;
11814                 case 256:
11815                   if (!ins->vex.w
11816                       || bytemode == vex_vsib_q_w_dq_mode)
11817                     indexes = att_names_ymm;
11818                   else
11819                     indexes = att_names_xmm;
11820                   break;
11821                 case 512:
11822                   if (!ins->vex.w
11823                       || bytemode == vex_vsib_q_w_dq_mode)
11824                     indexes = att_names_zmm;
11825                   else
11826                     indexes = att_names_ymm;
11827                   break;
11828                 default:
11829                   abort ();
11830                 }
11831               break;
11832             default:
11833               if (ins->rex2 & REX_X)
11834                 vindex += 16;
11835
11836               if (vindex != 4)
11837                 indexes = ins->address_mode == mode_64bit && !addr32flag
11838                           ? att_names64 : att_names32;
11839               break;
11840             }
11841           scale = ins->sib.scale;
11842           base = ins->sib.base;
11843           ins->codep++;
11844         }
11845       else
11846         {
11847           /* Check for mandatory SIB.  */
11848           if (bytemode == vex_vsib_d_w_dq_mode
11849               || bytemode == vex_vsib_q_w_dq_mode
11850               || bytemode == vex_sibmem_mode)
11851             {
11852               oappend (ins, "(bad)");
11853               return true;
11854             }
11855         }
11856       rbase = base + add;
11857
11858       switch (ins->modrm.mod)
11859         {
11860         case 0:
11861           if (base == 5)
11862             {
11863               havebase = 0;
11864               if (ins->address_mode == mode_64bit && !ins->has_sib)
11865                 riprel = 1;
11866               if (!get32s (ins, &disp))
11867                 return false;
11868               if (riprel && bytemode == v_bndmk_mode)
11869                 {
11870                   oappend (ins, "(bad)");
11871                   return true;
11872                 }
11873             }
11874           break;
11875         case 1:
11876           if (!get8s (ins, &disp))
11877             return false;
11878           if (ins->vex.evex && shift > 0)
11879             disp <<= shift;
11880           break;
11881         case 2:
11882           if (!get32s (ins, &disp))
11883             return false;
11884           break;
11885         }
11886
11887       needindex = 0;
11888       needaddr32 = 0;
11889       if (ins->has_sib
11890           && !havebase
11891           && !indexes
11892           && ins->address_mode != mode_16bit)
11893         {
11894           if (ins->address_mode == mode_64bit)
11895             {
11896               if (addr32flag)
11897                 {
11898                   /* Without base nor index registers, zero-extend the
11899                      lower 32-bit displacement to 64 bits.  */
11900                   disp &= 0xffffffff;
11901                   needindex = 1;
11902                 }
11903               needaddr32 = 1;
11904             }
11905           else
11906             {
11907               /* In 32-bit mode, we need index register to tell [offset]
11908                  from [eiz*1 + offset].  */
11909               needindex = 1;
11910             }
11911         }
11912
11913       havedisp = (havebase
11914                   || needindex
11915                   || (ins->has_sib && (indexes || scale != 0)));
11916
11917       if (!ins->intel_syntax)
11918         if (ins->modrm.mod != 0 || base == 5)
11919           {
11920             if (havedisp || riprel)
11921               print_displacement (ins, disp);
11922             else
11923               print_operand_value (ins, disp, dis_style_address_offset);
11924             if (riprel)
11925               {
11926                 set_op (ins, disp, true);
11927                 oappend_char (ins, '(');
11928                 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11929                                     dis_style_register);
11930                 oappend_char (ins, ')');
11931               }
11932           }
11933
11934       if ((havebase || indexes || needindex || needaddr32 || riprel)
11935           && (ins->address_mode != mode_64bit
11936               || ((bytemode != v_bnd_mode)
11937                   && (bytemode != v_bndmk_mode)
11938                   && (bytemode != bnd_mode)
11939                   && (bytemode != bnd_swap_mode))))
11940         ins->used_prefixes |= PREFIX_ADDR;
11941
11942       if (havedisp || (ins->intel_syntax && riprel))
11943         {
11944           oappend_char (ins, ins->open_char);
11945           if (ins->intel_syntax && riprel)
11946             {
11947               set_op (ins, disp, true);
11948               oappend_with_style (ins, !addr32flag ? "rip" : "eip",
11949                                   dis_style_register);
11950             }
11951           if (havebase)
11952             oappend_register
11953               (ins,
11954                (ins->address_mode == mode_64bit && !addr32flag
11955                 ? att_names64 : att_names32)[rbase]);
11956           if (ins->has_sib)
11957             {
11958               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11959                  print index to tell base + index from base.  */
11960               if (scale != 0
11961                   || needindex
11962                   || indexes
11963                   || (havebase && base != ESP_REG_NUM))
11964                 {
11965                   if (!ins->intel_syntax || havebase)
11966                     oappend_char (ins, ins->separator_char);
11967                   if (indexes)
11968                     {
11969                       if (ins->address_mode == mode_64bit || vindex < 16)
11970                         oappend_register (ins, indexes[vindex]);
11971                       else
11972                         oappend (ins, "(bad)");
11973                     }
11974                   else
11975                     oappend_register (ins,
11976                                       ins->address_mode == mode_64bit
11977                                       && !addr32flag
11978                                       ? att_index64
11979                                       : att_index32);
11980
11981                   oappend_char (ins, ins->scale_char);
11982                   oappend_char_with_style (ins, '0' + (1 << scale),
11983                                            dis_style_immediate);
11984                 }
11985             }
11986           if (ins->intel_syntax
11987               && (disp || ins->modrm.mod != 0 || base == 5))
11988             {
11989               if (!havedisp || (bfd_signed_vma) disp >= 0)
11990                   oappend_char (ins, '+');
11991               if (havedisp)
11992                 print_displacement (ins, disp);
11993               else
11994                 print_operand_value (ins, disp, dis_style_address_offset);
11995             }
11996
11997           oappend_char (ins, ins->close_char);
11998
11999           if (check_gather)
12000             {
12001               /* Both XMM/YMM/ZMM registers must be distinct.  */
12002               int modrm_reg = ins->modrm.reg;
12003
12004               if (ins->rex & REX_R)
12005                 modrm_reg += 8;
12006               if (ins->rex2 & REX_R)
12007                 modrm_reg += 16;
12008               if (vindex == modrm_reg)
12009                 oappend (ins, "/(bad)");
12010             }
12011         }
12012       else if (ins->intel_syntax)
12013         {
12014           if (ins->modrm.mod != 0 || base == 5)
12015             {
12016               if (!ins->active_seg_prefix)
12017                 {
12018                   oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12019                   oappend (ins, ":");
12020                 }
12021               print_operand_value (ins, disp, dis_style_text);
12022             }
12023         }
12024     }
12025   else if (bytemode == v_bnd_mode
12026            || bytemode == v_bndmk_mode
12027            || bytemode == bnd_mode
12028            || bytemode == bnd_swap_mode
12029            || bytemode == vex_vsib_d_w_dq_mode
12030            || bytemode == vex_vsib_q_w_dq_mode)
12031     {
12032       oappend (ins, "(bad)");
12033       return true;
12034     }
12035   else
12036     {
12037       /* 16 bit address mode */
12038       bfd_vma disp = 0;
12039
12040       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12041       switch (ins->modrm.mod)
12042         {
12043         case 0:
12044           if (ins->modrm.rm == 6)
12045             {
12046         case 2:
12047               if (!get16s (ins, &disp))
12048                 return false;
12049             }
12050           break;
12051         case 1:
12052           if (!get8s (ins, &disp))
12053             return false;
12054           if (ins->vex.evex && shift > 0)
12055             disp <<= shift;
12056           break;
12057         }
12058
12059       if (!ins->intel_syntax)
12060         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12061           print_displacement (ins, disp);
12062
12063       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12064         {
12065           oappend_char (ins, ins->open_char);
12066           oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12067                                           : att_index16[ins->modrm.rm]);
12068           if (ins->intel_syntax
12069               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12070             {
12071               if ((bfd_signed_vma) disp >= 0)
12072                 oappend_char (ins, '+');
12073               print_displacement (ins, disp);
12074             }
12075
12076           oappend_char (ins, ins->close_char);
12077         }
12078       else if (ins->intel_syntax)
12079         {
12080           if (!ins->active_seg_prefix)
12081             {
12082               oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12083               oappend (ins, ":");
12084             }
12085           print_operand_value (ins, disp & 0xffff, dis_style_text);
12086         }
12087     }
12088   if (ins->vex.b && ins->evex_type == evex_default)
12089     {
12090       ins->evex_used |= EVEX_b_used;
12091
12092       /* Broadcast can only ever be valid for memory sources.  */
12093       if (ins->obufp == ins->op_out[0])
12094         ins->vex.no_broadcast = true;
12095
12096       if (!ins->vex.no_broadcast
12097           && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12098         {
12099           if (bytemode == xh_mode)
12100             {
12101               switch (ins->vex.length)
12102                 {
12103                 case 128:
12104                   oappend (ins, "{1to8}");
12105                   break;
12106                 case 256:
12107                   oappend (ins, "{1to16}");
12108                   break;
12109                 case 512:
12110                   oappend (ins, "{1to32}");
12111                   break;
12112                 default:
12113                   abort ();
12114                 }
12115             }
12116           else if (bytemode == q_mode
12117                    || bytemode == ymmq_mode)
12118             ins->vex.no_broadcast = true;
12119           else if (ins->vex.w
12120                    || bytemode == evex_half_bcst_xmmqdh_mode
12121                    || bytemode == evex_half_bcst_xmmq_mode)
12122             {
12123               switch (ins->vex.length)
12124                 {
12125                 case 128:
12126                   oappend (ins, "{1to2}");
12127                   break;
12128                 case 256:
12129                   oappend (ins, "{1to4}");
12130                   break;
12131                 case 512:
12132                   oappend (ins, "{1to8}");
12133                   break;
12134                 default:
12135                   abort ();
12136                 }
12137             }
12138           else if (bytemode == x_mode
12139                    || bytemode == evex_half_bcst_xmmqh_mode)
12140             {
12141               switch (ins->vex.length)
12142                 {
12143                 case 128:
12144                   oappend (ins, "{1to4}");
12145                   break;
12146                 case 256:
12147                   oappend (ins, "{1to8}");
12148                   break;
12149                 case 512:
12150                   oappend (ins, "{1to16}");
12151                   break;
12152                 default:
12153                   abort ();
12154                 }
12155             }
12156           else
12157             ins->vex.no_broadcast = true;
12158         }
12159       if (ins->vex.no_broadcast)
12160         oappend (ins, "{bad}");
12161     }
12162
12163   return true;
12164 }
12165
12166 static bool
12167 OP_E (instr_info *ins, int bytemode, int sizeflag)
12168 {
12169   /* Skip mod/rm byte.  */
12170   MODRM_CHECK;
12171   if (!ins->has_skipped_modrm)
12172     {
12173       ins->codep++;
12174       ins->has_skipped_modrm = true;
12175     }
12176
12177   if (ins->modrm.mod == 3)
12178     {
12179       if ((sizeflag & SUFFIX_ALWAYS)
12180           && (bytemode == b_swap_mode
12181               || bytemode == bnd_swap_mode
12182               || bytemode == v_swap_mode))
12183         swap_operand (ins);
12184
12185       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12186       return true;
12187     }
12188
12189   /* Masking is invalid for insns with GPR-like memory destination. Set the
12190      flag uniformly, as the consumer will inspect it only for the destination
12191      operand.  */
12192   if (ins->vex.mask_register_specifier)
12193     ins->illegal_masking = true;
12194
12195   return OP_E_memory (ins, bytemode, sizeflag);
12196 }
12197
12198 static bool
12199 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12200 {
12201   if (ins->modrm.mod == 3 && bytemode == f_mode)
12202     /* bad lcall/ljmp */
12203     return BadOp (ins);
12204   if (!ins->intel_syntax)
12205     oappend (ins, "*");
12206   return OP_E (ins, bytemode, sizeflag);
12207 }
12208
12209 static bool
12210 OP_G (instr_info *ins, int bytemode, int sizeflag)
12211 {
12212   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12213   return true;
12214 }
12215
12216 static bool
12217 OP_REG (instr_info *ins, int code, int sizeflag)
12218 {
12219   const char *s;
12220   int add = 0;
12221
12222   switch (code)
12223     {
12224     case es_reg: case ss_reg: case cs_reg:
12225     case ds_reg: case fs_reg: case gs_reg:
12226       oappend_register (ins, att_names_seg[code - es_reg]);
12227       return true;
12228     }
12229
12230   USED_REX (REX_B);
12231   if (ins->rex & REX_B)
12232     add = 8;
12233   if (ins->rex2 & REX_B)
12234     add += 16;
12235
12236   switch (code)
12237     {
12238     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12239     case sp_reg: case bp_reg: case si_reg: case di_reg:
12240       s = att_names16[code - ax_reg + add];
12241       break;
12242     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12243       USED_REX (0);
12244       /* Fall through.  */
12245     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12246       if (ins->rex)
12247         s = att_names8rex[code - al_reg + add];
12248       else
12249         s = att_names8[code - al_reg];
12250       break;
12251     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12252     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12253       if (ins->address_mode == mode_64bit
12254           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12255         {
12256           s = att_names64[code - rAX_reg + add];
12257           break;
12258         }
12259       code += eAX_reg - rAX_reg;
12260       /* Fall through.  */
12261     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12262     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12263       USED_REX (REX_W);
12264       if (ins->rex & REX_W)
12265         s = att_names64[code - eAX_reg + add];
12266       else
12267         {
12268           if (sizeflag & DFLAG)
12269             s = att_names32[code - eAX_reg + add];
12270           else
12271             s = att_names16[code - eAX_reg + add];
12272           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12273         }
12274       break;
12275     default:
12276       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12277       return true;
12278     }
12279   oappend_register (ins, s);
12280   return true;
12281 }
12282
12283 static bool
12284 OP_IMREG (instr_info *ins, int code, int sizeflag)
12285 {
12286   const char *s;
12287
12288   switch (code)
12289     {
12290     case indir_dx_reg:
12291       if (!ins->intel_syntax)
12292         {
12293           oappend (ins, "(%dx)");
12294           return true;
12295         }
12296       s = att_names16[dx_reg - ax_reg];
12297       break;
12298     case al_reg: case cl_reg:
12299       s = att_names8[code - al_reg];
12300       break;
12301     case eAX_reg:
12302       USED_REX (REX_W);
12303       if (ins->rex & REX_W)
12304         {
12305           s = *att_names64;
12306           break;
12307         }
12308       /* Fall through.  */
12309     case z_mode_ax_reg:
12310       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12311         s = *att_names32;
12312       else
12313         s = *att_names16;
12314       if (!(ins->rex & REX_W))
12315         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12316       break;
12317     default:
12318       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12319       return true;
12320     }
12321   oappend_register (ins, s);
12322   return true;
12323 }
12324
12325 static bool
12326 OP_I (instr_info *ins, int bytemode, int sizeflag)
12327 {
12328   bfd_vma op;
12329
12330   switch (bytemode)
12331     {
12332     case b_mode:
12333       if (!fetch_code (ins->info, ins->codep + 1))
12334         return false;
12335       op = *ins->codep++;
12336       break;
12337     case v_mode:
12338       USED_REX (REX_W);
12339       if (ins->rex & REX_W)
12340         {
12341           if (!get32s (ins, &op))
12342             return false;
12343         }
12344       else
12345         {
12346           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12347           if (sizeflag & DFLAG)
12348             {
12349     case d_mode:
12350               if (!get32 (ins, &op))
12351                 return false;
12352             }
12353           else
12354             {
12355               /* Fall through.  */
12356     case w_mode:
12357               if (!get16 (ins, &op))
12358                 return false;
12359             }
12360         }
12361       break;
12362     case const_1_mode:
12363       if (ins->intel_syntax)
12364         oappend (ins, "1");
12365       else
12366         oappend (ins, "$1");
12367       return true;
12368     default:
12369       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12370       return true;
12371     }
12372
12373   oappend_immediate (ins, op);
12374   return true;
12375 }
12376
12377 static bool
12378 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12379 {
12380   uint64_t op;
12381
12382   if (bytemode != v_mode || ins->address_mode != mode_64bit
12383       || !(ins->rex & REX_W))
12384     return OP_I (ins, bytemode, sizeflag);
12385
12386   USED_REX (REX_W);
12387
12388   if (!get64 (ins, &op))
12389     return false;
12390
12391   oappend_immediate (ins, op);
12392   return true;
12393 }
12394
12395 static bool
12396 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12397 {
12398   bfd_vma op;
12399
12400   switch (bytemode)
12401     {
12402     case b_mode:
12403     case b_T_mode:
12404       if (!get8s (ins, &op))
12405         return false;
12406       if (bytemode == b_T_mode)
12407         {
12408           if (ins->address_mode != mode_64bit
12409               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12410             {
12411               /* The operand-size prefix is overridden by a REX prefix.  */
12412               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12413                 op &= 0xffffffff;
12414               else
12415                 op &= 0xffff;
12416           }
12417         }
12418       else
12419         {
12420           if (!(ins->rex & REX_W))
12421             {
12422               if (sizeflag & DFLAG)
12423                 op &= 0xffffffff;
12424               else
12425                 op &= 0xffff;
12426             }
12427         }
12428       break;
12429     case v_mode:
12430       /* The operand-size prefix is overridden by a REX prefix.  */
12431       if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12432         {
12433           if (!get16 (ins, &op))
12434             return false;
12435         }
12436       else if (!get32s (ins, &op))
12437         return false;
12438       break;
12439     default:
12440       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12441       return true;
12442     }
12443
12444   oappend_immediate (ins, op);
12445   return true;
12446 }
12447
12448 static bool
12449 OP_J (instr_info *ins, int bytemode, int sizeflag)
12450 {
12451   bfd_vma disp;
12452   bfd_vma mask = -1;
12453   bfd_vma segment = 0;
12454
12455   switch (bytemode)
12456     {
12457     case b_mode:
12458       if (!get8s (ins, &disp))
12459         return false;
12460       break;
12461     case v_mode:
12462     case dqw_mode:
12463       if ((sizeflag & DFLAG)
12464           || (ins->address_mode == mode_64bit
12465               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12466                   || (ins->rex & REX_W))))
12467         {
12468           if (!get32s (ins, &disp))
12469             return false;
12470         }
12471       else
12472         {
12473           if (!get16s (ins, &disp))
12474             return false;
12475           /* In 16bit mode, address is wrapped around at 64k within
12476              the same segment.  Otherwise, a data16 prefix on a jump
12477              instruction means that the pc is masked to 16 bits after
12478              the displacement is added!  */
12479           mask = 0xffff;
12480           if ((ins->prefixes & PREFIX_DATA) == 0)
12481             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12482                        & ~((bfd_vma) 0xffff));
12483         }
12484       if (ins->address_mode != mode_64bit
12485           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12486         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12487       break;
12488     default:
12489       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12490       return true;
12491     }
12492   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12493          | segment;
12494   set_op (ins, disp, false);
12495   print_operand_value (ins, disp, dis_style_text);
12496   return true;
12497 }
12498
12499 static bool
12500 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12501 {
12502   if (bytemode == w_mode)
12503     {
12504       oappend_register (ins, att_names_seg[ins->modrm.reg]);
12505       return true;
12506     }
12507   return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12508 }
12509
12510 static bool
12511 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12512 {
12513   bfd_vma seg, offset;
12514   int res;
12515   char scratch[24];
12516
12517   if (sizeflag & DFLAG)
12518     {
12519       if (!get32 (ins, &offset))
12520         return false;;
12521     }
12522   else if (!get16 (ins, &offset))
12523     return false;
12524   if (!get16 (ins, &seg))
12525     return false;;
12526   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12527
12528   res = snprintf (scratch, ARRAY_SIZE (scratch),
12529                   ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12530                   (unsigned) seg, (unsigned) offset);
12531   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12532     abort ();
12533   oappend (ins, scratch);
12534   return true;
12535 }
12536
12537 static bool
12538 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12539 {
12540   bfd_vma off;
12541
12542   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12543     intel_operand_size (ins, bytemode, sizeflag);
12544   append_seg (ins);
12545
12546   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12547     {
12548       if (!get32 (ins, &off))
12549         return false;
12550     }
12551   else
12552     {
12553       if (!get16 (ins, &off))
12554         return false;
12555     }
12556
12557   if (ins->intel_syntax)
12558     {
12559       if (!ins->active_seg_prefix)
12560         {
12561           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12562           oappend (ins, ":");
12563         }
12564     }
12565   print_operand_value (ins, off, dis_style_address_offset);
12566   return true;
12567 }
12568
12569 static bool
12570 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12571 {
12572   uint64_t off;
12573
12574   if (ins->address_mode != mode_64bit
12575       || (ins->prefixes & PREFIX_ADDR))
12576     return OP_OFF (ins, bytemode, sizeflag);
12577
12578   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12579     intel_operand_size (ins, bytemode, sizeflag);
12580   append_seg (ins);
12581
12582   if (!get64 (ins, &off))
12583     return false;
12584
12585   if (ins->intel_syntax)
12586     {
12587       if (!ins->active_seg_prefix)
12588         {
12589           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12590           oappend (ins, ":");
12591         }
12592     }
12593   print_operand_value (ins, off, dis_style_address_offset);
12594   return true;
12595 }
12596
12597 static void
12598 ptr_reg (instr_info *ins, int code, int sizeflag)
12599 {
12600   const char *s;
12601
12602   *ins->obufp++ = ins->open_char;
12603   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12604   if (ins->address_mode == mode_64bit)
12605     {
12606       if (!(sizeflag & AFLAG))
12607         s = att_names32[code - eAX_reg];
12608       else
12609         s = att_names64[code - eAX_reg];
12610     }
12611   else if (sizeflag & AFLAG)
12612     s = att_names32[code - eAX_reg];
12613   else
12614     s = att_names16[code - eAX_reg];
12615   oappend_register (ins, s);
12616   oappend_char (ins, ins->close_char);
12617 }
12618
12619 static bool
12620 OP_ESreg (instr_info *ins, int code, int sizeflag)
12621 {
12622   if (ins->intel_syntax)
12623     {
12624       switch (ins->codep[-1])
12625         {
12626         case 0x6d:      /* insw/insl */
12627           intel_operand_size (ins, z_mode, sizeflag);
12628           break;
12629         case 0xa5:      /* movsw/movsl/movsq */
12630         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12631         case 0xab:      /* stosw/stosl */
12632         case 0xaf:      /* scasw/scasl */
12633           intel_operand_size (ins, v_mode, sizeflag);
12634           break;
12635         default:
12636           intel_operand_size (ins, b_mode, sizeflag);
12637         }
12638     }
12639   oappend_register (ins, att_names_seg[0]);
12640   oappend_char (ins, ':');
12641   ptr_reg (ins, code, sizeflag);
12642   return true;
12643 }
12644
12645 static bool
12646 OP_DSreg (instr_info *ins, int code, int sizeflag)
12647 {
12648   if (ins->intel_syntax)
12649     {
12650       switch (ins->codep[-1])
12651         {
12652         case 0x6f:      /* outsw/outsl */
12653           intel_operand_size (ins, z_mode, sizeflag);
12654           break;
12655         case 0xa5:      /* movsw/movsl/movsq */
12656         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12657         case 0xad:      /* lodsw/lodsl/lodsq */
12658           intel_operand_size (ins, v_mode, sizeflag);
12659           break;
12660         default:
12661           intel_operand_size (ins, b_mode, sizeflag);
12662         }
12663     }
12664   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12665      default segment register DS is printed.  */
12666   if (!ins->active_seg_prefix)
12667     ins->active_seg_prefix = PREFIX_DS;
12668   append_seg (ins);
12669   ptr_reg (ins, code, sizeflag);
12670   return true;
12671 }
12672
12673 static bool
12674 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12675       int sizeflag ATTRIBUTE_UNUSED)
12676 {
12677   int add, res;
12678   char scratch[8];
12679
12680   if (ins->rex & REX_R)
12681     {
12682       USED_REX (REX_R);
12683       add = 8;
12684     }
12685   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12686     {
12687       ins->all_prefixes[ins->last_lock_prefix] = 0;
12688       ins->used_prefixes |= PREFIX_LOCK;
12689       add = 8;
12690     }
12691   else
12692     add = 0;
12693   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12694                   ins->modrm.reg + add);
12695   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12696     abort ();
12697   oappend_register (ins, scratch);
12698   return true;
12699 }
12700
12701 static bool
12702 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12703       int sizeflag ATTRIBUTE_UNUSED)
12704 {
12705   int add, res;
12706   char scratch[8];
12707
12708   USED_REX (REX_R);
12709   if (ins->rex & REX_R)
12710     add = 8;
12711   else
12712     add = 0;
12713   res = snprintf (scratch, ARRAY_SIZE (scratch),
12714                   ins->intel_syntax ? "dr%d" : "%%db%d",
12715                   ins->modrm.reg + add);
12716   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12717     abort ();
12718   oappend (ins, scratch);
12719   return true;
12720 }
12721
12722 static bool
12723 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12724       int sizeflag ATTRIBUTE_UNUSED)
12725 {
12726   int res;
12727   char scratch[8];
12728
12729   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12730   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12731     abort ();
12732   oappend_register (ins, scratch);
12733   return true;
12734 }
12735
12736 static bool
12737 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12738         int sizeflag ATTRIBUTE_UNUSED)
12739 {
12740   int reg = ins->modrm.reg;
12741   const char (*names)[8];
12742
12743   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12744   if (ins->prefixes & PREFIX_DATA)
12745     {
12746       names = att_names_xmm;
12747       USED_REX (REX_R);
12748       if (ins->rex & REX_R)
12749         reg += 8;
12750     }
12751   else
12752     names = att_names_mm;
12753   oappend_register (ins, names[reg]);
12754   return true;
12755 }
12756
12757 static void
12758 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12759 {
12760   const char (*names)[8];
12761
12762   if (bytemode == xmmq_mode
12763       || bytemode == evex_half_bcst_xmmqh_mode
12764       || bytemode == evex_half_bcst_xmmq_mode)
12765     {
12766       switch (ins->vex.length)
12767         {
12768         case 0:
12769         case 128:
12770         case 256:
12771           names = att_names_xmm;
12772           break;
12773         case 512:
12774           names = att_names_ymm;
12775           ins->evex_used |= EVEX_len_used;
12776           break;
12777         default:
12778           abort ();
12779         }
12780     }
12781   else if (bytemode == ymm_mode)
12782     names = att_names_ymm;
12783   else if (bytemode == tmm_mode)
12784     {
12785       if (reg >= 8)
12786         {
12787           oappend (ins, "(bad)");
12788           return;
12789         }
12790       names = att_names_tmm;
12791     }
12792   else if (ins->need_vex
12793            && bytemode != xmm_mode
12794            && bytemode != scalar_mode
12795            && bytemode != xmmdw_mode
12796            && bytemode != xmmqd_mode
12797            && bytemode != evex_half_bcst_xmmqdh_mode
12798            && bytemode != w_swap_mode
12799            && bytemode != b_mode
12800            && bytemode != w_mode
12801            && bytemode != d_mode
12802            && bytemode != q_mode)
12803     {
12804       ins->evex_used |= EVEX_len_used;
12805       switch (ins->vex.length)
12806         {
12807         case 128:
12808           names = att_names_xmm;
12809           break;
12810         case 256:
12811           if (ins->vex.w
12812               || bytemode != vex_vsib_q_w_dq_mode)
12813             names = att_names_ymm;
12814           else
12815             names = att_names_xmm;
12816           break;
12817         case 512:
12818           if (ins->vex.w
12819               || bytemode != vex_vsib_q_w_dq_mode)
12820             names = att_names_zmm;
12821           else
12822             names = att_names_ymm;
12823           break;
12824         default:
12825           abort ();
12826         }
12827     }
12828   else
12829     names = att_names_xmm;
12830   oappend_register (ins, names[reg]);
12831
12832   /* Legacy insns promoted to EVEX, like the legacy insns themselves, don't
12833      allow use of the upper 16 vector registers.  */
12834   if (ins->evex_type == evex_from_legacy && reg >= 16)
12835     oappend (ins, "(bad)");
12836 }
12837
12838 static bool
12839 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12840 {
12841   unsigned int reg = ins->modrm.reg;
12842
12843   USED_REX (REX_R);
12844   if (ins->rex & REX_R)
12845     reg += 8;
12846   if (ins->vex.evex)
12847     {
12848       if (ins->rex2 & REX_R)
12849         reg += 16;
12850     }
12851
12852   if (bytemode == tmm_mode)
12853     ins->modrm.reg = reg;
12854   else if (bytemode == scalar_mode)
12855     ins->vex.no_broadcast = true;
12856
12857   print_vector_reg (ins, reg, bytemode);
12858   return true;
12859 }
12860
12861 static bool
12862 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12863 {
12864   int reg;
12865   const char (*names)[8];
12866
12867   if (ins->modrm.mod != 3)
12868     {
12869       if (ins->intel_syntax
12870           && (bytemode == v_mode || bytemode == v_swap_mode))
12871         {
12872           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12873           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12874         }
12875       return OP_E (ins, bytemode, sizeflag);
12876     }
12877
12878   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12879     swap_operand (ins);
12880
12881   /* Skip mod/rm byte.  */
12882   MODRM_CHECK;
12883   ins->codep++;
12884   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12885   reg = ins->modrm.rm;
12886   if (ins->prefixes & PREFIX_DATA)
12887     {
12888       names = att_names_xmm;
12889       USED_REX (REX_B);
12890       if (ins->rex & REX_B)
12891         reg += 8;
12892     }
12893   else
12894     names = att_names_mm;
12895   oappend_register (ins, names[reg]);
12896   return true;
12897 }
12898
12899 /* cvt* are the only instructions in sse2 which have
12900    both SSE and MMX operands and also have 0x66 prefix
12901    in their opcode. 0x66 was originally used to differentiate
12902    between SSE and MMX instruction(operands). So we have to handle the
12903    cvt* separately using OP_EMC and OP_MXC */
12904 static bool
12905 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12906 {
12907   if (ins->modrm.mod != 3)
12908     {
12909       if (ins->intel_syntax && bytemode == v_mode)
12910         {
12911           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12912           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12913         }
12914       return OP_E (ins, bytemode, sizeflag);
12915     }
12916
12917   /* Skip mod/rm byte.  */
12918   MODRM_CHECK;
12919   ins->codep++;
12920   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12921   oappend_register (ins, att_names_mm[ins->modrm.rm]);
12922   return true;
12923 }
12924
12925 static bool
12926 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12927         int sizeflag ATTRIBUTE_UNUSED)
12928 {
12929   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12930   oappend_register (ins, att_names_mm[ins->modrm.reg]);
12931   return true;
12932 }
12933
12934 static bool
12935 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12936 {
12937   int reg;
12938
12939   /* Skip mod/rm byte.  */
12940   MODRM_CHECK;
12941   ins->codep++;
12942
12943   if (bytemode == dq_mode)
12944     bytemode = ins->vex.w ? q_mode : d_mode;
12945
12946   if (ins->modrm.mod != 3)
12947     return OP_E_memory (ins, bytemode, sizeflag);
12948
12949   reg = ins->modrm.rm;
12950   USED_REX (REX_B);
12951   if (ins->rex & REX_B)
12952     reg += 8;
12953   if (ins->rex2 & REX_B)
12954     reg += 16;
12955   if (ins->vex.evex)
12956     {
12957       USED_REX (REX_X);
12958       if ((ins->rex & REX_X))
12959         reg += 16;
12960     }
12961
12962   if ((sizeflag & SUFFIX_ALWAYS)
12963       && (bytemode == x_swap_mode
12964           || bytemode == w_swap_mode
12965           || bytemode == d_swap_mode
12966           || bytemode == q_swap_mode))
12967     swap_operand (ins);
12968
12969   if (bytemode == tmm_mode)
12970     ins->modrm.rm = reg;
12971
12972   print_vector_reg (ins, reg, bytemode);
12973   return true;
12974 }
12975
12976 static bool
12977 OP_R (instr_info *ins, int bytemode, int sizeflag)
12978 {
12979   if (ins->modrm.mod != 3)
12980     return BadOp (ins);
12981
12982   switch (bytemode)
12983     {
12984     case d_mode:
12985     case dq_mode:
12986     case q_mode:
12987     case mask_mode:
12988       return OP_E (ins, bytemode, sizeflag);
12989     case q_mm_mode:
12990       return OP_EM (ins, x_mode, sizeflag);
12991     case xmm_mode:
12992       if (ins->vex.length <= 128)
12993         break;
12994       return BadOp (ins);
12995     }
12996
12997   return OP_EX (ins, bytemode, sizeflag);
12998 }
12999
13000 static bool
13001 OP_M (instr_info *ins, int bytemode, int sizeflag)
13002 {
13003   /* Skip mod/rm byte.  */
13004   MODRM_CHECK;
13005   ins->codep++;
13006
13007   if (ins->modrm.mod == 3)
13008     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
13009     return BadOp (ins);
13010
13011   if (bytemode == x_mode)
13012     ins->vex.no_broadcast = true;
13013
13014   return OP_E_memory (ins, bytemode, sizeflag);
13015 }
13016
13017 static bool
13018 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
13019 {
13020   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
13021     return BadOp (ins);
13022   return OP_E (ins, bytemode, sizeflag);
13023 }
13024
13025 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13026    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13027
13028 static bool
13029 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13030 {
13031   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13032     {
13033       ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13034       return true;
13035     }
13036   if (opnd == 0)
13037     return OP_REG (ins, eAX_reg, sizeflag);
13038   return OP_IMREG (ins, eAX_reg, sizeflag);
13039 }
13040
13041 static const char *const Suffix3DNow[] = {
13042 /* 00 */        NULL,           NULL,           NULL,           NULL,
13043 /* 04 */        NULL,           NULL,           NULL,           NULL,
13044 /* 08 */        NULL,           NULL,           NULL,           NULL,
13045 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13046 /* 10 */        NULL,           NULL,           NULL,           NULL,
13047 /* 14 */        NULL,           NULL,           NULL,           NULL,
13048 /* 18 */        NULL,           NULL,           NULL,           NULL,
13049 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13050 /* 20 */        NULL,           NULL,           NULL,           NULL,
13051 /* 24 */        NULL,           NULL,           NULL,           NULL,
13052 /* 28 */        NULL,           NULL,           NULL,           NULL,
13053 /* 2C */        NULL,           NULL,           NULL,           NULL,
13054 /* 30 */        NULL,           NULL,           NULL,           NULL,
13055 /* 34 */        NULL,           NULL,           NULL,           NULL,
13056 /* 38 */        NULL,           NULL,           NULL,           NULL,
13057 /* 3C */        NULL,           NULL,           NULL,           NULL,
13058 /* 40 */        NULL,           NULL,           NULL,           NULL,
13059 /* 44 */        NULL,           NULL,           NULL,           NULL,
13060 /* 48 */        NULL,           NULL,           NULL,           NULL,
13061 /* 4C */        NULL,           NULL,           NULL,           NULL,
13062 /* 50 */        NULL,           NULL,           NULL,           NULL,
13063 /* 54 */        NULL,           NULL,           NULL,           NULL,
13064 /* 58 */        NULL,           NULL,           NULL,           NULL,
13065 /* 5C */        NULL,           NULL,           NULL,           NULL,
13066 /* 60 */        NULL,           NULL,           NULL,           NULL,
13067 /* 64 */        NULL,           NULL,           NULL,           NULL,
13068 /* 68 */        NULL,           NULL,           NULL,           NULL,
13069 /* 6C */        NULL,           NULL,           NULL,           NULL,
13070 /* 70 */        NULL,           NULL,           NULL,           NULL,
13071 /* 74 */        NULL,           NULL,           NULL,           NULL,
13072 /* 78 */        NULL,           NULL,           NULL,           NULL,
13073 /* 7C */        NULL,           NULL,           NULL,           NULL,
13074 /* 80 */        NULL,           NULL,           NULL,           NULL,
13075 /* 84 */        NULL,           NULL,           NULL,           NULL,
13076 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13077 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13078 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13079 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13080 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13081 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13082 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13083 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13084 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13085 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13086 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13087 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13088 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13089 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13090 /* C0 */        NULL,           NULL,           NULL,           NULL,
13091 /* C4 */        NULL,           NULL,           NULL,           NULL,
13092 /* C8 */        NULL,           NULL,           NULL,           NULL,
13093 /* CC */        NULL,           NULL,           NULL,           NULL,
13094 /* D0 */        NULL,           NULL,           NULL,           NULL,
13095 /* D4 */        NULL,           NULL,           NULL,           NULL,
13096 /* D8 */        NULL,           NULL,           NULL,           NULL,
13097 /* DC */        NULL,           NULL,           NULL,           NULL,
13098 /* E0 */        NULL,           NULL,           NULL,           NULL,
13099 /* E4 */        NULL,           NULL,           NULL,           NULL,
13100 /* E8 */        NULL,           NULL,           NULL,           NULL,
13101 /* EC */        NULL,           NULL,           NULL,           NULL,
13102 /* F0 */        NULL,           NULL,           NULL,           NULL,
13103 /* F4 */        NULL,           NULL,           NULL,           NULL,
13104 /* F8 */        NULL,           NULL,           NULL,           NULL,
13105 /* FC */        NULL,           NULL,           NULL,           NULL,
13106 };
13107
13108 static bool
13109 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13110                 int sizeflag ATTRIBUTE_UNUSED)
13111 {
13112   const char *mnemonic;
13113
13114   if (!fetch_code (ins->info, ins->codep + 1))
13115     return false;
13116   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13117      place where an 8-bit immediate would normally go.  ie. the last
13118      byte of the instruction.  */
13119   ins->obufp = ins->mnemonicendp;
13120   mnemonic = Suffix3DNow[*ins->codep++];
13121   if (mnemonic)
13122     ins->obufp = stpcpy (ins->obufp, mnemonic);
13123   else
13124     {
13125       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13126          of the opcode (0x0f0f) and the opcode suffix, we need to do
13127          all the ins->modrm processing first, and don't know until now that
13128          we have a bad opcode.  This necessitates some cleaning up.  */
13129       ins->op_out[0][0] = '\0';
13130       ins->op_out[1][0] = '\0';
13131       BadOp (ins);
13132     }
13133   ins->mnemonicendp = ins->obufp;
13134   return true;
13135 }
13136
13137 static const struct op simd_cmp_op[] =
13138 {
13139   { STRING_COMMA_LEN ("eq") },
13140   { STRING_COMMA_LEN ("lt") },
13141   { STRING_COMMA_LEN ("le") },
13142   { STRING_COMMA_LEN ("unord") },
13143   { STRING_COMMA_LEN ("neq") },
13144   { STRING_COMMA_LEN ("nlt") },
13145   { STRING_COMMA_LEN ("nle") },
13146   { STRING_COMMA_LEN ("ord") }
13147 };
13148
13149 static const struct op vex_cmp_op[] =
13150 {
13151   { STRING_COMMA_LEN ("eq_uq") },
13152   { STRING_COMMA_LEN ("nge") },
13153   { STRING_COMMA_LEN ("ngt") },
13154   { STRING_COMMA_LEN ("false") },
13155   { STRING_COMMA_LEN ("neq_oq") },
13156   { STRING_COMMA_LEN ("ge") },
13157   { STRING_COMMA_LEN ("gt") },
13158   { STRING_COMMA_LEN ("true") },
13159   { STRING_COMMA_LEN ("eq_os") },
13160   { STRING_COMMA_LEN ("lt_oq") },
13161   { STRING_COMMA_LEN ("le_oq") },
13162   { STRING_COMMA_LEN ("unord_s") },
13163   { STRING_COMMA_LEN ("neq_us") },
13164   { STRING_COMMA_LEN ("nlt_uq") },
13165   { STRING_COMMA_LEN ("nle_uq") },
13166   { STRING_COMMA_LEN ("ord_s") },
13167   { STRING_COMMA_LEN ("eq_us") },
13168   { STRING_COMMA_LEN ("nge_uq") },
13169   { STRING_COMMA_LEN ("ngt_uq") },
13170   { STRING_COMMA_LEN ("false_os") },
13171   { STRING_COMMA_LEN ("neq_os") },
13172   { STRING_COMMA_LEN ("ge_oq") },
13173   { STRING_COMMA_LEN ("gt_oq") },
13174   { STRING_COMMA_LEN ("true_us") },
13175 };
13176
13177 static bool
13178 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13179            int sizeflag ATTRIBUTE_UNUSED)
13180 {
13181   unsigned int cmp_type;
13182
13183   if (!fetch_code (ins->info, ins->codep + 1))
13184     return false;
13185   cmp_type = *ins->codep++;
13186   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13187     {
13188       char suffix[3];
13189       char *p = ins->mnemonicendp - 2;
13190       suffix[0] = p[0];
13191       suffix[1] = p[1];
13192       suffix[2] = '\0';
13193       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13194       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13195     }
13196   else if (ins->need_vex
13197            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13198     {
13199       char suffix[3];
13200       char *p = ins->mnemonicendp - 2;
13201       suffix[0] = p[0];
13202       suffix[1] = p[1];
13203       suffix[2] = '\0';
13204       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13205       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13206       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13207     }
13208   else
13209     {
13210       /* We have a reserved extension byte.  Output it directly.  */
13211       oappend_immediate (ins, cmp_type);
13212     }
13213   return true;
13214 }
13215
13216 static bool
13217 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13218 {
13219   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13220   if (!ins->intel_syntax)
13221     {
13222       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13223       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13224       if (bytemode == eBX_reg)
13225         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13226       ins->two_source_ops = true;
13227     }
13228   /* Skip mod/rm byte.  */
13229   MODRM_CHECK;
13230   ins->codep++;
13231   return true;
13232 }
13233
13234 static bool
13235 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13236             int sizeflag ATTRIBUTE_UNUSED)
13237 {
13238   /* monitor %{e,r,}ax,%ecx,%edx"  */
13239   if (!ins->intel_syntax)
13240     {
13241       const char (*names)[8] = (ins->address_mode == mode_64bit
13242                                 ? att_names64 : att_names32);
13243
13244       if (ins->prefixes & PREFIX_ADDR)
13245         {
13246           /* Remove "addr16/addr32".  */
13247           ins->all_prefixes[ins->last_addr_prefix] = 0;
13248           names = (ins->address_mode != mode_32bit
13249                    ? att_names32 : att_names16);
13250           ins->used_prefixes |= PREFIX_ADDR;
13251         }
13252       else if (ins->address_mode == mode_16bit)
13253         names = att_names16;
13254       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13255       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13256       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13257       ins->two_source_ops = true;
13258     }
13259   /* Skip mod/rm byte.  */
13260   MODRM_CHECK;
13261   ins->codep++;
13262   return true;
13263 }
13264
13265 static bool
13266 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13267 {
13268   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13269      lods and stos.  */
13270   if (ins->prefixes & PREFIX_REPZ)
13271     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13272
13273   switch (bytemode)
13274     {
13275     case al_reg:
13276     case eAX_reg:
13277     case indir_dx_reg:
13278       return OP_IMREG (ins, bytemode, sizeflag);
13279     case eDI_reg:
13280       return OP_ESreg (ins, bytemode, sizeflag);
13281     case eSI_reg:
13282       return OP_DSreg (ins, bytemode, sizeflag);
13283     default:
13284       abort ();
13285       break;
13286     }
13287   return true;
13288 }
13289
13290 static bool
13291 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13292            int sizeflag ATTRIBUTE_UNUSED)
13293 {
13294   if (ins->isa64 != amd64)
13295     return true;
13296
13297   ins->obufp = ins->obuf;
13298   BadOp (ins);
13299   ins->mnemonicendp = ins->obufp;
13300   ++ins->codep;
13301   return true;
13302 }
13303
13304 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13305    "bnd".  */
13306
13307 static bool
13308 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13309            int sizeflag ATTRIBUTE_UNUSED)
13310 {
13311   if (ins->prefixes & PREFIX_REPNZ)
13312     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13313   return true;
13314 }
13315
13316 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13317    "notrack".  */
13318
13319 static bool
13320 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13321                int sizeflag ATTRIBUTE_UNUSED)
13322 {
13323   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13324      we've seen a PREFIX_DS.  */
13325   if ((ins->prefixes & PREFIX_DS) != 0
13326       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13327     {
13328       /* NOTRACK prefix is only valid on indirect branch instructions.
13329          NB: DATA prefix is unsupported for Intel64.  */
13330       ins->active_seg_prefix = 0;
13331       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13332     }
13333   return true;
13334 }
13335
13336 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13337    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13338  */
13339
13340 static bool
13341 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13342 {
13343   if (ins->modrm.mod != 3
13344       && (ins->prefixes & PREFIX_LOCK) != 0)
13345     {
13346       if (ins->prefixes & PREFIX_REPZ)
13347         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13348       if (ins->prefixes & PREFIX_REPNZ)
13349         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13350     }
13351
13352   return OP_E (ins, bytemode, sizeflag);
13353 }
13354
13355 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13356    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13357  */
13358
13359 static bool
13360 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13361 {
13362   if (ins->modrm.mod != 3)
13363     {
13364       if (ins->prefixes & PREFIX_REPZ)
13365         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13366       if (ins->prefixes & PREFIX_REPNZ)
13367         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13368     }
13369
13370   return OP_E (ins, bytemode, sizeflag);
13371 }
13372
13373 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13374    "xrelease" for memory operand.  No check for LOCK prefix.   */
13375
13376 static bool
13377 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13378 {
13379   if (ins->modrm.mod != 3
13380       && ins->last_repz_prefix > ins->last_repnz_prefix
13381       && (ins->prefixes & PREFIX_REPZ) != 0)
13382     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13383
13384   return OP_E (ins, bytemode, sizeflag);
13385 }
13386
13387 static bool
13388 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13389 {
13390   USED_REX (REX_W);
13391   if (ins->rex & REX_W)
13392     {
13393       /* Change cmpxchg8b to cmpxchg16b.  */
13394       char *p = ins->mnemonicendp - 2;
13395       ins->mnemonicendp = stpcpy (p, "16b");
13396       bytemode = o_mode;
13397     }
13398   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13399     {
13400       if (ins->prefixes & PREFIX_REPZ)
13401         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13402       if (ins->prefixes & PREFIX_REPNZ)
13403         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13404     }
13405
13406   return OP_M (ins, bytemode, sizeflag);
13407 }
13408
13409 static bool
13410 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13411 {
13412   const char (*names)[8] = att_names_xmm;
13413
13414   if (ins->need_vex)
13415     {
13416       switch (ins->vex.length)
13417         {
13418         case 128:
13419           break;
13420         case 256:
13421           names = att_names_ymm;
13422           break;
13423         default:
13424           abort ();
13425         }
13426     }
13427   oappend_register (ins, names[reg]);
13428   return true;
13429 }
13430
13431 static bool
13432 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13433 {
13434   /* Add proper suffix to "fxsave" and "fxrstor".  */
13435   USED_REX (REX_W);
13436   if (ins->rex & REX_W)
13437     {
13438       char *p = ins->mnemonicendp;
13439       *p++ = '6';
13440       *p++ = '4';
13441       *p = '\0';
13442       ins->mnemonicendp = p;
13443     }
13444   return OP_M (ins, bytemode, sizeflag);
13445 }
13446
13447 /* Display the destination register operand for instructions with
13448    VEX. */
13449
13450 static bool
13451 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13452 {
13453   int reg, modrm_reg, sib_index = -1;
13454   const char (*names)[8];
13455
13456   if (!ins->need_vex)
13457     return true;
13458
13459   if (ins->evex_type == evex_from_legacy)
13460     {
13461       ins->evex_used |= EVEX_b_used;
13462       if (!ins->vex.nd)
13463         return true;
13464     }
13465
13466   reg = ins->vex.register_specifier;
13467   ins->vex.register_specifier = 0;
13468   if (ins->address_mode != mode_64bit)
13469     {
13470       if (ins->vex.evex && !ins->vex.v)
13471         {
13472           oappend (ins, "(bad)");
13473           return true;
13474         }
13475
13476       reg &= 7;
13477     }
13478   else if (ins->vex.evex && !ins->vex.v)
13479     reg += 16;
13480
13481   switch (bytemode)
13482     {
13483     case scalar_mode:
13484       oappend_register (ins, att_names_xmm[reg]);
13485       return true;
13486
13487     case vex_vsib_d_w_dq_mode:
13488     case vex_vsib_q_w_dq_mode:
13489       /* This must be the 3rd operand.  */
13490       if (ins->obufp != ins->op_out[2])
13491         abort ();
13492       if (ins->vex.length == 128
13493           || (bytemode != vex_vsib_d_w_dq_mode
13494               && !ins->vex.w))
13495         oappend_register (ins, att_names_xmm[reg]);
13496       else
13497         oappend_register (ins, att_names_ymm[reg]);
13498
13499       /* All 3 XMM/YMM registers must be distinct.  */
13500       modrm_reg = ins->modrm.reg;
13501       if (ins->rex & REX_R)
13502         modrm_reg += 8;
13503
13504       if (ins->has_sib && ins->modrm.rm == 4)
13505         {
13506           sib_index = ins->sib.index;
13507           if (ins->rex & REX_X)
13508             sib_index += 8;
13509         }
13510
13511       if (reg == modrm_reg || reg == sib_index)
13512         strcpy (ins->obufp, "/(bad)");
13513       if (modrm_reg == sib_index || modrm_reg == reg)
13514         strcat (ins->op_out[0], "/(bad)");
13515       if (sib_index == modrm_reg || sib_index == reg)
13516         strcat (ins->op_out[1], "/(bad)");
13517
13518       return true;
13519
13520     case tmm_mode:
13521       /* All 3 TMM registers must be distinct.  */
13522       if (reg >= 8)
13523         oappend (ins, "(bad)");
13524       else
13525         {
13526           /* This must be the 3rd operand.  */
13527           if (ins->obufp != ins->op_out[2])
13528             abort ();
13529           oappend_register (ins, att_names_tmm[reg]);
13530           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13531             strcpy (ins->obufp, "/(bad)");
13532         }
13533
13534       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13535           || ins->modrm.rm == reg)
13536         {
13537           if (ins->modrm.reg <= 8
13538               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13539             strcat (ins->op_out[0], "/(bad)");
13540           if (ins->modrm.rm <= 8
13541               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13542             strcat (ins->op_out[1], "/(bad)");
13543         }
13544
13545       return true;
13546     }
13547
13548   switch (ins->vex.length)
13549     {
13550     case 128:
13551       switch (bytemode)
13552         {
13553         case x_mode:
13554           names = att_names_xmm;
13555           ins->evex_used |= EVEX_len_used;
13556           break;
13557         case v_mode:
13558         case dq_mode:
13559           if (ins->rex & REX_W)
13560             names = att_names64;
13561           else if (bytemode == v_mode
13562                    && !(sizeflag & DFLAG))
13563             names = att_names16;
13564           else
13565             names = att_names32;
13566           break;
13567         case b_mode:
13568           names = att_names8rex;
13569           break;
13570         case q_mode:
13571           names = att_names64;
13572           break;
13573         case mask_bd_mode:
13574         case mask_mode:
13575           if (reg > 0x7)
13576             {
13577               oappend (ins, "(bad)");
13578               return true;
13579             }
13580           names = att_names_mask;
13581           break;
13582         default:
13583           abort ();
13584           return true;
13585         }
13586       break;
13587     case 256:
13588       switch (bytemode)
13589         {
13590         case x_mode:
13591           names = att_names_ymm;
13592           ins->evex_used |= EVEX_len_used;
13593           break;
13594         case mask_bd_mode:
13595         case mask_mode:
13596           if (reg <= 0x7)
13597             {
13598               names = att_names_mask;
13599               break;
13600             }
13601           /* Fall through.  */
13602         default:
13603           /* See PR binutils/20893 for a reproducer.  */
13604           oappend (ins, "(bad)");
13605           return true;
13606         }
13607       break;
13608     case 512:
13609       names = att_names_zmm;
13610       ins->evex_used |= EVEX_len_used;
13611       break;
13612     default:
13613       abort ();
13614       break;
13615     }
13616   oappend_register (ins, names[reg]);
13617   return true;
13618 }
13619
13620 static bool
13621 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13622 {
13623   if (ins->modrm.mod == 3)
13624     return OP_VEX (ins, bytemode, sizeflag);
13625   return true;
13626 }
13627
13628 static bool
13629 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13630 {
13631   OP_VEX (ins, bytemode, sizeflag);
13632
13633   if (ins->vex.w)
13634     {
13635       /* Swap 2nd and 3rd operands.  */
13636       char *tmp = ins->op_out[2];
13637
13638       ins->op_out[2] = ins->op_out[1];
13639       ins->op_out[1] = tmp;
13640     }
13641   return true;
13642 }
13643
13644 static bool
13645 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13646 {
13647   int reg;
13648   const char (*names)[8] = att_names_xmm;
13649
13650   if (!fetch_code (ins->info, ins->codep + 1))
13651     return false;
13652   reg = *ins->codep++;
13653
13654   if (bytemode != x_mode && bytemode != scalar_mode)
13655     abort ();
13656
13657   reg >>= 4;
13658   if (ins->address_mode != mode_64bit)
13659     reg &= 7;
13660
13661   if (bytemode == x_mode && ins->vex.length == 256)
13662     names = att_names_ymm;
13663
13664   oappend_register (ins, names[reg]);
13665
13666   if (ins->vex.w)
13667     {
13668       /* Swap 3rd and 4th operands.  */
13669       char *tmp = ins->op_out[3];
13670
13671       ins->op_out[3] = ins->op_out[2];
13672       ins->op_out[2] = tmp;
13673     }
13674   return true;
13675 }
13676
13677 static bool
13678 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13679           int sizeflag ATTRIBUTE_UNUSED)
13680 {
13681   oappend_immediate (ins, ins->codep[-1] & 0xf);
13682   return true;
13683 }
13684
13685 static bool
13686 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13687              int sizeflag ATTRIBUTE_UNUSED)
13688 {
13689   unsigned int cmp_type;
13690
13691   if (!ins->vex.evex)
13692     abort ();
13693
13694   if (!fetch_code (ins->info, ins->codep + 1))
13695     return false;
13696   cmp_type = *ins->codep++;
13697   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13698      If it's the case, print suffix, otherwise - print the immediate.  */
13699   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13700       && cmp_type != 3
13701       && cmp_type != 7)
13702     {
13703       char suffix[3];
13704       char *p = ins->mnemonicendp - 2;
13705
13706       /* vpcmp* can have both one- and two-lettered suffix.  */
13707       if (p[0] == 'p')
13708         {
13709           p++;
13710           suffix[0] = p[0];
13711           suffix[1] = '\0';
13712         }
13713       else
13714         {
13715           suffix[0] = p[0];
13716           suffix[1] = p[1];
13717           suffix[2] = '\0';
13718         }
13719
13720       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13721       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13722     }
13723   else
13724     {
13725       /* We have a reserved extension byte.  Output it directly.  */
13726       oappend_immediate (ins, cmp_type);
13727     }
13728   return true;
13729 }
13730
13731 static const struct op xop_cmp_op[] =
13732 {
13733   { STRING_COMMA_LEN ("lt") },
13734   { STRING_COMMA_LEN ("le") },
13735   { STRING_COMMA_LEN ("gt") },
13736   { STRING_COMMA_LEN ("ge") },
13737   { STRING_COMMA_LEN ("eq") },
13738   { STRING_COMMA_LEN ("neq") },
13739   { STRING_COMMA_LEN ("false") },
13740   { STRING_COMMA_LEN ("true") }
13741 };
13742
13743 static bool
13744 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13745              int sizeflag ATTRIBUTE_UNUSED)
13746 {
13747   unsigned int cmp_type;
13748
13749   if (!fetch_code (ins->info, ins->codep + 1))
13750     return false;
13751   cmp_type = *ins->codep++;
13752   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13753     {
13754       char suffix[3];
13755       char *p = ins->mnemonicendp - 2;
13756
13757       /* vpcom* can have both one- and two-lettered suffix.  */
13758       if (p[0] == 'm')
13759         {
13760           p++;
13761           suffix[0] = p[0];
13762           suffix[1] = '\0';
13763         }
13764       else
13765         {
13766           suffix[0] = p[0];
13767           suffix[1] = p[1];
13768           suffix[2] = '\0';
13769         }
13770
13771       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13772       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13773     }
13774   else
13775     {
13776       /* We have a reserved extension byte.  Output it directly.  */
13777       oappend_immediate (ins, cmp_type);
13778     }
13779   return true;
13780 }
13781
13782 static const struct op pclmul_op[] =
13783 {
13784   { STRING_COMMA_LEN ("lql") },
13785   { STRING_COMMA_LEN ("hql") },
13786   { STRING_COMMA_LEN ("lqh") },
13787   { STRING_COMMA_LEN ("hqh") }
13788 };
13789
13790 static bool
13791 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13792               int sizeflag ATTRIBUTE_UNUSED)
13793 {
13794   unsigned int pclmul_type;
13795
13796   if (!fetch_code (ins->info, ins->codep + 1))
13797     return false;
13798   pclmul_type = *ins->codep++;
13799   switch (pclmul_type)
13800     {
13801     case 0x10:
13802       pclmul_type = 2;
13803       break;
13804     case 0x11:
13805       pclmul_type = 3;
13806       break;
13807     default:
13808       break;
13809     }
13810   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13811     {
13812       char suffix[4];
13813       char *p = ins->mnemonicendp - 3;
13814       suffix[0] = p[0];
13815       suffix[1] = p[1];
13816       suffix[2] = p[2];
13817       suffix[3] = '\0';
13818       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13819       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13820     }
13821   else
13822     {
13823       /* We have a reserved extension byte.  Output it directly.  */
13824       oappend_immediate (ins, pclmul_type);
13825     }
13826   return true;
13827 }
13828
13829 static bool
13830 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13831 {
13832   /* Add proper suffix to "movsxd".  */
13833   char *p = ins->mnemonicendp;
13834
13835   switch (bytemode)
13836     {
13837     case movsxd_mode:
13838       if (!ins->intel_syntax)
13839         {
13840           USED_REX (REX_W);
13841           if (ins->rex & REX_W)
13842             {
13843               *p++ = 'l';
13844               *p++ = 'q';
13845               break;
13846             }
13847         }
13848
13849       *p++ = 'x';
13850       *p++ = 'd';
13851       break;
13852     default:
13853       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13854       break;
13855     }
13856
13857   ins->mnemonicendp = p;
13858   *p = '\0';
13859   return OP_E (ins, bytemode, sizeflag);
13860 }
13861
13862 static bool
13863 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13864 {
13865   unsigned int reg = ins->vex.register_specifier;
13866   unsigned int modrm_reg = ins->modrm.reg;
13867   unsigned int modrm_rm = ins->modrm.rm;
13868
13869   /* Calc destination register number.  */
13870   if (ins->rex & REX_R)
13871     modrm_reg += 8;
13872   if (ins->rex2 & REX_R)
13873     modrm_reg += 16;
13874
13875   /* Calc src1 register number.  */
13876   if (ins->address_mode != mode_64bit)
13877     reg &= 7;
13878   else if (ins->vex.evex && !ins->vex.v)
13879     reg += 16;
13880
13881   /* Calc src2 register number.  */
13882   if (ins->modrm.mod == 3)
13883     {
13884       if (ins->rex & REX_B)
13885         modrm_rm += 8;
13886       if (ins->rex & REX_X)
13887         modrm_rm += 16;
13888     }
13889
13890   /* Destination and source registers must be distinct, output bad if
13891      dest == src1 or dest == src2.  */
13892   if (modrm_reg == reg
13893       || (ins->modrm.mod == 3
13894           && modrm_reg == modrm_rm))
13895     {
13896       oappend (ins, "(bad)");
13897       return true;
13898     }
13899   return OP_XMM (ins, bytemode, sizeflag);
13900 }
13901
13902 static bool
13903 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13904 {
13905   if (ins->modrm.mod != 3 || !ins->vex.b)
13906     return true;
13907
13908   switch (bytemode)
13909     {
13910     case evex_rounding_64_mode:
13911       if (ins->address_mode != mode_64bit || !ins->vex.w)
13912         return true;
13913       /* Fall through.  */
13914     case evex_rounding_mode:
13915       ins->evex_used |= EVEX_b_used;
13916       oappend (ins, names_rounding[ins->vex.ll]);
13917       break;
13918     case evex_sae_mode:
13919       ins->evex_used |= EVEX_b_used;
13920       oappend (ins, "{");
13921       break;
13922     default:
13923       abort ();
13924     }
13925   oappend (ins, "sae}");
13926   return true;
13927 }
13928
13929 static bool
13930 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
13931 {
13932   if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
13933     {
13934       if (ins->intel_syntax)
13935         {
13936           ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
13937         }
13938       else
13939         {
13940           USED_REX (REX_W);
13941           if (ins->rex & REX_W)
13942             ins->mnemonicendp = stpcpy (ins->obuf, "nopq  ");
13943           else
13944             {
13945               if (sizeflag & DFLAG)
13946                 ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
13947               else
13948                 ins->mnemonicendp = stpcpy (ins->obuf, "nopw  ");
13949               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13950             }
13951         }
13952       bytemode = v_mode;
13953     }
13954
13955   return OP_M (ins, bytemode, sizeflag);
13956 }
13957
13958 static bool
13959 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
13960 {
13961   if (ins->modrm.mod != 3)
13962     return true;
13963
13964   unsigned int vvvv_reg = ins->vex.register_specifier
13965     | (!ins->vex.v << 4);
13966   unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
13967     + (ins->rex2 & REX_B ? 16 : 0);
13968
13969   /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers.  */
13970   if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
13971       || (!ins->modrm.reg
13972           && vvvv_reg == rm_reg))
13973     {
13974       oappend (ins, "(bad)");
13975       return true;
13976     }
13977
13978   return OP_VEX (ins, bytemode, sizeflag);
13979 }
13980
13981 static bool
13982 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
13983 {
13984   if (ins->last_rex2_prefix >= 0)
13985     {
13986       uint64_t op;
13987
13988       if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
13989           || (ins->rex & REX_W) != 0x0)
13990         {
13991           oappend (ins, "(bad)");
13992           return true;
13993         }
13994
13995       if (bytemode == eAX_reg)
13996         return true;
13997
13998       if (!get64 (ins, &op))
13999         return false;
14000
14001       ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
14002       ins->rex2 |= REX2_SPECIAL;
14003       oappend_immediate (ins, op);
14004
14005       return true;
14006     }
14007
14008   if (bytemode == eAX_reg)
14009     return OP_IMREG (ins, bytemode, sizeflag);
14010   return OP_OFF64 (ins, bytemode, sizeflag);
14011 }