1 /* Target-dependent code for the MIPS architecture, for GDB, the GNU Debugger.
3 Copyright (C) 1988-2021 Free Software Foundation, Inc.
5 Contributed by Alessandro Forin(af@cs.cmu.edu) at CMU
6 and by Per Bothner(bothner@cs.wisc.edu) at U.Wisconsin.
8 This file is part of GDB.
10 This program is free software; you can redistribute it and/or modify
11 it under the terms of the GNU General Public License as published by
12 the Free Software Foundation; either version 3 of the License, or
13 (at your option) any later version.
15 This program is distributed in the hope that it will be useful,
16 but WITHOUT ANY WARRANTY; without even the implied warranty of
17 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
18 GNU General Public License for more details.
20 You should have received a copy of the GNU General Public License
21 along with this program. If not, see <http://www.gnu.org/licenses/>. */
35 #include "arch-utils.h"
38 #include "mips-tdep.h"
40 #include "reggroups.h"
41 #include "opcode/mips.h"
45 #include "sim-regno.h"
48 #include "frame-unwind.h"
49 #include "frame-base.h"
50 #include "trad-frame.h"
53 #include "target-descriptions.h"
54 #include "dwarf2/frame.h"
55 #include "user-regs.h"
58 #include "target-float.h"
61 static struct type
*mips_register_type (struct gdbarch
*gdbarch
, int regnum
);
63 static int mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
,
65 static int micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
);
66 static int mips16_instruction_has_delay_slot (unsigned short inst
,
69 static int mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
71 static int micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
72 CORE_ADDR addr
, int mustbe32
);
73 static int mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
74 CORE_ADDR addr
, int mustbe32
);
76 static void mips_print_float_info (struct gdbarch
*, struct ui_file
*,
77 struct frame_info
*, const char *);
79 /* A useful bit in the CP0 status register (MIPS_PS_REGNUM). */
80 /* This bit is set if we are emulating 32-bit FPRs on a 64-bit chip. */
81 #define ST0_FR (1 << 26)
83 /* The sizes of floating point registers. */
87 MIPS_FPU_SINGLE_REGSIZE
= 4,
88 MIPS_FPU_DOUBLE_REGSIZE
= 8
97 static const char *mips_abi_string
;
99 static const char *const mips_abi_strings
[] = {
110 /* Enum describing the different kinds of breakpoints. */
112 enum mips_breakpoint_kind
114 /* 16-bit MIPS16 mode breakpoint. */
115 MIPS_BP_KIND_MIPS16
= 2,
117 /* 16-bit microMIPS mode breakpoint. */
118 MIPS_BP_KIND_MICROMIPS16
= 3,
120 /* 32-bit standard MIPS mode breakpoint. */
121 MIPS_BP_KIND_MIPS32
= 4,
123 /* 32-bit microMIPS mode breakpoint. */
124 MIPS_BP_KIND_MICROMIPS32
= 5,
127 /* For backwards compatibility we default to MIPS16. This flag is
128 overridden as soon as unambiguous ELF file flags tell us the
129 compressed ISA encoding used. */
130 static const char mips_compression_mips16
[] = "mips16";
131 static const char mips_compression_micromips
[] = "micromips";
132 static const char *const mips_compression_strings
[] =
134 mips_compression_mips16
,
135 mips_compression_micromips
,
139 static const char *mips_compression_string
= mips_compression_mips16
;
141 /* The standard register names, and all the valid aliases for them. */
142 struct register_alias
148 /* Aliases for o32 and most other ABIs. */
149 const struct register_alias mips_o32_aliases
[] = {
156 /* Aliases for n32 and n64. */
157 const struct register_alias mips_n32_n64_aliases
[] = {
164 /* Aliases for ABI-independent registers. */
165 const struct register_alias mips_register_aliases
[] = {
166 /* The architecture manuals specify these ABI-independent names for
168 #define R(n) { "r" #n, n }
169 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
170 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
171 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
172 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
175 /* k0 and k1 are sometimes called these instead (for "kernel
180 /* This is the traditional GDB name for the CP0 status register. */
181 { "sr", MIPS_PS_REGNUM
},
183 /* This is the traditional GDB name for the CP0 BadVAddr register. */
184 { "bad", MIPS_EMBED_BADVADDR_REGNUM
},
186 /* This is the traditional GDB name for the FCSR. */
187 { "fsr", MIPS_EMBED_FP0_REGNUM
+ 32 }
190 const struct register_alias mips_numeric_register_aliases
[] = {
191 #define R(n) { #n, n }
192 R(0), R(1), R(2), R(3), R(4), R(5), R(6), R(7),
193 R(8), R(9), R(10), R(11), R(12), R(13), R(14), R(15),
194 R(16), R(17), R(18), R(19), R(20), R(21), R(22), R(23),
195 R(24), R(25), R(26), R(27), R(28), R(29), R(30), R(31),
199 #ifndef MIPS_DEFAULT_FPU_TYPE
200 #define MIPS_DEFAULT_FPU_TYPE MIPS_FPU_DOUBLE
202 static int mips_fpu_type_auto
= 1;
203 static enum mips_fpu_type mips_fpu_type
= MIPS_DEFAULT_FPU_TYPE
;
205 static unsigned int mips_debug
= 0;
207 /* Properties (for struct target_desc) describing the g/G packet
209 #define PROPERTY_GP32 "internal: transfers-32bit-registers"
210 #define PROPERTY_GP64 "internal: transfers-64bit-registers"
212 struct target_desc
*mips_tdesc_gp32
;
213 struct target_desc
*mips_tdesc_gp64
;
215 /* The current set of options to be passed to the disassembler. */
216 static char *mips_disassembler_options
;
218 /* Implicit disassembler options for individual ABIs. These tell
219 libopcodes to use general-purpose register names corresponding
220 to the ABI we have selected, perhaps via a `set mips abi ...'
221 override, rather than ones inferred from the ABI set in the ELF
222 headers of the binary file selected for debugging. */
223 static const char mips_disassembler_options_o32
[] = "gpr-names=32";
224 static const char mips_disassembler_options_n32
[] = "gpr-names=n32";
225 static const char mips_disassembler_options_n64
[] = "gpr-names=64";
227 const struct mips_regnum
*
228 mips_regnum (struct gdbarch
*gdbarch
)
230 return gdbarch_tdep (gdbarch
)->regnum
;
234 mips_fpa0_regnum (struct gdbarch
*gdbarch
)
236 return mips_regnum (gdbarch
)->fp0
+ 12;
239 /* Return 1 if REGNUM refers to a floating-point general register, raw
240 or cooked. Otherwise return 0. */
243 mips_float_register_p (struct gdbarch
*gdbarch
, int regnum
)
245 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
247 return (rawnum
>= mips_regnum (gdbarch
)->fp0
248 && rawnum
< mips_regnum (gdbarch
)->fp0
+ 32);
251 #define MIPS_EABI(gdbarch) (gdbarch_tdep (gdbarch)->mips_abi \
253 || gdbarch_tdep (gdbarch)->mips_abi == MIPS_ABI_EABI64)
255 #define MIPS_LAST_FP_ARG_REGNUM(gdbarch) \
256 (gdbarch_tdep (gdbarch)->mips_last_fp_arg_regnum)
258 #define MIPS_LAST_ARG_REGNUM(gdbarch) \
259 (gdbarch_tdep (gdbarch)->mips_last_arg_regnum)
261 #define MIPS_FPU_TYPE(gdbarch) (gdbarch_tdep (gdbarch)->mips_fpu_type)
263 /* Return the MIPS ABI associated with GDBARCH. */
265 mips_abi (struct gdbarch
*gdbarch
)
267 return gdbarch_tdep (gdbarch
)->mips_abi
;
271 mips_isa_regsize (struct gdbarch
*gdbarch
)
273 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
275 /* If we know how big the registers are, use that size. */
276 if (tdep
->register_size_valid_p
)
277 return tdep
->register_size
;
279 /* Fall back to the previous behavior. */
280 return (gdbarch_bfd_arch_info (gdbarch
)->bits_per_word
281 / gdbarch_bfd_arch_info (gdbarch
)->bits_per_byte
);
284 /* Max saved register size. */
285 #define MAX_MIPS_ABI_REGSIZE 8
287 /* Return the currently configured (or set) saved register size. */
290 mips_abi_regsize (struct gdbarch
*gdbarch
)
292 switch (mips_abi (gdbarch
))
294 case MIPS_ABI_EABI32
:
300 case MIPS_ABI_EABI64
:
302 case MIPS_ABI_UNKNOWN
:
305 internal_error (__FILE__
, __LINE__
, _("bad switch"));
309 /* MIPS16/microMIPS function addresses are odd (bit 0 is set). Here
310 are some functions to handle addresses associated with compressed
311 code including but not limited to testing, setting, or clearing
312 bit 0 of such addresses. */
314 /* Return one iff compressed code is the MIPS16 instruction set. */
317 is_mips16_isa (struct gdbarch
*gdbarch
)
319 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MIPS16
;
322 /* Return one iff compressed code is the microMIPS instruction set. */
325 is_micromips_isa (struct gdbarch
*gdbarch
)
327 return gdbarch_tdep (gdbarch
)->mips_isa
== ISA_MICROMIPS
;
330 /* Return one iff ADDR denotes compressed code. */
333 is_compact_addr (CORE_ADDR addr
)
338 /* Return one iff ADDR denotes standard ISA code. */
341 is_mips_addr (CORE_ADDR addr
)
343 return !is_compact_addr (addr
);
346 /* Return one iff ADDR denotes MIPS16 code. */
349 is_mips16_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
351 return is_compact_addr (addr
) && is_mips16_isa (gdbarch
);
354 /* Return one iff ADDR denotes microMIPS code. */
357 is_micromips_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
359 return is_compact_addr (addr
) && is_micromips_isa (gdbarch
);
362 /* Strip the ISA (compression) bit off from ADDR. */
365 unmake_compact_addr (CORE_ADDR addr
)
367 return ((addr
) & ~(CORE_ADDR
) 1);
370 /* Add the ISA (compression) bit to ADDR. */
373 make_compact_addr (CORE_ADDR addr
)
375 return ((addr
) | (CORE_ADDR
) 1);
378 /* Extern version of unmake_compact_addr; we use a separate function
379 so that unmake_compact_addr can be inlined throughout this file. */
382 mips_unmake_compact_addr (CORE_ADDR addr
)
384 return unmake_compact_addr (addr
);
387 /* Functions for setting and testing a bit in a minimal symbol that
388 marks it as MIPS16 or microMIPS function. The MSB of the minimal
389 symbol's "info" field is used for this purpose.
391 gdbarch_elf_make_msymbol_special tests whether an ELF symbol is
392 "special", i.e. refers to a MIPS16 or microMIPS function, and sets
393 one of the "special" bits in a minimal symbol to mark it accordingly.
394 The test checks an ELF-private flag that is valid for true function
395 symbols only; for synthetic symbols such as for PLT stubs that have
396 no ELF-private part at all the MIPS BFD backend arranges for this
397 information to be carried in the asymbol's udata field instead.
399 msymbol_is_mips16 and msymbol_is_micromips test the "special" bit
400 in a minimal symbol. */
403 mips_elf_make_msymbol_special (asymbol
* sym
, struct minimal_symbol
*msym
)
405 elf_symbol_type
*elfsym
= (elf_symbol_type
*) sym
;
406 unsigned char st_other
;
408 if ((sym
->flags
& BSF_SYNTHETIC
) == 0)
409 st_other
= elfsym
->internal_elf_sym
.st_other
;
410 else if ((sym
->flags
& BSF_FUNCTION
) != 0)
411 st_other
= sym
->udata
.i
;
415 if (ELF_ST_IS_MICROMIPS (st_other
))
417 MSYMBOL_TARGET_FLAG_MICROMIPS (msym
) = 1;
418 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
420 else if (ELF_ST_IS_MIPS16 (st_other
))
422 MSYMBOL_TARGET_FLAG_MIPS16 (msym
) = 1;
423 SET_MSYMBOL_VALUE_ADDRESS (msym
, MSYMBOL_VALUE_RAW_ADDRESS (msym
) | 1);
427 /* Return one iff MSYM refers to standard ISA code. */
430 msymbol_is_mips (struct minimal_symbol
*msym
)
432 return !(MSYMBOL_TARGET_FLAG_MIPS16 (msym
)
433 | MSYMBOL_TARGET_FLAG_MICROMIPS (msym
));
436 /* Return one iff MSYM refers to MIPS16 code. */
439 msymbol_is_mips16 (struct minimal_symbol
*msym
)
441 return MSYMBOL_TARGET_FLAG_MIPS16 (msym
);
444 /* Return one iff MSYM refers to microMIPS code. */
447 msymbol_is_micromips (struct minimal_symbol
*msym
)
449 return MSYMBOL_TARGET_FLAG_MICROMIPS (msym
);
452 /* Set the ISA bit in the main symbol too, complementing the corresponding
453 minimal symbol setting and reflecting the run-time value of the symbol.
454 The need for comes from the ISA bit having been cleared as code in
455 `_bfd_mips_elf_symbol_processing' separated it into the ELF symbol's
456 `st_other' STO_MIPS16 or STO_MICROMIPS annotation, making the values
457 of symbols referring to compressed code different in GDB to the values
458 used by actual code. That in turn makes them evaluate incorrectly in
459 expressions, producing results different to what the same expressions
460 yield when compiled into the program being debugged. */
463 mips_make_symbol_special (struct symbol
*sym
, struct objfile
*objfile
)
465 if (SYMBOL_CLASS (sym
) == LOC_BLOCK
)
467 /* We are in symbol reading so it is OK to cast away constness. */
468 struct block
*block
= (struct block
*) SYMBOL_BLOCK_VALUE (sym
);
469 CORE_ADDR compact_block_start
;
470 struct bound_minimal_symbol msym
;
472 compact_block_start
= BLOCK_START (block
) | 1;
473 msym
= lookup_minimal_symbol_by_pc (compact_block_start
);
474 if (msym
.minsym
&& !msymbol_is_mips (msym
.minsym
))
476 BLOCK_START (block
) = compact_block_start
;
481 /* XFER a value from the big/little/left end of the register.
482 Depending on the size of the value it might occupy the entire
483 register or just part of it. Make an allowance for this, aligning
484 things accordingly. */
487 mips_xfer_register (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
488 int reg_num
, int length
,
489 enum bfd_endian endian
, gdb_byte
*in
,
490 const gdb_byte
*out
, int buf_offset
)
494 gdb_assert (reg_num
>= gdbarch_num_regs (gdbarch
));
495 /* Need to transfer the left or right part of the register, based on
496 the targets byte order. */
500 reg_offset
= register_size (gdbarch
, reg_num
) - length
;
502 case BFD_ENDIAN_LITTLE
:
505 case BFD_ENDIAN_UNKNOWN
: /* Indicates no alignment. */
509 internal_error (__FILE__
, __LINE__
, _("bad switch"));
512 fprintf_unfiltered (gdb_stderr
,
513 "xfer $%d, reg offset %d, buf offset %d, length %d, ",
514 reg_num
, reg_offset
, buf_offset
, length
);
515 if (mips_debug
&& out
!= NULL
)
518 fprintf_unfiltered (gdb_stdlog
, "out ");
519 for (i
= 0; i
< length
; i
++)
520 fprintf_unfiltered (gdb_stdlog
, "%02x", out
[buf_offset
+ i
]);
523 regcache
->cooked_read_part (reg_num
, reg_offset
, length
, in
+ buf_offset
);
525 regcache
->cooked_write_part (reg_num
, reg_offset
, length
, out
+ buf_offset
);
526 if (mips_debug
&& in
!= NULL
)
529 fprintf_unfiltered (gdb_stdlog
, "in ");
530 for (i
= 0; i
< length
; i
++)
531 fprintf_unfiltered (gdb_stdlog
, "%02x", in
[buf_offset
+ i
]);
534 fprintf_unfiltered (gdb_stdlog
, "\n");
537 /* Determine if a MIPS3 or later cpu is operating in MIPS{1,2} FPU
538 compatiblity mode. A return value of 1 means that we have
539 physical 64-bit registers, but should treat them as 32-bit registers. */
542 mips2_fp_compat (struct frame_info
*frame
)
544 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
545 /* MIPS1 and MIPS2 have only 32 bit FPRs, and the FR bit is not
547 if (register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) == 4)
551 /* FIXME drow 2002-03-10: This is disabled until we can do it consistently,
552 in all the places we deal with FP registers. PR gdb/413. */
553 /* Otherwise check the FR bit in the status register - it controls
554 the FP compatiblity mode. If it is clear we are in compatibility
556 if ((get_frame_register_unsigned (frame
, MIPS_PS_REGNUM
) & ST0_FR
) == 0)
563 #define VM_MIN_ADDRESS (CORE_ADDR)0x400000
565 static CORE_ADDR
heuristic_proc_start (struct gdbarch
*, CORE_ADDR
);
567 /* The list of available "set mips " and "show mips " commands. */
569 static struct cmd_list_element
*setmipscmdlist
= NULL
;
570 static struct cmd_list_element
*showmipscmdlist
= NULL
;
572 /* Integer registers 0 thru 31 are handled explicitly by
573 mips_register_name(). Processor specific registers 32 and above
574 are listed in the following tables. */
577 { NUM_MIPS_PROCESSOR_REGS
= (90 - 32) };
581 static const char * const mips_generic_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
582 "sr", "lo", "hi", "bad", "cause", "pc",
583 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
584 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
585 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
586 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
590 /* Names of tx39 registers. */
592 static const char * const mips_tx39_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
593 "sr", "lo", "hi", "bad", "cause", "pc",
594 "", "", "", "", "", "", "", "",
595 "", "", "", "", "", "", "", "",
596 "", "", "", "", "", "", "", "",
597 "", "", "", "", "", "", "", "",
599 "", "", "", "", "", "", "", "",
600 "", "", "config", "cache", "debug", "depc", "epc",
603 /* Names of registers with Linux kernels. */
604 static const char * const mips_linux_reg_names
[NUM_MIPS_PROCESSOR_REGS
] = {
605 "sr", "lo", "hi", "bad", "cause", "pc",
606 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
607 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
608 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
609 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
614 /* Return the name of the register corresponding to REGNO. */
616 mips_register_name (struct gdbarch
*gdbarch
, int regno
)
618 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
619 /* GPR names for all ABIs other than n32/n64. */
620 static const char *mips_gpr_names
[] = {
621 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
622 "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7",
623 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
624 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra",
627 /* GPR names for n32 and n64 ABIs. */
628 static const char *mips_n32_n64_gpr_names
[] = {
629 "zero", "at", "v0", "v1", "a0", "a1", "a2", "a3",
630 "a4", "a5", "a6", "a7", "t0", "t1", "t2", "t3",
631 "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7",
632 "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra"
635 enum mips_abi abi
= mips_abi (gdbarch
);
637 /* Map [gdbarch_num_regs .. 2*gdbarch_num_regs) onto the raw registers,
638 but then don't make the raw register names visible. This (upper)
639 range of user visible register numbers are the pseudo-registers.
641 This approach was adopted accommodate the following scenario:
642 It is possible to debug a 64-bit device using a 32-bit
643 programming model. In such instances, the raw registers are
644 configured to be 64-bits wide, while the pseudo registers are
645 configured to be 32-bits wide. The registers that the user
646 sees - the pseudo registers - match the users expectations
647 given the programming model being used. */
648 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
649 if (regno
< gdbarch_num_regs (gdbarch
))
652 /* The MIPS integer registers are always mapped from 0 to 31. The
653 names of the registers (which reflects the conventions regarding
654 register use) vary depending on the ABI. */
655 if (0 <= rawnum
&& rawnum
< 32)
657 if (abi
== MIPS_ABI_N32
|| abi
== MIPS_ABI_N64
)
658 return mips_n32_n64_gpr_names
[rawnum
];
660 return mips_gpr_names
[rawnum
];
662 else if (tdesc_has_registers (gdbarch_target_desc (gdbarch
)))
663 return tdesc_register_name (gdbarch
, rawnum
);
664 else if (32 <= rawnum
&& rawnum
< gdbarch_num_regs (gdbarch
))
666 gdb_assert (rawnum
- 32 < NUM_MIPS_PROCESSOR_REGS
);
667 if (tdep
->mips_processor_reg_names
[rawnum
- 32])
668 return tdep
->mips_processor_reg_names
[rawnum
- 32];
672 internal_error (__FILE__
, __LINE__
,
673 _("mips_register_name: bad register number %d"), rawnum
);
676 /* Return the groups that a MIPS register can be categorised into. */
679 mips_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
680 struct reggroup
*reggroup
)
685 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
686 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
687 if (reggroup
== all_reggroup
)
689 vector_p
= register_type (gdbarch
, regnum
)->is_vector ();
690 float_p
= register_type (gdbarch
, regnum
)->code () == TYPE_CODE_FLT
;
691 /* FIXME: cagney/2003-04-13: Can't yet use gdbarch_num_regs
692 (gdbarch), as not all architectures are multi-arch. */
693 raw_p
= rawnum
< gdbarch_num_regs (gdbarch
);
694 if (gdbarch_register_name (gdbarch
, regnum
) == NULL
695 || gdbarch_register_name (gdbarch
, regnum
)[0] == '\0')
697 if (reggroup
== float_reggroup
)
698 return float_p
&& pseudo
;
699 if (reggroup
== vector_reggroup
)
700 return vector_p
&& pseudo
;
701 if (reggroup
== general_reggroup
)
702 return (!vector_p
&& !float_p
) && pseudo
;
703 /* Save the pseudo registers. Need to make certain that any code
704 extracting register values from a saved register cache also uses
706 if (reggroup
== save_reggroup
)
707 return raw_p
&& pseudo
;
708 /* Restore the same pseudo register. */
709 if (reggroup
== restore_reggroup
)
710 return raw_p
&& pseudo
;
714 /* Return the groups that a MIPS register can be categorised into.
715 This version is only used if we have a target description which
716 describes real registers (and their groups). */
719 mips_tdesc_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
720 struct reggroup
*reggroup
)
722 int rawnum
= regnum
% gdbarch_num_regs (gdbarch
);
723 int pseudo
= regnum
/ gdbarch_num_regs (gdbarch
);
726 /* Only save, restore, and display the pseudo registers. Need to
727 make certain that any code extracting register values from a
728 saved register cache also uses pseudo registers.
730 Note: saving and restoring the pseudo registers is slightly
731 strange; if we have 64 bits, we should save and restore all
732 64 bits. But this is hard and has little benefit. */
736 ret
= tdesc_register_in_reggroup_p (gdbarch
, rawnum
, reggroup
);
740 return mips_register_reggroup_p (gdbarch
, regnum
, reggroup
);
743 /* Map the symbol table registers which live in the range [1 *
744 gdbarch_num_regs .. 2 * gdbarch_num_regs) back onto the corresponding raw
745 registers. Take care of alignment and size problems. */
747 static enum register_status
748 mips_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
749 int cookednum
, gdb_byte
*buf
)
751 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
752 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
753 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
754 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
755 return regcache
->raw_read (rawnum
, buf
);
756 else if (register_size (gdbarch
, rawnum
) >
757 register_size (gdbarch
, cookednum
))
759 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
760 return regcache
->raw_read_part (rawnum
, 0, 4, buf
);
763 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
765 enum register_status status
;
767 status
= regcache
->raw_read (rawnum
, ®val
);
768 if (status
== REG_VALID
)
769 store_signed_integer (buf
, 4, byte_order
, regval
);
774 internal_error (__FILE__
, __LINE__
, _("bad register size"));
778 mips_pseudo_register_write (struct gdbarch
*gdbarch
,
779 struct regcache
*regcache
, int cookednum
,
782 int rawnum
= cookednum
% gdbarch_num_regs (gdbarch
);
783 gdb_assert (cookednum
>= gdbarch_num_regs (gdbarch
)
784 && cookednum
< 2 * gdbarch_num_regs (gdbarch
));
785 if (register_size (gdbarch
, rawnum
) == register_size (gdbarch
, cookednum
))
786 regcache
->raw_write (rawnum
, buf
);
787 else if (register_size (gdbarch
, rawnum
) >
788 register_size (gdbarch
, cookednum
))
790 if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
791 regcache
->raw_write_part (rawnum
, 0, 4, buf
);
794 /* Sign extend the shortened version of the register prior
795 to placing it in the raw register. This is required for
796 some mips64 parts in order to avoid unpredictable behavior. */
797 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
798 LONGEST regval
= extract_signed_integer (buf
, 4, byte_order
);
799 regcache_raw_write_signed (regcache
, rawnum
, regval
);
803 internal_error (__FILE__
, __LINE__
, _("bad register size"));
807 mips_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
808 struct agent_expr
*ax
, int reg
)
810 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
811 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
812 && reg
< 2 * gdbarch_num_regs (gdbarch
));
814 ax_reg_mask (ax
, rawnum
);
820 mips_ax_pseudo_register_push_stack (struct gdbarch
*gdbarch
,
821 struct agent_expr
*ax
, int reg
)
823 int rawnum
= reg
% gdbarch_num_regs (gdbarch
);
824 gdb_assert (reg
>= gdbarch_num_regs (gdbarch
)
825 && reg
< 2 * gdbarch_num_regs (gdbarch
));
826 if (register_size (gdbarch
, rawnum
) >= register_size (gdbarch
, reg
))
830 if (register_size (gdbarch
, rawnum
) > register_size (gdbarch
, reg
))
832 if (!gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
833 || gdbarch_byte_order (gdbarch
) != BFD_ENDIAN_BIG
)
836 ax_simple (ax
, aop_lsh
);
839 ax_simple (ax
, aop_rsh_signed
);
843 internal_error (__FILE__
, __LINE__
, _("bad register size"));
848 /* Table to translate 3-bit register field to actual register number. */
849 static const signed char mips_reg3_to_reg
[8] = { 16, 17, 2, 3, 4, 5, 6, 7 };
851 /* Heuristic_proc_start may hunt through the text section for a long
852 time across a 2400 baud serial line. Allows the user to limit this
855 static int heuristic_fence_post
= 0;
857 /* Number of bytes of storage in the actual machine representation for
858 register N. NOTE: This defines the pseudo register type so need to
859 rebuild the architecture vector. */
861 static bool mips64_transfers_32bit_regs_p
= false;
864 set_mips64_transfers_32bit_regs (const char *args
, int from_tty
,
865 struct cmd_list_element
*c
)
867 struct gdbarch_info info
;
868 gdbarch_info_init (&info
);
869 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
870 instead of relying on globals. Doing that would let generic code
871 handle the search for this specific architecture. */
872 if (!gdbarch_update_p (info
))
874 mips64_transfers_32bit_regs_p
= 0;
875 error (_("32-bit compatibility mode not supported"));
879 /* Convert to/from a register and the corresponding memory value. */
881 /* This predicate tests for the case of an 8 byte floating point
882 value that is being transferred to or from a pair of floating point
883 registers each of which are (or are considered to be) only 4 bytes
886 mips_convert_register_float_case_p (struct gdbarch
*gdbarch
, int regnum
,
889 return (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
890 && register_size (gdbarch
, regnum
) == 4
891 && mips_float_register_p (gdbarch
, regnum
)
892 && type
->code () == TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8);
895 /* This predicate tests for the case of a value of less than 8
896 bytes in width that is being transfered to or from an 8 byte
897 general purpose register. */
899 mips_convert_register_gpreg_case_p (struct gdbarch
*gdbarch
, int regnum
,
902 int num_regs
= gdbarch_num_regs (gdbarch
);
904 return (register_size (gdbarch
, regnum
) == 8
905 && regnum
% num_regs
> 0 && regnum
% num_regs
< 32
906 && TYPE_LENGTH (type
) < 8);
910 mips_convert_register_p (struct gdbarch
*gdbarch
,
911 int regnum
, struct type
*type
)
913 return (mips_convert_register_float_case_p (gdbarch
, regnum
, type
)
914 || mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
));
918 mips_register_to_value (struct frame_info
*frame
, int regnum
,
919 struct type
*type
, gdb_byte
*to
,
920 int *optimizedp
, int *unavailablep
)
922 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
924 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
926 get_frame_register (frame
, regnum
+ 0, to
+ 4);
927 get_frame_register (frame
, regnum
+ 1, to
+ 0);
929 if (!get_frame_register_bytes (frame
, regnum
+ 0, 0, {to
+ 4, 4},
930 optimizedp
, unavailablep
))
933 if (!get_frame_register_bytes (frame
, regnum
+ 1, 0, {to
+ 0, 4},
934 optimizedp
, unavailablep
))
936 *optimizedp
= *unavailablep
= 0;
939 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
941 size_t len
= TYPE_LENGTH (type
);
944 offset
= gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
? 8 - len
: 0;
945 if (!get_frame_register_bytes (frame
, regnum
, offset
, {to
, len
},
946 optimizedp
, unavailablep
))
949 *optimizedp
= *unavailablep
= 0;
954 internal_error (__FILE__
, __LINE__
,
955 _("mips_register_to_value: unrecognized case"));
960 mips_value_to_register (struct frame_info
*frame
, int regnum
,
961 struct type
*type
, const gdb_byte
*from
)
963 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
965 if (mips_convert_register_float_case_p (gdbarch
, regnum
, type
))
967 put_frame_register (frame
, regnum
+ 0, from
+ 4);
968 put_frame_register (frame
, regnum
+ 1, from
+ 0);
970 else if (mips_convert_register_gpreg_case_p (gdbarch
, regnum
, type
))
973 size_t len
= TYPE_LENGTH (type
);
975 /* Sign extend values, irrespective of type, that are stored to
976 a 64-bit general purpose register. (32-bit unsigned values
977 are stored as signed quantities within a 64-bit register.
978 When performing an operation, in compiled code, that combines
979 a 32-bit unsigned value with a signed 64-bit value, a type
980 conversion is first performed that zeroes out the high 32 bits.) */
981 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
984 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, -1);
986 store_signed_integer (fill
, 8, BFD_ENDIAN_BIG
, 0);
987 put_frame_register_bytes (frame
, regnum
, 0, {fill
, 8 - len
});
988 put_frame_register_bytes (frame
, regnum
, 8 - len
, {from
, len
});
992 if (from
[len
-1] & 0x80)
993 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, -1);
995 store_signed_integer (fill
, 8, BFD_ENDIAN_LITTLE
, 0);
996 put_frame_register_bytes (frame
, regnum
, 0, {from
, len
});
997 put_frame_register_bytes (frame
, regnum
, len
, {fill
, 8 - len
});
1002 internal_error (__FILE__
, __LINE__
,
1003 _("mips_value_to_register: unrecognized case"));
1007 /* Return the GDB type object for the "standard" data type of data in
1010 static struct type
*
1011 mips_register_type (struct gdbarch
*gdbarch
, int regnum
)
1013 gdb_assert (regnum
>= 0 && regnum
< 2 * gdbarch_num_regs (gdbarch
));
1014 if (mips_float_register_p (gdbarch
, regnum
))
1016 /* The floating-point registers raw, or cooked, always match
1017 mips_isa_regsize(), and also map 1:1, byte for byte. */
1018 if (mips_isa_regsize (gdbarch
) == 4)
1019 return builtin_type (gdbarch
)->builtin_float
;
1021 return builtin_type (gdbarch
)->builtin_double
;
1023 else if (regnum
< gdbarch_num_regs (gdbarch
))
1025 /* The raw or ISA registers. These are all sized according to
1027 if (mips_isa_regsize (gdbarch
) == 4)
1028 return builtin_type (gdbarch
)->builtin_int32
;
1030 return builtin_type (gdbarch
)->builtin_int64
;
1034 int rawnum
= regnum
- gdbarch_num_regs (gdbarch
);
1036 /* The cooked or ABI registers. These are sized according to
1037 the ABI (with a few complications). */
1038 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1039 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1040 return builtin_type (gdbarch
)->builtin_int32
;
1041 else if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1042 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1043 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1044 /* The pseudo/cooked view of the embedded registers is always
1045 32-bit. The raw view is handled below. */
1046 return builtin_type (gdbarch
)->builtin_int32
;
1047 else if (gdbarch_tdep (gdbarch
)->mips64_transfers_32bit_regs_p
)
1048 /* The target, while possibly using a 64-bit register buffer,
1049 is only transfering 32-bits of each integer register.
1050 Reflect this in the cooked/pseudo (ABI) register value. */
1051 return builtin_type (gdbarch
)->builtin_int32
;
1052 else if (mips_abi_regsize (gdbarch
) == 4)
1053 /* The ABI is restricted to 32-bit registers (the ISA could be
1055 return builtin_type (gdbarch
)->builtin_int32
;
1058 return builtin_type (gdbarch
)->builtin_int64
;
1062 /* Return the GDB type for the pseudo register REGNUM, which is the
1063 ABI-level view. This function is only called if there is a target
1064 description which includes registers, so we know precisely the
1065 types of hardware registers. */
1067 static struct type
*
1068 mips_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
1070 const int num_regs
= gdbarch_num_regs (gdbarch
);
1071 int rawnum
= regnum
% num_regs
;
1072 struct type
*rawtype
;
1074 gdb_assert (regnum
>= num_regs
&& regnum
< 2 * num_regs
);
1076 /* Absent registers are still absent. */
1077 rawtype
= gdbarch_register_type (gdbarch
, rawnum
);
1078 if (TYPE_LENGTH (rawtype
) == 0)
1081 /* Present the floating point registers however the hardware did;
1082 do not try to convert between FPU layouts. */
1083 if (mips_float_register_p (gdbarch
, rawnum
))
1086 /* Floating-point control registers are always 32-bit even though for
1087 backwards compatibility reasons 64-bit targets will transfer them
1088 as 64-bit quantities even if using XML descriptions. */
1089 if (rawnum
== mips_regnum (gdbarch
)->fp_control_status
1090 || rawnum
== mips_regnum (gdbarch
)->fp_implementation_revision
)
1091 return builtin_type (gdbarch
)->builtin_int32
;
1093 /* Use pointer types for registers if we can. For n32 we can not,
1094 since we do not have a 64-bit pointer type. */
1095 if (mips_abi_regsize (gdbarch
)
1096 == TYPE_LENGTH (builtin_type (gdbarch
)->builtin_data_ptr
))
1098 if (rawnum
== MIPS_SP_REGNUM
1099 || rawnum
== mips_regnum (gdbarch
)->badvaddr
)
1100 return builtin_type (gdbarch
)->builtin_data_ptr
;
1101 else if (rawnum
== mips_regnum (gdbarch
)->pc
)
1102 return builtin_type (gdbarch
)->builtin_func_ptr
;
1105 if (mips_abi_regsize (gdbarch
) == 4 && TYPE_LENGTH (rawtype
) == 8
1106 && ((rawnum
>= MIPS_ZERO_REGNUM
&& rawnum
<= MIPS_PS_REGNUM
)
1107 || rawnum
== mips_regnum (gdbarch
)->lo
1108 || rawnum
== mips_regnum (gdbarch
)->hi
1109 || rawnum
== mips_regnum (gdbarch
)->badvaddr
1110 || rawnum
== mips_regnum (gdbarch
)->cause
1111 || rawnum
== mips_regnum (gdbarch
)->pc
1112 || (mips_regnum (gdbarch
)->dspacc
!= -1
1113 && rawnum
>= mips_regnum (gdbarch
)->dspacc
1114 && rawnum
< mips_regnum (gdbarch
)->dspacc
+ 6)))
1115 return builtin_type (gdbarch
)->builtin_int32
;
1117 /* The pseudo/cooked view of embedded registers is always
1118 32-bit, even if the target transfers 64-bit values for them.
1119 New targets relying on XML descriptions should only transfer
1120 the necessary 32 bits, but older versions of GDB expected 64,
1121 so allow the target to provide 64 bits without interfering
1122 with the displayed type. */
1123 if (gdbarch_osabi (gdbarch
) != GDB_OSABI_LINUX
1124 && rawnum
>= MIPS_FIRST_EMBED_REGNUM
1125 && rawnum
<= MIPS_LAST_EMBED_REGNUM
)
1126 return builtin_type (gdbarch
)->builtin_int32
;
1128 /* For all other registers, pass through the hardware type. */
1132 /* Should the upper word of 64-bit addresses be zeroed? */
1133 static enum auto_boolean mask_address_var
= AUTO_BOOLEAN_AUTO
;
1136 mips_mask_address_p (struct gdbarch_tdep
*tdep
)
1138 switch (mask_address_var
)
1140 case AUTO_BOOLEAN_TRUE
:
1142 case AUTO_BOOLEAN_FALSE
:
1145 case AUTO_BOOLEAN_AUTO
:
1146 return tdep
->default_mask_address_p
;
1148 internal_error (__FILE__
, __LINE__
,
1149 _("mips_mask_address_p: bad switch"));
1155 show_mask_address (struct ui_file
*file
, int from_tty
,
1156 struct cmd_list_element
*c
, const char *value
)
1158 struct gdbarch_tdep
*tdep
= gdbarch_tdep (target_gdbarch ());
1160 deprecated_show_value_hack (file
, from_tty
, c
, value
);
1161 switch (mask_address_var
)
1163 case AUTO_BOOLEAN_TRUE
:
1164 printf_filtered ("The 32 bit mips address mask is enabled\n");
1166 case AUTO_BOOLEAN_FALSE
:
1167 printf_filtered ("The 32 bit mips address mask is disabled\n");
1169 case AUTO_BOOLEAN_AUTO
:
1171 ("The 32 bit address mask is set automatically. Currently %s\n",
1172 mips_mask_address_p (tdep
) ? "enabled" : "disabled");
1175 internal_error (__FILE__
, __LINE__
, _("show_mask_address: bad switch"));
1180 /* Tell if the program counter value in MEMADDR is in a standard ISA
1184 mips_pc_is_mips (CORE_ADDR memaddr
)
1186 struct bound_minimal_symbol sym
;
1188 /* Flags indicating that this is a MIPS16 or microMIPS function is
1189 stored by elfread.c in the high bit of the info field. Use this
1190 to decide if the function is standard MIPS. Otherwise if bit 0
1191 of the address is clear, then this is a standard MIPS function. */
1192 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1194 return msymbol_is_mips (sym
.minsym
);
1196 return is_mips_addr (memaddr
);
1199 /* Tell if the program counter value in MEMADDR is in a MIPS16 function. */
1202 mips_pc_is_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1204 struct bound_minimal_symbol sym
;
1206 /* A flag indicating that this is a MIPS16 function is stored by
1207 elfread.c in the high bit of the info field. Use this to decide
1208 if the function is MIPS16. Otherwise if bit 0 of the address is
1209 set, then ELF file flags will tell if this is a MIPS16 function. */
1210 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1212 return msymbol_is_mips16 (sym
.minsym
);
1214 return is_mips16_addr (gdbarch
, memaddr
);
1217 /* Tell if the program counter value in MEMADDR is in a microMIPS function. */
1220 mips_pc_is_micromips (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1222 struct bound_minimal_symbol sym
;
1224 /* A flag indicating that this is a microMIPS function is stored by
1225 elfread.c in the high bit of the info field. Use this to decide
1226 if the function is microMIPS. Otherwise if bit 0 of the address
1227 is set, then ELF file flags will tell if this is a microMIPS
1229 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1231 return msymbol_is_micromips (sym
.minsym
);
1233 return is_micromips_addr (gdbarch
, memaddr
);
1236 /* Tell the ISA type of the function the program counter value in MEMADDR
1239 static enum mips_isa
1240 mips_pc_isa (struct gdbarch
*gdbarch
, CORE_ADDR memaddr
)
1242 struct bound_minimal_symbol sym
;
1244 /* A flag indicating that this is a MIPS16 or a microMIPS function
1245 is stored by elfread.c in the high bit of the info field. Use
1246 this to decide if the function is MIPS16 or microMIPS or normal
1247 MIPS. Otherwise if bit 0 of the address is set, then ELF file
1248 flags will tell if this is a MIPS16 or a microMIPS function. */
1249 sym
= lookup_minimal_symbol_by_pc (make_compact_addr (memaddr
));
1252 if (msymbol_is_micromips (sym
.minsym
))
1253 return ISA_MICROMIPS
;
1254 else if (msymbol_is_mips16 (sym
.minsym
))
1261 if (is_mips_addr (memaddr
))
1263 else if (is_micromips_addr (gdbarch
, memaddr
))
1264 return ISA_MICROMIPS
;
1270 /* Set the ISA bit correctly in the PC, used by DWARF-2 machinery.
1271 The need for comes from the ISA bit having been cleared, making
1272 addresses in FDE, range records, etc. referring to compressed code
1273 different to those in line information, the symbol table and finally
1274 the PC register. That in turn confuses many operations. */
1277 mips_adjust_dwarf2_addr (CORE_ADDR pc
)
1279 pc
= unmake_compact_addr (pc
);
1280 return mips_pc_is_mips (pc
) ? pc
: make_compact_addr (pc
);
1283 /* Recalculate the line record requested so that the resulting PC has
1284 the ISA bit set correctly, used by DWARF-2 machinery. The need for
1285 this adjustment comes from some records associated with compressed
1286 code having the ISA bit cleared, most notably at function prologue
1287 ends. The ISA bit is in this context retrieved from the minimal
1288 symbol covering the address requested, which in turn has been
1289 constructed from the binary's symbol table rather than DWARF-2
1290 information. The correct setting of the ISA bit is required for
1291 breakpoint addresses to correctly match against the stop PC.
1293 As line entries can specify relative address adjustments we need to
1294 keep track of the absolute value of the last line address recorded
1295 in line information, so that we can calculate the actual address to
1296 apply the ISA bit adjustment to. We use PC for this tracking and
1297 keep the original address there.
1299 As such relative address adjustments can be odd within compressed
1300 code we need to keep track of the last line address with the ISA
1301 bit adjustment applied too, as the original address may or may not
1302 have had the ISA bit set. We use ADJ_PC for this tracking and keep
1303 the adjusted address there.
1305 For relative address adjustments we then use these variables to
1306 calculate the address intended by line information, which will be
1307 PC-relative, and return an updated adjustment carrying ISA bit
1308 information, which will be ADJ_PC-relative. For absolute address
1309 adjustments we just return the same address that we store in ADJ_PC
1312 As the first line entry can be relative to an implied address value
1313 of 0 we need to have the initial address set up that we store in PC
1314 and ADJ_PC. This is arranged with a call from `dwarf_decode_lines_1'
1315 that sets PC to 0 and ADJ_PC accordingly, usually 0 as well. */
1318 mips_adjust_dwarf2_line (CORE_ADDR addr
, int rel
)
1320 static CORE_ADDR adj_pc
;
1321 static CORE_ADDR pc
;
1324 pc
= rel
? pc
+ addr
: addr
;
1325 isa_pc
= mips_adjust_dwarf2_addr (pc
);
1326 addr
= rel
? isa_pc
- adj_pc
: isa_pc
;
1331 /* Various MIPS16 thunk (aka stub or trampoline) names. */
1333 static const char mips_str_mips16_call_stub
[] = "__mips16_call_stub_";
1334 static const char mips_str_mips16_ret_stub
[] = "__mips16_ret_";
1335 static const char mips_str_call_fp_stub
[] = "__call_stub_fp_";
1336 static const char mips_str_call_stub
[] = "__call_stub_";
1337 static const char mips_str_fn_stub
[] = "__fn_stub_";
1339 /* This is used as a PIC thunk prefix. */
1341 static const char mips_str_pic
[] = ".pic.";
1343 /* Return non-zero if the PC is inside a call thunk (aka stub or
1344 trampoline) that should be treated as a temporary frame. */
1347 mips_in_frame_stub (CORE_ADDR pc
)
1349 CORE_ADDR start_addr
;
1352 /* Find the starting address of the function containing the PC. */
1353 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
1356 /* If the PC is in __mips16_call_stub_*, this is a call/return stub. */
1357 if (startswith (name
, mips_str_mips16_call_stub
))
1359 /* If the PC is in __call_stub_*, this is a call/return or a call stub. */
1360 if (startswith (name
, mips_str_call_stub
))
1362 /* If the PC is in __fn_stub_*, this is a call stub. */
1363 if (startswith (name
, mips_str_fn_stub
))
1366 return 0; /* Not a stub. */
1369 /* MIPS believes that the PC has a sign extended value. Perhaps the
1370 all registers should be sign extended for simplicity? */
1373 mips_read_pc (readable_regcache
*regcache
)
1375 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1378 regcache
->cooked_read (regnum
, &pc
);
1383 mips_unwind_pc (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1387 pc
= frame_unwind_register_signed (next_frame
, gdbarch_pc_regnum (gdbarch
));
1388 /* macro/2012-04-20: This hack skips over MIPS16 call thunks as
1389 intermediate frames. In this case we can get the caller's address
1390 from $ra, or if $ra contains an address within a thunk as well, then
1391 it must be in the return path of __mips16_call_stub_{s,d}{f,c}_{0..10}
1392 and thus the caller's address is in $s2. */
1393 if (frame_relative_level (next_frame
) >= 0 && mips_in_frame_stub (pc
))
1395 pc
= frame_unwind_register_signed
1396 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
1397 if (mips_in_frame_stub (pc
))
1398 pc
= frame_unwind_register_signed
1399 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
1405 mips_unwind_sp (struct gdbarch
*gdbarch
, struct frame_info
*next_frame
)
1407 return frame_unwind_register_signed
1408 (next_frame
, gdbarch_num_regs (gdbarch
) + MIPS_SP_REGNUM
);
1411 /* Assuming THIS_FRAME is a dummy, return the frame ID of that
1412 dummy frame. The frame ID's base needs to match the TOS value
1413 saved by save_dummy_frame_tos(), and the PC match the dummy frame's
1416 static struct frame_id
1417 mips_dummy_id (struct gdbarch
*gdbarch
, struct frame_info
*this_frame
)
1419 return frame_id_build
1420 (get_frame_register_signed (this_frame
,
1421 gdbarch_num_regs (gdbarch
)
1423 get_frame_pc (this_frame
));
1426 /* Implement the "write_pc" gdbarch method. */
1429 mips_write_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1431 int regnum
= gdbarch_pc_regnum (regcache
->arch ());
1433 regcache_cooked_write_unsigned (regcache
, regnum
, pc
);
1436 /* Fetch and return instruction from the specified location. Handle
1437 MIPS16/microMIPS as appropriate. */
1440 mips_fetch_instruction (struct gdbarch
*gdbarch
,
1441 enum mips_isa isa
, CORE_ADDR addr
, int *errp
)
1443 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1444 gdb_byte buf
[MIPS_INSN32_SIZE
];
1452 instlen
= MIPS_INSN16_SIZE
;
1453 addr
= unmake_compact_addr (addr
);
1456 instlen
= MIPS_INSN32_SIZE
;
1459 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1462 err
= target_read_memory (addr
, buf
, instlen
);
1468 memory_error (TARGET_XFER_E_IO
, addr
);
1471 return extract_unsigned_integer (buf
, instlen
, byte_order
);
1474 /* These are the fields of 32 bit mips instructions. */
1475 #define mips32_op(x) (x >> 26)
1476 #define itype_op(x) (x >> 26)
1477 #define itype_rs(x) ((x >> 21) & 0x1f)
1478 #define itype_rt(x) ((x >> 16) & 0x1f)
1479 #define itype_immediate(x) (x & 0xffff)
1481 #define jtype_op(x) (x >> 26)
1482 #define jtype_target(x) (x & 0x03ffffff)
1484 #define rtype_op(x) (x >> 26)
1485 #define rtype_rs(x) ((x >> 21) & 0x1f)
1486 #define rtype_rt(x) ((x >> 16) & 0x1f)
1487 #define rtype_rd(x) ((x >> 11) & 0x1f)
1488 #define rtype_shamt(x) ((x >> 6) & 0x1f)
1489 #define rtype_funct(x) (x & 0x3f)
1491 /* MicroMIPS instruction fields. */
1492 #define micromips_op(x) ((x) >> 10)
1494 /* 16-bit/32-bit-high-part instruction formats, B and S refer to the lowest
1495 bit and the size respectively of the field extracted. */
1496 #define b0s4_imm(x) ((x) & 0xf)
1497 #define b0s5_imm(x) ((x) & 0x1f)
1498 #define b0s5_reg(x) ((x) & 0x1f)
1499 #define b0s7_imm(x) ((x) & 0x7f)
1500 #define b0s10_imm(x) ((x) & 0x3ff)
1501 #define b1s4_imm(x) (((x) >> 1) & 0xf)
1502 #define b1s9_imm(x) (((x) >> 1) & 0x1ff)
1503 #define b2s3_cc(x) (((x) >> 2) & 0x7)
1504 #define b4s2_regl(x) (((x) >> 4) & 0x3)
1505 #define b5s5_op(x) (((x) >> 5) & 0x1f)
1506 #define b5s5_reg(x) (((x) >> 5) & 0x1f)
1507 #define b6s4_op(x) (((x) >> 6) & 0xf)
1508 #define b7s3_reg(x) (((x) >> 7) & 0x7)
1510 /* 32-bit instruction formats, B and S refer to the lowest bit and the size
1511 respectively of the field extracted. */
1512 #define b0s6_op(x) ((x) & 0x3f)
1513 #define b0s11_op(x) ((x) & 0x7ff)
1514 #define b0s12_imm(x) ((x) & 0xfff)
1515 #define b0s16_imm(x) ((x) & 0xffff)
1516 #define b0s26_imm(x) ((x) & 0x3ffffff)
1517 #define b6s10_ext(x) (((x) >> 6) & 0x3ff)
1518 #define b11s5_reg(x) (((x) >> 11) & 0x1f)
1519 #define b12s4_op(x) (((x) >> 12) & 0xf)
1521 /* Return the size in bytes of the instruction INSN encoded in the ISA
1525 mips_insn_size (enum mips_isa isa
, ULONGEST insn
)
1530 if ((micromips_op (insn
) & 0x4) == 0x4
1531 || (micromips_op (insn
) & 0x7) == 0x0)
1532 return 2 * MIPS_INSN16_SIZE
;
1534 return MIPS_INSN16_SIZE
;
1536 if ((insn
& 0xf800) == 0xf000)
1537 return 2 * MIPS_INSN16_SIZE
;
1539 return MIPS_INSN16_SIZE
;
1541 return MIPS_INSN32_SIZE
;
1543 internal_error (__FILE__
, __LINE__
, _("invalid ISA"));
1547 mips32_relative_offset (ULONGEST inst
)
1549 return ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 2;
1552 /* Determine the address of the next instruction executed after the INST
1553 floating condition branch instruction at PC. COUNT specifies the
1554 number of the floating condition bits tested by the branch. */
1557 mips32_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1558 ULONGEST inst
, CORE_ADDR pc
, int count
)
1560 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1561 int cnum
= (itype_rt (inst
) >> 2) & (count
- 1);
1562 int tf
= itype_rt (inst
) & 1;
1563 int mask
= (1 << count
) - 1;
1568 /* No way to handle; it'll most likely trap anyway. */
1571 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1572 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1574 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1575 pc
+= mips32_relative_offset (inst
);
1582 /* Return nonzero if the gdbarch is an Octeon series. */
1585 is_octeon (struct gdbarch
*gdbarch
)
1587 const struct bfd_arch_info
*info
= gdbarch_bfd_arch_info (gdbarch
);
1589 return (info
->mach
== bfd_mach_mips_octeon
1590 || info
->mach
== bfd_mach_mips_octeonp
1591 || info
->mach
== bfd_mach_mips_octeon2
);
1594 /* Return true if the OP represents the Octeon's BBIT instruction. */
1597 is_octeon_bbit_op (int op
, struct gdbarch
*gdbarch
)
1599 if (!is_octeon (gdbarch
))
1601 /* BBIT0 is encoded as LWC2: 110 010. */
1602 /* BBIT032 is encoded as LDC2: 110 110. */
1603 /* BBIT1 is encoded as SWC2: 111 010. */
1604 /* BBIT132 is encoded as SDC2: 111 110. */
1605 if (op
== 50 || op
== 54 || op
== 58 || op
== 62)
1611 /* Determine where to set a single step breakpoint while considering
1612 branch prediction. */
1615 mips32_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1617 struct gdbarch
*gdbarch
= regcache
->arch ();
1620 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
1621 op
= itype_op (inst
);
1622 if ((inst
& 0xe0000000) != 0) /* Not a special, jump or branch
1626 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
1637 goto greater_branch
;
1642 else if (op
== 17 && itype_rs (inst
) == 8)
1643 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
1644 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 1);
1645 else if (op
== 17 && itype_rs (inst
) == 9
1646 && (itype_rt (inst
) & 2) == 0)
1647 /* BC1ANY2F, BC1ANY2T: 010001 01001 xxx0x */
1648 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 2);
1649 else if (op
== 17 && itype_rs (inst
) == 10
1650 && (itype_rt (inst
) & 2) == 0)
1651 /* BC1ANY4F, BC1ANY4T: 010001 01010 xxx0x */
1652 pc
= mips32_bc1_pc (gdbarch
, regcache
, inst
, pc
+ 4, 4);
1655 /* The new PC will be alternate mode. */
1659 reg
= jtype_target (inst
) << 2;
1660 /* Add 1 to indicate 16-bit mode -- invert ISA mode. */
1661 pc
= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff) + reg
+ 1;
1663 else if (is_octeon_bbit_op (op
, gdbarch
))
1667 branch_if
= op
== 58 || op
== 62;
1668 bit
= itype_rt (inst
);
1670 /* Take into account the *32 instructions. */
1671 if (op
== 54 || op
== 62)
1674 if (((regcache_raw_get_signed (regcache
,
1675 itype_rs (inst
)) >> bit
) & 1)
1677 pc
+= mips32_relative_offset (inst
) + 4;
1679 pc
+= 8; /* After the delay slot. */
1683 pc
+= 4; /* Not a branch, next instruction is easy. */
1686 { /* This gets way messy. */
1688 /* Further subdivide into SPECIAL, REGIMM and other. */
1689 switch (op
& 0x07) /* Extract bits 28,27,26. */
1691 case 0: /* SPECIAL */
1692 op
= rtype_funct (inst
);
1697 /* Set PC to that address. */
1698 pc
= regcache_raw_get_signed (regcache
, rtype_rs (inst
));
1700 case 12: /* SYSCALL */
1702 struct gdbarch_tdep
*tdep
;
1704 tdep
= gdbarch_tdep (gdbarch
);
1705 if (tdep
->syscall_next_pc
!= NULL
)
1706 pc
= tdep
->syscall_next_pc (get_current_frame ());
1715 break; /* end SPECIAL */
1716 case 1: /* REGIMM */
1718 op
= itype_rt (inst
); /* branch condition */
1723 case 16: /* BLTZAL */
1724 case 18: /* BLTZALL */
1726 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) < 0)
1727 pc
+= mips32_relative_offset (inst
) + 4;
1729 pc
+= 8; /* after the delay slot */
1733 case 17: /* BGEZAL */
1734 case 19: /* BGEZALL */
1735 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) >= 0)
1736 pc
+= mips32_relative_offset (inst
) + 4;
1738 pc
+= 8; /* after the delay slot */
1740 case 0x1c: /* BPOSGE32 */
1741 case 0x1e: /* BPOSGE64 */
1743 if (itype_rs (inst
) == 0)
1745 unsigned int pos
= (op
& 2) ? 64 : 32;
1746 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1749 /* No way to handle; it'll most likely trap anyway. */
1752 if ((regcache_raw_get_unsigned (regcache
,
1753 dspctl
) & 0x7f) >= pos
)
1754 pc
+= mips32_relative_offset (inst
);
1759 /* All of the other instructions in the REGIMM category */
1764 break; /* end REGIMM */
1769 reg
= jtype_target (inst
) << 2;
1770 /* Upper four bits get never changed... */
1771 pc
= reg
+ ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
1774 case 4: /* BEQ, BEQL */
1776 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) ==
1777 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1778 pc
+= mips32_relative_offset (inst
) + 4;
1782 case 5: /* BNE, BNEL */
1784 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) !=
1785 regcache_raw_get_signed (regcache
, itype_rt (inst
)))
1786 pc
+= mips32_relative_offset (inst
) + 4;
1790 case 6: /* BLEZ, BLEZL */
1791 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) <= 0)
1792 pc
+= mips32_relative_offset (inst
) + 4;
1798 greater_branch
: /* BGTZ, BGTZL */
1799 if (regcache_raw_get_signed (regcache
, itype_rs (inst
)) > 0)
1800 pc
+= mips32_relative_offset (inst
) + 4;
1807 } /* mips32_next_pc */
1809 /* Extract the 7-bit signed immediate offset from the microMIPS instruction
1813 micromips_relative_offset7 (ULONGEST insn
)
1815 return ((b0s7_imm (insn
) ^ 0x40) - 0x40) << 1;
1818 /* Extract the 10-bit signed immediate offset from the microMIPS instruction
1822 micromips_relative_offset10 (ULONGEST insn
)
1824 return ((b0s10_imm (insn
) ^ 0x200) - 0x200) << 1;
1827 /* Extract the 16-bit signed immediate offset from the microMIPS instruction
1831 micromips_relative_offset16 (ULONGEST insn
)
1833 return ((b0s16_imm (insn
) ^ 0x8000) - 0x8000) << 1;
1836 /* Return the size in bytes of the microMIPS instruction at the address PC. */
1839 micromips_pc_insn_size (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1843 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1844 return mips_insn_size (ISA_MICROMIPS
, insn
);
1847 /* Calculate the address of the next microMIPS instruction to execute
1848 after the INSN coprocessor 1 conditional branch instruction at the
1849 address PC. COUNT denotes the number of coprocessor condition bits
1850 examined by the branch. */
1853 micromips_bc1_pc (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
1854 ULONGEST insn
, CORE_ADDR pc
, int count
)
1856 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
1857 int cnum
= b2s3_cc (insn
>> 16) & (count
- 1);
1858 int tf
= b5s5_op (insn
>> 16) & 1;
1859 int mask
= (1 << count
) - 1;
1864 /* No way to handle; it'll most likely trap anyway. */
1867 fcs
= regcache_raw_get_unsigned (regcache
, fcsr
);
1868 cond
= ((fcs
>> 24) & 0xfe) | ((fcs
>> 23) & 0x01);
1870 if (((cond
>> cnum
) & mask
) != mask
* !tf
)
1871 pc
+= micromips_relative_offset16 (insn
);
1873 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1878 /* Calculate the address of the next microMIPS instruction to execute
1879 after the instruction at the address PC. */
1882 micromips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
1884 struct gdbarch
*gdbarch
= regcache
->arch ();
1887 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1888 pc
+= MIPS_INSN16_SIZE
;
1889 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
1891 /* 32-bit instructions. */
1892 case 2 * MIPS_INSN16_SIZE
:
1894 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
1895 pc
+= MIPS_INSN16_SIZE
;
1896 switch (micromips_op (insn
>> 16))
1898 case 0x00: /* POOL32A: bits 000000 */
1899 switch (b0s6_op (insn
))
1901 case 0x3c: /* POOL32Axf: bits 000000 ... 111100 */
1902 switch (b6s10_ext (insn
))
1904 case 0x3c: /* JALR: 000000 0000111100 111100 */
1905 case 0x7c: /* JALR.HB: 000000 0001111100 111100 */
1906 case 0x13c: /* JALRS: 000000 0100111100 111100 */
1907 case 0x17c: /* JALRS.HB: 000000 0101111100 111100 */
1908 pc
= regcache_raw_get_signed (regcache
,
1909 b0s5_reg (insn
>> 16));
1911 case 0x22d: /* SYSCALL: 000000 1000101101 111100 */
1913 struct gdbarch_tdep
*tdep
;
1915 tdep
= gdbarch_tdep (gdbarch
);
1916 if (tdep
->syscall_next_pc
!= NULL
)
1917 pc
= tdep
->syscall_next_pc (get_current_frame ());
1925 case 0x10: /* POOL32I: bits 010000 */
1926 switch (b5s5_op (insn
>> 16))
1928 case 0x00: /* BLTZ: bits 010000 00000 */
1929 case 0x01: /* BLTZAL: bits 010000 00001 */
1930 case 0x11: /* BLTZALS: bits 010000 10001 */
1931 if (regcache_raw_get_signed (regcache
,
1932 b0s5_reg (insn
>> 16)) < 0)
1933 pc
+= micromips_relative_offset16 (insn
);
1935 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1938 case 0x02: /* BGEZ: bits 010000 00010 */
1939 case 0x03: /* BGEZAL: bits 010000 00011 */
1940 case 0x13: /* BGEZALS: bits 010000 10011 */
1941 if (regcache_raw_get_signed (regcache
,
1942 b0s5_reg (insn
>> 16)) >= 0)
1943 pc
+= micromips_relative_offset16 (insn
);
1945 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1948 case 0x04: /* BLEZ: bits 010000 00100 */
1949 if (regcache_raw_get_signed (regcache
,
1950 b0s5_reg (insn
>> 16)) <= 0)
1951 pc
+= micromips_relative_offset16 (insn
);
1953 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1956 case 0x05: /* BNEZC: bits 010000 00101 */
1957 if (regcache_raw_get_signed (regcache
,
1958 b0s5_reg (insn
>> 16)) != 0)
1959 pc
+= micromips_relative_offset16 (insn
);
1962 case 0x06: /* BGTZ: bits 010000 00110 */
1963 if (regcache_raw_get_signed (regcache
,
1964 b0s5_reg (insn
>> 16)) > 0)
1965 pc
+= micromips_relative_offset16 (insn
);
1967 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
1970 case 0x07: /* BEQZC: bits 010000 00111 */
1971 if (regcache_raw_get_signed (regcache
,
1972 b0s5_reg (insn
>> 16)) == 0)
1973 pc
+= micromips_relative_offset16 (insn
);
1976 case 0x14: /* BC2F: bits 010000 10100 xxx00 */
1977 case 0x15: /* BC2T: bits 010000 10101 xxx00 */
1978 if (((insn
>> 16) & 0x3) == 0x0)
1979 /* BC2F, BC2T: don't know how to handle these. */
1983 case 0x1a: /* BPOSGE64: bits 010000 11010 */
1984 case 0x1b: /* BPOSGE32: bits 010000 11011 */
1986 unsigned int pos
= (b5s5_op (insn
>> 16) & 1) ? 32 : 64;
1987 int dspctl
= mips_regnum (gdbarch
)->dspctl
;
1990 /* No way to handle; it'll most likely trap anyway. */
1993 if ((regcache_raw_get_unsigned (regcache
,
1994 dspctl
) & 0x7f) >= pos
)
1995 pc
+= micromips_relative_offset16 (insn
);
1997 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2001 case 0x1c: /* BC1F: bits 010000 11100 xxx00 */
2002 /* BC1ANY2F: bits 010000 11100 xxx01 */
2003 case 0x1d: /* BC1T: bits 010000 11101 xxx00 */
2004 /* BC1ANY2T: bits 010000 11101 xxx01 */
2005 if (((insn
>> 16) & 0x2) == 0x0)
2006 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
,
2007 ((insn
>> 16) & 0x1) + 1);
2010 case 0x1e: /* BC1ANY4F: bits 010000 11110 xxx01 */
2011 case 0x1f: /* BC1ANY4T: bits 010000 11111 xxx01 */
2012 if (((insn
>> 16) & 0x3) == 0x1)
2013 pc
= micromips_bc1_pc (gdbarch
, regcache
, insn
, pc
, 4);
2018 case 0x1d: /* JALS: bits 011101 */
2019 case 0x35: /* J: bits 110101 */
2020 case 0x3d: /* JAL: bits 111101 */
2021 pc
= ((pc
| 0x7fffffe) ^ 0x7fffffe) | (b0s26_imm (insn
) << 1);
2024 case 0x25: /* BEQ: bits 100101 */
2025 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2026 == regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2027 pc
+= micromips_relative_offset16 (insn
);
2029 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2032 case 0x2d: /* BNE: bits 101101 */
2033 if (regcache_raw_get_signed (regcache
, b0s5_reg (insn
>> 16))
2034 != regcache_raw_get_signed (regcache
, b5s5_reg (insn
>> 16)))
2035 pc
+= micromips_relative_offset16 (insn
);
2037 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2040 case 0x3c: /* JALX: bits 111100 */
2041 pc
= ((pc
| 0xfffffff) ^ 0xfffffff) | (b0s26_imm (insn
) << 2);
2046 /* 16-bit instructions. */
2047 case MIPS_INSN16_SIZE
:
2048 switch (micromips_op (insn
))
2050 case 0x11: /* POOL16C: bits 010001 */
2051 if ((b5s5_op (insn
) & 0x1c) == 0xc)
2052 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
2053 pc
= regcache_raw_get_signed (regcache
, b0s5_reg (insn
));
2054 else if (b5s5_op (insn
) == 0x18)
2055 /* JRADDIUSP: bits 010001 11000 */
2056 pc
= regcache_raw_get_signed (regcache
, MIPS_RA_REGNUM
);
2059 case 0x23: /* BEQZ16: bits 100011 */
2061 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2063 if (regcache_raw_get_signed (regcache
, rs
) == 0)
2064 pc
+= micromips_relative_offset7 (insn
);
2066 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2070 case 0x2b: /* BNEZ16: bits 101011 */
2072 int rs
= mips_reg3_to_reg
[b7s3_reg (insn
)];
2074 if (regcache_raw_get_signed (regcache
, rs
) != 0)
2075 pc
+= micromips_relative_offset7 (insn
);
2077 pc
+= micromips_pc_insn_size (gdbarch
, pc
);
2081 case 0x33: /* B16: bits 110011 */
2082 pc
+= micromips_relative_offset10 (insn
);
2091 /* Decoding the next place to set a breakpoint is irregular for the
2092 mips 16 variant, but fortunately, there fewer instructions. We have
2093 to cope ith extensions for 16 bit instructions and a pair of actual
2094 32 bit instructions. We dont want to set a single step instruction
2095 on the extend instruction either. */
2097 /* Lots of mips16 instruction formats */
2098 /* Predicting jumps requires itype,ritype,i8type
2099 and their extensions extItype,extritype,extI8type. */
2100 enum mips16_inst_fmts
2102 itype
, /* 0 immediate 5,10 */
2103 ritype
, /* 1 5,3,8 */
2104 rrtype
, /* 2 5,3,3,5 */
2105 rritype
, /* 3 5,3,3,5 */
2106 rrrtype
, /* 4 5,3,3,3,2 */
2107 rriatype
, /* 5 5,3,3,1,4 */
2108 shifttype
, /* 6 5,3,3,3,2 */
2109 i8type
, /* 7 5,3,8 */
2110 i8movtype
, /* 8 5,3,3,5 */
2111 i8mov32rtype
, /* 9 5,3,5,3 */
2112 i64type
, /* 10 5,3,8 */
2113 ri64type
, /* 11 5,3,3,5 */
2114 jalxtype
, /* 12 5,1,5,5,16 - a 32 bit instruction */
2115 exiItype
, /* 13 5,6,5,5,1,1,1,1,1,1,5 */
2116 extRitype
, /* 14 5,6,5,5,3,1,1,1,5 */
2117 extRRItype
, /* 15 5,5,5,5,3,3,5 */
2118 extRRIAtype
, /* 16 5,7,4,5,3,3,1,4 */
2119 EXTshifttype
, /* 17 5,5,1,1,1,1,1,1,5,3,3,1,1,1,2 */
2120 extI8type
, /* 18 5,6,5,5,3,1,1,1,5 */
2121 extI64type
, /* 19 5,6,5,5,3,1,1,1,5 */
2122 extRi64type
, /* 20 5,6,5,5,3,3,5 */
2123 extshift64type
/* 21 5,5,1,1,1,1,1,1,5,1,1,1,3,5 */
2125 /* I am heaping all the fields of the formats into one structure and
2126 then, only the fields which are involved in instruction extension. */
2130 unsigned int regx
; /* Function in i8 type. */
2135 /* The EXT-I, EXT-ri nad EXT-I8 instructions all have the same format
2136 for the bits which make up the immediate extension. */
2139 extended_offset (unsigned int extension
)
2143 value
= (extension
>> 16) & 0x1f; /* Extract 15:11. */
2145 value
|= (extension
>> 21) & 0x3f; /* Extract 10:5. */
2147 value
|= extension
& 0x1f; /* Extract 4:0. */
2152 /* Only call this function if you know that this is an extendable
2153 instruction. It won't malfunction, but why make excess remote memory
2154 references? If the immediate operands get sign extended or something,
2155 do it after the extension is performed. */
2156 /* FIXME: Every one of these cases needs to worry about sign extension
2157 when the offset is to be used in relative addressing. */
2160 fetch_mips_16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2162 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2165 pc
= unmake_compact_addr (pc
); /* Clear the low order bit. */
2166 target_read_memory (pc
, buf
, 2);
2167 return extract_unsigned_integer (buf
, 2, byte_order
);
2171 unpack_mips16 (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
2172 unsigned int extension
,
2174 enum mips16_inst_fmts insn_format
, struct upk_mips16
*upk
)
2179 switch (insn_format
)
2186 value
= extended_offset ((extension
<< 16) | inst
);
2187 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2191 value
= inst
& 0x7ff;
2192 value
= (value
^ 0x400) - 0x400; /* Sign-extend. */
2201 { /* A register identifier and an offset. */
2202 /* Most of the fields are the same as I type but the
2203 immediate value is of a different length. */
2207 value
= extended_offset ((extension
<< 16) | inst
);
2208 value
= (value
^ 0x8000) - 0x8000; /* Sign-extend. */
2212 value
= inst
& 0xff; /* 8 bits */
2213 value
= (value
^ 0x80) - 0x80; /* Sign-extend. */
2216 regx
= (inst
>> 8) & 0x07; /* i8 funct */
2222 unsigned long value
;
2223 unsigned int nexthalf
;
2224 value
= ((inst
& 0x1f) << 5) | ((inst
>> 5) & 0x1f);
2225 value
= value
<< 16;
2226 nexthalf
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
+ 2, NULL
);
2227 /* Low bit still set. */
2235 internal_error (__FILE__
, __LINE__
, _("bad switch"));
2237 upk
->offset
= offset
;
2243 /* Calculate the destination of a branch whose 16-bit opcode word is at PC,
2244 and having a signed 16-bit OFFSET. */
2247 add_offset_16 (CORE_ADDR pc
, int offset
)
2249 return pc
+ (offset
<< 1) + 2;
2253 extended_mips16_next_pc (regcache
*regcache
, CORE_ADDR pc
,
2254 unsigned int extension
, unsigned int insn
)
2256 struct gdbarch
*gdbarch
= regcache
->arch ();
2257 int op
= (insn
>> 11);
2260 case 2: /* Branch */
2262 struct upk_mips16 upk
;
2263 unpack_mips16 (gdbarch
, pc
, extension
, insn
, itype
, &upk
);
2264 pc
= add_offset_16 (pc
, upk
.offset
);
2267 case 3: /* JAL , JALX - Watch out, these are 32 bit
2270 struct upk_mips16 upk
;
2271 unpack_mips16 (gdbarch
, pc
, extension
, insn
, jalxtype
, &upk
);
2272 pc
= ((pc
+ 2) & (~(CORE_ADDR
) 0x0fffffff)) | (upk
.offset
<< 2);
2273 if ((insn
>> 10) & 0x01) /* Exchange mode */
2274 pc
= pc
& ~0x01; /* Clear low bit, indicate 32 bit mode. */
2281 struct upk_mips16 upk
;
2283 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2284 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2286 pc
= add_offset_16 (pc
, upk
.offset
);
2293 struct upk_mips16 upk
;
2295 unpack_mips16 (gdbarch
, pc
, extension
, insn
, ritype
, &upk
);
2296 reg
= regcache_raw_get_signed (regcache
, mips_reg3_to_reg
[upk
.regx
]);
2298 pc
= add_offset_16 (pc
, upk
.offset
);
2303 case 12: /* I8 Formats btez btnez */
2305 struct upk_mips16 upk
;
2307 unpack_mips16 (gdbarch
, pc
, extension
, insn
, i8type
, &upk
);
2308 /* upk.regx contains the opcode */
2309 /* Test register is 24 */
2310 reg
= regcache_raw_get_signed (regcache
, 24);
2311 if (((upk
.regx
== 0) && (reg
== 0)) /* BTEZ */
2312 || ((upk
.regx
== 1) && (reg
!= 0))) /* BTNEZ */
2313 pc
= add_offset_16 (pc
, upk
.offset
);
2318 case 29: /* RR Formats JR, JALR, JALR-RA */
2320 struct upk_mips16 upk
;
2321 /* upk.fmt = rrtype; */
2326 upk
.regx
= (insn
>> 8) & 0x07;
2327 upk
.regy
= (insn
>> 5) & 0x07;
2328 if ((upk
.regy
& 1) == 0)
2329 reg
= mips_reg3_to_reg
[upk
.regx
];
2331 reg
= 31; /* Function return instruction. */
2332 pc
= regcache_raw_get_signed (regcache
, reg
);
2339 /* This is an instruction extension. Fetch the real instruction
2340 (which follows the extension) and decode things based on
2344 pc
= extended_mips16_next_pc (regcache
, pc
, insn
,
2345 fetch_mips_16 (gdbarch
, pc
));
2358 mips16_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2360 struct gdbarch
*gdbarch
= regcache
->arch ();
2361 unsigned int insn
= fetch_mips_16 (gdbarch
, pc
);
2362 return extended_mips16_next_pc (regcache
, pc
, 0, insn
);
2365 /* The mips_next_pc function supports single_step when the remote
2366 target monitor or stub is not developed enough to do a single_step.
2367 It works by decoding the current instruction and predicting where a
2368 branch will go. This isn't hard because all the data is available.
2369 The MIPS32, MIPS16 and microMIPS variants are quite different. */
2371 mips_next_pc (struct regcache
*regcache
, CORE_ADDR pc
)
2373 struct gdbarch
*gdbarch
= regcache
->arch ();
2375 if (mips_pc_is_mips16 (gdbarch
, pc
))
2376 return mips16_next_pc (regcache
, pc
);
2377 else if (mips_pc_is_micromips (gdbarch
, pc
))
2378 return micromips_next_pc (regcache
, pc
);
2380 return mips32_next_pc (regcache
, pc
);
2383 /* Return non-zero if the MIPS16 instruction INSN is a compact branch
2387 mips16_instruction_is_compact_branch (unsigned short insn
)
2389 switch (insn
& 0xf800)
2392 return (insn
& 0x009f) == 0x80; /* JALRC/JRC */
2394 return (insn
& 0x0600) == 0; /* BTNEZ/BTEQZ */
2395 case 0x2800: /* BNEZ */
2396 case 0x2000: /* BEQZ */
2397 case 0x1000: /* B */
2404 /* Return non-zero if the microMIPS instruction INSN is a compact branch
2408 micromips_instruction_is_compact_branch (unsigned short insn
)
2410 switch (micromips_op (insn
))
2412 case 0x11: /* POOL16C: bits 010001 */
2413 return (b5s5_op (insn
) == 0x18
2414 /* JRADDIUSP: bits 010001 11000 */
2415 || b5s5_op (insn
) == 0xd);
2416 /* JRC: bits 010011 01101 */
2417 case 0x10: /* POOL32I: bits 010000 */
2418 return (b5s5_op (insn
) & 0x1d) == 0x5;
2419 /* BEQZC/BNEZC: bits 010000 001x1 */
2425 struct mips_frame_cache
2428 trad_frame_saved_reg
*saved_regs
;
2431 /* Set a register's saved stack address in temp_saved_regs. If an
2432 address has already been set for this register, do nothing; this
2433 way we will only recognize the first save of a given register in a
2436 For simplicity, save the address in both [0 .. gdbarch_num_regs) and
2437 [gdbarch_num_regs .. 2*gdbarch_num_regs).
2438 Strictly speaking, only the second range is used as it is only second
2439 range (the ABI instead of ISA registers) that comes into play when finding
2440 saved registers in a frame. */
2443 set_reg_offset (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
,
2444 int regnum
, CORE_ADDR offset
)
2446 if (this_cache
!= NULL
2447 && this_cache
->saved_regs
[regnum
].is_realreg ()
2448 && this_cache
->saved_regs
[regnum
].realreg () == regnum
)
2450 this_cache
->saved_regs
[regnum
+ 0
2451 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2452 this_cache
->saved_regs
[regnum
+ 1
2453 * gdbarch_num_regs (gdbarch
)].set_addr (offset
);
2458 /* Fetch the immediate value from a MIPS16 instruction.
2459 If the previous instruction was an EXTEND, use it to extend
2460 the upper bits of the immediate value. This is a helper function
2461 for mips16_scan_prologue. */
2464 mips16_get_imm (unsigned short prev_inst
, /* previous instruction */
2465 unsigned short inst
, /* current instruction */
2466 int nbits
, /* number of bits in imm field */
2467 int scale
, /* scale factor to be applied to imm */
2468 int is_signed
) /* is the imm field signed? */
2472 if ((prev_inst
& 0xf800) == 0xf000) /* prev instruction was EXTEND? */
2474 offset
= ((prev_inst
& 0x1f) << 11) | (prev_inst
& 0x7e0);
2475 if (offset
& 0x8000) /* check for negative extend */
2476 offset
= 0 - (0x10000 - (offset
& 0xffff));
2477 return offset
| (inst
& 0x1f);
2481 int max_imm
= 1 << nbits
;
2482 int mask
= max_imm
- 1;
2483 int sign_bit
= max_imm
>> 1;
2485 offset
= inst
& mask
;
2486 if (is_signed
&& (offset
& sign_bit
))
2487 offset
= 0 - (max_imm
- offset
);
2488 return offset
* scale
;
2493 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
2494 the associated FRAME_CACHE if not null.
2495 Return the address of the first instruction past the prologue. */
2498 mips16_scan_prologue (struct gdbarch
*gdbarch
,
2499 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2500 struct frame_info
*this_frame
,
2501 struct mips_frame_cache
*this_cache
)
2503 int prev_non_prologue_insn
= 0;
2504 int this_non_prologue_insn
;
2505 int non_prologue_insns
= 0;
2508 CORE_ADDR frame_addr
= 0; /* Value of $r17, used as frame pointer. */
2510 long frame_offset
= 0; /* Size of stack frame. */
2511 long frame_adjust
= 0; /* Offset of FP from SP. */
2512 int frame_reg
= MIPS_SP_REGNUM
;
2513 unsigned short prev_inst
= 0; /* saved copy of previous instruction. */
2514 unsigned inst
= 0; /* current instruction */
2515 unsigned entry_inst
= 0; /* the entry instruction */
2516 unsigned save_inst
= 0; /* the save instruction */
2517 int prev_delay_slot
= 0;
2521 int extend_bytes
= 0;
2522 int prev_extend_bytes
= 0;
2523 CORE_ADDR end_prologue_addr
;
2525 /* Can be called when there's no process, and hence when there's no
2527 if (this_frame
!= NULL
)
2528 sp
= get_frame_register_signed (this_frame
,
2529 gdbarch_num_regs (gdbarch
)
2534 if (limit_pc
> start_pc
+ 200)
2535 limit_pc
= start_pc
+ 200;
2538 /* Permit at most one non-prologue non-control-transfer instruction
2539 in the middle which may have been reordered by the compiler for
2541 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN16_SIZE
)
2543 this_non_prologue_insn
= 0;
2546 /* Save the previous instruction. If it's an EXTEND, we'll extract
2547 the immediate offset extension from it in mips16_get_imm. */
2550 /* Fetch and decode the instruction. */
2551 inst
= (unsigned short) mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
2554 /* Normally we ignore extend instructions. However, if it is
2555 not followed by a valid prologue instruction, then this
2556 instruction is not part of the prologue either. We must
2557 remember in this case to adjust the end_prologue_addr back
2559 if ((inst
& 0xf800) == 0xf000) /* extend */
2561 extend_bytes
= MIPS_INSN16_SIZE
;
2565 prev_extend_bytes
= extend_bytes
;
2568 if ((inst
& 0xff00) == 0x6300 /* addiu sp */
2569 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
2571 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 1);
2572 if (offset
< 0) /* Negative stack adjustment? */
2573 frame_offset
-= offset
;
2575 /* Exit loop if a positive stack adjustment is found, which
2576 usually means that the stack cleanup code in the function
2577 epilogue is reached. */
2580 else if ((inst
& 0xf800) == 0xd000) /* sw reg,n($sp) */
2582 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2583 reg
= mips_reg3_to_reg
[(inst
& 0x700) >> 8];
2584 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2586 else if ((inst
& 0xff00) == 0xf900) /* sd reg,n($sp) */
2588 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2589 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2590 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2592 else if ((inst
& 0xff00) == 0x6200) /* sw $ra,n($sp) */
2594 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2595 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2597 else if ((inst
& 0xff00) == 0xfa00) /* sd $ra,n($sp) */
2599 offset
= mips16_get_imm (prev_inst
, inst
, 8, 8, 0);
2600 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2602 else if (inst
== 0x673d) /* move $s1, $sp */
2607 else if ((inst
& 0xff00) == 0x0100) /* addiu $s1,sp,n */
2609 offset
= mips16_get_imm (prev_inst
, inst
, 8, 4, 0);
2610 frame_addr
= sp
+ offset
;
2612 frame_adjust
= offset
;
2614 else if ((inst
& 0xFF00) == 0xd900) /* sw reg,offset($s1) */
2616 offset
= mips16_get_imm (prev_inst
, inst
, 5, 4, 0);
2617 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2618 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2620 else if ((inst
& 0xFF00) == 0x7900) /* sd reg,offset($s1) */
2622 offset
= mips16_get_imm (prev_inst
, inst
, 5, 8, 0);
2623 reg
= mips_reg3_to_reg
[(inst
& 0xe0) >> 5];
2624 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
2626 else if ((inst
& 0xf81f) == 0xe809
2627 && (inst
& 0x700) != 0x700) /* entry */
2628 entry_inst
= inst
; /* Save for later processing. */
2629 else if ((inst
& 0xff80) == 0x6480) /* save */
2631 save_inst
= inst
; /* Save for later processing. */
2632 if (prev_extend_bytes
) /* extend */
2633 save_inst
|= prev_inst
<< 16;
2635 else if ((inst
& 0xff1c) == 0x6704) /* move reg,$a0-$a3 */
2637 /* This instruction is part of the prologue, but we don't
2638 need to do anything special to handle it. */
2640 else if (mips16_instruction_has_delay_slot (inst
, 0))
2641 /* JAL/JALR/JALX/JR */
2643 /* The instruction in the delay slot can be a part
2644 of the prologue, so move forward once more. */
2646 if (mips16_instruction_has_delay_slot (inst
, 1))
2649 prev_extend_bytes
= MIPS_INSN16_SIZE
;
2650 cur_pc
+= MIPS_INSN16_SIZE
; /* 32-bit instruction */
2655 this_non_prologue_insn
= 1;
2658 non_prologue_insns
+= this_non_prologue_insn
;
2660 /* A jump or branch, or enough non-prologue insns seen? If so,
2661 then we must have reached the end of the prologue by now. */
2662 if (prev_delay_slot
|| non_prologue_insns
> 1
2663 || mips16_instruction_is_compact_branch (inst
))
2666 prev_non_prologue_insn
= this_non_prologue_insn
;
2667 prev_delay_slot
= in_delay_slot
;
2668 prev_pc
= cur_pc
- prev_extend_bytes
;
2671 /* The entry instruction is typically the first instruction in a function,
2672 and it stores registers at offsets relative to the value of the old SP
2673 (before the prologue). But the value of the sp parameter to this
2674 function is the new SP (after the prologue has been executed). So we
2675 can't calculate those offsets until we've seen the entire prologue,
2676 and can calculate what the old SP must have been. */
2677 if (entry_inst
!= 0)
2679 int areg_count
= (entry_inst
>> 8) & 7;
2680 int sreg_count
= (entry_inst
>> 6) & 3;
2682 /* The entry instruction always subtracts 32 from the SP. */
2685 /* Now we can calculate what the SP must have been at the
2686 start of the function prologue. */
2689 /* Check if a0-a3 were saved in the caller's argument save area. */
2690 for (reg
= 4, offset
= 0; reg
< areg_count
+ 4; reg
++)
2692 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2693 offset
+= mips_abi_regsize (gdbarch
);
2696 /* Check if the ra register was pushed on the stack. */
2698 if (entry_inst
& 0x20)
2700 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2701 offset
-= mips_abi_regsize (gdbarch
);
2704 /* Check if the s0 and s1 registers were pushed on the stack. */
2705 for (reg
= 16; reg
< sreg_count
+ 16; reg
++)
2707 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2708 offset
-= mips_abi_regsize (gdbarch
);
2712 /* The SAVE instruction is similar to ENTRY, except that defined by the
2713 MIPS16e ASE of the MIPS Architecture. Unlike with ENTRY though, the
2714 size of the frame is specified as an immediate field of instruction
2715 and an extended variation exists which lets additional registers and
2716 frame space to be specified. The instruction always treats registers
2717 as 32-bit so its usefulness for 64-bit ABIs is questionable. */
2718 if (save_inst
!= 0 && mips_abi_regsize (gdbarch
) == 4)
2720 static int args_table
[16] = {
2721 0, 0, 0, 0, 1, 1, 1, 1,
2722 2, 2, 2, 0, 3, 3, 4, -1,
2724 static int astatic_table
[16] = {
2725 0, 1, 2, 3, 0, 1, 2, 3,
2726 0, 1, 2, 4, 0, 1, 0, -1,
2728 int aregs
= (save_inst
>> 16) & 0xf;
2729 int xsregs
= (save_inst
>> 24) & 0x7;
2730 int args
= args_table
[aregs
];
2731 int astatic
= astatic_table
[aregs
];
2736 warning (_("Invalid number of argument registers encoded in SAVE."));
2741 warning (_("Invalid number of static registers encoded in SAVE."));
2745 /* For standard SAVE the frame size of 0 means 128. */
2746 frame_size
= ((save_inst
>> 16) & 0xf0) | (save_inst
& 0xf);
2747 if (frame_size
== 0 && (save_inst
>> 16) == 0)
2750 frame_offset
+= frame_size
;
2752 /* Now we can calculate what the SP must have been at the
2753 start of the function prologue. */
2756 /* Check if A0-A3 were saved in the caller's argument save area. */
2757 for (reg
= MIPS_A0_REGNUM
, offset
= 0; reg
< args
+ 4; reg
++)
2759 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2760 offset
+= mips_abi_regsize (gdbarch
);
2765 /* Check if the RA register was pushed on the stack. */
2766 if (save_inst
& 0x40)
2768 set_reg_offset (gdbarch
, this_cache
, MIPS_RA_REGNUM
, sp
+ offset
);
2769 offset
-= mips_abi_regsize (gdbarch
);
2772 /* Check if the S8 register was pushed on the stack. */
2775 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ offset
);
2776 offset
-= mips_abi_regsize (gdbarch
);
2779 /* Check if S2-S7 were pushed on the stack. */
2780 for (reg
= 18 + xsregs
- 1; reg
> 18 - 1; reg
--)
2782 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2783 offset
-= mips_abi_regsize (gdbarch
);
2786 /* Check if the S1 register was pushed on the stack. */
2787 if (save_inst
& 0x10)
2789 set_reg_offset (gdbarch
, this_cache
, 17, sp
+ offset
);
2790 offset
-= mips_abi_regsize (gdbarch
);
2792 /* Check if the S0 register was pushed on the stack. */
2793 if (save_inst
& 0x20)
2795 set_reg_offset (gdbarch
, this_cache
, 16, sp
+ offset
);
2796 offset
-= mips_abi_regsize (gdbarch
);
2799 /* Check if A0-A3 were pushed on the stack. */
2800 for (reg
= MIPS_A0_REGNUM
+ 3; reg
> MIPS_A0_REGNUM
+ 3 - astatic
; reg
--)
2802 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
2803 offset
-= mips_abi_regsize (gdbarch
);
2807 if (this_cache
!= NULL
)
2810 (get_frame_register_signed (this_frame
,
2811 gdbarch_num_regs (gdbarch
) + frame_reg
)
2812 + frame_offset
- frame_adjust
);
2813 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
2814 be able to get rid of the assignment below, evetually. But it's
2815 still needed for now. */
2816 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2817 + mips_regnum (gdbarch
)->pc
]
2818 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
2821 /* Set end_prologue_addr to the address of the instruction immediately
2822 after the last one we scanned. Unless the last one looked like a
2823 non-prologue instruction (and we looked ahead), in which case use
2824 its address instead. */
2825 end_prologue_addr
= (prev_non_prologue_insn
|| prev_delay_slot
2826 ? prev_pc
: cur_pc
- prev_extend_bytes
);
2828 return end_prologue_addr
;
2831 /* Heuristic unwinder for 16-bit MIPS instruction set (aka MIPS16).
2832 Procedures that use the 32-bit instruction set are handled by the
2833 mips_insn32 unwinder. */
2835 static struct mips_frame_cache
*
2836 mips_insn16_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
2838 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2839 struct mips_frame_cache
*cache
;
2841 if ((*this_cache
) != NULL
)
2842 return (struct mips_frame_cache
*) (*this_cache
);
2843 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
2844 (*this_cache
) = cache
;
2845 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
2847 /* Analyze the function prologue. */
2849 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
2850 CORE_ADDR start_addr
;
2852 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
2853 if (start_addr
== 0)
2854 start_addr
= heuristic_proc_start (gdbarch
, pc
);
2855 /* We can't analyze the prologue if we couldn't find the begining
2857 if (start_addr
== 0)
2860 mips16_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
2861 (struct mips_frame_cache
*) *this_cache
);
2864 /* gdbarch_sp_regnum contains the value and not the address. */
2865 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
2866 + MIPS_SP_REGNUM
].set_value (cache
->base
);
2868 return (struct mips_frame_cache
*) (*this_cache
);
2872 mips_insn16_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
2873 struct frame_id
*this_id
)
2875 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2877 /* This marks the outermost frame. */
2878 if (info
->base
== 0)
2880 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
2883 static struct value
*
2884 mips_insn16_frame_prev_register (struct frame_info
*this_frame
,
2885 void **this_cache
, int regnum
)
2887 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2889 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
2893 mips_insn16_frame_sniffer (const struct frame_unwind
*self
,
2894 struct frame_info
*this_frame
, void **this_cache
)
2896 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2897 CORE_ADDR pc
= get_frame_pc (this_frame
);
2898 if (mips_pc_is_mips16 (gdbarch
, pc
))
2903 static const struct frame_unwind mips_insn16_frame_unwind
=
2906 default_frame_unwind_stop_reason
,
2907 mips_insn16_frame_this_id
,
2908 mips_insn16_frame_prev_register
,
2910 mips_insn16_frame_sniffer
2914 mips_insn16_frame_base_address (struct frame_info
*this_frame
,
2917 struct mips_frame_cache
*info
= mips_insn16_frame_cache (this_frame
,
2922 static const struct frame_base mips_insn16_frame_base
=
2924 &mips_insn16_frame_unwind
,
2925 mips_insn16_frame_base_address
,
2926 mips_insn16_frame_base_address
,
2927 mips_insn16_frame_base_address
2930 static const struct frame_base
*
2931 mips_insn16_frame_base_sniffer (struct frame_info
*this_frame
)
2933 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2934 CORE_ADDR pc
= get_frame_pc (this_frame
);
2935 if (mips_pc_is_mips16 (gdbarch
, pc
))
2936 return &mips_insn16_frame_base
;
2941 /* Decode a 9-bit signed immediate argument of ADDIUSP -- -2 is mapped
2942 to -258, -1 -- to -257, 0 -- to 256, 1 -- to 257 and other values are
2943 interpreted directly, and then multiplied by 4. */
2946 micromips_decode_imm9 (int imm
)
2948 imm
= (imm
^ 0x100) - 0x100;
2949 if (imm
> -3 && imm
< 2)
2954 /* Analyze the function prologue from START_PC to LIMIT_PC. Return
2955 the address of the first instruction past the prologue. */
2958 micromips_scan_prologue (struct gdbarch
*gdbarch
,
2959 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
2960 struct frame_info
*this_frame
,
2961 struct mips_frame_cache
*this_cache
)
2963 CORE_ADDR end_prologue_addr
;
2964 int prev_non_prologue_insn
= 0;
2965 int frame_reg
= MIPS_SP_REGNUM
;
2966 int this_non_prologue_insn
;
2967 int non_prologue_insns
= 0;
2968 long frame_offset
= 0; /* Size of stack frame. */
2969 long frame_adjust
= 0; /* Offset of FP from SP. */
2970 int prev_delay_slot
= 0;
2974 ULONGEST insn
; /* current instruction */
2978 long v1_off
= 0; /* The assumption is LUI will replace it. */
2989 /* Can be called when there's no process, and hence when there's no
2991 if (this_frame
!= NULL
)
2992 sp
= get_frame_register_signed (this_frame
,
2993 gdbarch_num_regs (gdbarch
)
2998 if (limit_pc
> start_pc
+ 200)
2999 limit_pc
= start_pc
+ 200;
3002 /* Permit at most one non-prologue non-control-transfer instruction
3003 in the middle which may have been reordered by the compiler for
3005 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= loc
)
3007 this_non_prologue_insn
= 0;
3011 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, cur_pc
, NULL
);
3012 loc
+= MIPS_INSN16_SIZE
;
3013 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
3015 /* 32-bit instructions. */
3016 case 2 * MIPS_INSN16_SIZE
:
3018 insn
|= mips_fetch_instruction (gdbarch
,
3019 ISA_MICROMIPS
, cur_pc
+ loc
, NULL
);
3020 loc
+= MIPS_INSN16_SIZE
;
3021 switch (micromips_op (insn
>> 16))
3023 /* Record $sp/$fp adjustment. */
3024 /* Discard (D)ADDU $gp,$jp used for PIC code. */
3025 case 0x0: /* POOL32A: bits 000000 */
3026 case 0x16: /* POOL32S: bits 010110 */
3027 op
= b0s11_op (insn
);
3028 sreg
= b0s5_reg (insn
>> 16);
3029 treg
= b5s5_reg (insn
>> 16);
3030 dreg
= b11s5_reg (insn
);
3032 /* SUBU: bits 000000 00111010000 */
3033 /* DSUBU: bits 010110 00111010000 */
3034 && dreg
== MIPS_SP_REGNUM
&& sreg
== MIPS_SP_REGNUM
3036 /* (D)SUBU $sp, $v1 */
3038 else if (op
!= 0x150
3039 /* ADDU: bits 000000 00101010000 */
3040 /* DADDU: bits 010110 00101010000 */
3041 || dreg
!= 28 || sreg
!= 28 || treg
!= MIPS_T9_REGNUM
)
3042 this_non_prologue_insn
= 1;
3045 case 0x8: /* POOL32B: bits 001000 */
3046 op
= b12s4_op (insn
);
3047 breg
= b0s5_reg (insn
>> 16);
3048 reglist
= sreg
= b5s5_reg (insn
>> 16);
3049 offset
= (b0s12_imm (insn
) ^ 0x800) - 0x800;
3050 if ((op
== 0x9 || op
== 0xc)
3051 /* SWP: bits 001000 1001 */
3052 /* SDP: bits 001000 1100 */
3053 && breg
== MIPS_SP_REGNUM
&& sreg
< MIPS_RA_REGNUM
)
3054 /* S[DW]P reg,offset($sp) */
3056 s
= 4 << ((b12s4_op (insn
) & 0x4) == 0x4);
3057 set_reg_offset (gdbarch
, this_cache
,
3059 set_reg_offset (gdbarch
, this_cache
,
3060 sreg
+ 1, sp
+ offset
+ s
);
3062 else if ((op
== 0xd || op
== 0xf)
3063 /* SWM: bits 001000 1101 */
3064 /* SDM: bits 001000 1111 */
3065 && breg
== MIPS_SP_REGNUM
3066 /* SWM reglist,offset($sp) */
3067 && ((reglist
>= 1 && reglist
<= 9)
3068 || (reglist
>= 16 && reglist
<= 25)))
3070 int sreglist
= std::min(reglist
& 0xf, 8);
3072 s
= 4 << ((b12s4_op (insn
) & 0x2) == 0x2);
3073 for (i
= 0; i
< sreglist
; i
++)
3074 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ s
* i
);
3075 if ((reglist
& 0xf) > 8)
3076 set_reg_offset (gdbarch
, this_cache
, 30, sp
+ s
* i
++);
3077 if ((reglist
& 0x10) == 0x10)
3078 set_reg_offset (gdbarch
, this_cache
,
3079 MIPS_RA_REGNUM
, sp
+ s
* i
++);
3082 this_non_prologue_insn
= 1;
3085 /* Record $sp/$fp adjustment. */
3086 /* Discard (D)ADDIU $gp used for PIC code. */
3087 case 0xc: /* ADDIU: bits 001100 */
3088 case 0x17: /* DADDIU: bits 010111 */
3089 sreg
= b0s5_reg (insn
>> 16);
3090 dreg
= b5s5_reg (insn
>> 16);
3091 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3092 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
)
3093 /* (D)ADDIU $sp, imm */
3095 else if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3096 /* (D)ADDIU $fp, $sp, imm */
3098 frame_adjust
= offset
;
3101 else if (sreg
!= 28 || dreg
!= 28)
3102 /* (D)ADDIU $gp, imm */
3103 this_non_prologue_insn
= 1;
3106 /* LUI $v1 is used for larger $sp adjustments. */
3107 /* Discard LUI $gp used for PIC code. */
3108 case 0x10: /* POOL32I: bits 010000 */
3109 if (b5s5_op (insn
>> 16) == 0xd
3110 /* LUI: bits 010000 001101 */
3111 && b0s5_reg (insn
>> 16) == 3)
3113 v1_off
= ((b0s16_imm (insn
) << 16) ^ 0x80000000) - 0x80000000;
3114 else if (b5s5_op (insn
>> 16) != 0xd
3115 /* LUI: bits 010000 001101 */
3116 || b0s5_reg (insn
>> 16) != 28)
3118 this_non_prologue_insn
= 1;
3121 /* ORI $v1 is used for larger $sp adjustments. */
3122 case 0x14: /* ORI: bits 010100 */
3123 sreg
= b0s5_reg (insn
>> 16);
3124 dreg
= b5s5_reg (insn
>> 16);
3125 if (sreg
== 3 && dreg
== 3)
3127 v1_off
|= b0s16_imm (insn
);
3129 this_non_prologue_insn
= 1;
3132 case 0x26: /* SWC1: bits 100110 */
3133 case 0x2e: /* SDC1: bits 101110 */
3134 breg
= b0s5_reg (insn
>> 16);
3135 if (breg
!= MIPS_SP_REGNUM
)
3136 /* S[DW]C1 reg,offset($sp) */
3137 this_non_prologue_insn
= 1;
3140 case 0x36: /* SD: bits 110110 */
3141 case 0x3e: /* SW: bits 111110 */
3142 breg
= b0s5_reg (insn
>> 16);
3143 sreg
= b5s5_reg (insn
>> 16);
3144 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
3145 if (breg
== MIPS_SP_REGNUM
)
3146 /* S[DW] reg,offset($sp) */
3147 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3149 this_non_prologue_insn
= 1;
3153 /* The instruction in the delay slot can be a part
3154 of the prologue, so move forward once more. */
3155 if (micromips_instruction_has_delay_slot (insn
, 0))
3158 this_non_prologue_insn
= 1;
3164 /* 16-bit instructions. */
3165 case MIPS_INSN16_SIZE
:
3166 switch (micromips_op (insn
))
3168 case 0x3: /* MOVE: bits 000011 */
3169 sreg
= b0s5_reg (insn
);
3170 dreg
= b5s5_reg (insn
);
3171 if (sreg
== MIPS_SP_REGNUM
&& dreg
== 30)
3174 else if ((sreg
& 0x1c) != 0x4)
3175 /* MOVE reg, $a0-$a3 */
3176 this_non_prologue_insn
= 1;
3179 case 0x11: /* POOL16C: bits 010001 */
3180 if (b6s4_op (insn
) == 0x5)
3181 /* SWM: bits 010001 0101 */
3183 offset
= ((b0s4_imm (insn
) << 2) ^ 0x20) - 0x20;
3184 reglist
= b4s2_regl (insn
);
3185 for (i
= 0; i
<= reglist
; i
++)
3186 set_reg_offset (gdbarch
, this_cache
, 16 + i
, sp
+ 4 * i
);
3187 set_reg_offset (gdbarch
, this_cache
,
3188 MIPS_RA_REGNUM
, sp
+ 4 * i
++);
3191 this_non_prologue_insn
= 1;
3194 case 0x13: /* POOL16D: bits 010011 */
3195 if ((insn
& 0x1) == 0x1)
3196 /* ADDIUSP: bits 010011 1 */
3197 sp_adj
= micromips_decode_imm9 (b1s9_imm (insn
));
3198 else if (b5s5_reg (insn
) == MIPS_SP_REGNUM
)
3199 /* ADDIUS5: bits 010011 0 */
3200 /* ADDIUS5 $sp, imm */
3201 sp_adj
= (b1s4_imm (insn
) ^ 8) - 8;
3203 this_non_prologue_insn
= 1;
3206 case 0x32: /* SWSP: bits 110010 */
3207 offset
= b0s5_imm (insn
) << 2;
3208 sreg
= b5s5_reg (insn
);
3209 set_reg_offset (gdbarch
, this_cache
, sreg
, sp
+ offset
);
3213 /* The instruction in the delay slot can be a part
3214 of the prologue, so move forward once more. */
3215 if (micromips_instruction_has_delay_slot (insn
<< 16, 0))
3218 this_non_prologue_insn
= 1;
3224 frame_offset
-= sp_adj
;
3226 non_prologue_insns
+= this_non_prologue_insn
;
3228 /* A jump or branch, enough non-prologue insns seen or positive
3229 stack adjustment? If so, then we must have reached the end
3230 of the prologue by now. */
3231 if (prev_delay_slot
|| non_prologue_insns
> 1 || sp_adj
> 0
3232 || micromips_instruction_is_compact_branch (insn
))
3235 prev_non_prologue_insn
= this_non_prologue_insn
;
3236 prev_delay_slot
= in_delay_slot
;
3240 if (this_cache
!= NULL
)
3243 (get_frame_register_signed (this_frame
,
3244 gdbarch_num_regs (gdbarch
) + frame_reg
)
3245 + frame_offset
- frame_adjust
);
3246 /* FIXME: brobecker/2004-10-10: Just as in the mips32 case, we should
3247 be able to get rid of the assignment below, evetually. But it's
3248 still needed for now. */
3249 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3250 + mips_regnum (gdbarch
)->pc
]
3251 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
];
3254 /* Set end_prologue_addr to the address of the instruction immediately
3255 after the last one we scanned. Unless the last one looked like a
3256 non-prologue instruction (and we looked ahead), in which case use
3257 its address instead. */
3259 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3261 return end_prologue_addr
;
3264 /* Heuristic unwinder for procedures using microMIPS instructions.
3265 Procedures that use the 32-bit instruction set are handled by the
3266 mips_insn32 unwinder. Likewise MIPS16 and the mips_insn16 unwinder. */
3268 static struct mips_frame_cache
*
3269 mips_micro_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3271 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3272 struct mips_frame_cache
*cache
;
3274 if ((*this_cache
) != NULL
)
3275 return (struct mips_frame_cache
*) (*this_cache
);
3277 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3278 (*this_cache
) = cache
;
3279 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3281 /* Analyze the function prologue. */
3283 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3284 CORE_ADDR start_addr
;
3286 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3287 if (start_addr
== 0)
3288 start_addr
= heuristic_proc_start (get_frame_arch (this_frame
), pc
);
3289 /* We can't analyze the prologue if we couldn't find the begining
3291 if (start_addr
== 0)
3294 micromips_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3295 (struct mips_frame_cache
*) *this_cache
);
3298 /* gdbarch_sp_regnum contains the value and not the address. */
3299 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3300 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3302 return (struct mips_frame_cache
*) (*this_cache
);
3306 mips_micro_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3307 struct frame_id
*this_id
)
3309 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3311 /* This marks the outermost frame. */
3312 if (info
->base
== 0)
3314 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3317 static struct value
*
3318 mips_micro_frame_prev_register (struct frame_info
*this_frame
,
3319 void **this_cache
, int regnum
)
3321 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3323 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3327 mips_micro_frame_sniffer (const struct frame_unwind
*self
,
3328 struct frame_info
*this_frame
, void **this_cache
)
3330 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3331 CORE_ADDR pc
= get_frame_pc (this_frame
);
3333 if (mips_pc_is_micromips (gdbarch
, pc
))
3338 static const struct frame_unwind mips_micro_frame_unwind
=
3341 default_frame_unwind_stop_reason
,
3342 mips_micro_frame_this_id
,
3343 mips_micro_frame_prev_register
,
3345 mips_micro_frame_sniffer
3349 mips_micro_frame_base_address (struct frame_info
*this_frame
,
3352 struct mips_frame_cache
*info
= mips_micro_frame_cache (this_frame
,
3357 static const struct frame_base mips_micro_frame_base
=
3359 &mips_micro_frame_unwind
,
3360 mips_micro_frame_base_address
,
3361 mips_micro_frame_base_address
,
3362 mips_micro_frame_base_address
3365 static const struct frame_base
*
3366 mips_micro_frame_base_sniffer (struct frame_info
*this_frame
)
3368 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3369 CORE_ADDR pc
= get_frame_pc (this_frame
);
3371 if (mips_pc_is_micromips (gdbarch
, pc
))
3372 return &mips_micro_frame_base
;
3377 /* Mark all the registers as unset in the saved_regs array
3378 of THIS_CACHE. Do nothing if THIS_CACHE is null. */
3381 reset_saved_regs (struct gdbarch
*gdbarch
, struct mips_frame_cache
*this_cache
)
3383 if (this_cache
== NULL
|| this_cache
->saved_regs
== NULL
)
3387 const int num_regs
= gdbarch_num_regs (gdbarch
);
3390 /* Reset the register values to their default state. Register i's value
3391 is in register i. */
3392 for (i
= 0; i
< num_regs
; i
++)
3393 this_cache
->saved_regs
[i
].set_realreg (i
);
3397 /* Analyze the function prologue from START_PC to LIMIT_PC. Builds
3398 the associated FRAME_CACHE if not null.
3399 Return the address of the first instruction past the prologue. */
3402 mips32_scan_prologue (struct gdbarch
*gdbarch
,
3403 CORE_ADDR start_pc
, CORE_ADDR limit_pc
,
3404 struct frame_info
*this_frame
,
3405 struct mips_frame_cache
*this_cache
)
3407 int prev_non_prologue_insn
;
3408 int this_non_prologue_insn
;
3409 int non_prologue_insns
;
3410 CORE_ADDR frame_addr
= 0; /* Value of $r30. Used by gcc for
3412 int prev_delay_slot
;
3417 int frame_reg
= MIPS_SP_REGNUM
;
3419 CORE_ADDR end_prologue_addr
;
3420 int seen_sp_adjust
= 0;
3421 int load_immediate_bytes
= 0;
3423 int regsize_is_64_bits
= (mips_abi_regsize (gdbarch
) == 8);
3425 /* Can be called when there's no process, and hence when there's no
3427 if (this_frame
!= NULL
)
3428 sp
= get_frame_register_signed (this_frame
,
3429 gdbarch_num_regs (gdbarch
)
3434 if (limit_pc
> start_pc
+ 200)
3435 limit_pc
= start_pc
+ 200;
3438 prev_non_prologue_insn
= 0;
3439 non_prologue_insns
= 0;
3440 prev_delay_slot
= 0;
3443 /* Permit at most one non-prologue non-control-transfer instruction
3444 in the middle which may have been reordered by the compiler for
3447 for (cur_pc
= start_pc
; cur_pc
< limit_pc
; cur_pc
+= MIPS_INSN32_SIZE
)
3449 unsigned long inst
, high_word
;
3453 this_non_prologue_insn
= 0;
3456 /* Fetch the instruction. */
3457 inst
= (unsigned long) mips_fetch_instruction (gdbarch
, ISA_MIPS
,
3460 /* Save some code by pre-extracting some useful fields. */
3461 high_word
= (inst
>> 16) & 0xffff;
3462 offset
= ((inst
& 0xffff) ^ 0x8000) - 0x8000;
3463 reg
= high_word
& 0x1f;
3465 if (high_word
== 0x27bd /* addiu $sp,$sp,-i */
3466 || high_word
== 0x23bd /* addi $sp,$sp,-i */
3467 || high_word
== 0x67bd) /* daddiu $sp,$sp,-i */
3469 if (offset
< 0) /* Negative stack adjustment? */
3470 frame_offset
-= offset
;
3472 /* Exit loop if a positive stack adjustment is found, which
3473 usually means that the stack cleanup code in the function
3474 epilogue is reached. */
3478 else if (((high_word
& 0xFFE0) == 0xafa0) /* sw reg,offset($sp) */
3479 && !regsize_is_64_bits
)
3481 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3483 else if (((high_word
& 0xFFE0) == 0xffa0) /* sd reg,offset($sp) */
3484 && regsize_is_64_bits
)
3486 /* Irix 6.2 N32 ABI uses sd instructions for saving $gp and $ra. */
3487 set_reg_offset (gdbarch
, this_cache
, reg
, sp
+ offset
);
3489 else if (high_word
== 0x27be) /* addiu $30,$sp,size */
3491 /* Old gcc frame, r30 is virtual frame pointer. */
3492 if (offset
!= frame_offset
)
3493 frame_addr
= sp
+ offset
;
3494 else if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3496 unsigned alloca_adjust
;
3499 frame_addr
= get_frame_register_signed
3500 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3503 alloca_adjust
= (unsigned) (frame_addr
- (sp
+ offset
));
3504 if (alloca_adjust
> 0)
3506 /* FP > SP + frame_size. This may be because of
3507 an alloca or somethings similar. Fix sp to
3508 "pre-alloca" value, and try again. */
3509 sp
+= alloca_adjust
;
3510 /* Need to reset the status of all registers. Otherwise,
3511 we will hit a guard that prevents the new address
3512 for each register to be recomputed during the second
3514 reset_saved_regs (gdbarch
, this_cache
);
3519 /* move $30,$sp. With different versions of gas this will be either
3520 `addu $30,$sp,$zero' or `or $30,$sp,$zero' or `daddu 30,sp,$0'.
3521 Accept any one of these. */
3522 else if (inst
== 0x03A0F021 || inst
== 0x03a0f025 || inst
== 0x03a0f02d)
3524 /* New gcc frame, virtual frame pointer is at r30 + frame_size. */
3525 if (this_frame
&& frame_reg
== MIPS_SP_REGNUM
)
3527 unsigned alloca_adjust
;
3530 frame_addr
= get_frame_register_signed
3531 (this_frame
, gdbarch_num_regs (gdbarch
) + 30);
3533 alloca_adjust
= (unsigned) (frame_addr
- sp
);
3534 if (alloca_adjust
> 0)
3536 /* FP > SP + frame_size. This may be because of
3537 an alloca or somethings similar. Fix sp to
3538 "pre-alloca" value, and try again. */
3540 /* Need to reset the status of all registers. Otherwise,
3541 we will hit a guard that prevents the new address
3542 for each register to be recomputed during the second
3544 reset_saved_regs (gdbarch
, this_cache
);
3549 else if ((high_word
& 0xFFE0) == 0xafc0 /* sw reg,offset($30) */
3550 && !regsize_is_64_bits
)
3552 set_reg_offset (gdbarch
, this_cache
, reg
, frame_addr
+ offset
);
3554 else if ((high_word
& 0xFFE0) == 0xE7A0 /* swc1 freg,n($sp) */
3555 || (high_word
& 0xF3E0) == 0xA3C0 /* sx reg,n($s8) */
3556 || (inst
& 0xFF9F07FF) == 0x00800021 /* move reg,$a0-$a3 */
3557 || high_word
== 0x3c1c /* lui $gp,n */
3558 || high_word
== 0x279c /* addiu $gp,$gp,n */
3559 || inst
== 0x0399e021 /* addu $gp,$gp,$t9 */
3560 || inst
== 0x033ce021 /* addu $gp,$t9,$gp */
3563 /* These instructions are part of the prologue, but we don't
3564 need to do anything special to handle them. */
3566 /* The instructions below load $at or $t0 with an immediate
3567 value in preparation for a stack adjustment via
3568 subu $sp,$sp,[$at,$t0]. These instructions could also
3569 initialize a local variable, so we accept them only before
3570 a stack adjustment instruction was seen. */
3571 else if (!seen_sp_adjust
3573 && (high_word
== 0x3c01 /* lui $at,n */
3574 || high_word
== 0x3c08 /* lui $t0,n */
3575 || high_word
== 0x3421 /* ori $at,$at,n */
3576 || high_word
== 0x3508 /* ori $t0,$t0,n */
3577 || high_word
== 0x3401 /* ori $at,$zero,n */
3578 || high_word
== 0x3408 /* ori $t0,$zero,n */
3581 load_immediate_bytes
+= MIPS_INSN32_SIZE
; /* FIXME! */
3583 /* Check for branches and jumps. The instruction in the delay
3584 slot can be a part of the prologue, so move forward once more. */
3585 else if (mips32_instruction_has_delay_slot (gdbarch
, inst
))
3589 /* This instruction is not an instruction typically found
3590 in a prologue, so we must have reached the end of the
3594 this_non_prologue_insn
= 1;
3597 non_prologue_insns
+= this_non_prologue_insn
;
3599 /* A jump or branch, or enough non-prologue insns seen? If so,
3600 then we must have reached the end of the prologue by now. */
3601 if (prev_delay_slot
|| non_prologue_insns
> 1)
3604 prev_non_prologue_insn
= this_non_prologue_insn
;
3605 prev_delay_slot
= in_delay_slot
;
3609 if (this_cache
!= NULL
)
3612 (get_frame_register_signed (this_frame
,
3613 gdbarch_num_regs (gdbarch
) + frame_reg
)
3615 /* FIXME: brobecker/2004-09-15: We should be able to get rid of
3616 this assignment below, eventually. But it's still needed
3618 this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3619 + mips_regnum (gdbarch
)->pc
]
3620 = this_cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3624 /* Set end_prologue_addr to the address of the instruction immediately
3625 after the last one we scanned. Unless the last one looked like a
3626 non-prologue instruction (and we looked ahead), in which case use
3627 its address instead. */
3629 = prev_non_prologue_insn
|| prev_delay_slot
? prev_pc
: cur_pc
;
3631 /* In a frameless function, we might have incorrectly
3632 skipped some load immediate instructions. Undo the skipping
3633 if the load immediate was not followed by a stack adjustment. */
3634 if (load_immediate_bytes
&& !seen_sp_adjust
)
3635 end_prologue_addr
-= load_immediate_bytes
;
3637 return end_prologue_addr
;
3640 /* Heuristic unwinder for procedures using 32-bit instructions (covers
3641 both 32-bit and 64-bit MIPS ISAs). Procedures using 16-bit
3642 instructions (a.k.a. MIPS16) are handled by the mips_insn16
3643 unwinder. Likewise microMIPS and the mips_micro unwinder. */
3645 static struct mips_frame_cache
*
3646 mips_insn32_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3648 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3649 struct mips_frame_cache
*cache
;
3651 if ((*this_cache
) != NULL
)
3652 return (struct mips_frame_cache
*) (*this_cache
);
3654 cache
= FRAME_OBSTACK_ZALLOC (struct mips_frame_cache
);
3655 (*this_cache
) = cache
;
3656 cache
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
3658 /* Analyze the function prologue. */
3660 const CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3661 CORE_ADDR start_addr
;
3663 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3664 if (start_addr
== 0)
3665 start_addr
= heuristic_proc_start (gdbarch
, pc
);
3666 /* We can't analyze the prologue if we couldn't find the begining
3668 if (start_addr
== 0)
3671 mips32_scan_prologue (gdbarch
, start_addr
, pc
, this_frame
,
3672 (struct mips_frame_cache
*) *this_cache
);
3675 /* gdbarch_sp_regnum contains the value and not the address. */
3676 cache
->saved_regs
[gdbarch_num_regs (gdbarch
)
3677 + MIPS_SP_REGNUM
].set_value (cache
->base
);
3679 return (struct mips_frame_cache
*) (*this_cache
);
3683 mips_insn32_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3684 struct frame_id
*this_id
)
3686 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3688 /* This marks the outermost frame. */
3689 if (info
->base
== 0)
3691 (*this_id
) = frame_id_build (info
->base
, get_frame_func (this_frame
));
3694 static struct value
*
3695 mips_insn32_frame_prev_register (struct frame_info
*this_frame
,
3696 void **this_cache
, int regnum
)
3698 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3700 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
3704 mips_insn32_frame_sniffer (const struct frame_unwind
*self
,
3705 struct frame_info
*this_frame
, void **this_cache
)
3707 CORE_ADDR pc
= get_frame_pc (this_frame
);
3708 if (mips_pc_is_mips (pc
))
3713 static const struct frame_unwind mips_insn32_frame_unwind
=
3716 default_frame_unwind_stop_reason
,
3717 mips_insn32_frame_this_id
,
3718 mips_insn32_frame_prev_register
,
3720 mips_insn32_frame_sniffer
3724 mips_insn32_frame_base_address (struct frame_info
*this_frame
,
3727 struct mips_frame_cache
*info
= mips_insn32_frame_cache (this_frame
,
3732 static const struct frame_base mips_insn32_frame_base
=
3734 &mips_insn32_frame_unwind
,
3735 mips_insn32_frame_base_address
,
3736 mips_insn32_frame_base_address
,
3737 mips_insn32_frame_base_address
3740 static const struct frame_base
*
3741 mips_insn32_frame_base_sniffer (struct frame_info
*this_frame
)
3743 CORE_ADDR pc
= get_frame_pc (this_frame
);
3744 if (mips_pc_is_mips (pc
))
3745 return &mips_insn32_frame_base
;
3750 static struct trad_frame_cache
*
3751 mips_stub_frame_cache (struct frame_info
*this_frame
, void **this_cache
)
3754 CORE_ADDR start_addr
;
3755 CORE_ADDR stack_addr
;
3756 struct trad_frame_cache
*this_trad_cache
;
3757 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
3758 int num_regs
= gdbarch_num_regs (gdbarch
);
3760 if ((*this_cache
) != NULL
)
3761 return (struct trad_frame_cache
*) (*this_cache
);
3762 this_trad_cache
= trad_frame_cache_zalloc (this_frame
);
3763 (*this_cache
) = this_trad_cache
;
3765 /* The return address is in the link register. */
3766 trad_frame_set_reg_realreg (this_trad_cache
,
3767 gdbarch_pc_regnum (gdbarch
),
3768 num_regs
+ MIPS_RA_REGNUM
);
3770 /* Frame ID, since it's a frameless / stackless function, no stack
3771 space is allocated and SP on entry is the current SP. */
3772 pc
= get_frame_pc (this_frame
);
3773 find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
);
3774 stack_addr
= get_frame_register_signed (this_frame
,
3775 num_regs
+ MIPS_SP_REGNUM
);
3776 trad_frame_set_id (this_trad_cache
, frame_id_build (stack_addr
, start_addr
));
3778 /* Assume that the frame's base is the same as the
3780 trad_frame_set_this_base (this_trad_cache
, stack_addr
);
3782 return this_trad_cache
;
3786 mips_stub_frame_this_id (struct frame_info
*this_frame
, void **this_cache
,
3787 struct frame_id
*this_id
)
3789 struct trad_frame_cache
*this_trad_cache
3790 = mips_stub_frame_cache (this_frame
, this_cache
);
3791 trad_frame_get_id (this_trad_cache
, this_id
);
3794 static struct value
*
3795 mips_stub_frame_prev_register (struct frame_info
*this_frame
,
3796 void **this_cache
, int regnum
)
3798 struct trad_frame_cache
*this_trad_cache
3799 = mips_stub_frame_cache (this_frame
, this_cache
);
3800 return trad_frame_get_register (this_trad_cache
, this_frame
, regnum
);
3804 mips_stub_frame_sniffer (const struct frame_unwind
*self
,
3805 struct frame_info
*this_frame
, void **this_cache
)
3808 CORE_ADDR pc
= get_frame_address_in_block (this_frame
);
3809 struct bound_minimal_symbol msym
;
3811 /* Use the stub unwinder for unreadable code. */
3812 if (target_read_memory (get_frame_pc (this_frame
), dummy
, 4) != 0)
3815 if (in_plt_section (pc
) || in_mips_stubs_section (pc
))
3818 /* Calling a PIC function from a non-PIC function passes through a
3819 stub. The stub for foo is named ".pic.foo". */
3820 msym
= lookup_minimal_symbol_by_pc (pc
);
3821 if (msym
.minsym
!= NULL
3822 && msym
.minsym
->linkage_name () != NULL
3823 && startswith (msym
.minsym
->linkage_name (), ".pic."))
3829 static const struct frame_unwind mips_stub_frame_unwind
=
3832 default_frame_unwind_stop_reason
,
3833 mips_stub_frame_this_id
,
3834 mips_stub_frame_prev_register
,
3836 mips_stub_frame_sniffer
3840 mips_stub_frame_base_address (struct frame_info
*this_frame
,
3843 struct trad_frame_cache
*this_trad_cache
3844 = mips_stub_frame_cache (this_frame
, this_cache
);
3845 return trad_frame_get_this_base (this_trad_cache
);
3848 static const struct frame_base mips_stub_frame_base
=
3850 &mips_stub_frame_unwind
,
3851 mips_stub_frame_base_address
,
3852 mips_stub_frame_base_address
,
3853 mips_stub_frame_base_address
3856 static const struct frame_base
*
3857 mips_stub_frame_base_sniffer (struct frame_info
*this_frame
)
3859 if (mips_stub_frame_sniffer (&mips_stub_frame_unwind
, this_frame
, NULL
))
3860 return &mips_stub_frame_base
;
3865 /* mips_addr_bits_remove - remove useless address bits */
3868 mips_addr_bits_remove (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
3870 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
3872 if (mips_mask_address_p (tdep
) && (((ULONGEST
) addr
) >> 32 == 0xffffffffUL
))
3873 /* This hack is a work-around for existing boards using PMON, the
3874 simulator, and any other 64-bit targets that doesn't have true
3875 64-bit addressing. On these targets, the upper 32 bits of
3876 addresses are ignored by the hardware. Thus, the PC or SP are
3877 likely to have been sign extended to all 1s by instruction
3878 sequences that load 32-bit addresses. For example, a typical
3879 piece of code that loads an address is this:
3881 lui $r2, <upper 16 bits>
3882 ori $r2, <lower 16 bits>
3884 But the lui sign-extends the value such that the upper 32 bits
3885 may be all 1s. The workaround is simply to mask off these
3886 bits. In the future, gcc may be changed to support true 64-bit
3887 addressing, and this masking will have to be disabled. */
3888 return addr
&= 0xffffffffUL
;
3894 /* Checks for an atomic sequence of instructions beginning with a LL/LLD
3895 instruction and ending with a SC/SCD instruction. If such a sequence
3896 is found, attempt to step through it. A breakpoint is placed at the end of
3899 /* Instructions used during single-stepping of atomic sequences, standard
3901 #define LL_OPCODE 0x30
3902 #define LLD_OPCODE 0x34
3903 #define SC_OPCODE 0x38
3904 #define SCD_OPCODE 0x3c
3906 static std::vector
<CORE_ADDR
>
3907 mips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
3909 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
3911 CORE_ADDR branch_bp
; /* Breakpoint at branch instruction's destination. */
3915 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
3916 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
3918 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3919 /* Assume all atomic sequences start with a ll/lld instruction. */
3920 if (itype_op (insn
) != LL_OPCODE
&& itype_op (insn
) != LLD_OPCODE
)
3923 /* Assume that no atomic sequence is longer than "atomic_sequence_length"
3925 for (insn_count
= 0; insn_count
< atomic_sequence_length
; ++insn_count
)
3928 loc
+= MIPS_INSN32_SIZE
;
3929 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, loc
, NULL
);
3931 /* Assume that there is at most one branch in the atomic
3932 sequence. If a branch is found, put a breakpoint in its
3933 destination address. */
3934 switch (itype_op (insn
))
3936 case 0: /* SPECIAL */
3937 if (rtype_funct (insn
) >> 1 == 4) /* JR, JALR */
3938 return {}; /* fallback to the standard single-step code. */
3940 case 1: /* REGIMM */
3941 is_branch
= ((itype_rt (insn
) & 0xc) == 0 /* B{LT,GE}Z* */
3942 || ((itype_rt (insn
) & 0x1e) == 0
3943 && itype_rs (insn
) == 0)); /* BPOSGE* */
3947 return {}; /* fallback to the standard single-step code. */
3954 case 22: /* BLEZL */
3955 case 23: /* BGTTL */
3959 is_branch
= ((itype_rs (insn
) == 9 || itype_rs (insn
) == 10)
3960 && (itype_rt (insn
) & 0x2) == 0);
3961 if (is_branch
) /* BC1ANY2F, BC1ANY2T, BC1ANY4F, BC1ANY4T */
3966 is_branch
= (itype_rs (insn
) == 8); /* BCzF, BCzFL, BCzT, BCzTL */
3971 branch_bp
= loc
+ mips32_relative_offset (insn
) + 4;
3972 if (last_breakpoint
>= 1)
3973 return {}; /* More than one branch found, fallback to the
3974 standard single-step code. */
3975 breaks
[1] = branch_bp
;
3979 if (itype_op (insn
) == SC_OPCODE
|| itype_op (insn
) == SCD_OPCODE
)
3983 /* Assume that the atomic sequence ends with a sc/scd instruction. */
3984 if (itype_op (insn
) != SC_OPCODE
&& itype_op (insn
) != SCD_OPCODE
)
3987 loc
+= MIPS_INSN32_SIZE
;
3989 /* Insert a breakpoint right after the end of the atomic sequence. */
3992 /* Check for duplicated breakpoints. Check also for a breakpoint
3993 placed (branch instruction's destination) in the atomic sequence. */
3994 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
3995 last_breakpoint
= 0;
3997 std::vector
<CORE_ADDR
> next_pcs
;
3999 /* Effectively inserts the breakpoints. */
4000 for (index
= 0; index
<= last_breakpoint
; index
++)
4001 next_pcs
.push_back (breaks
[index
]);
4006 static std::vector
<CORE_ADDR
>
4007 micromips_deal_with_atomic_sequence (struct gdbarch
*gdbarch
,
4010 const int atomic_sequence_length
= 16; /* Instruction sequence length. */
4011 int last_breakpoint
= 0; /* Defaults to 0 (no breakpoints placed). */
4012 CORE_ADDR breaks
[2] = {CORE_ADDR_MAX
, CORE_ADDR_MAX
};
4013 CORE_ADDR branch_bp
= 0; /* Breakpoint at branch instruction's
4021 /* Assume all atomic sequences start with a ll/lld instruction. */
4022 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4023 if (micromips_op (insn
) != 0x18) /* POOL32C: bits 011000 */
4025 loc
+= MIPS_INSN16_SIZE
;
4027 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4028 if ((b12s4_op (insn
) & 0xb) != 0x3) /* LL, LLD: bits 011000 0x11 */
4030 loc
+= MIPS_INSN16_SIZE
;
4032 /* Assume all atomic sequences end with an sc/scd instruction. Assume
4033 that no atomic sequence is longer than "atomic_sequence_length"
4035 for (insn_count
= 0;
4036 !sc_found
&& insn_count
< atomic_sequence_length
;
4041 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, loc
, NULL
);
4042 loc
+= MIPS_INSN16_SIZE
;
4044 /* Assume that there is at most one conditional branch in the
4045 atomic sequence. If a branch is found, put a breakpoint in
4046 its destination address. */
4047 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
4049 /* 32-bit instructions. */
4050 case 2 * MIPS_INSN16_SIZE
:
4051 switch (micromips_op (insn
))
4053 case 0x10: /* POOL32I: bits 010000 */
4054 if ((b5s5_op (insn
) & 0x18) != 0x0
4055 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
4056 /* BLEZ, BNEZC, BGTZ, BEQZC: 010000 001xx */
4057 && (b5s5_op (insn
) & 0x1d) != 0x11
4058 /* BLTZALS, BGEZALS: bits 010000 100x1 */
4059 && ((b5s5_op (insn
) & 0x1e) != 0x14
4060 || (insn
& 0x3) != 0x0)
4061 /* BC2F, BC2T: bits 010000 1010x xxx00 */
4062 && (b5s5_op (insn
) & 0x1e) != 0x1a
4063 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
4064 && ((b5s5_op (insn
) & 0x1e) != 0x1c
4065 || (insn
& 0x3) != 0x0)
4066 /* BC1F, BC1T: bits 010000 1110x xxx00 */
4067 && ((b5s5_op (insn
) & 0x1c) != 0x1c
4068 || (insn
& 0x3) != 0x1))
4069 /* BC1ANY*: bits 010000 111xx xxx01 */
4073 case 0x25: /* BEQ: bits 100101 */
4074 case 0x2d: /* BNE: bits 101101 */
4076 insn
|= mips_fetch_instruction (gdbarch
,
4077 ISA_MICROMIPS
, loc
, NULL
);
4078 branch_bp
= (loc
+ MIPS_INSN16_SIZE
4079 + micromips_relative_offset16 (insn
));
4083 case 0x00: /* POOL32A: bits 000000 */
4085 insn
|= mips_fetch_instruction (gdbarch
,
4086 ISA_MICROMIPS
, loc
, NULL
);
4087 if (b0s6_op (insn
) != 0x3c
4088 /* POOL32Axf: bits 000000 ... 111100 */
4089 || (b6s10_ext (insn
) & 0x2bf) != 0x3c)
4090 /* JALR, JALR.HB: 000000 000x111100 111100 */
4091 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
4095 case 0x1d: /* JALS: bits 011101 */
4096 case 0x35: /* J: bits 110101 */
4097 case 0x3d: /* JAL: bits 111101 */
4098 case 0x3c: /* JALX: bits 111100 */
4099 return {}; /* Fall back to the standard single-step code. */
4101 case 0x18: /* POOL32C: bits 011000 */
4102 if ((b12s4_op (insn
) & 0xb) == 0xb)
4103 /* SC, SCD: bits 011000 1x11 */
4107 loc
+= MIPS_INSN16_SIZE
;
4110 /* 16-bit instructions. */
4111 case MIPS_INSN16_SIZE
:
4112 switch (micromips_op (insn
))
4114 case 0x23: /* BEQZ16: bits 100011 */
4115 case 0x2b: /* BNEZ16: bits 101011 */
4116 branch_bp
= loc
+ micromips_relative_offset7 (insn
);
4120 case 0x11: /* POOL16C: bits 010001 */
4121 if ((b5s5_op (insn
) & 0x1c) != 0xc
4122 /* JR16, JRC, JALR16, JALRS16: 010001 011xx */
4123 && b5s5_op (insn
) != 0x18)
4124 /* JRADDIUSP: bits 010001 11000 */
4126 return {}; /* Fall back to the standard single-step code. */
4128 case 0x33: /* B16: bits 110011 */
4129 return {}; /* Fall back to the standard single-step code. */
4135 if (last_breakpoint
>= 1)
4136 return {}; /* More than one branch found, fallback to the
4137 standard single-step code. */
4138 breaks
[1] = branch_bp
;
4145 /* Insert a breakpoint right after the end of the atomic sequence. */
4148 /* Check for duplicated breakpoints. Check also for a breakpoint
4149 placed (branch instruction's destination) in the atomic sequence */
4150 if (last_breakpoint
&& pc
<= breaks
[1] && breaks
[1] <= breaks
[0])
4151 last_breakpoint
= 0;
4153 std::vector
<CORE_ADDR
> next_pcs
;
4155 /* Effectively inserts the breakpoints. */
4156 for (index
= 0; index
<= last_breakpoint
; index
++)
4157 next_pcs
.push_back (breaks
[index
]);
4162 static std::vector
<CORE_ADDR
>
4163 deal_with_atomic_sequence (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4165 if (mips_pc_is_mips (pc
))
4166 return mips_deal_with_atomic_sequence (gdbarch
, pc
);
4167 else if (mips_pc_is_micromips (gdbarch
, pc
))
4168 return micromips_deal_with_atomic_sequence (gdbarch
, pc
);
4173 /* mips_software_single_step() is called just before we want to resume
4174 the inferior, if we want to single-step it but there is no hardware
4175 or kernel single-step support (MIPS on GNU/Linux for example). We find
4176 the target of the coming instruction and breakpoint it. */
4178 std::vector
<CORE_ADDR
>
4179 mips_software_single_step (struct regcache
*regcache
)
4181 struct gdbarch
*gdbarch
= regcache
->arch ();
4182 CORE_ADDR pc
, next_pc
;
4184 pc
= regcache_read_pc (regcache
);
4185 std::vector
<CORE_ADDR
> next_pcs
= deal_with_atomic_sequence (gdbarch
, pc
);
4187 if (!next_pcs
.empty ())
4190 next_pc
= mips_next_pc (regcache
, pc
);
4195 /* Test whether the PC points to the return instruction at the
4196 end of a function. */
4199 mips_about_to_return (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4204 /* This used to check for MIPS16, but this piece of code is never
4205 called for MIPS16 functions. And likewise microMIPS ones. */
4206 gdb_assert (mips_pc_is_mips (pc
));
4208 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
4210 return (insn
& ~hint
) == 0x3e00008; /* jr(.hb) $ra */
4214 /* This fencepost looks highly suspicious to me. Removing it also
4215 seems suspicious as it could affect remote debugging across serial
4219 heuristic_proc_start (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4225 struct inferior
*inf
;
4227 pc
= gdbarch_addr_bits_remove (gdbarch
, pc
);
4229 fence
= start_pc
- heuristic_fence_post
;
4233 if (heuristic_fence_post
== -1 || fence
< VM_MIN_ADDRESS
)
4234 fence
= VM_MIN_ADDRESS
;
4236 instlen
= mips_pc_is_mips (pc
) ? MIPS_INSN32_SIZE
: MIPS_INSN16_SIZE
;
4238 inf
= current_inferior ();
4240 /* Search back for previous return. */
4241 for (start_pc
-= instlen
;; start_pc
-= instlen
)
4242 if (start_pc
< fence
)
4244 /* It's not clear to me why we reach this point when
4245 stop_soon, but with this test, at least we
4246 don't print out warnings for every child forked (eg, on
4247 decstation). 22apr93 rich@cygnus.com. */
4248 if (inf
->control
.stop_soon
== NO_STOP_QUIETLY
)
4250 static int blurb_printed
= 0;
4252 warning (_("GDB can't find the start of the function at %s."),
4253 paddress (gdbarch
, pc
));
4257 /* This actually happens frequently in embedded
4258 development, when you first connect to a board
4259 and your stack pointer and pc are nowhere in
4260 particular. This message needs to give people
4261 in that situation enough information to
4262 determine that it's no big deal. */
4263 printf_filtered ("\n\
4264 GDB is unable to find the start of the function at %s\n\
4265 and thus can't determine the size of that function's stack frame.\n\
4266 This means that GDB may be unable to access that stack frame, or\n\
4267 the frames below it.\n\
4268 This problem is most likely caused by an invalid program counter or\n\
4270 However, if you think GDB should simply search farther back\n\
4271 from %s for code which looks like the beginning of a\n\
4272 function, you can increase the range of the search using the `set\n\
4273 heuristic-fence-post' command.\n",
4274 paddress (gdbarch
, pc
), paddress (gdbarch
, pc
));
4281 else if (mips_pc_is_mips16 (gdbarch
, start_pc
))
4283 unsigned short inst
;
4285 /* On MIPS16, any one of the following is likely to be the
4286 start of a function:
4292 extend -n followed by 'addiu sp,+n' or 'daddiu sp,+n'. */
4293 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, start_pc
, NULL
);
4294 if ((inst
& 0xff80) == 0x6480) /* save */
4296 if (start_pc
- instlen
>= fence
)
4298 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
,
4299 start_pc
- instlen
, NULL
);
4300 if ((inst
& 0xf800) == 0xf000) /* extend */
4301 start_pc
-= instlen
;
4305 else if (((inst
& 0xf81f) == 0xe809
4306 && (inst
& 0x700) != 0x700) /* entry */
4307 || (inst
& 0xff80) == 0x6380 /* addiu sp,-n */
4308 || (inst
& 0xff80) == 0xfb80 /* daddiu sp,-n */
4309 || ((inst
& 0xf810) == 0xf010 && seen_adjsp
)) /* extend -n */
4311 else if ((inst
& 0xff00) == 0x6300 /* addiu sp */
4312 || (inst
& 0xff00) == 0xfb00) /* daddiu sp */
4317 else if (mips_pc_is_micromips (gdbarch
, start_pc
))
4325 /* On microMIPS, any one of the following is likely to be the
4326 start of a function:
4330 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
4331 switch (micromips_op (insn
))
4333 case 0xc: /* ADDIU: bits 001100 */
4334 case 0x17: /* DADDIU: bits 010111 */
4335 sreg
= b0s5_reg (insn
);
4336 dreg
= b5s5_reg (insn
);
4338 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
,
4339 pc
+ MIPS_INSN16_SIZE
, NULL
);
4340 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
4341 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
4342 /* (D)ADDIU $sp, imm */
4347 case 0x10: /* POOL32I: bits 010000 */
4348 if (b5s5_op (insn
) == 0xd
4349 /* LUI: bits 010000 001101 */
4350 && b0s5_reg (insn
>> 16) == 28)
4355 case 0x13: /* POOL16D: bits 010011 */
4356 if ((insn
& 0x1) == 0x1)
4357 /* ADDIUSP: bits 010011 1 */
4359 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
4365 /* ADDIUS5: bits 010011 0 */
4367 dreg
= b5s5_reg (insn
);
4368 offset
= (b1s4_imm (insn
) ^ 8) - 8;
4369 if (dreg
== MIPS_SP_REGNUM
&& offset
< 0)
4370 /* ADDIUS5 $sp, -imm */
4378 else if (mips_about_to_return (gdbarch
, start_pc
))
4380 /* Skip return and its delay slot. */
4381 start_pc
+= 2 * MIPS_INSN32_SIZE
;
4388 struct mips_objfile_private
4394 /* According to the current ABI, should the type be passed in a
4395 floating-point register (assuming that there is space)? When there
4396 is no FPU, FP are not even considered as possible candidates for
4397 FP registers and, consequently this returns false - forces FP
4398 arguments into integer registers. */
4401 fp_register_arg_p (struct gdbarch
*gdbarch
, enum type_code typecode
,
4402 struct type
*arg_type
)
4404 return ((typecode
== TYPE_CODE_FLT
4405 || (MIPS_EABI (gdbarch
)
4406 && (typecode
== TYPE_CODE_STRUCT
4407 || typecode
== TYPE_CODE_UNION
)
4408 && arg_type
->num_fields () == 1
4409 && check_typedef (arg_type
->field (0).type ())->code ()
4411 && MIPS_FPU_TYPE(gdbarch
) != MIPS_FPU_NONE
);
4414 /* On o32, argument passing in GPRs depends on the alignment of the type being
4415 passed. Return 1 if this type must be aligned to a doubleword boundary. */
4418 mips_type_needs_double_align (struct type
*type
)
4420 enum type_code typecode
= type
->code ();
4422 if (typecode
== TYPE_CODE_FLT
&& TYPE_LENGTH (type
) == 8)
4424 else if (typecode
== TYPE_CODE_STRUCT
)
4426 if (type
->num_fields () < 1)
4428 return mips_type_needs_double_align (type
->field (0).type ());
4430 else if (typecode
== TYPE_CODE_UNION
)
4434 n
= type
->num_fields ();
4435 for (i
= 0; i
< n
; i
++)
4436 if (mips_type_needs_double_align (type
->field (i
).type ()))
4443 /* Adjust the address downward (direction of stack growth) so that it
4444 is correctly aligned for a new stack frame. */
4446 mips_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
4448 return align_down (addr
, 16);
4451 /* Implement the "push_dummy_code" gdbarch method. */
4454 mips_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
,
4455 CORE_ADDR funaddr
, struct value
**args
,
4456 int nargs
, struct type
*value_type
,
4457 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
4458 struct regcache
*regcache
)
4460 static gdb_byte nop_insn
[] = { 0, 0, 0, 0 };
4464 /* Reserve enough room on the stack for our breakpoint instruction. */
4465 bp_slot
= sp
- sizeof (nop_insn
);
4467 /* Return to microMIPS mode if calling microMIPS code to avoid
4468 triggering an address error exception on processors that only
4469 support microMIPS execution. */
4470 *bp_addr
= (mips_pc_is_micromips (gdbarch
, funaddr
)
4471 ? make_compact_addr (bp_slot
) : bp_slot
);
4473 /* The breakpoint layer automatically adjusts the address of
4474 breakpoints inserted in a branch delay slot. With enough
4475 bad luck, the 4 bytes located just before our breakpoint
4476 instruction could look like a branch instruction, and thus
4477 trigger the adjustement, and break the function call entirely.
4478 So, we reserve those 4 bytes and write a nop instruction
4479 to prevent that from happening. */
4480 nop_addr
= bp_slot
- sizeof (nop_insn
);
4481 write_memory (nop_addr
, nop_insn
, sizeof (nop_insn
));
4482 sp
= mips_frame_align (gdbarch
, nop_addr
);
4484 /* Inferior resumes at the function entry point. */
4491 mips_eabi_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4492 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4493 int nargs
, struct value
**args
, CORE_ADDR sp
,
4494 function_call_return_method return_method
,
4495 CORE_ADDR struct_addr
)
4501 int stack_offset
= 0;
4502 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4503 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4504 int abi_regsize
= mips_abi_regsize (gdbarch
);
4506 /* For shared libraries, "t9" needs to point at the function
4508 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4510 /* Set the return address register to point to the entry point of
4511 the program, where a breakpoint lies in wait. */
4512 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4514 /* First ensure that the stack and structure return address (if any)
4515 are properly aligned. The stack has to be at least 64-bit
4516 aligned even on 32-bit machines, because doubles must be 64-bit
4517 aligned. For n32 and n64, stack frames need to be 128-bit
4518 aligned, so we round to this widest known alignment. */
4520 sp
= align_down (sp
, 16);
4521 struct_addr
= align_down (struct_addr
, 16);
4523 /* Now make space on the stack for the args. We allocate more
4524 than necessary for EABI, because the first few arguments are
4525 passed in registers, but that's OK. */
4526 for (argnum
= 0; argnum
< nargs
; argnum
++)
4527 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), abi_regsize
);
4528 sp
-= align_up (arg_space
, 16);
4531 fprintf_unfiltered (gdb_stdlog
,
4532 "mips_eabi_push_dummy_call: sp=%s allocated %ld\n",
4533 paddress (gdbarch
, sp
),
4534 (long) align_up (arg_space
, 16));
4536 /* Initialize the integer and float register pointers. */
4537 argreg
= MIPS_A0_REGNUM
;
4538 float_argreg
= mips_fpa0_regnum (gdbarch
);
4540 /* The struct_return pointer occupies the first parameter-passing reg. */
4541 if (return_method
== return_method_struct
)
4544 fprintf_unfiltered (gdb_stdlog
,
4545 "mips_eabi_push_dummy_call: "
4546 "struct_return reg=%d %s\n",
4547 argreg
, paddress (gdbarch
, struct_addr
));
4548 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4551 /* Now load as many as possible of the first arguments into
4552 registers, and push the rest onto the stack. Loop thru args
4553 from first to last. */
4554 for (argnum
= 0; argnum
< nargs
; argnum
++)
4556 const gdb_byte
*val
;
4557 /* This holds the address of structures that are passed by
4559 gdb_byte ref_valbuf
[MAX_MIPS_ABI_REGSIZE
];
4560 struct value
*arg
= args
[argnum
];
4561 struct type
*arg_type
= check_typedef (value_type (arg
));
4562 int len
= TYPE_LENGTH (arg_type
);
4563 enum type_code typecode
= arg_type
->code ();
4566 fprintf_unfiltered (gdb_stdlog
,
4567 "mips_eabi_push_dummy_call: %d len=%d type=%d",
4568 argnum
+ 1, len
, (int) typecode
);
4570 /* The EABI passes structures that do not fit in a register by
4572 if (len
> abi_regsize
4573 && (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
))
4575 gdb_assert (abi_regsize
<= ARRAY_SIZE (ref_valbuf
));
4576 store_unsigned_integer (ref_valbuf
, abi_regsize
, byte_order
,
4577 value_address (arg
));
4578 typecode
= TYPE_CODE_PTR
;
4582 fprintf_unfiltered (gdb_stdlog
, " push");
4585 val
= value_contents (arg
);
4587 /* 32-bit ABIs always start floating point arguments in an
4588 even-numbered floating point register. Round the FP register
4589 up before the check to see if there are any FP registers
4590 left. Non MIPS_EABI targets also pass the FP in the integer
4591 registers so also round up normal registers. */
4592 if (abi_regsize
< 8 && fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4594 if ((float_argreg
& 1))
4598 /* Floating point arguments passed in registers have to be
4599 treated specially. On 32-bit architectures, doubles
4600 are passed in register pairs; the even register gets
4601 the low word, and the odd register gets the high word.
4602 On non-EABI processors, the first two floating point arguments are
4603 also copied to general registers, because MIPS16 functions
4604 don't use float registers for arguments. This duplication of
4605 arguments in general registers can't hurt non-MIPS16 functions
4606 because those registers are normally skipped. */
4607 /* MIPS_EABI squeezes a struct that contains a single floating
4608 point value into an FP register instead of pushing it onto the
4610 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4611 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
4613 /* EABI32 will pass doubles in consecutive registers, even on
4614 64-bit cores. At one time, we used to check the size of
4615 `float_argreg' to determine whether or not to pass doubles
4616 in consecutive registers, but this is not sufficient for
4617 making the ABI determination. */
4618 if (len
== 8 && mips_abi (gdbarch
) == MIPS_ABI_EABI32
)
4620 int low_offset
= gdbarch_byte_order (gdbarch
)
4621 == BFD_ENDIAN_BIG
? 4 : 0;
4624 /* Write the low word of the double to the even register(s). */
4625 regval
= extract_signed_integer (val
+ low_offset
,
4628 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4629 float_argreg
, phex (regval
, 4));
4630 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4632 /* Write the high word of the double to the odd register(s). */
4633 regval
= extract_signed_integer (val
+ 4 - low_offset
,
4636 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4637 float_argreg
, phex (regval
, 4));
4638 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4642 /* This is a floating point value that fits entirely
4643 in a single register. */
4644 /* On 32 bit ABI's the float_argreg is further adjusted
4645 above to ensure that it is even register aligned. */
4646 LONGEST regval
= extract_signed_integer (val
, len
, byte_order
);
4648 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4649 float_argreg
, phex (regval
, len
));
4650 regcache_cooked_write_signed (regcache
, float_argreg
++, regval
);
4655 /* Copy the argument to general registers or the stack in
4656 register-sized pieces. Large arguments are split between
4657 registers and stack. */
4658 /* Note: structs whose size is not a multiple of abi_regsize
4659 are treated specially: Irix cc passes
4660 them in registers where gcc sometimes puts them on the
4661 stack. For maximum compatibility, we will put them in
4663 int odd_sized_struct
= (len
> abi_regsize
&& len
% abi_regsize
!= 0);
4665 /* Note: Floating-point values that didn't fit into an FP
4666 register are only written to memory. */
4669 /* Remember if the argument was written to the stack. */
4670 int stack_used_p
= 0;
4671 int partial_len
= (len
< abi_regsize
? len
: abi_regsize
);
4674 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
4677 /* Write this portion of the argument to the stack. */
4678 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
4680 || fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4682 /* Should shorter than int integer values be
4683 promoted to int before being stored? */
4684 int longword_offset
= 0;
4687 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
4689 if (abi_regsize
== 8
4690 && (typecode
== TYPE_CODE_INT
4691 || typecode
== TYPE_CODE_PTR
4692 || typecode
== TYPE_CODE_FLT
) && len
<= 4)
4693 longword_offset
= abi_regsize
- len
;
4694 else if ((typecode
== TYPE_CODE_STRUCT
4695 || typecode
== TYPE_CODE_UNION
)
4696 && TYPE_LENGTH (arg_type
) < abi_regsize
)
4697 longword_offset
= abi_regsize
- len
;
4702 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
4703 paddress (gdbarch
, stack_offset
));
4704 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
4705 paddress (gdbarch
, longword_offset
));
4708 addr
= sp
+ stack_offset
+ longword_offset
;
4713 fprintf_unfiltered (gdb_stdlog
, " @%s ",
4714 paddress (gdbarch
, addr
));
4715 for (i
= 0; i
< partial_len
; i
++)
4717 fprintf_unfiltered (gdb_stdlog
, "%02x",
4721 write_memory (addr
, val
, partial_len
);
4724 /* Note!!! This is NOT an else clause. Odd sized
4725 structs may go thru BOTH paths. Floating point
4726 arguments will not. */
4727 /* Write this portion of the argument to a general
4728 purpose register. */
4729 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
)
4730 && !fp_register_arg_p (gdbarch
, typecode
, arg_type
))
4733 extract_signed_integer (val
, partial_len
, byte_order
);
4736 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
4738 phex (regval
, abi_regsize
));
4739 regcache_cooked_write_signed (regcache
, argreg
, regval
);
4746 /* Compute the offset into the stack at which we will
4747 copy the next parameter.
4749 In the new EABI (and the NABI32), the stack_offset
4750 only needs to be adjusted when it has been used. */
4753 stack_offset
+= align_up (partial_len
, abi_regsize
);
4757 fprintf_unfiltered (gdb_stdlog
, "\n");
4760 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
4762 /* Return adjusted stack pointer. */
4766 /* Determine the return value convention being used. */
4768 static enum return_value_convention
4769 mips_eabi_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
4770 struct type
*type
, struct regcache
*regcache
,
4771 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
4773 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
4774 int fp_return_type
= 0;
4775 int offset
, regnum
, xfer
;
4777 if (TYPE_LENGTH (type
) > 2 * mips_abi_regsize (gdbarch
))
4778 return RETURN_VALUE_STRUCT_CONVENTION
;
4780 /* Floating point type? */
4781 if (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
4783 if (type
->code () == TYPE_CODE_FLT
)
4785 /* Structs with a single field of float type
4786 are returned in a floating point register. */
4787 if ((type
->code () == TYPE_CODE_STRUCT
4788 || type
->code () == TYPE_CODE_UNION
)
4789 && type
->num_fields () == 1)
4791 struct type
*fieldtype
= type
->field (0).type ();
4793 if (check_typedef (fieldtype
)->code () == TYPE_CODE_FLT
)
4800 /* A floating-point value belongs in the least significant part
4803 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
4804 regnum
= mips_regnum (gdbarch
)->fp0
;
4808 /* An integer value goes in V0/V1. */
4810 fprintf_unfiltered (gdb_stderr
, "Return scalar in $v0\n");
4811 regnum
= MIPS_V0_REGNUM
;
4814 offset
< TYPE_LENGTH (type
);
4815 offset
+= mips_abi_regsize (gdbarch
), regnum
++)
4817 xfer
= mips_abi_regsize (gdbarch
);
4818 if (offset
+ xfer
> TYPE_LENGTH (type
))
4819 xfer
= TYPE_LENGTH (type
) - offset
;
4820 mips_xfer_register (gdbarch
, regcache
,
4821 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
4822 gdbarch_byte_order (gdbarch
), readbuf
, writebuf
,
4826 return RETURN_VALUE_REGISTER_CONVENTION
;
4830 /* N32/N64 ABI stuff. */
4832 /* Search for a naturally aligned double at OFFSET inside a struct
4833 ARG_TYPE. The N32 / N64 ABIs pass these in floating point
4837 mips_n32n64_fp_arg_chunk_p (struct gdbarch
*gdbarch
, struct type
*arg_type
,
4842 if (arg_type
->code () != TYPE_CODE_STRUCT
)
4845 if (MIPS_FPU_TYPE (gdbarch
) != MIPS_FPU_DOUBLE
)
4848 if (TYPE_LENGTH (arg_type
) < offset
+ MIPS64_REGSIZE
)
4851 for (i
= 0; i
< arg_type
->num_fields (); i
++)
4854 struct type
*field_type
;
4856 /* We're only looking at normal fields. */
4857 if (field_is_static (&arg_type
->field (i
))
4858 || (TYPE_FIELD_BITPOS (arg_type
, i
) % 8) != 0)
4861 /* If we have gone past the offset, there is no double to pass. */
4862 pos
= TYPE_FIELD_BITPOS (arg_type
, i
) / 8;
4866 field_type
= check_typedef (arg_type
->field (i
).type ());
4868 /* If this field is entirely before the requested offset, go
4869 on to the next one. */
4870 if (pos
+ TYPE_LENGTH (field_type
) <= offset
)
4873 /* If this is our special aligned double, we can stop. */
4874 if (field_type
->code () == TYPE_CODE_FLT
4875 && TYPE_LENGTH (field_type
) == MIPS64_REGSIZE
)
4878 /* This field starts at or before the requested offset, and
4879 overlaps it. If it is a structure, recurse inwards. */
4880 return mips_n32n64_fp_arg_chunk_p (gdbarch
, field_type
, offset
- pos
);
4887 mips_n32n64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
4888 struct regcache
*regcache
, CORE_ADDR bp_addr
,
4889 int nargs
, struct value
**args
, CORE_ADDR sp
,
4890 function_call_return_method return_method
,
4891 CORE_ADDR struct_addr
)
4897 int stack_offset
= 0;
4898 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4899 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
4901 /* For shared libraries, "t9" needs to point at the function
4903 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
4905 /* Set the return address register to point to the entry point of
4906 the program, where a breakpoint lies in wait. */
4907 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
4909 /* First ensure that the stack and structure return address (if any)
4910 are properly aligned. The stack has to be at least 64-bit
4911 aligned even on 32-bit machines, because doubles must be 64-bit
4912 aligned. For n32 and n64, stack frames need to be 128-bit
4913 aligned, so we round to this widest known alignment. */
4915 sp
= align_down (sp
, 16);
4916 struct_addr
= align_down (struct_addr
, 16);
4918 /* Now make space on the stack for the args. */
4919 for (argnum
= 0; argnum
< nargs
; argnum
++)
4920 arg_space
+= align_up (TYPE_LENGTH (value_type (args
[argnum
])), MIPS64_REGSIZE
);
4921 sp
-= align_up (arg_space
, 16);
4924 fprintf_unfiltered (gdb_stdlog
,
4925 "mips_n32n64_push_dummy_call: sp=%s allocated %ld\n",
4926 paddress (gdbarch
, sp
),
4927 (long) align_up (arg_space
, 16));
4929 /* Initialize the integer and float register pointers. */
4930 argreg
= MIPS_A0_REGNUM
;
4931 float_argreg
= mips_fpa0_regnum (gdbarch
);
4933 /* The struct_return pointer occupies the first parameter-passing reg. */
4934 if (return_method
== return_method_struct
)
4937 fprintf_unfiltered (gdb_stdlog
,
4938 "mips_n32n64_push_dummy_call: "
4939 "struct_return reg=%d %s\n",
4940 argreg
, paddress (gdbarch
, struct_addr
));
4941 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
4944 /* Now load as many as possible of the first arguments into
4945 registers, and push the rest onto the stack. Loop thru args
4946 from first to last. */
4947 for (argnum
= 0; argnum
< nargs
; argnum
++)
4949 const gdb_byte
*val
;
4950 struct value
*arg
= args
[argnum
];
4951 struct type
*arg_type
= check_typedef (value_type (arg
));
4952 int len
= TYPE_LENGTH (arg_type
);
4953 enum type_code typecode
= arg_type
->code ();
4956 fprintf_unfiltered (gdb_stdlog
,
4957 "mips_n32n64_push_dummy_call: %d len=%d type=%d",
4958 argnum
+ 1, len
, (int) typecode
);
4960 val
= value_contents (arg
);
4962 /* A 128-bit long double value requires an even-odd pair of
4963 floating-point registers. */
4965 && fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4966 && (float_argreg
& 1))
4972 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
4973 && argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
4975 /* This is a floating point value that fits entirely
4976 in a single register or a pair of registers. */
4977 int reglen
= (len
<= MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
4978 LONGEST regval
= extract_unsigned_integer (val
, reglen
, byte_order
);
4980 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4981 float_argreg
, phex (regval
, reglen
));
4982 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
4985 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
4986 argreg
, phex (regval
, reglen
));
4987 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
4992 regval
= extract_unsigned_integer (val
+ reglen
,
4993 reglen
, byte_order
);
4995 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
4996 float_argreg
, phex (regval
, reglen
));
4997 regcache_cooked_write_unsigned (regcache
, float_argreg
, regval
);
5000 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5001 argreg
, phex (regval
, reglen
));
5002 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5009 /* Copy the argument to general registers or the stack in
5010 register-sized pieces. Large arguments are split between
5011 registers and stack. */
5012 /* For N32/N64, structs, unions, or other composite types are
5013 treated as a sequence of doublewords, and are passed in integer
5014 or floating point registers as though they were simple scalar
5015 parameters to the extent that they fit, with any excess on the
5016 stack packed according to the normal memory layout of the
5018 The caller does not reserve space for the register arguments;
5019 the callee is responsible for reserving it if required. */
5020 /* Note: Floating-point values that didn't fit into an FP
5021 register are only written to memory. */
5024 /* Remember if the argument was written to the stack. */
5025 int stack_used_p
= 0;
5026 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5029 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5032 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5033 gdb_assert (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
));
5035 /* Write this portion of the argument to the stack. */
5036 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
))
5038 /* Should shorter than int integer values be
5039 promoted to int before being stored? */
5040 int longword_offset
= 0;
5043 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
5045 if ((typecode
== TYPE_CODE_INT
5046 || typecode
== TYPE_CODE_PTR
)
5048 longword_offset
= MIPS64_REGSIZE
- len
;
5053 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5054 paddress (gdbarch
, stack_offset
));
5055 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5056 paddress (gdbarch
, longword_offset
));
5059 addr
= sp
+ stack_offset
+ longword_offset
;
5064 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5065 paddress (gdbarch
, addr
));
5066 for (i
= 0; i
< partial_len
; i
++)
5068 fprintf_unfiltered (gdb_stdlog
, "%02x",
5072 write_memory (addr
, val
, partial_len
);
5075 /* Note!!! This is NOT an else clause. Odd sized
5076 structs may go thru BOTH paths. */
5077 /* Write this portion of the argument to a general
5078 purpose register. */
5079 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5083 /* Sign extend pointers, 32-bit integers and signed
5084 16-bit and 8-bit integers; everything else is taken
5087 if ((partial_len
== 4
5088 && (typecode
== TYPE_CODE_PTR
5089 || typecode
== TYPE_CODE_INT
))
5091 && typecode
== TYPE_CODE_INT
5092 && !arg_type
->is_unsigned ()))
5093 regval
= extract_signed_integer (val
, partial_len
,
5096 regval
= extract_unsigned_integer (val
, partial_len
,
5099 /* A non-floating-point argument being passed in a
5100 general register. If a struct or union, and if
5101 the remaining length is smaller than the register
5102 size, we have to adjust the register value on
5105 It does not seem to be necessary to do the
5106 same for integral types. */
5108 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5109 && partial_len
< MIPS64_REGSIZE
5110 && (typecode
== TYPE_CODE_STRUCT
5111 || typecode
== TYPE_CODE_UNION
))
5112 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
5116 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5118 phex (regval
, MIPS64_REGSIZE
));
5119 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5121 if (mips_n32n64_fp_arg_chunk_p (gdbarch
, arg_type
,
5122 TYPE_LENGTH (arg_type
) - len
))
5125 fprintf_filtered (gdb_stdlog
, " - fpreg=%d val=%s",
5127 phex (regval
, MIPS64_REGSIZE
));
5128 regcache_cooked_write_unsigned (regcache
, float_argreg
,
5139 /* Compute the offset into the stack at which we will
5140 copy the next parameter.
5142 In N32 (N64?), the stack_offset only needs to be
5143 adjusted when it has been used. */
5146 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
5150 fprintf_unfiltered (gdb_stdlog
, "\n");
5153 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5155 /* Return adjusted stack pointer. */
5159 static enum return_value_convention
5160 mips_n32n64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5161 struct type
*type
, struct regcache
*regcache
,
5162 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5164 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5166 /* From MIPSpro N32 ABI Handbook, Document Number: 007-2816-004
5168 Function results are returned in $2 (and $3 if needed), or $f0 (and $f2
5169 if needed), as appropriate for the type. Composite results (struct,
5170 union, or array) are returned in $2/$f0 and $3/$f2 according to the
5173 * A struct with only one or two floating point fields is returned in $f0
5174 (and $f2 if necessary). This is a generalization of the Fortran COMPLEX
5177 * Any other composite results of at most 128 bits are returned in
5178 $2 (first 64 bits) and $3 (remainder, if necessary).
5180 * Larger composite results are handled by converting the function to a
5181 procedure with an implicit first parameter, which is a pointer to an area
5182 reserved by the caller to receive the result. [The o32-bit ABI requires
5183 that all composite results be handled by conversion to implicit first
5184 parameters. The MIPS/SGI Fortran implementation has always made a
5185 specific exception to return COMPLEX results in the floating point
5188 if (TYPE_LENGTH (type
) > 2 * MIPS64_REGSIZE
)
5189 return RETURN_VALUE_STRUCT_CONVENTION
;
5190 else if (type
->code () == TYPE_CODE_FLT
5191 && TYPE_LENGTH (type
) == 16
5192 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5194 /* A 128-bit floating-point value fills both $f0 and $f2. The
5195 two registers are used in the same as memory order, so the
5196 eight bytes with the lower memory address are in $f0. */
5198 fprintf_unfiltered (gdb_stderr
, "Return float in $f0 and $f2\n");
5199 mips_xfer_register (gdbarch
, regcache
,
5200 (gdbarch_num_regs (gdbarch
)
5201 + mips_regnum (gdbarch
)->fp0
),
5202 8, gdbarch_byte_order (gdbarch
),
5203 readbuf
, writebuf
, 0);
5204 mips_xfer_register (gdbarch
, regcache
,
5205 (gdbarch_num_regs (gdbarch
)
5206 + mips_regnum (gdbarch
)->fp0
+ 2),
5207 8, gdbarch_byte_order (gdbarch
),
5208 readbuf
? readbuf
+ 8 : readbuf
,
5209 writebuf
? writebuf
+ 8 : writebuf
, 0);
5210 return RETURN_VALUE_REGISTER_CONVENTION
;
5212 else if (type
->code () == TYPE_CODE_FLT
5213 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5215 /* A single or double floating-point value that fits in FP0. */
5217 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5218 mips_xfer_register (gdbarch
, regcache
,
5219 (gdbarch_num_regs (gdbarch
)
5220 + mips_regnum (gdbarch
)->fp0
),
5222 gdbarch_byte_order (gdbarch
),
5223 readbuf
, writebuf
, 0);
5224 return RETURN_VALUE_REGISTER_CONVENTION
;
5226 else if (type
->code () == TYPE_CODE_STRUCT
5227 && type
->num_fields () <= 2
5228 && type
->num_fields () >= 1
5229 && ((type
->num_fields () == 1
5230 && (check_typedef (type
->field (0).type ())->code ()
5232 || (type
->num_fields () == 2
5233 && (check_typedef (type
->field (0).type ())->code ()
5235 && (check_typedef (type
->field (1).type ())->code ()
5236 == TYPE_CODE_FLT
))))
5238 /* A struct that contains one or two floats. Each value is part
5239 in the least significant part of their floating point
5240 register (or GPR, for soft float). */
5243 for (field
= 0, regnum
= (tdep
->mips_fpu_type
!= MIPS_FPU_NONE
5244 ? mips_regnum (gdbarch
)->fp0
5246 field
< type
->num_fields (); field
++, regnum
+= 2)
5248 int offset
= (FIELD_BITPOS (type
->field (field
))
5251 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5253 if (TYPE_LENGTH (type
->field (field
).type ()) == 16)
5255 /* A 16-byte long double field goes in two consecutive
5257 mips_xfer_register (gdbarch
, regcache
,
5258 gdbarch_num_regs (gdbarch
) + regnum
,
5260 gdbarch_byte_order (gdbarch
),
5261 readbuf
, writebuf
, offset
);
5262 mips_xfer_register (gdbarch
, regcache
,
5263 gdbarch_num_regs (gdbarch
) + regnum
+ 1,
5265 gdbarch_byte_order (gdbarch
),
5266 readbuf
, writebuf
, offset
+ 8);
5269 mips_xfer_register (gdbarch
, regcache
,
5270 gdbarch_num_regs (gdbarch
) + regnum
,
5271 TYPE_LENGTH (type
->field (field
).type ()),
5272 gdbarch_byte_order (gdbarch
),
5273 readbuf
, writebuf
, offset
);
5275 return RETURN_VALUE_REGISTER_CONVENTION
;
5277 else if (type
->code () == TYPE_CODE_STRUCT
5278 || type
->code () == TYPE_CODE_UNION
5279 || type
->code () == TYPE_CODE_ARRAY
)
5281 /* A composite type. Extract the left justified value,
5282 regardless of the byte order. I.e. DO NOT USE
5286 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5287 offset
< TYPE_LENGTH (type
);
5288 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5290 int xfer
= register_size (gdbarch
, regnum
);
5291 if (offset
+ xfer
> TYPE_LENGTH (type
))
5292 xfer
= TYPE_LENGTH (type
) - offset
;
5294 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5295 offset
, xfer
, regnum
);
5296 mips_xfer_register (gdbarch
, regcache
,
5297 gdbarch_num_regs (gdbarch
) + regnum
,
5298 xfer
, BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
,
5301 return RETURN_VALUE_REGISTER_CONVENTION
;
5305 /* A scalar extract each part but least-significant-byte
5309 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5310 offset
< TYPE_LENGTH (type
);
5311 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5313 int xfer
= register_size (gdbarch
, regnum
);
5314 if (offset
+ xfer
> TYPE_LENGTH (type
))
5315 xfer
= TYPE_LENGTH (type
) - offset
;
5317 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5318 offset
, xfer
, regnum
);
5319 mips_xfer_register (gdbarch
, regcache
,
5320 gdbarch_num_regs (gdbarch
) + regnum
,
5321 xfer
, gdbarch_byte_order (gdbarch
),
5322 readbuf
, writebuf
, offset
);
5324 return RETURN_VALUE_REGISTER_CONVENTION
;
5328 /* Which registers to use for passing floating-point values between
5329 function calls, one of floating-point, general and both kinds of
5330 registers. O32 and O64 use different register kinds for standard
5331 MIPS and MIPS16 code; to make the handling of cases where we may
5332 not know what kind of code is being used (e.g. no debug information)
5333 easier we sometimes use both kinds. */
5342 /* O32 ABI stuff. */
5345 mips_o32_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5346 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5347 int nargs
, struct value
**args
, CORE_ADDR sp
,
5348 function_call_return_method return_method
,
5349 CORE_ADDR struct_addr
)
5355 int stack_offset
= 0;
5356 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5357 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5359 /* For shared libraries, "t9" needs to point at the function
5361 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5363 /* Set the return address register to point to the entry point of
5364 the program, where a breakpoint lies in wait. */
5365 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5367 /* First ensure that the stack and structure return address (if any)
5368 are properly aligned. The stack has to be at least 64-bit
5369 aligned even on 32-bit machines, because doubles must be 64-bit
5370 aligned. For n32 and n64, stack frames need to be 128-bit
5371 aligned, so we round to this widest known alignment. */
5373 sp
= align_down (sp
, 16);
5374 struct_addr
= align_down (struct_addr
, 16);
5376 /* Now make space on the stack for the args. */
5377 for (argnum
= 0; argnum
< nargs
; argnum
++)
5379 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5381 /* Align to double-word if necessary. */
5382 if (mips_type_needs_double_align (arg_type
))
5383 arg_space
= align_up (arg_space
, MIPS32_REGSIZE
* 2);
5384 /* Allocate space on the stack. */
5385 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS32_REGSIZE
);
5387 sp
-= align_up (arg_space
, 16);
5390 fprintf_unfiltered (gdb_stdlog
,
5391 "mips_o32_push_dummy_call: sp=%s allocated %ld\n",
5392 paddress (gdbarch
, sp
),
5393 (long) align_up (arg_space
, 16));
5395 /* Initialize the integer and float register pointers. */
5396 argreg
= MIPS_A0_REGNUM
;
5397 float_argreg
= mips_fpa0_regnum (gdbarch
);
5399 /* The struct_return pointer occupies the first parameter-passing reg. */
5400 if (return_method
== return_method_struct
)
5403 fprintf_unfiltered (gdb_stdlog
,
5404 "mips_o32_push_dummy_call: "
5405 "struct_return reg=%d %s\n",
5406 argreg
, paddress (gdbarch
, struct_addr
));
5407 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5408 stack_offset
+= MIPS32_REGSIZE
;
5411 /* Now load as many as possible of the first arguments into
5412 registers, and push the rest onto the stack. Loop thru args
5413 from first to last. */
5414 for (argnum
= 0; argnum
< nargs
; argnum
++)
5416 const gdb_byte
*val
;
5417 struct value
*arg
= args
[argnum
];
5418 struct type
*arg_type
= check_typedef (value_type (arg
));
5419 int len
= TYPE_LENGTH (arg_type
);
5420 enum type_code typecode
= arg_type
->code ();
5423 fprintf_unfiltered (gdb_stdlog
,
5424 "mips_o32_push_dummy_call: %d len=%d type=%d",
5425 argnum
+ 1, len
, (int) typecode
);
5427 val
= value_contents (arg
);
5429 /* 32-bit ABIs always start floating point arguments in an
5430 even-numbered floating point register. Round the FP register
5431 up before the check to see if there are any FP registers
5432 left. O32 targets also pass the FP in the integer registers
5433 so also round up normal registers. */
5434 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
))
5436 if ((float_argreg
& 1))
5440 /* Floating point arguments passed in registers have to be
5441 treated specially. On 32-bit architectures, doubles are
5442 passed in register pairs; the even FP register gets the
5443 low word, and the odd FP register gets the high word.
5444 On O32, the first two floating point arguments are also
5445 copied to general registers, following their memory order,
5446 because MIPS16 functions don't use float registers for
5447 arguments. This duplication of arguments in general
5448 registers can't hurt non-MIPS16 functions, because those
5449 registers are normally skipped. */
5451 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5452 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5454 if (register_size (gdbarch
, float_argreg
) < 8 && len
== 8)
5456 int freg_offset
= gdbarch_byte_order (gdbarch
)
5457 == BFD_ENDIAN_BIG
? 1 : 0;
5458 unsigned long regval
;
5461 regval
= extract_unsigned_integer (val
, 4, byte_order
);
5463 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5464 float_argreg
+ freg_offset
,
5466 regcache_cooked_write_unsigned (regcache
,
5467 float_argreg
++ + freg_offset
,
5470 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5471 argreg
, phex (regval
, 4));
5472 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5475 regval
= extract_unsigned_integer (val
+ 4, 4, byte_order
);
5477 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5478 float_argreg
- freg_offset
,
5480 regcache_cooked_write_unsigned (regcache
,
5481 float_argreg
++ - freg_offset
,
5484 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5485 argreg
, phex (regval
, 4));
5486 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5490 /* This is a floating point value that fits entirely
5491 in a single register. */
5492 /* On 32 bit ABI's the float_argreg is further adjusted
5493 above to ensure that it is even register aligned. */
5494 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5496 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5497 float_argreg
, phex (regval
, len
));
5498 regcache_cooked_write_unsigned (regcache
,
5499 float_argreg
++, regval
);
5500 /* Although two FP registers are reserved for each
5501 argument, only one corresponding integer register is
5504 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5505 argreg
, phex (regval
, len
));
5506 regcache_cooked_write_unsigned (regcache
, argreg
++, regval
);
5508 /* Reserve space for the FP register. */
5509 stack_offset
+= align_up (len
, MIPS32_REGSIZE
);
5513 /* Copy the argument to general registers or the stack in
5514 register-sized pieces. Large arguments are split between
5515 registers and stack. */
5516 /* Note: structs whose size is not a multiple of MIPS32_REGSIZE
5517 are treated specially: Irix cc passes
5518 them in registers where gcc sometimes puts them on the
5519 stack. For maximum compatibility, we will put them in
5521 int odd_sized_struct
= (len
> MIPS32_REGSIZE
5522 && len
% MIPS32_REGSIZE
!= 0);
5523 /* Structures should be aligned to eight bytes (even arg registers)
5524 on MIPS_ABI_O32, if their first member has double precision. */
5525 if (mips_type_needs_double_align (arg_type
))
5530 stack_offset
+= MIPS32_REGSIZE
;
5535 int partial_len
= (len
< MIPS32_REGSIZE
? len
: MIPS32_REGSIZE
);
5538 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5541 /* Write this portion of the argument to the stack. */
5542 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5543 || odd_sized_struct
)
5545 /* Should shorter than int integer values be
5546 promoted to int before being stored? */
5547 int longword_offset
= 0;
5552 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
5553 paddress (gdbarch
, stack_offset
));
5554 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
5555 paddress (gdbarch
, longword_offset
));
5558 addr
= sp
+ stack_offset
+ longword_offset
;
5563 fprintf_unfiltered (gdb_stdlog
, " @%s ",
5564 paddress (gdbarch
, addr
));
5565 for (i
= 0; i
< partial_len
; i
++)
5567 fprintf_unfiltered (gdb_stdlog
, "%02x",
5571 write_memory (addr
, val
, partial_len
);
5574 /* Note!!! This is NOT an else clause. Odd sized
5575 structs may go thru BOTH paths. */
5576 /* Write this portion of the argument to a general
5577 purpose register. */
5578 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
5580 LONGEST regval
= extract_signed_integer (val
, partial_len
,
5582 /* Value may need to be sign extended, because
5583 mips_isa_regsize() != mips_abi_regsize(). */
5585 /* A non-floating-point argument being passed in a
5586 general register. If a struct or union, and if
5587 the remaining length is smaller than the register
5588 size, we have to adjust the register value on
5591 It does not seem to be necessary to do the
5592 same for integral types.
5594 Also don't do this adjustment on O64 binaries.
5596 cagney/2001-07-23: gdb/179: Also, GCC, when
5597 outputting LE O32 with sizeof (struct) <
5598 mips_abi_regsize(), generates a left shift
5599 as part of storing the argument in a register
5600 (the left shift isn't generated when
5601 sizeof (struct) >= mips_abi_regsize()). Since
5602 it is quite possible that this is GCC
5603 contradicting the LE/O32 ABI, GDB has not been
5604 adjusted to accommodate this. Either someone
5605 needs to demonstrate that the LE/O32 ABI
5606 specifies such a left shift OR this new ABI gets
5607 identified as such and GDB gets tweaked
5610 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
5611 && partial_len
< MIPS32_REGSIZE
5612 && (typecode
== TYPE_CODE_STRUCT
5613 || typecode
== TYPE_CODE_UNION
))
5614 regval
<<= ((MIPS32_REGSIZE
- partial_len
)
5618 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
5620 phex (regval
, MIPS32_REGSIZE
));
5621 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5624 /* Prevent subsequent floating point arguments from
5625 being passed in floating point registers. */
5626 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
5632 /* Compute the offset into the stack at which we will
5633 copy the next parameter.
5635 In older ABIs, the caller reserved space for
5636 registers that contained arguments. This was loosely
5637 refered to as their "home". Consequently, space is
5638 always allocated. */
5640 stack_offset
+= align_up (partial_len
, MIPS32_REGSIZE
);
5644 fprintf_unfiltered (gdb_stdlog
, "\n");
5647 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
5649 /* Return adjusted stack pointer. */
5653 static enum return_value_convention
5654 mips_o32_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
5655 struct type
*type
, struct regcache
*regcache
,
5656 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
5658 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
5659 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
5660 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
5661 enum mips_fval_reg fval_reg
;
5663 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
5664 if (type
->code () == TYPE_CODE_STRUCT
5665 || type
->code () == TYPE_CODE_UNION
5666 || type
->code () == TYPE_CODE_ARRAY
)
5667 return RETURN_VALUE_STRUCT_CONVENTION
;
5668 else if (type
->code () == TYPE_CODE_FLT
5669 && TYPE_LENGTH (type
) == 4 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5671 /* A single-precision floating-point value. If reading in or copying,
5672 then we get it from/put it to FP0 for standard MIPS code or GPR2
5673 for MIPS16 code. If writing out only, then we put it to both FP0
5674 and GPR2. We do not support reading in with no function known, if
5675 this safety check ever triggers, then we'll have to try harder. */
5676 gdb_assert (function
|| !readbuf
);
5681 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
5684 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
5686 case mips_fval_both
:
5687 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
5690 if (fval_reg
!= mips_fval_gpr
)
5691 mips_xfer_register (gdbarch
, regcache
,
5692 (gdbarch_num_regs (gdbarch
)
5693 + mips_regnum (gdbarch
)->fp0
),
5695 gdbarch_byte_order (gdbarch
),
5696 readbuf
, writebuf
, 0);
5697 if (fval_reg
!= mips_fval_fpr
)
5698 mips_xfer_register (gdbarch
, regcache
,
5699 gdbarch_num_regs (gdbarch
) + 2,
5701 gdbarch_byte_order (gdbarch
),
5702 readbuf
, writebuf
, 0);
5703 return RETURN_VALUE_REGISTER_CONVENTION
;
5705 else if (type
->code () == TYPE_CODE_FLT
5706 && TYPE_LENGTH (type
) == 8 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5708 /* A double-precision floating-point value. If reading in or copying,
5709 then we get it from/put it to FP1 and FP0 for standard MIPS code or
5710 GPR2 and GPR3 for MIPS16 code. If writing out only, then we put it
5711 to both FP1/FP0 and GPR2/GPR3. We do not support reading in with
5712 no function known, if this safety check ever triggers, then we'll
5713 have to try harder. */
5714 gdb_assert (function
|| !readbuf
);
5719 fprintf_unfiltered (gdb_stderr
, "Return float in $fp1/$fp0\n");
5722 fprintf_unfiltered (gdb_stderr
, "Return float in $2/$3\n");
5724 case mips_fval_both
:
5725 fprintf_unfiltered (gdb_stderr
,
5726 "Return float in $fp1/$fp0 and $2/$3\n");
5729 if (fval_reg
!= mips_fval_gpr
)
5731 /* The most significant part goes in FP1, and the least significant
5733 switch (gdbarch_byte_order (gdbarch
))
5735 case BFD_ENDIAN_LITTLE
:
5736 mips_xfer_register (gdbarch
, regcache
,
5737 (gdbarch_num_regs (gdbarch
)
5738 + mips_regnum (gdbarch
)->fp0
+ 0),
5739 4, gdbarch_byte_order (gdbarch
),
5740 readbuf
, writebuf
, 0);
5741 mips_xfer_register (gdbarch
, regcache
,
5742 (gdbarch_num_regs (gdbarch
)
5743 + mips_regnum (gdbarch
)->fp0
+ 1),
5744 4, gdbarch_byte_order (gdbarch
),
5745 readbuf
, writebuf
, 4);
5747 case BFD_ENDIAN_BIG
:
5748 mips_xfer_register (gdbarch
, regcache
,
5749 (gdbarch_num_regs (gdbarch
)
5750 + mips_regnum (gdbarch
)->fp0
+ 1),
5751 4, gdbarch_byte_order (gdbarch
),
5752 readbuf
, writebuf
, 0);
5753 mips_xfer_register (gdbarch
, regcache
,
5754 (gdbarch_num_regs (gdbarch
)
5755 + mips_regnum (gdbarch
)->fp0
+ 0),
5756 4, gdbarch_byte_order (gdbarch
),
5757 readbuf
, writebuf
, 4);
5760 internal_error (__FILE__
, __LINE__
, _("bad switch"));
5763 if (fval_reg
!= mips_fval_fpr
)
5765 /* The two 32-bit parts are always placed in GPR2 and GPR3
5766 following these registers' memory order. */
5767 mips_xfer_register (gdbarch
, regcache
,
5768 gdbarch_num_regs (gdbarch
) + 2,
5769 4, gdbarch_byte_order (gdbarch
),
5770 readbuf
, writebuf
, 0);
5771 mips_xfer_register (gdbarch
, regcache
,
5772 gdbarch_num_regs (gdbarch
) + 3,
5773 4, gdbarch_byte_order (gdbarch
),
5774 readbuf
, writebuf
, 4);
5776 return RETURN_VALUE_REGISTER_CONVENTION
;
5779 else if (type
->code () == TYPE_CODE_STRUCT
5780 && type
->num_fields () <= 2
5781 && type
->num_fields () >= 1
5782 && ((type
->num_fields () == 1
5783 && (TYPE_CODE (type
->field (0).type ())
5785 || (type
->num_fields () == 2
5786 && (TYPE_CODE (type
->field (0).type ())
5788 && (TYPE_CODE (type
->field (1).type ())
5790 && tdep
->mips_fpu_type
!= MIPS_FPU_NONE
)
5792 /* A struct that contains one or two floats. Each value is part
5793 in the least significant part of their floating point
5797 for (field
= 0, regnum
= mips_regnum (gdbarch
)->fp0
;
5798 field
< type
->num_fields (); field
++, regnum
+= 2)
5800 int offset
= (FIELD_BITPOS (type
->fields ()[field
])
5803 fprintf_unfiltered (gdb_stderr
, "Return float struct+%d\n",
5805 mips_xfer_register (gdbarch
, regcache
,
5806 gdbarch_num_regs (gdbarch
) + regnum
,
5807 TYPE_LENGTH (type
->field (field
).type ()),
5808 gdbarch_byte_order (gdbarch
),
5809 readbuf
, writebuf
, offset
);
5811 return RETURN_VALUE_REGISTER_CONVENTION
;
5815 else if (type
->code () == TYPE_CODE_STRUCT
5816 || type
->code () == TYPE_CODE_UNION
)
5818 /* A structure or union. Extract the left justified value,
5819 regardless of the byte order. I.e. DO NOT USE
5823 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5824 offset
< TYPE_LENGTH (type
);
5825 offset
+= register_size (gdbarch
, regnum
), regnum
++)
5827 int xfer
= register_size (gdbarch
, regnum
);
5828 if (offset
+ xfer
> TYPE_LENGTH (type
))
5829 xfer
= TYPE_LENGTH (type
) - offset
;
5831 fprintf_unfiltered (gdb_stderr
, "Return struct+%d:%d in $%d\n",
5832 offset
, xfer
, regnum
);
5833 mips_xfer_register (gdbarch
, regcache
,
5834 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5835 BFD_ENDIAN_UNKNOWN
, readbuf
, writebuf
, offset
);
5837 return RETURN_VALUE_REGISTER_CONVENTION
;
5842 /* A scalar extract each part but least-significant-byte
5843 justified. o32 thinks registers are 4 byte, regardless of
5847 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
5848 offset
< TYPE_LENGTH (type
);
5849 offset
+= MIPS32_REGSIZE
, regnum
++)
5851 int xfer
= MIPS32_REGSIZE
;
5852 if (offset
+ xfer
> TYPE_LENGTH (type
))
5853 xfer
= TYPE_LENGTH (type
) - offset
;
5855 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
5856 offset
, xfer
, regnum
);
5857 mips_xfer_register (gdbarch
, regcache
,
5858 gdbarch_num_regs (gdbarch
) + regnum
, xfer
,
5859 gdbarch_byte_order (gdbarch
),
5860 readbuf
, writebuf
, offset
);
5862 return RETURN_VALUE_REGISTER_CONVENTION
;
5866 /* O64 ABI. This is a hacked up kind of 64-bit version of the o32
5870 mips_o64_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
5871 struct regcache
*regcache
, CORE_ADDR bp_addr
,
5873 struct value
**args
, CORE_ADDR sp
,
5874 function_call_return_method return_method
, CORE_ADDR struct_addr
)
5880 int stack_offset
= 0;
5881 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5882 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
5884 /* For shared libraries, "t9" needs to point at the function
5886 regcache_cooked_write_signed (regcache
, MIPS_T9_REGNUM
, func_addr
);
5888 /* Set the return address register to point to the entry point of
5889 the program, where a breakpoint lies in wait. */
5890 regcache_cooked_write_signed (regcache
, MIPS_RA_REGNUM
, bp_addr
);
5892 /* First ensure that the stack and structure return address (if any)
5893 are properly aligned. The stack has to be at least 64-bit
5894 aligned even on 32-bit machines, because doubles must be 64-bit
5895 aligned. For n32 and n64, stack frames need to be 128-bit
5896 aligned, so we round to this widest known alignment. */
5898 sp
= align_down (sp
, 16);
5899 struct_addr
= align_down (struct_addr
, 16);
5901 /* Now make space on the stack for the args. */
5902 for (argnum
= 0; argnum
< nargs
; argnum
++)
5904 struct type
*arg_type
= check_typedef (value_type (args
[argnum
]));
5906 /* Allocate space on the stack. */
5907 arg_space
+= align_up (TYPE_LENGTH (arg_type
), MIPS64_REGSIZE
);
5909 sp
-= align_up (arg_space
, 16);
5912 fprintf_unfiltered (gdb_stdlog
,
5913 "mips_o64_push_dummy_call: sp=%s allocated %ld\n",
5914 paddress (gdbarch
, sp
),
5915 (long) align_up (arg_space
, 16));
5917 /* Initialize the integer and float register pointers. */
5918 argreg
= MIPS_A0_REGNUM
;
5919 float_argreg
= mips_fpa0_regnum (gdbarch
);
5921 /* The struct_return pointer occupies the first parameter-passing reg. */
5922 if (return_method
== return_method_struct
)
5925 fprintf_unfiltered (gdb_stdlog
,
5926 "mips_o64_push_dummy_call: "
5927 "struct_return reg=%d %s\n",
5928 argreg
, paddress (gdbarch
, struct_addr
));
5929 regcache_cooked_write_unsigned (regcache
, argreg
++, struct_addr
);
5930 stack_offset
+= MIPS64_REGSIZE
;
5933 /* Now load as many as possible of the first arguments into
5934 registers, and push the rest onto the stack. Loop thru args
5935 from first to last. */
5936 for (argnum
= 0; argnum
< nargs
; argnum
++)
5938 const gdb_byte
*val
;
5939 struct value
*arg
= args
[argnum
];
5940 struct type
*arg_type
= check_typedef (value_type (arg
));
5941 int len
= TYPE_LENGTH (arg_type
);
5942 enum type_code typecode
= arg_type
->code ();
5945 fprintf_unfiltered (gdb_stdlog
,
5946 "mips_o64_push_dummy_call: %d len=%d type=%d",
5947 argnum
+ 1, len
, (int) typecode
);
5949 val
= value_contents (arg
);
5951 /* Floating point arguments passed in registers have to be
5952 treated specially. On 32-bit architectures, doubles are
5953 passed in register pairs; the even FP register gets the
5954 low word, and the odd FP register gets the high word.
5955 On O64, the first two floating point arguments are also
5956 copied to general registers, because MIPS16 functions
5957 don't use float registers for arguments. This duplication
5958 of arguments in general registers can't hurt non-MIPS16
5959 functions because those registers are normally skipped. */
5961 if (fp_register_arg_p (gdbarch
, typecode
, arg_type
)
5962 && float_argreg
<= MIPS_LAST_FP_ARG_REGNUM (gdbarch
))
5964 LONGEST regval
= extract_unsigned_integer (val
, len
, byte_order
);
5966 fprintf_unfiltered (gdb_stdlog
, " - fpreg=%d val=%s",
5967 float_argreg
, phex (regval
, len
));
5968 regcache_cooked_write_unsigned (regcache
, float_argreg
++, regval
);
5970 fprintf_unfiltered (gdb_stdlog
, " - reg=%d val=%s",
5971 argreg
, phex (regval
, len
));
5972 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
5974 /* Reserve space for the FP register. */
5975 stack_offset
+= align_up (len
, MIPS64_REGSIZE
);
5979 /* Copy the argument to general registers or the stack in
5980 register-sized pieces. Large arguments are split between
5981 registers and stack. */
5982 /* Note: structs whose size is not a multiple of MIPS64_REGSIZE
5983 are treated specially: Irix cc passes them in registers
5984 where gcc sometimes puts them on the stack. For maximum
5985 compatibility, we will put them in both places. */
5986 int odd_sized_struct
= (len
> MIPS64_REGSIZE
5987 && len
% MIPS64_REGSIZE
!= 0);
5990 int partial_len
= (len
< MIPS64_REGSIZE
? len
: MIPS64_REGSIZE
);
5993 fprintf_unfiltered (gdb_stdlog
, " -- partial=%d",
5996 /* Write this portion of the argument to the stack. */
5997 if (argreg
> MIPS_LAST_ARG_REGNUM (gdbarch
)
5998 || odd_sized_struct
)
6000 /* Should shorter than int integer values be
6001 promoted to int before being stored? */
6002 int longword_offset
= 0;
6004 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6006 if ((typecode
== TYPE_CODE_INT
6007 || typecode
== TYPE_CODE_PTR
6008 || typecode
== TYPE_CODE_FLT
)
6010 longword_offset
= MIPS64_REGSIZE
- len
;
6015 fprintf_unfiltered (gdb_stdlog
, " - stack_offset=%s",
6016 paddress (gdbarch
, stack_offset
));
6017 fprintf_unfiltered (gdb_stdlog
, " longword_offset=%s",
6018 paddress (gdbarch
, longword_offset
));
6021 addr
= sp
+ stack_offset
+ longword_offset
;
6026 fprintf_unfiltered (gdb_stdlog
, " @%s ",
6027 paddress (gdbarch
, addr
));
6028 for (i
= 0; i
< partial_len
; i
++)
6030 fprintf_unfiltered (gdb_stdlog
, "%02x",
6034 write_memory (addr
, val
, partial_len
);
6037 /* Note!!! This is NOT an else clause. Odd sized
6038 structs may go thru BOTH paths. */
6039 /* Write this portion of the argument to a general
6040 purpose register. */
6041 if (argreg
<= MIPS_LAST_ARG_REGNUM (gdbarch
))
6043 LONGEST regval
= extract_signed_integer (val
, partial_len
,
6045 /* Value may need to be sign extended, because
6046 mips_isa_regsize() != mips_abi_regsize(). */
6048 /* A non-floating-point argument being passed in a
6049 general register. If a struct or union, and if
6050 the remaining length is smaller than the register
6051 size, we have to adjust the register value on
6054 It does not seem to be necessary to do the
6055 same for integral types. */
6057 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
6058 && partial_len
< MIPS64_REGSIZE
6059 && (typecode
== TYPE_CODE_STRUCT
6060 || typecode
== TYPE_CODE_UNION
))
6061 regval
<<= ((MIPS64_REGSIZE
- partial_len
)
6065 fprintf_filtered (gdb_stdlog
, " - reg=%d val=%s",
6067 phex (regval
, MIPS64_REGSIZE
));
6068 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
6071 /* Prevent subsequent floating point arguments from
6072 being passed in floating point registers. */
6073 float_argreg
= MIPS_LAST_FP_ARG_REGNUM (gdbarch
) + 1;
6079 /* Compute the offset into the stack at which we will
6080 copy the next parameter.
6082 In older ABIs, the caller reserved space for
6083 registers that contained arguments. This was loosely
6084 refered to as their "home". Consequently, space is
6085 always allocated. */
6087 stack_offset
+= align_up (partial_len
, MIPS64_REGSIZE
);
6091 fprintf_unfiltered (gdb_stdlog
, "\n");
6094 regcache_cooked_write_signed (regcache
, MIPS_SP_REGNUM
, sp
);
6096 /* Return adjusted stack pointer. */
6100 static enum return_value_convention
6101 mips_o64_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
6102 struct type
*type
, struct regcache
*regcache
,
6103 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
6105 CORE_ADDR func_addr
= function
? find_function_addr (function
, NULL
) : 0;
6106 int mips16
= mips_pc_is_mips16 (gdbarch
, func_addr
);
6107 enum mips_fval_reg fval_reg
;
6109 fval_reg
= readbuf
? mips16
? mips_fval_gpr
: mips_fval_fpr
: mips_fval_both
;
6110 if (type
->code () == TYPE_CODE_STRUCT
6111 || type
->code () == TYPE_CODE_UNION
6112 || type
->code () == TYPE_CODE_ARRAY
)
6113 return RETURN_VALUE_STRUCT_CONVENTION
;
6114 else if (fp_register_arg_p (gdbarch
, type
->code (), type
))
6116 /* A floating-point value. If reading in or copying, then we get it
6117 from/put it to FP0 for standard MIPS code or GPR2 for MIPS16 code.
6118 If writing out only, then we put it to both FP0 and GPR2. We do
6119 not support reading in with no function known, if this safety
6120 check ever triggers, then we'll have to try harder. */
6121 gdb_assert (function
|| !readbuf
);
6126 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0\n");
6129 fprintf_unfiltered (gdb_stderr
, "Return float in $2\n");
6131 case mips_fval_both
:
6132 fprintf_unfiltered (gdb_stderr
, "Return float in $fp0 and $2\n");
6135 if (fval_reg
!= mips_fval_gpr
)
6136 mips_xfer_register (gdbarch
, regcache
,
6137 (gdbarch_num_regs (gdbarch
)
6138 + mips_regnum (gdbarch
)->fp0
),
6140 gdbarch_byte_order (gdbarch
),
6141 readbuf
, writebuf
, 0);
6142 if (fval_reg
!= mips_fval_fpr
)
6143 mips_xfer_register (gdbarch
, regcache
,
6144 gdbarch_num_regs (gdbarch
) + 2,
6146 gdbarch_byte_order (gdbarch
),
6147 readbuf
, writebuf
, 0);
6148 return RETURN_VALUE_REGISTER_CONVENTION
;
6152 /* A scalar extract each part but least-significant-byte
6156 for (offset
= 0, regnum
= MIPS_V0_REGNUM
;
6157 offset
< TYPE_LENGTH (type
);
6158 offset
+= MIPS64_REGSIZE
, regnum
++)
6160 int xfer
= MIPS64_REGSIZE
;
6161 if (offset
+ xfer
> TYPE_LENGTH (type
))
6162 xfer
= TYPE_LENGTH (type
) - offset
;
6164 fprintf_unfiltered (gdb_stderr
, "Return scalar+%d:%d in $%d\n",
6165 offset
, xfer
, regnum
);
6166 mips_xfer_register (gdbarch
, regcache
,
6167 gdbarch_num_regs (gdbarch
) + regnum
,
6168 xfer
, gdbarch_byte_order (gdbarch
),
6169 readbuf
, writebuf
, offset
);
6171 return RETURN_VALUE_REGISTER_CONVENTION
;
6175 /* Floating point register management.
6177 Background: MIPS1 & 2 fp registers are 32 bits wide. To support
6178 64bit operations, these early MIPS cpus treat fp register pairs
6179 (f0,f1) as a single register (d0). Later MIPS cpu's have 64 bit fp
6180 registers and offer a compatibility mode that emulates the MIPS2 fp
6181 model. When operating in MIPS2 fp compat mode, later cpu's split
6182 double precision floats into two 32-bit chunks and store them in
6183 consecutive fp regs. To display 64-bit floats stored in this
6184 fashion, we have to combine 32 bits from f0 and 32 bits from f1.
6185 Throw in user-configurable endianness and you have a real mess.
6187 The way this works is:
6188 - If we are in 32-bit mode or on a 32-bit processor, then a 64-bit
6189 double-precision value will be split across two logical registers.
6190 The lower-numbered logical register will hold the low-order bits,
6191 regardless of the processor's endianness.
6192 - If we are on a 64-bit processor, and we are looking for a
6193 single-precision value, it will be in the low ordered bits
6194 of a 64-bit GPR (after mfc1, for example) or a 64-bit register
6195 save slot in memory.
6196 - If we are in 64-bit mode, everything is straightforward.
6198 Note that this code only deals with "live" registers at the top of the
6199 stack. We will attempt to deal with saved registers later, when
6200 the raw/cooked register interface is in place. (We need a general
6201 interface that can deal with dynamic saved register sizes -- fp
6202 regs could be 32 bits wide in one frame and 64 on the frame above
6205 /* Copy a 32-bit single-precision value from the current frame
6206 into rare_buffer. */
6209 mips_read_fp_register_single (struct frame_info
*frame
, int regno
,
6210 gdb_byte
*rare_buffer
)
6212 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6213 int raw_size
= register_size (gdbarch
, regno
);
6214 gdb_byte
*raw_buffer
= (gdb_byte
*) alloca (raw_size
);
6216 if (!deprecated_frame_register_read (frame
, regno
, raw_buffer
))
6217 error (_("can't read register %d (%s)"),
6218 regno
, gdbarch_register_name (gdbarch
, regno
));
6221 /* We have a 64-bit value for this register. Find the low-order
6225 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6230 memcpy (rare_buffer
, raw_buffer
+ offset
, 4);
6234 memcpy (rare_buffer
, raw_buffer
, 4);
6238 /* Copy a 64-bit double-precision value from the current frame into
6239 rare_buffer. This may include getting half of it from the next
6243 mips_read_fp_register_double (struct frame_info
*frame
, int regno
,
6244 gdb_byte
*rare_buffer
)
6246 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6247 int raw_size
= register_size (gdbarch
, regno
);
6249 if (raw_size
== 8 && !mips2_fp_compat (frame
))
6251 /* We have a 64-bit value for this register, and we should use
6253 if (!deprecated_frame_register_read (frame
, regno
, rare_buffer
))
6254 error (_("can't read register %d (%s)"),
6255 regno
, gdbarch_register_name (gdbarch
, regno
));
6259 int rawnum
= regno
% gdbarch_num_regs (gdbarch
);
6261 if ((rawnum
- mips_regnum (gdbarch
)->fp0
) & 1)
6262 internal_error (__FILE__
, __LINE__
,
6263 _("mips_read_fp_register_double: bad access to "
6264 "odd-numbered FP register"));
6266 /* mips_read_fp_register_single will find the correct 32 bits from
6268 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6270 mips_read_fp_register_single (frame
, regno
, rare_buffer
+ 4);
6271 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
);
6275 mips_read_fp_register_single (frame
, regno
, rare_buffer
);
6276 mips_read_fp_register_single (frame
, regno
+ 1, rare_buffer
+ 4);
6282 mips_print_fp_register (struct ui_file
*file
, struct frame_info
*frame
,
6284 { /* Do values for FP (float) regs. */
6285 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6286 gdb_byte
*raw_buffer
;
6287 std::string flt_str
, dbl_str
;
6289 const struct type
*flt_type
= builtin_type (gdbarch
)->builtin_float
;
6290 const struct type
*dbl_type
= builtin_type (gdbarch
)->builtin_double
;
6294 alloca (2 * register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
)));
6296 fprintf_filtered (file
, "%s:", gdbarch_register_name (gdbarch
, regnum
));
6297 fprintf_filtered (file
, "%*s",
6298 4 - (int) strlen (gdbarch_register_name (gdbarch
, regnum
)),
6301 if (register_size (gdbarch
, regnum
) == 4 || mips2_fp_compat (frame
))
6303 struct value_print_options opts
;
6305 /* 4-byte registers: Print hex and floating. Also print even
6306 numbered registers as doubles. */
6307 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6308 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6310 get_formatted_print_options (&opts
, 'x');
6311 print_scalar_formatted (raw_buffer
,
6312 builtin_type (gdbarch
)->builtin_uint32
,
6315 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6317 if ((regnum
- gdbarch_num_regs (gdbarch
)) % 2 == 0)
6319 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6320 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6322 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6327 struct value_print_options opts
;
6329 /* Eight byte registers: print each one as hex, float and double. */
6330 mips_read_fp_register_single (frame
, regnum
, raw_buffer
);
6331 flt_str
= target_float_to_string (raw_buffer
, flt_type
, "%-17.9g");
6333 mips_read_fp_register_double (frame
, regnum
, raw_buffer
);
6334 dbl_str
= target_float_to_string (raw_buffer
, dbl_type
, "%-24.17g");
6336 get_formatted_print_options (&opts
, 'x');
6337 print_scalar_formatted (raw_buffer
,
6338 builtin_type (gdbarch
)->builtin_uint64
,
6341 fprintf_filtered (file
, " flt: %s", flt_str
.c_str ());
6342 fprintf_filtered (file
, " dbl: %s", dbl_str
.c_str ());
6347 mips_print_register (struct ui_file
*file
, struct frame_info
*frame
,
6350 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6351 struct value_print_options opts
;
6354 if (mips_float_register_p (gdbarch
, regnum
))
6356 mips_print_fp_register (file
, frame
, regnum
);
6360 val
= get_frame_register_value (frame
, regnum
);
6362 fputs_filtered (gdbarch_register_name (gdbarch
, regnum
), file
);
6364 /* The problem with printing numeric register names (r26, etc.) is that
6365 the user can't use them on input. Probably the best solution is to
6366 fix it so that either the numeric or the funky (a2, etc.) names
6367 are accepted on input. */
6368 if (regnum
< MIPS_NUMREGS
)
6369 fprintf_filtered (file
, "(r%d): ", regnum
);
6371 fprintf_filtered (file
, ": ");
6373 get_formatted_print_options (&opts
, 'x');
6374 value_print_scalar_formatted (val
, &opts
, 0, file
);
6377 /* Print IEEE exception condition bits in FLAGS. */
6380 print_fpu_flags (struct ui_file
*file
, int flags
)
6382 if (flags
& (1 << 0))
6383 fputs_filtered (" inexact", file
);
6384 if (flags
& (1 << 1))
6385 fputs_filtered (" uflow", file
);
6386 if (flags
& (1 << 2))
6387 fputs_filtered (" oflow", file
);
6388 if (flags
& (1 << 3))
6389 fputs_filtered (" div0", file
);
6390 if (flags
& (1 << 4))
6391 fputs_filtered (" inval", file
);
6392 if (flags
& (1 << 5))
6393 fputs_filtered (" unimp", file
);
6394 fputc_filtered ('\n', file
);
6397 /* Print interesting information about the floating point processor
6398 (if present) or emulator. */
6401 mips_print_float_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6402 struct frame_info
*frame
, const char *args
)
6404 int fcsr
= mips_regnum (gdbarch
)->fp_control_status
;
6405 enum mips_fpu_type type
= MIPS_FPU_TYPE (gdbarch
);
6409 if (fcsr
== -1 || !read_frame_register_unsigned (frame
, fcsr
, &fcs
))
6410 type
= MIPS_FPU_NONE
;
6412 fprintf_filtered (file
, "fpu type: %s\n",
6413 type
== MIPS_FPU_DOUBLE
? "double-precision"
6414 : type
== MIPS_FPU_SINGLE
? "single-precision"
6417 if (type
== MIPS_FPU_NONE
)
6420 fprintf_filtered (file
, "reg size: %d bits\n",
6421 register_size (gdbarch
, mips_regnum (gdbarch
)->fp0
) * 8);
6423 fputs_filtered ("cond :", file
);
6424 if (fcs
& (1 << 23))
6425 fputs_filtered (" 0", file
);
6426 for (i
= 1; i
<= 7; i
++)
6427 if (fcs
& (1 << (24 + i
)))
6428 fprintf_filtered (file
, " %d", i
);
6429 fputc_filtered ('\n', file
);
6431 fputs_filtered ("cause :", file
);
6432 print_fpu_flags (file
, (fcs
>> 12) & 0x3f);
6433 fputs ("mask :", stdout
);
6434 print_fpu_flags (file
, (fcs
>> 7) & 0x1f);
6435 fputs ("flags :", stdout
);
6436 print_fpu_flags (file
, (fcs
>> 2) & 0x1f);
6438 fputs_filtered ("rounding: ", file
);
6441 case 0: fputs_filtered ("nearest\n", file
); break;
6442 case 1: fputs_filtered ("zero\n", file
); break;
6443 case 2: fputs_filtered ("+inf\n", file
); break;
6444 case 3: fputs_filtered ("-inf\n", file
); break;
6447 fputs_filtered ("flush :", file
);
6448 if (fcs
& (1 << 21))
6449 fputs_filtered (" nearest", file
);
6450 if (fcs
& (1 << 22))
6451 fputs_filtered (" override", file
);
6452 if (fcs
& (1 << 24))
6453 fputs_filtered (" zero", file
);
6454 if ((fcs
& (0xb << 21)) == 0)
6455 fputs_filtered (" no", file
);
6456 fputc_filtered ('\n', file
);
6458 fprintf_filtered (file
, "nan2008 : %s\n", fcs
& (1 << 18) ? "yes" : "no");
6459 fprintf_filtered (file
, "abs2008 : %s\n", fcs
& (1 << 19) ? "yes" : "no");
6460 fputc_filtered ('\n', file
);
6462 default_print_float_info (gdbarch
, file
, frame
, args
);
6465 /* Replacement for generic do_registers_info.
6466 Print regs in pretty columns. */
6469 print_fp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6472 fprintf_filtered (file
, " ");
6473 mips_print_fp_register (file
, frame
, regnum
);
6474 fprintf_filtered (file
, "\n");
6479 /* Print a row's worth of GP (int) registers, with name labels above. */
6482 print_gp_register_row (struct ui_file
*file
, struct frame_info
*frame
,
6485 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
6486 /* Do values for GP (int) regs. */
6487 const gdb_byte
*raw_buffer
;
6488 struct value
*value
;
6489 int ncols
= (mips_abi_regsize (gdbarch
) == 8 ? 4 : 8); /* display cols
6494 /* For GP registers, we print a separate row of names above the vals. */
6495 for (col
= 0, regnum
= start_regnum
;
6496 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6499 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6500 continue; /* unused register */
6501 if (mips_float_register_p (gdbarch
, regnum
))
6502 break; /* End the row: reached FP register. */
6503 /* Large registers are handled separately. */
6504 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6507 break; /* End the row before this register. */
6509 /* Print this register on a row by itself. */
6510 mips_print_register (file
, frame
, regnum
);
6511 fprintf_filtered (file
, "\n");
6515 fprintf_filtered (file
, " ");
6516 fprintf_filtered (file
,
6517 mips_abi_regsize (gdbarch
) == 8 ? "%17s" : "%9s",
6518 gdbarch_register_name (gdbarch
, regnum
));
6525 /* Print the R0 to R31 names. */
6526 if ((start_regnum
% gdbarch_num_regs (gdbarch
)) < MIPS_NUMREGS
)
6527 fprintf_filtered (file
, "\n R%-4d",
6528 start_regnum
% gdbarch_num_regs (gdbarch
));
6530 fprintf_filtered (file
, "\n ");
6532 /* Now print the values in hex, 4 or 8 to the row. */
6533 for (col
= 0, regnum
= start_regnum
;
6534 col
< ncols
&& regnum
< gdbarch_num_cooked_regs (gdbarch
);
6537 if (*gdbarch_register_name (gdbarch
, regnum
) == '\0')
6538 continue; /* unused register */
6539 if (mips_float_register_p (gdbarch
, regnum
))
6540 break; /* End row: reached FP register. */
6541 if (register_size (gdbarch
, regnum
) > mips_abi_regsize (gdbarch
))
6542 break; /* End row: large register. */
6544 /* OK: get the data in raw format. */
6545 value
= get_frame_register_value (frame
, regnum
);
6546 if (value_optimized_out (value
)
6547 || !value_entirely_available (value
))
6549 fprintf_filtered (file
, "%*s ",
6550 (int) mips_abi_regsize (gdbarch
) * 2,
6551 (mips_abi_regsize (gdbarch
) == 4 ? "<unavl>"
6552 : "<unavailable>"));
6556 raw_buffer
= value_contents_all (value
);
6557 /* pad small registers */
6559 byte
< (mips_abi_regsize (gdbarch
)
6560 - register_size (gdbarch
, regnum
)); byte
++)
6561 fprintf_filtered (file
, " ");
6562 /* Now print the register value in hex, endian order. */
6563 if (gdbarch_byte_order (gdbarch
) == BFD_ENDIAN_BIG
)
6565 register_size (gdbarch
, regnum
) - register_size (gdbarch
, regnum
);
6566 byte
< register_size (gdbarch
, regnum
); byte
++)
6567 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6569 for (byte
= register_size (gdbarch
, regnum
) - 1;
6571 fprintf_filtered (file
, "%02x", raw_buffer
[byte
]);
6572 fprintf_filtered (file
, " ");
6575 if (col
> 0) /* ie. if we actually printed anything... */
6576 fprintf_filtered (file
, "\n");
6581 /* MIPS_DO_REGISTERS_INFO(): called by "info register" command. */
6584 mips_print_registers_info (struct gdbarch
*gdbarch
, struct ui_file
*file
,
6585 struct frame_info
*frame
, int regnum
, int all
)
6587 if (regnum
!= -1) /* Do one specified register. */
6589 gdb_assert (regnum
>= gdbarch_num_regs (gdbarch
));
6590 if (*(gdbarch_register_name (gdbarch
, regnum
)) == '\0')
6591 error (_("Not a valid register for the current processor type"));
6593 mips_print_register (file
, frame
, regnum
);
6594 fprintf_filtered (file
, "\n");
6597 /* Do all (or most) registers. */
6599 regnum
= gdbarch_num_regs (gdbarch
);
6600 while (regnum
< gdbarch_num_cooked_regs (gdbarch
))
6602 if (mips_float_register_p (gdbarch
, regnum
))
6604 if (all
) /* True for "INFO ALL-REGISTERS" command. */
6605 regnum
= print_fp_register_row (file
, frame
, regnum
);
6607 regnum
+= MIPS_NUMREGS
; /* Skip floating point regs. */
6610 regnum
= print_gp_register_row (file
, frame
, regnum
);
6616 mips_single_step_through_delay (struct gdbarch
*gdbarch
,
6617 struct frame_info
*frame
)
6619 CORE_ADDR pc
= get_frame_pc (frame
);
6624 if ((mips_pc_is_mips (pc
)
6625 && !mips32_insn_at_pc_has_delay_slot (gdbarch
, pc
))
6626 || (mips_pc_is_micromips (gdbarch
, pc
)
6627 && !micromips_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0))
6628 || (mips_pc_is_mips16 (gdbarch
, pc
)
6629 && !mips16_insn_at_pc_has_delay_slot (gdbarch
, pc
, 0)))
6632 isa
= mips_pc_isa (gdbarch
, pc
);
6633 /* _has_delay_slot above will have validated the read. */
6634 insn
= mips_fetch_instruction (gdbarch
, isa
, pc
, NULL
);
6635 size
= mips_insn_size (isa
, insn
);
6637 const address_space
*aspace
= get_frame_address_space (frame
);
6639 return breakpoint_here_p (aspace
, pc
+ size
) != no_breakpoint_here
;
6642 /* To skip prologues, I use this predicate. Returns either PC itself
6643 if the code at PC does not look like a function prologue; otherwise
6644 returns an address that (if we're lucky) follows the prologue. If
6645 LENIENT, then we must skip everything which is involved in setting
6646 up the frame (it's OK to skip more, just so long as we don't skip
6647 anything which might clobber the registers which are being saved.
6648 We must skip more in the case where part of the prologue is in the
6649 delay slot of a non-prologue instruction). */
6652 mips_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6655 CORE_ADDR func_addr
;
6657 /* See if we can determine the end of the prologue via the symbol table.
6658 If so, then return either PC, or the PC after the prologue, whichever
6660 if (find_pc_partial_function (pc
, NULL
, &func_addr
, NULL
))
6662 CORE_ADDR post_prologue_pc
6663 = skip_prologue_using_sal (gdbarch
, func_addr
);
6664 if (post_prologue_pc
!= 0)
6665 return std::max (pc
, post_prologue_pc
);
6668 /* Can't determine prologue from the symbol table, need to examine
6671 /* Find an upper limit on the function prologue using the debug
6672 information. If the debug information could not be used to provide
6673 that bound, then use an arbitrary large number as the upper bound. */
6674 limit_pc
= skip_prologue_using_sal (gdbarch
, pc
);
6676 limit_pc
= pc
+ 100; /* Magic. */
6678 if (mips_pc_is_mips16 (gdbarch
, pc
))
6679 return mips16_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6680 else if (mips_pc_is_micromips (gdbarch
, pc
))
6681 return micromips_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6683 return mips32_scan_prologue (gdbarch
, pc
, limit_pc
, NULL
, NULL
);
6686 /* Implement the stack_frame_destroyed_p gdbarch method (32-bit version).
6687 This is a helper function for mips_stack_frame_destroyed_p. */
6690 mips32_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6692 CORE_ADDR func_addr
= 0, func_end
= 0;
6694 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6696 /* The MIPS epilogue is max. 12 bytes long. */
6697 CORE_ADDR addr
= func_end
- 12;
6699 if (addr
< func_addr
+ 4)
6700 addr
= func_addr
+ 4;
6704 for (; pc
< func_end
; pc
+= MIPS_INSN32_SIZE
)
6706 unsigned long high_word
;
6709 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
6710 high_word
= (inst
>> 16) & 0xffff;
6712 if (high_word
!= 0x27bd /* addiu $sp,$sp,offset */
6713 && high_word
!= 0x67bd /* daddiu $sp,$sp,offset */
6714 && inst
!= 0x03e00008 /* jr $ra */
6715 && inst
!= 0x00000000) /* nop */
6725 /* Implement the stack_frame_destroyed_p gdbarch method (microMIPS version).
6726 This is a helper function for mips_stack_frame_destroyed_p. */
6729 micromips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6731 CORE_ADDR func_addr
= 0;
6732 CORE_ADDR func_end
= 0;
6740 if (!find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6743 /* The microMIPS epilogue is max. 12 bytes long. */
6744 addr
= func_end
- 12;
6746 if (addr
< func_addr
+ 2)
6747 addr
= func_addr
+ 2;
6751 for (; pc
< func_end
; pc
+= loc
)
6754 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, NULL
);
6755 loc
+= MIPS_INSN16_SIZE
;
6756 switch (mips_insn_size (ISA_MICROMIPS
, insn
))
6758 /* 32-bit instructions. */
6759 case 2 * MIPS_INSN16_SIZE
:
6761 insn
|= mips_fetch_instruction (gdbarch
,
6762 ISA_MICROMIPS
, pc
+ loc
, NULL
);
6763 loc
+= MIPS_INSN16_SIZE
;
6764 switch (micromips_op (insn
>> 16))
6766 case 0xc: /* ADDIU: bits 001100 */
6767 case 0x17: /* DADDIU: bits 010111 */
6768 sreg
= b0s5_reg (insn
>> 16);
6769 dreg
= b5s5_reg (insn
>> 16);
6770 offset
= (b0s16_imm (insn
) ^ 0x8000) - 0x8000;
6771 if (sreg
== MIPS_SP_REGNUM
&& dreg
== MIPS_SP_REGNUM
6772 /* (D)ADDIU $sp, imm */
6782 /* 16-bit instructions. */
6783 case MIPS_INSN16_SIZE
:
6784 switch (micromips_op (insn
))
6786 case 0x3: /* MOVE: bits 000011 */
6787 sreg
= b0s5_reg (insn
);
6788 dreg
= b5s5_reg (insn
);
6789 if (sreg
== 0 && dreg
== 0)
6790 /* MOVE $zero, $zero aka NOP */
6794 case 0x11: /* POOL16C: bits 010001 */
6795 if (b5s5_op (insn
) == 0x18
6796 /* JRADDIUSP: bits 010011 11000 */
6797 || (b5s5_op (insn
) == 0xd
6798 /* JRC: bits 010011 01101 */
6799 && b0s5_reg (insn
) == MIPS_RA_REGNUM
))
6804 case 0x13: /* POOL16D: bits 010011 */
6805 offset
= micromips_decode_imm9 (b1s9_imm (insn
));
6806 if ((insn
& 0x1) == 0x1
6807 /* ADDIUSP: bits 010011 1 */
6821 /* Implement the stack_frame_destroyed_p gdbarch method (16-bit version).
6822 This is a helper function for mips_stack_frame_destroyed_p. */
6825 mips16_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6827 CORE_ADDR func_addr
= 0, func_end
= 0;
6829 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
6831 /* The MIPS epilogue is max. 12 bytes long. */
6832 CORE_ADDR addr
= func_end
- 12;
6834 if (addr
< func_addr
+ 4)
6835 addr
= func_addr
+ 4;
6839 for (; pc
< func_end
; pc
+= MIPS_INSN16_SIZE
)
6841 unsigned short inst
;
6843 inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, pc
, NULL
);
6845 if ((inst
& 0xf800) == 0xf000) /* extend */
6848 if (inst
!= 0x6300 /* addiu $sp,offset */
6849 && inst
!= 0xfb00 /* daddiu $sp,$sp,offset */
6850 && inst
!= 0xe820 /* jr $ra */
6851 && inst
!= 0xe8a0 /* jrc $ra */
6852 && inst
!= 0x6500) /* nop */
6862 /* Implement the stack_frame_destroyed_p gdbarch method.
6864 The epilogue is defined here as the area at the end of a function,
6865 after an instruction which destroys the function's stack frame. */
6868 mips_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
6870 if (mips_pc_is_mips16 (gdbarch
, pc
))
6871 return mips16_stack_frame_destroyed_p (gdbarch
, pc
);
6872 else if (mips_pc_is_micromips (gdbarch
, pc
))
6873 return micromips_stack_frame_destroyed_p (gdbarch
, pc
);
6875 return mips32_stack_frame_destroyed_p (gdbarch
, pc
);
6878 /* Commands to show/set the MIPS FPU type. */
6881 show_mipsfpu_command (const char *args
, int from_tty
)
6885 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
6888 ("The MIPS floating-point coprocessor is unknown "
6889 "because the current architecture is not MIPS.\n");
6893 switch (MIPS_FPU_TYPE (target_gdbarch ()))
6895 case MIPS_FPU_SINGLE
:
6896 fpu
= "single-precision";
6898 case MIPS_FPU_DOUBLE
:
6899 fpu
= "double-precision";
6902 fpu
= "absent (none)";
6905 internal_error (__FILE__
, __LINE__
, _("bad switch"));
6907 if (mips_fpu_type_auto
)
6908 printf_unfiltered ("The MIPS floating-point coprocessor "
6909 "is set automatically (currently %s)\n",
6913 ("The MIPS floating-point coprocessor is assumed to be %s\n", fpu
);
6918 set_mipsfpu_single_command (const char *args
, int from_tty
)
6920 struct gdbarch_info info
;
6921 gdbarch_info_init (&info
);
6922 mips_fpu_type
= MIPS_FPU_SINGLE
;
6923 mips_fpu_type_auto
= 0;
6924 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6925 instead of relying on globals. Doing that would let generic code
6926 handle the search for this specific architecture. */
6927 if (!gdbarch_update_p (info
))
6928 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6932 set_mipsfpu_double_command (const char *args
, int from_tty
)
6934 struct gdbarch_info info
;
6935 gdbarch_info_init (&info
);
6936 mips_fpu_type
= MIPS_FPU_DOUBLE
;
6937 mips_fpu_type_auto
= 0;
6938 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6939 instead of relying on globals. Doing that would let generic code
6940 handle the search for this specific architecture. */
6941 if (!gdbarch_update_p (info
))
6942 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6946 set_mipsfpu_none_command (const char *args
, int from_tty
)
6948 struct gdbarch_info info
;
6949 gdbarch_info_init (&info
);
6950 mips_fpu_type
= MIPS_FPU_NONE
;
6951 mips_fpu_type_auto
= 0;
6952 /* FIXME: cagney/2003-11-15: Should be setting a field in "info"
6953 instead of relying on globals. Doing that would let generic code
6954 handle the search for this specific architecture. */
6955 if (!gdbarch_update_p (info
))
6956 internal_error (__FILE__
, __LINE__
, _("set mipsfpu failed"));
6960 set_mipsfpu_auto_command (const char *args
, int from_tty
)
6962 mips_fpu_type_auto
= 1;
6965 /* Just like reinit_frame_cache, but with the right arguments to be
6966 callable as an sfunc. */
6969 reinit_frame_cache_sfunc (const char *args
, int from_tty
,
6970 struct cmd_list_element
*c
)
6972 reinit_frame_cache ();
6976 gdb_print_insn_mips (bfd_vma memaddr
, struct disassemble_info
*info
)
6978 gdb_disassembler
*di
6979 = static_cast<gdb_disassembler
*>(info
->application_data
);
6980 struct gdbarch
*gdbarch
= di
->arch ();
6982 /* FIXME: cagney/2003-06-26: Is this even necessary? The
6983 disassembler needs to be able to locally determine the ISA, and
6984 not rely on GDB. Otherwize the stand-alone 'objdump -d' will not
6986 if (mips_pc_is_mips16 (gdbarch
, memaddr
))
6987 info
->mach
= bfd_mach_mips16
;
6988 else if (mips_pc_is_micromips (gdbarch
, memaddr
))
6989 info
->mach
= bfd_mach_mips_micromips
;
6991 /* Round down the instruction address to the appropriate boundary. */
6992 memaddr
&= (info
->mach
== bfd_mach_mips16
6993 || info
->mach
== bfd_mach_mips_micromips
) ? ~1 : ~3;
6995 return default_print_insn (memaddr
, info
);
6998 /* Implement the breakpoint_kind_from_pc gdbarch method. */
7001 mips_breakpoint_kind_from_pc (struct gdbarch
*gdbarch
, CORE_ADDR
*pcptr
)
7003 CORE_ADDR pc
= *pcptr
;
7005 if (mips_pc_is_mips16 (gdbarch
, pc
))
7007 *pcptr
= unmake_compact_addr (pc
);
7008 return MIPS_BP_KIND_MIPS16
;
7010 else if (mips_pc_is_micromips (gdbarch
, pc
))
7015 *pcptr
= unmake_compact_addr (pc
);
7016 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, pc
, &status
);
7017 if (status
|| (mips_insn_size (ISA_MICROMIPS
, insn
) == 2))
7018 return MIPS_BP_KIND_MICROMIPS16
;
7020 return MIPS_BP_KIND_MICROMIPS32
;
7023 return MIPS_BP_KIND_MIPS32
;
7026 /* Implement the sw_breakpoint_from_kind gdbarch method. */
7028 static const gdb_byte
*
7029 mips_sw_breakpoint_from_kind (struct gdbarch
*gdbarch
, int kind
, int *size
)
7031 enum bfd_endian byte_order_for_code
= gdbarch_byte_order_for_code (gdbarch
);
7035 case MIPS_BP_KIND_MIPS16
:
7037 static gdb_byte mips16_big_breakpoint
[] = { 0xe8, 0xa5 };
7038 static gdb_byte mips16_little_breakpoint
[] = { 0xa5, 0xe8 };
7041 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7042 return mips16_big_breakpoint
;
7044 return mips16_little_breakpoint
;
7046 case MIPS_BP_KIND_MICROMIPS16
:
7048 static gdb_byte micromips16_big_breakpoint
[] = { 0x46, 0x85 };
7049 static gdb_byte micromips16_little_breakpoint
[] = { 0x85, 0x46 };
7053 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7054 return micromips16_big_breakpoint
;
7056 return micromips16_little_breakpoint
;
7058 case MIPS_BP_KIND_MICROMIPS32
:
7060 static gdb_byte micromips32_big_breakpoint
[] = { 0, 0x5, 0, 0x7 };
7061 static gdb_byte micromips32_little_breakpoint
[] = { 0x5, 0, 0x7, 0 };
7064 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7065 return micromips32_big_breakpoint
;
7067 return micromips32_little_breakpoint
;
7069 case MIPS_BP_KIND_MIPS32
:
7071 static gdb_byte big_breakpoint
[] = { 0, 0x5, 0, 0xd };
7072 static gdb_byte little_breakpoint
[] = { 0xd, 0, 0x5, 0 };
7075 if (byte_order_for_code
== BFD_ENDIAN_BIG
)
7076 return big_breakpoint
;
7078 return little_breakpoint
;
7081 gdb_assert_not_reached ("unexpected mips breakpoint kind");
7085 /* Return non-zero if the standard MIPS instruction INST has a branch
7086 delay slot (i.e. it is a jump or branch instruction). This function
7087 is based on mips32_next_pc. */
7090 mips32_instruction_has_delay_slot (struct gdbarch
*gdbarch
, ULONGEST inst
)
7096 op
= itype_op (inst
);
7097 if ((inst
& 0xe0000000) != 0)
7099 rs
= itype_rs (inst
);
7100 rt
= itype_rt (inst
);
7101 return (is_octeon_bbit_op (op
, gdbarch
)
7102 || op
>> 2 == 5 /* BEQL, BNEL, BLEZL, BGTZL: bits 0101xx */
7103 || op
== 29 /* JALX: bits 011101 */
7106 /* BC1F, BC1FL, BC1T, BC1TL: 010001 01000 */
7107 || (rs
== 9 && (rt
& 0x2) == 0)
7108 /* BC1ANY2F, BC1ANY2T: bits 010001 01001 */
7109 || (rs
== 10 && (rt
& 0x2) == 0))));
7110 /* BC1ANY4F, BC1ANY4T: bits 010001 01010 */
7113 switch (op
& 0x07) /* extract bits 28,27,26 */
7115 case 0: /* SPECIAL */
7116 op
= rtype_funct (inst
);
7117 return (op
== 8 /* JR */
7118 || op
== 9); /* JALR */
7119 break; /* end SPECIAL */
7120 case 1: /* REGIMM */
7121 rs
= itype_rs (inst
);
7122 rt
= itype_rt (inst
); /* branch condition */
7123 return ((rt
& 0xc) == 0
7124 /* BLTZ, BLTZL, BGEZ, BGEZL: bits 000xx */
7125 /* BLTZAL, BLTZALL, BGEZAL, BGEZALL: 100xx */
7126 || ((rt
& 0x1e) == 0x1c && rs
== 0));
7127 /* BPOSGE32, BPOSGE64: bits 1110x */
7128 break; /* end REGIMM */
7129 default: /* J, JAL, BEQ, BNE, BLEZ, BGTZ */
7135 /* Return non-zero if a standard MIPS instruction at ADDR has a branch
7136 delay slot (i.e. it is a jump or branch instruction). */
7139 mips32_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
7144 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, addr
, &status
);
7148 return mips32_instruction_has_delay_slot (gdbarch
, insn
);
7151 /* Return non-zero if the microMIPS instruction INSN, comprising the
7152 16-bit major opcode word in the high 16 bits and any second word
7153 in the low 16 bits, has a branch delay slot (i.e. it is a non-compact
7154 jump or branch instruction). The instruction must be 32-bit if
7155 MUSTBE32 is set or can be any instruction otherwise. */
7158 micromips_instruction_has_delay_slot (ULONGEST insn
, int mustbe32
)
7160 ULONGEST major
= insn
>> 16;
7162 switch (micromips_op (major
))
7164 /* 16-bit instructions. */
7165 case 0x33: /* B16: bits 110011 */
7166 case 0x2b: /* BNEZ16: bits 101011 */
7167 case 0x23: /* BEQZ16: bits 100011 */
7169 case 0x11: /* POOL16C: bits 010001 */
7171 && ((b5s5_op (major
) == 0xc
7172 /* JR16: bits 010001 01100 */
7173 || (b5s5_op (major
) & 0x1e) == 0xe)));
7174 /* JALR16, JALRS16: bits 010001 0111x */
7175 /* 32-bit instructions. */
7176 case 0x3d: /* JAL: bits 111101 */
7177 case 0x3c: /* JALX: bits 111100 */
7178 case 0x35: /* J: bits 110101 */
7179 case 0x2d: /* BNE: bits 101101 */
7180 case 0x25: /* BEQ: bits 100101 */
7181 case 0x1d: /* JALS: bits 011101 */
7183 case 0x10: /* POOL32I: bits 010000 */
7184 return ((b5s5_op (major
) & 0x1c) == 0x0
7185 /* BLTZ, BLTZAL, BGEZ, BGEZAL: 010000 000xx */
7186 || (b5s5_op (major
) & 0x1d) == 0x4
7187 /* BLEZ, BGTZ: bits 010000 001x0 */
7188 || (b5s5_op (major
) & 0x1d) == 0x11
7189 /* BLTZALS, BGEZALS: bits 010000 100x1 */
7190 || ((b5s5_op (major
) & 0x1e) == 0x14
7191 && (major
& 0x3) == 0x0)
7192 /* BC2F, BC2T: bits 010000 1010x xxx00 */
7193 || (b5s5_op (major
) & 0x1e) == 0x1a
7194 /* BPOSGE64, BPOSGE32: bits 010000 1101x */
7195 || ((b5s5_op (major
) & 0x1e) == 0x1c
7196 && (major
& 0x3) == 0x0)
7197 /* BC1F, BC1T: bits 010000 1110x xxx00 */
7198 || ((b5s5_op (major
) & 0x1c) == 0x1c
7199 && (major
& 0x3) == 0x1));
7200 /* BC1ANY*: bits 010000 111xx xxx01 */
7201 case 0x0: /* POOL32A: bits 000000 */
7202 return (b0s6_op (insn
) == 0x3c
7203 /* POOL32Axf: bits 000000 ... 111100 */
7204 && (b6s10_ext (insn
) & 0x2bf) == 0x3c);
7205 /* JALR, JALR.HB: 000000 000x111100 111100 */
7206 /* JALRS, JALRS.HB: 000000 010x111100 111100 */
7212 /* Return non-zero if a microMIPS instruction at ADDR has a branch delay
7213 slot (i.e. it is a non-compact jump instruction). The instruction
7214 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7217 micromips_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7218 CORE_ADDR addr
, int mustbe32
)
7224 insn
= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7227 size
= mips_insn_size (ISA_MICROMIPS
, insn
);
7229 if (size
== 2 * MIPS_INSN16_SIZE
)
7231 insn
|= mips_fetch_instruction (gdbarch
, ISA_MICROMIPS
, addr
, &status
);
7236 return micromips_instruction_has_delay_slot (insn
, mustbe32
);
7239 /* Return non-zero if the MIPS16 instruction INST, which must be
7240 a 32-bit instruction if MUSTBE32 is set or can be any instruction
7241 otherwise, has a branch delay slot (i.e. it is a non-compact jump
7242 instruction). This function is based on mips16_next_pc. */
7245 mips16_instruction_has_delay_slot (unsigned short inst
, int mustbe32
)
7247 if ((inst
& 0xf89f) == 0xe800) /* JR/JALR (16-bit instruction) */
7249 return (inst
& 0xf800) == 0x1800; /* JAL/JALX (32-bit instruction) */
7252 /* Return non-zero if a MIPS16 instruction at ADDR has a branch delay
7253 slot (i.e. it is a non-compact jump instruction). The instruction
7254 must be 32-bit if MUSTBE32 is set or can be any instruction otherwise. */
7257 mips16_insn_at_pc_has_delay_slot (struct gdbarch
*gdbarch
,
7258 CORE_ADDR addr
, int mustbe32
)
7260 unsigned short insn
;
7263 insn
= mips_fetch_instruction (gdbarch
, ISA_MIPS16
, addr
, &status
);
7267 return mips16_instruction_has_delay_slot (insn
, mustbe32
);
7270 /* Calculate the starting address of the MIPS memory segment BPADDR is in.
7271 This assumes KSSEG exists. */
7274 mips_segment_boundary (CORE_ADDR bpaddr
)
7276 CORE_ADDR mask
= CORE_ADDR_MAX
;
7279 if (sizeof (CORE_ADDR
) == 8)
7280 /* Get the topmost two bits of bpaddr in a 32-bit safe manner (avoid
7281 a compiler warning produced where CORE_ADDR is a 32-bit type even
7282 though in that case this is dead code). */
7283 switch (bpaddr
>> ((sizeof (CORE_ADDR
) << 3) - 2) & 3)
7286 if (bpaddr
== (bfd_signed_vma
) (int32_t) bpaddr
)
7287 segsize
= 29; /* 32-bit compatibility segment */
7289 segsize
= 62; /* xkseg */
7291 case 2: /* xkphys */
7294 default: /* xksseg (1), xkuseg/kuseg (0) */
7298 else if (bpaddr
& 0x80000000) /* kernel segment */
7301 segsize
= 31; /* user segment */
7303 return bpaddr
& mask
;
7306 /* Move the breakpoint at BPADDR out of any branch delay slot by shifting
7307 it backwards if necessary. Return the address of the new location. */
7310 mips_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
7312 CORE_ADDR prev_addr
;
7314 CORE_ADDR func_addr
;
7316 /* If a breakpoint is set on the instruction in a branch delay slot,
7317 GDB gets confused. When the breakpoint is hit, the PC isn't on
7318 the instruction in the branch delay slot, the PC will point to
7319 the branch instruction. Since the PC doesn't match any known
7320 breakpoints, GDB reports a trap exception.
7322 There are two possible fixes for this problem.
7324 1) When the breakpoint gets hit, see if the BD bit is set in the
7325 Cause register (which indicates the last exception occurred in a
7326 branch delay slot). If the BD bit is set, fix the PC to point to
7327 the instruction in the branch delay slot.
7329 2) When the user sets the breakpoint, don't allow him to set the
7330 breakpoint on the instruction in the branch delay slot. Instead
7331 move the breakpoint to the branch instruction (which will have
7334 The problem with the first solution is that if the user then
7335 single-steps the processor, the branch instruction will get
7336 skipped (since GDB thinks the PC is on the instruction in the
7339 So, we'll use the second solution. To do this we need to know if
7340 the instruction we're trying to set the breakpoint on is in the
7341 branch delay slot. */
7343 boundary
= mips_segment_boundary (bpaddr
);
7345 /* Make sure we don't scan back before the beginning of the current
7346 function, since we may fetch constant data or insns that look like
7347 a jump. Of course we might do that anyway if the compiler has
7348 moved constants inline. :-( */
7349 if (find_pc_partial_function (bpaddr
, NULL
, &func_addr
, NULL
)
7350 && func_addr
> boundary
&& func_addr
<= bpaddr
)
7351 boundary
= func_addr
;
7353 if (mips_pc_is_mips (bpaddr
))
7355 if (bpaddr
== boundary
)
7358 /* If the previous instruction has a branch delay slot, we have
7359 to move the breakpoint to the branch instruction. */
7360 prev_addr
= bpaddr
- 4;
7361 if (mips32_insn_at_pc_has_delay_slot (gdbarch
, prev_addr
))
7366 int (*insn_at_pc_has_delay_slot
) (struct gdbarch
*, CORE_ADDR
, int);
7367 CORE_ADDR addr
, jmpaddr
;
7370 boundary
= unmake_compact_addr (boundary
);
7372 /* The only MIPS16 instructions with delay slots are JAL, JALX,
7373 JALR and JR. An absolute JAL/JALX is always 4 bytes long,
7374 so try for that first, then try the 2 byte JALR/JR.
7375 The microMIPS ASE has a whole range of jumps and branches
7376 with delay slots, some of which take 4 bytes and some take
7377 2 bytes, so the idea is the same.
7378 FIXME: We have to assume that bpaddr is not the second half
7379 of an extended instruction. */
7380 insn_at_pc_has_delay_slot
= (mips_pc_is_micromips (gdbarch
, bpaddr
)
7381 ? micromips_insn_at_pc_has_delay_slot
7382 : mips16_insn_at_pc_has_delay_slot
);
7386 for (i
= 1; i
< 4; i
++)
7388 if (unmake_compact_addr (addr
) == boundary
)
7390 addr
-= MIPS_INSN16_SIZE
;
7391 if (i
== 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 0))
7392 /* Looks like a JR/JALR at [target-1], but it could be
7393 the second word of a previous JAL/JALX, so record it
7394 and check back one more. */
7396 else if (i
> 1 && insn_at_pc_has_delay_slot (gdbarch
, addr
, 1))
7399 /* Looks like a JAL/JALX at [target-2], but it could also
7400 be the second word of a previous JAL/JALX, record it,
7401 and check back one more. */
7404 /* Looks like a JAL/JALX at [target-3], so any previously
7405 recorded JAL/JALX or JR/JALR must be wrong, because:
7408 -2: JAL-ext (can't be JAL/JALX)
7409 -1: bdslot (can't be JR/JALR)
7412 Of course it could be another JAL-ext which looks
7413 like a JAL, but in that case we'd have broken out
7414 of this loop at [target-2]:
7418 -2: bdslot (can't be jmp)
7425 /* Not a jump instruction: if we're at [target-1] this
7426 could be the second word of a JAL/JALX, so continue;
7427 otherwise we're done. */
7440 /* Return non-zero if SUFFIX is one of the numeric suffixes used for MIPS16
7441 call stubs, one of 1, 2, 5, 6, 9, 10, or, if ZERO is non-zero, also 0. */
7444 mips_is_stub_suffix (const char *suffix
, int zero
)
7449 return zero
&& suffix
[1] == '\0';
7451 return suffix
[1] == '\0' || (suffix
[1] == '0' && suffix
[2] == '\0');
7456 return suffix
[1] == '\0';
7462 /* Return non-zero if MODE is one of the mode infixes used for MIPS16
7463 call stubs, one of sf, df, sc, or dc. */
7466 mips_is_stub_mode (const char *mode
)
7468 return ((mode
[0] == 's' || mode
[0] == 'd')
7469 && (mode
[1] == 'f' || mode
[1] == 'c'));
7472 /* Code at PC is a compiler-generated stub. Such a stub for a function
7473 bar might have a name like __fn_stub_bar, and might look like this:
7480 followed by (or interspersed with):
7487 addiu $25, $25, %lo(bar)
7490 ($1 may be used in old code; for robustness we accept any register)
7493 lui $28, %hi(_gp_disp)
7494 addiu $28, $28, %lo(_gp_disp)
7497 addiu $25, $25, %lo(bar)
7500 In the case of a __call_stub_bar stub, the sequence to set up
7501 arguments might look like this:
7508 followed by (or interspersed with) one of the jump sequences above.
7510 In the case of a __call_stub_fp_bar stub, JAL or JALR is used instead
7511 of J or JR, respectively, followed by:
7517 We are at the beginning of the stub here, and scan down and extract
7518 the target address from the jump immediate instruction or, if a jump
7519 register instruction is used, from the register referred. Return
7520 the value of PC calculated or 0 if inconclusive.
7522 The limit on the search is arbitrarily set to 20 instructions. FIXME. */
7525 mips_get_mips16_fn_stub_pc (struct frame_info
*frame
, CORE_ADDR pc
)
7527 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7528 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7529 int addrreg
= MIPS_ZERO_REGNUM
;
7530 CORE_ADDR start_pc
= pc
;
7531 CORE_ADDR target_pc
= 0;
7538 status
== 0 && target_pc
== 0 && i
< 20;
7539 i
++, pc
+= MIPS_INSN32_SIZE
)
7541 ULONGEST inst
= mips_fetch_instruction (gdbarch
, ISA_MIPS
, pc
, NULL
);
7547 switch (itype_op (inst
))
7549 case 0: /* SPECIAL */
7550 switch (rtype_funct (inst
))
7554 rs
= rtype_rs (inst
);
7555 if (rs
== MIPS_GP_REGNUM
)
7556 target_pc
= gp
; /* Hmm... */
7557 else if (rs
== addrreg
)
7561 case 0x21: /* ADDU */
7562 rt
= rtype_rt (inst
);
7563 rs
= rtype_rs (inst
);
7564 rd
= rtype_rd (inst
);
7565 if (rd
== MIPS_GP_REGNUM
7566 && ((rs
== MIPS_GP_REGNUM
&& rt
== MIPS_T9_REGNUM
)
7567 || (rs
== MIPS_T9_REGNUM
&& rt
== MIPS_GP_REGNUM
)))
7575 target_pc
= jtype_target (inst
) << 2;
7576 target_pc
+= ((pc
+ 4) & ~(CORE_ADDR
) 0x0fffffff);
7580 rt
= itype_rt (inst
);
7581 rs
= itype_rs (inst
);
7584 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7585 if (rt
== MIPS_GP_REGNUM
)
7587 else if (rt
== addrreg
)
7593 rt
= itype_rt (inst
);
7594 imm
= ((itype_immediate (inst
) ^ 0x8000) - 0x8000) << 16;
7595 if (rt
== MIPS_GP_REGNUM
)
7597 else if (rt
!= MIPS_ZERO_REGNUM
)
7605 rt
= itype_rt (inst
);
7606 rs
= itype_rs (inst
);
7607 imm
= (itype_immediate (inst
) ^ 0x8000) - 0x8000;
7608 if (gp
!= 0 && rs
== MIPS_GP_REGNUM
)
7612 memset (buf
, 0, sizeof (buf
));
7613 status
= target_read_memory (gp
+ imm
, buf
, sizeof (buf
));
7615 addr
= extract_signed_integer (buf
, sizeof (buf
), byte_order
);
7624 /* If PC is in a MIPS16 call or return stub, return the address of the
7625 target PC, which is either the callee or the caller. There are several
7626 cases which must be handled:
7628 * If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7629 and the target PC is in $31 ($ra).
7630 * If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7631 and the target PC is in $2.
7632 * If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7633 i.e. before the JALR instruction, this is effectively a call stub
7634 and the target PC is in $2. Otherwise this is effectively
7635 a return stub and the target PC is in $18.
7636 * If the PC is at the start of __call_stub_fp_*, i.e. before the
7637 JAL or JALR instruction, this is effectively a call stub and the
7638 target PC is buried in the instruction stream. Otherwise this
7639 is effectively a return stub and the target PC is in $18.
7640 * If the PC is in __call_stub_* or in __fn_stub_*, this is a call
7641 stub and the target PC is buried in the instruction stream.
7643 See the source code for the stubs in gcc/config/mips/mips16.S, or the
7644 stub builder in gcc/config/mips/mips.c (mips16_build_call_stub) for the
7648 mips_skip_mips16_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7650 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7651 CORE_ADDR start_addr
;
7655 /* Find the starting address and name of the function containing the PC. */
7656 if (find_pc_partial_function (pc
, &name
, &start_addr
, NULL
) == 0)
7659 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub
7660 and the target PC is in $31 ($ra). */
7661 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7662 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7663 && mips_is_stub_mode (name
+ prefixlen
)
7664 && name
[prefixlen
+ 2] == '\0')
7665 return get_frame_register_signed
7666 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_RA_REGNUM
);
7668 /* If the PC is in __mips16_call_stub_*, this is one of the call
7669 call/return stubs. */
7670 prefixlen
= strlen (mips_str_mips16_call_stub
);
7671 if (strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0)
7673 /* If the PC is in __mips16_call_stub_{1..10}, this is a call stub
7674 and the target PC is in $2. */
7675 if (mips_is_stub_suffix (name
+ prefixlen
, 0))
7676 return get_frame_register_signed
7677 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7679 /* If the PC at the start of __mips16_call_stub_{s,d}{f,c}_{0..10},
7680 i.e. before the JALR instruction, this is effectively a call stub
7681 and the target PC is in $2. Otherwise this is effectively
7682 a return stub and the target PC is in $18. */
7683 else if (mips_is_stub_mode (name
+ prefixlen
)
7684 && name
[prefixlen
+ 2] == '_'
7685 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 0))
7687 if (pc
== start_addr
)
7688 /* This is the 'call' part of a call stub. The return
7689 address is in $2. */
7690 return get_frame_register_signed
7691 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_V0_REGNUM
);
7693 /* This is the 'return' part of a call stub. The return
7694 address is in $18. */
7695 return get_frame_register_signed
7696 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7699 return 0; /* Not a stub. */
7702 /* If the PC is in __call_stub_* or __fn_stub*, this is one of the
7703 compiler-generated call or call/return stubs. */
7704 if (startswith (name
, mips_str_fn_stub
)
7705 || startswith (name
, mips_str_call_stub
))
7707 if (pc
== start_addr
)
7708 /* This is the 'call' part of a call stub. Call this helper
7709 to scan through this code for interesting instructions
7710 and determine the final PC. */
7711 return mips_get_mips16_fn_stub_pc (frame
, pc
);
7713 /* This is the 'return' part of a call stub. The return address
7715 return get_frame_register_signed
7716 (frame
, gdbarch_num_regs (gdbarch
) + MIPS_S2_REGNUM
);
7719 return 0; /* Not a stub. */
7722 /* Return non-zero if the PC is inside a return thunk (aka stub or trampoline).
7723 This implements the IN_SOLIB_RETURN_TRAMPOLINE macro. */
7726 mips_in_return_stub (struct gdbarch
*gdbarch
, CORE_ADDR pc
, const char *name
)
7728 CORE_ADDR start_addr
;
7731 /* Find the starting address of the function containing the PC. */
7732 if (find_pc_partial_function (pc
, NULL
, &start_addr
, NULL
) == 0)
7735 /* If the PC is in __mips16_call_stub_{s,d}{f,c}_{0..10} but not at
7736 the start, i.e. after the JALR instruction, this is effectively
7738 prefixlen
= strlen (mips_str_mips16_call_stub
);
7739 if (pc
!= start_addr
7740 && strncmp (name
, mips_str_mips16_call_stub
, prefixlen
) == 0
7741 && mips_is_stub_mode (name
+ prefixlen
)
7742 && name
[prefixlen
+ 2] == '_'
7743 && mips_is_stub_suffix (name
+ prefixlen
+ 3, 1))
7746 /* If the PC is in __call_stub_fp_* but not at the start, i.e. after
7747 the JAL or JALR instruction, this is effectively a return stub. */
7748 prefixlen
= strlen (mips_str_call_fp_stub
);
7749 if (pc
!= start_addr
7750 && strncmp (name
, mips_str_call_fp_stub
, prefixlen
) == 0)
7753 /* Consume the .pic. prefix of any PIC stub, this function must return
7754 true when the PC is in a PIC stub of a __mips16_ret_{d,s}{f,c} stub
7755 or the call stub path will trigger in handle_inferior_event causing
7757 prefixlen
= strlen (mips_str_pic
);
7758 if (strncmp (name
, mips_str_pic
, prefixlen
) == 0)
7761 /* If the PC is in __mips16_ret_{d,s}{f,c}, this is a return stub. */
7762 prefixlen
= strlen (mips_str_mips16_ret_stub
);
7763 if (strncmp (name
, mips_str_mips16_ret_stub
, prefixlen
) == 0
7764 && mips_is_stub_mode (name
+ prefixlen
)
7765 && name
[prefixlen
+ 2] == '\0')
7768 return 0; /* Not a stub. */
7771 /* If the current PC is the start of a non-PIC-to-PIC stub, return the
7772 PC of the stub target. The stub just loads $t9 and jumps to it,
7773 so that $t9 has the correct value at function entry. */
7776 mips_skip_pic_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7778 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
7779 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7780 struct bound_minimal_symbol msym
;
7782 gdb_byte stub_code
[16];
7783 int32_t stub_words
[4];
7785 /* The stub for foo is named ".pic.foo", and is either two
7786 instructions inserted before foo or a three instruction sequence
7787 which jumps to foo. */
7788 msym
= lookup_minimal_symbol_by_pc (pc
);
7789 if (msym
.minsym
== NULL
7790 || BMSYMBOL_VALUE_ADDRESS (msym
) != pc
7791 || msym
.minsym
->linkage_name () == NULL
7792 || !startswith (msym
.minsym
->linkage_name (), ".pic."))
7795 /* A two-instruction header. */
7796 if (MSYMBOL_SIZE (msym
.minsym
) == 8)
7799 /* A three-instruction (plus delay slot) trampoline. */
7800 if (MSYMBOL_SIZE (msym
.minsym
) == 16)
7802 if (target_read_memory (pc
, stub_code
, 16) != 0)
7804 for (i
= 0; i
< 4; i
++)
7805 stub_words
[i
] = extract_unsigned_integer (stub_code
+ i
* 4,
7808 /* A stub contains these instructions:
7811 addiu t9, t9, %lo(target)
7814 This works even for N64, since stubs are only generated with
7816 if ((stub_words
[0] & 0xffff0000U
) == 0x3c190000
7817 && (stub_words
[1] & 0xfc000000U
) == 0x08000000
7818 && (stub_words
[2] & 0xffff0000U
) == 0x27390000
7819 && stub_words
[3] == 0x00000000)
7820 return ((((stub_words
[0] & 0x0000ffff) << 16)
7821 + (stub_words
[2] & 0x0000ffff)) ^ 0x8000) - 0x8000;
7824 /* Not a recognized stub. */
7829 mips_skip_trampoline_code (struct frame_info
*frame
, CORE_ADDR pc
)
7831 CORE_ADDR requested_pc
= pc
;
7832 CORE_ADDR target_pc
;
7839 new_pc
= mips_skip_mips16_trampoline_code (frame
, pc
);
7843 new_pc
= find_solib_trampoline_target (frame
, pc
);
7847 new_pc
= mips_skip_pic_trampoline_code (frame
, pc
);
7851 while (pc
!= target_pc
);
7853 return pc
!= requested_pc
? pc
: 0;
7856 /* Convert a dbx stab register number (from `r' declaration) to a GDB
7857 [1 * gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7860 mips_stab_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7863 if (num
>= 0 && num
< 32)
7865 else if (num
>= 38 && num
< 70)
7866 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 38;
7868 regnum
= mips_regnum (gdbarch
)->hi
;
7870 regnum
= mips_regnum (gdbarch
)->lo
;
7871 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 72 && num
< 78)
7872 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 72;
7875 return gdbarch_num_regs (gdbarch
) + regnum
;
7879 /* Convert a dwarf, dwarf2, or ecoff register number to a GDB [1 *
7880 gdbarch_num_regs .. 2 * gdbarch_num_regs) REGNUM. */
7883 mips_dwarf_dwarf2_ecoff_reg_to_regnum (struct gdbarch
*gdbarch
, int num
)
7886 if (num
>= 0 && num
< 32)
7888 else if (num
>= 32 && num
< 64)
7889 regnum
= num
+ mips_regnum (gdbarch
)->fp0
- 32;
7891 regnum
= mips_regnum (gdbarch
)->hi
;
7893 regnum
= mips_regnum (gdbarch
)->lo
;
7894 else if (mips_regnum (gdbarch
)->dspacc
!= -1 && num
>= 66 && num
< 72)
7895 regnum
= num
+ mips_regnum (gdbarch
)->dspacc
- 66;
7898 return gdbarch_num_regs (gdbarch
) + regnum
;
7902 mips_register_sim_regno (struct gdbarch
*gdbarch
, int regnum
)
7904 /* Only makes sense to supply raw registers. */
7905 gdb_assert (regnum
>= 0 && regnum
< gdbarch_num_regs (gdbarch
));
7906 /* FIXME: cagney/2002-05-13: Need to look at the pseudo register to
7907 decide if it is valid. Should instead define a standard sim/gdb
7908 register numbering scheme. */
7909 if (gdbarch_register_name (gdbarch
,
7910 gdbarch_num_regs (gdbarch
) + regnum
) != NULL
7911 && gdbarch_register_name (gdbarch
,
7912 gdbarch_num_regs (gdbarch
)
7913 + regnum
)[0] != '\0')
7916 return LEGACY_SIM_REGNO_IGNORE
;
7920 /* Convert an integer into an address. Extracting the value signed
7921 guarantees a correctly sign extended address. */
7924 mips_integer_to_address (struct gdbarch
*gdbarch
,
7925 struct type
*type
, const gdb_byte
*buf
)
7927 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
7928 return extract_signed_integer (buf
, TYPE_LENGTH (type
), byte_order
);
7931 /* Dummy virtual frame pointer method. This is no more or less accurate
7932 than most other architectures; we just need to be explicit about it,
7933 because the pseudo-register gdbarch_sp_regnum will otherwise lead to
7934 an assertion failure. */
7937 mips_virtual_frame_pointer (struct gdbarch
*gdbarch
,
7938 CORE_ADDR pc
, int *reg
, LONGEST
*offset
)
7940 *reg
= MIPS_SP_REGNUM
;
7945 mips_find_abi_section (bfd
*abfd
, asection
*sect
, void *obj
)
7947 enum mips_abi
*abip
= (enum mips_abi
*) obj
;
7948 const char *name
= bfd_section_name (sect
);
7950 if (*abip
!= MIPS_ABI_UNKNOWN
)
7953 if (!startswith (name
, ".mdebug."))
7956 if (strcmp (name
, ".mdebug.abi32") == 0)
7957 *abip
= MIPS_ABI_O32
;
7958 else if (strcmp (name
, ".mdebug.abiN32") == 0)
7959 *abip
= MIPS_ABI_N32
;
7960 else if (strcmp (name
, ".mdebug.abi64") == 0)
7961 *abip
= MIPS_ABI_N64
;
7962 else if (strcmp (name
, ".mdebug.abiO64") == 0)
7963 *abip
= MIPS_ABI_O64
;
7964 else if (strcmp (name
, ".mdebug.eabi32") == 0)
7965 *abip
= MIPS_ABI_EABI32
;
7966 else if (strcmp (name
, ".mdebug.eabi64") == 0)
7967 *abip
= MIPS_ABI_EABI64
;
7969 warning (_("unsupported ABI %s."), name
+ 8);
7973 mips_find_long_section (bfd
*abfd
, asection
*sect
, void *obj
)
7975 int *lbp
= (int *) obj
;
7976 const char *name
= bfd_section_name (sect
);
7978 if (startswith (name
, ".gcc_compiled_long32"))
7980 else if (startswith (name
, ".gcc_compiled_long64"))
7982 else if (startswith (name
, ".gcc_compiled_long"))
7983 warning (_("unrecognized .gcc_compiled_longXX"));
7986 static enum mips_abi
7987 global_mips_abi (void)
7991 for (i
= 0; mips_abi_strings
[i
] != NULL
; i
++)
7992 if (mips_abi_strings
[i
] == mips_abi_string
)
7993 return (enum mips_abi
) i
;
7995 internal_error (__FILE__
, __LINE__
, _("unknown ABI string"));
7998 /* Return the default compressed instruction set, either of MIPS16
7999 or microMIPS, selected when none could have been determined from
8000 the ELF header of the binary being executed (or no binary has been
8003 static enum mips_isa
8004 global_mips_compression (void)
8008 for (i
= 0; mips_compression_strings
[i
] != NULL
; i
++)
8009 if (mips_compression_strings
[i
] == mips_compression_string
)
8010 return (enum mips_isa
) i
;
8012 internal_error (__FILE__
, __LINE__
, _("unknown compressed ISA string"));
8016 mips_register_g_packet_guesses (struct gdbarch
*gdbarch
)
8018 /* If the size matches the set of 32-bit or 64-bit integer registers,
8019 assume that's what we've got. */
8020 register_remote_g_packet_guess (gdbarch
, 38 * 4, mips_tdesc_gp32
);
8021 register_remote_g_packet_guess (gdbarch
, 38 * 8, mips_tdesc_gp64
);
8023 /* If the size matches the full set of registers GDB traditionally
8024 knows about, including floating point, for either 32-bit or
8025 64-bit, assume that's what we've got. */
8026 register_remote_g_packet_guess (gdbarch
, 90 * 4, mips_tdesc_gp32
);
8027 register_remote_g_packet_guess (gdbarch
, 90 * 8, mips_tdesc_gp64
);
8029 /* Otherwise we don't have a useful guess. */
8032 static struct value
*
8033 value_of_mips_user_reg (struct frame_info
*frame
, const void *baton
)
8035 const int *reg_p
= (const int *) baton
;
8036 return value_of_register (*reg_p
, frame
);
8039 static struct gdbarch
*
8040 mips_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8042 struct gdbarch
*gdbarch
;
8043 struct gdbarch_tdep
*tdep
;
8045 enum mips_abi mips_abi
, found_abi
, wanted_abi
;
8047 enum mips_fpu_type fpu_type
;
8048 tdesc_arch_data_up tdesc_data
;
8049 int elf_fpu_type
= Val_GNU_MIPS_ABI_FP_ANY
;
8050 const char * const *reg_names
;
8051 struct mips_regnum mips_regnum
, *regnum
;
8052 enum mips_isa mips_isa
;
8056 /* First of all, extract the elf_flags, if available. */
8057 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8058 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
8059 else if (arches
!= NULL
)
8060 elf_flags
= gdbarch_tdep (arches
->gdbarch
)->elf_flags
;
8064 fprintf_unfiltered (gdb_stdlog
,
8065 "mips_gdbarch_init: elf_flags = 0x%08x\n", elf_flags
);
8067 /* Check ELF_FLAGS to see if it specifies the ABI being used. */
8068 switch ((elf_flags
& EF_MIPS_ABI
))
8070 case E_MIPS_ABI_O32
:
8071 found_abi
= MIPS_ABI_O32
;
8073 case E_MIPS_ABI_O64
:
8074 found_abi
= MIPS_ABI_O64
;
8076 case E_MIPS_ABI_EABI32
:
8077 found_abi
= MIPS_ABI_EABI32
;
8079 case E_MIPS_ABI_EABI64
:
8080 found_abi
= MIPS_ABI_EABI64
;
8083 if ((elf_flags
& EF_MIPS_ABI2
))
8084 found_abi
= MIPS_ABI_N32
;
8086 found_abi
= MIPS_ABI_UNKNOWN
;
8090 /* GCC creates a pseudo-section whose name describes the ABI. */
8091 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
!= NULL
)
8092 bfd_map_over_sections (info
.abfd
, mips_find_abi_section
, &found_abi
);
8094 /* If we have no useful BFD information, use the ABI from the last
8095 MIPS architecture (if there is one). */
8096 if (found_abi
== MIPS_ABI_UNKNOWN
&& info
.abfd
== NULL
&& arches
!= NULL
)
8097 found_abi
= gdbarch_tdep (arches
->gdbarch
)->found_abi
;
8099 /* Try the architecture for any hint of the correct ABI. */
8100 if (found_abi
== MIPS_ABI_UNKNOWN
8101 && info
.bfd_arch_info
!= NULL
8102 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8104 switch (info
.bfd_arch_info
->mach
)
8106 case bfd_mach_mips3900
:
8107 found_abi
= MIPS_ABI_EABI32
;
8109 case bfd_mach_mips4100
:
8110 case bfd_mach_mips5000
:
8111 found_abi
= MIPS_ABI_EABI64
;
8113 case bfd_mach_mips8000
:
8114 case bfd_mach_mips10000
:
8115 /* On Irix, ELF64 executables use the N64 ABI. The
8116 pseudo-sections which describe the ABI aren't present
8117 on IRIX. (Even for executables created by gcc.) */
8118 if (info
.abfd
!= NULL
8119 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8120 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8121 found_abi
= MIPS_ABI_N64
;
8123 found_abi
= MIPS_ABI_N32
;
8128 /* Default 64-bit objects to N64 instead of O32. */
8129 if (found_abi
== MIPS_ABI_UNKNOWN
8130 && info
.abfd
!= NULL
8131 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
8132 && elf_elfheader (info
.abfd
)->e_ident
[EI_CLASS
] == ELFCLASS64
)
8133 found_abi
= MIPS_ABI_N64
;
8136 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: found_abi = %d\n",
8139 /* What has the user specified from the command line? */
8140 wanted_abi
= global_mips_abi ();
8142 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: wanted_abi = %d\n",
8145 /* Now that we have found what the ABI for this binary would be,
8146 check whether the user is overriding it. */
8147 if (wanted_abi
!= MIPS_ABI_UNKNOWN
)
8148 mips_abi
= wanted_abi
;
8149 else if (found_abi
!= MIPS_ABI_UNKNOWN
)
8150 mips_abi
= found_abi
;
8152 mips_abi
= MIPS_ABI_O32
;
8154 fprintf_unfiltered (gdb_stdlog
, "mips_gdbarch_init: mips_abi = %d\n",
8157 /* Make sure we don't use a 32-bit architecture with a 64-bit ABI. */
8158 if (mips_abi
!= MIPS_ABI_EABI32
8159 && mips_abi
!= MIPS_ABI_O32
8160 && info
.bfd_arch_info
!= NULL
8161 && info
.bfd_arch_info
->arch
== bfd_arch_mips
8162 && info
.bfd_arch_info
->bits_per_word
< 64)
8163 info
.bfd_arch_info
= bfd_lookup_arch (bfd_arch_mips
, bfd_mach_mips4000
);
8165 /* Determine the default compressed ISA. */
8166 if ((elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) != 0
8167 && (elf_flags
& EF_MIPS_ARCH_ASE_M16
) == 0)
8168 mips_isa
= ISA_MICROMIPS
;
8169 else if ((elf_flags
& EF_MIPS_ARCH_ASE_M16
) != 0
8170 && (elf_flags
& EF_MIPS_ARCH_ASE_MICROMIPS
) == 0)
8171 mips_isa
= ISA_MIPS16
;
8173 mips_isa
= global_mips_compression ();
8174 mips_compression_string
= mips_compression_strings
[mips_isa
];
8176 /* Also used when doing an architecture lookup. */
8178 fprintf_unfiltered (gdb_stdlog
,
8179 "mips_gdbarch_init: "
8180 "mips64_transfers_32bit_regs_p = %d\n",
8181 mips64_transfers_32bit_regs_p
);
8183 /* Determine the MIPS FPU type. */
8186 && bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
8187 elf_fpu_type
= bfd_elf_get_obj_attr_int (info
.abfd
, OBJ_ATTR_GNU
,
8188 Tag_GNU_MIPS_ABI_FP
);
8189 #endif /* HAVE_ELF */
8191 if (!mips_fpu_type_auto
)
8192 fpu_type
= mips_fpu_type
;
8193 else if (elf_fpu_type
!= Val_GNU_MIPS_ABI_FP_ANY
)
8195 switch (elf_fpu_type
)
8197 case Val_GNU_MIPS_ABI_FP_DOUBLE
:
8198 fpu_type
= MIPS_FPU_DOUBLE
;
8200 case Val_GNU_MIPS_ABI_FP_SINGLE
:
8201 fpu_type
= MIPS_FPU_SINGLE
;
8203 case Val_GNU_MIPS_ABI_FP_SOFT
:
8205 /* Soft float or unknown. */
8206 fpu_type
= MIPS_FPU_NONE
;
8210 else if (info
.bfd_arch_info
!= NULL
8211 && info
.bfd_arch_info
->arch
== bfd_arch_mips
)
8212 switch (info
.bfd_arch_info
->mach
)
8214 case bfd_mach_mips3900
:
8215 case bfd_mach_mips4100
:
8216 case bfd_mach_mips4111
:
8217 case bfd_mach_mips4120
:
8218 fpu_type
= MIPS_FPU_NONE
;
8220 case bfd_mach_mips4650
:
8221 fpu_type
= MIPS_FPU_SINGLE
;
8224 fpu_type
= MIPS_FPU_DOUBLE
;
8227 else if (arches
!= NULL
)
8228 fpu_type
= MIPS_FPU_TYPE (arches
->gdbarch
);
8230 fpu_type
= MIPS_FPU_DOUBLE
;
8232 fprintf_unfiltered (gdb_stdlog
,
8233 "mips_gdbarch_init: fpu_type = %d\n", fpu_type
);
8235 /* Check for blatant incompatibilities. */
8237 /* If we have only 32-bit registers, then we can't debug a 64-bit
8239 if (info
.target_desc
8240 && tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
8241 && mips_abi
!= MIPS_ABI_EABI32
8242 && mips_abi
!= MIPS_ABI_O32
)
8245 /* Fill in the OS dependent register numbers and names. */
8246 if (info
.osabi
== GDB_OSABI_LINUX
)
8248 mips_regnum
.fp0
= 38;
8249 mips_regnum
.pc
= 37;
8250 mips_regnum
.cause
= 36;
8251 mips_regnum
.badvaddr
= 35;
8252 mips_regnum
.hi
= 34;
8253 mips_regnum
.lo
= 33;
8254 mips_regnum
.fp_control_status
= 70;
8255 mips_regnum
.fp_implementation_revision
= 71;
8256 mips_regnum
.dspacc
= -1;
8257 mips_regnum
.dspctl
= -1;
8261 reg_names
= mips_linux_reg_names
;
8265 mips_regnum
.lo
= MIPS_EMBED_LO_REGNUM
;
8266 mips_regnum
.hi
= MIPS_EMBED_HI_REGNUM
;
8267 mips_regnum
.badvaddr
= MIPS_EMBED_BADVADDR_REGNUM
;
8268 mips_regnum
.cause
= MIPS_EMBED_CAUSE_REGNUM
;
8269 mips_regnum
.pc
= MIPS_EMBED_PC_REGNUM
;
8270 mips_regnum
.fp0
= MIPS_EMBED_FP0_REGNUM
;
8271 mips_regnum
.fp_control_status
= 70;
8272 mips_regnum
.fp_implementation_revision
= 71;
8273 mips_regnum
.dspacc
= dspacc
= -1;
8274 mips_regnum
.dspctl
= dspctl
= -1;
8275 num_regs
= MIPS_LAST_EMBED_REGNUM
+ 1;
8276 if (info
.bfd_arch_info
!= NULL
8277 && info
.bfd_arch_info
->mach
== bfd_mach_mips3900
)
8278 reg_names
= mips_tx39_reg_names
;
8280 reg_names
= mips_generic_reg_names
;
8283 /* Check any target description for validity. */
8284 if (tdesc_has_registers (info
.target_desc
))
8286 static const char *const mips_gprs
[] = {
8287 "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
8288 "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
8289 "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
8290 "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31"
8292 static const char *const mips_fprs
[] = {
8293 "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7",
8294 "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15",
8295 "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23",
8296 "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31",
8299 const struct tdesc_feature
*feature
;
8302 feature
= tdesc_find_feature (info
.target_desc
,
8303 "org.gnu.gdb.mips.cpu");
8304 if (feature
== NULL
)
8307 tdesc_data
= tdesc_data_alloc ();
8310 for (i
= MIPS_ZERO_REGNUM
; i
<= MIPS_RA_REGNUM
; i
++)
8311 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (), i
,
8315 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8316 mips_regnum
.lo
, "lo");
8317 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8318 mips_regnum
.hi
, "hi");
8319 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8320 mips_regnum
.pc
, "pc");
8325 feature
= tdesc_find_feature (info
.target_desc
,
8326 "org.gnu.gdb.mips.cp0");
8327 if (feature
== NULL
)
8331 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8332 mips_regnum
.badvaddr
, "badvaddr");
8333 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8334 MIPS_PS_REGNUM
, "status");
8335 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8336 mips_regnum
.cause
, "cause");
8341 /* FIXME drow/2007-05-17: The FPU should be optional. The MIPS
8342 backend is not prepared for that, though. */
8343 feature
= tdesc_find_feature (info
.target_desc
,
8344 "org.gnu.gdb.mips.fpu");
8345 if (feature
== NULL
)
8349 for (i
= 0; i
< 32; i
++)
8350 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8351 i
+ mips_regnum
.fp0
, mips_fprs
[i
]);
8353 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8354 mips_regnum
.fp_control_status
,
8357 &= tdesc_numbered_register (feature
, tdesc_data
.get (),
8358 mips_regnum
.fp_implementation_revision
,
8364 num_regs
= mips_regnum
.fp_implementation_revision
+ 1;
8368 feature
= tdesc_find_feature (info
.target_desc
,
8369 "org.gnu.gdb.mips.dsp");
8370 /* The DSP registers are optional; it's OK if they are absent. */
8371 if (feature
!= NULL
)
8375 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8376 dspacc
+ i
++, "hi1");
8377 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8378 dspacc
+ i
++, "lo1");
8379 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8380 dspacc
+ i
++, "hi2");
8381 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8382 dspacc
+ i
++, "lo2");
8383 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8384 dspacc
+ i
++, "hi3");
8385 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8386 dspacc
+ i
++, "lo3");
8388 valid_p
&= tdesc_numbered_register (feature
, tdesc_data
.get (),
8394 mips_regnum
.dspacc
= dspacc
;
8395 mips_regnum
.dspctl
= dspctl
;
8397 num_regs
= mips_regnum
.dspctl
+ 1;
8401 /* It would be nice to detect an attempt to use a 64-bit ABI
8402 when only 32-bit registers are provided. */
8406 /* Try to find a pre-existing architecture. */
8407 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8409 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8411 /* MIPS needs to be pedantic about which ABI and the compressed
8412 ISA variation the object is using. */
8413 if (gdbarch_tdep (arches
->gdbarch
)->elf_flags
!= elf_flags
)
8415 if (gdbarch_tdep (arches
->gdbarch
)->mips_abi
!= mips_abi
)
8417 if (gdbarch_tdep (arches
->gdbarch
)->mips_isa
!= mips_isa
)
8419 /* Need to be pedantic about which register virtual size is
8421 if (gdbarch_tdep (arches
->gdbarch
)->mips64_transfers_32bit_regs_p
8422 != mips64_transfers_32bit_regs_p
)
8424 /* Be pedantic about which FPU is selected. */
8425 if (MIPS_FPU_TYPE (arches
->gdbarch
) != fpu_type
)
8428 return arches
->gdbarch
;
8431 /* Need a new architecture. Fill in a target specific vector. */
8432 tdep
= XCNEW (struct gdbarch_tdep
);
8433 gdbarch
= gdbarch_alloc (&info
, tdep
);
8434 tdep
->elf_flags
= elf_flags
;
8435 tdep
->mips64_transfers_32bit_regs_p
= mips64_transfers_32bit_regs_p
;
8436 tdep
->found_abi
= found_abi
;
8437 tdep
->mips_abi
= mips_abi
;
8438 tdep
->mips_isa
= mips_isa
;
8439 tdep
->mips_fpu_type
= fpu_type
;
8440 tdep
->register_size_valid_p
= 0;
8441 tdep
->register_size
= 0;
8443 if (info
.target_desc
)
8445 /* Some useful properties can be inferred from the target. */
8446 if (tdesc_property (info
.target_desc
, PROPERTY_GP32
) != NULL
)
8448 tdep
->register_size_valid_p
= 1;
8449 tdep
->register_size
= 4;
8451 else if (tdesc_property (info
.target_desc
, PROPERTY_GP64
) != NULL
)
8453 tdep
->register_size_valid_p
= 1;
8454 tdep
->register_size
= 8;
8458 /* Initially set everything according to the default ABI/ISA. */
8459 set_gdbarch_short_bit (gdbarch
, 16);
8460 set_gdbarch_int_bit (gdbarch
, 32);
8461 set_gdbarch_float_bit (gdbarch
, 32);
8462 set_gdbarch_double_bit (gdbarch
, 64);
8463 set_gdbarch_long_double_bit (gdbarch
, 64);
8464 set_gdbarch_register_reggroup_p (gdbarch
, mips_register_reggroup_p
);
8465 set_gdbarch_pseudo_register_read (gdbarch
, mips_pseudo_register_read
);
8466 set_gdbarch_pseudo_register_write (gdbarch
, mips_pseudo_register_write
);
8468 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8469 mips_ax_pseudo_register_collect
);
8470 set_gdbarch_ax_pseudo_register_push_stack
8471 (gdbarch
, mips_ax_pseudo_register_push_stack
);
8473 set_gdbarch_elf_make_msymbol_special (gdbarch
,
8474 mips_elf_make_msymbol_special
);
8475 set_gdbarch_make_symbol_special (gdbarch
, mips_make_symbol_special
);
8476 set_gdbarch_adjust_dwarf2_addr (gdbarch
, mips_adjust_dwarf2_addr
);
8477 set_gdbarch_adjust_dwarf2_line (gdbarch
, mips_adjust_dwarf2_line
);
8479 regnum
= GDBARCH_OBSTACK_ZALLOC (gdbarch
, struct mips_regnum
);
8480 *regnum
= mips_regnum
;
8481 set_gdbarch_fp0_regnum (gdbarch
, regnum
->fp0
);
8482 set_gdbarch_num_regs (gdbarch
, num_regs
);
8483 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8484 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8485 set_gdbarch_virtual_frame_pointer (gdbarch
, mips_virtual_frame_pointer
);
8486 tdep
->mips_processor_reg_names
= reg_names
;
8487 tdep
->regnum
= regnum
;
8492 set_gdbarch_push_dummy_call (gdbarch
, mips_o32_push_dummy_call
);
8493 set_gdbarch_return_value (gdbarch
, mips_o32_return_value
);
8494 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8495 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8496 tdep
->default_mask_address_p
= 0;
8497 set_gdbarch_long_bit (gdbarch
, 32);
8498 set_gdbarch_ptr_bit (gdbarch
, 32);
8499 set_gdbarch_long_long_bit (gdbarch
, 64);
8502 set_gdbarch_push_dummy_call (gdbarch
, mips_o64_push_dummy_call
);
8503 set_gdbarch_return_value (gdbarch
, mips_o64_return_value
);
8504 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 4 - 1;
8505 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 4 - 1;
8506 tdep
->default_mask_address_p
= 0;
8507 set_gdbarch_long_bit (gdbarch
, 32);
8508 set_gdbarch_ptr_bit (gdbarch
, 32);
8509 set_gdbarch_long_long_bit (gdbarch
, 64);
8511 case MIPS_ABI_EABI32
:
8512 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8513 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8514 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8515 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8516 tdep
->default_mask_address_p
= 0;
8517 set_gdbarch_long_bit (gdbarch
, 32);
8518 set_gdbarch_ptr_bit (gdbarch
, 32);
8519 set_gdbarch_long_long_bit (gdbarch
, 64);
8521 case MIPS_ABI_EABI64
:
8522 set_gdbarch_push_dummy_call (gdbarch
, mips_eabi_push_dummy_call
);
8523 set_gdbarch_return_value (gdbarch
, mips_eabi_return_value
);
8524 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8525 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8526 tdep
->default_mask_address_p
= 0;
8527 set_gdbarch_long_bit (gdbarch
, 64);
8528 set_gdbarch_ptr_bit (gdbarch
, 64);
8529 set_gdbarch_long_long_bit (gdbarch
, 64);
8532 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8533 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8534 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8535 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8536 tdep
->default_mask_address_p
= 0;
8537 set_gdbarch_long_bit (gdbarch
, 32);
8538 set_gdbarch_ptr_bit (gdbarch
, 32);
8539 set_gdbarch_long_long_bit (gdbarch
, 64);
8540 set_gdbarch_long_double_bit (gdbarch
, 128);
8541 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8544 set_gdbarch_push_dummy_call (gdbarch
, mips_n32n64_push_dummy_call
);
8545 set_gdbarch_return_value (gdbarch
, mips_n32n64_return_value
);
8546 tdep
->mips_last_arg_regnum
= MIPS_A0_REGNUM
+ 8 - 1;
8547 tdep
->mips_last_fp_arg_regnum
= tdep
->regnum
->fp0
+ 12 + 8 - 1;
8548 tdep
->default_mask_address_p
= 0;
8549 set_gdbarch_long_bit (gdbarch
, 64);
8550 set_gdbarch_ptr_bit (gdbarch
, 64);
8551 set_gdbarch_long_long_bit (gdbarch
, 64);
8552 set_gdbarch_long_double_bit (gdbarch
, 128);
8553 set_gdbarch_long_double_format (gdbarch
, floatformats_ibm_long_double
);
8556 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8559 /* GCC creates a pseudo-section whose name specifies the size of
8560 longs, since -mlong32 or -mlong64 may be used independent of
8561 other options. How those options affect pointer sizes is ABI and
8562 architecture dependent, so use them to override the default sizes
8563 set by the ABI. This table shows the relationship between ABI,
8564 -mlongXX, and size of pointers:
8566 ABI -mlongXX ptr bits
8567 --- -------- --------
8581 Note that for o32 and eabi32, pointers are always 32 bits
8582 regardless of any -mlongXX option. For all others, pointers and
8583 longs are the same, as set by -mlongXX or set by defaults. */
8585 if (info
.abfd
!= NULL
)
8589 bfd_map_over_sections (info
.abfd
, mips_find_long_section
, &long_bit
);
8592 set_gdbarch_long_bit (gdbarch
, long_bit
);
8596 case MIPS_ABI_EABI32
:
8601 case MIPS_ABI_EABI64
:
8602 set_gdbarch_ptr_bit (gdbarch
, long_bit
);
8605 internal_error (__FILE__
, __LINE__
, _("unknown ABI in switch"));
8610 /* FIXME: jlarmour/2000-04-07: There *is* a flag EF_MIPS_32BIT_MODE
8611 that could indicate -gp32 BUT gas/config/tc-mips.c contains the
8614 ``We deliberately don't allow "-gp32" to set the MIPS_32BITMODE
8615 flag in object files because to do so would make it impossible to
8616 link with libraries compiled without "-gp32". This is
8617 unnecessarily restrictive.
8619 We could solve this problem by adding "-gp32" multilibs to gcc,
8620 but to set this flag before gcc is built with such multilibs will
8621 break too many systems.''
8623 But even more unhelpfully, the default linker output target for
8624 mips64-elf is elf32-bigmips, and has EF_MIPS_32BIT_MODE set, even
8625 for 64-bit programs - you need to change the ABI to change this,
8626 and not all gcc targets support that currently. Therefore using
8627 this flag to detect 32-bit mode would do the wrong thing given
8628 the current gcc - it would make GDB treat these 64-bit programs
8629 as 32-bit programs by default. */
8631 set_gdbarch_read_pc (gdbarch
, mips_read_pc
);
8632 set_gdbarch_write_pc (gdbarch
, mips_write_pc
);
8634 /* Add/remove bits from an address. The MIPS needs be careful to
8635 ensure that all 32 bit addresses are sign extended to 64 bits. */
8636 set_gdbarch_addr_bits_remove (gdbarch
, mips_addr_bits_remove
);
8638 /* Unwind the frame. */
8639 set_gdbarch_unwind_pc (gdbarch
, mips_unwind_pc
);
8640 set_gdbarch_unwind_sp (gdbarch
, mips_unwind_sp
);
8641 set_gdbarch_dummy_id (gdbarch
, mips_dummy_id
);
8643 /* Map debug register numbers onto internal register numbers. */
8644 set_gdbarch_stab_reg_to_regnum (gdbarch
, mips_stab_reg_to_regnum
);
8645 set_gdbarch_ecoff_reg_to_regnum (gdbarch
,
8646 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8647 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
,
8648 mips_dwarf_dwarf2_ecoff_reg_to_regnum
);
8649 set_gdbarch_register_sim_regno (gdbarch
, mips_register_sim_regno
);
8651 /* MIPS version of CALL_DUMMY. */
8653 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8654 set_gdbarch_push_dummy_code (gdbarch
, mips_push_dummy_code
);
8655 set_gdbarch_frame_align (gdbarch
, mips_frame_align
);
8657 set_gdbarch_print_float_info (gdbarch
, mips_print_float_info
);
8659 set_gdbarch_convert_register_p (gdbarch
, mips_convert_register_p
);
8660 set_gdbarch_register_to_value (gdbarch
, mips_register_to_value
);
8661 set_gdbarch_value_to_register (gdbarch
, mips_value_to_register
);
8663 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8664 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, mips_breakpoint_kind_from_pc
);
8665 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, mips_sw_breakpoint_from_kind
);
8666 set_gdbarch_adjust_breakpoint_address (gdbarch
,
8667 mips_adjust_breakpoint_address
);
8669 set_gdbarch_skip_prologue (gdbarch
, mips_skip_prologue
);
8671 set_gdbarch_stack_frame_destroyed_p (gdbarch
, mips_stack_frame_destroyed_p
);
8673 set_gdbarch_pointer_to_address (gdbarch
, signed_pointer_to_address
);
8674 set_gdbarch_address_to_pointer (gdbarch
, address_to_signed_pointer
);
8675 set_gdbarch_integer_to_address (gdbarch
, mips_integer_to_address
);
8677 set_gdbarch_register_type (gdbarch
, mips_register_type
);
8679 set_gdbarch_print_registers_info (gdbarch
, mips_print_registers_info
);
8681 set_gdbarch_print_insn (gdbarch
, gdb_print_insn_mips
);
8682 if (mips_abi
== MIPS_ABI_N64
)
8683 set_gdbarch_disassembler_options_implicit
8684 (gdbarch
, (const char *) mips_disassembler_options_n64
);
8685 else if (mips_abi
== MIPS_ABI_N32
)
8686 set_gdbarch_disassembler_options_implicit
8687 (gdbarch
, (const char *) mips_disassembler_options_n32
);
8689 set_gdbarch_disassembler_options_implicit
8690 (gdbarch
, (const char *) mips_disassembler_options_o32
);
8691 set_gdbarch_disassembler_options (gdbarch
, &mips_disassembler_options
);
8692 set_gdbarch_valid_disassembler_options (gdbarch
,
8693 disassembler_options_mips ());
8695 /* FIXME: cagney/2003-08-29: The macros target_have_steppable_watchpoint,
8696 HAVE_NONSTEPPABLE_WATCHPOINT, and target_have_continuable_watchpoint
8697 need to all be folded into the target vector. Since they are
8698 being used as guards for target_stopped_by_watchpoint, why not have
8699 target_stopped_by_watchpoint return the type of watchpoint that the code
8701 set_gdbarch_have_nonsteppable_watchpoint (gdbarch
, 1);
8703 set_gdbarch_skip_trampoline_code (gdbarch
, mips_skip_trampoline_code
);
8705 /* NOTE drow/2012-04-25: We overload the core solib trampoline code
8706 to support MIPS16. This is a bad thing. Make sure not to do it
8707 if we have an OS ABI that actually supports shared libraries, since
8708 shared library support is more important. If we have an OS someday
8709 that supports both shared libraries and MIPS16, we'll have to find
8710 a better place for these.
8711 macro/2012-04-25: But that applies to return trampolines only and
8712 currently no MIPS OS ABI uses shared libraries that have them. */
8713 set_gdbarch_in_solib_return_trampoline (gdbarch
, mips_in_return_stub
);
8715 set_gdbarch_single_step_through_delay (gdbarch
,
8716 mips_single_step_through_delay
);
8718 /* Virtual tables. */
8719 set_gdbarch_vbit_in_delta (gdbarch
, 1);
8721 mips_register_g_packet_guesses (gdbarch
);
8723 /* Hook in OS ABI-specific overrides, if they have been registered. */
8724 info
.tdesc_data
= tdesc_data
.get ();
8725 gdbarch_init_osabi (info
, gdbarch
);
8727 /* The hook may have adjusted num_regs, fetch the final value and
8728 set pc_regnum and sp_regnum now that it has been fixed. */
8729 num_regs
= gdbarch_num_regs (gdbarch
);
8730 set_gdbarch_pc_regnum (gdbarch
, regnum
->pc
+ num_regs
);
8731 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8733 /* Unwind the frame. */
8734 dwarf2_append_unwinders (gdbarch
);
8735 frame_unwind_append_unwinder (gdbarch
, &mips_stub_frame_unwind
);
8736 frame_unwind_append_unwinder (gdbarch
, &mips_insn16_frame_unwind
);
8737 frame_unwind_append_unwinder (gdbarch
, &mips_micro_frame_unwind
);
8738 frame_unwind_append_unwinder (gdbarch
, &mips_insn32_frame_unwind
);
8739 frame_base_append_sniffer (gdbarch
, dwarf2_frame_base_sniffer
);
8740 frame_base_append_sniffer (gdbarch
, mips_stub_frame_base_sniffer
);
8741 frame_base_append_sniffer (gdbarch
, mips_insn16_frame_base_sniffer
);
8742 frame_base_append_sniffer (gdbarch
, mips_micro_frame_base_sniffer
);
8743 frame_base_append_sniffer (gdbarch
, mips_insn32_frame_base_sniffer
);
8745 if (tdesc_data
!= nullptr)
8747 set_tdesc_pseudo_register_type (gdbarch
, mips_pseudo_register_type
);
8748 tdesc_use_registers (gdbarch
, info
.target_desc
, std::move (tdesc_data
));
8750 /* Override the normal target description methods to handle our
8751 dual real and pseudo registers. */
8752 set_gdbarch_register_name (gdbarch
, mips_register_name
);
8753 set_gdbarch_register_reggroup_p (gdbarch
,
8754 mips_tdesc_register_reggroup_p
);
8756 num_regs
= gdbarch_num_regs (gdbarch
);
8757 set_gdbarch_num_pseudo_regs (gdbarch
, num_regs
);
8758 set_gdbarch_pc_regnum (gdbarch
, tdep
->regnum
->pc
+ num_regs
);
8759 set_gdbarch_sp_regnum (gdbarch
, MIPS_SP_REGNUM
+ num_regs
);
8762 /* Add ABI-specific aliases for the registers. */
8763 if (mips_abi
== MIPS_ABI_N32
|| mips_abi
== MIPS_ABI_N64
)
8764 for (i
= 0; i
< ARRAY_SIZE (mips_n32_n64_aliases
); i
++)
8765 user_reg_add (gdbarch
, mips_n32_n64_aliases
[i
].name
,
8766 value_of_mips_user_reg
, &mips_n32_n64_aliases
[i
].regnum
);
8768 for (i
= 0; i
< ARRAY_SIZE (mips_o32_aliases
); i
++)
8769 user_reg_add (gdbarch
, mips_o32_aliases
[i
].name
,
8770 value_of_mips_user_reg
, &mips_o32_aliases
[i
].regnum
);
8772 /* Add some other standard aliases. */
8773 for (i
= 0; i
< ARRAY_SIZE (mips_register_aliases
); i
++)
8774 user_reg_add (gdbarch
, mips_register_aliases
[i
].name
,
8775 value_of_mips_user_reg
, &mips_register_aliases
[i
].regnum
);
8777 for (i
= 0; i
< ARRAY_SIZE (mips_numeric_register_aliases
); i
++)
8778 user_reg_add (gdbarch
, mips_numeric_register_aliases
[i
].name
,
8779 value_of_mips_user_reg
,
8780 &mips_numeric_register_aliases
[i
].regnum
);
8786 mips_abi_update (const char *ignore_args
,
8787 int from_tty
, struct cmd_list_element
*c
)
8789 struct gdbarch_info info
;
8791 /* Force the architecture to update, and (if it's a MIPS architecture)
8792 mips_gdbarch_init will take care of the rest. */
8793 gdbarch_info_init (&info
);
8794 gdbarch_update_p (info
);
8797 /* Print out which MIPS ABI is in use. */
8800 show_mips_abi (struct ui_file
*file
,
8802 struct cmd_list_element
*ignored_cmd
,
8803 const char *ignored_value
)
8805 if (gdbarch_bfd_arch_info (target_gdbarch ())->arch
!= bfd_arch_mips
)
8808 "The MIPS ABI is unknown because the current architecture "
8812 enum mips_abi global_abi
= global_mips_abi ();
8813 enum mips_abi actual_abi
= mips_abi (target_gdbarch ());
8814 const char *actual_abi_str
= mips_abi_strings
[actual_abi
];
8816 if (global_abi
== MIPS_ABI_UNKNOWN
)
8819 "The MIPS ABI is set automatically (currently \"%s\").\n",
8821 else if (global_abi
== actual_abi
)
8824 "The MIPS ABI is assumed to be \"%s\" (due to user setting).\n",
8828 /* Probably shouldn't happen... */
8829 fprintf_filtered (file
,
8830 "The (auto detected) MIPS ABI \"%s\" is in use "
8831 "even though the user setting was \"%s\".\n",
8832 actual_abi_str
, mips_abi_strings
[global_abi
]);
8837 /* Print out which MIPS compressed ISA encoding is used. */
8840 show_mips_compression (struct ui_file
*file
, int from_tty
,
8841 struct cmd_list_element
*c
, const char *value
)
8843 fprintf_filtered (file
, _("The compressed ISA encoding used is %s.\n"),
8847 /* Return a textual name for MIPS FPU type FPU_TYPE. */
8850 mips_fpu_type_str (enum mips_fpu_type fpu_type
)
8856 case MIPS_FPU_SINGLE
:
8858 case MIPS_FPU_DOUBLE
:
8866 mips_dump_tdep (struct gdbarch
*gdbarch
, struct ui_file
*file
)
8868 struct gdbarch_tdep
*tdep
= gdbarch_tdep (gdbarch
);
8872 int ef_mips_32bitmode
;
8873 /* Determine the ISA. */
8874 switch (tdep
->elf_flags
& EF_MIPS_ARCH
)
8892 /* Determine the size of a pointer. */
8893 ef_mips_32bitmode
= (tdep
->elf_flags
& EF_MIPS_32BITMODE
);
8894 fprintf_unfiltered (file
,
8895 "mips_dump_tdep: tdep->elf_flags = 0x%x\n",
8897 fprintf_unfiltered (file
,
8898 "mips_dump_tdep: ef_mips_32bitmode = %d\n",
8900 fprintf_unfiltered (file
,
8901 "mips_dump_tdep: ef_mips_arch = %d\n",
8903 fprintf_unfiltered (file
,
8904 "mips_dump_tdep: tdep->mips_abi = %d (%s)\n",
8905 tdep
->mips_abi
, mips_abi_strings
[tdep
->mips_abi
]);
8906 fprintf_unfiltered (file
,
8908 "mips_mask_address_p() %d (default %d)\n",
8909 mips_mask_address_p (tdep
),
8910 tdep
->default_mask_address_p
);
8912 fprintf_unfiltered (file
,
8913 "mips_dump_tdep: MIPS_DEFAULT_FPU_TYPE = %d (%s)\n",
8914 MIPS_DEFAULT_FPU_TYPE
,
8915 mips_fpu_type_str (MIPS_DEFAULT_FPU_TYPE
));
8916 fprintf_unfiltered (file
, "mips_dump_tdep: MIPS_EABI = %d\n",
8917 MIPS_EABI (gdbarch
));
8918 fprintf_unfiltered (file
,
8919 "mips_dump_tdep: MIPS_FPU_TYPE = %d (%s)\n",
8920 MIPS_FPU_TYPE (gdbarch
),
8921 mips_fpu_type_str (MIPS_FPU_TYPE (gdbarch
)));
8924 void _initialize_mips_tdep ();
8926 _initialize_mips_tdep ()
8928 static struct cmd_list_element
*mipsfpulist
= NULL
;
8930 mips_abi_string
= mips_abi_strings
[MIPS_ABI_UNKNOWN
];
8931 if (MIPS_ABI_LAST
+ 1
8932 != sizeof (mips_abi_strings
) / sizeof (mips_abi_strings
[0]))
8933 internal_error (__FILE__
, __LINE__
, _("mips_abi_strings out of sync"));
8935 gdbarch_register (bfd_arch_mips
, mips_gdbarch_init
, mips_dump_tdep
);
8937 /* Create feature sets with the appropriate properties. The values
8938 are not important. */
8939 mips_tdesc_gp32
= allocate_target_description ().release ();
8940 set_tdesc_property (mips_tdesc_gp32
, PROPERTY_GP32
, "");
8942 mips_tdesc_gp64
= allocate_target_description ().release ();
8943 set_tdesc_property (mips_tdesc_gp64
, PROPERTY_GP64
, "");
8945 /* Add root prefix command for all "set mips"/"show mips" commands. */
8946 add_basic_prefix_cmd ("mips", no_class
,
8947 _("Various MIPS specific commands."),
8948 &setmipscmdlist
, "set mips ", 0, &setlist
);
8950 add_show_prefix_cmd ("mips", no_class
,
8951 _("Various MIPS specific commands."),
8952 &showmipscmdlist
, "show mips ", 0, &showlist
);
8954 /* Allow the user to override the ABI. */
8955 add_setshow_enum_cmd ("abi", class_obscure
, mips_abi_strings
,
8956 &mips_abi_string
, _("\
8957 Set the MIPS ABI used by this program."), _("\
8958 Show the MIPS ABI used by this program."), _("\
8959 This option can be set to one of:\n\
8960 auto - the default ABI associated with the current binary\n\
8969 &setmipscmdlist
, &showmipscmdlist
);
8971 /* Allow the user to set the ISA to assume for compressed code if ELF
8972 file flags don't tell or there is no program file selected. This
8973 setting is updated whenever unambiguous ELF file flags are interpreted,
8974 and carried over to subsequent sessions. */
8975 add_setshow_enum_cmd ("compression", class_obscure
, mips_compression_strings
,
8976 &mips_compression_string
, _("\
8977 Set the compressed ISA encoding used by MIPS code."), _("\
8978 Show the compressed ISA encoding used by MIPS code."), _("\
8979 Select the compressed ISA encoding used in functions that have no symbol\n\
8980 information available. The encoding can be set to either of:\n\
8983 and is updated automatically from ELF file flags if available."),
8985 show_mips_compression
,
8986 &setmipscmdlist
, &showmipscmdlist
);
8988 /* Let the user turn off floating point and set the fence post for
8989 heuristic_proc_start. */
8991 add_basic_prefix_cmd ("mipsfpu", class_support
,
8992 _("Set use of MIPS floating-point coprocessor."),
8993 &mipsfpulist
, "set mipsfpu ", 0, &setlist
);
8994 add_cmd ("single", class_support
, set_mipsfpu_single_command
,
8995 _("Select single-precision MIPS floating-point coprocessor."),
8997 add_cmd ("double", class_support
, set_mipsfpu_double_command
,
8998 _("Select double-precision MIPS floating-point coprocessor."),
9000 add_alias_cmd ("on", "double", class_support
, 1, &mipsfpulist
);
9001 add_alias_cmd ("yes", "double", class_support
, 1, &mipsfpulist
);
9002 add_alias_cmd ("1", "double", class_support
, 1, &mipsfpulist
);
9003 add_cmd ("none", class_support
, set_mipsfpu_none_command
,
9004 _("Select no MIPS floating-point coprocessor."), &mipsfpulist
);
9005 add_alias_cmd ("off", "none", class_support
, 1, &mipsfpulist
);
9006 add_alias_cmd ("no", "none", class_support
, 1, &mipsfpulist
);
9007 add_alias_cmd ("0", "none", class_support
, 1, &mipsfpulist
);
9008 add_cmd ("auto", class_support
, set_mipsfpu_auto_command
,
9009 _("Select MIPS floating-point coprocessor automatically."),
9011 add_cmd ("mipsfpu", class_support
, show_mipsfpu_command
,
9012 _("Show current use of MIPS floating-point coprocessor target."),
9015 /* We really would like to have both "0" and "unlimited" work, but
9016 command.c doesn't deal with that. So make it a var_zinteger
9017 because the user can always use "999999" or some such for unlimited. */
9018 add_setshow_zinteger_cmd ("heuristic-fence-post", class_support
,
9019 &heuristic_fence_post
, _("\
9020 Set the distance searched for the start of a function."), _("\
9021 Show the distance searched for the start of a function."), _("\
9022 If you are debugging a stripped executable, GDB needs to search through the\n\
9023 program for the start of a function. This command sets the distance of the\n\
9024 search. The only need to set it is when debugging a stripped executable."),
9025 reinit_frame_cache_sfunc
,
9026 NULL
, /* FIXME: i18n: The distance searched for
9027 the start of a function is %s. */
9028 &setlist
, &showlist
);
9030 /* Allow the user to control whether the upper bits of 64-bit
9031 addresses should be zeroed. */
9032 add_setshow_auto_boolean_cmd ("mask-address", no_class
,
9033 &mask_address_var
, _("\
9034 Set zeroing of upper 32 bits of 64-bit addresses."), _("\
9035 Show zeroing of upper 32 bits of 64-bit addresses."), _("\
9036 Use \"on\" to enable the masking, \"off\" to disable it and \"auto\" to\n\
9037 allow GDB to determine the correct value."),
9038 NULL
, show_mask_address
,
9039 &setmipscmdlist
, &showmipscmdlist
);
9041 /* Allow the user to control the size of 32 bit registers within the
9042 raw remote packet. */
9043 add_setshow_boolean_cmd ("remote-mips64-transfers-32bit-regs", class_obscure
,
9044 &mips64_transfers_32bit_regs_p
, _("\
9045 Set compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9047 Show compatibility with 64-bit MIPS target that transfers 32-bit quantities."),
9049 Use \"on\" to enable backward compatibility with older MIPS 64 GDB+target\n\
9050 that would transfer 32 bits for some registers (e.g. SR, FSR) and\n\
9051 64 bits for others. Use \"off\" to disable compatibility mode"),
9052 set_mips64_transfers_32bit_regs
,
9053 NULL
, /* FIXME: i18n: Compatibility with 64-bit
9054 MIPS target that transfers 32-bit
9055 quantities is %s. */
9056 &setlist
, &showlist
);
9058 /* Debug this files internals. */
9059 add_setshow_zuinteger_cmd ("mips", class_maintenance
,
9061 Set mips debugging."), _("\
9062 Show mips debugging."), _("\
9063 When non-zero, mips specific debugging is enabled."),
9065 NULL
, /* FIXME: i18n: Mips debugging is
9067 &setdebuglist
, &showdebuglist
);