1 /* BFD support for handling relocation entries.
2 Copyright (C) 1990-2023 Free Software Foundation, Inc.
3 Written by Cygnus Support.
5 This file is part of BFD, the Binary File Descriptor library.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; if not, write to the Free Software
19 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
20 MA 02110-1301, USA. */
26 BFD maintains relocations in much the same way it maintains
27 symbols: they are left alone until required, then read in
28 en-masse and translated into an internal form. A common
29 routine <<bfd_perform_relocation>> acts upon the
30 canonical form to do the fixup.
32 Relocations are maintained on a per section basis,
33 while symbols are maintained on a per BFD basis.
35 All that a back end has to do to fit the BFD interface is to create
36 a <<struct reloc_cache_entry>> for each relocation
37 in a particular section, and fill in the right bits of the structures.
46 /* DO compile in the reloc_code name table from libbfd.h. */
47 #define _BFD_MAKE_TABLE_bfd_reloc_code_real
58 typedef arelent, howto manager, Relocations, Relocations
63 This is the structure of a relocation entry:
66 .typedef enum bfd_reloc_status
68 . {* No errors detected. Note - the value 2 is used so that it
69 . will not be mistaken for the boolean TRUE or FALSE values. *}
72 . {* The relocation was performed, but there was an overflow. *}
75 . {* The address to relocate was not within the section supplied. *}
76 . bfd_reloc_outofrange,
78 . {* Used by special functions. *}
81 . {* Unsupported relocation size requested. *}
82 . bfd_reloc_notsupported,
84 . {* Target specific meaning. *}
87 . {* The symbol to relocate against was undefined. *}
88 . bfd_reloc_undefined,
90 . {* The relocation was performed, but may not be ok. If this type is
91 . returned, the error_message argument to bfd_perform_relocation
95 . bfd_reloc_status_type;
97 .typedef const struct reloc_howto_struct reloc_howto_type;
101 .struct reloc_cache_entry
103 . {* A pointer into the canonical table of pointers. *}
104 . struct bfd_symbol **sym_ptr_ptr;
106 . {* offset in section. *}
107 . bfd_size_type address;
109 . {* addend for relocation value. *}
112 . {* Pointer to how to perform the required relocation. *}
113 . reloc_howto_type *howto;
122 Here is a description of each of the fields within an <<arelent>>:
126 The symbol table pointer points to a pointer to the symbol
127 associated with the relocation request. It is the pointer
128 into the table returned by the back end's
129 <<canonicalize_symtab>> action. @xref{Symbols}. The symbol is
130 referenced through a pointer to a pointer so that tools like
131 the linker can fix up all the symbols of the same name by
132 modifying only one pointer. The relocation routine looks in
133 the symbol and uses the base of the section the symbol is
134 attached to and the value of the symbol as the initial
135 relocation offset. If the symbol pointer is zero, then the
136 section provided is looked up.
140 The <<address>> field gives the offset in bytes from the base of
141 the section data which owns the relocation record to the first
142 byte of relocatable information. The actual data relocated
143 will be relative to this point; for example, a relocation
144 type which modifies the bottom two bytes of a four byte word
145 would not touch the first byte pointed to in a big endian
150 The <<addend>> is a value provided by the back end to be added (!)
151 to the relocation offset. Its interpretation is dependent upon
152 the howto. For example, on the 68k the code:
157 | return foo[0x12345678];
160 Could be compiled into:
163 | moveb @@#12345678,d0
168 This could create a reloc pointing to <<foo>>, but leave the
169 offset in the data, something like:
171 |RELOCATION RECORDS FOR [.text]:
175 |00000000 4e56 fffc ; linkw fp,#-4
176 |00000004 1039 1234 5678 ; moveb @@#12345678,d0
177 |0000000a 49c0 ; extbl d0
178 |0000000c 4e5e ; unlk fp
181 Using coff and an 88k, some instructions don't have enough
182 space in them to represent the full address range, and
183 pointers have to be loaded in two parts. So you'd get something like:
185 | or.u r13,r0,hi16(_foo+0x12345678)
186 | ld.b r2,r13,lo16(_foo+0x12345678)
189 This should create two relocs, both pointing to <<_foo>>, and with
190 0x12340000 in their addend field. The data would consist of:
192 |RELOCATION RECORDS FOR [.text]:
194 |00000002 HVRT16 _foo+0x12340000
195 |00000006 LVRT16 _foo+0x12340000
197 |00000000 5da05678 ; or.u r13,r0,0x5678
198 |00000004 1c4d5678 ; ld.b r2,r13,0x5678
199 |00000008 f400c001 ; jmp r1
201 The relocation routine digs out the value from the data, adds
202 it to the addend to get the original offset, and then adds the
203 value of <<_foo>>. Note that all 32 bits have to be kept around
204 somewhere, to cope with carry from bit 15 to bit 16.
206 One further example is the sparc and the a.out format. The
207 sparc has a similar problem to the 88k, in that some
208 instructions don't have room for an entire offset, but on the
209 sparc the parts are created in odd sized lumps. The designers of
210 the a.out format chose to not use the data within the section
211 for storing part of the offset; all the offset is kept within
212 the reloc. Anything in the data should be ignored.
215 | sethi %hi(_foo+0x12345678),%g2
216 | ldsb [%g2+%lo(_foo+0x12345678)],%i0
220 Both relocs contain a pointer to <<foo>>, and the offsets
223 |RELOCATION RECORDS FOR [.text]:
225 |00000004 HI22 _foo+0x12345678
226 |00000008 LO10 _foo+0x12345678
228 |00000000 9de3bf90 ; save %sp,-112,%sp
229 |00000004 05000000 ; sethi %hi(_foo+0),%g2
230 |00000008 f048a000 ; ldsb [%g2+%lo(_foo+0)],%i0
231 |0000000c 81c7e008 ; ret
232 |00000010 81e80000 ; restore
236 The <<howto>> field can be imagined as a
237 relocation instruction. It is a pointer to a structure which
238 contains information on what to do with all of the other
239 information in the reloc record and data section. A back end
240 would normally have a relocation instruction set and turn
241 relocations into pointers to the correct structure on input -
242 but it would be possible to create each howto field on demand.
248 <<enum complain_overflow>>
250 Indicates what sort of overflow checking should be done when
251 performing a relocation.
254 .enum complain_overflow
256 . {* Do not complain on overflow. *}
257 . complain_overflow_dont,
259 . {* Complain if the value overflows when considered as a signed
260 . number one bit larger than the field. ie. A bitfield of N bits
261 . is allowed to represent -2**n to 2**n-1. *}
262 . complain_overflow_bitfield,
264 . {* Complain if the value overflows when considered as a signed
266 . complain_overflow_signed,
268 . {* Complain if the value overflows when considered as an
269 . unsigned number. *}
270 . complain_overflow_unsigned
279 The <<reloc_howto_type>> is a structure which contains all the
280 information that libbfd needs to know to tie up a back end's data.
283 .struct reloc_howto_struct
285 . {* The type field has mainly a documentary use - the back end can
286 . do what it wants with it, though normally the back end's idea of
287 . an external reloc number is stored in this field. *}
290 . {* The size of the item to be relocated in bytes. *}
291 . unsigned int size:4;
293 . {* The number of bits in the field to be relocated. This is used
294 . when doing overflow checking. *}
295 . unsigned int bitsize:7;
297 . {* The value the final relocation is shifted right by. This drops
298 . unwanted data from the relocation. *}
299 . unsigned int rightshift:6;
301 . {* The bit position of the reloc value in the destination.
302 . The relocated value is left shifted by this amount. *}
303 . unsigned int bitpos:6;
305 . {* What type of overflow error should be checked for when
307 . ENUM_BITFIELD (complain_overflow) complain_on_overflow:2;
309 . {* The relocation value should be negated before applying. *}
310 . unsigned int negate:1;
312 . {* The relocation is relative to the item being relocated. *}
313 . unsigned int pc_relative:1;
315 . {* Some formats record a relocation addend in the section contents
316 . rather than with the relocation. For ELF formats this is the
317 . distinction between USE_REL and USE_RELA (though the code checks
318 . for USE_REL == 1/0). The value of this field is TRUE if the
319 . addend is recorded with the section contents; when performing a
320 . partial link (ld -r) the section contents (the data) will be
321 . modified. The value of this field is FALSE if addends are
322 . recorded with the relocation (in arelent.addend); when performing
323 . a partial link the relocation will be modified.
324 . All relocations for all ELF USE_RELA targets should set this field
325 . to FALSE (values of TRUE should be looked on with suspicion).
326 . However, the converse is not true: not all relocations of all ELF
327 . USE_REL targets set this field to TRUE. Why this is so is peculiar
328 . to each particular target. For relocs that aren't used in partial
329 . links (e.g. GOT stuff) it doesn't matter what this is set to. *}
330 . unsigned int partial_inplace:1;
332 . {* When some formats create PC relative instructions, they leave
333 . the value of the pc of the place being relocated in the offset
334 . slot of the instruction, so that a PC relative relocation can
335 . be made just by adding in an ordinary offset (e.g., sun3 a.out).
336 . Some formats leave the displacement part of an instruction
337 . empty (e.g., ELF); this flag signals the fact. *}
338 . unsigned int pcrel_offset:1;
340 . {* Whether bfd_install_relocation should just install the addend,
341 . or should follow the practice of some older object formats and
342 . install a value including the symbol. *}
343 . unsigned int install_addend:1;
345 . {* src_mask selects the part of the instruction (or data) to be used
346 . in the relocation sum. If the target relocations don't have an
347 . addend in the reloc, eg. ELF USE_REL, src_mask will normally equal
348 . dst_mask to extract the addend from the section contents. If
349 . relocations do have an addend in the reloc, eg. ELF USE_RELA, this
350 . field should normally be zero. Non-zero values for ELF USE_RELA
351 . targets should be viewed with suspicion as normally the value in
352 . the dst_mask part of the section contents should be ignored. *}
355 . {* dst_mask selects which parts of the instruction (or data) are
356 . replaced with a relocated value. *}
359 . {* If this field is non null, then the supplied function is
360 . called rather than the normal function. This allows really
361 . strange relocation methods to be accommodated. *}
362 . bfd_reloc_status_type (*special_function)
363 . (bfd *, arelent *, struct bfd_symbol *, void *, asection *,
366 . {* The textual name of the relocation type. *}
377 The HOWTO macro fills in a reloc_howto_type (a typedef for
378 const struct reloc_howto_struct).
380 .#define HOWTO_INSTALL_ADDEND 0
381 .#define HOWTO_RSIZE(sz) ((sz) < 0 ? -(sz) : (sz))
382 .#define HOWTO(type, right, size, bits, pcrel, left, ovf, func, name, \
383 . inplace, src_mask, dst_mask, pcrel_off) \
384 . { (unsigned) type, HOWTO_RSIZE (size), bits, right, left, ovf, \
385 . size < 0, pcrel, inplace, pcrel_off, HOWTO_INSTALL_ADDEND, \
386 . src_mask, dst_mask, func, name }
389 This is used to fill in an empty howto entry in an array.
391 .#define EMPTY_HOWTO(C) \
392 . HOWTO ((C), 0, 1, 0, false, 0, complain_overflow_dont, NULL, \
393 . NULL, false, 0, 0, false)
395 .static inline unsigned int
396 .bfd_get_reloc_size (reloc_howto_type *howto)
398 . return howto->size;
408 How relocs are tied together in an <<asection>>:
410 .typedef struct relent_chain
413 . struct relent_chain *next;
419 /* N_ONES produces N one bits, without undefined behaviour for N
420 between zero and the number of bits in a bfd_vma. */
421 #define N_ONES(n) ((n) == 0 ? 0 : ((bfd_vma) 1 << ((n) - 1) << 1) - 1)
428 bfd_reloc_status_type bfd_check_overflow
429 (enum complain_overflow how,
430 unsigned int bitsize,
431 unsigned int rightshift,
432 unsigned int addrsize,
436 Perform overflow checking on @var{relocation} which has
437 @var{bitsize} significant bits and will be shifted right by
438 @var{rightshift} bits, on a machine with addresses containing
439 @var{addrsize} significant bits. The result is either of
440 @code{bfd_reloc_ok} or @code{bfd_reloc_overflow}.
444 bfd_reloc_status_type
445 bfd_check_overflow (enum complain_overflow how
,
446 unsigned int bitsize
,
447 unsigned int rightshift
,
448 unsigned int addrsize
,
451 bfd_vma fieldmask
, addrmask
, signmask
, ss
, a
;
452 bfd_reloc_status_type flag
= bfd_reloc_ok
;
457 /* Note: BITSIZE should always be <= ADDRSIZE, but in case it's not,
458 we'll be permissive: extra bits in the field mask will
459 automatically extend the address mask for purposes of the
461 fieldmask
= N_ONES (bitsize
);
462 signmask
= ~fieldmask
;
463 addrmask
= N_ONES (addrsize
) | (fieldmask
<< rightshift
);
464 a
= (relocation
& addrmask
) >> rightshift
;
468 case complain_overflow_dont
:
471 case complain_overflow_signed
:
472 /* If any sign bits are set, all sign bits must be set. That
473 is, A must be a valid negative address after shifting. */
474 signmask
= ~ (fieldmask
>> 1);
477 case complain_overflow_bitfield
:
478 /* Bitfields are sometimes signed, sometimes unsigned. We
479 explicitly allow an address wrap too, which means a bitfield
480 of n bits is allowed to store -2**n to 2**n-1. Thus overflow
481 if the value has some, but not all, bits set outside the
484 if (ss
!= 0 && ss
!= ((addrmask
>> rightshift
) & signmask
))
485 flag
= bfd_reloc_overflow
;
488 case complain_overflow_unsigned
:
489 /* We have an overflow if the address does not fit in the field. */
490 if ((a
& signmask
) != 0)
491 flag
= bfd_reloc_overflow
;
503 bfd_reloc_offset_in_range
506 bool bfd_reloc_offset_in_range
507 (reloc_howto_type *howto,
510 bfd_size_type offset);
513 Returns TRUE if the reloc described by @var{HOWTO} can be
514 applied at @var{OFFSET} octets in @var{SECTION}.
518 /* HOWTO describes a relocation, at offset OCTET. Return whether the
519 relocation field is within SECTION of ABFD. */
522 bfd_reloc_offset_in_range (reloc_howto_type
*howto
,
527 bfd_size_type octet_end
= bfd_get_section_limit_octets (abfd
, section
);
528 bfd_size_type reloc_size
= bfd_get_reloc_size (howto
);
530 /* The reloc field must be contained entirely within the section.
531 Allow zero length fields (marker relocs or NONE relocs where no
532 relocation will be performed) at the end of the section. */
533 return octet
<= octet_end
&& reloc_size
<= octet_end
- octet
;
536 /* Read and return the section contents at DATA converted to a host
537 integer (bfd_vma). The number of bytes read is given by the HOWTO. */
540 read_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
)
542 switch (bfd_get_reloc_size (howto
))
548 return bfd_get_8 (abfd
, data
);
551 return bfd_get_16 (abfd
, data
);
554 return bfd_get_24 (abfd
, data
);
557 return bfd_get_32 (abfd
, data
);
561 return bfd_get_64 (abfd
, data
);
570 /* Convert VAL to target format and write to DATA. The number of
571 bytes written is given by the HOWTO. */
574 write_reloc (bfd
*abfd
, bfd_vma val
, bfd_byte
*data
, reloc_howto_type
*howto
)
576 switch (bfd_get_reloc_size (howto
))
582 bfd_put_8 (abfd
, val
, data
);
586 bfd_put_16 (abfd
, val
, data
);
590 bfd_put_24 (abfd
, val
, data
);
594 bfd_put_32 (abfd
, val
, data
);
599 bfd_put_64 (abfd
, val
, data
);
608 /* Apply RELOCATION value to target bytes at DATA, according to
612 apply_reloc (bfd
*abfd
, bfd_byte
*data
, reloc_howto_type
*howto
,
615 bfd_vma val
= read_reloc (abfd
, data
, howto
);
618 relocation
= -relocation
;
620 val
= ((val
& ~howto
->dst_mask
)
621 | (((val
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
623 write_reloc (abfd
, val
, data
, howto
);
628 bfd_perform_relocation
631 bfd_reloc_status_type bfd_perform_relocation
633 arelent *reloc_entry,
635 asection *input_section,
637 char **error_message);
640 If @var{output_bfd} is supplied to this function, the
641 generated image will be relocatable; the relocations are
642 copied to the output file after they have been changed to
643 reflect the new state of the world. There are two ways of
644 reflecting the results of partial linkage in an output file:
645 by modifying the output data in place, and by modifying the
646 relocation record. Some native formats (e.g., basic a.out and
647 basic coff) have no way of specifying an addend in the
648 relocation type, so the addend has to go in the output data.
649 This is no big deal since in these formats the output data
650 slot will always be big enough for the addend. Complex reloc
651 types with addends were invented to solve just this problem.
652 The @var{error_message} argument is set to an error message if
653 this return @code{bfd_reloc_dangerous}.
657 bfd_reloc_status_type
658 bfd_perform_relocation (bfd
*abfd
,
659 arelent
*reloc_entry
,
661 asection
*input_section
,
663 char **error_message
)
666 bfd_reloc_status_type flag
= bfd_reloc_ok
;
667 bfd_size_type octets
;
668 bfd_vma output_base
= 0;
669 reloc_howto_type
*howto
= reloc_entry
->howto
;
670 asection
*reloc_target_output_section
;
673 symbol
= *(reloc_entry
->sym_ptr_ptr
);
675 /* If we are not producing relocatable output, return an error if
676 the symbol is not defined. An undefined weak symbol is
677 considered to have a value of zero (SVR4 ABI, p. 4-27). */
678 if (bfd_is_und_section (symbol
->section
)
679 && (symbol
->flags
& BSF_WEAK
) == 0
680 && output_bfd
== NULL
)
681 flag
= bfd_reloc_undefined
;
683 /* If there is a function supplied to handle this relocation type,
684 call it. It'll return `bfd_reloc_continue' if further processing
686 if (howto
&& howto
->special_function
)
688 bfd_reloc_status_type cont
;
690 /* Note - we do not call bfd_reloc_offset_in_range here as the
691 reloc_entry->address field might actually be valid for the
692 backend concerned. It is up to the special_function itself
693 to call bfd_reloc_offset_in_range if needed. */
694 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
, data
,
695 input_section
, output_bfd
,
697 if (cont
!= bfd_reloc_continue
)
701 if (bfd_is_abs_section (symbol
->section
)
702 && output_bfd
!= NULL
)
704 reloc_entry
->address
+= input_section
->output_offset
;
708 /* PR 17512: file: 0f67f69d. */
710 return bfd_reloc_undefined
;
712 /* Is the address of the relocation really within the section? */
713 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
714 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
715 return bfd_reloc_outofrange
;
717 /* Work out which section the relocation is targeted at and the
718 initial relocation command value. */
720 /* Get symbol value. (Common symbols are special.) */
721 if (bfd_is_com_section (symbol
->section
))
724 relocation
= symbol
->value
;
726 reloc_target_output_section
= symbol
->section
->output_section
;
728 /* Convert input-section-relative symbol value to absolute. */
729 if ((output_bfd
&& ! howto
->partial_inplace
)
730 || reloc_target_output_section
== NULL
)
733 output_base
= reloc_target_output_section
->vma
;
735 output_base
+= symbol
->section
->output_offset
;
737 /* If symbol addresses are in octets, convert to bytes. */
738 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
739 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
740 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
742 relocation
+= output_base
;
744 /* Add in supplied addend. */
745 relocation
+= reloc_entry
->addend
;
747 /* Here the variable relocation holds the final address of the
748 symbol we are relocating against, plus any addend. */
750 if (howto
->pc_relative
)
752 /* This is a PC relative relocation. We want to set RELOCATION
753 to the distance between the address of the symbol and the
754 location. RELOCATION is already the address of the symbol.
756 We start by subtracting the address of the section containing
759 If pcrel_offset is set, we must further subtract the position
760 of the location within the section. Some targets arrange for
761 the addend to be the negative of the position of the location
762 within the section; for example, i386-aout does this. For
763 i386-aout, pcrel_offset is FALSE. Some other targets do not
764 include the position of the location; for example, ELF.
765 For those targets, pcrel_offset is TRUE.
767 If we are producing relocatable output, then we must ensure
768 that this reloc will be correctly computed when the final
769 relocation is done. If pcrel_offset is FALSE we want to wind
770 up with the negative of the location within the section,
771 which means we must adjust the existing addend by the change
772 in the location within the section. If pcrel_offset is TRUE
773 we do not want to adjust the existing addend at all.
775 FIXME: This seems logical to me, but for the case of
776 producing relocatable output it is not what the code
777 actually does. I don't want to change it, because it seems
778 far too likely that something will break. */
781 input_section
->output_section
->vma
+ input_section
->output_offset
;
783 if (howto
->pcrel_offset
)
784 relocation
-= reloc_entry
->address
;
787 if (output_bfd
!= NULL
)
789 if (! howto
->partial_inplace
)
791 /* This is a partial relocation, and we want to apply the relocation
792 to the reloc entry rather than the raw data. Modify the reloc
793 inplace to reflect what we now know. */
794 reloc_entry
->addend
= relocation
;
795 reloc_entry
->address
+= input_section
->output_offset
;
800 /* This is a partial relocation, but inplace, so modify the
803 If we've relocated with a symbol with a section, change
804 into a ref to the section belonging to the symbol. */
806 reloc_entry
->address
+= input_section
->output_offset
;
809 if (abfd
->xvec
->flavour
== bfd_target_coff_flavour
)
811 /* For m68k-coff, the addend was being subtracted twice during
812 relocation with -r. Removing the line below this comment
813 fixes that problem; see PR 2953.
815 However, Ian wrote the following, regarding removing the line below,
816 which explains why it is still enabled: --djm
818 If you put a patch like that into BFD you need to check all the COFF
819 linkers. I am fairly certain that patch will break coff-i386 (e.g.,
820 SCO); see coff_i386_reloc in coff-i386.c where I worked around the
821 problem in a different way. There may very well be a reason that the
822 code works as it does.
824 Hmmm. The first obvious point is that bfd_perform_relocation should
825 not have any tests that depend upon the flavour. It's seem like
826 entirely the wrong place for such a thing. The second obvious point
827 is that the current code ignores the reloc addend when producing
828 relocatable output for COFF. That's peculiar. In fact, I really
829 have no idea what the point of the line you want to remove is.
831 A typical COFF reloc subtracts the old value of the symbol and adds in
832 the new value to the location in the object file (if it's a pc
833 relative reloc it adds the difference between the symbol value and the
834 location). When relocating we need to preserve that property.
836 BFD handles this by setting the addend to the negative of the old
837 value of the symbol. Unfortunately it handles common symbols in a
838 non-standard way (it doesn't subtract the old value) but that's a
839 different story (we can't change it without losing backward
840 compatibility with old object files) (coff-i386 does subtract the old
841 value, to be compatible with existing coff-i386 targets, like SCO).
843 So everything works fine when not producing relocatable output. When
844 we are producing relocatable output, logically we should do exactly
845 what we do when not producing relocatable output. Therefore, your
846 patch is correct. In fact, it should probably always just set
847 reloc_entry->addend to 0 for all cases, since it is, in fact, going to
848 add the value into the object file. This won't hurt the COFF code,
849 which doesn't use the addend; I'm not sure what it will do to other
850 formats (the thing to check for would be whether any formats both use
851 the addend and set partial_inplace).
853 When I wanted to make coff-i386 produce relocatable output, I ran
854 into the problem that you are running into: I wanted to remove that
855 line. Rather than risk it, I made the coff-i386 relocs use a special
856 function; it's coff_i386_reloc in coff-i386.c. The function
857 specifically adds the addend field into the object file, knowing that
858 bfd_perform_relocation is not going to. If you remove that line, then
859 coff-i386.c will wind up adding the addend field in twice. It's
860 trivial to fix; it just needs to be done.
862 The problem with removing the line is just that it may break some
863 working code. With BFD it's hard to be sure of anything. The right
864 way to deal with this is simply to build and test at least all the
865 supported COFF targets. It should be straightforward if time and disk
866 space consuming. For each target:
868 2) generate some executable, and link it using -r (I would
869 probably use paranoia.o and link against newlib/libc.a, which
870 for all the supported targets would be available in
871 /usr/cygnus/progressive/H-host/target/lib/libc.a).
872 3) make the change to reloc.c
873 4) rebuild the linker
875 6) if the resulting object files are the same, you have at least
877 7) if they are different you have to figure out which version is
880 relocation
-= reloc_entry
->addend
;
881 reloc_entry
->addend
= 0;
885 reloc_entry
->addend
= relocation
;
890 /* FIXME: This overflow checking is incomplete, because the value
891 might have overflowed before we get here. For a correct check we
892 need to compute the value in a size larger than bitsize, but we
893 can't reasonably do that for a reloc the same size as a host
895 FIXME: We should also do overflow checking on the result after
896 adding in the value contained in the object file. */
897 if (howto
->complain_on_overflow
!= complain_overflow_dont
898 && flag
== bfd_reloc_ok
)
899 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
902 bfd_arch_bits_per_address (abfd
),
905 /* Either we are relocating all the way, or we don't want to apply
906 the relocation to the reloc entry (probably because there isn't
907 any room in the output format to describe addends to relocs). */
909 /* The cast to bfd_vma avoids a bug in the Alpha OSF/1 C compiler
910 (OSF version 1.3, compiler version 3.11). It miscompiles the
924 x <<= (unsigned long) s.i0;
928 printf ("succeeded (%lx)\n", x);
932 relocation
>>= (bfd_vma
) howto
->rightshift
;
934 /* Shift everything up to where it's going to be used. */
935 relocation
<<= (bfd_vma
) howto
->bitpos
;
937 /* Wait for the day when all have the mask in them. */
940 i instruction to be left alone
941 o offset within instruction
942 r relocation offset to apply
951 (( i i i i i o o o o o from bfd_get<size>
952 and S S S S S) to get the size offset we want
953 + r r r r r r r r r r) to get the final value to place
954 and D D D D D to chop to right size
955 -----------------------
958 ( i i i i i o o o o o from bfd_get<size>
959 and N N N N N ) get instruction
960 -----------------------
966 -----------------------
967 = R R R R R R R R R R put into bfd_put<size>
970 data
= (bfd_byte
*) data
+ octets
;
971 apply_reloc (abfd
, data
, howto
, relocation
);
977 bfd_install_relocation
980 bfd_reloc_status_type bfd_install_relocation
982 arelent *reloc_entry,
983 void *data, bfd_vma data_start,
984 asection *input_section,
985 char **error_message);
988 This looks remarkably like <<bfd_perform_relocation>>, except it
989 does not expect that the section contents have been filled in.
990 I.e., it's suitable for use when creating, rather than applying
993 For now, this function should be considered reserved for the
997 bfd_reloc_status_type
998 bfd_install_relocation (bfd
*abfd
,
999 arelent
*reloc_entry
,
1001 bfd_vma data_start_offset
,
1002 asection
*input_section
,
1003 char **error_message
)
1006 bfd_reloc_status_type flag
= bfd_reloc_ok
;
1007 bfd_size_type octets
;
1008 bfd_vma output_base
= 0;
1009 reloc_howto_type
*howto
= reloc_entry
->howto
;
1010 asection
*reloc_target_output_section
;
1014 symbol
= *(reloc_entry
->sym_ptr_ptr
);
1016 /* If there is a function supplied to handle this relocation type,
1017 call it. It'll return `bfd_reloc_continue' if further processing
1019 if (howto
&& howto
->special_function
)
1021 bfd_reloc_status_type cont
;
1023 /* Note - we do not call bfd_reloc_offset_in_range here as the
1024 reloc_entry->address field might actually be valid for the
1025 backend concerned. It is up to the special_function itself
1026 to call bfd_reloc_offset_in_range if needed. */
1027 cont
= howto
->special_function (abfd
, reloc_entry
, symbol
,
1028 /* XXX - Non-portable! */
1029 ((bfd_byte
*) data_start
1030 - data_start_offset
),
1031 input_section
, abfd
, error_message
);
1032 if (cont
!= bfd_reloc_continue
)
1036 if (howto
->install_addend
)
1037 relocation
= reloc_entry
->addend
;
1040 if (bfd_is_abs_section (symbol
->section
))
1041 return bfd_reloc_ok
;
1043 /* Work out which section the relocation is targeted at and the
1044 initial relocation command value. */
1046 /* Get symbol value. (Common symbols are special.) */
1047 if (bfd_is_com_section (symbol
->section
))
1050 relocation
= symbol
->value
;
1052 reloc_target_output_section
= symbol
->section
;
1054 /* Convert input-section-relative symbol value to absolute. */
1055 if (! howto
->partial_inplace
)
1058 output_base
= reloc_target_output_section
->vma
;
1060 /* If symbol addresses are in octets, convert to bytes. */
1061 if (bfd_get_flavour (abfd
) == bfd_target_elf_flavour
1062 && (symbol
->section
->flags
& SEC_ELF_OCTETS
))
1063 output_base
*= bfd_octets_per_byte (abfd
, input_section
);
1065 relocation
+= output_base
;
1067 /* Add in supplied addend. */
1068 relocation
+= reloc_entry
->addend
;
1070 /* Here the variable relocation holds the final address of the
1071 symbol we are relocating against, plus any addend. */
1073 if (howto
->pc_relative
)
1075 relocation
-= input_section
->vma
;
1077 if (howto
->pcrel_offset
&& howto
->partial_inplace
)
1078 relocation
-= reloc_entry
->address
;
1082 if (!howto
->partial_inplace
)
1084 reloc_entry
->addend
= relocation
;
1088 if (!howto
->install_addend
1089 && abfd
->xvec
->flavour
== bfd_target_coff_flavour
)
1091 /* This is just weird. We're subtracting out the original
1092 addend, so that for COFF the addend is ignored??? */
1093 relocation
-= reloc_entry
->addend
;
1094 /* FIXME: There should be no target specific code here... */
1095 if (strcmp (abfd
->xvec
->name
, "coff-z8k") != 0)
1096 reloc_entry
->addend
= 0;
1099 reloc_entry
->addend
= relocation
;
1101 /* Is the address of the relocation really within the section? */
1102 octets
= reloc_entry
->address
* bfd_octets_per_byte (abfd
, input_section
);
1103 if (!bfd_reloc_offset_in_range (howto
, abfd
, input_section
, octets
))
1104 return bfd_reloc_outofrange
;
1106 /* FIXME: This overflow checking is incomplete, because the value
1107 might have overflowed before we get here. For a correct check we
1108 need to compute the value in a size larger than bitsize, but we
1109 can't reasonably do that for a reloc the same size as a host
1111 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1112 flag
= bfd_check_overflow (howto
->complain_on_overflow
,
1115 bfd_arch_bits_per_address (abfd
),
1118 relocation
>>= (bfd_vma
) howto
->rightshift
;
1120 /* Shift everything up to where it's going to be used. */
1121 relocation
<<= (bfd_vma
) howto
->bitpos
;
1123 data
= (bfd_byte
*) data_start
+ (octets
- data_start_offset
);
1124 apply_reloc (abfd
, data
, howto
, relocation
);
1128 /* This relocation routine is used by some of the backend linkers.
1129 They do not construct asymbol or arelent structures, so there is no
1130 reason for them to use bfd_perform_relocation. Also,
1131 bfd_perform_relocation is so hacked up it is easier to write a new
1132 function than to try to deal with it.
1134 This routine does a final relocation. Whether it is useful for a
1135 relocatable link depends upon how the object format defines
1138 FIXME: This routine ignores any special_function in the HOWTO,
1139 since the existing special_function values have been written for
1140 bfd_perform_relocation.
1142 HOWTO is the reloc howto information.
1143 INPUT_BFD is the BFD which the reloc applies to.
1144 INPUT_SECTION is the section which the reloc applies to.
1145 CONTENTS is the contents of the section.
1146 ADDRESS is the address of the reloc within INPUT_SECTION.
1147 VALUE is the value of the symbol the reloc refers to.
1148 ADDEND is the addend of the reloc. */
1150 bfd_reloc_status_type
1151 _bfd_final_link_relocate (reloc_howto_type
*howto
,
1153 asection
*input_section
,
1160 bfd_size_type octets
= (address
1161 * bfd_octets_per_byte (input_bfd
, input_section
));
1163 /* Sanity check the address. */
1164 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, octets
))
1165 return bfd_reloc_outofrange
;
1167 /* This function assumes that we are dealing with a basic relocation
1168 against a symbol. We want to compute the value of the symbol to
1169 relocate to. This is just VALUE, the value of the symbol, plus
1170 ADDEND, any addend associated with the reloc. */
1171 relocation
= value
+ addend
;
1173 /* If the relocation is PC relative, we want to set RELOCATION to
1174 the distance between the symbol (currently in RELOCATION) and the
1175 location we are relocating. Some targets (e.g., i386-aout)
1176 arrange for the contents of the section to be the negative of the
1177 offset of the location within the section; for such targets
1178 pcrel_offset is FALSE. Other targets (e.g., ELF) simply leave
1179 the contents of the section as zero; for such targets
1180 pcrel_offset is TRUE. If pcrel_offset is FALSE we do not need to
1181 subtract out the offset of the location within the section (which
1182 is just ADDRESS). */
1183 if (howto
->pc_relative
)
1185 relocation
-= (input_section
->output_section
->vma
1186 + input_section
->output_offset
);
1187 if (howto
->pcrel_offset
)
1188 relocation
-= address
;
1191 return _bfd_relocate_contents (howto
, input_bfd
, relocation
,
1195 /* Relocate a given location using a given value and howto. */
1197 bfd_reloc_status_type
1198 _bfd_relocate_contents (reloc_howto_type
*howto
,
1204 bfd_reloc_status_type flag
;
1205 unsigned int rightshift
= howto
->rightshift
;
1206 unsigned int bitpos
= howto
->bitpos
;
1209 relocation
= -relocation
;
1211 /* Get the value we are going to relocate. */
1212 x
= read_reloc (input_bfd
, location
, howto
);
1214 /* Check for overflow. FIXME: We may drop bits during the addition
1215 which we don't check for. We must either check at every single
1216 operation, which would be tedious, or we must do the computations
1217 in a type larger than bfd_vma, which would be inefficient. */
1218 flag
= bfd_reloc_ok
;
1219 if (howto
->complain_on_overflow
!= complain_overflow_dont
)
1221 bfd_vma addrmask
, fieldmask
, signmask
, ss
;
1224 /* Get the values to be added together. For signed and unsigned
1225 relocations, we assume that all values should be truncated to
1226 the size of an address. For bitfields, all the bits matter.
1227 See also bfd_check_overflow. */
1228 fieldmask
= N_ONES (howto
->bitsize
);
1229 signmask
= ~fieldmask
;
1230 addrmask
= (N_ONES (bfd_arch_bits_per_address (input_bfd
))
1231 | (fieldmask
<< rightshift
));
1232 a
= (relocation
& addrmask
) >> rightshift
;
1233 b
= (x
& howto
->src_mask
& addrmask
) >> bitpos
;
1234 addrmask
>>= rightshift
;
1236 switch (howto
->complain_on_overflow
)
1238 case complain_overflow_signed
:
1239 /* If any sign bits are set, all sign bits must be set.
1240 That is, A must be a valid negative address after
1242 signmask
= ~(fieldmask
>> 1);
1245 case complain_overflow_bitfield
:
1246 /* Much like the signed check, but for a field one bit
1247 wider. We allow a bitfield to represent numbers in the
1248 range -2**n to 2**n-1, where n is the number of bits in the
1249 field. Note that when bfd_vma is 32 bits, a 32-bit reloc
1250 can't overflow, which is exactly what we want. */
1252 if (ss
!= 0 && ss
!= (addrmask
& signmask
))
1253 flag
= bfd_reloc_overflow
;
1255 /* We only need this next bit of code if the sign bit of B
1256 is below the sign bit of A. This would only happen if
1257 SRC_MASK had fewer bits than BITSIZE. Note that if
1258 SRC_MASK has more bits than BITSIZE, we can get into
1259 trouble; we would need to verify that B is in range, as
1260 we do for A above. */
1261 ss
= ((~howto
->src_mask
) >> 1) & howto
->src_mask
;
1264 /* Set all the bits above the sign bit. */
1267 /* Now we can do the addition. */
1270 /* See if the result has the correct sign. Bits above the
1271 sign bit are junk now; ignore them. If the sum is
1272 positive, make sure we did not have all negative inputs;
1273 if the sum is negative, make sure we did not have all
1274 positive inputs. The test below looks only at the sign
1275 bits, and it really just
1276 SIGN (A) == SIGN (B) && SIGN (A) != SIGN (SUM)
1278 We mask with addrmask here to explicitly allow an address
1279 wrap-around. The Linux kernel relies on it, and it is
1280 the only way to write assembler code which can run when
1281 loaded at a location 0x80000000 away from the location at
1282 which it is linked. */
1283 if (((~(a
^ b
)) & (a
^ sum
)) & signmask
& addrmask
)
1284 flag
= bfd_reloc_overflow
;
1287 case complain_overflow_unsigned
:
1288 /* Checking for an unsigned overflow is relatively easy:
1289 trim the addresses and add, and trim the result as well.
1290 Overflow is normally indicated when the result does not
1291 fit in the field. However, we also need to consider the
1292 case when, e.g., fieldmask is 0x7fffffff or smaller, an
1293 input is 0x80000000, and bfd_vma is only 32 bits; then we
1294 will get sum == 0, but there is an overflow, since the
1295 inputs did not fit in the field. Instead of doing a
1296 separate test, we can check for this by or-ing in the
1297 operands when testing for the sum overflowing its final
1299 sum
= (a
+ b
) & addrmask
;
1300 if ((a
| b
| sum
) & signmask
)
1301 flag
= bfd_reloc_overflow
;
1309 /* Put RELOCATION in the right bits. */
1310 relocation
>>= (bfd_vma
) rightshift
;
1311 relocation
<<= (bfd_vma
) bitpos
;
1313 /* Add RELOCATION to the right bits of X. */
1314 x
= ((x
& ~howto
->dst_mask
)
1315 | (((x
& howto
->src_mask
) + relocation
) & howto
->dst_mask
));
1317 /* Put the relocated value back in the object file. */
1318 write_reloc (input_bfd
, x
, location
, howto
);
1322 /* Clear a given location using a given howto, by applying a fixed relocation
1323 value and discarding any in-place addend. This is used for fixed-up
1324 relocations against discarded symbols, to make ignorable debug or unwind
1325 information more obvious. */
1327 bfd_reloc_status_type
1328 _bfd_clear_contents (reloc_howto_type
*howto
,
1330 asection
*input_section
,
1337 if (!bfd_reloc_offset_in_range (howto
, input_bfd
, input_section
, off
))
1338 return bfd_reloc_outofrange
;
1340 /* Get the value we are going to relocate. */
1341 location
= buf
+ off
;
1342 x
= read_reloc (input_bfd
, location
, howto
);
1344 /* Zero out the unwanted bits of X. */
1345 x
&= ~howto
->dst_mask
;
1347 /* For a range list, use 1 instead of 0 as placeholder. 0
1348 would terminate the list, hiding any later entries. */
1349 if (strcmp (bfd_section_name (input_section
), ".debug_ranges") == 0
1350 && (howto
->dst_mask
& 1) != 0)
1353 /* Put the relocated value back in the object file. */
1354 write_reloc (input_bfd
, x
, location
, howto
);
1355 return bfd_reloc_ok
;
1361 howto manager, , typedef arelent, Relocations
1366 When an application wants to create a relocation, but doesn't
1367 know what the target machine might call it, it can find out by
1368 using this bit of code.
1374 bfd_reloc_code_real_type
1377 The insides of a reloc code. The idea is that, eventually, there
1378 will be one enumerator for every type of relocation we ever do.
1379 Pass one of these values to <<bfd_reloc_type_lookup>>, and it'll
1380 return a howto pointer.
1382 This does mean that the application must determine the correct
1383 enumerator value; you can't get a howto pointer from a random set
1404 Basic absolute relocations of N bits.
1419 PC-relative relocations. Sometimes these are relative to the address
1420 of the relocation itself; sometimes they are relative to the start of
1421 the section containing the relocation. It depends on the specific target.
1428 Section relative relocations. Some targets need this for DWARF2.
1431 BFD_RELOC_32_GOT_PCREL
1433 BFD_RELOC_16_GOT_PCREL
1435 BFD_RELOC_8_GOT_PCREL
1441 BFD_RELOC_LO16_GOTOFF
1443 BFD_RELOC_HI16_GOTOFF
1445 BFD_RELOC_HI16_S_GOTOFF
1449 BFD_RELOC_64_PLT_PCREL
1451 BFD_RELOC_32_PLT_PCREL
1453 BFD_RELOC_24_PLT_PCREL
1455 BFD_RELOC_16_PLT_PCREL
1457 BFD_RELOC_8_PLT_PCREL
1465 BFD_RELOC_LO16_PLTOFF
1467 BFD_RELOC_HI16_PLTOFF
1469 BFD_RELOC_HI16_S_PLTOFF
1483 BFD_RELOC_68K_GLOB_DAT
1485 BFD_RELOC_68K_JMP_SLOT
1487 BFD_RELOC_68K_RELATIVE
1489 BFD_RELOC_68K_TLS_GD32
1491 BFD_RELOC_68K_TLS_GD16
1493 BFD_RELOC_68K_TLS_GD8
1495 BFD_RELOC_68K_TLS_LDM32
1497 BFD_RELOC_68K_TLS_LDM16
1499 BFD_RELOC_68K_TLS_LDM8
1501 BFD_RELOC_68K_TLS_LDO32
1503 BFD_RELOC_68K_TLS_LDO16
1505 BFD_RELOC_68K_TLS_LDO8
1507 BFD_RELOC_68K_TLS_IE32
1509 BFD_RELOC_68K_TLS_IE16
1511 BFD_RELOC_68K_TLS_IE8
1513 BFD_RELOC_68K_TLS_LE32
1515 BFD_RELOC_68K_TLS_LE16
1517 BFD_RELOC_68K_TLS_LE8
1519 Relocations used by 68K ELF.
1522 BFD_RELOC_32_BASEREL
1524 BFD_RELOC_16_BASEREL
1526 BFD_RELOC_LO16_BASEREL
1528 BFD_RELOC_HI16_BASEREL
1530 BFD_RELOC_HI16_S_BASEREL
1536 Linkage-table relative.
1541 Absolute 8-bit relocation, but used to form an address like 0xFFnn.
1544 BFD_RELOC_32_PCREL_S2
1546 BFD_RELOC_16_PCREL_S2
1548 BFD_RELOC_23_PCREL_S2
1550 These PC-relative relocations are stored as word displacements --
1551 i.e., byte displacements shifted right two bits. The 30-bit word
1552 displacement (<<32_PCREL_S2>> -- 32 bits, shifted 2) is used on the
1553 SPARC. (SPARC tools generally refer to this as <<WDISP30>>.) The
1554 signed 16-bit displacement is used on the MIPS, and the 23-bit
1555 displacement is used on the Alpha.
1562 High 22 bits and low 10 bits of 32-bit value, placed into lower bits of
1563 the target word. These are used on the SPARC.
1570 For systems that allocate a Global Pointer register, these are
1571 displacements off that register. These relocation types are
1572 handled specially, because the value the register will have is
1573 decided relatively late.
1578 BFD_RELOC_SPARC_WDISP22
1584 BFD_RELOC_SPARC_GOT10
1586 BFD_RELOC_SPARC_GOT13
1588 BFD_RELOC_SPARC_GOT22
1590 BFD_RELOC_SPARC_PC10
1592 BFD_RELOC_SPARC_PC22
1594 BFD_RELOC_SPARC_WPLT30
1596 BFD_RELOC_SPARC_COPY
1598 BFD_RELOC_SPARC_GLOB_DAT
1600 BFD_RELOC_SPARC_JMP_SLOT
1602 BFD_RELOC_SPARC_RELATIVE
1604 BFD_RELOC_SPARC_UA16
1606 BFD_RELOC_SPARC_UA32
1608 BFD_RELOC_SPARC_UA64
1610 BFD_RELOC_SPARC_GOTDATA_HIX22
1612 BFD_RELOC_SPARC_GOTDATA_LOX10
1614 BFD_RELOC_SPARC_GOTDATA_OP_HIX22
1616 BFD_RELOC_SPARC_GOTDATA_OP_LOX10
1618 BFD_RELOC_SPARC_GOTDATA_OP
1620 BFD_RELOC_SPARC_JMP_IREL
1622 BFD_RELOC_SPARC_IRELATIVE
1624 SPARC ELF relocations. There is probably some overlap with other
1625 relocation types already defined.
1628 BFD_RELOC_SPARC_BASE13
1630 BFD_RELOC_SPARC_BASE22
1632 I think these are specific to SPARC a.out (e.g., Sun 4).
1642 BFD_RELOC_SPARC_OLO10
1644 BFD_RELOC_SPARC_HH22
1646 BFD_RELOC_SPARC_HM10
1648 BFD_RELOC_SPARC_LM22
1650 BFD_RELOC_SPARC_PC_HH22
1652 BFD_RELOC_SPARC_PC_HM10
1654 BFD_RELOC_SPARC_PC_LM22
1656 BFD_RELOC_SPARC_WDISP16
1658 BFD_RELOC_SPARC_WDISP19
1666 BFD_RELOC_SPARC_DISP64
1669 BFD_RELOC_SPARC_PLT32
1671 BFD_RELOC_SPARC_PLT64
1673 BFD_RELOC_SPARC_HIX22
1675 BFD_RELOC_SPARC_LOX10
1683 BFD_RELOC_SPARC_REGISTER
1687 BFD_RELOC_SPARC_SIZE32
1689 BFD_RELOC_SPARC_SIZE64
1691 BFD_RELOC_SPARC_WDISP10
1696 BFD_RELOC_SPARC_REV32
1698 SPARC little endian relocation
1700 BFD_RELOC_SPARC_TLS_GD_HI22
1702 BFD_RELOC_SPARC_TLS_GD_LO10
1704 BFD_RELOC_SPARC_TLS_GD_ADD
1706 BFD_RELOC_SPARC_TLS_GD_CALL
1708 BFD_RELOC_SPARC_TLS_LDM_HI22
1710 BFD_RELOC_SPARC_TLS_LDM_LO10
1712 BFD_RELOC_SPARC_TLS_LDM_ADD
1714 BFD_RELOC_SPARC_TLS_LDM_CALL
1716 BFD_RELOC_SPARC_TLS_LDO_HIX22
1718 BFD_RELOC_SPARC_TLS_LDO_LOX10
1720 BFD_RELOC_SPARC_TLS_LDO_ADD
1722 BFD_RELOC_SPARC_TLS_IE_HI22
1724 BFD_RELOC_SPARC_TLS_IE_LO10
1726 BFD_RELOC_SPARC_TLS_IE_LD
1728 BFD_RELOC_SPARC_TLS_IE_LDX
1730 BFD_RELOC_SPARC_TLS_IE_ADD
1732 BFD_RELOC_SPARC_TLS_LE_HIX22
1734 BFD_RELOC_SPARC_TLS_LE_LOX10
1736 BFD_RELOC_SPARC_TLS_DTPMOD32
1738 BFD_RELOC_SPARC_TLS_DTPMOD64
1740 BFD_RELOC_SPARC_TLS_DTPOFF32
1742 BFD_RELOC_SPARC_TLS_DTPOFF64
1744 BFD_RELOC_SPARC_TLS_TPOFF32
1746 BFD_RELOC_SPARC_TLS_TPOFF64
1748 SPARC TLS relocations
1757 BFD_RELOC_SPU_IMM10W
1761 BFD_RELOC_SPU_IMM16W
1765 BFD_RELOC_SPU_PCREL9a
1767 BFD_RELOC_SPU_PCREL9b
1769 BFD_RELOC_SPU_PCREL16
1779 BFD_RELOC_SPU_ADD_PIC
1784 BFD_RELOC_ALPHA_GPDISP_HI16
1786 Alpha ECOFF and ELF relocations. Some of these treat the symbol or
1787 "addend" in some special way.
1788 For GPDISP_HI16 ("gpdisp") relocations, the symbol is ignored when
1789 writing; when reading, it will be the absolute section symbol. The
1790 addend is the displacement in bytes of the "lda" instruction from
1791 the "ldah" instruction (which is at the address of this reloc).
1793 BFD_RELOC_ALPHA_GPDISP_LO16
1795 For GPDISP_LO16 ("ignore") relocations, the symbol is handled as
1796 with GPDISP_HI16 relocs. The addend is ignored when writing the
1797 relocations out, and is filled in with the file's GP value on
1798 reading, for convenience.
1801 BFD_RELOC_ALPHA_GPDISP
1803 The ELF GPDISP relocation is exactly the same as the GPDISP_HI16
1804 relocation except that there is no accompanying GPDISP_LO16
1808 BFD_RELOC_ALPHA_LITERAL
1810 BFD_RELOC_ALPHA_ELF_LITERAL
1812 BFD_RELOC_ALPHA_LITUSE
1814 The Alpha LITERAL/LITUSE relocs are produced by a symbol reference;
1815 the assembler turns it into a LDQ instruction to load the address of
1816 the symbol, and then fills in a register in the real instruction.
1818 The LITERAL reloc, at the LDQ instruction, refers to the .lita
1819 section symbol. The addend is ignored when writing, but is filled
1820 in with the file's GP value on reading, for convenience, as with the
1823 The ELF_LITERAL reloc is somewhere between 16_GOTOFF and GPDISP_LO16.
1824 It should refer to the symbol to be referenced, as with 16_GOTOFF,
1825 but it generates output not based on the position within the .got
1826 section, but relative to the GP value chosen for the file during the
1829 The LITUSE reloc, on the instruction using the loaded address, gives
1830 information to the linker that it might be able to use to optimize
1831 away some literal section references. The symbol is ignored (read
1832 as the absolute section symbol), and the "addend" indicates the type
1833 of instruction using the register:
1834 1 - "memory" fmt insn
1835 2 - byte-manipulation (byte offset reg)
1836 3 - jsr (target of branch)
1839 BFD_RELOC_ALPHA_HINT
1841 The HINT relocation indicates a value that should be filled into the
1842 "hint" field of a jmp/jsr/ret instruction, for possible branch-
1843 prediction logic which may be provided on some processors.
1846 BFD_RELOC_ALPHA_LINKAGE
1848 The LINKAGE relocation outputs a linkage pair in the object file,
1849 which is filled by the linker.
1852 BFD_RELOC_ALPHA_CODEADDR
1854 The CODEADDR relocation outputs a STO_CA in the object file,
1855 which is filled by the linker.
1858 BFD_RELOC_ALPHA_GPREL_HI16
1860 BFD_RELOC_ALPHA_GPREL_LO16
1862 The GPREL_HI/LO relocations together form a 32-bit offset from the
1866 BFD_RELOC_ALPHA_BRSGP
1868 Like BFD_RELOC_23_PCREL_S2, except that the source and target must
1869 share a common GP, and the target address is adjusted for
1870 STO_ALPHA_STD_GPLOAD.
1875 The NOP relocation outputs a NOP if the longword displacement
1876 between two procedure entry points is < 2^21.
1881 The BSR relocation outputs a BSR if the longword displacement
1882 between two procedure entry points is < 2^21.
1887 The LDA relocation outputs a LDA if the longword displacement
1888 between two procedure entry points is < 2^16.
1893 The BOH relocation outputs a BSR if the longword displacement
1894 between two procedure entry points is < 2^21, or else a hint.
1897 BFD_RELOC_ALPHA_TLSGD
1899 BFD_RELOC_ALPHA_TLSLDM
1901 BFD_RELOC_ALPHA_DTPMOD64
1903 BFD_RELOC_ALPHA_GOTDTPREL16
1905 BFD_RELOC_ALPHA_DTPREL64
1907 BFD_RELOC_ALPHA_DTPREL_HI16
1909 BFD_RELOC_ALPHA_DTPREL_LO16
1911 BFD_RELOC_ALPHA_DTPREL16
1913 BFD_RELOC_ALPHA_GOTTPREL16
1915 BFD_RELOC_ALPHA_TPREL64
1917 BFD_RELOC_ALPHA_TPREL_HI16
1919 BFD_RELOC_ALPHA_TPREL_LO16
1921 BFD_RELOC_ALPHA_TPREL16
1923 Alpha thread-local storage relocations.
1928 BFD_RELOC_MICROMIPS_JMP
1930 The MIPS jump instruction.
1933 BFD_RELOC_MIPS16_JMP
1935 The MIPS16 jump instruction.
1938 BFD_RELOC_MIPS16_GPREL
1940 MIPS16 GP relative reloc.
1945 High 16 bits of 32-bit value; simple reloc.
1950 High 16 bits of 32-bit value but the low 16 bits will be sign
1951 extended and added to form the final result. If the low 16
1952 bits form a negative number, we need to add one to the high value
1953 to compensate for the borrow when the low bits are added.
1961 BFD_RELOC_HI16_PCREL
1963 High 16 bits of 32-bit pc-relative value
1965 BFD_RELOC_HI16_S_PCREL
1967 High 16 bits of 32-bit pc-relative value, adjusted
1969 BFD_RELOC_LO16_PCREL
1971 Low 16 bits of pc-relative value
1974 BFD_RELOC_MIPS16_GOT16
1976 BFD_RELOC_MIPS16_CALL16
1978 Equivalent of BFD_RELOC_MIPS_*, but with the MIPS16 layout of
1979 16-bit immediate fields
1981 BFD_RELOC_MIPS16_HI16
1983 MIPS16 high 16 bits of 32-bit value.
1985 BFD_RELOC_MIPS16_HI16_S
1987 MIPS16 high 16 bits of 32-bit value but the low 16 bits will be sign
1988 extended and added to form the final result. If the low 16
1989 bits form a negative number, we need to add one to the high value
1990 to compensate for the borrow when the low bits are added.
1992 BFD_RELOC_MIPS16_LO16
1997 BFD_RELOC_MIPS16_TLS_GD
1999 BFD_RELOC_MIPS16_TLS_LDM
2001 BFD_RELOC_MIPS16_TLS_DTPREL_HI16
2003 BFD_RELOC_MIPS16_TLS_DTPREL_LO16
2005 BFD_RELOC_MIPS16_TLS_GOTTPREL
2007 BFD_RELOC_MIPS16_TLS_TPREL_HI16
2009 BFD_RELOC_MIPS16_TLS_TPREL_LO16
2011 MIPS16 TLS relocations
2014 BFD_RELOC_MIPS_LITERAL
2016 BFD_RELOC_MICROMIPS_LITERAL
2018 Relocation against a MIPS literal section.
2021 BFD_RELOC_MICROMIPS_7_PCREL_S1
2023 BFD_RELOC_MICROMIPS_10_PCREL_S1
2025 BFD_RELOC_MICROMIPS_16_PCREL_S1
2027 microMIPS PC-relative relocations.
2030 BFD_RELOC_MIPS16_16_PCREL_S1
2032 MIPS16 PC-relative relocation.
2035 BFD_RELOC_MIPS_21_PCREL_S2
2037 BFD_RELOC_MIPS_26_PCREL_S2
2039 BFD_RELOC_MIPS_18_PCREL_S3
2041 BFD_RELOC_MIPS_19_PCREL_S2
2043 MIPS PC-relative relocations.
2046 BFD_RELOC_MICROMIPS_GPREL16
2048 BFD_RELOC_MICROMIPS_HI16
2050 BFD_RELOC_MICROMIPS_HI16_S
2052 BFD_RELOC_MICROMIPS_LO16
2054 microMIPS versions of generic BFD relocs.
2057 BFD_RELOC_MIPS_GOT16
2059 BFD_RELOC_MICROMIPS_GOT16
2061 BFD_RELOC_MIPS_CALL16
2063 BFD_RELOC_MICROMIPS_CALL16
2065 BFD_RELOC_MIPS_GOT_HI16
2067 BFD_RELOC_MICROMIPS_GOT_HI16
2069 BFD_RELOC_MIPS_GOT_LO16
2071 BFD_RELOC_MICROMIPS_GOT_LO16
2073 BFD_RELOC_MIPS_CALL_HI16
2075 BFD_RELOC_MICROMIPS_CALL_HI16
2077 BFD_RELOC_MIPS_CALL_LO16
2079 BFD_RELOC_MICROMIPS_CALL_LO16
2083 BFD_RELOC_MICROMIPS_SUB
2085 BFD_RELOC_MIPS_GOT_PAGE
2087 BFD_RELOC_MICROMIPS_GOT_PAGE
2089 BFD_RELOC_MIPS_GOT_OFST
2091 BFD_RELOC_MICROMIPS_GOT_OFST
2093 BFD_RELOC_MIPS_GOT_DISP
2095 BFD_RELOC_MICROMIPS_GOT_DISP
2097 BFD_RELOC_MIPS_SHIFT5
2099 BFD_RELOC_MIPS_SHIFT6
2101 BFD_RELOC_MIPS_INSERT_A
2103 BFD_RELOC_MIPS_INSERT_B
2105 BFD_RELOC_MIPS_DELETE
2107 BFD_RELOC_MIPS_HIGHEST
2109 BFD_RELOC_MICROMIPS_HIGHEST
2111 BFD_RELOC_MIPS_HIGHER
2113 BFD_RELOC_MICROMIPS_HIGHER
2115 BFD_RELOC_MIPS_SCN_DISP
2117 BFD_RELOC_MICROMIPS_SCN_DISP
2121 BFD_RELOC_MIPS_RELGOT
2125 BFD_RELOC_MICROMIPS_JALR
2127 BFD_RELOC_MIPS_TLS_DTPMOD32
2129 BFD_RELOC_MIPS_TLS_DTPREL32
2131 BFD_RELOC_MIPS_TLS_DTPMOD64
2133 BFD_RELOC_MIPS_TLS_DTPREL64
2135 BFD_RELOC_MIPS_TLS_GD
2137 BFD_RELOC_MICROMIPS_TLS_GD
2139 BFD_RELOC_MIPS_TLS_LDM
2141 BFD_RELOC_MICROMIPS_TLS_LDM
2143 BFD_RELOC_MIPS_TLS_DTPREL_HI16
2145 BFD_RELOC_MICROMIPS_TLS_DTPREL_HI16
2147 BFD_RELOC_MIPS_TLS_DTPREL_LO16
2149 BFD_RELOC_MICROMIPS_TLS_DTPREL_LO16
2151 BFD_RELOC_MIPS_TLS_GOTTPREL
2153 BFD_RELOC_MICROMIPS_TLS_GOTTPREL
2155 BFD_RELOC_MIPS_TLS_TPREL32
2157 BFD_RELOC_MIPS_TLS_TPREL64
2159 BFD_RELOC_MIPS_TLS_TPREL_HI16
2161 BFD_RELOC_MICROMIPS_TLS_TPREL_HI16
2163 BFD_RELOC_MIPS_TLS_TPREL_LO16
2165 BFD_RELOC_MICROMIPS_TLS_TPREL_LO16
2169 MIPS ELF relocations.
2175 BFD_RELOC_MIPS_JUMP_SLOT
2177 MIPS ELF relocations (VxWorks and PLT extensions).
2181 BFD_RELOC_MOXIE_10_PCREL
2183 Moxie ELF relocations.
2195 BFD_RELOC_FT32_RELAX
2203 BFD_RELOC_FT32_DIFF32
2205 FT32 ELF relocations.
2209 BFD_RELOC_FRV_LABEL16
2211 BFD_RELOC_FRV_LABEL24
2217 BFD_RELOC_FRV_GPREL12
2219 BFD_RELOC_FRV_GPRELU12
2221 BFD_RELOC_FRV_GPREL32
2223 BFD_RELOC_FRV_GPRELHI
2225 BFD_RELOC_FRV_GPRELLO
2233 BFD_RELOC_FRV_FUNCDESC
2235 BFD_RELOC_FRV_FUNCDESC_GOT12
2237 BFD_RELOC_FRV_FUNCDESC_GOTHI
2239 BFD_RELOC_FRV_FUNCDESC_GOTLO
2241 BFD_RELOC_FRV_FUNCDESC_VALUE
2243 BFD_RELOC_FRV_FUNCDESC_GOTOFF12
2245 BFD_RELOC_FRV_FUNCDESC_GOTOFFHI
2247 BFD_RELOC_FRV_FUNCDESC_GOTOFFLO
2249 BFD_RELOC_FRV_GOTOFF12
2251 BFD_RELOC_FRV_GOTOFFHI
2253 BFD_RELOC_FRV_GOTOFFLO
2255 BFD_RELOC_FRV_GETTLSOFF
2257 BFD_RELOC_FRV_TLSDESC_VALUE
2259 BFD_RELOC_FRV_GOTTLSDESC12
2261 BFD_RELOC_FRV_GOTTLSDESCHI
2263 BFD_RELOC_FRV_GOTTLSDESCLO
2265 BFD_RELOC_FRV_TLSMOFF12
2267 BFD_RELOC_FRV_TLSMOFFHI
2269 BFD_RELOC_FRV_TLSMOFFLO
2271 BFD_RELOC_FRV_GOTTLSOFF12
2273 BFD_RELOC_FRV_GOTTLSOFFHI
2275 BFD_RELOC_FRV_GOTTLSOFFLO
2277 BFD_RELOC_FRV_TLSOFF
2279 BFD_RELOC_FRV_TLSDESC_RELAX
2281 BFD_RELOC_FRV_GETTLSOFF_RELAX
2283 BFD_RELOC_FRV_TLSOFF_RELAX
2285 BFD_RELOC_FRV_TLSMOFF
2287 Fujitsu Frv Relocations.
2291 BFD_RELOC_MN10300_GOTOFF24
2293 This is a 24bit GOT-relative reloc for the mn10300.
2295 BFD_RELOC_MN10300_GOT32
2297 This is a 32bit GOT-relative reloc for the mn10300, offset by two bytes
2300 BFD_RELOC_MN10300_GOT24
2302 This is a 24bit GOT-relative reloc for the mn10300, offset by two bytes
2305 BFD_RELOC_MN10300_GOT16
2307 This is a 16bit GOT-relative reloc for the mn10300, offset by two bytes
2310 BFD_RELOC_MN10300_COPY
2312 Copy symbol at runtime.
2314 BFD_RELOC_MN10300_GLOB_DAT
2318 BFD_RELOC_MN10300_JMP_SLOT
2322 BFD_RELOC_MN10300_RELATIVE
2324 Adjust by program base.
2326 BFD_RELOC_MN10300_SYM_DIFF
2328 Together with another reloc targeted at the same location,
2329 allows for a value that is the difference of two symbols
2330 in the same section.
2332 BFD_RELOC_MN10300_ALIGN
2334 The addend of this reloc is an alignment power that must
2335 be honoured at the offset's location, regardless of linker
2338 BFD_RELOC_MN10300_TLS_GD
2340 BFD_RELOC_MN10300_TLS_LD
2342 BFD_RELOC_MN10300_TLS_LDO
2344 BFD_RELOC_MN10300_TLS_GOTIE
2346 BFD_RELOC_MN10300_TLS_IE
2348 BFD_RELOC_MN10300_TLS_LE
2350 BFD_RELOC_MN10300_TLS_DTPMOD
2352 BFD_RELOC_MN10300_TLS_DTPOFF
2354 BFD_RELOC_MN10300_TLS_TPOFF
2356 Various TLS-related relocations.
2358 BFD_RELOC_MN10300_32_PCREL
2360 This is a 32bit pcrel reloc for the mn10300, offset by two bytes in the
2363 BFD_RELOC_MN10300_16_PCREL
2365 This is a 16bit pcrel reloc for the mn10300, offset by two bytes in the
2376 BFD_RELOC_386_GLOB_DAT
2378 BFD_RELOC_386_JUMP_SLOT
2380 BFD_RELOC_386_RELATIVE
2382 BFD_RELOC_386_GOTOFF
2386 BFD_RELOC_386_TLS_TPOFF
2388 BFD_RELOC_386_TLS_IE
2390 BFD_RELOC_386_TLS_GOTIE
2392 BFD_RELOC_386_TLS_LE
2394 BFD_RELOC_386_TLS_GD
2396 BFD_RELOC_386_TLS_LDM
2398 BFD_RELOC_386_TLS_LDO_32
2400 BFD_RELOC_386_TLS_IE_32
2402 BFD_RELOC_386_TLS_LE_32
2404 BFD_RELOC_386_TLS_DTPMOD32
2406 BFD_RELOC_386_TLS_DTPOFF32
2408 BFD_RELOC_386_TLS_TPOFF32
2410 BFD_RELOC_386_TLS_GOTDESC
2412 BFD_RELOC_386_TLS_DESC_CALL
2414 BFD_RELOC_386_TLS_DESC
2416 BFD_RELOC_386_IRELATIVE
2418 BFD_RELOC_386_GOT32X
2420 i386/elf relocations
2423 BFD_RELOC_X86_64_GOT32
2425 BFD_RELOC_X86_64_PLT32
2427 BFD_RELOC_X86_64_COPY
2429 BFD_RELOC_X86_64_GLOB_DAT
2431 BFD_RELOC_X86_64_JUMP_SLOT
2433 BFD_RELOC_X86_64_RELATIVE
2435 BFD_RELOC_X86_64_GOTPCREL
2437 BFD_RELOC_X86_64_32S
2439 BFD_RELOC_X86_64_DTPMOD64
2441 BFD_RELOC_X86_64_DTPOFF64
2443 BFD_RELOC_X86_64_TPOFF64
2445 BFD_RELOC_X86_64_TLSGD
2447 BFD_RELOC_X86_64_TLSLD
2449 BFD_RELOC_X86_64_DTPOFF32
2451 BFD_RELOC_X86_64_GOTTPOFF
2453 BFD_RELOC_X86_64_TPOFF32
2455 BFD_RELOC_X86_64_GOTOFF64
2457 BFD_RELOC_X86_64_GOTPC32
2459 BFD_RELOC_X86_64_GOT64
2461 BFD_RELOC_X86_64_GOTPCREL64
2463 BFD_RELOC_X86_64_GOTPC64
2465 BFD_RELOC_X86_64_GOTPLT64
2467 BFD_RELOC_X86_64_PLTOFF64
2469 BFD_RELOC_X86_64_GOTPC32_TLSDESC
2471 BFD_RELOC_X86_64_TLSDESC_CALL
2473 BFD_RELOC_X86_64_TLSDESC
2475 BFD_RELOC_X86_64_IRELATIVE
2477 BFD_RELOC_X86_64_PC32_BND
2479 BFD_RELOC_X86_64_PLT32_BND
2481 BFD_RELOC_X86_64_GOTPCRELX
2483 BFD_RELOC_X86_64_REX_GOTPCRELX
2485 x86-64/elf relocations
2488 BFD_RELOC_NS32K_IMM_8
2490 BFD_RELOC_NS32K_IMM_16
2492 BFD_RELOC_NS32K_IMM_32
2494 BFD_RELOC_NS32K_IMM_8_PCREL
2496 BFD_RELOC_NS32K_IMM_16_PCREL
2498 BFD_RELOC_NS32K_IMM_32_PCREL
2500 BFD_RELOC_NS32K_DISP_8
2502 BFD_RELOC_NS32K_DISP_16
2504 BFD_RELOC_NS32K_DISP_32
2506 BFD_RELOC_NS32K_DISP_8_PCREL
2508 BFD_RELOC_NS32K_DISP_16_PCREL
2510 BFD_RELOC_NS32K_DISP_32_PCREL
2515 BFD_RELOC_PDP11_DISP_8_PCREL
2517 BFD_RELOC_PDP11_DISP_6_PCREL
2522 BFD_RELOC_PJ_CODE_HI16
2524 BFD_RELOC_PJ_CODE_LO16
2526 BFD_RELOC_PJ_CODE_DIR16
2528 BFD_RELOC_PJ_CODE_DIR32
2530 BFD_RELOC_PJ_CODE_REL16
2532 BFD_RELOC_PJ_CODE_REL32
2534 Picojava relocs. Not all of these appear in object files.
2543 BFD_RELOC_PPC_TOC16_LO
2545 BFD_RELOC_PPC_TOC16_HI
2549 BFD_RELOC_PPC_B16_BRTAKEN
2551 BFD_RELOC_PPC_B16_BRNTAKEN
2555 BFD_RELOC_PPC_BA16_BRTAKEN
2557 BFD_RELOC_PPC_BA16_BRNTAKEN
2561 BFD_RELOC_PPC_GLOB_DAT
2563 BFD_RELOC_PPC_JMP_SLOT
2565 BFD_RELOC_PPC_RELATIVE
2567 BFD_RELOC_PPC_LOCAL24PC
2569 BFD_RELOC_PPC_EMB_NADDR32
2571 BFD_RELOC_PPC_EMB_NADDR16
2573 BFD_RELOC_PPC_EMB_NADDR16_LO
2575 BFD_RELOC_PPC_EMB_NADDR16_HI
2577 BFD_RELOC_PPC_EMB_NADDR16_HA
2579 BFD_RELOC_PPC_EMB_SDAI16
2581 BFD_RELOC_PPC_EMB_SDA2I16
2583 BFD_RELOC_PPC_EMB_SDA2REL
2585 BFD_RELOC_PPC_EMB_SDA21
2587 BFD_RELOC_PPC_EMB_MRKREF
2589 BFD_RELOC_PPC_EMB_RELSEC16
2591 BFD_RELOC_PPC_EMB_RELST_LO
2593 BFD_RELOC_PPC_EMB_RELST_HI
2595 BFD_RELOC_PPC_EMB_RELST_HA
2597 BFD_RELOC_PPC_EMB_BIT_FLD
2599 BFD_RELOC_PPC_EMB_RELSDA
2601 BFD_RELOC_PPC_VLE_REL8
2603 BFD_RELOC_PPC_VLE_REL15
2605 BFD_RELOC_PPC_VLE_REL24
2607 BFD_RELOC_PPC_VLE_LO16A
2609 BFD_RELOC_PPC_VLE_LO16D
2611 BFD_RELOC_PPC_VLE_HI16A
2613 BFD_RELOC_PPC_VLE_HI16D
2615 BFD_RELOC_PPC_VLE_HA16A
2617 BFD_RELOC_PPC_VLE_HA16D
2619 BFD_RELOC_PPC_VLE_SDA21
2621 BFD_RELOC_PPC_VLE_SDA21_LO
2623 BFD_RELOC_PPC_VLE_SDAREL_LO16A
2625 BFD_RELOC_PPC_VLE_SDAREL_LO16D
2627 BFD_RELOC_PPC_VLE_SDAREL_HI16A
2629 BFD_RELOC_PPC_VLE_SDAREL_HI16D
2631 BFD_RELOC_PPC_VLE_SDAREL_HA16A
2633 BFD_RELOC_PPC_VLE_SDAREL_HA16D
2635 BFD_RELOC_PPC_16DX_HA
2637 BFD_RELOC_PPC_REL16DX_HA
2641 BFD_RELOC_PPC64_HIGHER
2643 BFD_RELOC_PPC64_HIGHER_S
2645 BFD_RELOC_PPC64_HIGHEST
2647 BFD_RELOC_PPC64_HIGHEST_S
2649 BFD_RELOC_PPC64_TOC16_LO
2651 BFD_RELOC_PPC64_TOC16_HI
2653 BFD_RELOC_PPC64_TOC16_HA
2657 BFD_RELOC_PPC64_PLTGOT16
2659 BFD_RELOC_PPC64_PLTGOT16_LO
2661 BFD_RELOC_PPC64_PLTGOT16_HI
2663 BFD_RELOC_PPC64_PLTGOT16_HA
2665 BFD_RELOC_PPC64_ADDR16_DS
2667 BFD_RELOC_PPC64_ADDR16_LO_DS
2669 BFD_RELOC_PPC64_GOT16_DS
2671 BFD_RELOC_PPC64_GOT16_LO_DS
2673 BFD_RELOC_PPC64_PLT16_LO_DS
2675 BFD_RELOC_PPC64_SECTOFF_DS
2677 BFD_RELOC_PPC64_SECTOFF_LO_DS
2679 BFD_RELOC_PPC64_TOC16_DS
2681 BFD_RELOC_PPC64_TOC16_LO_DS
2683 BFD_RELOC_PPC64_PLTGOT16_DS
2685 BFD_RELOC_PPC64_PLTGOT16_LO_DS
2687 BFD_RELOC_PPC64_ADDR16_HIGH
2689 BFD_RELOC_PPC64_ADDR16_HIGHA
2691 BFD_RELOC_PPC64_REL16_HIGH
2693 BFD_RELOC_PPC64_REL16_HIGHA
2695 BFD_RELOC_PPC64_REL16_HIGHER
2697 BFD_RELOC_PPC64_REL16_HIGHERA
2699 BFD_RELOC_PPC64_REL16_HIGHEST
2701 BFD_RELOC_PPC64_REL16_HIGHESTA
2703 BFD_RELOC_PPC64_ADDR64_LOCAL
2705 BFD_RELOC_PPC64_ENTRY
2707 BFD_RELOC_PPC64_REL24_NOTOC
2709 BFD_RELOC_PPC64_REL24_P9NOTOC
2713 BFD_RELOC_PPC64_D34_LO
2715 BFD_RELOC_PPC64_D34_HI30
2717 BFD_RELOC_PPC64_D34_HA30
2719 BFD_RELOC_PPC64_PCREL34
2721 BFD_RELOC_PPC64_GOT_PCREL34
2723 BFD_RELOC_PPC64_PLT_PCREL34
2725 BFD_RELOC_PPC64_ADDR16_HIGHER34
2727 BFD_RELOC_PPC64_ADDR16_HIGHERA34
2729 BFD_RELOC_PPC64_ADDR16_HIGHEST34
2731 BFD_RELOC_PPC64_ADDR16_HIGHESTA34
2733 BFD_RELOC_PPC64_REL16_HIGHER34
2735 BFD_RELOC_PPC64_REL16_HIGHERA34
2737 BFD_RELOC_PPC64_REL16_HIGHEST34
2739 BFD_RELOC_PPC64_REL16_HIGHESTA34
2743 BFD_RELOC_PPC64_PCREL28
2745 Power(rs6000) and PowerPC relocations.
2762 BFD_RELOC_PPC_DTPMOD
2764 BFD_RELOC_PPC_TPREL16
2766 BFD_RELOC_PPC_TPREL16_LO
2768 BFD_RELOC_PPC_TPREL16_HI
2770 BFD_RELOC_PPC_TPREL16_HA
2774 BFD_RELOC_PPC_DTPREL16
2776 BFD_RELOC_PPC_DTPREL16_LO
2778 BFD_RELOC_PPC_DTPREL16_HI
2780 BFD_RELOC_PPC_DTPREL16_HA
2782 BFD_RELOC_PPC_DTPREL
2784 BFD_RELOC_PPC_GOT_TLSGD16
2786 BFD_RELOC_PPC_GOT_TLSGD16_LO
2788 BFD_RELOC_PPC_GOT_TLSGD16_HI
2790 BFD_RELOC_PPC_GOT_TLSGD16_HA
2792 BFD_RELOC_PPC_GOT_TLSLD16
2794 BFD_RELOC_PPC_GOT_TLSLD16_LO
2796 BFD_RELOC_PPC_GOT_TLSLD16_HI
2798 BFD_RELOC_PPC_GOT_TLSLD16_HA
2800 BFD_RELOC_PPC_GOT_TPREL16
2802 BFD_RELOC_PPC_GOT_TPREL16_LO
2804 BFD_RELOC_PPC_GOT_TPREL16_HI
2806 BFD_RELOC_PPC_GOT_TPREL16_HA
2808 BFD_RELOC_PPC_GOT_DTPREL16
2810 BFD_RELOC_PPC_GOT_DTPREL16_LO
2812 BFD_RELOC_PPC_GOT_DTPREL16_HI
2814 BFD_RELOC_PPC_GOT_DTPREL16_HA
2816 BFD_RELOC_PPC64_TLSGD
2818 BFD_RELOC_PPC64_TLSLD
2820 BFD_RELOC_PPC64_TLSLE
2822 BFD_RELOC_PPC64_TLSIE
2824 BFD_RELOC_PPC64_TLSM
2826 BFD_RELOC_PPC64_TLSML
2828 BFD_RELOC_PPC64_TPREL16_DS
2830 BFD_RELOC_PPC64_TPREL16_LO_DS
2832 BFD_RELOC_PPC64_TPREL16_HIGH
2834 BFD_RELOC_PPC64_TPREL16_HIGHA
2836 BFD_RELOC_PPC64_TPREL16_HIGHER
2838 BFD_RELOC_PPC64_TPREL16_HIGHERA
2840 BFD_RELOC_PPC64_TPREL16_HIGHEST
2842 BFD_RELOC_PPC64_TPREL16_HIGHESTA
2844 BFD_RELOC_PPC64_DTPREL16_DS
2846 BFD_RELOC_PPC64_DTPREL16_LO_DS
2848 BFD_RELOC_PPC64_DTPREL16_HIGH
2850 BFD_RELOC_PPC64_DTPREL16_HIGHA
2852 BFD_RELOC_PPC64_DTPREL16_HIGHER
2854 BFD_RELOC_PPC64_DTPREL16_HIGHERA
2856 BFD_RELOC_PPC64_DTPREL16_HIGHEST
2858 BFD_RELOC_PPC64_DTPREL16_HIGHESTA
2860 BFD_RELOC_PPC64_TPREL34
2862 BFD_RELOC_PPC64_DTPREL34
2864 BFD_RELOC_PPC64_GOT_TLSGD_PCREL34
2866 BFD_RELOC_PPC64_GOT_TLSLD_PCREL34
2868 BFD_RELOC_PPC64_GOT_TPREL_PCREL34
2870 BFD_RELOC_PPC64_GOT_DTPREL_PCREL34
2872 BFD_RELOC_PPC64_TLS_PCREL
2874 PowerPC and PowerPC64 thread-local storage relocations.
2879 IBM 370/390 relocations
2884 The type of reloc used to build a constructor table - at the moment
2885 probably a 32 bit wide absolute relocation, but the target can choose.
2886 It generally does map to one of the other relocation types.
2889 BFD_RELOC_ARM_PCREL_BRANCH
2891 ARM 26 bit pc-relative branch. The lowest two bits must be zero and are
2892 not stored in the instruction.
2894 BFD_RELOC_ARM_PCREL_BLX
2896 ARM 26 bit pc-relative branch. The lowest bit must be zero and is
2897 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
2898 field in the instruction.
2900 BFD_RELOC_THUMB_PCREL_BLX
2902 Thumb 22 bit pc-relative branch. The lowest bit must be zero and is
2903 not stored in the instruction. The 2nd lowest bit comes from a 1 bit
2904 field in the instruction.
2906 BFD_RELOC_ARM_PCREL_CALL
2908 ARM 26-bit pc-relative branch for an unconditional BL or BLX instruction.
2910 BFD_RELOC_ARM_PCREL_JUMP
2912 ARM 26-bit pc-relative branch for B or conditional BL instruction.
2915 BFD_RELOC_THUMB_PCREL_BRANCH5
2917 ARM 5-bit pc-relative branch for Branch Future instructions.
2920 BFD_RELOC_THUMB_PCREL_BFCSEL
2922 ARM 6-bit pc-relative branch for BFCSEL instruction.
2925 BFD_RELOC_ARM_THUMB_BF17
2927 ARM 17-bit pc-relative branch for Branch Future instructions.
2930 BFD_RELOC_ARM_THUMB_BF13
2932 ARM 13-bit pc-relative branch for BFCSEL instruction.
2935 BFD_RELOC_ARM_THUMB_BF19
2937 ARM 19-bit pc-relative branch for Branch Future Link instruction.
2940 BFD_RELOC_ARM_THUMB_LOOP12
2942 ARM 12-bit pc-relative branch for Low Overhead Loop instructions.
2945 BFD_RELOC_THUMB_PCREL_BRANCH7
2947 BFD_RELOC_THUMB_PCREL_BRANCH9
2949 BFD_RELOC_THUMB_PCREL_BRANCH12
2951 BFD_RELOC_THUMB_PCREL_BRANCH20
2953 BFD_RELOC_THUMB_PCREL_BRANCH23
2955 BFD_RELOC_THUMB_PCREL_BRANCH25
2957 Thumb 7-, 9-, 12-, 20-, 23-, and 25-bit pc-relative branches.
2958 The lowest bit must be zero and is not stored in the instruction.
2959 Note that the corresponding ELF R_ARM_THM_JUMPnn constant has an
2960 "nn" one smaller in all cases. Note further that BRANCH23
2961 corresponds to R_ARM_THM_CALL.
2964 BFD_RELOC_ARM_OFFSET_IMM
2966 12-bit immediate offset, used in ARM-format ldr and str instructions.
2969 BFD_RELOC_ARM_THUMB_OFFSET
2971 5-bit immediate offset, used in Thumb-format ldr and str instructions.
2974 BFD_RELOC_ARM_TARGET1
2976 Pc-relative or absolute relocation depending on target. Used for
2977 entries in .init_array sections.
2979 BFD_RELOC_ARM_ROSEGREL32
2981 Read-only segment base relative address.
2983 BFD_RELOC_ARM_SBREL32
2985 Data segment base relative address.
2987 BFD_RELOC_ARM_TARGET2
2989 This reloc is used for references to RTTI data from exception handling
2990 tables. The actual definition depends on the target. It may be a
2991 pc-relative or some form of GOT-indirect relocation.
2993 BFD_RELOC_ARM_PREL31
2995 31-bit PC relative address.
3001 BFD_RELOC_ARM_MOVW_PCREL
3003 BFD_RELOC_ARM_MOVT_PCREL
3005 BFD_RELOC_ARM_THUMB_MOVW
3007 BFD_RELOC_ARM_THUMB_MOVT
3009 BFD_RELOC_ARM_THUMB_MOVW_PCREL
3011 BFD_RELOC_ARM_THUMB_MOVT_PCREL
3013 Low and High halfword relocations for MOVW and MOVT instructions.
3016 BFD_RELOC_ARM_GOTFUNCDESC
3018 BFD_RELOC_ARM_GOTOFFFUNCDESC
3020 BFD_RELOC_ARM_FUNCDESC
3022 BFD_RELOC_ARM_FUNCDESC_VALUE
3024 BFD_RELOC_ARM_TLS_GD32_FDPIC
3026 BFD_RELOC_ARM_TLS_LDM32_FDPIC
3028 BFD_RELOC_ARM_TLS_IE32_FDPIC
3030 ARM FDPIC specific relocations.
3033 BFD_RELOC_ARM_JUMP_SLOT
3035 BFD_RELOC_ARM_GLOB_DAT
3041 BFD_RELOC_ARM_RELATIVE
3043 BFD_RELOC_ARM_GOTOFF
3047 BFD_RELOC_ARM_GOT_PREL
3049 Relocations for setting up GOTs and PLTs for shared libraries.
3052 BFD_RELOC_ARM_TLS_GD32
3054 BFD_RELOC_ARM_TLS_LDO32
3056 BFD_RELOC_ARM_TLS_LDM32
3058 BFD_RELOC_ARM_TLS_DTPOFF32
3060 BFD_RELOC_ARM_TLS_DTPMOD32
3062 BFD_RELOC_ARM_TLS_TPOFF32
3064 BFD_RELOC_ARM_TLS_IE32
3066 BFD_RELOC_ARM_TLS_LE32
3068 BFD_RELOC_ARM_TLS_GOTDESC
3070 BFD_RELOC_ARM_TLS_CALL
3072 BFD_RELOC_ARM_THM_TLS_CALL
3074 BFD_RELOC_ARM_TLS_DESCSEQ
3076 BFD_RELOC_ARM_THM_TLS_DESCSEQ
3078 BFD_RELOC_ARM_TLS_DESC
3080 ARM thread-local storage relocations.
3083 BFD_RELOC_ARM_ALU_PC_G0_NC
3085 BFD_RELOC_ARM_ALU_PC_G0
3087 BFD_RELOC_ARM_ALU_PC_G1_NC
3089 BFD_RELOC_ARM_ALU_PC_G1
3091 BFD_RELOC_ARM_ALU_PC_G2
3093 BFD_RELOC_ARM_LDR_PC_G0
3095 BFD_RELOC_ARM_LDR_PC_G1
3097 BFD_RELOC_ARM_LDR_PC_G2
3099 BFD_RELOC_ARM_LDRS_PC_G0
3101 BFD_RELOC_ARM_LDRS_PC_G1
3103 BFD_RELOC_ARM_LDRS_PC_G2
3105 BFD_RELOC_ARM_LDC_PC_G0
3107 BFD_RELOC_ARM_LDC_PC_G1
3109 BFD_RELOC_ARM_LDC_PC_G2
3111 BFD_RELOC_ARM_ALU_SB_G0_NC
3113 BFD_RELOC_ARM_ALU_SB_G0
3115 BFD_RELOC_ARM_ALU_SB_G1_NC
3117 BFD_RELOC_ARM_ALU_SB_G1
3119 BFD_RELOC_ARM_ALU_SB_G2
3121 BFD_RELOC_ARM_LDR_SB_G0
3123 BFD_RELOC_ARM_LDR_SB_G1
3125 BFD_RELOC_ARM_LDR_SB_G2
3127 BFD_RELOC_ARM_LDRS_SB_G0
3129 BFD_RELOC_ARM_LDRS_SB_G1
3131 BFD_RELOC_ARM_LDRS_SB_G2
3133 BFD_RELOC_ARM_LDC_SB_G0
3135 BFD_RELOC_ARM_LDC_SB_G1
3137 BFD_RELOC_ARM_LDC_SB_G2
3139 ARM group relocations.
3144 Annotation of BX instructions.
3147 BFD_RELOC_ARM_IRELATIVE
3149 ARM support for STT_GNU_IFUNC.
3152 BFD_RELOC_ARM_THUMB_ALU_ABS_G0_NC
3154 BFD_RELOC_ARM_THUMB_ALU_ABS_G1_NC
3156 BFD_RELOC_ARM_THUMB_ALU_ABS_G2_NC
3158 BFD_RELOC_ARM_THUMB_ALU_ABS_G3_NC
3160 Thumb1 relocations to support execute-only code.
3163 BFD_RELOC_ARM_IMMEDIATE
3165 BFD_RELOC_ARM_ADRL_IMMEDIATE
3167 BFD_RELOC_ARM_T32_IMMEDIATE
3169 BFD_RELOC_ARM_T32_ADD_IMM
3171 BFD_RELOC_ARM_T32_IMM12
3173 BFD_RELOC_ARM_T32_ADD_PC12
3175 BFD_RELOC_ARM_SHIFT_IMM
3185 BFD_RELOC_ARM_CP_OFF_IMM
3187 BFD_RELOC_ARM_CP_OFF_IMM_S2
3189 BFD_RELOC_ARM_T32_CP_OFF_IMM
3191 BFD_RELOC_ARM_T32_CP_OFF_IMM_S2
3193 BFD_RELOC_ARM_T32_VLDR_VSTR_OFF_IMM
3195 BFD_RELOC_ARM_ADR_IMM
3197 BFD_RELOC_ARM_LDR_IMM
3199 BFD_RELOC_ARM_LITERAL
3201 BFD_RELOC_ARM_IN_POOL
3203 BFD_RELOC_ARM_OFFSET_IMM8
3205 BFD_RELOC_ARM_T32_OFFSET_U8
3207 BFD_RELOC_ARM_T32_OFFSET_IMM
3209 BFD_RELOC_ARM_HWLITERAL
3211 BFD_RELOC_ARM_THUMB_ADD
3213 BFD_RELOC_ARM_THUMB_IMM
3215 BFD_RELOC_ARM_THUMB_SHIFT
3217 These relocs are only used within the ARM assembler. They are not
3218 (at present) written to any object files.
3221 BFD_RELOC_SH_PCDISP8BY2
3223 BFD_RELOC_SH_PCDISP12BY2
3231 BFD_RELOC_SH_DISP12BY2
3233 BFD_RELOC_SH_DISP12BY4
3235 BFD_RELOC_SH_DISP12BY8
3239 BFD_RELOC_SH_DISP20BY8
3243 BFD_RELOC_SH_IMM4BY2
3245 BFD_RELOC_SH_IMM4BY4
3249 BFD_RELOC_SH_IMM8BY2
3251 BFD_RELOC_SH_IMM8BY4
3253 BFD_RELOC_SH_PCRELIMM8BY2
3255 BFD_RELOC_SH_PCRELIMM8BY4
3257 BFD_RELOC_SH_SWITCH16
3259 BFD_RELOC_SH_SWITCH32
3273 BFD_RELOC_SH_LOOP_START
3275 BFD_RELOC_SH_LOOP_END
3279 BFD_RELOC_SH_GLOB_DAT
3281 BFD_RELOC_SH_JMP_SLOT
3283 BFD_RELOC_SH_RELATIVE
3287 BFD_RELOC_SH_GOT_LOW16
3289 BFD_RELOC_SH_GOT_MEDLOW16
3291 BFD_RELOC_SH_GOT_MEDHI16
3293 BFD_RELOC_SH_GOT_HI16
3295 BFD_RELOC_SH_GOTPLT_LOW16
3297 BFD_RELOC_SH_GOTPLT_MEDLOW16
3299 BFD_RELOC_SH_GOTPLT_MEDHI16
3301 BFD_RELOC_SH_GOTPLT_HI16
3303 BFD_RELOC_SH_PLT_LOW16
3305 BFD_RELOC_SH_PLT_MEDLOW16
3307 BFD_RELOC_SH_PLT_MEDHI16
3309 BFD_RELOC_SH_PLT_HI16
3311 BFD_RELOC_SH_GOTOFF_LOW16
3313 BFD_RELOC_SH_GOTOFF_MEDLOW16
3315 BFD_RELOC_SH_GOTOFF_MEDHI16
3317 BFD_RELOC_SH_GOTOFF_HI16
3319 BFD_RELOC_SH_GOTPC_LOW16
3321 BFD_RELOC_SH_GOTPC_MEDLOW16
3323 BFD_RELOC_SH_GOTPC_MEDHI16
3325 BFD_RELOC_SH_GOTPC_HI16
3329 BFD_RELOC_SH_GLOB_DAT64
3331 BFD_RELOC_SH_JMP_SLOT64
3333 BFD_RELOC_SH_RELATIVE64
3335 BFD_RELOC_SH_GOT10BY4
3337 BFD_RELOC_SH_GOT10BY8
3339 BFD_RELOC_SH_GOTPLT10BY4
3341 BFD_RELOC_SH_GOTPLT10BY8
3343 BFD_RELOC_SH_GOTPLT32
3345 BFD_RELOC_SH_SHMEDIA_CODE
3351 BFD_RELOC_SH_IMMS6BY32
3357 BFD_RELOC_SH_IMMS10BY2
3359 BFD_RELOC_SH_IMMS10BY4
3361 BFD_RELOC_SH_IMMS10BY8
3367 BFD_RELOC_SH_IMM_LOW16
3369 BFD_RELOC_SH_IMM_LOW16_PCREL
3371 BFD_RELOC_SH_IMM_MEDLOW16
3373 BFD_RELOC_SH_IMM_MEDLOW16_PCREL
3375 BFD_RELOC_SH_IMM_MEDHI16
3377 BFD_RELOC_SH_IMM_MEDHI16_PCREL
3379 BFD_RELOC_SH_IMM_HI16
3381 BFD_RELOC_SH_IMM_HI16_PCREL
3385 BFD_RELOC_SH_TLS_GD_32
3387 BFD_RELOC_SH_TLS_LD_32
3389 BFD_RELOC_SH_TLS_LDO_32
3391 BFD_RELOC_SH_TLS_IE_32
3393 BFD_RELOC_SH_TLS_LE_32
3395 BFD_RELOC_SH_TLS_DTPMOD32
3397 BFD_RELOC_SH_TLS_DTPOFF32
3399 BFD_RELOC_SH_TLS_TPOFF32
3403 BFD_RELOC_SH_GOTOFF20
3405 BFD_RELOC_SH_GOTFUNCDESC
3407 BFD_RELOC_SH_GOTFUNCDESC20
3409 BFD_RELOC_SH_GOTOFFFUNCDESC
3411 BFD_RELOC_SH_GOTOFFFUNCDESC20
3413 BFD_RELOC_SH_FUNCDESC
3415 Renesas / SuperH SH relocs. Not all of these appear in object files.
3438 BFD_RELOC_ARC_SECTOFF
3440 BFD_RELOC_ARC_S21H_PCREL
3442 BFD_RELOC_ARC_S21W_PCREL
3444 BFD_RELOC_ARC_S25H_PCREL
3446 BFD_RELOC_ARC_S25W_PCREL
3450 BFD_RELOC_ARC_SDA_LDST
3452 BFD_RELOC_ARC_SDA_LDST1
3454 BFD_RELOC_ARC_SDA_LDST2
3456 BFD_RELOC_ARC_SDA16_LD
3458 BFD_RELOC_ARC_SDA16_LD1
3460 BFD_RELOC_ARC_SDA16_LD2
3462 BFD_RELOC_ARC_S13_PCREL
3468 BFD_RELOC_ARC_32_ME_S
3470 BFD_RELOC_ARC_N32_ME
3472 BFD_RELOC_ARC_SECTOFF_ME
3474 BFD_RELOC_ARC_SDA32_ME
3478 BFD_RELOC_AC_SECTOFF_U8
3480 BFD_RELOC_AC_SECTOFF_U8_1
3482 BFD_RELOC_AC_SECTOFF_U8_2
3484 BFD_RELOC_AC_SECTOFF_S9
3486 BFD_RELOC_AC_SECTOFF_S9_1
3488 BFD_RELOC_AC_SECTOFF_S9_2
3490 BFD_RELOC_ARC_SECTOFF_ME_1
3492 BFD_RELOC_ARC_SECTOFF_ME_2
3494 BFD_RELOC_ARC_SECTOFF_1
3496 BFD_RELOC_ARC_SECTOFF_2
3498 BFD_RELOC_ARC_SDA_12
3500 BFD_RELOC_ARC_SDA16_ST2
3502 BFD_RELOC_ARC_32_PCREL
3508 BFD_RELOC_ARC_GOTPC32
3514 BFD_RELOC_ARC_GLOB_DAT
3516 BFD_RELOC_ARC_JMP_SLOT
3518 BFD_RELOC_ARC_RELATIVE
3520 BFD_RELOC_ARC_GOTOFF
3524 BFD_RELOC_ARC_S21W_PCREL_PLT
3526 BFD_RELOC_ARC_S25H_PCREL_PLT
3528 BFD_RELOC_ARC_TLS_DTPMOD
3530 BFD_RELOC_ARC_TLS_TPOFF
3532 BFD_RELOC_ARC_TLS_GD_GOT
3534 BFD_RELOC_ARC_TLS_GD_LD
3536 BFD_RELOC_ARC_TLS_GD_CALL
3538 BFD_RELOC_ARC_TLS_IE_GOT
3540 BFD_RELOC_ARC_TLS_DTPOFF
3542 BFD_RELOC_ARC_TLS_DTPOFF_S9
3544 BFD_RELOC_ARC_TLS_LE_S9
3546 BFD_RELOC_ARC_TLS_LE_32
3548 BFD_RELOC_ARC_S25W_PCREL_PLT
3550 BFD_RELOC_ARC_S21H_PCREL_PLT
3552 BFD_RELOC_ARC_NPS_CMEM16
3554 BFD_RELOC_ARC_JLI_SECTOFF
3559 BFD_RELOC_BFIN_16_IMM
3561 ADI Blackfin 16 bit immediate absolute reloc.
3563 BFD_RELOC_BFIN_16_HIGH
3565 ADI Blackfin 16 bit immediate absolute reloc higher 16 bits.
3567 BFD_RELOC_BFIN_4_PCREL
3569 ADI Blackfin 'a' part of LSETUP.
3571 BFD_RELOC_BFIN_5_PCREL
3575 BFD_RELOC_BFIN_16_LOW
3577 ADI Blackfin 16 bit immediate absolute reloc lower 16 bits.
3579 BFD_RELOC_BFIN_10_PCREL
3583 BFD_RELOC_BFIN_11_PCREL
3585 ADI Blackfin 'b' part of LSETUP.
3587 BFD_RELOC_BFIN_12_PCREL_JUMP
3591 BFD_RELOC_BFIN_12_PCREL_JUMP_S
3593 ADI Blackfin Short jump, pcrel.
3595 BFD_RELOC_BFIN_24_PCREL_CALL_X
3597 ADI Blackfin Call.x not implemented.
3599 BFD_RELOC_BFIN_24_PCREL_JUMP_L
3601 ADI Blackfin Long Jump pcrel.
3603 BFD_RELOC_BFIN_GOT17M4
3605 BFD_RELOC_BFIN_GOTHI
3607 BFD_RELOC_BFIN_GOTLO
3609 BFD_RELOC_BFIN_FUNCDESC
3611 BFD_RELOC_BFIN_FUNCDESC_GOT17M4
3613 BFD_RELOC_BFIN_FUNCDESC_GOTHI
3615 BFD_RELOC_BFIN_FUNCDESC_GOTLO
3617 BFD_RELOC_BFIN_FUNCDESC_VALUE
3619 BFD_RELOC_BFIN_FUNCDESC_GOTOFF17M4
3621 BFD_RELOC_BFIN_FUNCDESC_GOTOFFHI
3623 BFD_RELOC_BFIN_FUNCDESC_GOTOFFLO
3625 BFD_RELOC_BFIN_GOTOFF17M4
3627 BFD_RELOC_BFIN_GOTOFFHI
3629 BFD_RELOC_BFIN_GOTOFFLO
3631 ADI Blackfin FD-PIC relocations.
3635 ADI Blackfin GOT relocation.
3637 BFD_RELOC_BFIN_PLTPC
3639 ADI Blackfin PLTPC relocation.
3641 BFD_ARELOC_BFIN_PUSH
3643 ADI Blackfin arithmetic relocation.
3645 BFD_ARELOC_BFIN_CONST
3647 ADI Blackfin arithmetic relocation.
3651 ADI Blackfin arithmetic relocation.
3655 ADI Blackfin arithmetic relocation.
3657 BFD_ARELOC_BFIN_MULT
3659 ADI Blackfin arithmetic relocation.
3663 ADI Blackfin arithmetic relocation.
3667 ADI Blackfin arithmetic relocation.
3669 BFD_ARELOC_BFIN_LSHIFT
3671 ADI Blackfin arithmetic relocation.
3673 BFD_ARELOC_BFIN_RSHIFT
3675 ADI Blackfin arithmetic relocation.
3679 ADI Blackfin arithmetic relocation.
3683 ADI Blackfin arithmetic relocation.
3687 ADI Blackfin arithmetic relocation.
3689 BFD_ARELOC_BFIN_LAND
3691 ADI Blackfin arithmetic relocation.
3695 ADI Blackfin arithmetic relocation.
3699 ADI Blackfin arithmetic relocation.
3703 ADI Blackfin arithmetic relocation.
3705 BFD_ARELOC_BFIN_COMP
3707 ADI Blackfin arithmetic relocation.
3709 BFD_ARELOC_BFIN_PAGE
3711 ADI Blackfin arithmetic relocation.
3713 BFD_ARELOC_BFIN_HWPAGE
3715 ADI Blackfin arithmetic relocation.
3717 BFD_ARELOC_BFIN_ADDR
3719 ADI Blackfin arithmetic relocation.
3722 BFD_RELOC_D10V_10_PCREL_R
3724 Mitsubishi D10V relocs.
3725 This is a 10-bit reloc with the right 2 bits
3728 BFD_RELOC_D10V_10_PCREL_L
3730 Mitsubishi D10V relocs.
3731 This is a 10-bit reloc with the right 2 bits
3732 assumed to be 0. This is the same as the previous reloc
3733 except it is in the left container, i.e.,
3734 shifted left 15 bits.
3738 This is an 18-bit reloc with the right 2 bits
3741 BFD_RELOC_D10V_18_PCREL
3743 This is an 18-bit reloc with the right 2 bits
3749 Mitsubishi D30V relocs.
3750 This is a 6-bit absolute reloc.
3752 BFD_RELOC_D30V_9_PCREL
3754 This is a 6-bit pc-relative reloc with
3755 the right 3 bits assumed to be 0.
3757 BFD_RELOC_D30V_9_PCREL_R
3759 This is a 6-bit pc-relative reloc with
3760 the right 3 bits assumed to be 0. Same
3761 as the previous reloc but on the right side
3766 This is a 12-bit absolute reloc with the
3767 right 3 bitsassumed to be 0.
3769 BFD_RELOC_D30V_15_PCREL
3771 This is a 12-bit pc-relative reloc with
3772 the right 3 bits assumed to be 0.
3774 BFD_RELOC_D30V_15_PCREL_R
3776 This is a 12-bit pc-relative reloc with
3777 the right 3 bits assumed to be 0. Same
3778 as the previous reloc but on the right side
3783 This is an 18-bit absolute reloc with
3784 the right 3 bits assumed to be 0.
3786 BFD_RELOC_D30V_21_PCREL
3788 This is an 18-bit pc-relative reloc with
3789 the right 3 bits assumed to be 0.
3791 BFD_RELOC_D30V_21_PCREL_R
3793 This is an 18-bit pc-relative reloc with
3794 the right 3 bits assumed to be 0. Same
3795 as the previous reloc but on the right side
3800 This is a 32-bit absolute reloc.
3802 BFD_RELOC_D30V_32_PCREL
3804 This is a 32-bit pc-relative reloc.
3807 BFD_RELOC_DLX_HI16_S
3822 BFD_RELOC_M32C_RL_JUMP
3824 BFD_RELOC_M32C_RL_1ADDR
3826 BFD_RELOC_M32C_RL_2ADDR
3828 Renesas M16C/M32C Relocations.
3833 Renesas M32R (formerly Mitsubishi M32R) relocs.
3834 This is a 24 bit absolute address.
3836 BFD_RELOC_M32R_10_PCREL
3838 This is a 10-bit pc-relative reloc with the right 2 bits assumed to be 0.
3840 BFD_RELOC_M32R_18_PCREL
3842 This is an 18-bit reloc with the right 2 bits assumed to be 0.
3844 BFD_RELOC_M32R_26_PCREL
3846 This is a 26-bit reloc with the right 2 bits assumed to be 0.
3848 BFD_RELOC_M32R_HI16_ULO
3850 This is a 16-bit reloc containing the high 16 bits of an address
3851 used when the lower 16 bits are treated as unsigned.
3853 BFD_RELOC_M32R_HI16_SLO
3855 This is a 16-bit reloc containing the high 16 bits of an address
3856 used when the lower 16 bits are treated as signed.
3860 This is a 16-bit reloc containing the lower 16 bits of an address.
3862 BFD_RELOC_M32R_SDA16
3864 This is a 16-bit reloc containing the small data area offset for use in
3865 add3, load, and store instructions.
3867 BFD_RELOC_M32R_GOT24
3869 BFD_RELOC_M32R_26_PLTREL
3873 BFD_RELOC_M32R_GLOB_DAT
3875 BFD_RELOC_M32R_JMP_SLOT
3877 BFD_RELOC_M32R_RELATIVE
3879 BFD_RELOC_M32R_GOTOFF
3881 BFD_RELOC_M32R_GOTOFF_HI_ULO
3883 BFD_RELOC_M32R_GOTOFF_HI_SLO
3885 BFD_RELOC_M32R_GOTOFF_LO
3887 BFD_RELOC_M32R_GOTPC24
3889 BFD_RELOC_M32R_GOT16_HI_ULO
3891 BFD_RELOC_M32R_GOT16_HI_SLO
3893 BFD_RELOC_M32R_GOT16_LO
3895 BFD_RELOC_M32R_GOTPC_HI_ULO
3897 BFD_RELOC_M32R_GOTPC_HI_SLO
3899 BFD_RELOC_M32R_GOTPC_LO
3908 This is a 20 bit absolute address.
3910 BFD_RELOC_NDS32_9_PCREL
3912 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3914 BFD_RELOC_NDS32_WORD_9_PCREL
3916 This is a 9-bit pc-relative reloc with the right 1 bit assumed to be 0.
3918 BFD_RELOC_NDS32_15_PCREL
3920 This is an 15-bit reloc with the right 1 bit assumed to be 0.
3922 BFD_RELOC_NDS32_17_PCREL
3924 This is an 17-bit reloc with the right 1 bit assumed to be 0.
3926 BFD_RELOC_NDS32_25_PCREL
3928 This is a 25-bit reloc with the right 1 bit assumed to be 0.
3930 BFD_RELOC_NDS32_HI20
3932 This is a 20-bit reloc containing the high 20 bits of an address
3933 used with the lower 12 bits
3935 BFD_RELOC_NDS32_LO12S3
3937 This is a 12-bit reloc containing the lower 12 bits of an address
3938 then shift right by 3. This is used with ldi,sdi...
3940 BFD_RELOC_NDS32_LO12S2
3942 This is a 12-bit reloc containing the lower 12 bits of an address
3943 then shift left by 2. This is used with lwi,swi...
3945 BFD_RELOC_NDS32_LO12S1
3947 This is a 12-bit reloc containing the lower 12 bits of an address
3948 then shift left by 1. This is used with lhi,shi...
3950 BFD_RELOC_NDS32_LO12S0
3952 This is a 12-bit reloc containing the lower 12 bits of an address
3953 then shift left by 0. This is used with lbisbi...
3955 BFD_RELOC_NDS32_LO12S0_ORI
3957 This is a 12-bit reloc containing the lower 12 bits of an address
3958 then shift left by 0. This is only used with branch relaxations
3960 BFD_RELOC_NDS32_SDA15S3
3962 This is a 15-bit reloc containing the small data area 18-bit signed offset
3963 and shift left by 3 for use in ldi, sdi...
3965 BFD_RELOC_NDS32_SDA15S2
3967 This is a 15-bit reloc containing the small data area 17-bit signed offset
3968 and shift left by 2 for use in lwi, swi...
3970 BFD_RELOC_NDS32_SDA15S1
3972 This is a 15-bit reloc containing the small data area 16-bit signed offset
3973 and shift left by 1 for use in lhi, shi...
3975 BFD_RELOC_NDS32_SDA15S0
3977 This is a 15-bit reloc containing the small data area 15-bit signed offset
3978 and shift left by 0 for use in lbi, sbi...
3980 BFD_RELOC_NDS32_SDA16S3
3982 This is a 16-bit reloc containing the small data area 16-bit signed offset
3985 BFD_RELOC_NDS32_SDA17S2
3987 This is a 17-bit reloc containing the small data area 17-bit signed offset
3988 and shift left by 2 for use in lwi.gp, swi.gp...
3990 BFD_RELOC_NDS32_SDA18S1
3992 This is a 18-bit reloc containing the small data area 18-bit signed offset
3993 and shift left by 1 for use in lhi.gp, shi.gp...
3995 BFD_RELOC_NDS32_SDA19S0
3997 This is a 19-bit reloc containing the small data area 19-bit signed offset
3998 and shift left by 0 for use in lbi.gp, sbi.gp...
4000 BFD_RELOC_NDS32_GOT20
4002 BFD_RELOC_NDS32_9_PLTREL
4004 BFD_RELOC_NDS32_25_PLTREL
4006 BFD_RELOC_NDS32_COPY
4008 BFD_RELOC_NDS32_GLOB_DAT
4010 BFD_RELOC_NDS32_JMP_SLOT
4012 BFD_RELOC_NDS32_RELATIVE
4014 BFD_RELOC_NDS32_GOTOFF
4016 BFD_RELOC_NDS32_GOTOFF_HI20
4018 BFD_RELOC_NDS32_GOTOFF_LO12
4020 BFD_RELOC_NDS32_GOTPC20
4022 BFD_RELOC_NDS32_GOT_HI20
4024 BFD_RELOC_NDS32_GOT_LO12
4026 BFD_RELOC_NDS32_GOTPC_HI20
4028 BFD_RELOC_NDS32_GOTPC_LO12
4032 BFD_RELOC_NDS32_INSN16
4034 BFD_RELOC_NDS32_LABEL
4036 BFD_RELOC_NDS32_LONGCALL1
4038 BFD_RELOC_NDS32_LONGCALL2
4040 BFD_RELOC_NDS32_LONGCALL3
4042 BFD_RELOC_NDS32_LONGJUMP1
4044 BFD_RELOC_NDS32_LONGJUMP2
4046 BFD_RELOC_NDS32_LONGJUMP3
4048 BFD_RELOC_NDS32_LOADSTORE
4050 BFD_RELOC_NDS32_9_FIXED
4052 BFD_RELOC_NDS32_15_FIXED
4054 BFD_RELOC_NDS32_17_FIXED
4056 BFD_RELOC_NDS32_25_FIXED
4058 BFD_RELOC_NDS32_LONGCALL4
4060 BFD_RELOC_NDS32_LONGCALL5
4062 BFD_RELOC_NDS32_LONGCALL6
4064 BFD_RELOC_NDS32_LONGJUMP4
4066 BFD_RELOC_NDS32_LONGJUMP5
4068 BFD_RELOC_NDS32_LONGJUMP6
4070 BFD_RELOC_NDS32_LONGJUMP7
4074 BFD_RELOC_NDS32_PLTREL_HI20
4076 BFD_RELOC_NDS32_PLTREL_LO12
4078 BFD_RELOC_NDS32_PLT_GOTREL_HI20
4080 BFD_RELOC_NDS32_PLT_GOTREL_LO12
4084 BFD_RELOC_NDS32_SDA12S2_DP
4086 BFD_RELOC_NDS32_SDA12S2_SP
4088 BFD_RELOC_NDS32_LO12S2_DP
4090 BFD_RELOC_NDS32_LO12S2_SP
4094 BFD_RELOC_NDS32_DWARF2_OP1
4096 BFD_RELOC_NDS32_DWARF2_OP2
4098 BFD_RELOC_NDS32_DWARF2_LEB
4100 for dwarf2 debug_line.
4102 BFD_RELOC_NDS32_UPDATE_TA
4104 for eliminate 16-bit instructions
4106 BFD_RELOC_NDS32_PLT_GOTREL_LO20
4108 BFD_RELOC_NDS32_PLT_GOTREL_LO15
4110 BFD_RELOC_NDS32_PLT_GOTREL_LO19
4112 BFD_RELOC_NDS32_GOT_LO15
4114 BFD_RELOC_NDS32_GOT_LO19
4116 BFD_RELOC_NDS32_GOTOFF_LO15
4118 BFD_RELOC_NDS32_GOTOFF_LO19
4120 BFD_RELOC_NDS32_GOT15S2
4122 BFD_RELOC_NDS32_GOT17S2
4124 for PIC object relaxation
4129 This is a 5 bit absolute address.
4131 BFD_RELOC_NDS32_10_UPCREL
4133 This is a 10-bit unsigned pc-relative reloc with the right 1 bit assumed to be 0.
4135 BFD_RELOC_NDS32_SDA_FP7U2_RELA
4137 If fp were omitted, fp can used as another gp.
4139 BFD_RELOC_NDS32_RELAX_ENTRY
4141 BFD_RELOC_NDS32_GOT_SUFF
4143 BFD_RELOC_NDS32_GOTOFF_SUFF
4145 BFD_RELOC_NDS32_PLT_GOT_SUFF
4147 BFD_RELOC_NDS32_MULCALL_SUFF
4151 BFD_RELOC_NDS32_PTR_COUNT
4153 BFD_RELOC_NDS32_PTR_RESOLVED
4155 BFD_RELOC_NDS32_PLTBLOCK
4157 BFD_RELOC_NDS32_RELAX_REGION_BEGIN
4159 BFD_RELOC_NDS32_RELAX_REGION_END
4161 BFD_RELOC_NDS32_MINUEND
4163 BFD_RELOC_NDS32_SUBTRAHEND
4165 BFD_RELOC_NDS32_DIFF8
4167 BFD_RELOC_NDS32_DIFF16
4169 BFD_RELOC_NDS32_DIFF32
4171 BFD_RELOC_NDS32_DIFF_ULEB128
4173 BFD_RELOC_NDS32_EMPTY
4175 relaxation relative relocation types
4177 BFD_RELOC_NDS32_25_ABS
4179 This is a 25 bit absolute address.
4181 BFD_RELOC_NDS32_DATA
4183 BFD_RELOC_NDS32_TRAN
4185 BFD_RELOC_NDS32_17IFC_PCREL
4187 BFD_RELOC_NDS32_10IFCU_PCREL
4189 For ex9 and ifc using.
4191 BFD_RELOC_NDS32_TPOFF
4193 BFD_RELOC_NDS32_GOTTPOFF
4195 BFD_RELOC_NDS32_TLS_LE_HI20
4197 BFD_RELOC_NDS32_TLS_LE_LO12
4199 BFD_RELOC_NDS32_TLS_LE_20
4201 BFD_RELOC_NDS32_TLS_LE_15S0
4203 BFD_RELOC_NDS32_TLS_LE_15S1
4205 BFD_RELOC_NDS32_TLS_LE_15S2
4207 BFD_RELOC_NDS32_TLS_LE_ADD
4209 BFD_RELOC_NDS32_TLS_LE_LS
4211 BFD_RELOC_NDS32_TLS_IE_HI20
4213 BFD_RELOC_NDS32_TLS_IE_LO12
4215 BFD_RELOC_NDS32_TLS_IE_LO12S2
4217 BFD_RELOC_NDS32_TLS_IEGP_HI20
4219 BFD_RELOC_NDS32_TLS_IEGP_LO12
4221 BFD_RELOC_NDS32_TLS_IEGP_LO12S2
4223 BFD_RELOC_NDS32_TLS_IEGP_LW
4225 BFD_RELOC_NDS32_TLS_DESC
4227 BFD_RELOC_NDS32_TLS_DESC_HI20
4229 BFD_RELOC_NDS32_TLS_DESC_LO12
4231 BFD_RELOC_NDS32_TLS_DESC_20
4233 BFD_RELOC_NDS32_TLS_DESC_SDA17S2
4235 BFD_RELOC_NDS32_TLS_DESC_ADD
4237 BFD_RELOC_NDS32_TLS_DESC_FUNC
4239 BFD_RELOC_NDS32_TLS_DESC_CALL
4241 BFD_RELOC_NDS32_TLS_DESC_MEM
4243 BFD_RELOC_NDS32_REMOVE
4245 BFD_RELOC_NDS32_GROUP
4251 For floating load store relaxation.
4255 BFD_RELOC_V850_9_PCREL
4257 This is a 9-bit reloc
4259 BFD_RELOC_V850_22_PCREL
4261 This is a 22-bit reloc
4264 BFD_RELOC_V850_SDA_16_16_OFFSET
4266 This is a 16 bit offset from the short data area pointer.
4268 BFD_RELOC_V850_SDA_15_16_OFFSET
4270 This is a 16 bit offset (of which only 15 bits are used) from the
4271 short data area pointer.
4273 BFD_RELOC_V850_ZDA_16_16_OFFSET
4275 This is a 16 bit offset from the zero data area pointer.
4277 BFD_RELOC_V850_ZDA_15_16_OFFSET
4279 This is a 16 bit offset (of which only 15 bits are used) from the
4280 zero data area pointer.
4282 BFD_RELOC_V850_TDA_6_8_OFFSET
4284 This is an 8 bit offset (of which only 6 bits are used) from the
4285 tiny data area pointer.
4287 BFD_RELOC_V850_TDA_7_8_OFFSET
4289 This is an 8bit offset (of which only 7 bits are used) from the tiny
4292 BFD_RELOC_V850_TDA_7_7_OFFSET
4294 This is a 7 bit offset from the tiny data area pointer.
4296 BFD_RELOC_V850_TDA_16_16_OFFSET
4298 This is a 16 bit offset from the tiny data area pointer.
4301 BFD_RELOC_V850_TDA_4_5_OFFSET
4303 This is a 5 bit offset (of which only 4 bits are used) from the tiny
4306 BFD_RELOC_V850_TDA_4_4_OFFSET
4308 This is a 4 bit offset from the tiny data area pointer.
4310 BFD_RELOC_V850_SDA_16_16_SPLIT_OFFSET
4312 This is a 16 bit offset from the short data area pointer, with the
4313 bits placed non-contiguously in the instruction.
4315 BFD_RELOC_V850_ZDA_16_16_SPLIT_OFFSET
4317 This is a 16 bit offset from the zero data area pointer, with the
4318 bits placed non-contiguously in the instruction.
4320 BFD_RELOC_V850_CALLT_6_7_OFFSET
4322 This is a 6 bit offset from the call table base pointer.
4324 BFD_RELOC_V850_CALLT_16_16_OFFSET
4326 This is a 16 bit offset from the call table base pointer.
4328 BFD_RELOC_V850_LONGCALL
4330 Used for relaxing indirect function calls.
4332 BFD_RELOC_V850_LONGJUMP
4334 Used for relaxing indirect jumps.
4336 BFD_RELOC_V850_ALIGN
4338 Used to maintain alignment whilst relaxing.
4340 BFD_RELOC_V850_LO16_SPLIT_OFFSET
4342 This is a variation of BFD_RELOC_LO16 that can be used in v850e ld.bu
4345 BFD_RELOC_V850_16_PCREL
4347 This is a 16-bit reloc.
4349 BFD_RELOC_V850_17_PCREL
4351 This is a 17-bit reloc.
4355 This is a 23-bit reloc.
4357 BFD_RELOC_V850_32_PCREL
4359 This is a 32-bit reloc.
4361 BFD_RELOC_V850_32_ABS
4363 This is a 32-bit reloc.
4365 BFD_RELOC_V850_16_SPLIT_OFFSET
4367 This is a 16-bit reloc.
4369 BFD_RELOC_V850_16_S1
4371 This is a 16-bit reloc.
4373 BFD_RELOC_V850_LO16_S1
4375 Low 16 bits. 16 bit shifted by 1.
4377 BFD_RELOC_V850_CALLT_15_16_OFFSET
4379 This is a 16 bit offset from the call table base pointer.
4381 BFD_RELOC_V850_32_GOTPCREL
4385 BFD_RELOC_V850_16_GOT
4389 BFD_RELOC_V850_32_GOT
4393 BFD_RELOC_V850_22_PLT_PCREL
4397 BFD_RELOC_V850_32_PLT_PCREL
4405 BFD_RELOC_V850_GLOB_DAT
4409 BFD_RELOC_V850_JMP_SLOT
4413 BFD_RELOC_V850_RELATIVE
4417 BFD_RELOC_V850_16_GOTOFF
4421 BFD_RELOC_V850_32_GOTOFF
4436 This is a 8bit DP reloc for the tms320c30, where the most
4437 significant 8 bits of a 24 bit word are placed into the least
4438 significant 8 bits of the opcode.
4441 BFD_RELOC_TIC54X_PARTLS7
4443 This is a 7bit reloc for the tms320c54x, where the least
4444 significant 7 bits of a 16 bit word are placed into the least
4445 significant 7 bits of the opcode.
4448 BFD_RELOC_TIC54X_PARTMS9
4450 This is a 9bit DP reloc for the tms320c54x, where the most
4451 significant 9 bits of a 16 bit word are placed into the least
4452 significant 9 bits of the opcode.
4457 This is an extended address 23-bit reloc for the tms320c54x.
4460 BFD_RELOC_TIC54X_16_OF_23
4462 This is a 16-bit reloc for the tms320c54x, where the least
4463 significant 16 bits of a 23-bit extended address are placed into
4467 BFD_RELOC_TIC54X_MS7_OF_23
4469 This is a reloc for the tms320c54x, where the most
4470 significant 7 bits of a 23-bit extended address are placed into
4474 BFD_RELOC_C6000_PCR_S21
4476 BFD_RELOC_C6000_PCR_S12
4478 BFD_RELOC_C6000_PCR_S10
4480 BFD_RELOC_C6000_PCR_S7
4482 BFD_RELOC_C6000_ABS_S16
4484 BFD_RELOC_C6000_ABS_L16
4486 BFD_RELOC_C6000_ABS_H16
4488 BFD_RELOC_C6000_SBR_U15_B
4490 BFD_RELOC_C6000_SBR_U15_H
4492 BFD_RELOC_C6000_SBR_U15_W
4494 BFD_RELOC_C6000_SBR_S16
4496 BFD_RELOC_C6000_SBR_L16_B
4498 BFD_RELOC_C6000_SBR_L16_H
4500 BFD_RELOC_C6000_SBR_L16_W
4502 BFD_RELOC_C6000_SBR_H16_B
4504 BFD_RELOC_C6000_SBR_H16_H
4506 BFD_RELOC_C6000_SBR_H16_W
4508 BFD_RELOC_C6000_SBR_GOT_U15_W
4510 BFD_RELOC_C6000_SBR_GOT_L16_W
4512 BFD_RELOC_C6000_SBR_GOT_H16_W
4514 BFD_RELOC_C6000_DSBT_INDEX
4516 BFD_RELOC_C6000_PREL31
4518 BFD_RELOC_C6000_COPY
4520 BFD_RELOC_C6000_JUMP_SLOT
4522 BFD_RELOC_C6000_EHTYPE
4524 BFD_RELOC_C6000_PCR_H16
4526 BFD_RELOC_C6000_PCR_L16
4528 BFD_RELOC_C6000_ALIGN
4530 BFD_RELOC_C6000_FPHEAD
4532 BFD_RELOC_C6000_NOCMP
4534 TMS320C6000 relocations.
4539 This is a 48 bit reloc for the FR30 that stores 32 bits.
4543 This is a 32 bit reloc for the FR30 that stores 20 bits split up into
4546 BFD_RELOC_FR30_6_IN_4
4548 This is a 16 bit reloc for the FR30 that stores a 6 bit word offset in
4551 BFD_RELOC_FR30_8_IN_8
4553 This is a 16 bit reloc for the FR30 that stores an 8 bit byte offset
4556 BFD_RELOC_FR30_9_IN_8
4558 This is a 16 bit reloc for the FR30 that stores a 9 bit short offset
4561 BFD_RELOC_FR30_10_IN_8
4563 This is a 16 bit reloc for the FR30 that stores a 10 bit word offset
4566 BFD_RELOC_FR30_9_PCREL
4568 This is a 16 bit reloc for the FR30 that stores a 9 bit pc relative
4569 short offset into 8 bits.
4571 BFD_RELOC_FR30_12_PCREL
4573 This is a 16 bit reloc for the FR30 that stores a 12 bit pc relative
4574 short offset into 11 bits.
4577 BFD_RELOC_MCORE_PCREL_IMM8BY4
4579 BFD_RELOC_MCORE_PCREL_IMM11BY2
4581 BFD_RELOC_MCORE_PCREL_IMM4BY2
4583 BFD_RELOC_MCORE_PCREL_32
4585 BFD_RELOC_MCORE_PCREL_JSR_IMM11BY2
4589 Motorola Mcore relocations.
4598 BFD_RELOC_MEP_PCREL8A2
4600 BFD_RELOC_MEP_PCREL12A2
4602 BFD_RELOC_MEP_PCREL17A2
4604 BFD_RELOC_MEP_PCREL24A2
4606 BFD_RELOC_MEP_PCABS24A2
4618 BFD_RELOC_MEP_TPREL7
4620 BFD_RELOC_MEP_TPREL7A2
4622 BFD_RELOC_MEP_TPREL7A4
4624 BFD_RELOC_MEP_UIMM24
4626 BFD_RELOC_MEP_ADDR24A4
4628 BFD_RELOC_MEP_GNU_VTINHERIT
4630 BFD_RELOC_MEP_GNU_VTENTRY
4632 Toshiba Media Processor Relocations.
4636 BFD_RELOC_METAG_HIADDR16
4638 BFD_RELOC_METAG_LOADDR16
4640 BFD_RELOC_METAG_RELBRANCH
4642 BFD_RELOC_METAG_GETSETOFF
4644 BFD_RELOC_METAG_HIOG
4646 BFD_RELOC_METAG_LOOG
4648 BFD_RELOC_METAG_REL8
4650 BFD_RELOC_METAG_REL16
4652 BFD_RELOC_METAG_HI16_GOTOFF
4654 BFD_RELOC_METAG_LO16_GOTOFF
4656 BFD_RELOC_METAG_GETSET_GOTOFF
4658 BFD_RELOC_METAG_GETSET_GOT
4660 BFD_RELOC_METAG_HI16_GOTPC
4662 BFD_RELOC_METAG_LO16_GOTPC
4664 BFD_RELOC_METAG_HI16_PLT
4666 BFD_RELOC_METAG_LO16_PLT
4668 BFD_RELOC_METAG_RELBRANCH_PLT
4670 BFD_RELOC_METAG_GOTOFF
4674 BFD_RELOC_METAG_COPY
4676 BFD_RELOC_METAG_JMP_SLOT
4678 BFD_RELOC_METAG_RELATIVE
4680 BFD_RELOC_METAG_GLOB_DAT
4682 BFD_RELOC_METAG_TLS_GD
4684 BFD_RELOC_METAG_TLS_LDM
4686 BFD_RELOC_METAG_TLS_LDO_HI16
4688 BFD_RELOC_METAG_TLS_LDO_LO16
4690 BFD_RELOC_METAG_TLS_LDO
4692 BFD_RELOC_METAG_TLS_IE
4694 BFD_RELOC_METAG_TLS_IENONPIC
4696 BFD_RELOC_METAG_TLS_IENONPIC_HI16
4698 BFD_RELOC_METAG_TLS_IENONPIC_LO16
4700 BFD_RELOC_METAG_TLS_TPOFF
4702 BFD_RELOC_METAG_TLS_DTPMOD
4704 BFD_RELOC_METAG_TLS_DTPOFF
4706 BFD_RELOC_METAG_TLS_LE
4708 BFD_RELOC_METAG_TLS_LE_HI16
4710 BFD_RELOC_METAG_TLS_LE_LO16
4712 Imagination Technologies Meta relocations.
4717 BFD_RELOC_MMIX_GETA_1
4719 BFD_RELOC_MMIX_GETA_2
4721 BFD_RELOC_MMIX_GETA_3
4723 These are relocations for the GETA instruction.
4725 BFD_RELOC_MMIX_CBRANCH
4727 BFD_RELOC_MMIX_CBRANCH_J
4729 BFD_RELOC_MMIX_CBRANCH_1
4731 BFD_RELOC_MMIX_CBRANCH_2
4733 BFD_RELOC_MMIX_CBRANCH_3
4735 These are relocations for a conditional branch instruction.
4737 BFD_RELOC_MMIX_PUSHJ
4739 BFD_RELOC_MMIX_PUSHJ_1
4741 BFD_RELOC_MMIX_PUSHJ_2
4743 BFD_RELOC_MMIX_PUSHJ_3
4745 BFD_RELOC_MMIX_PUSHJ_STUBBABLE
4747 These are relocations for the PUSHJ instruction.
4751 BFD_RELOC_MMIX_JMP_1
4753 BFD_RELOC_MMIX_JMP_2
4755 BFD_RELOC_MMIX_JMP_3
4757 These are relocations for the JMP instruction.
4759 BFD_RELOC_MMIX_ADDR19
4761 This is a relocation for a relative address as in a GETA instruction or
4764 BFD_RELOC_MMIX_ADDR27
4766 This is a relocation for a relative address as in a JMP instruction.
4768 BFD_RELOC_MMIX_REG_OR_BYTE
4770 This is a relocation for an instruction field that may be a general
4771 register or a value 0..255.
4775 This is a relocation for an instruction field that may be a general
4778 BFD_RELOC_MMIX_BASE_PLUS_OFFSET
4780 This is a relocation for two instruction fields holding a register and
4781 an offset, the equivalent of the relocation.
4783 BFD_RELOC_MMIX_LOCAL
4785 This relocation is an assertion that the expression is not allocated as
4786 a global register. It does not modify contents.
4789 BFD_RELOC_AVR_7_PCREL
4791 This is a 16 bit reloc for the AVR that stores 8 bit pc relative
4792 short offset into 7 bits.
4794 BFD_RELOC_AVR_13_PCREL
4796 This is a 16 bit reloc for the AVR that stores 13 bit pc relative
4797 short offset into 12 bits.
4801 This is a 16 bit reloc for the AVR that stores 17 bit value (usually
4802 program memory address) into 16 bits.
4804 BFD_RELOC_AVR_LO8_LDI
4806 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4807 data memory address) into 8 bit immediate value of LDI insn.
4809 BFD_RELOC_AVR_HI8_LDI
4811 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4812 of data memory address) into 8 bit immediate value of LDI insn.
4814 BFD_RELOC_AVR_HH8_LDI
4816 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4817 of program memory address) into 8 bit immediate value of LDI insn.
4819 BFD_RELOC_AVR_MS8_LDI
4821 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4822 of 32 bit value) into 8 bit immediate value of LDI insn.
4824 BFD_RELOC_AVR_LO8_LDI_NEG
4826 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4827 (usually data memory address) into 8 bit immediate value of SUBI insn.
4829 BFD_RELOC_AVR_HI8_LDI_NEG
4831 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4832 (high 8 bit of data memory address) into 8 bit immediate value of
4835 BFD_RELOC_AVR_HH8_LDI_NEG
4837 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4838 (most high 8 bit of program memory address) into 8 bit immediate value
4839 of LDI or SUBI insn.
4841 BFD_RELOC_AVR_MS8_LDI_NEG
4843 This is a 16 bit reloc for the AVR that stores negated 8 bit value (msb
4844 of 32 bit value) into 8 bit immediate value of LDI insn.
4846 BFD_RELOC_AVR_LO8_LDI_PM
4848 This is a 16 bit reloc for the AVR that stores 8 bit value (usually
4849 command address) into 8 bit immediate value of LDI insn.
4851 BFD_RELOC_AVR_LO8_LDI_GS
4853 This is a 16 bit reloc for the AVR that stores 8 bit value
4854 (command address) into 8 bit immediate value of LDI insn. If the address
4855 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4858 BFD_RELOC_AVR_HI8_LDI_PM
4860 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4861 of command address) into 8 bit immediate value of LDI insn.
4863 BFD_RELOC_AVR_HI8_LDI_GS
4865 This is a 16 bit reloc for the AVR that stores 8 bit value (high 8 bit
4866 of command address) into 8 bit immediate value of LDI insn. If the address
4867 is beyond the 128k boundary, the linker inserts a jump stub for this reloc
4870 BFD_RELOC_AVR_HH8_LDI_PM
4872 This is a 16 bit reloc for the AVR that stores 8 bit value (most high 8 bit
4873 of command address) into 8 bit immediate value of LDI insn.
4875 BFD_RELOC_AVR_LO8_LDI_PM_NEG
4877 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4878 (usually command address) into 8 bit immediate value of SUBI insn.
4880 BFD_RELOC_AVR_HI8_LDI_PM_NEG
4882 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4883 (high 8 bit of 16 bit command address) into 8 bit immediate value
4886 BFD_RELOC_AVR_HH8_LDI_PM_NEG
4888 This is a 16 bit reloc for the AVR that stores negated 8 bit value
4889 (high 6 bit of 22 bit command address) into 8 bit immediate
4894 This is a 32 bit reloc for the AVR that stores 23 bit value
4899 This is a 16 bit reloc for the AVR that stores all needed bits
4900 for absolute addressing with ldi with overflow check to linktime
4904 This is a 6 bit reloc for the AVR that stores offset for ldd/std
4907 BFD_RELOC_AVR_6_ADIW
4909 This is a 6 bit reloc for the AVR that stores offset for adiw/sbiw
4914 This is a 8 bit reloc for the AVR that stores bits 0..7 of a symbol
4915 in .byte lo8(symbol)
4919 This is a 8 bit reloc for the AVR that stores bits 8..15 of a symbol
4920 in .byte hi8(symbol)
4924 This is a 8 bit reloc for the AVR that stores bits 16..23 of a symbol
4925 in .byte hlo8(symbol)
4929 BFD_RELOC_AVR_DIFF16
4931 BFD_RELOC_AVR_DIFF32
4933 AVR relocations to mark the difference of two local symbols.
4934 These are only needed to support linker relaxation and can be ignored
4935 when not relaxing. The field is set to the value of the difference
4936 assuming no relaxation. The relocation encodes the position of the
4937 second symbol so the linker can determine whether to adjust the field
4940 BFD_RELOC_AVR_LDS_STS_16
4942 This is a 7 bit reloc for the AVR that stores SRAM address for 16bit
4943 lds and sts instructions supported only tiny core.
4947 This is a 6 bit reloc for the AVR that stores an I/O register
4948 number for the IN and OUT instructions
4952 This is a 5 bit reloc for the AVR that stores an I/O register
4953 number for the SBIC, SBIS, SBI and CBI instructions
4956 BFD_RELOC_RISCV_HI20
4958 BFD_RELOC_RISCV_PCREL_HI20
4960 BFD_RELOC_RISCV_PCREL_LO12_I
4962 BFD_RELOC_RISCV_PCREL_LO12_S
4964 BFD_RELOC_RISCV_LO12_I
4966 BFD_RELOC_RISCV_LO12_S
4968 BFD_RELOC_RISCV_GPREL12_I
4970 BFD_RELOC_RISCV_GPREL12_S
4972 BFD_RELOC_RISCV_TPREL_HI20
4974 BFD_RELOC_RISCV_TPREL_LO12_I
4976 BFD_RELOC_RISCV_TPREL_LO12_S
4978 BFD_RELOC_RISCV_TPREL_ADD
4980 BFD_RELOC_RISCV_CALL
4982 BFD_RELOC_RISCV_CALL_PLT
4984 BFD_RELOC_RISCV_ADD8
4986 BFD_RELOC_RISCV_ADD16
4988 BFD_RELOC_RISCV_ADD32
4990 BFD_RELOC_RISCV_ADD64
4992 BFD_RELOC_RISCV_SUB8
4994 BFD_RELOC_RISCV_SUB16
4996 BFD_RELOC_RISCV_SUB32
4998 BFD_RELOC_RISCV_SUB64
5000 BFD_RELOC_RISCV_GOT_HI20
5002 BFD_RELOC_RISCV_TLS_GOT_HI20
5004 BFD_RELOC_RISCV_TLS_GD_HI20
5008 BFD_RELOC_RISCV_TLS_DTPMOD32
5010 BFD_RELOC_RISCV_TLS_DTPREL32
5012 BFD_RELOC_RISCV_TLS_DTPMOD64
5014 BFD_RELOC_RISCV_TLS_DTPREL64
5016 BFD_RELOC_RISCV_TLS_TPREL32
5018 BFD_RELOC_RISCV_TLS_TPREL64
5020 BFD_RELOC_RISCV_ALIGN
5022 BFD_RELOC_RISCV_RVC_BRANCH
5024 BFD_RELOC_RISCV_RVC_JUMP
5026 BFD_RELOC_RISCV_RVC_LUI
5028 BFD_RELOC_RISCV_GPREL_I
5030 BFD_RELOC_RISCV_GPREL_S
5032 BFD_RELOC_RISCV_TPREL_I
5034 BFD_RELOC_RISCV_TPREL_S
5036 BFD_RELOC_RISCV_RELAX
5040 BFD_RELOC_RISCV_SUB6
5042 BFD_RELOC_RISCV_SET6
5044 BFD_RELOC_RISCV_SET8
5046 BFD_RELOC_RISCV_SET16
5048 BFD_RELOC_RISCV_SET32
5050 BFD_RELOC_RISCV_32_PCREL
5052 BFD_RELOC_RISCV_SET_ULEB128
5054 BFD_RELOC_RISCV_SUB_ULEB128
5061 BFD_RELOC_RL78_NEG16
5063 BFD_RELOC_RL78_NEG24
5065 BFD_RELOC_RL78_NEG32
5067 BFD_RELOC_RL78_16_OP
5069 BFD_RELOC_RL78_24_OP
5071 BFD_RELOC_RL78_32_OP
5079 BFD_RELOC_RL78_DIR3U_PCREL
5083 BFD_RELOC_RL78_GPRELB
5085 BFD_RELOC_RL78_GPRELW
5087 BFD_RELOC_RL78_GPRELL
5091 BFD_RELOC_RL78_OP_SUBTRACT
5093 BFD_RELOC_RL78_OP_NEG
5095 BFD_RELOC_RL78_OP_AND
5097 BFD_RELOC_RL78_OP_SHRA
5101 BFD_RELOC_RL78_ABS16
5103 BFD_RELOC_RL78_ABS16_REV
5105 BFD_RELOC_RL78_ABS32
5107 BFD_RELOC_RL78_ABS32_REV
5109 BFD_RELOC_RL78_ABS16U
5111 BFD_RELOC_RL78_ABS16UW
5113 BFD_RELOC_RL78_ABS16UL
5115 BFD_RELOC_RL78_RELAX
5125 BFD_RELOC_RL78_SADDR
5127 Renesas RL78 Relocations.
5150 BFD_RELOC_RX_DIR3U_PCREL
5162 BFD_RELOC_RX_OP_SUBTRACT
5170 BFD_RELOC_RX_ABS16_REV
5174 BFD_RELOC_RX_ABS32_REV
5178 BFD_RELOC_RX_ABS16UW
5180 BFD_RELOC_RX_ABS16UL
5184 Renesas RX Relocations.
5197 32 bit PC relative PLT address.
5201 Copy symbol at runtime.
5203 BFD_RELOC_390_GLOB_DAT
5207 BFD_RELOC_390_JMP_SLOT
5211 BFD_RELOC_390_RELATIVE
5213 Adjust by program base.
5217 32 bit PC relative offset to GOT.
5223 BFD_RELOC_390_PC12DBL
5225 PC relative 12 bit shifted by 1.
5227 BFD_RELOC_390_PLT12DBL
5229 12 bit PC rel. PLT shifted by 1.
5231 BFD_RELOC_390_PC16DBL
5233 PC relative 16 bit shifted by 1.
5235 BFD_RELOC_390_PLT16DBL
5237 16 bit PC rel. PLT shifted by 1.
5239 BFD_RELOC_390_PC24DBL
5241 PC relative 24 bit shifted by 1.
5243 BFD_RELOC_390_PLT24DBL
5245 24 bit PC rel. PLT shifted by 1.
5247 BFD_RELOC_390_PC32DBL
5249 PC relative 32 bit shifted by 1.
5251 BFD_RELOC_390_PLT32DBL
5253 32 bit PC rel. PLT shifted by 1.
5255 BFD_RELOC_390_GOTPCDBL
5257 32 bit PC rel. GOT shifted by 1.
5265 64 bit PC relative PLT address.
5267 BFD_RELOC_390_GOTENT
5269 32 bit rel. offset to GOT entry.
5271 BFD_RELOC_390_GOTOFF64
5273 64 bit offset to GOT.
5275 BFD_RELOC_390_GOTPLT12
5277 12-bit offset to symbol-entry within GOT, with PLT handling.
5279 BFD_RELOC_390_GOTPLT16
5281 16-bit offset to symbol-entry within GOT, with PLT handling.
5283 BFD_RELOC_390_GOTPLT32
5285 32-bit offset to symbol-entry within GOT, with PLT handling.
5287 BFD_RELOC_390_GOTPLT64
5289 64-bit offset to symbol-entry within GOT, with PLT handling.
5291 BFD_RELOC_390_GOTPLTENT
5293 32-bit rel. offset to symbol-entry within GOT, with PLT handling.
5295 BFD_RELOC_390_PLTOFF16
5297 16-bit rel. offset from the GOT to a PLT entry.
5299 BFD_RELOC_390_PLTOFF32
5301 32-bit rel. offset from the GOT to a PLT entry.
5303 BFD_RELOC_390_PLTOFF64
5305 64-bit rel. offset from the GOT to a PLT entry.
5308 BFD_RELOC_390_TLS_LOAD
5310 BFD_RELOC_390_TLS_GDCALL
5312 BFD_RELOC_390_TLS_LDCALL
5314 BFD_RELOC_390_TLS_GD32
5316 BFD_RELOC_390_TLS_GD64
5318 BFD_RELOC_390_TLS_GOTIE12
5320 BFD_RELOC_390_TLS_GOTIE32
5322 BFD_RELOC_390_TLS_GOTIE64
5324 BFD_RELOC_390_TLS_LDM32
5326 BFD_RELOC_390_TLS_LDM64
5328 BFD_RELOC_390_TLS_IE32
5330 BFD_RELOC_390_TLS_IE64
5332 BFD_RELOC_390_TLS_IEENT
5334 BFD_RELOC_390_TLS_LE32
5336 BFD_RELOC_390_TLS_LE64
5338 BFD_RELOC_390_TLS_LDO32
5340 BFD_RELOC_390_TLS_LDO64
5342 BFD_RELOC_390_TLS_DTPMOD
5344 BFD_RELOC_390_TLS_DTPOFF
5346 BFD_RELOC_390_TLS_TPOFF
5348 s390 tls relocations.
5355 BFD_RELOC_390_GOTPLT20
5357 BFD_RELOC_390_TLS_GOTIE20
5359 Long displacement extension.
5362 BFD_RELOC_390_IRELATIVE
5364 STT_GNU_IFUNC relocation.
5367 BFD_RELOC_SCORE_GPREL15
5370 Low 16 bit for load/store
5372 BFD_RELOC_SCORE_DUMMY2
5376 This is a 24-bit reloc with the right 1 bit assumed to be 0
5378 BFD_RELOC_SCORE_BRANCH
5380 This is a 19-bit reloc with the right 1 bit assumed to be 0
5382 BFD_RELOC_SCORE_IMM30
5384 This is a 32-bit reloc for 48-bit instructions.
5386 BFD_RELOC_SCORE_IMM32
5388 This is a 32-bit reloc for 48-bit instructions.
5390 BFD_RELOC_SCORE16_JMP
5392 This is a 11-bit reloc with the right 1 bit assumed to be 0
5394 BFD_RELOC_SCORE16_BRANCH
5396 This is a 8-bit reloc with the right 1 bit assumed to be 0
5398 BFD_RELOC_SCORE_BCMP
5400 This is a 9-bit reloc with the right 1 bit assumed to be 0
5402 BFD_RELOC_SCORE_GOT15
5404 BFD_RELOC_SCORE_GOT_LO16
5406 BFD_RELOC_SCORE_CALL15
5408 BFD_RELOC_SCORE_DUMMY_HI16
5410 Undocumented Score relocs
5415 Scenix IP2K - 9-bit register number / data address
5419 Scenix IP2K - 4-bit register/data bank number
5421 BFD_RELOC_IP2K_ADDR16CJP
5423 Scenix IP2K - low 13 bits of instruction word address
5425 BFD_RELOC_IP2K_PAGE3
5427 Scenix IP2K - high 3 bits of instruction word address
5429 BFD_RELOC_IP2K_LO8DATA
5431 BFD_RELOC_IP2K_HI8DATA
5433 BFD_RELOC_IP2K_EX8DATA
5435 Scenix IP2K - ext/low/high 8 bits of data address
5437 BFD_RELOC_IP2K_LO8INSN
5439 BFD_RELOC_IP2K_HI8INSN
5441 Scenix IP2K - low/high 8 bits of instruction word address
5443 BFD_RELOC_IP2K_PC_SKIP
5445 Scenix IP2K - even/odd PC modifier to modify snb pcl.0
5449 Scenix IP2K - 16 bit word address in text section.
5451 BFD_RELOC_IP2K_FR_OFFSET
5453 Scenix IP2K - 7-bit sp or dp offset
5455 BFD_RELOC_VPE4KMATH_DATA
5457 BFD_RELOC_VPE4KMATH_INSN
5459 Scenix VPE4K coprocessor - data/insn-space addressing
5462 BFD_RELOC_VTABLE_INHERIT
5464 BFD_RELOC_VTABLE_ENTRY
5466 These two relocations are used by the linker to determine which of
5467 the entries in a C++ virtual function table are actually used. When
5468 the --gc-sections option is given, the linker will zero out the entries
5469 that are not used, so that the code for those functions need not be
5470 included in the output.
5472 VTABLE_INHERIT is a zero-space relocation used to describe to the
5473 linker the inheritance tree of a C++ virtual function table. The
5474 relocation's symbol should be the parent class' vtable, and the
5475 relocation should be located at the child vtable.
5477 VTABLE_ENTRY is a zero-space relocation that describes the use of a
5478 virtual function table entry. The reloc's symbol should refer to the
5479 table of the class mentioned in the code. Off of that base, an offset
5480 describes the entry that is being used. For Rela hosts, this offset
5481 is stored in the reloc's addend. For Rel hosts, we are forced to put
5482 this offset in the reloc's section offset.
5485 BFD_RELOC_IA64_IMM14
5487 BFD_RELOC_IA64_IMM22
5489 BFD_RELOC_IA64_IMM64
5491 BFD_RELOC_IA64_DIR32MSB
5493 BFD_RELOC_IA64_DIR32LSB
5495 BFD_RELOC_IA64_DIR64MSB
5497 BFD_RELOC_IA64_DIR64LSB
5499 BFD_RELOC_IA64_GPREL22
5501 BFD_RELOC_IA64_GPREL64I
5503 BFD_RELOC_IA64_GPREL32MSB
5505 BFD_RELOC_IA64_GPREL32LSB
5507 BFD_RELOC_IA64_GPREL64MSB
5509 BFD_RELOC_IA64_GPREL64LSB
5511 BFD_RELOC_IA64_LTOFF22
5513 BFD_RELOC_IA64_LTOFF64I
5515 BFD_RELOC_IA64_PLTOFF22
5517 BFD_RELOC_IA64_PLTOFF64I
5519 BFD_RELOC_IA64_PLTOFF64MSB
5521 BFD_RELOC_IA64_PLTOFF64LSB
5523 BFD_RELOC_IA64_FPTR64I
5525 BFD_RELOC_IA64_FPTR32MSB
5527 BFD_RELOC_IA64_FPTR32LSB
5529 BFD_RELOC_IA64_FPTR64MSB
5531 BFD_RELOC_IA64_FPTR64LSB
5533 BFD_RELOC_IA64_PCREL21B
5535 BFD_RELOC_IA64_PCREL21BI
5537 BFD_RELOC_IA64_PCREL21M
5539 BFD_RELOC_IA64_PCREL21F
5541 BFD_RELOC_IA64_PCREL22
5543 BFD_RELOC_IA64_PCREL60B
5545 BFD_RELOC_IA64_PCREL64I
5547 BFD_RELOC_IA64_PCREL32MSB
5549 BFD_RELOC_IA64_PCREL32LSB
5551 BFD_RELOC_IA64_PCREL64MSB
5553 BFD_RELOC_IA64_PCREL64LSB
5555 BFD_RELOC_IA64_LTOFF_FPTR22
5557 BFD_RELOC_IA64_LTOFF_FPTR64I
5559 BFD_RELOC_IA64_LTOFF_FPTR32MSB
5561 BFD_RELOC_IA64_LTOFF_FPTR32LSB
5563 BFD_RELOC_IA64_LTOFF_FPTR64MSB
5565 BFD_RELOC_IA64_LTOFF_FPTR64LSB
5567 BFD_RELOC_IA64_SEGREL32MSB
5569 BFD_RELOC_IA64_SEGREL32LSB
5571 BFD_RELOC_IA64_SEGREL64MSB
5573 BFD_RELOC_IA64_SEGREL64LSB
5575 BFD_RELOC_IA64_SECREL32MSB
5577 BFD_RELOC_IA64_SECREL32LSB
5579 BFD_RELOC_IA64_SECREL64MSB
5581 BFD_RELOC_IA64_SECREL64LSB
5583 BFD_RELOC_IA64_REL32MSB
5585 BFD_RELOC_IA64_REL32LSB
5587 BFD_RELOC_IA64_REL64MSB
5589 BFD_RELOC_IA64_REL64LSB
5591 BFD_RELOC_IA64_LTV32MSB
5593 BFD_RELOC_IA64_LTV32LSB
5595 BFD_RELOC_IA64_LTV64MSB
5597 BFD_RELOC_IA64_LTV64LSB
5599 BFD_RELOC_IA64_IPLTMSB
5601 BFD_RELOC_IA64_IPLTLSB
5605 BFD_RELOC_IA64_LTOFF22X
5607 BFD_RELOC_IA64_LDXMOV
5609 BFD_RELOC_IA64_TPREL14
5611 BFD_RELOC_IA64_TPREL22
5613 BFD_RELOC_IA64_TPREL64I
5615 BFD_RELOC_IA64_TPREL64MSB
5617 BFD_RELOC_IA64_TPREL64LSB
5619 BFD_RELOC_IA64_LTOFF_TPREL22
5621 BFD_RELOC_IA64_DTPMOD64MSB
5623 BFD_RELOC_IA64_DTPMOD64LSB
5625 BFD_RELOC_IA64_LTOFF_DTPMOD22
5627 BFD_RELOC_IA64_DTPREL14
5629 BFD_RELOC_IA64_DTPREL22
5631 BFD_RELOC_IA64_DTPREL64I
5633 BFD_RELOC_IA64_DTPREL32MSB
5635 BFD_RELOC_IA64_DTPREL32LSB
5637 BFD_RELOC_IA64_DTPREL64MSB
5639 BFD_RELOC_IA64_DTPREL64LSB
5641 BFD_RELOC_IA64_LTOFF_DTPREL22
5643 Intel IA64 Relocations.
5646 BFD_RELOC_M68HC11_HI8
5648 Motorola 68HC11 reloc.
5649 This is the 8 bit high part of an absolute address.
5651 BFD_RELOC_M68HC11_LO8
5653 Motorola 68HC11 reloc.
5654 This is the 8 bit low part of an absolute address.
5656 BFD_RELOC_M68HC11_3B
5658 Motorola 68HC11 reloc.
5659 This is the 3 bit of a value.
5661 BFD_RELOC_M68HC11_RL_JUMP
5663 Motorola 68HC11 reloc.
5664 This reloc marks the beginning of a jump/call instruction.
5665 It is used for linker relaxation to correctly identify beginning
5666 of instruction and change some branches to use PC-relative
5669 BFD_RELOC_M68HC11_RL_GROUP
5671 Motorola 68HC11 reloc.
5672 This reloc marks a group of several instructions that gcc generates
5673 and for which the linker relaxation pass can modify and/or remove
5676 BFD_RELOC_M68HC11_LO16
5678 Motorola 68HC11 reloc.
5679 This is the 16-bit lower part of an address. It is used for 'call'
5680 instruction to specify the symbol address without any special
5681 transformation (due to memory bank window).
5683 BFD_RELOC_M68HC11_PAGE
5685 Motorola 68HC11 reloc.
5686 This is a 8-bit reloc that specifies the page number of an address.
5687 It is used by 'call' instruction to specify the page number of
5690 BFD_RELOC_M68HC11_24
5692 Motorola 68HC11 reloc.
5693 This is a 24-bit reloc that represents the address with a 16-bit
5694 value and a 8-bit page number. The symbol address is transformed
5695 to follow the 16K memory bank of 68HC12 (seen as mapped in the window).
5697 BFD_RELOC_M68HC12_5B
5699 Motorola 68HC12 reloc.
5700 This is the 5 bits of a value.
5702 BFD_RELOC_XGATE_RL_JUMP
5704 Freescale XGATE reloc.
5705 This reloc marks the beginning of a bra/jal instruction.
5707 BFD_RELOC_XGATE_RL_GROUP
5709 Freescale XGATE reloc.
5710 This reloc marks a group of several instructions that gcc generates
5711 and for which the linker relaxation pass can modify and/or remove
5714 BFD_RELOC_XGATE_LO16
5716 Freescale XGATE reloc.
5717 This is the 16-bit lower part of an address. It is used for the '16-bit'
5720 BFD_RELOC_XGATE_GPAGE
5722 Freescale XGATE reloc.
5726 Freescale XGATE reloc.
5728 BFD_RELOC_XGATE_PCREL_9
5730 Freescale XGATE reloc.
5731 This is a 9-bit pc-relative reloc.
5733 BFD_RELOC_XGATE_PCREL_10
5735 Freescale XGATE reloc.
5736 This is a 10-bit pc-relative reloc.
5738 BFD_RELOC_XGATE_IMM8_LO
5740 Freescale XGATE reloc.
5741 This is the 16-bit lower part of an address. It is used for the '16-bit'
5744 BFD_RELOC_XGATE_IMM8_HI
5746 Freescale XGATE reloc.
5747 This is the 16-bit higher part of an address. It is used for the '16-bit'
5750 BFD_RELOC_XGATE_IMM3
5752 Freescale XGATE reloc.
5753 This is a 3-bit pc-relative reloc.
5755 BFD_RELOC_XGATE_IMM4
5757 Freescale XGATE reloc.
5758 This is a 4-bit pc-relative reloc.
5760 BFD_RELOC_XGATE_IMM5
5762 Freescale XGATE reloc.
5763 This is a 5-bit pc-relative reloc.
5765 BFD_RELOC_M68HC12_9B
5767 Motorola 68HC12 reloc.
5768 This is the 9 bits of a value.
5770 BFD_RELOC_M68HC12_16B
5772 Motorola 68HC12 reloc.
5773 This is the 16 bits of a value.
5775 BFD_RELOC_M68HC12_9_PCREL
5777 Motorola 68HC12/XGATE reloc.
5778 This is a PCREL9 branch.
5780 BFD_RELOC_M68HC12_10_PCREL
5782 Motorola 68HC12/XGATE reloc.
5783 This is a PCREL10 branch.
5785 BFD_RELOC_M68HC12_LO8XG
5787 Motorola 68HC12/XGATE reloc.
5788 This is the 8 bit low part of an absolute address and immediately precedes
5789 a matching HI8XG part.
5791 BFD_RELOC_M68HC12_HI8XG
5793 Motorola 68HC12/XGATE reloc.
5794 This is the 8 bit high part of an absolute address and immediately follows
5795 a matching LO8XG part.
5797 BFD_RELOC_S12Z_15_PCREL
5799 Freescale S12Z reloc.
5800 This is a 15 bit relative address. If the most significant bits are all zero
5801 then it may be truncated to 8 bits.
5806 BFD_RELOC_CR16_NUM16
5808 BFD_RELOC_CR16_NUM32
5810 BFD_RELOC_CR16_NUM32a
5812 BFD_RELOC_CR16_REGREL0
5814 BFD_RELOC_CR16_REGREL4
5816 BFD_RELOC_CR16_REGREL4a
5818 BFD_RELOC_CR16_REGREL14
5820 BFD_RELOC_CR16_REGREL14a
5822 BFD_RELOC_CR16_REGREL16
5824 BFD_RELOC_CR16_REGREL20
5826 BFD_RELOC_CR16_REGREL20a
5828 BFD_RELOC_CR16_ABS20
5830 BFD_RELOC_CR16_ABS24
5836 BFD_RELOC_CR16_IMM16
5838 BFD_RELOC_CR16_IMM20
5840 BFD_RELOC_CR16_IMM24
5842 BFD_RELOC_CR16_IMM32
5844 BFD_RELOC_CR16_IMM32a
5846 BFD_RELOC_CR16_DISP4
5848 BFD_RELOC_CR16_DISP8
5850 BFD_RELOC_CR16_DISP16
5852 BFD_RELOC_CR16_DISP20
5854 BFD_RELOC_CR16_DISP24
5856 BFD_RELOC_CR16_DISP24a
5858 BFD_RELOC_CR16_SWITCH8
5860 BFD_RELOC_CR16_SWITCH16
5862 BFD_RELOC_CR16_SWITCH32
5864 BFD_RELOC_CR16_GOT_REGREL20
5866 BFD_RELOC_CR16_GOTC_REGREL20
5868 BFD_RELOC_CR16_GLOB_DAT
5870 NS CR16 Relocations.
5877 BFD_RELOC_CRX_REL8_CMP
5885 BFD_RELOC_CRX_REGREL12
5887 BFD_RELOC_CRX_REGREL22
5889 BFD_RELOC_CRX_REGREL28
5891 BFD_RELOC_CRX_REGREL32
5907 BFD_RELOC_CRX_SWITCH8
5909 BFD_RELOC_CRX_SWITCH16
5911 BFD_RELOC_CRX_SWITCH32
5916 BFD_RELOC_CRIS_BDISP8
5918 BFD_RELOC_CRIS_UNSIGNED_5
5920 BFD_RELOC_CRIS_SIGNED_6
5922 BFD_RELOC_CRIS_UNSIGNED_6
5924 BFD_RELOC_CRIS_SIGNED_8
5926 BFD_RELOC_CRIS_UNSIGNED_8
5928 BFD_RELOC_CRIS_SIGNED_16
5930 BFD_RELOC_CRIS_UNSIGNED_16
5932 BFD_RELOC_CRIS_LAPCQ_OFFSET
5934 BFD_RELOC_CRIS_UNSIGNED_4
5936 These relocs are only used within the CRIS assembler. They are not
5937 (at present) written to any object files.
5941 BFD_RELOC_CRIS_GLOB_DAT
5943 BFD_RELOC_CRIS_JUMP_SLOT
5945 BFD_RELOC_CRIS_RELATIVE
5947 Relocs used in ELF shared libraries for CRIS.
5949 BFD_RELOC_CRIS_32_GOT
5951 32-bit offset to symbol-entry within GOT.
5953 BFD_RELOC_CRIS_16_GOT
5955 16-bit offset to symbol-entry within GOT.
5957 BFD_RELOC_CRIS_32_GOTPLT
5959 32-bit offset to symbol-entry within GOT, with PLT handling.
5961 BFD_RELOC_CRIS_16_GOTPLT
5963 16-bit offset to symbol-entry within GOT, with PLT handling.
5965 BFD_RELOC_CRIS_32_GOTREL
5967 32-bit offset to symbol, relative to GOT.
5969 BFD_RELOC_CRIS_32_PLT_GOTREL
5971 32-bit offset to symbol with PLT entry, relative to GOT.
5973 BFD_RELOC_CRIS_32_PLT_PCREL
5975 32-bit offset to symbol with PLT entry, relative to this relocation.
5978 BFD_RELOC_CRIS_32_GOT_GD
5980 BFD_RELOC_CRIS_16_GOT_GD
5982 BFD_RELOC_CRIS_32_GD
5986 BFD_RELOC_CRIS_32_DTPREL
5988 BFD_RELOC_CRIS_16_DTPREL
5990 BFD_RELOC_CRIS_32_GOT_TPREL
5992 BFD_RELOC_CRIS_16_GOT_TPREL
5994 BFD_RELOC_CRIS_32_TPREL
5996 BFD_RELOC_CRIS_16_TPREL
5998 BFD_RELOC_CRIS_DTPMOD
6000 BFD_RELOC_CRIS_32_IE
6002 Relocs used in TLS code for CRIS.
6005 BFD_RELOC_OR1K_REL_26
6007 BFD_RELOC_OR1K_SLO16
6009 BFD_RELOC_OR1K_PCREL_PG21
6013 BFD_RELOC_OR1K_SLO13
6015 BFD_RELOC_OR1K_GOTPC_HI16
6017 BFD_RELOC_OR1K_GOTPC_LO16
6019 BFD_RELOC_OR1K_GOT_AHI16
6021 BFD_RELOC_OR1K_GOT16
6023 BFD_RELOC_OR1K_GOT_PG21
6025 BFD_RELOC_OR1K_GOT_LO13
6027 BFD_RELOC_OR1K_PLT26
6029 BFD_RELOC_OR1K_PLTA26
6031 BFD_RELOC_OR1K_GOTOFF_SLO16
6035 BFD_RELOC_OR1K_GLOB_DAT
6037 BFD_RELOC_OR1K_JMP_SLOT
6039 BFD_RELOC_OR1K_RELATIVE
6041 BFD_RELOC_OR1K_TLS_GD_HI16
6043 BFD_RELOC_OR1K_TLS_GD_LO16
6045 BFD_RELOC_OR1K_TLS_GD_PG21
6047 BFD_RELOC_OR1K_TLS_GD_LO13
6049 BFD_RELOC_OR1K_TLS_LDM_HI16
6051 BFD_RELOC_OR1K_TLS_LDM_LO16
6053 BFD_RELOC_OR1K_TLS_LDM_PG21
6055 BFD_RELOC_OR1K_TLS_LDM_LO13
6057 BFD_RELOC_OR1K_TLS_LDO_HI16
6059 BFD_RELOC_OR1K_TLS_LDO_LO16
6061 BFD_RELOC_OR1K_TLS_IE_HI16
6063 BFD_RELOC_OR1K_TLS_IE_AHI16
6065 BFD_RELOC_OR1K_TLS_IE_LO16
6067 BFD_RELOC_OR1K_TLS_IE_PG21
6069 BFD_RELOC_OR1K_TLS_IE_LO13
6071 BFD_RELOC_OR1K_TLS_LE_HI16
6073 BFD_RELOC_OR1K_TLS_LE_AHI16
6075 BFD_RELOC_OR1K_TLS_LE_LO16
6077 BFD_RELOC_OR1K_TLS_LE_SLO16
6079 BFD_RELOC_OR1K_TLS_TPOFF
6081 BFD_RELOC_OR1K_TLS_DTPOFF
6083 BFD_RELOC_OR1K_TLS_DTPMOD
6085 OpenRISC 1000 Relocations.
6088 BFD_RELOC_H8_DIR16A8
6090 BFD_RELOC_H8_DIR16R8
6092 BFD_RELOC_H8_DIR24A8
6094 BFD_RELOC_H8_DIR24R8
6096 BFD_RELOC_H8_DIR32A16
6098 BFD_RELOC_H8_DISP32A16
6103 BFD_RELOC_XSTORMY16_REL_12
6105 BFD_RELOC_XSTORMY16_12
6107 BFD_RELOC_XSTORMY16_24
6109 BFD_RELOC_XSTORMY16_FPTR16
6111 Sony Xstormy16 Relocations.
6116 Self-describing complex relocations.
6120 BFD_RELOC_VAX_GLOB_DAT
6122 BFD_RELOC_VAX_JMP_SLOT
6124 BFD_RELOC_VAX_RELATIVE
6126 Relocations used by VAX ELF.
6131 Morpho MT - 16 bit immediate relocation.
6135 Morpho MT - Hi 16 bits of an address.
6139 Morpho MT - Low 16 bits of an address.
6141 BFD_RELOC_MT_GNU_VTINHERIT
6143 Morpho MT - Used to tell the linker which vtable entries are used.
6145 BFD_RELOC_MT_GNU_VTENTRY
6147 Morpho MT - Used to tell the linker which vtable entries are used.
6149 BFD_RELOC_MT_PCINSN8
6151 Morpho MT - 8 bit immediate relocation.
6154 BFD_RELOC_MSP430_10_PCREL
6156 BFD_RELOC_MSP430_16_PCREL
6160 BFD_RELOC_MSP430_16_PCREL_BYTE
6162 BFD_RELOC_MSP430_16_BYTE
6164 BFD_RELOC_MSP430_2X_PCREL
6166 BFD_RELOC_MSP430_RL_PCREL
6168 BFD_RELOC_MSP430_ABS8
6170 BFD_RELOC_MSP430X_PCR20_EXT_SRC
6172 BFD_RELOC_MSP430X_PCR20_EXT_DST
6174 BFD_RELOC_MSP430X_PCR20_EXT_ODST
6176 BFD_RELOC_MSP430X_ABS20_EXT_SRC
6178 BFD_RELOC_MSP430X_ABS20_EXT_DST
6180 BFD_RELOC_MSP430X_ABS20_EXT_ODST
6182 BFD_RELOC_MSP430X_ABS20_ADR_SRC
6184 BFD_RELOC_MSP430X_ABS20_ADR_DST
6186 BFD_RELOC_MSP430X_PCR16
6188 BFD_RELOC_MSP430X_PCR20_CALL
6190 BFD_RELOC_MSP430X_ABS16
6192 BFD_RELOC_MSP430_ABS_HI16
6194 BFD_RELOC_MSP430_PREL31
6196 BFD_RELOC_MSP430_SYM_DIFF
6198 BFD_RELOC_MSP430_SET_ULEB128
6200 BFD_RELOC_MSP430_SUB_ULEB128
6203 msp430 specific relocation codes
6210 BFD_RELOC_NIOS2_CALL26
6212 BFD_RELOC_NIOS2_IMM5
6214 BFD_RELOC_NIOS2_CACHE_OPX
6216 BFD_RELOC_NIOS2_IMM6
6218 BFD_RELOC_NIOS2_IMM8
6220 BFD_RELOC_NIOS2_HI16
6222 BFD_RELOC_NIOS2_LO16
6224 BFD_RELOC_NIOS2_HIADJ16
6226 BFD_RELOC_NIOS2_GPREL
6228 BFD_RELOC_NIOS2_UJMP
6230 BFD_RELOC_NIOS2_CJMP
6232 BFD_RELOC_NIOS2_CALLR
6234 BFD_RELOC_NIOS2_ALIGN
6236 BFD_RELOC_NIOS2_GOT16
6238 BFD_RELOC_NIOS2_CALL16
6240 BFD_RELOC_NIOS2_GOTOFF_LO
6242 BFD_RELOC_NIOS2_GOTOFF_HA
6244 BFD_RELOC_NIOS2_PCREL_LO
6246 BFD_RELOC_NIOS2_PCREL_HA
6248 BFD_RELOC_NIOS2_TLS_GD16
6250 BFD_RELOC_NIOS2_TLS_LDM16
6252 BFD_RELOC_NIOS2_TLS_LDO16
6254 BFD_RELOC_NIOS2_TLS_IE16
6256 BFD_RELOC_NIOS2_TLS_LE16
6258 BFD_RELOC_NIOS2_TLS_DTPMOD
6260 BFD_RELOC_NIOS2_TLS_DTPREL
6262 BFD_RELOC_NIOS2_TLS_TPREL
6264 BFD_RELOC_NIOS2_COPY
6266 BFD_RELOC_NIOS2_GLOB_DAT
6268 BFD_RELOC_NIOS2_JUMP_SLOT
6270 BFD_RELOC_NIOS2_RELATIVE
6272 BFD_RELOC_NIOS2_GOTOFF
6274 BFD_RELOC_NIOS2_CALL26_NOAT
6276 BFD_RELOC_NIOS2_GOT_LO
6278 BFD_RELOC_NIOS2_GOT_HA
6280 BFD_RELOC_NIOS2_CALL_LO
6282 BFD_RELOC_NIOS2_CALL_HA
6284 BFD_RELOC_NIOS2_R2_S12
6286 BFD_RELOC_NIOS2_R2_I10_1_PCREL
6288 BFD_RELOC_NIOS2_R2_T1I7_1_PCREL
6290 BFD_RELOC_NIOS2_R2_T1I7_2
6292 BFD_RELOC_NIOS2_R2_T2I4
6294 BFD_RELOC_NIOS2_R2_T2I4_1
6296 BFD_RELOC_NIOS2_R2_T2I4_2
6298 BFD_RELOC_NIOS2_R2_X1I7_2
6300 BFD_RELOC_NIOS2_R2_X2L5
6302 BFD_RELOC_NIOS2_R2_F1I5_2
6304 BFD_RELOC_NIOS2_R2_L5I4X1
6306 BFD_RELOC_NIOS2_R2_T1X1I6
6308 BFD_RELOC_NIOS2_R2_T1X1I6_2
6310 Relocations used by the Altera Nios II core.
6315 PRU LDI 16-bit unsigned data-memory relocation.
6317 BFD_RELOC_PRU_U16_PMEMIMM
6319 PRU LDI 16-bit unsigned instruction-memory relocation.
6323 PRU relocation for two consecutive LDI load instructions that load a
6324 32 bit value into a register. If the higher bits are all zero, then
6325 the second instruction may be relaxed.
6327 BFD_RELOC_PRU_S10_PCREL
6329 PRU QBBx 10-bit signed PC-relative relocation.
6331 BFD_RELOC_PRU_U8_PCREL
6333 PRU 8-bit unsigned relocation used for the LOOP instruction.
6335 BFD_RELOC_PRU_32_PMEM
6337 BFD_RELOC_PRU_16_PMEM
6339 PRU Program Memory relocations. Used to convert from byte addressing to
6340 32-bit word addressing.
6342 BFD_RELOC_PRU_GNU_DIFF8
6344 BFD_RELOC_PRU_GNU_DIFF16
6346 BFD_RELOC_PRU_GNU_DIFF32
6348 BFD_RELOC_PRU_GNU_DIFF16_PMEM
6350 BFD_RELOC_PRU_GNU_DIFF32_PMEM
6352 PRU relocations to mark the difference of two local symbols.
6353 These are only needed to support linker relaxation and can be ignored
6354 when not relaxing. The field is set to the value of the difference
6355 assuming no relaxation. The relocation encodes the position of the
6356 second symbol so the linker can determine whether to adjust the field
6357 value. The PMEM variants encode the word difference, instead of byte
6358 difference between symbols.
6361 BFD_RELOC_IQ2000_OFFSET_16
6363 BFD_RELOC_IQ2000_OFFSET_21
6365 BFD_RELOC_IQ2000_UHI16
6370 BFD_RELOC_XTENSA_RTLD
6372 Special Xtensa relocation used only by PLT entries in ELF shared
6373 objects to indicate that the runtime linker should set the value
6374 to one of its own internal functions or data structures.
6376 BFD_RELOC_XTENSA_GLOB_DAT
6378 BFD_RELOC_XTENSA_JMP_SLOT
6380 BFD_RELOC_XTENSA_RELATIVE
6382 Xtensa relocations for ELF shared objects.
6384 BFD_RELOC_XTENSA_PLT
6386 Xtensa relocation used in ELF object files for symbols that may require
6387 PLT entries. Otherwise, this is just a generic 32-bit relocation.
6389 BFD_RELOC_XTENSA_DIFF8
6391 BFD_RELOC_XTENSA_DIFF16
6393 BFD_RELOC_XTENSA_DIFF32
6395 Xtensa relocations for backward compatibility. These have been replaced
6396 by BFD_RELOC_XTENSA_PDIFF and BFD_RELOC_XTENSA_NDIFF.
6397 Xtensa relocations to mark the difference of two local symbols.
6398 These are only needed to support linker relaxation and can be ignored
6399 when not relaxing. The field is set to the value of the difference
6400 assuming no relaxation. The relocation encodes the position of the
6401 first symbol so the linker can determine whether to adjust the field
6404 BFD_RELOC_XTENSA_SLOT0_OP
6406 BFD_RELOC_XTENSA_SLOT1_OP
6408 BFD_RELOC_XTENSA_SLOT2_OP
6410 BFD_RELOC_XTENSA_SLOT3_OP
6412 BFD_RELOC_XTENSA_SLOT4_OP
6414 BFD_RELOC_XTENSA_SLOT5_OP
6416 BFD_RELOC_XTENSA_SLOT6_OP
6418 BFD_RELOC_XTENSA_SLOT7_OP
6420 BFD_RELOC_XTENSA_SLOT8_OP
6422 BFD_RELOC_XTENSA_SLOT9_OP
6424 BFD_RELOC_XTENSA_SLOT10_OP
6426 BFD_RELOC_XTENSA_SLOT11_OP
6428 BFD_RELOC_XTENSA_SLOT12_OP
6430 BFD_RELOC_XTENSA_SLOT13_OP
6432 BFD_RELOC_XTENSA_SLOT14_OP
6434 Generic Xtensa relocations for instruction operands. Only the slot
6435 number is encoded in the relocation. The relocation applies to the
6436 last PC-relative immediate operand, or if there are no PC-relative
6437 immediates, to the last immediate operand.
6439 BFD_RELOC_XTENSA_SLOT0_ALT
6441 BFD_RELOC_XTENSA_SLOT1_ALT
6443 BFD_RELOC_XTENSA_SLOT2_ALT
6445 BFD_RELOC_XTENSA_SLOT3_ALT
6447 BFD_RELOC_XTENSA_SLOT4_ALT
6449 BFD_RELOC_XTENSA_SLOT5_ALT
6451 BFD_RELOC_XTENSA_SLOT6_ALT
6453 BFD_RELOC_XTENSA_SLOT7_ALT
6455 BFD_RELOC_XTENSA_SLOT8_ALT
6457 BFD_RELOC_XTENSA_SLOT9_ALT
6459 BFD_RELOC_XTENSA_SLOT10_ALT
6461 BFD_RELOC_XTENSA_SLOT11_ALT
6463 BFD_RELOC_XTENSA_SLOT12_ALT
6465 BFD_RELOC_XTENSA_SLOT13_ALT
6467 BFD_RELOC_XTENSA_SLOT14_ALT
6469 Alternate Xtensa relocations. Only the slot is encoded in the
6470 relocation. The meaning of these relocations is opcode-specific.
6472 BFD_RELOC_XTENSA_OP0
6474 BFD_RELOC_XTENSA_OP1
6476 BFD_RELOC_XTENSA_OP2
6478 Xtensa relocations for backward compatibility. These have all been
6479 replaced by BFD_RELOC_XTENSA_SLOT0_OP.
6481 BFD_RELOC_XTENSA_ASM_EXPAND
6483 Xtensa relocation to mark that the assembler expanded the
6484 instructions from an original target. The expansion size is
6485 encoded in the reloc size.
6487 BFD_RELOC_XTENSA_ASM_SIMPLIFY
6489 Xtensa relocation to mark that the linker should simplify
6490 assembler-expanded instructions. This is commonly used
6491 internally by the linker after analysis of a
6492 BFD_RELOC_XTENSA_ASM_EXPAND.
6494 BFD_RELOC_XTENSA_TLSDESC_FN
6496 BFD_RELOC_XTENSA_TLSDESC_ARG
6498 BFD_RELOC_XTENSA_TLS_DTPOFF
6500 BFD_RELOC_XTENSA_TLS_TPOFF
6502 BFD_RELOC_XTENSA_TLS_FUNC
6504 BFD_RELOC_XTENSA_TLS_ARG
6506 BFD_RELOC_XTENSA_TLS_CALL
6508 Xtensa TLS relocations.
6510 BFD_RELOC_XTENSA_PDIFF8
6512 BFD_RELOC_XTENSA_PDIFF16
6514 BFD_RELOC_XTENSA_PDIFF32
6516 BFD_RELOC_XTENSA_NDIFF8
6518 BFD_RELOC_XTENSA_NDIFF16
6520 BFD_RELOC_XTENSA_NDIFF32
6522 Xtensa relocations to mark the difference of two local symbols.
6523 These are only needed to support linker relaxation and can be ignored
6524 when not relaxing. The field is set to the value of the difference
6525 assuming no relaxation. The relocation encodes the position of the
6526 subtracted symbol so the linker can determine whether to adjust the field
6527 value. PDIFF relocations are used for positive differences, NDIFF
6528 relocations are used for negative differences. The difference value
6529 is treated as unsigned with these relocation types, giving full
6535 8 bit signed offset in (ix+d) or (iy+d).
6539 First 8 bits of multibyte (32, 24 or 16 bit) value.
6543 Second 8 bits of multibyte (32, 24 or 16 bit) value.
6547 Third 8 bits of multibyte (32 or 24 bit) value.
6551 Fourth 8 bits of multibyte (32 bit) value.
6555 Lowest 16 bits of multibyte (32 or 24 bit) value.
6559 Highest 16 bits of multibyte (32 or 24 bit) value.
6563 Like BFD_RELOC_16 but big-endian.
6581 BFD_RELOC_LM32_BRANCH
6583 BFD_RELOC_LM32_16_GOT
6585 BFD_RELOC_LM32_GOTOFF_HI16
6587 BFD_RELOC_LM32_GOTOFF_LO16
6591 BFD_RELOC_LM32_GLOB_DAT
6593 BFD_RELOC_LM32_JMP_SLOT
6595 BFD_RELOC_LM32_RELATIVE
6597 Lattice Mico32 relocations.
6600 BFD_RELOC_MACH_O_SECTDIFF
6602 Difference between two section addreses. Must be followed by a
6603 BFD_RELOC_MACH_O_PAIR.
6605 BFD_RELOC_MACH_O_LOCAL_SECTDIFF
6607 Like BFD_RELOC_MACH_O_SECTDIFF but with a local symbol.
6609 BFD_RELOC_MACH_O_PAIR
6611 Pair of relocation. Contains the first symbol.
6613 BFD_RELOC_MACH_O_SUBTRACTOR32
6615 Symbol will be substracted. Must be followed by a BFD_RELOC_32.
6617 BFD_RELOC_MACH_O_SUBTRACTOR64
6619 Symbol will be substracted. Must be followed by a BFD_RELOC_64.
6622 BFD_RELOC_MACH_O_X86_64_BRANCH32
6624 BFD_RELOC_MACH_O_X86_64_BRANCH8
6626 PCREL relocations. They are marked as branch to create PLT entry if
6629 BFD_RELOC_MACH_O_X86_64_GOT
6631 Used when referencing a GOT entry.
6633 BFD_RELOC_MACH_O_X86_64_GOT_LOAD
6635 Used when loading a GOT entry with movq. It is specially marked so that
6636 the linker could optimize the movq to a leaq if possible.
6638 BFD_RELOC_MACH_O_X86_64_PCREL32_1
6640 Same as BFD_RELOC_32_PCREL but with an implicit -1 addend.
6642 BFD_RELOC_MACH_O_X86_64_PCREL32_2
6644 Same as BFD_RELOC_32_PCREL but with an implicit -2 addend.
6646 BFD_RELOC_MACH_O_X86_64_PCREL32_4
6648 Same as BFD_RELOC_32_PCREL but with an implicit -4 addend.
6650 BFD_RELOC_MACH_O_X86_64_TLV
6652 Used when referencing a TLV entry.
6656 BFD_RELOC_MACH_O_ARM64_ADDEND
6658 Addend for PAGE or PAGEOFF.
6660 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGE21
6662 Relative offset to page of GOT slot.
6664 BFD_RELOC_MACH_O_ARM64_GOT_LOAD_PAGEOFF12
6666 Relative offset within page of GOT slot.
6668 BFD_RELOC_MACH_O_ARM64_POINTER_TO_GOT
6670 Address of a GOT entry.
6673 BFD_RELOC_MICROBLAZE_32_LO
6675 This is a 32 bit reloc for the microblaze that stores the
6676 low 16 bits of a value
6678 BFD_RELOC_MICROBLAZE_32_LO_PCREL
6680 This is a 32 bit pc-relative reloc for the microblaze that
6681 stores the low 16 bits of a value
6683 BFD_RELOC_MICROBLAZE_32_ROSDA
6685 This is a 32 bit reloc for the microblaze that stores a
6686 value relative to the read-only small data area anchor
6688 BFD_RELOC_MICROBLAZE_32_RWSDA
6690 This is a 32 bit reloc for the microblaze that stores a
6691 value relative to the read-write small data area anchor
6693 BFD_RELOC_MICROBLAZE_32_SYM_OP_SYM
6695 This is a 32 bit reloc for the microblaze to handle
6696 expressions of the form "Symbol Op Symbol"
6698 BFD_RELOC_MICROBLAZE_64_NONE
6700 This is a 64 bit reloc that stores the 32 bit pc relative
6701 value in two words (with an imm instruction). No relocation is
6702 done here - only used for relaxing
6704 BFD_RELOC_MICROBLAZE_64_GOTPC
6706 This is a 64 bit reloc that stores the 32 bit pc relative
6707 value in two words (with an imm instruction). The relocation is
6708 PC-relative GOT offset
6710 BFD_RELOC_MICROBLAZE_64_GOT
6712 This is a 64 bit reloc that stores the 32 bit pc relative
6713 value in two words (with an imm instruction). The relocation is
6716 BFD_RELOC_MICROBLAZE_64_PLT
6718 This is a 64 bit reloc that stores the 32 bit pc relative
6719 value in two words (with an imm instruction). The relocation is
6720 PC-relative offset into PLT
6722 BFD_RELOC_MICROBLAZE_64_GOTOFF
6724 This is a 64 bit reloc that stores the 32 bit GOT relative
6725 value in two words (with an imm instruction). The relocation is
6726 relative offset from _GLOBAL_OFFSET_TABLE_
6728 BFD_RELOC_MICROBLAZE_32_GOTOFF
6730 This is a 32 bit reloc that stores the 32 bit GOT relative
6731 value in a word. The relocation is relative offset from
6732 _GLOBAL_OFFSET_TABLE_
6734 BFD_RELOC_MICROBLAZE_COPY
6736 This is used to tell the dynamic linker to copy the value out of
6737 the dynamic object into the runtime process image.
6739 BFD_RELOC_MICROBLAZE_64_TLS
6743 BFD_RELOC_MICROBLAZE_64_TLSGD
6745 This is a 64 bit reloc that stores the 32 bit GOT relative value
6746 of the GOT TLS GD info entry in two words (with an imm instruction). The
6747 relocation is GOT offset.
6749 BFD_RELOC_MICROBLAZE_64_TLSLD
6751 This is a 64 bit reloc that stores the 32 bit GOT relative value
6752 of the GOT TLS LD info entry in two words (with an imm instruction). The
6753 relocation is GOT offset.
6755 BFD_RELOC_MICROBLAZE_32_TLSDTPMOD
6757 This is a 32 bit reloc that stores the Module ID to GOT(n).
6759 BFD_RELOC_MICROBLAZE_32_TLSDTPREL
6761 This is a 32 bit reloc that stores TLS offset to GOT(n+1).
6763 BFD_RELOC_MICROBLAZE_64_TLSDTPREL
6765 This is a 32 bit reloc for storing TLS offset to two words (uses imm
6768 BFD_RELOC_MICROBLAZE_64_TLSGOTTPREL
6770 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6771 to two words (uses imm instruction).
6773 BFD_RELOC_MICROBLAZE_64_TLSTPREL
6775 This is a 64 bit reloc that stores 32-bit thread pointer relative offset
6776 to two words (uses imm instruction).
6778 BFD_RELOC_MICROBLAZE_64_TEXTPCREL
6780 This is a 64 bit reloc that stores the 32 bit pc relative
6781 value in two words (with an imm instruction). The relocation is
6782 PC-relative offset from start of TEXT.
6784 BFD_RELOC_MICROBLAZE_64_TEXTREL
6786 This is a 64 bit reloc that stores the 32 bit offset
6787 value in two words (with an imm instruction). The relocation is
6788 relative offset from start of TEXT.
6790 BFD_RELOC_KVX_RELOC_START
6792 KVX pseudo relocation code to mark the start of the KVX
6793 relocation enumerators. N.B. the order of the enumerators is
6794 important as several tables in the KVX bfd backend are indexed
6795 by these enumerators; make sure they are all synced.";
6799 KVX null relocation code.
6807 BFD_RELOC_KVX_S16_PCREL
6809 BFD_RELOC_KVX_PCREL17
6811 BFD_RELOC_KVX_PCREL27
6813 BFD_RELOC_KVX_32_PCREL
6815 BFD_RELOC_KVX_S37_PCREL_LO10
6817 BFD_RELOC_KVX_S37_PCREL_UP27
6819 BFD_RELOC_KVX_S43_PCREL_LO10
6821 BFD_RELOC_KVX_S43_PCREL_UP27
6823 BFD_RELOC_KVX_S43_PCREL_EX6
6825 BFD_RELOC_KVX_S64_PCREL_LO10
6827 BFD_RELOC_KVX_S64_PCREL_UP27
6829 BFD_RELOC_KVX_S64_PCREL_EX27
6831 BFD_RELOC_KVX_64_PCREL
6835 BFD_RELOC_KVX_S32_LO5
6837 BFD_RELOC_KVX_S32_UP27
6839 BFD_RELOC_KVX_S37_LO10
6841 BFD_RELOC_KVX_S37_UP27
6843 BFD_RELOC_KVX_S37_GOTOFF_LO10
6845 BFD_RELOC_KVX_S37_GOTOFF_UP27
6847 BFD_RELOC_KVX_S43_GOTOFF_LO10
6849 BFD_RELOC_KVX_S43_GOTOFF_UP27
6851 BFD_RELOC_KVX_S43_GOTOFF_EX6
6853 BFD_RELOC_KVX_32_GOTOFF
6855 BFD_RELOC_KVX_64_GOTOFF
6857 BFD_RELOC_KVX_32_GOT
6859 BFD_RELOC_KVX_S37_GOT_LO10
6861 BFD_RELOC_KVX_S37_GOT_UP27
6863 BFD_RELOC_KVX_S43_GOT_LO10
6865 BFD_RELOC_KVX_S43_GOT_UP27
6867 BFD_RELOC_KVX_S43_GOT_EX6
6869 BFD_RELOC_KVX_64_GOT
6871 BFD_RELOC_KVX_GLOB_DAT
6875 BFD_RELOC_KVX_JMP_SLOT
6877 BFD_RELOC_KVX_RELATIVE
6879 BFD_RELOC_KVX_S43_LO10
6881 BFD_RELOC_KVX_S43_UP27
6883 BFD_RELOC_KVX_S43_EX6
6885 BFD_RELOC_KVX_S64_LO10
6887 BFD_RELOC_KVX_S64_UP27
6889 BFD_RELOC_KVX_S64_EX27
6891 BFD_RELOC_KVX_S37_GOTADDR_LO10
6893 BFD_RELOC_KVX_S37_GOTADDR_UP27
6895 BFD_RELOC_KVX_S43_GOTADDR_LO10
6897 BFD_RELOC_KVX_S43_GOTADDR_UP27
6899 BFD_RELOC_KVX_S43_GOTADDR_EX6
6901 BFD_RELOC_KVX_S64_GOTADDR_LO10
6903 BFD_RELOC_KVX_S64_GOTADDR_UP27
6905 BFD_RELOC_KVX_S64_GOTADDR_EX27
6907 BFD_RELOC_KVX_64_DTPMOD
6909 BFD_RELOC_KVX_64_DTPOFF
6911 BFD_RELOC_KVX_S37_TLS_DTPOFF_LO10
6913 BFD_RELOC_KVX_S37_TLS_DTPOFF_UP27
6915 BFD_RELOC_KVX_S43_TLS_DTPOFF_LO10
6917 BFD_RELOC_KVX_S43_TLS_DTPOFF_UP27
6919 BFD_RELOC_KVX_S43_TLS_DTPOFF_EX6
6921 BFD_RELOC_KVX_S37_TLS_GD_LO10
6923 BFD_RELOC_KVX_S37_TLS_GD_UP27
6925 BFD_RELOC_KVX_S43_TLS_GD_LO10
6927 BFD_RELOC_KVX_S43_TLS_GD_UP27
6929 BFD_RELOC_KVX_S43_TLS_GD_EX6
6931 BFD_RELOC_KVX_S37_TLS_LD_LO10
6933 BFD_RELOC_KVX_S37_TLS_LD_UP27
6935 BFD_RELOC_KVX_S43_TLS_LD_LO10
6937 BFD_RELOC_KVX_S43_TLS_LD_UP27
6939 BFD_RELOC_KVX_S43_TLS_LD_EX6
6941 BFD_RELOC_KVX_64_TPOFF
6943 BFD_RELOC_KVX_S37_TLS_IE_LO10
6945 BFD_RELOC_KVX_S37_TLS_IE_UP27
6947 BFD_RELOC_KVX_S43_TLS_IE_LO10
6949 BFD_RELOC_KVX_S43_TLS_IE_UP27
6951 BFD_RELOC_KVX_S43_TLS_IE_EX6
6953 BFD_RELOC_KVX_S37_TLS_LE_LO10
6955 BFD_RELOC_KVX_S37_TLS_LE_UP27
6957 BFD_RELOC_KVX_S43_TLS_LE_LO10
6959 BFD_RELOC_KVX_S43_TLS_LE_UP27
6961 BFD_RELOC_KVX_S43_TLS_LE_EX6
6967 BFD_RELOC_KVX_RELOC_END
6969 KVX pseudo relocation code to mark the end of the KVX
6970 relocation enumerators that have direct mapping to ELF reloc codes.
6971 There are a few more enumerators after this one; those are mainly
6972 used by the KVX assembler for the internal fixup or to select
6973 one of the above enumerators.
6975 BFD_RELOC_AARCH64_RELOC_START
6977 AArch64 pseudo relocation code to mark the start of the AArch64
6978 relocation enumerators. N.B. the order of the enumerators is
6979 important as several tables in the AArch64 bfd backend are indexed
6980 by these enumerators; make sure they are all synced.
6982 BFD_RELOC_AARCH64_NULL
6984 Deprecated AArch64 null relocation code.
6986 BFD_RELOC_AARCH64_NONE
6988 AArch64 null relocation code.
6990 BFD_RELOC_AARCH64_64
6992 BFD_RELOC_AARCH64_32
6994 BFD_RELOC_AARCH64_16
6996 Basic absolute relocations of N bits. These are equivalent to
6997 BFD_RELOC_N and they were added to assist the indexing of the howto
7000 BFD_RELOC_AARCH64_64_PCREL
7002 BFD_RELOC_AARCH64_32_PCREL
7004 BFD_RELOC_AARCH64_16_PCREL
7006 PC-relative relocations. These are equivalent to BFD_RELOC_N_PCREL
7007 and they were added to assist the indexing of the howto table.
7009 BFD_RELOC_AARCH64_MOVW_G0
7011 AArch64 MOV[NZK] instruction with most significant bits 0 to 15
7012 of an unsigned address/value.
7014 BFD_RELOC_AARCH64_MOVW_G0_NC
7016 AArch64 MOV[NZK] instruction with less significant bits 0 to 15 of
7017 an address/value. No overflow checking.
7019 BFD_RELOC_AARCH64_MOVW_G1
7021 AArch64 MOV[NZK] instruction with most significant bits 16 to 31
7022 of an unsigned address/value.
7024 BFD_RELOC_AARCH64_MOVW_G1_NC
7026 AArch64 MOV[NZK] instruction with less significant bits 16 to 31
7027 of an address/value. No overflow checking.
7029 BFD_RELOC_AARCH64_MOVW_G2
7031 AArch64 MOV[NZK] instruction with most significant bits 32 to 47
7032 of an unsigned address/value.
7034 BFD_RELOC_AARCH64_MOVW_G2_NC
7036 AArch64 MOV[NZK] instruction with less significant bits 32 to 47
7037 of an address/value. No overflow checking.
7039 BFD_RELOC_AARCH64_MOVW_G3
7041 AArch64 MOV[NZK] instruction with most signficant bits 48 to 64
7042 of a signed or unsigned address/value.
7044 BFD_RELOC_AARCH64_MOVW_G0_S
7046 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7047 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7050 BFD_RELOC_AARCH64_MOVW_G1_S
7052 AArch64 MOV[NZ] instruction with most significant bits 16 to 31
7053 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7056 BFD_RELOC_AARCH64_MOVW_G2_S
7058 AArch64 MOV[NZ] instruction with most significant bits 32 to 47
7059 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7062 BFD_RELOC_AARCH64_MOVW_PREL_G0
7064 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7065 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7068 BFD_RELOC_AARCH64_MOVW_PREL_G0_NC
7070 AArch64 MOV[NZ] instruction with most significant bits 0 to 15
7071 of a signed value. Changes instruction to MOVZ or MOVN depending on the
7074 BFD_RELOC_AARCH64_MOVW_PREL_G1
7076 AArch64 MOVK instruction with most significant bits 16 to 31
7079 BFD_RELOC_AARCH64_MOVW_PREL_G1_NC
7081 AArch64 MOVK instruction with most significant bits 16 to 31
7084 BFD_RELOC_AARCH64_MOVW_PREL_G2
7086 AArch64 MOVK instruction with most significant bits 32 to 47
7089 BFD_RELOC_AARCH64_MOVW_PREL_G2_NC
7091 AArch64 MOVK instruction with most significant bits 32 to 47
7094 BFD_RELOC_AARCH64_MOVW_PREL_G3
7096 AArch64 MOVK instruction with most significant bits 47 to 63
7099 BFD_RELOC_AARCH64_LD_LO19_PCREL
7101 AArch64 Load Literal instruction, holding a 19 bit pc-relative word
7102 offset. The lowest two bits must be zero and are not stored in the
7103 instruction, giving a 21 bit signed byte offset.
7105 BFD_RELOC_AARCH64_ADR_LO21_PCREL
7107 AArch64 ADR instruction, holding a simple 21 bit pc-relative byte offset.
7109 BFD_RELOC_AARCH64_ADR_HI21_PCREL
7111 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7112 offset, giving a 4KB aligned page base address.
7114 BFD_RELOC_AARCH64_ADR_HI21_NC_PCREL
7116 AArch64 ADRP instruction, with bits 12 to 32 of a pc-relative page
7117 offset, giving a 4KB aligned page base address, but with no overflow
7120 BFD_RELOC_AARCH64_ADD_LO12
7122 AArch64 ADD immediate instruction, holding bits 0 to 11 of the address.
7123 Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7125 BFD_RELOC_AARCH64_LDST8_LO12
7127 AArch64 8-bit load/store instruction, holding bits 0 to 11 of the
7128 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7130 BFD_RELOC_AARCH64_TSTBR14
7132 AArch64 14 bit pc-relative test bit and branch.
7133 The lowest two bits must be zero and are not stored in the instruction,
7134 giving a 16 bit signed byte offset.
7136 BFD_RELOC_AARCH64_BRANCH19
7138 AArch64 19 bit pc-relative conditional branch and compare & branch.
7139 The lowest two bits must be zero and are not stored in the instruction,
7140 giving a 21 bit signed byte offset.
7142 BFD_RELOC_AARCH64_JUMP26
7144 AArch64 26 bit pc-relative unconditional branch.
7145 The lowest two bits must be zero and are not stored in the instruction,
7146 giving a 28 bit signed byte offset.
7148 BFD_RELOC_AARCH64_CALL26
7150 AArch64 26 bit pc-relative unconditional branch and link.
7151 The lowest two bits must be zero and are not stored in the instruction,
7152 giving a 28 bit signed byte offset.
7154 BFD_RELOC_AARCH64_LDST16_LO12
7156 AArch64 16-bit load/store instruction, holding bits 0 to 11 of the
7157 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7159 BFD_RELOC_AARCH64_LDST32_LO12
7161 AArch64 32-bit load/store instruction, holding bits 0 to 11 of the
7162 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7164 BFD_RELOC_AARCH64_LDST64_LO12
7166 AArch64 64-bit load/store instruction, holding bits 0 to 11 of the
7167 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7169 BFD_RELOC_AARCH64_LDST128_LO12
7171 AArch64 128-bit load/store instruction, holding bits 0 to 11 of the
7172 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7174 BFD_RELOC_AARCH64_GOT_LD_PREL19
7176 AArch64 Load Literal instruction, holding a 19 bit PC relative word
7177 offset of the global offset table entry for a symbol. The lowest two
7178 bits must be zero and are not stored in the instruction, giving a 21
7179 bit signed byte offset. This relocation type requires signed overflow
7182 BFD_RELOC_AARCH64_ADR_GOT_PAGE
7184 Get to the page base of the global offset table entry for a symbol as
7185 part of an ADRP instruction using a 21 bit PC relative value.Used in
7186 conjunction with BFD_RELOC_AARCH64_LD64_GOT_LO12_NC.
7188 BFD_RELOC_AARCH64_LD64_GOT_LO12_NC
7190 Unsigned 12 bit byte offset for 64 bit load/store from the page of
7191 the GOT entry for this symbol. Used in conjunction with
7192 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in LP64 ABI only.
7194 BFD_RELOC_AARCH64_LD32_GOT_LO12_NC
7196 Unsigned 12 bit byte offset for 32 bit load/store from the page of
7197 the GOT entry for this symbol. Used in conjunction with
7198 BFD_RELOC_AARCH64_ADR_GOT_PAGE. Valid in ILP32 ABI only.
7200 BFD_RELOC_AARCH64_MOVW_GOTOFF_G0_NC
7202 Unsigned 16 bit byte offset for 64 bit load/store from the GOT entry
7203 for this symbol. Valid in LP64 ABI only.
7205 BFD_RELOC_AARCH64_MOVW_GOTOFF_G1
7207 Unsigned 16 bit byte higher offset for 64 bit load/store from the GOT entry
7208 for this symbol. Valid in LP64 ABI only.
7210 BFD_RELOC_AARCH64_LD64_GOTOFF_LO15
7212 Unsigned 15 bit byte offset for 64 bit load/store from the page of
7213 the GOT entry for this symbol. Valid in LP64 ABI only.
7215 BFD_RELOC_AARCH64_LD32_GOTPAGE_LO14
7217 Scaled 14 bit byte offset to the page base of the global offset table.
7219 BFD_RELOC_AARCH64_LD64_GOTPAGE_LO15
7221 Scaled 15 bit byte offset to the page base of the global offset table.
7223 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21
7225 Get to the page base of the global offset table entry for a symbols
7226 tls_index structure as part of an adrp instruction using a 21 bit PC
7227 relative value. Used in conjunction with
7228 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC.
7230 BFD_RELOC_AARCH64_TLSGD_ADR_PREL21
7232 AArch64 TLS General Dynamic
7234 BFD_RELOC_AARCH64_TLSGD_ADD_LO12_NC
7236 Unsigned 12 bit byte offset to global offset table entry for a symbols
7237 tls_index structure. Used in conjunction with
7238 BFD_RELOC_AARCH64_TLSGD_ADR_PAGE21.
7240 BFD_RELOC_AARCH64_TLSGD_MOVW_G0_NC
7242 AArch64 TLS General Dynamic relocation.
7244 BFD_RELOC_AARCH64_TLSGD_MOVW_G1
7246 AArch64 TLS General Dynamic relocation.
7248 BFD_RELOC_AARCH64_TLSIE_ADR_GOTTPREL_PAGE21
7250 AArch64 TLS INITIAL EXEC relocation.
7252 BFD_RELOC_AARCH64_TLSIE_LD64_GOTTPREL_LO12_NC
7254 AArch64 TLS INITIAL EXEC relocation.
7256 BFD_RELOC_AARCH64_TLSIE_LD32_GOTTPREL_LO12_NC
7258 AArch64 TLS INITIAL EXEC relocation.
7260 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_PREL19
7262 AArch64 TLS INITIAL EXEC relocation.
7264 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G0_NC
7266 AArch64 TLS INITIAL EXEC relocation.
7268 BFD_RELOC_AARCH64_TLSIE_MOVW_GOTTPREL_G1
7270 AArch64 TLS INITIAL EXEC relocation.
7272 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_HI12
7274 bit[23:12] of byte offset to module TLS base address.
7276 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12
7278 Unsigned 12 bit byte offset to module TLS base address.
7280 BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12_NC
7282 No overflow check version of BFD_RELOC_AARCH64_TLSLD_ADD_DTPREL_LO12.
7284 BFD_RELOC_AARCH64_TLSLD_ADD_LO12_NC
7286 Unsigned 12 bit byte offset to global offset table entry for a symbols
7287 tls_index structure. Used in conjunction with
7288 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21.
7290 BFD_RELOC_AARCH64_TLSLD_ADR_PAGE21
7292 GOT entry page address for AArch64 TLS Local Dynamic, used with ADRP
7295 BFD_RELOC_AARCH64_TLSLD_ADR_PREL21
7297 GOT entry address for AArch64 TLS Local Dynamic, used with ADR instruction.
7299 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12
7301 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7304 BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12_NC
7306 Similar as BFD_RELOC_AARCH64_TLSLD_LDST16_DTPREL_LO12, but no overflow check.
7308 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12
7310 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7313 BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12_NC
7315 Similar as BFD_RELOC_AARCH64_TLSLD_LDST32_DTPREL_LO12, but no overflow check.
7317 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12
7319 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7322 BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12_NC
7324 Similar as BFD_RELOC_AARCH64_TLSLD_LDST64_DTPREL_LO12, but no overflow check.
7326 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12
7328 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7331 BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12_NC
7333 Similar as BFD_RELOC_AARCH64_TLSLD_LDST8_DTPREL_LO12, but no overflow check.
7335 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7337 bit[15:0] of byte offset to module TLS base address.
7339 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0_NC
7341 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G0
7343 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7345 bit[31:16] of byte offset to module TLS base address.
7347 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1_NC
7349 No overflow check version of BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G1
7351 BFD_RELOC_AARCH64_TLSLD_MOVW_DTPREL_G2
7353 bit[47:32] of byte offset to module TLS base address.
7355 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G2
7357 AArch64 TLS LOCAL EXEC relocation.
7359 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1
7361 AArch64 TLS LOCAL EXEC relocation.
7363 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G1_NC
7365 AArch64 TLS LOCAL EXEC relocation.
7367 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0
7369 AArch64 TLS LOCAL EXEC relocation.
7371 BFD_RELOC_AARCH64_TLSLE_MOVW_TPREL_G0_NC
7373 AArch64 TLS LOCAL EXEC relocation.
7375 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_HI12
7377 AArch64 TLS LOCAL EXEC relocation.
7379 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12
7381 AArch64 TLS LOCAL EXEC relocation.
7383 BFD_RELOC_AARCH64_TLSLE_ADD_TPREL_LO12_NC
7385 AArch64 TLS LOCAL EXEC relocation.
7387 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12
7389 bit[11:1] of byte offset to module TLS base address, encoded in ldst
7392 BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12_NC
7394 Similar as BFD_RELOC_AARCH64_TLSLE_LDST16_TPREL_LO12, but no overflow check.
7396 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12
7398 bit[11:2] of byte offset to module TLS base address, encoded in ldst
7401 BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12_NC
7403 Similar as BFD_RELOC_AARCH64_TLSLE_LDST32_TPREL_LO12, but no overflow check.
7405 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12
7407 bit[11:3] of byte offset to module TLS base address, encoded in ldst
7410 BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12_NC
7412 Similar as BFD_RELOC_AARCH64_TLSLE_LDST64_TPREL_LO12, but no overflow check.
7414 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12
7416 bit[11:0] of byte offset to module TLS base address, encoded in ldst
7419 BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12_NC
7421 Similar as BFD_RELOC_AARCH64_TLSLE_LDST8_TPREL_LO12, but no overflow check.
7423 BFD_RELOC_AARCH64_TLSDESC_LD_PREL19
7425 AArch64 TLS DESC relocation.
7427 BFD_RELOC_AARCH64_TLSDESC_ADR_PREL21
7429 AArch64 TLS DESC relocation.
7431 BFD_RELOC_AARCH64_TLSDESC_ADR_PAGE21
7433 AArch64 TLS DESC relocation.
7435 BFD_RELOC_AARCH64_TLSDESC_LD64_LO12
7437 AArch64 TLS DESC relocation.
7439 BFD_RELOC_AARCH64_TLSDESC_LD32_LO12_NC
7441 AArch64 TLS DESC relocation.
7443 BFD_RELOC_AARCH64_TLSDESC_ADD_LO12
7445 AArch64 TLS DESC relocation.
7447 BFD_RELOC_AARCH64_TLSDESC_OFF_G1
7449 AArch64 TLS DESC relocation.
7451 BFD_RELOC_AARCH64_TLSDESC_OFF_G0_NC
7453 AArch64 TLS DESC relocation.
7455 BFD_RELOC_AARCH64_TLSDESC_LDR
7457 AArch64 TLS DESC relocation.
7459 BFD_RELOC_AARCH64_TLSDESC_ADD
7461 AArch64 TLS DESC relocation.
7463 BFD_RELOC_AARCH64_TLSDESC_CALL
7465 AArch64 TLS DESC relocation.
7467 BFD_RELOC_AARCH64_COPY
7469 AArch64 TLS relocation.
7471 BFD_RELOC_AARCH64_GLOB_DAT
7473 AArch64 TLS relocation.
7475 BFD_RELOC_AARCH64_JUMP_SLOT
7477 AArch64 TLS relocation.
7479 BFD_RELOC_AARCH64_RELATIVE
7481 AArch64 TLS relocation.
7483 BFD_RELOC_AARCH64_TLS_DTPMOD
7485 AArch64 TLS relocation.
7487 BFD_RELOC_AARCH64_TLS_DTPREL
7489 AArch64 TLS relocation.
7491 BFD_RELOC_AARCH64_TLS_TPREL
7493 AArch64 TLS relocation.
7495 BFD_RELOC_AARCH64_TLSDESC
7497 AArch64 TLS relocation.
7499 BFD_RELOC_AARCH64_IRELATIVE
7501 AArch64 support for STT_GNU_IFUNC.
7503 BFD_RELOC_AARCH64_RELOC_END
7505 AArch64 pseudo relocation code to mark the end of the AArch64
7506 relocation enumerators that have direct mapping to ELF reloc codes.
7507 There are a few more enumerators after this one; those are mainly
7508 used by the AArch64 assembler for the internal fixup or to select
7509 one of the above enumerators.
7511 BFD_RELOC_AARCH64_GAS_INTERNAL_FIXUP
7513 AArch64 pseudo relocation code to be used internally by the AArch64
7514 assembler and not (currently) written to any object files.
7516 BFD_RELOC_AARCH64_LDST_LO12
7518 AArch64 unspecified load/store instruction, holding bits 0 to 11 of the
7519 address. Used in conjunction with BFD_RELOC_AARCH64_ADR_HI21_PCREL.
7521 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12
7523 AArch64 pseudo relocation code for TLS local dynamic mode. It's to be
7524 used internally by the AArch64 assembler and not (currently) written to
7527 BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12_NC
7529 Similar as BFD_RELOC_AARCH64_TLSLD_LDST_DTPREL_LO12, but no overflow check.
7531 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12
7533 AArch64 pseudo relocation code for TLS local exec mode. It's to be
7534 used internally by the AArch64 assembler and not (currently) written to
7537 BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12_NC
7539 Similar as BFD_RELOC_AARCH64_TLSLE_LDST_TPREL_LO12, but no overflow check.
7541 BFD_RELOC_AARCH64_LD_GOT_LO12_NC
7543 AArch64 pseudo relocation code to be used internally by the AArch64
7544 assembler and not (currently) written to any object files.
7546 BFD_RELOC_AARCH64_TLSIE_LD_GOTTPREL_LO12_NC
7548 AArch64 pseudo relocation code to be used internally by the AArch64
7549 assembler and not (currently) written to any object files.
7551 BFD_RELOC_AARCH64_TLSDESC_LD_LO12_NC
7553 AArch64 pseudo relocation code to be used internally by the AArch64
7554 assembler and not (currently) written to any object files.
7556 BFD_RELOC_TILEPRO_COPY
7558 BFD_RELOC_TILEPRO_GLOB_DAT
7560 BFD_RELOC_TILEPRO_JMP_SLOT
7562 BFD_RELOC_TILEPRO_RELATIVE
7564 BFD_RELOC_TILEPRO_BROFF_X1
7566 BFD_RELOC_TILEPRO_JOFFLONG_X1
7568 BFD_RELOC_TILEPRO_JOFFLONG_X1_PLT
7570 BFD_RELOC_TILEPRO_IMM8_X0
7572 BFD_RELOC_TILEPRO_IMM8_Y0
7574 BFD_RELOC_TILEPRO_IMM8_X1
7576 BFD_RELOC_TILEPRO_IMM8_Y1
7578 BFD_RELOC_TILEPRO_DEST_IMM8_X1
7580 BFD_RELOC_TILEPRO_MT_IMM15_X1
7582 BFD_RELOC_TILEPRO_MF_IMM15_X1
7584 BFD_RELOC_TILEPRO_IMM16_X0
7586 BFD_RELOC_TILEPRO_IMM16_X1
7588 BFD_RELOC_TILEPRO_IMM16_X0_LO
7590 BFD_RELOC_TILEPRO_IMM16_X1_LO
7592 BFD_RELOC_TILEPRO_IMM16_X0_HI
7594 BFD_RELOC_TILEPRO_IMM16_X1_HI
7596 BFD_RELOC_TILEPRO_IMM16_X0_HA
7598 BFD_RELOC_TILEPRO_IMM16_X1_HA
7600 BFD_RELOC_TILEPRO_IMM16_X0_PCREL
7602 BFD_RELOC_TILEPRO_IMM16_X1_PCREL
7604 BFD_RELOC_TILEPRO_IMM16_X0_LO_PCREL
7606 BFD_RELOC_TILEPRO_IMM16_X1_LO_PCREL
7608 BFD_RELOC_TILEPRO_IMM16_X0_HI_PCREL
7610 BFD_RELOC_TILEPRO_IMM16_X1_HI_PCREL
7612 BFD_RELOC_TILEPRO_IMM16_X0_HA_PCREL
7614 BFD_RELOC_TILEPRO_IMM16_X1_HA_PCREL
7616 BFD_RELOC_TILEPRO_IMM16_X0_GOT
7618 BFD_RELOC_TILEPRO_IMM16_X1_GOT
7620 BFD_RELOC_TILEPRO_IMM16_X0_GOT_LO
7622 BFD_RELOC_TILEPRO_IMM16_X1_GOT_LO
7624 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HI
7626 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HI
7628 BFD_RELOC_TILEPRO_IMM16_X0_GOT_HA
7630 BFD_RELOC_TILEPRO_IMM16_X1_GOT_HA
7632 BFD_RELOC_TILEPRO_MMSTART_X0
7634 BFD_RELOC_TILEPRO_MMEND_X0
7636 BFD_RELOC_TILEPRO_MMSTART_X1
7638 BFD_RELOC_TILEPRO_MMEND_X1
7640 BFD_RELOC_TILEPRO_SHAMT_X0
7642 BFD_RELOC_TILEPRO_SHAMT_X1
7644 BFD_RELOC_TILEPRO_SHAMT_Y0
7646 BFD_RELOC_TILEPRO_SHAMT_Y1
7648 BFD_RELOC_TILEPRO_TLS_GD_CALL
7650 BFD_RELOC_TILEPRO_IMM8_X0_TLS_GD_ADD
7652 BFD_RELOC_TILEPRO_IMM8_X1_TLS_GD_ADD
7654 BFD_RELOC_TILEPRO_IMM8_Y0_TLS_GD_ADD
7656 BFD_RELOC_TILEPRO_IMM8_Y1_TLS_GD_ADD
7658 BFD_RELOC_TILEPRO_TLS_IE_LOAD
7660 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD
7662 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD
7664 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_LO
7666 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_LO
7668 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HI
7670 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HI
7672 BFD_RELOC_TILEPRO_IMM16_X0_TLS_GD_HA
7674 BFD_RELOC_TILEPRO_IMM16_X1_TLS_GD_HA
7676 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE
7678 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE
7680 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_LO
7682 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_LO
7684 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HI
7686 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HI
7688 BFD_RELOC_TILEPRO_IMM16_X0_TLS_IE_HA
7690 BFD_RELOC_TILEPRO_IMM16_X1_TLS_IE_HA
7692 BFD_RELOC_TILEPRO_TLS_DTPMOD32
7694 BFD_RELOC_TILEPRO_TLS_DTPOFF32
7696 BFD_RELOC_TILEPRO_TLS_TPOFF32
7698 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE
7700 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE
7702 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_LO
7704 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_LO
7706 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HI
7708 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HI
7710 BFD_RELOC_TILEPRO_IMM16_X0_TLS_LE_HA
7712 BFD_RELOC_TILEPRO_IMM16_X1_TLS_LE_HA
7714 Tilera TILEPro Relocations.
7716 BFD_RELOC_TILEGX_HW0
7718 BFD_RELOC_TILEGX_HW1
7720 BFD_RELOC_TILEGX_HW2
7722 BFD_RELOC_TILEGX_HW3
7724 BFD_RELOC_TILEGX_HW0_LAST
7726 BFD_RELOC_TILEGX_HW1_LAST
7728 BFD_RELOC_TILEGX_HW2_LAST
7730 BFD_RELOC_TILEGX_COPY
7732 BFD_RELOC_TILEGX_GLOB_DAT
7734 BFD_RELOC_TILEGX_JMP_SLOT
7736 BFD_RELOC_TILEGX_RELATIVE
7738 BFD_RELOC_TILEGX_BROFF_X1
7740 BFD_RELOC_TILEGX_JUMPOFF_X1
7742 BFD_RELOC_TILEGX_JUMPOFF_X1_PLT
7744 BFD_RELOC_TILEGX_IMM8_X0
7746 BFD_RELOC_TILEGX_IMM8_Y0
7748 BFD_RELOC_TILEGX_IMM8_X1
7750 BFD_RELOC_TILEGX_IMM8_Y1
7752 BFD_RELOC_TILEGX_DEST_IMM8_X1
7754 BFD_RELOC_TILEGX_MT_IMM14_X1
7756 BFD_RELOC_TILEGX_MF_IMM14_X1
7758 BFD_RELOC_TILEGX_MMSTART_X0
7760 BFD_RELOC_TILEGX_MMEND_X0
7762 BFD_RELOC_TILEGX_SHAMT_X0
7764 BFD_RELOC_TILEGX_SHAMT_X1
7766 BFD_RELOC_TILEGX_SHAMT_Y0
7768 BFD_RELOC_TILEGX_SHAMT_Y1
7770 BFD_RELOC_TILEGX_IMM16_X0_HW0
7772 BFD_RELOC_TILEGX_IMM16_X1_HW0
7774 BFD_RELOC_TILEGX_IMM16_X0_HW1
7776 BFD_RELOC_TILEGX_IMM16_X1_HW1
7778 BFD_RELOC_TILEGX_IMM16_X0_HW2
7780 BFD_RELOC_TILEGX_IMM16_X1_HW2
7782 BFD_RELOC_TILEGX_IMM16_X0_HW3
7784 BFD_RELOC_TILEGX_IMM16_X1_HW3
7786 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST
7788 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST
7790 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST
7792 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST
7794 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST
7796 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST
7798 BFD_RELOC_TILEGX_IMM16_X0_HW0_PCREL
7800 BFD_RELOC_TILEGX_IMM16_X1_HW0_PCREL
7802 BFD_RELOC_TILEGX_IMM16_X0_HW1_PCREL
7804 BFD_RELOC_TILEGX_IMM16_X1_HW1_PCREL
7806 BFD_RELOC_TILEGX_IMM16_X0_HW2_PCREL
7808 BFD_RELOC_TILEGX_IMM16_X1_HW2_PCREL
7810 BFD_RELOC_TILEGX_IMM16_X0_HW3_PCREL
7812 BFD_RELOC_TILEGX_IMM16_X1_HW3_PCREL
7814 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PCREL
7816 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PCREL
7818 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PCREL
7820 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PCREL
7822 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PCREL
7824 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PCREL
7826 BFD_RELOC_TILEGX_IMM16_X0_HW0_GOT
7828 BFD_RELOC_TILEGX_IMM16_X1_HW0_GOT
7830 BFD_RELOC_TILEGX_IMM16_X0_HW0_PLT_PCREL
7832 BFD_RELOC_TILEGX_IMM16_X1_HW0_PLT_PCREL
7834 BFD_RELOC_TILEGX_IMM16_X0_HW1_PLT_PCREL
7836 BFD_RELOC_TILEGX_IMM16_X1_HW1_PLT_PCREL
7838 BFD_RELOC_TILEGX_IMM16_X0_HW2_PLT_PCREL
7840 BFD_RELOC_TILEGX_IMM16_X1_HW2_PLT_PCREL
7842 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_GOT
7844 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_GOT
7846 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_GOT
7848 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_GOT
7850 BFD_RELOC_TILEGX_IMM16_X0_HW3_PLT_PCREL
7852 BFD_RELOC_TILEGX_IMM16_X1_HW3_PLT_PCREL
7854 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_GD
7856 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_GD
7858 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_LE
7860 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_LE
7862 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_LE
7864 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_LE
7866 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_LE
7868 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_LE
7870 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_GD
7872 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_GD
7874 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_GD
7876 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_GD
7878 BFD_RELOC_TILEGX_IMM16_X0_HW0_TLS_IE
7880 BFD_RELOC_TILEGX_IMM16_X1_HW0_TLS_IE
7882 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_PLT_PCREL
7884 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_PLT_PCREL
7886 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_PLT_PCREL
7888 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_PLT_PCREL
7890 BFD_RELOC_TILEGX_IMM16_X0_HW2_LAST_PLT_PCREL
7892 BFD_RELOC_TILEGX_IMM16_X1_HW2_LAST_PLT_PCREL
7894 BFD_RELOC_TILEGX_IMM16_X0_HW0_LAST_TLS_IE
7896 BFD_RELOC_TILEGX_IMM16_X1_HW0_LAST_TLS_IE
7898 BFD_RELOC_TILEGX_IMM16_X0_HW1_LAST_TLS_IE
7900 BFD_RELOC_TILEGX_IMM16_X1_HW1_LAST_TLS_IE
7902 BFD_RELOC_TILEGX_TLS_DTPMOD64
7904 BFD_RELOC_TILEGX_TLS_DTPOFF64
7906 BFD_RELOC_TILEGX_TLS_TPOFF64
7908 BFD_RELOC_TILEGX_TLS_DTPMOD32
7910 BFD_RELOC_TILEGX_TLS_DTPOFF32
7912 BFD_RELOC_TILEGX_TLS_TPOFF32
7914 BFD_RELOC_TILEGX_TLS_GD_CALL
7916 BFD_RELOC_TILEGX_IMM8_X0_TLS_GD_ADD
7918 BFD_RELOC_TILEGX_IMM8_X1_TLS_GD_ADD
7920 BFD_RELOC_TILEGX_IMM8_Y0_TLS_GD_ADD
7922 BFD_RELOC_TILEGX_IMM8_Y1_TLS_GD_ADD
7924 BFD_RELOC_TILEGX_TLS_IE_LOAD
7926 BFD_RELOC_TILEGX_IMM8_X0_TLS_ADD
7928 BFD_RELOC_TILEGX_IMM8_X1_TLS_ADD
7930 BFD_RELOC_TILEGX_IMM8_Y0_TLS_ADD
7932 BFD_RELOC_TILEGX_IMM8_Y1_TLS_ADD
7934 Tilera TILE-Gx Relocations.
7939 BFD_RELOC_BPF_DISP32
7941 BFD_RELOC_BPF_DISPCALL32
7943 BFD_RELOC_BPF_DISP16
7945 Linux eBPF relocations.
7948 BFD_RELOC_EPIPHANY_SIMM8
7950 Adapteva EPIPHANY - 8 bit signed pc-relative displacement
7952 BFD_RELOC_EPIPHANY_SIMM24
7954 Adapteva EPIPHANY - 24 bit signed pc-relative displacement
7956 BFD_RELOC_EPIPHANY_HIGH
7958 Adapteva EPIPHANY - 16 most-significant bits of absolute address
7960 BFD_RELOC_EPIPHANY_LOW
7962 Adapteva EPIPHANY - 16 least-significant bits of absolute address
7964 BFD_RELOC_EPIPHANY_SIMM11
7966 Adapteva EPIPHANY - 11 bit signed number - add/sub immediate
7968 BFD_RELOC_EPIPHANY_IMM11
7970 Adapteva EPIPHANY - 11 bit sign-magnitude number (ld/st displacement)
7972 BFD_RELOC_EPIPHANY_IMM8
7974 Adapteva EPIPHANY - 8 bit immediate for 16 bit mov instruction.
7977 BFD_RELOC_VISIUM_HI16
7979 BFD_RELOC_VISIUM_LO16
7981 BFD_RELOC_VISIUM_IM16
7983 BFD_RELOC_VISIUM_REL16
7985 BFD_RELOC_VISIUM_HI16_PCREL
7987 BFD_RELOC_VISIUM_LO16_PCREL
7989 BFD_RELOC_VISIUM_IM16_PCREL
7994 BFD_RELOC_WASM32_LEB128
7996 BFD_RELOC_WASM32_LEB128_GOT
7998 BFD_RELOC_WASM32_LEB128_GOT_CODE
8000 BFD_RELOC_WASM32_LEB128_PLT
8002 BFD_RELOC_WASM32_PLT_INDEX
8004 BFD_RELOC_WASM32_ABS32_CODE
8006 BFD_RELOC_WASM32_COPY
8008 BFD_RELOC_WASM32_CODE_POINTER
8010 BFD_RELOC_WASM32_INDEX
8012 BFD_RELOC_WASM32_PLT_SIG
8014 WebAssembly relocations.
8017 BFD_RELOC_CKCORE_NONE
8019 BFD_RELOC_CKCORE_ADDR32
8021 BFD_RELOC_CKCORE_PCREL_IMM8BY4
8023 BFD_RELOC_CKCORE_PCREL_IMM11BY2
8025 BFD_RELOC_CKCORE_PCREL_IMM4BY2
8027 BFD_RELOC_CKCORE_PCREL32
8029 BFD_RELOC_CKCORE_PCREL_JSR_IMM11BY2
8031 BFD_RELOC_CKCORE_GNU_VTINHERIT
8033 BFD_RELOC_CKCORE_GNU_VTENTRY
8035 BFD_RELOC_CKCORE_RELATIVE
8037 BFD_RELOC_CKCORE_COPY
8039 BFD_RELOC_CKCORE_GLOB_DAT
8041 BFD_RELOC_CKCORE_JUMP_SLOT
8043 BFD_RELOC_CKCORE_GOTOFF
8045 BFD_RELOC_CKCORE_GOTPC
8047 BFD_RELOC_CKCORE_GOT32
8049 BFD_RELOC_CKCORE_PLT32
8051 BFD_RELOC_CKCORE_ADDRGOT
8053 BFD_RELOC_CKCORE_ADDRPLT
8055 BFD_RELOC_CKCORE_PCREL_IMM26BY2
8057 BFD_RELOC_CKCORE_PCREL_IMM16BY2
8059 BFD_RELOC_CKCORE_PCREL_IMM16BY4
8061 BFD_RELOC_CKCORE_PCREL_IMM10BY2
8063 BFD_RELOC_CKCORE_PCREL_IMM10BY4
8065 BFD_RELOC_CKCORE_ADDR_HI16
8067 BFD_RELOC_CKCORE_ADDR_LO16
8069 BFD_RELOC_CKCORE_GOTPC_HI16
8071 BFD_RELOC_CKCORE_GOTPC_LO16
8073 BFD_RELOC_CKCORE_GOTOFF_HI16
8075 BFD_RELOC_CKCORE_GOTOFF_LO16
8077 BFD_RELOC_CKCORE_GOT12
8079 BFD_RELOC_CKCORE_GOT_HI16
8081 BFD_RELOC_CKCORE_GOT_LO16
8083 BFD_RELOC_CKCORE_PLT12
8085 BFD_RELOC_CKCORE_PLT_HI16
8087 BFD_RELOC_CKCORE_PLT_LO16
8089 BFD_RELOC_CKCORE_ADDRGOT_HI16
8091 BFD_RELOC_CKCORE_ADDRGOT_LO16
8093 BFD_RELOC_CKCORE_ADDRPLT_HI16
8095 BFD_RELOC_CKCORE_ADDRPLT_LO16
8097 BFD_RELOC_CKCORE_PCREL_JSR_IMM26BY2
8099 BFD_RELOC_CKCORE_TOFFSET_LO16
8101 BFD_RELOC_CKCORE_DOFFSET_LO16
8103 BFD_RELOC_CKCORE_PCREL_IMM18BY2
8105 BFD_RELOC_CKCORE_DOFFSET_IMM18
8107 BFD_RELOC_CKCORE_DOFFSET_IMM18BY2
8109 BFD_RELOC_CKCORE_DOFFSET_IMM18BY4
8111 BFD_RELOC_CKCORE_GOTOFF_IMM18
8113 BFD_RELOC_CKCORE_GOT_IMM18BY4
8115 BFD_RELOC_CKCORE_PLT_IMM18BY4
8117 BFD_RELOC_CKCORE_PCREL_IMM7BY4
8119 BFD_RELOC_CKCORE_TLS_LE32
8121 BFD_RELOC_CKCORE_TLS_IE32
8123 BFD_RELOC_CKCORE_TLS_GD32
8125 BFD_RELOC_CKCORE_TLS_LDM32
8127 BFD_RELOC_CKCORE_TLS_LDO32
8129 BFD_RELOC_CKCORE_TLS_DTPMOD32
8131 BFD_RELOC_CKCORE_TLS_DTPOFF32
8133 BFD_RELOC_CKCORE_TLS_TPOFF32
8135 BFD_RELOC_CKCORE_PCREL_FLRW_IMM8BY4
8137 BFD_RELOC_CKCORE_NOJSRI
8139 BFD_RELOC_CKCORE_CALLGRAPH
8141 BFD_RELOC_CKCORE_IRELATIVE
8143 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM4BY4
8145 BFD_RELOC_CKCORE_PCREL_BLOOP_IMM12BY4
8155 BFD_RELOC_LARCH_TLS_DTPMOD32
8157 BFD_RELOC_LARCH_TLS_DTPREL32
8159 BFD_RELOC_LARCH_TLS_DTPMOD64
8161 BFD_RELOC_LARCH_TLS_DTPREL64
8163 BFD_RELOC_LARCH_TLS_TPREL32
8165 BFD_RELOC_LARCH_TLS_TPREL64
8167 BFD_RELOC_LARCH_MARK_LA
8169 BFD_RELOC_LARCH_MARK_PCREL
8171 BFD_RELOC_LARCH_SOP_PUSH_PCREL
8173 BFD_RELOC_LARCH_SOP_PUSH_ABSOLUTE
8175 BFD_RELOC_LARCH_SOP_PUSH_DUP
8177 BFD_RELOC_LARCH_SOP_PUSH_GPREL
8179 BFD_RELOC_LARCH_SOP_PUSH_TLS_TPREL
8181 BFD_RELOC_LARCH_SOP_PUSH_TLS_GOT
8183 BFD_RELOC_LARCH_SOP_PUSH_TLS_GD
8185 BFD_RELOC_LARCH_SOP_PUSH_PLT_PCREL
8187 BFD_RELOC_LARCH_SOP_ASSERT
8189 BFD_RELOC_LARCH_SOP_NOT
8191 BFD_RELOC_LARCH_SOP_SUB
8193 BFD_RELOC_LARCH_SOP_SL
8195 BFD_RELOC_LARCH_SOP_SR
8197 BFD_RELOC_LARCH_SOP_ADD
8199 BFD_RELOC_LARCH_SOP_AND
8201 BFD_RELOC_LARCH_SOP_IF_ELSE
8203 BFD_RELOC_LARCH_SOP_POP_32_S_10_5
8205 BFD_RELOC_LARCH_SOP_POP_32_U_10_12
8207 BFD_RELOC_LARCH_SOP_POP_32_S_10_12
8209 BFD_RELOC_LARCH_SOP_POP_32_S_10_16
8211 BFD_RELOC_LARCH_SOP_POP_32_S_10_16_S2
8213 BFD_RELOC_LARCH_SOP_POP_32_S_5_20
8215 BFD_RELOC_LARCH_SOP_POP_32_S_0_5_10_16_S2
8217 BFD_RELOC_LARCH_SOP_POP_32_S_0_10_10_16_S2
8219 BFD_RELOC_LARCH_SOP_POP_32_U
8221 BFD_RELOC_LARCH_ADD8
8223 BFD_RELOC_LARCH_ADD16
8225 BFD_RELOC_LARCH_ADD24
8227 BFD_RELOC_LARCH_ADD32
8229 BFD_RELOC_LARCH_ADD64
8231 BFD_RELOC_LARCH_SUB8
8233 BFD_RELOC_LARCH_SUB16
8235 BFD_RELOC_LARCH_SUB24
8237 BFD_RELOC_LARCH_SUB32
8239 BFD_RELOC_LARCH_SUB64
8249 BFD_RELOC_LARCH_ABS_HI20
8251 BFD_RELOC_LARCH_ABS_LO12
8253 BFD_RELOC_LARCH_ABS64_LO20
8255 BFD_RELOC_LARCH_ABS64_HI12
8258 BFD_RELOC_LARCH_PCALA_HI20
8260 BFD_RELOC_LARCH_PCALA_LO12
8262 BFD_RELOC_LARCH_PCALA64_LO20
8264 BFD_RELOC_LARCH_PCALA64_HI12
8267 BFD_RELOC_LARCH_GOT_PC_HI20
8269 BFD_RELOC_LARCH_GOT_PC_LO12
8271 BFD_RELOC_LARCH_GOT64_PC_LO20
8273 BFD_RELOC_LARCH_GOT64_PC_HI12
8275 BFD_RELOC_LARCH_GOT_HI20
8277 BFD_RELOC_LARCH_GOT_LO12
8279 BFD_RELOC_LARCH_GOT64_LO20
8281 BFD_RELOC_LARCH_GOT64_HI12
8284 BFD_RELOC_LARCH_TLS_LE_HI20
8286 BFD_RELOC_LARCH_TLS_LE_LO12
8288 BFD_RELOC_LARCH_TLS_LE64_LO20
8290 BFD_RELOC_LARCH_TLS_LE64_HI12
8292 BFD_RELOC_LARCH_TLS_IE_PC_HI20
8294 BFD_RELOC_LARCH_TLS_IE_PC_LO12
8296 BFD_RELOC_LARCH_TLS_IE64_PC_LO20
8298 BFD_RELOC_LARCH_TLS_IE64_PC_HI12
8300 BFD_RELOC_LARCH_TLS_IE_HI20
8302 BFD_RELOC_LARCH_TLS_IE_LO12
8304 BFD_RELOC_LARCH_TLS_IE64_LO20
8306 BFD_RELOC_LARCH_TLS_IE64_HI12
8308 BFD_RELOC_LARCH_TLS_LD_PC_HI20
8310 BFD_RELOC_LARCH_TLS_LD_HI20
8312 BFD_RELOC_LARCH_TLS_GD_PC_HI20
8314 BFD_RELOC_LARCH_TLS_GD_HI20
8317 BFD_RELOC_LARCH_32_PCREL
8320 BFD_RELOC_LARCH_RELAX
8323 BFD_RELOC_LARCH_DELETE
8326 BFD_RELOC_LARCH_ALIGN
8329 BFD_RELOC_LARCH_PCREL20_S2
8335 BFD_RELOC_LARCH_ADD6
8337 BFD_RELOC_LARCH_SUB6
8340 BFD_RELOC_LARCH_ADD_ULEB128
8342 BFD_RELOC_LARCH_SUB_ULEB128
8345 BFD_RELOC_LARCH_64_PCREL
8354 .typedef enum bfd_reloc_code_real bfd_reloc_code_real_type;
8360 bfd_reloc_type_lookup
8361 bfd_reloc_name_lookup
8364 reloc_howto_type *bfd_reloc_type_lookup
8365 (bfd *abfd, bfd_reloc_code_real_type code);
8366 reloc_howto_type *bfd_reloc_name_lookup
8367 (bfd *abfd, const char *reloc_name);
8370 Return a pointer to a howto structure which, when
8371 invoked, will perform the relocation @var{code} on data from the
8376 bfd_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8378 return BFD_SEND (abfd
, reloc_type_lookup
, (abfd
, code
));
8382 bfd_reloc_name_lookup (bfd
*abfd
, const char *reloc_name
)
8384 return BFD_SEND (abfd
, reloc_name_lookup
, (abfd
, reloc_name
));
8387 static reloc_howto_type bfd_howto_32
=
8388 HOWTO (0, 00, 4, 32, false, 0, complain_overflow_dont
, 0, "VRT32", false, 0xffffffff, 0xffffffff, true);
8392 bfd_default_reloc_type_lookup
8395 reloc_howto_type *bfd_default_reloc_type_lookup
8396 (bfd *abfd, bfd_reloc_code_real_type code);
8399 Provides a default relocation lookup routine for any architecture.
8403 bfd_default_reloc_type_lookup (bfd
*abfd
, bfd_reloc_code_real_type code
)
8405 /* Very limited support is provided for relocs in generic targets
8406 such as elf32-little. FIXME: Should we always return NULL? */
8407 if (code
== BFD_RELOC_CTOR
8408 && bfd_arch_bits_per_address (abfd
) == 32)
8409 return &bfd_howto_32
;
8415 bfd_get_reloc_code_name
8418 const char *bfd_get_reloc_code_name (bfd_reloc_code_real_type code);
8421 Provides a printable name for the supplied relocation code.
8422 Useful mainly for printing error messages.
8426 bfd_get_reloc_code_name (bfd_reloc_code_real_type code
)
8428 if (code
> BFD_RELOC_UNUSED
)
8430 return bfd_reloc_code_real_names
[code
];
8435 bfd_generic_relax_section
8438 bool bfd_generic_relax_section
8441 struct bfd_link_info *,
8445 Provides default handling for relaxing for back ends which
8450 bfd_generic_relax_section (bfd
*abfd ATTRIBUTE_UNUSED
,
8451 asection
*section ATTRIBUTE_UNUSED
,
8452 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
,
8455 if (bfd_link_relocatable (link_info
))
8456 (*link_info
->callbacks
->einfo
)
8457 (_("%P%F: --relax and -r may not be used together\n"));
8465 bfd_generic_gc_sections
8468 bool bfd_generic_gc_sections
8469 (bfd *, struct bfd_link_info *);
8472 Provides default handling for relaxing for back ends which
8473 don't do section gc -- i.e., does nothing.
8477 bfd_generic_gc_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8478 struct bfd_link_info
*info ATTRIBUTE_UNUSED
)
8485 bfd_generic_lookup_section_flags
8488 bool bfd_generic_lookup_section_flags
8489 (struct bfd_link_info *, struct flag_info *, asection *);
8492 Provides default handling for section flags lookup
8493 -- i.e., does nothing.
8494 Returns FALSE if the section should be omitted, otherwise TRUE.
8498 bfd_generic_lookup_section_flags (struct bfd_link_info
*info ATTRIBUTE_UNUSED
,
8499 struct flag_info
*flaginfo
,
8500 asection
*section ATTRIBUTE_UNUSED
)
8502 if (flaginfo
!= NULL
)
8504 _bfd_error_handler (_("INPUT_SECTION_FLAGS are not supported"));
8512 bfd_generic_merge_sections
8515 bool bfd_generic_merge_sections
8516 (bfd *, struct bfd_link_info *);
8519 Provides default handling for SEC_MERGE section merging for back ends
8520 which don't have SEC_MERGE support -- i.e., does nothing.
8524 bfd_generic_merge_sections (bfd
*abfd ATTRIBUTE_UNUSED
,
8525 struct bfd_link_info
*link_info ATTRIBUTE_UNUSED
)
8532 bfd_generic_get_relocated_section_contents
8535 bfd_byte *bfd_generic_get_relocated_section_contents
8537 struct bfd_link_info *link_info,
8538 struct bfd_link_order *link_order,
8544 Provides default handling of relocation effort for back ends
8545 which can't be bothered to do it efficiently.
8549 bfd_generic_get_relocated_section_contents (bfd
*abfd
,
8550 struct bfd_link_info
*link_info
,
8551 struct bfd_link_order
*link_order
,
8556 bfd
*input_bfd
= link_order
->u
.indirect
.section
->owner
;
8557 asection
*input_section
= link_order
->u
.indirect
.section
;
8559 arelent
**reloc_vector
;
8562 reloc_size
= bfd_get_reloc_upper_bound (input_bfd
, input_section
);
8566 /* Read in the section. */
8567 bfd_byte
*orig_data
= data
;
8568 if (!bfd_get_full_section_contents (input_bfd
, input_section
, &data
))
8574 if (reloc_size
== 0)
8577 reloc_vector
= (arelent
**) bfd_malloc (reloc_size
);
8578 if (reloc_vector
== NULL
)
8581 reloc_count
= bfd_canonicalize_reloc (input_bfd
,
8585 if (reloc_count
< 0)
8588 if (reloc_count
> 0)
8592 for (parent
= reloc_vector
; *parent
!= NULL
; parent
++)
8594 char *error_message
= NULL
;
8596 bfd_reloc_status_type r
;
8598 symbol
= *(*parent
)->sym_ptr_ptr
;
8599 /* PR ld/19628: A specially crafted input file
8600 can result in a NULL symbol pointer here. */
8603 link_info
->callbacks
->einfo
8604 /* xgettext:c-format */
8605 (_("%X%P: %pB(%pA): error: relocation for offset %V has no value\n"),
8606 abfd
, input_section
, (* parent
)->address
);
8610 /* Zap reloc field when the symbol is from a discarded
8611 section, ignoring any addend. Do the same when called
8612 from bfd_simple_get_relocated_section_contents for
8613 undefined symbols in debug sections. This is to keep
8614 debug info reasonably sane, in particular so that
8615 DW_FORM_ref_addr to another file's .debug_info isn't
8616 confused with an offset into the current file's
8618 if ((symbol
->section
!= NULL
&& discarded_section (symbol
->section
))
8619 || (symbol
->section
== bfd_und_section_ptr
8620 && (input_section
->flags
& SEC_DEBUGGING
) != 0
8621 && link_info
->input_bfds
== link_info
->output_bfd
))
8624 static reloc_howto_type none_howto
8625 = HOWTO (0, 0, 0, 0, false, 0, complain_overflow_dont
, NULL
,
8626 "unused", false, 0, 0, false);
8628 off
= ((*parent
)->address
8629 * bfd_octets_per_byte (input_bfd
, input_section
));
8630 _bfd_clear_contents ((*parent
)->howto
, input_bfd
,
8631 input_section
, data
, off
);
8632 (*parent
)->sym_ptr_ptr
= bfd_abs_section_ptr
->symbol_ptr_ptr
;
8633 (*parent
)->addend
= 0;
8634 (*parent
)->howto
= &none_howto
;
8638 r
= bfd_perform_relocation (input_bfd
,
8642 relocatable
? abfd
: NULL
,
8647 asection
*os
= input_section
->output_section
;
8649 /* A partial link, so keep the relocs. */
8650 os
->orelocation
[os
->reloc_count
] = *parent
;
8654 if (r
!= bfd_reloc_ok
)
8658 case bfd_reloc_undefined
:
8659 (*link_info
->callbacks
->undefined_symbol
)
8660 (link_info
, bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8661 input_bfd
, input_section
, (*parent
)->address
, true);
8663 case bfd_reloc_dangerous
:
8664 BFD_ASSERT (error_message
!= NULL
);
8665 (*link_info
->callbacks
->reloc_dangerous
)
8666 (link_info
, error_message
,
8667 input_bfd
, input_section
, (*parent
)->address
);
8669 case bfd_reloc_overflow
:
8670 (*link_info
->callbacks
->reloc_overflow
)
8672 bfd_asymbol_name (*(*parent
)->sym_ptr_ptr
),
8673 (*parent
)->howto
->name
, (*parent
)->addend
,
8674 input_bfd
, input_section
, (*parent
)->address
);
8676 case bfd_reloc_outofrange
:
8678 This error can result when processing some partially
8679 complete binaries. Do not abort, but issue an error
8681 link_info
->callbacks
->einfo
8682 /* xgettext:c-format */
8683 (_("%X%P: %pB(%pA): relocation \"%pR\" goes out of range\n"),
8684 abfd
, input_section
, * parent
);
8687 case bfd_reloc_notsupported
:
8689 This error can result when processing a corrupt binary.
8690 Do not abort. Issue an error message instead. */
8691 link_info
->callbacks
->einfo
8692 /* xgettext:c-format */
8693 (_("%X%P: %pB(%pA): relocation \"%pR\" is not supported\n"),
8694 abfd
, input_section
, * parent
);
8698 /* PR 17512; file: 90c2a92e.
8699 Report unexpected results, without aborting. */
8700 link_info
->callbacks
->einfo
8701 /* xgettext:c-format */
8702 (_("%X%P: %pB(%pA): relocation \"%pR\" returns an unrecognized value %x\n"),
8703 abfd
, input_section
, * parent
, r
);
8711 free (reloc_vector
);
8715 free (reloc_vector
);
8716 if (orig_data
== NULL
)
8723 _bfd_generic_set_reloc
8726 void _bfd_generic_set_reloc
8730 unsigned int count);
8733 Installs a new set of internal relocations in SECTION.
8737 _bfd_generic_set_reloc (bfd
*abfd ATTRIBUTE_UNUSED
,
8742 section
->orelocation
= relptr
;
8743 section
->reloc_count
= count
;
8745 section
->flags
|= SEC_RELOC
;
8747 section
->flags
&= ~SEC_RELOC
;
8752 _bfd_unrecognized_reloc
8755 bool _bfd_unrecognized_reloc
8758 unsigned int r_type);
8761 Reports an unrecognized reloc.
8762 Written as a function in order to reduce code duplication.
8763 Returns FALSE so that it can be called from a return statement.
8767 _bfd_unrecognized_reloc (bfd
* abfd
, sec_ptr section
, unsigned int r_type
)
8769 /* xgettext:c-format */
8770 _bfd_error_handler (_("%pB: unrecognized relocation type %#x in section `%pA'"),
8771 abfd
, r_type
, section
);
8773 /* PR 21803: Suggest the most likely cause of this error. */
8774 _bfd_error_handler (_("is this version of the linker - %s - out of date ?"),
8775 BFD_VERSION_STRING
);
8777 bfd_set_error (bfd_error_bad_value
);
8782 _bfd_norelocs_bfd_reloc_type_lookup
8784 bfd_reloc_code_real_type code ATTRIBUTE_UNUSED
)
8786 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8790 _bfd_norelocs_bfd_reloc_name_lookup (bfd
*abfd
,
8791 const char *reloc_name ATTRIBUTE_UNUSED
)
8793 return (reloc_howto_type
*) _bfd_ptr_bfd_null_error (abfd
);
8797 _bfd_nodynamic_canonicalize_dynamic_reloc (bfd
*abfd
,
8798 arelent
**relp ATTRIBUTE_UNUSED
,
8799 asymbol
**symp ATTRIBUTE_UNUSED
)
8801 return _bfd_long_bfd_n1_error (abfd
);