gdb/lm32-tdep.c

   1 /* Target-dependent code for Lattice Mico32 processor, for GDB.
   2    Contributed by Jon Beniston <jon@beniston.com>
   3
   4    Copyright (C) 2009-2023 Free Software Foundation, Inc.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 #include "defs.h"
  22 #include "frame.h"
  23 #include "frame-unwind.h"
  24 #include "frame-base.h"
  25 #include "inferior.h"
  26 #include "dis-asm.h"
  27 #include "symfile.h"
  28 #include "remote.h"
  29 #include "gdbcore.h"
  30 #include "sim/sim-lm32.h"
  31 #include "arch-utils.h"
  32 #include "regcache.h"
  33 #include "trad-frame.h"
  34 #include "reggroups.h"
  35 #include <algorithm>
  36 #include "gdbarch.h"
  37
  38 /* Make cgen names unique to prevent ODR conflicts with other targets.  */
  39 #define GDB_CGEN_REMAP_PREFIX lm32
  40 #include "cgen-remap.h"
  41 #include "opcodes/lm32-desc.h"
  42
  43 /* Macros to extract fields from an instruction.  */
  44 #define LM32_OPCODE(insn)       ((insn >> 26) & 0x3f)
  45 #define LM32_REG0(insn)         ((insn >> 21) & 0x1f)
  46 #define LM32_REG1(insn)         ((insn >> 16) & 0x1f)
  47 #define LM32_REG2(insn)         ((insn >> 11) & 0x1f)
  48 #define LM32_IMM16(insn)        ((((long)insn & 0xffff) << 16) >> 16)
  49
  50 struct lm32_gdbarch_tdep : gdbarch_tdep_base
  51 {
  52   /* gdbarch target dependent data here.  Currently unused for LM32.  */
  53 };
  54
  55 struct lm32_frame_cache
  56 {
  57   /* The frame's base.  Used when constructing a frame ID.  */
  58   CORE_ADDR base;
  59   CORE_ADDR pc;
  60   /* Size of frame.  */
  61   int size;
  62   /* Table indicating the location of each and every register.  */
  63   trad_frame_saved_reg *saved_regs;
  64 };
  65
  66 /* Return whether a given register is in a given group.  */
  67
  68 static int
  69 lm32_register_reggroup_p (struct gdbarch *gdbarch, int regnum,
  70                           const struct reggroup *group)
  71 {
  72   if (group == general_reggroup)
  73     return ((regnum >= SIM_LM32_R0_REGNUM) && (regnum <= SIM_LM32_RA_REGNUM))
  74       || (regnum == SIM_LM32_PC_REGNUM);
  75   else if (group == system_reggroup)
  76     return ((regnum >= SIM_LM32_BA_REGNUM) && (regnum <= SIM_LM32_EA_REGNUM))
  77       || ((regnum >= SIM_LM32_EID_REGNUM) && (regnum <= SIM_LM32_IP_REGNUM));
  78   return default_register_reggroup_p (gdbarch, regnum, group);
  79 }
  80
  81 /* Return a name that corresponds to the given register number.  */
  82
  83 static const char *
  84 lm32_register_name (struct gdbarch *gdbarch, int reg_nr)
  85 {
  86   static const char *register_names[] = {
  87     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
  88     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
  89     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
  90     "r24", "r25", "gp", "fp", "sp", "ra", "ea", "ba",
  91     "PC", "EID", "EBA", "DEBA", "IE", "IM", "IP"
  92   };
  93
  94   gdb_static_assert (ARRAY_SIZE (register_names) == SIM_LM32_NUM_REGS);
  95   return register_names[reg_nr];
  96 }
  97
  98 /* Return type of register.  */
  99
 100 static struct type *
 101 lm32_register_type (struct gdbarch *gdbarch, int reg_nr)
 102 {
 103   return builtin_type (gdbarch)->builtin_int32;
 104 }
 105
 106 /* Return non-zero if a register can't be written.  */
 107
 108 static int
 109 lm32_cannot_store_register (struct gdbarch *gdbarch, int regno)
 110 {
 111   return (regno == SIM_LM32_R0_REGNUM) || (regno == SIM_LM32_EID_REGNUM);
 112 }
 113
 114 /* Analyze a function's prologue.  */
 115
 116 static CORE_ADDR
 117 lm32_analyze_prologue (struct gdbarch *gdbarch,
 118                        CORE_ADDR pc, CORE_ADDR limit,
 119                        struct lm32_frame_cache *info)
 120 {
 121   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 122   unsigned long instruction;
 123
 124   /* Keep reading though instructions, until we come across an instruction
 125      that isn't likely to be part of the prologue.  */
 126   info->size = 0;
 127   for (; pc < limit; pc += 4)
 128     {
 129
 130       /* Read an instruction.  */
 131       instruction = read_memory_integer (pc, 4, byte_order);
 132
 133       if ((LM32_OPCODE (instruction) == OP_SW)
 134           && (LM32_REG0 (instruction) == SIM_LM32_SP_REGNUM))
 135         {
 136           /* Any stack displaced store is likely part of the prologue.
 137              Record that the register is being saved, and the offset
 138              into the stack.  */
 139           info->saved_regs[LM32_REG1 (instruction)].set_addr (LM32_IMM16 (instruction));
 140         }
 141       else if ((LM32_OPCODE (instruction) == OP_ADDI)
 142                && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 143         {
 144           /* An add to the SP is likely to be part of the prologue.
 145              Adjust stack size by whatever the instruction adds to the sp.  */
 146           info->size -= LM32_IMM16 (instruction);
 147         }
 148       else if (                 /* add fp,fp,sp */
 149                 ((LM32_OPCODE (instruction) == OP_ADD)
 150                  && (LM32_REG2 (instruction) == SIM_LM32_FP_REGNUM)
 151                  && (LM32_REG0 (instruction) == SIM_LM32_FP_REGNUM)
 152                  && (LM32_REG1 (instruction) == SIM_LM32_SP_REGNUM))
 153                 /* mv fp,imm */
 154                 || ((LM32_OPCODE (instruction) == OP_ADDI)
 155                     && (LM32_REG1 (instruction) == SIM_LM32_FP_REGNUM)
 156                     && (LM32_REG0 (instruction) == SIM_LM32_R0_REGNUM)))
 157         {
 158           /* Likely to be in the prologue for functions that require
 159              a frame pointer.  */
 160         }
 161       else
 162         {
 163           /* Any other instruction is likely not to be part of the
 164              prologue.  */
 165           break;
 166         }
 167     }
 168
 169   return pc;
 170 }
 171
 172 /* Return PC of first non prologue instruction, for the function at the
 173    specified address.  */
 174
 175 static CORE_ADDR
 176 lm32_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 177 {
 178   CORE_ADDR func_addr, limit_pc;
 179   struct lm32_frame_cache frame_info;
 180   trad_frame_saved_reg saved_regs[SIM_LM32_NUM_REGS];
 181
 182   /* See if we can determine the end of the prologue via the symbol table.
 183      If so, then return either PC, or the PC after the prologue, whichever
 184      is greater.  */
 185   if (find_pc_partial_function (pc, NULL, &func_addr, NULL))
 186     {
 187       CORE_ADDR post_prologue_pc
 188         = skip_prologue_using_sal (gdbarch, func_addr);
 189       if (post_prologue_pc != 0)
 190         return std::max (pc, post_prologue_pc);
 191     }
 192
 193   /* Can't determine prologue from the symbol table, need to examine
 194      instructions.  */
 195
 196   /* Find an upper limit on the function prologue using the debug
 197      information.  If the debug information could not be used to provide
 198      that bound, then use an arbitrary large number as the upper bound.  */
 199   limit_pc = skip_prologue_using_sal (gdbarch, pc);
 200   if (limit_pc == 0)
 201     limit_pc = pc + 100;        /* Magic.  */
 202
 203   frame_info.saved_regs = saved_regs;
 204   return lm32_analyze_prologue (gdbarch, pc, limit_pc, &frame_info);
 205 }
 206
 207 /* Create a breakpoint instruction.  */
 208 constexpr gdb_byte lm32_break_insn[4] = { OP_RAISE << 2, 0, 0, 2 };
 209
 210 typedef BP_MANIPULATION (lm32_break_insn) lm32_breakpoint;
 211
 212
 213 /* Setup registers and stack for faking a call to a function in the
 214    inferior.  */
 215
 216 static CORE_ADDR
 217 lm32_push_dummy_call (struct gdbarch *gdbarch, struct value *function,
 218                       struct regcache *regcache, CORE_ADDR bp_addr,
 219                       int nargs, struct value **args, CORE_ADDR sp,
 220                       function_call_return_method return_method,
 221                       CORE_ADDR struct_addr)
 222 {
 223   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 224   int first_arg_reg = SIM_LM32_R1_REGNUM;
 225   int num_arg_regs = 8;
 226   int i;
 227
 228   /* Set the return address.  */
 229   regcache_cooked_write_signed (regcache, SIM_LM32_RA_REGNUM, bp_addr);
 230
 231   /* If we're returning a large struct, a pointer to the address to
 232      store it at is passed as a first hidden parameter.  */
 233   if (return_method == return_method_struct)
 234     {
 235       regcache_cooked_write_unsigned (regcache, first_arg_reg, struct_addr);
 236       first_arg_reg++;
 237       num_arg_regs--;
 238       sp -= 4;
 239     }
 240
 241   /* Setup parameters.  */
 242   for (i = 0; i < nargs; i++)
 243     {
 244       struct value *arg = args[i];
 245       struct type *arg_type = check_typedef (arg->type ());
 246       gdb_byte *contents;
 247       ULONGEST val;
 248
 249       /* Promote small integer types to int.  */
 250       switch (arg_type->code ())
 251         {
 252         case TYPE_CODE_INT:
 253         case TYPE_CODE_BOOL:
 254         case TYPE_CODE_CHAR:
 255         case TYPE_CODE_RANGE:
 256         case TYPE_CODE_ENUM:
 257           if (arg_type->length () < 4)
 258             {
 259               arg_type = builtin_type (gdbarch)->builtin_int32;
 260               arg = value_cast (arg_type, arg);
 261             }
 262           break;
 263         }
 264
 265       /* FIXME: Handle structures.  */
 266
 267       contents = (gdb_byte *) arg->contents ().data ();
 268       val = extract_unsigned_integer (contents, arg_type->length (),
 269                                       byte_order);
 270
 271       /* First num_arg_regs parameters are passed by registers,
 272          and the rest are passed on the stack.  */
 273       if (i < num_arg_regs)
 274         regcache_cooked_write_unsigned (regcache, first_arg_reg + i, val);
 275       else
 276         {
 277           write_memory_unsigned_integer (sp, arg_type->length (), byte_order,
 278                                          val);
 279           sp -= 4;
 280         }
 281     }
 282
 283   /* Update stack pointer.  */
 284   regcache_cooked_write_signed (regcache, SIM_LM32_SP_REGNUM, sp);
 285
 286   /* Return adjusted stack pointer.  */
 287   return sp;
 288 }
 289
 290 /* Extract return value after calling a function in the inferior.  */
 291
 292 static void
 293 lm32_extract_return_value (struct type *type, struct regcache *regcache,
 294                            gdb_byte *valbuf)
 295 {
 296   struct gdbarch *gdbarch = regcache->arch ();
 297   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 298   ULONGEST l;
 299   CORE_ADDR return_buffer;
 300
 301   if (type->code () != TYPE_CODE_STRUCT
 302       && type->code () != TYPE_CODE_UNION
 303       && type->code () != TYPE_CODE_ARRAY && type->length () <= 4)
 304     {
 305       /* Return value is returned in a single register.  */
 306       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 307       store_unsigned_integer (valbuf, type->length (), byte_order, l);
 308     }
 309   else if ((type->code () == TYPE_CODE_INT) && (type->length () == 8))
 310     {
 311       /* 64-bit values are returned in a register pair.  */
 312       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 313       memcpy (valbuf, &l, 4);
 314       regcache_cooked_read_unsigned (regcache, SIM_LM32_R2_REGNUM, &l);
 315       memcpy (valbuf + 4, &l, 4);
 316     }
 317   else
 318     {
 319       /* Aggregate types greater than a single register are returned
 320          in memory.  FIXME: Unless they are only 2 regs?.  */
 321       regcache_cooked_read_unsigned (regcache, SIM_LM32_R1_REGNUM, &l);
 322       return_buffer = l;
 323       read_memory (return_buffer, valbuf, type->length ());
 324     }
 325 }
 326
 327 /* Write into appropriate registers a function return value of type
 328    TYPE, given in virtual format.  */
 329 static void
 330 lm32_store_return_value (struct type *type, struct regcache *regcache,
 331                          const gdb_byte *valbuf)
 332 {
 333   struct gdbarch *gdbarch = regcache->arch ();
 334   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 335   ULONGEST val;
 336   int len = type->length ();
 337
 338   if (len <= 4)
 339     {
 340       val = extract_unsigned_integer (valbuf, len, byte_order);
 341       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 342     }
 343   else if (len <= 8)
 344     {
 345       val = extract_unsigned_integer (valbuf, 4, byte_order);
 346       regcache_cooked_write_unsigned (regcache, SIM_LM32_R1_REGNUM, val);
 347       val = extract_unsigned_integer (valbuf + 4, len - 4, byte_order);
 348       regcache_cooked_write_unsigned (regcache, SIM_LM32_R2_REGNUM, val);
 349     }
 350   else
 351     error (_("lm32_store_return_value: type length too large."));
 352 }
 353
 354 /* Determine whether a functions return value is in a register or memory.  */
 355 static enum return_value_convention
 356 lm32_return_value (struct gdbarch *gdbarch, struct value *function,
 357                    struct type *valtype, struct regcache *regcache,
 358                    gdb_byte *readbuf, const gdb_byte *writebuf)
 359 {
 360   enum type_code code = valtype->code ();
 361
 362   if (code == TYPE_CODE_STRUCT
 363       || code == TYPE_CODE_UNION
 364       || code == TYPE_CODE_ARRAY || valtype->length () > 8)
 365     return RETURN_VALUE_STRUCT_CONVENTION;
 366
 367   if (readbuf)
 368     lm32_extract_return_value (valtype, regcache, readbuf);
 369   if (writebuf)
 370     lm32_store_return_value (valtype, regcache, writebuf);
 371
 372   return RETURN_VALUE_REGISTER_CONVENTION;
 373 }
 374
 375 /* Put here the code to store, into fi->saved_regs, the addresses of
 376    the saved registers of frame described by FRAME_INFO.  This
 377    includes special registers such as pc and fp saved in special ways
 378    in the stack frame.  sp is even more special: the address we return
 379    for it IS the sp for the next frame.  */
 380
 381 static struct lm32_frame_cache *
 382 lm32_frame_cache (frame_info_ptr this_frame, void **this_prologue_cache)
 383 {
 384   CORE_ADDR current_pc;
 385   ULONGEST prev_sp;
 386   ULONGEST this_base;
 387   struct lm32_frame_cache *info;
 388   int i;
 389
 390   if ((*this_prologue_cache))
 391     return (struct lm32_frame_cache *) (*this_prologue_cache);
 392
 393   info = FRAME_OBSTACK_ZALLOC (struct lm32_frame_cache);
 394   (*this_prologue_cache) = info;
 395   info->saved_regs = trad_frame_alloc_saved_regs (this_frame);
 396
 397   info->pc = get_frame_func (this_frame);
 398   current_pc = get_frame_pc (this_frame);
 399   lm32_analyze_prologue (get_frame_arch (this_frame),
 400                          info->pc, current_pc, info);
 401
 402   /* Compute the frame's base, and the previous frame's SP.  */
 403   this_base = get_frame_register_unsigned (this_frame, SIM_LM32_SP_REGNUM);
 404   prev_sp = this_base + info->size;
 405   info->base = this_base;
 406
 407   /* Convert callee save offsets into addresses.  */
 408   for (i = 0; i < gdbarch_num_regs (get_frame_arch (this_frame)) - 1; i++)
 409     {
 410       if (info->saved_regs[i].is_addr ())
 411         info->saved_regs[i].set_addr (this_base + info->saved_regs[i].addr ());
 412     }
 413
 414   /* The call instruction moves the caller's PC in the callee's RA register.
 415      Since this is an unwind, do the reverse.  Copy the location of RA register
 416      into PC (the address / regnum) so that a request for PC will be
 417      converted into a request for the RA register.  */
 418   info->saved_regs[SIM_LM32_PC_REGNUM] = info->saved_regs[SIM_LM32_RA_REGNUM];
 419
 420   /* The previous frame's SP needed to be computed.  Save the computed
 421      value.  */
 422   info->saved_regs[SIM_LM32_SP_REGNUM].set_value (prev_sp);
 423
 424   return info;
 425 }
 426
 427 static void
 428 lm32_frame_this_id (frame_info_ptr this_frame, void **this_cache,
 429                     struct frame_id *this_id)
 430 {
 431   struct lm32_frame_cache *cache = lm32_frame_cache (this_frame, this_cache);
 432
 433   /* This marks the outermost frame.  */
 434   if (cache->base == 0)
 435     return;
 436
 437   (*this_id) = frame_id_build (cache->base, cache->pc);
 438 }
 439
 440 static struct value *
 441 lm32_frame_prev_register (frame_info_ptr this_frame,
 442                           void **this_prologue_cache, int regnum)
 443 {
 444   struct lm32_frame_cache *info;
 445
 446   info = lm32_frame_cache (this_frame, this_prologue_cache);
 447   return trad_frame_get_prev_register (this_frame, info->saved_regs, regnum);
 448 }
 449
 450 static const struct frame_unwind lm32_frame_unwind = {
 451   "lm32 prologue",
 452   NORMAL_FRAME,
 453   default_frame_unwind_stop_reason,
 454   lm32_frame_this_id,
 455   lm32_frame_prev_register,
 456   NULL,
 457   default_frame_sniffer
 458 };
 459
 460 static CORE_ADDR
 461 lm32_frame_base_address (frame_info_ptr this_frame, void **this_cache)
 462 {
 463   struct lm32_frame_cache *info = lm32_frame_cache (this_frame, this_cache);
 464
 465   return info->base;
 466 }
 467
 468 static const struct frame_base lm32_frame_base = {
 469   &lm32_frame_unwind,
 470   lm32_frame_base_address,
 471   lm32_frame_base_address,
 472   lm32_frame_base_address
 473 };
 474
 475 static CORE_ADDR
 476 lm32_frame_align (struct gdbarch *gdbarch, CORE_ADDR sp)
 477 {
 478   /* Align to the size of an instruction (so that they can safely be
 479      pushed onto the stack.  */
 480   return sp & ~3;
 481 }
 482
 483 static struct gdbarch *
 484 lm32_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 485 {
 486   /* If there is already a candidate, use it.  */
 487   arches = gdbarch_list_lookup_by_info (arches, &info);
 488   if (arches != NULL)
 489     return arches->gdbarch;
 490
 491   /* None found, create a new architecture from the information provided.  */
 492   gdbarch *gdbarch
 493     = gdbarch_alloc (&info, gdbarch_tdep_up (new lm32_gdbarch_tdep));
 494
 495   /* Type sizes.  */
 496   set_gdbarch_short_bit (gdbarch, 16);
 497   set_gdbarch_int_bit (gdbarch, 32);
 498   set_gdbarch_long_bit (gdbarch, 32);
 499   set_gdbarch_long_long_bit (gdbarch, 64);
 500   set_gdbarch_float_bit (gdbarch, 32);
 501   set_gdbarch_double_bit (gdbarch, 64);
 502   set_gdbarch_long_double_bit (gdbarch, 64);
 503   set_gdbarch_ptr_bit (gdbarch, 32);
 504
 505   /* Register info.  */
 506   set_gdbarch_num_regs (gdbarch, SIM_LM32_NUM_REGS);
 507   set_gdbarch_sp_regnum (gdbarch, SIM_LM32_SP_REGNUM);
 508   set_gdbarch_pc_regnum (gdbarch, SIM_LM32_PC_REGNUM);
 509   set_gdbarch_register_name (gdbarch, lm32_register_name);
 510   set_gdbarch_register_type (gdbarch, lm32_register_type);
 511   set_gdbarch_cannot_store_register (gdbarch, lm32_cannot_store_register);
 512
 513   /* Frame info.  */
 514   set_gdbarch_skip_prologue (gdbarch, lm32_skip_prologue);
 515   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 516   set_gdbarch_decr_pc_after_break (gdbarch, 0);
 517   set_gdbarch_frame_args_skip (gdbarch, 0);
 518
 519   /* Frame unwinding.  */
 520   set_gdbarch_frame_align (gdbarch, lm32_frame_align);
 521   frame_base_set_default (gdbarch, &lm32_frame_base);
 522   frame_unwind_append_unwinder (gdbarch, &lm32_frame_unwind);
 523
 524   /* Breakpoints.  */
 525   set_gdbarch_breakpoint_kind_from_pc (gdbarch, lm32_breakpoint::kind_from_pc);
 526   set_gdbarch_sw_breakpoint_from_kind (gdbarch, lm32_breakpoint::bp_from_kind);
 527   set_gdbarch_have_nonsteppable_watchpoint (gdbarch, 1);
 528
 529   /* Calling functions in the inferior.  */
 530   set_gdbarch_push_dummy_call (gdbarch, lm32_push_dummy_call);
 531   set_gdbarch_return_value (gdbarch, lm32_return_value);
 532
 533   set_gdbarch_register_reggroup_p (gdbarch, lm32_register_reggroup_p);
 534
 535   return gdbarch;
 536 }
 537
 538 void _initialize_lm32_tdep ();
 539 void
 540 _initialize_lm32_tdep ()
 541 {
 542   gdbarch_register (bfd_arch_lm32, lm32_gdbarch_init);
 543 }