1 2023-07-30 Nick Clifton <nickc@redhat.com>
3 This is the 2.41 release.
4 * configure: Regenerate.
5 * po/opcodes.pot: Regenerate.
7 2023-07-03 Nick Clifton <nickc@redhat.com>
9 * configure: Regenerate.
10 * po/opcodes.pot: Regenerate.
12 2023-07-03 Nick Clifton <nickc@redhat.com>
16 2023-05-23 Nick Clifton <nickc@redhat.com>
18 * po/sv.po: Updated translation.
20 2023-04-21 Tom Tromey <tromey@adacore.com>
22 * i386-dis.c (OP_J): Check result of get16.
24 2023-04-12 Claudiu Zissulescu <claziss@synopsys.com>
26 * arc-tbl.h: Remove vadds2, vadds2h, vadds4h, vaddsubs,
27 vaddsubs2h, vaddsubs4h, vsubadds, vsubadds2h, vsubadds4h, vsubs2,
28 vsubs2h, and vsubs4h instructions.
30 2023-04-11 Nick Clifton <nickc@redhat.com>
33 * nfp-dis.c (init_nfp6000_priv): Check that the output section
36 2023-03-15 Nick Clifton <nickc@redhat.com>
39 * mep-dis.c: Regenerate.
41 2023-03-15 Nick Clifton <nickc@redhat.com>
44 * arm-dis.c (get_sym_code_type): Check for non-ELF symbols.
46 2023-02-28 Richard Ball <richard.ball@arm.com>
48 * aarch64-opc.c: Add MEC system registers.
50 2023-01-03 Nick Clifton <nickc@redhat.com>
52 * po/de.po: Updated German translation.
53 * po/ro.po: Updated Romainian translation.
54 * po/uk.po: Updated Ukrainian translation.
56 2022-12-31 Nick Clifton <nickc@redhat.com>
58 * 2.40 branch created.
60 2022-11-22 Shahab Vahedi <shahab@synopsys.com>
62 * arc-regs.h: Change isa_config address to 0xc1.
63 isa_config exists for ARC700 and ARCV2 and not ARCALL.
65 2022-10-31 Yoshinori Sato <ysato@users.sourceforge.jp>
67 * rx-decode.opc: Switch arguments of the MVTACGU insn.
68 * rx-decode.c: Regenerate.
70 2022-09-22 Yoshinori Sato <ysato@users.sourceforge.jp>
72 * sh-dis.c (print_insn_sh): Enforce bit7 of LDC Rm,Rn_BANK and STC
73 Rm_BANK,Rn is always 1.
75 2022-07-21 Peter Bergner <bergner@linux.ibm.com>
77 * ppc-opc.c (XACC_MASK, XX3ACC_MASK): New defines.
78 (P_GER_MASK, xxmfacc, xxmtacc, xxsetaccz, xvi8ger4pp, xvi8ger4,
79 xvf16ger2pp, xvf16ger2, xvf32gerpp, xvf32ger, xvi4ger8pp, xvi4ger8,
80 xvi16ger2spp, xvi16ger2s, xvbf16ger2pp, xvbf16ger2, xvf64gerpp,
81 xvf64ger, xvi16ger2, xvf16ger2np, xvf32gernp, xvi8ger4spp, xvi16ger2pp,
82 xvbf16ger2np, xvf64gernp, xvf16ger2pn, xvf32gerpn, xvbf16ger2pn,
83 xvf64gerpn, xvf16ger2nn, xvf32gernn, xvbf16ger2nn, xvf64gernn: Use them.
85 2022-07-18 Claudiu Zissulescu <claziss@synopsys.com>
87 * disassemble.c (disassemble_init_for_target): Set
88 created_styled_output for ARC based targets.
89 * arc-dis.c (find_format_from_table): Use fprintf_styled_ftype
90 instead of fprintf_ftype throughout.
91 (find_format): Likewise.
92 (print_flags): Likewise.
93 (print_insn_arc): Likewise.
95 2022-07-08 Nick Clifton <nickc@redhat.com>
97 * 2.39 branch created.
99 2022-07-04 Marcus Nilsson <brainbomb@gmail.com>
101 * disassemble.c: (disassemble_init_for_target): Set
102 created_styled_output for AVR based targets.
103 * avr-dis.c: (print_insn_avr): Use fprintf_styled_ftype
104 instead of fprintf_ftype throughout.
105 (avr_operand): Pass in and fill disassembler_style when
108 2022-04-07 Andreas Krebbel <krebbel@linux.ibm.com>
110 * s390-mkopc.c (main): Enable z16 as CPU string in the opcode
113 2022-03-16 Simon Marchi <simon.marchi@efficios.com>
115 * configure.ac: Handle bfd_amdgcn_arch.
116 * configure: Re-generate.
118 2022-03-06 Sagar Patel <sagarmp@cs.unc.edu>
119 Maciej W. Rozycki <macro@orcam.me.uk>
121 * mips-opc.c (mips_builtin_opcodes): Fix INSN2_ALIAS annotation
122 for "bal", "beqz", "beqzl", "bnez" and "bnezl" instructions.
123 * micromips-opc.c (micromips_opcodes): Likewise for "beqz" and
126 2022-02-17 Nick Clifton <nickc@redhat.com>
128 * po/sr.po: Updated Serbian translation.
130 2022-02-14 Sergei Trofimovich <siarheit@google.com>
132 * microblaze-opcm.h: Renamed 'fsqrt' to 'microblaze_fsqrt'.
133 * microblaze-opc.h: Follow 'fsqrt' rename.
135 2022-01-24 Nick Clifton <nickc@redhat.com>
137 * po/ro.po: Updated Romanian translation.
138 * po/uk.po: Updated Ukranian translation.
140 2022-01-22 Nick Clifton <nickc@redhat.com>
142 * configure: Regenerate.
143 * po/opcodes.pot: Regenerate.
145 2022-01-22 Nick Clifton <nickc@redhat.com>
147 * 2.38 release branch created.
149 2022-01-17 Nick Clifton <nickc@redhat.com>
151 * Makefile.in: Regenerate.
152 * po/opcodes.pot: Regenerate.
154 2021-12-02 Marcus Nilsson <brainbomb@gmail.com>
156 * avr-dis.c (avr_operand); Pass in disassemble_info and fill
157 in insn_type on branching instructions.
159 2021-11-25 Andrew Burgess <aburgess@redhat.com>
160 Simon Cook <simon.cook@embecosm.com>
162 * riscv-dis.c (enum riscv_option_arg_t): New enum typedef.
163 (riscv_options): New static global.
164 (disassembler_options_riscv): New function.
165 (print_riscv_disassembler_options): Rewrite to use
166 disassembler_options_riscv.
168 2021-11-25 Nick Clifton <nickc@redhat.com>
171 * aarch64-asm.c: Replace assert(0) with real code.
172 * aarch64-dis.c: Likewise.
173 * aarch64-opc.c: Likewise.
175 2021-11-25 Nick Clifton <nickc@redhat.com>
177 * po/fr.po; Updated French translation.
179 2021-10-27 Maciej W. Rozycki <macro@embecosm.com>
181 * Makefile.am: Remove obsolete comment.
182 * configure.ac: Refer `libbfd.la' to link shared BFD library
184 * Makefile.in: Regenerate.
185 * configure: Regenerate.
187 2021-09-27 Nick Alcock <nick.alcock@oracle.com>
189 * configure: Regenerate.
191 2021-09-25 Peter Bergner <bergner@linux.ibm.com>
193 * ppc-opc.c (powerpc_opcodes) <mfppr, mfppr32, mtppr, mtppr32>: Enable
196 2021-09-20 Andrew Burgess <andrew.burgess@embecosm.com>
198 * riscv-dis.c (riscv_disassemble_insn): Print a .%dbyte opcode
199 before an unknown instruction, '%d' is replaced with the
202 2021-09-02 Nick Clifton <nickc@redhat.com>
205 * v850-opc.c (D16): Use BFD_RELOC_V850_LO16_SPLIT_OFFSET in place
208 2021-08-17 Shahab Vahedi <shahab@synopsys.com>
210 * arc-regs.h (DEF): Fix the register numbers.
212 2021-08-10 Nick Clifton <nickc@redhat.com>
214 * po/sr.po: Updated Serbian translation.
216 2021-07-26 Chenghua Xu <xuchenghua@loongson.cn>
218 * mips-dis.c (mips_arch_choices): Correct gs264e bfd_mach.
220 2021-06-07 Andreas Krebbel <krebbel@linux.ibm.com>
222 * s390-opc.txt: Add qpaci.
224 2021-07-03 Nick Clifton <nickc@redhat.com>
226 * configure: Regenerate.
227 * po/opcodes.pot: Regenerate.
229 2021-07-03 Nick Clifton <nickc@redhat.com>
231 * 2.37 release branch created.
233 2021-07-02 Alan Modra <amodra@gmail.com>
235 * nds32-dis.c (nds32_find_reg_keyword): Constify arg and return.
236 (nds32_parse_audio_ext, nds32_parse_opcode): Constify psys_reg.
237 (nds32_field_table, nds32_opcode_table, nds32_keyword_table),
238 (nds32_opcodes, nds32_operand_fields, nds32_keywords),
239 (nds32_keyword_gpr): Move declarations to..
240 * nds32-asm.h: ..here, constifying to match definitions.
242 2021-07-01 Mike Frysinger <vapier@gentoo.org>
244 * Makefile.am (GUILE): New variable.
245 (CGEN): Use $(GUILE).
246 * Makefile.in: Regenerate.
248 2021-07-01 Mike Frysinger <vapier@gentoo.org>
250 * mep-asm.c (macros): Mark static & const.
251 (lookup_macro): Change return & m to const.
252 (expand_macro): Change mac to const.
253 (expand_string): Change pmacro to const.
255 2021-07-01 Mike Frysinger <vapier@gentoo.org>
257 * nds32-asm.c (operand_fields): Rename to ...
258 (nds32_operand_fields): ... this.
259 (keyword_gpr): Rename to ...
260 (nds32_keyword_gpr): ... this.
261 (keyword_usr, keyword_dxr, keyword_sr, keyword_cp, keyword_cpr,
262 keyword_fsr, keyword_fdr, keyword_abdim, keyword_abm,
263 keyword_dpref_st, keyword_cctl_lv, keyword_standby_st,
264 keyword_msync_st, keyword_im5_i, keyword_im5_m, keyword_accumulator,
265 keyword_aridx, keyword_aridx2, keyword_aridxi, keyword_aridxi_mx):
267 (keywords): Rename to ...
268 (nds32_keywords): ... this.
269 * nds32-dis.c: Rename operand_fields to nds32_operand_fields,
270 keywords to nds32_keywords, and keyword_gpr to nds32_keyword_gpr.
272 2021-07-01 Mike Frysinger <vapier@gentoo.org>
274 * z80-dis.c (opc_ed): Make const.
275 (pref_ed): Make p const.
277 2021-07-01 Mike Frysinger <vapier@gentoo.org>
279 * microblaze-dis.c (get_field_special): Make op const.
280 (read_insn_microblaze): Make opr & op const. Rename opcodes to
282 (print_insn_microblaze): Make op & pop const.
283 (get_insn_microblaze): Make op const. Rename opcodes to
285 (microblaze_get_target_address): Likewise.
286 * microblaze-opc.h (struct op_code_struct): Make const.
287 Rename opcodes to microblaze_opcodes.
289 2021-07-01 Mike Frysinger <vapier@gentoo.org>
291 * aarch64-gen.c (aarch64_opcode_table): Add const.
292 * aarch64-tbl.h (aarch64_opcode_table): Likewise.
294 2021-06-22 Andrew Burgess <andrew.burgess@embecosm.com>
296 * cgen-dis.c (count_decodable_bits): Use __builtin_popcount when
299 2021-06-22 Alan Modra <amodra@gmail.com>
301 * pj-dis.c (print_insn_pj): Don't print trailing tab. Do
302 print separator for pcrel insns.
304 2021-06-19 Alan Modra <amodra@gmail.com>
306 * vax-dis.c (print_insn_vax): Avoid pointer overflow.
308 2021-06-19 Alan Modra <amodra@gmail.com>
310 * tic30-dis.c (get_register_operand): Don't ask strncpy to fill
313 2021-06-17 Alan Modra <amodra@gmail.com>
315 * ppc-opc.c (powerpc_opcodes): Move cell db*cyc to proper location
318 2021-06-03 Alan Modra <amodra@gmail.com>
321 * mcore-dis.c (print_insn_mcore): Correct loopt disassembly.
322 Use unsigned int for inst.
324 2021-06-02 Shahab Vahedi <shahab@synopsys.com>
326 * arc-dis.c (arc_option_arg_t): New enumeration.
327 (arc_options): New variable.
328 (disassembler_options_arc): New function.
329 (print_arc_disassembler_options): Reimplement in terms of
330 "disassembler_options_arc".
332 2021-05-29 Alan Modra <amodra@gmail.com>
334 * ppc-dis.c (lookup_powerpc): Test deprecated field when -Many.
335 Don't special case PPC_OPCODE_RAW.
336 (lookup_prefix): Likewise.
337 (lookup_vle, lookup_spe2): Similarly. Add dialect parameter and..
338 (print_insn_powerpc): ..update caller.
339 * ppc-opc.c (EXT): Define.
340 (powerpc_opcodes): Mark extended mnemonics with EXT.
341 (prefix_opcodes, vle_opcodes): Likewise.
342 (XISEL, XISEL_MASK): Add cr field and simplify.
343 (powerpc_opcodes): Use XISEL with extended isel mnemonics and sort
344 all isel variants to where the base mnemonic belongs. Sort dstt,
347 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
349 * mips-opc.c (mips_builtin_opcodes): Reorder legacy COP0, COP2,
350 COP3 opcode instructions.
352 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
354 * mips-opc.c (mips_builtin_opcodes): Update exclusion list for
355 "ldc2", "ldc3", "lwc0", "lwc2", "lwc3", "sdc2", "sdc3", "swc0",
356 "swc2", "swc3", "cfc0", "ctc0", "bc2f", "bc2fl", "bc2t",
357 "bc2tl", "cfc2", "ctc2", "dmfc2", "dmtc2", "mfc2", "mtc2",
358 "bc3f", "bc3fl", "bc3t", "bc3tl", "cfc3", "ctc3", "mfc3",
359 "mtc3", "bc0f", "bc0fl", "bc0t", "bc0tl", "rfe", "c2", "c3",
360 "cop2", and "cop3" entries.
362 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
364 * mips-opc.c (mips_builtin_opcodes): Remove "dmfc3" and "dmtc3"
365 entries and associated comments.
367 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
369 * mips-opc.c (mips_builtin_opcodes): Move the "rfe" entry ahead
372 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
374 * mips-dis.c (mips_cp1_names_mips): New variable.
375 (mips_arch_choices): Use it rather than `mips_cp1_names_numeric'
376 for "r3000", "r4000", "r4010", "vr4100", "vr4111", "vr4120",
377 "r4300", "r4400", "r4600", "r4650", "r5000", "vr5400", "vr5500",
378 "r5900", "r6000", "rm7000", "rm9000", "r8000", "r10000",
379 "r12000", "r14000", "r16000", "mips5", "loongson2e", and
382 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
384 * mips-dis.c (print_reg) <OP_REG_COPRO>: Move control register
385 handling code over to...
386 <OP_REG_CONTROL>: ... this new case.
387 * mips-opc.c (decode_mips_operand) <'g', 'y'>: New cases.
388 (mips_builtin_opcodes): Update "cfc1", "ctc1", "cttc1", "cttc2",
389 "cfc0", "ctc0", "cfc2", "ctc2", "cfc3", and "ctc3" entries
390 replacing the `G' operand code with `g'. Update "cftc1" and
391 "cftc2" entries replacing the `E' operand code with `y'.
392 * micromips-opc.c (decode_micromips_operand) <'g'>: New case.
393 (micromips_opcodes): Update "cfc1", "cfc2", "ctc1", and "ctc2"
394 entries replacing the `G' operand code with `g'.
396 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
398 * mips-dis.c (mips_cp0_names_r3900): New variable.
399 (mips_arch_choices): Use it rather than `mips_cp0_names_numeric'
402 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
404 * mips-opc.c (mips_builtin_opcodes): Switch "cttc2", "mttc2",
405 and "mtthc2" to using the `G' rather than `g' operand code for
406 the coprocessor control register referred.
408 2021-05-29 Maciej W. Rozycki <macro@orcam.me.uk>
410 * micromips-opc.c (micromips_opcodes): Swap the two "dmtc1"
411 entries with each other.
413 2021-05-27 Peter Bergner <bergner@linux.ibm.com>
415 * ppc-opc.c (powerpc_opcodes) <xxmr, xxlnot>: New extended mnemonics.
417 2021-05-25 Alan Modra <amodra@gmail.com>
419 * cris-desc.c: Regenerate.
420 * cris-desc.h: Regenerate.
421 * cris-opc.h: Regenerate.
422 * po/POTFILES.in: Regenerate.
424 2021-05-24 Mike Frysinger <vapier@gentoo.org>
426 * Makefile.am (HFILES): Add cris-desc.h & cris-opc.h.
427 (TARGET_LIBOPCODES_CFILES): Add cris-desc.c.
428 (CGEN_CPUS): Add cris.
430 (stamp-cris): New rule.
431 * cgen.sh: Handle desc action.
432 * configure.ac (bfd_cris_arch): Add cris-desc.lo.
433 * Makefile.in, configure: Regenerate.
435 2021-05-18 Job Noorman <mtvec@pm.me>
438 * riscv-dis.c (riscv_get_disassembler): Get elf attributes only for
441 2021-05-17 Alex Coplan <alex.coplan@arm.com>
443 * arm-dis.c (mve_opcodes): Fix disassembly of
444 MVE_VMOV2_GP_TO_VEC_LANE when idx == 1.
445 (is_mve_encoding_conflict): MVE vector loads should not match
447 (is_mve_unpredictable): It's not unpredictable to use the same
448 source register twice (for MVE_VMOV2_GP_TO_VEC_LANE).
450 2021-05-11 Nick Clifton <nickc@redhat.com>
453 * tic30-dis.c (print_insn_tic30): Prevent attempts to read beyond
454 the end of the code buffer.
456 2021-05-06 Stafford Horne <shorne@gmail.com>
459 * or1k-asm.c: Regenerate.
461 2021-05-01 Max Filippov <jcmvbkbc@gmail.com>
463 * xtensa-dis.c (print_insn_xtensa): Fill in info->insn_type and
464 info->insn_info_valid.
466 2021-04-26 Jan Beulich <jbeulich@suse.com>
468 * i386-opc.tbl (lea): Add Optimize.
469 * opcodes/i386-tbl.h: Re-generate.
471 2020-04-23 Max Filippov <jcmvbkbc@gmail.com>
473 * xtensa-dis.c (print_xtensa_operand): For PC-relative operand
474 of l32r fetch and display referenced literal value.
476 2021-04-23 Max Filippov <jcmvbkbc@gmail.com>
478 * xtensa-dis.c (print_insn_xtensa): Set info->bytes_per_chunk
479 to 4 for literal disassembly.
481 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
483 * aarch64-opc.c: Add new registers (RPAOS, RPALOS, PAALLOS, PAALL) support
484 for TLBI instruction.
486 2021-04-19 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
488 * aarch64-opc.c: Add new register (CIPAPA, CIGDPAPA) support for
491 2021-04-19 Jan Beulich <jbeulich@suse.com>
493 * aarch64-asm.c (encode_asimd_fcvt): Add initializer for
495 (convert_mov_to_movewide): Add initializer for "value".
497 2021-04-16 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
499 * aarch64-opc.c: Add RME system registers.
501 2021-04-16 Lifang Xia <lifang_xia@c-sky.com>
503 * riscv-opc.c (riscv_opcodes): New insn alias for addi. Compress
504 "addi d,CV,z" to "c.mv d,CV".
506 2021-04-12 Alan Modra <amodra@gmail.com>
508 * configure.ac (--enable-checking): Add support.
509 * config.in: Regenerate.
510 * configure: Regenerate.
512 2021-04-09 Tejas Belagod <tejas.belagod@arm.com>
514 * aarch64-tbl.h (struct aarch64_opcode aarch64_opcode_table): Reclassify
515 LD64/ST64 instructions to lse_atomic instead of ldstexcl.
517 2021-04-09 Alan Modra <amodra@gmail.com>
519 * ppc-dis.c (struct dis_private): Add "special".
520 (POWERPC_DIALECT): Delete. Replace uses with..
521 (private_data): ..this. New inline function.
522 (disassemble_init_powerpc): Init "special" names.
523 (skip_optional_operands): Add is_pcrel arg, set when detecting R
524 field of prefix instructions.
525 (bsearch_reloc, print_got_plt): New functions.
526 (print_insn_powerpc): For pcrel instructions, print target address
527 and symbol if known, and decode plt and got loads too.
529 2021-04-08 Alan Modra <amodra@gmail.com>
532 * ppc-opc.c (powerpc_opcodes): Correct usprg typos, add mfpir.
534 2021-04-08 Alan Modra <amodra@gmail.com>
537 * ppc-opc.c (DCBT_EO): Move earlier.
538 (insert_thct, extract_thct, insert_thds, extract_thds): New functions.
539 (powerpc_operands): Add THCT and THDS entries.
540 (powerpc_opcodes): Add dcbtstct, dcbtstds, dcbna, dcbtct, dcbtds.
542 2021-04-06 Alan Modra <amodra@gmail.com>
544 * dis-buf.c (generic_symbol_at_address): Return symbol* NULL.
545 * s12z-dis.c (decode_possible_symbol): Use symbol returned from
546 symbol_at_address_func.
548 2021-04-05 Alan Modra <amodra@gmail.com>
550 * configure.ac: Don't check for limits.h, string.h, strings.h or
552 (AC_ISC_POSIX): Don't invoke.
553 * sysdep.h: Include stdlib.h and string.h unconditionally.
554 * i386-opc.h: Include limits.h unconditionally.
555 * wasm32-dis.c: Likewise.
556 * cgen-opc.c: Don't include alloca-conf.h.
557 * config.in: Regenerate.
558 * configure: Regenerate.
560 2021-04-01 Martin Liska <mliska@suse.cz>
562 * arm-dis.c (strneq): Remove strneq and use startswith.
563 * cr16-dis.c (print_insn_cr16): Likewise.
564 * score-dis.c (streq): Likewise.
566 * score7-dis.c (strneq): Likewise.
568 2021-04-01 Alan Modra <amodra@gmail.com>
571 * ppc-opc.c (powerpc_opcodes): Add mfummcr2 and mfmmcr2.
573 2021-03-31 Alan Modra <amodra@gmail.com>
575 * sysdep.h (POISON_BFD_BOOLEAN): Define.
576 * aarch64-asm-2.c, * aarch64-asm.c, * aarch64-asm.h,
577 * aarch64-dis-2.c, * aarch64-dis.c, * aarch64-dis.h,
578 * aarch64-gen.c, * aarch64-opc.c, * aarch64-opc.h, * arc-dis.c,
579 * arc-dis.h, * arc-fxi.h, * arc-opc.c, * arm-dis.c, * bfin-dis.c,
580 * cris-dis.c, * csky-dis.c, * csky-opc.h, * dis-buf.c,
581 * disassemble.c, * frv-opc.c, * frv-opc.h, * h8300-dis.c,
582 * i386-dis.c, * m68k-dis.c, * metag-dis.c, * microblaze-dis.c,
583 * microblaze-dis.h, * micromips-opc.c, * mips-dis.c,
584 * mips-formats.h, * mips-opc.c, * mips16-opc.c, * mmix-dis.c,
585 * msp430-dis.c, * nds32-dis.c, * nfp-dis.c, * nios2-dis.c,
586 * ppc-dis.c, * riscv-dis.c, * score-dis.c, * score7-dis.c,
587 * tic6x-dis.c, * v850-dis.c, * vax-dis.c, * wasm32-dis.c,
588 * xtensa-dis.c: Replace bfd_boolean with bool, FALSE with false,
589 and TRUE with true throughout.
591 2021-03-31 Alan Modra <amodra@gmail.com>
593 * aarch64-dis.c: Include stdint.h in place of bfd_stdint.h.
594 * aarch64-dis.h: Likewise.
595 * aarch64-opc.c: Likewise.
596 * avr-dis.c: Likewise.
597 * csky-dis.c: Likewise.
598 * nds32-asm.c: Likewise.
599 * nds32-dis.c: Likewise.
600 * nfp-dis.c: Likewise.
601 * riscv-dis.c: Likewise.
602 * s12z-dis.c: Likewise.
603 * wasm32-dis.c: Likewise.
605 2021-03-30 Jan Beulich <jbeulich@suse.com>
607 * i386-opc.c (cs, ds, ss, es, fs, gs): Delete.
608 (i386_seg_prefixes): New.
609 * i386-opc.h (cs, ds, ss, es, fs, gs): Delete.
610 (i386_seg_prefixes): Declare.
612 2021-03-30 Jan Beulich <jbeulich@suse.com>
614 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Delete.
616 2021-03-30 Jan Beulich <jbeulich@suse.com>
618 * i386-opc.h (REGNAM_AL, REGNAM_AX, REGNAM_EAX): Adjust values.
619 * i386-reg.tbl (st): Move down.
620 (st(0)): Delete. Extend comment.
621 * i386-tbl.h: Re-generate.
623 2021-03-29 Jan Beulich <jbeulich@suse.com>
625 * i386-opc.tbl (movq, movabs): Move next to mov counterparts.
626 (cmpsd): Move next to cmps.
627 (movsd): Move next to movs.
628 (cmpxchg16b): Move to separate section.
629 (fisttp, fisttpll): Likewise.
630 (monitor, mwait): Likewise.
631 * i386-tbl.h: Re-generate.
633 2021-03-29 Jan Beulich <jbeulich@suse.com>
635 * i386-opc.tbl (psadbw): Add <sse2:comm>.
637 * i386-tbl.h: Re-generate.
639 2021-03-29 Jan Beulich <jbeulich@suse.com>
641 * i386-opc.tbl (mmx, sse, sse2, sse3, ssse3, sse41, sse42, aes,
642 pclmul, gfni): New templates. Use them wherever possible. Move
643 SSE4.1 pextrw into respective section.
644 * i386-tbl.h: Re-generate.
646 2021-03-29 Jan Beulich <jbeulich@suse.com>
648 * i386-gen.c (output_i386_opcode): Widen type of "opcode". Use
649 strtoull(). Bump upper loop bound. Widen masks. Sanity check
651 * i386-opc.tbl (Prefix_0X66, Prefix_0XF2, Prefix_0XF3): Delete.
652 Convert all of their uses to representation in opcode.
654 2021-03-29 Jan Beulich <jbeulich@suse.com>
656 * i386-opc.h (struct insn_template): Shrink base_opcode to 16
657 bits. Shrink extension_opcode to 9 bits. Make it signed. Change
658 value of None. Shrink operands to 3 bits.
660 2021-03-29 Jan Beulich <jbeulich@suse.com>
662 * i386-gen.c (process_i386_opcode_modifier): New parameter
664 (output_i386_opcode): New local variable "space". Adjust
665 process_i386_opcode_modifier() invocation.
666 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
668 * i386-tbl.h: Re-generate.
670 2021-03-29 Alan Modra <amodra@gmail.com>
672 * aarch64-opc.c (vector_qualifier_p): Simplify boolean expression.
673 (fp_qualifier_p, get_data_pattern): Likewise.
674 (aarch64_get_operand_modifier_from_value): Likewise.
675 (aarch64_extend_operator_p, aarch64_shift_operator_p): Likewise.
676 (operand_variant_qualifier_p): Likewise.
677 (qualifier_value_in_range_constraint_p): Likewise.
678 (aarch64_get_qualifier_esize): Likewise.
679 (aarch64_get_qualifier_nelem): Likewise.
680 (aarch64_get_qualifier_standard_value): Likewise.
681 (get_lower_bound, get_upper_bound): Likewise.
682 (aarch64_find_best_match, match_operands_qualifier): Likewise.
683 (aarch64_print_operand): Likewise.
684 * aarch64-opc.h (operand_has_inserter, operand_has_extractor): Likewise.
685 (operand_need_sign_extension, operand_need_shift_by_two): Likewise.
686 (operand_need_shift_by_four, operand_maybe_stack_pointer): Likewise.
687 * arm-dis.c (print_insn_mve, print_insn_thumb32): Likewise.
688 * tic6x-dis.c (tic6x_check_fetch_packet_header): Likewise.
689 (print_insn_tic6x): Likewise.
691 2021-03-29 Alan Modra <amodra@gmail.com>
693 * arc-dis.c (extract_operand_value): Correct NULL cast.
694 * frv-opc.h: Regenerate.
696 2021-03-26 Jan Beulich <jbeulich@suse.com>
698 * i386-opc.tbl (movq): Add CpuSSE2 to SSE2 form. Add CpuMMX to
700 * i386-tbl.h: Re-generate.
702 2021-03-25 Abid Qadeer <abidh@codesourcery.com>
704 * nios2-dis.c (nios2_print_insn_arg): Fix sign extension of
705 immediate in br.n instruction.
707 2021-03-25 Jan Beulich <jbeulich@suse.com>
709 * i386-dis.c (XMGatherD, VexGatherD): New.
710 (vex_table): Use VexGatherD for vpgatherd* and vgatherdp*.
711 (print_insn): Check masking for S/G insns.
712 (OP_E_memory): New local variable check_gather. Extend mandatory
713 SIB check. Check register conflicts for (EVEX-encoded) gathers.
714 Extend check for disallowed 16-bit addressing.
715 (OP_VEX): New local variables modrm_reg and sib_index. Convert
716 if()s to switch(). Check register conflicts for (VEX-encoded)
717 gathers. Drop no longer reachable cases.
718 * i386-dis-evex.h (evex_table): Use XMGatherD for vpgatherd* and
721 2021-03-25 Jan Beulich <jbeulich@suse.com>
723 * i386-dis.c (print_insn): Mark as bad EVEX encodings specifying
724 zeroing-masking without masking.
726 2021-03-25 Jan Beulich <jbeulich@suse.com>
728 * i386-opc.tbl (invlpgb): Fix multi-operand form.
729 (pvalidate, rmpupdate, rmpadjust): Add multi-operand forms. Mark
730 single-operand forms as deprecated.
731 * i386-tbl.h: Re-generate.
733 2021-03-25 Alan Modra <amodra@gmail.com>
736 * ppc-opc.c (XLOCB_MASK): Delete.
737 (XLBOBB_MASK, XLBOBIBB_MASK, XLBOCBBB_MASK): Define using
739 (powerpc_opcodes): Accept a BH field on all extended forms of
740 bclr, bclrl, bcctr, bcctrl, bctar, bctarl.
742 2021-03-24 Jan Beulich <jbeulich@suse.com>
744 * i386-gen.c (output_i386_opcode): Drop processing of
745 opcode_length. Calculate length from base_opcode. Adjust prefix
746 encoding determination.
747 (process_i386_opcodes): Drop output of fake opcode_length.
748 * i386-opc.h (struct insn_template): Drop opcode_length field.
749 * i386-opc.tbl: Drop opcode length field from all templates.
750 * i386-tbl.h: Re-generate.
752 2021-03-24 Jan Beulich <jbeulich@suse.com>
754 * i386-gen.c (process_i386_opcode_modifier): Return void. New
755 parameter "prefix". Drop local variable "regular_encoding".
756 Record prefix setting / check for consistency.
757 (output_i386_opcode): Parse opcode_length and base_opcode
758 earlier. Derive prefix encoding. Drop no longer applicable
759 consistency checking. Adjust process_i386_opcode_modifier()
761 (process_i386_opcodes): Adjust process_i386_opcode_modifier()
763 * i386-tbl.h: Re-generate.
765 2021-03-24 Jan Beulich <jbeulich@suse.com>
767 * i386-gen.c (process_i386_opcode_modifier): Drop IsPrefix
769 * i386-opc.h (Prefix_*): Move #define-s.
770 * i386-opc.tbl: Move pseudo prefix enumerator values to
771 extension opcode field. Introduce pseudopfx template.
772 * i386-tbl.h: Re-generate.
774 2021-03-23 Jan Beulich <jbeulich@suse.com>
776 * i386-opc.h (PREFIX_0XF2, PREFIX_0XF3): Excahnge values. Extend
778 * i386-tbl.h: Re-generate.
780 2021-03-23 Jan Beulich <jbeulich@suse.com>
782 * i386-opc.h (struct insn_template): Move cpu_flags field past
784 * i386-tbl.h: Re-generate.
786 2021-03-23 Jan Beulich <jbeulich@suse.com>
788 * i386-gen.c (opcode_modifiers): New OpcodeSpace element.
789 * i386-opc.h (OpcodeSpace): New enumerator.
790 (VEX0F, VEX0F38, VEX0F3A, XOP08, XOP09, XOP0A): Rename to ...
791 (SPACE_BASE, SPACE_0F, SPACE_0F38, SPACE_0F3A, SPACE_XOP08,
792 SPACE_XOP09, SPACE_XOP0A): ... respectively.
793 (struct i386_opcode_modifier): New field opcodespace. Shrink
795 i386-opc.tbl (Space0F, Space0F38, Space0F3A, SpaceXOP08,
796 SpaceXOP09, SpaceXOP0A): Define. Use them to replace
798 * i386-tbl.h: Re-generate.
800 2021-03-22 Martin Liska <mliska@suse.cz>
802 * aarch64-dis.c (parse_aarch64_dis_option): Replace usage of CONST_STRNEQ with startswith.
803 * arc-dis.c (parse_option): Likewise.
804 * arm-dis.c (parse_arm_disassembler_options): Likewise.
805 * cris-dis.c (print_with_operands): Likewise.
806 * h8300-dis.c (bfd_h8_disassemble): Likewise.
807 * i386-dis.c (print_insn): Likewise.
808 * ia64-gen.c (fetch_insn_class): Likewise.
809 (parse_resource_users): Likewise.
810 (in_iclass): Likewise.
811 (lookup_specifier): Likewise.
812 (insert_opcode_dependencies): Likewise.
813 * mips-dis.c (parse_mips_ase_option): Likewise.
814 (parse_mips_dis_option): Likewise.
815 * s390-dis.c (disassemble_init_s390): Likewise.
816 * wasm32-dis.c (parse_wasm32_disassembler_options): Likewise.
818 2021-03-16 Kuan-Lin Chen <kuanlinchentw@gmail.com>
820 * riscv-opc.c (riscv_opcodes): Add zba, zbb and zbc instructions.
822 2021-03-12 Przemyslaw Wirkus <przemyslaw.wirkus@arm.com>
824 * aarch64-opc.c: Add lorc_el1, lorea_el1, lorn_el1, lorsa_el1,
825 icc_ctlr_el3, icc_sre_elx, ich_vtr_el2 system registers.
827 2021-03-12 Alan Modra <amodra@gmail.com>
829 * i386-dis.c (print_insn <PREFIX_IGNORED>): Correct typo.
831 2021-03-11 Jan Beulich <jbeulich@suse.com>
833 * i386-dis.c (OP_XMM): Re-order checks.
835 2021-03-11 Jan Beulich <jbeulich@suse.com>
837 * i386-dis.c (putop): Drop need_vex check when also checking
839 (intel_operand_size, OP_E_memory): Drop vex.evex check when also
842 2021-03-11 Jan Beulich <jbeulich@suse.com>
844 * i386-dis.c (OP_E_memory): Drop xmmq_mode from broadcast
845 checks. Move case label past broadcast check.
847 2021-03-10 Jan Beulich <jbeulich@suse.com>
849 * opcodes/i386-dis.c (MVexVSIBDQWpX, MVexVSIBQDWpX,
850 vex_vsib_d_w_d_mode, vex_vsib_q_w_d_mode,
851 REG_EVEX_0F38C7_M_0_L_2_W_0, REG_EVEX_0F38C7_M_0_L_2_W_1,
852 EVEX_W_0F3891, EVEX_W_0F3893, EVEX_W_0F38A1, EVEX_W_0F38A3,
853 EVEX_W_0F38C7_M_0_L_2): Delete.
854 (REG_EVEX_0F38C7_M_0_L_2): New.
855 (intel_operand_size): Handle VEX and EVEX the same for
856 vex_vsib_d_w_dq_mode and vex_vsib_q_w_dq_mode. Drop
857 vex_vsib_d_w_d_mode and vex_vsib_q_w_d_mode cases.
858 (OP_E_memory, OP_XMM, OP_VEX): Drop vex_vsib_d_w_d_mode and
859 vex_vsib_q_w_d_mode uses.
860 * i386-dis-evex.h (evex_table): Adjust opcode 0F3891, 0F3893,
861 0F38A1, and 0F38A3 entries.
862 * i386-dis-evex-len.h (evex_len_table): Adjust opcode 0F38C7
864 * i386-dis-evex-reg.h: Fold opcode 0F38C7 entries.
865 * i386-dis-evex-w.h: Delete opcode 0F3891, 0F3893, 0F38A1, and
868 2021-03-10 Jan Beulich <jbeulich@suse.com>
870 * opcodes/i386-dis.c (REG_0FXOP_09_01_L_0, REG_0FXOP_09_02_L_0,
871 REG_0FXOP_09_12_M_1_L_0, REG_0FXOP_0A_12_L_0,
872 MOD_VEX_0FXOP_09_12): Rename to ...
873 (REG_XOP_09_01_L_0, REG_XOP_09_02_L_0, REG_XOP_09_12_M_1_L_0,
874 REG_XOP_0A_12_L_0, MOD_XOP_09_12): ... these.
875 (MOD_62_32BIT, MOD_8D, MOD_C4_32BIT, MOD_C5_32BIT,
876 RM_0F3A0F_P_1_MOD_3_REG_0, X86_64_0F24, X86_64_0F26,
877 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
878 X86_64_VEX_0F385E, X86_64_0FC7_REG_6_MOD_3_PREFIX_1): Move.
879 (reg_table): Adjust comments.
880 (x86_64_table): Move X86_64_0F24, X86_64_0F26,
881 X86_64_VEX_0F3849, X86_64_VEX_0F384B, X86_64_VEX_0F385C,
882 X86_64_VEX_0F385E, and X86_64_0FC7_REG_6_MOD_3_PREFIX_1 entries.
883 (xop_table): Adjust opcode 09_01, 09_02, and 09_12 entries.
884 (vex_len_table): Adjust opcode 0A_12 entry.
885 (mod_table): Move MOD_62_32BIT, MOD_8D, MOD_C4_32BIT,
886 MOD_C5_32BIT, and MOD_XOP_09_12 entries.
887 (rm_table): Move hreset entry.
889 2021-03-10 Jan Beulich <jbeulich@suse.com>
891 * opcodes/i386-dis.c (EVEX_LEN_0F6E, EVEX_LEN_0F7E_P_1,
892 EVEX_LEN_0F7E_P_2, EVEX_LEN_0FC4, EVEX_LEN_0FC5, EVEX_LEN_0FD6,
893 EVEX_LEN_0F3816, EVEX_LEN_0F3A14, EVEX_LEN_0F3A15,
894 EVEX_LEN_0F3A16, EVEX_LEN_0F3A17, EVEX_LEN_0F3A20,
895 EVEX_LEN_0F3A21_W_0, EVEX_LEN_0F3A22, EVEX_W_0FD6_L_0): Delete.
896 (EVEX_LEN_0F3816, EVEX_W_0FD6): New.
897 (get_valid_dis386): Also handle 512-bit vector length when
898 vectoring into vex_len_table[].
899 * i386-dis-evex.h (evex_table): Adjust opcode 0F6E, 0FC4, 0FC5,
900 0FD6, 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22
902 * i386-dis-evex-len.h: Delete opcode 0F6E, 0FC4, 0FC5, 0FD6,
903 0F3A14, 0F3A15, 0F3A16, 0F3A17, 0F3A20, and 0F3A22 entries.
904 * i386-dis-evex-prefix.h: Adjust 0F7E entry.
905 * i386-dis-evex-w.h: Adjust 0F7E, 0F7F, 0FD6, and 0F3A21
908 2021-03-10 Jan Beulich <jbeulich@suse.com>
910 * opcodes/i386-dis.c (EVEX_LEN_0F3A00_W_1, EVEX_LEN_0F3A01_W_1):
911 Rename to EVEX_LEN_0F3A00 and EVEX_LEN_0F3A01 respectively.
912 EVEX_W_0F3A00, EVEX_W_0F3A01): Delete.
913 * i386-dis-evex.h (evex_table): Adjust opcode 0F3A00 and 0F3A01
915 * i386-dis-evex-len.h (evex_len_table): Likewise.
916 * i386-dis-evex-w.h: Remove opcode 0F3A00 and 0F3A01 entries.
918 2021-03-10 Jan Beulich <jbeulich@suse.com>
920 * opcodes/i386-dis.c (REG_EVEX_0F38C6, REG_EVEX_0F38C7,
921 MOD_EVEX_0F381A_W_0, MOD_EVEX_0F381A_W_1, MOD_EVEX_0F381B_W_0,
922 MOD_EVEX_0F381B_W_1, MOD_EVEX_0F385A_W_0, MOD_EVEX_0F385A_W_1,
923 MOD_EVEX_0F385B_W_0, MOD_EVEX_0F385B_W_1,
924 MOD_EVEX_0F38C6_REG_1, MOD_EVEX_0F38C6_REG_2,
925 MOD_EVEX_0F38C6_REG_5, MOD_EVEX_0F38C6_REG_6,
926 MOD_EVEX_0F38C7_REG_1, MOD_EVEX_0F38C7_REG_2,
927 MOD_EVEX_0F38C7_REG_5, MOD_EVEX_0F38C7_REG_6
928 EVEX_LEN_0F3819_W_0, EVEX_LEN_0F3819_W_1,
929 EVEX_LEN_0F381A_W_0_M_0, EVEX_LEN_0F381A_W_1_M_0,
930 EVEX_LEN_0F381B_W_0_M_0, EVEX_LEN_0F381B_W_1_M_0,
931 EVEX_LEN_0F385A_W_0_M_0, EVEX_LEN_0F385A_W_1_M_0,
932 EVEX_LEN_0F385B_W_0_M_0, EVEX_LEN_0F385B_W_1_M_0,
933 EVEX_LEN_0F38C6_R_1_M_0, EVEX_LEN_0F38C6_R_2_M_0,
934 EVEX_LEN_0F38C6_R_5_M_0, EVEX_LEN_0F38C6_R_6_M_0,
935 EVEX_LEN_0F38C7_R_1_M_0_W_0, EVEX_LEN_0F38C7_R_1_M_0_W_1,
936 EVEX_LEN_0F38C7_R_2_M_0_W_0, EVEX_LEN_0F38C7_R_2_M_0_W_1,
937 EVEX_LEN_0F38C7_R_5_M_0_W_0, EVEX_LEN_0F38C7_R_5_M_0_W_1,
938 EVEX_LEN_0F38C7_R_6_M_0_W_0, EVEX_LEN_0F38C7_R_6_M_0_W_1,
939 EVEX_LEN_0F3A18_W_0, EVEX_LEN_0F3A18_W_1, EVEX_LEN_0F3A19_W_0,
940 EVEX_LEN_0F3A19_W_1, EVEX_LEN_0F3A1A_W_0, EVEX_LEN_0F3A1A_W_1,
941 EVEX_LEN_0F3A1B_W_0, EVEX_LEN_0F3A1B_W_1, EVEX_LEN_0F3A23_W_0,
942 EVEX_LEN_0F3A23_W_1, EVEX_LEN_0F3A38_W_0, EVEX_LEN_0F3A38_W_1,
943 EVEX_LEN_0F3A39_W_0, EVEX_LEN_0F3A39_W_1, EVEX_LEN_0F3A3A_W_0,
944 EVEX_LEN_0F3A3A_W_1, EVEX_LEN_0F3A3B_W_0, EVEX_LEN_0F3A3B_W_1,
945 EVEX_LEN_0F3A43_W_0, EVEX_LEN_0F3A43_W_1 EVEX_W_0F3819,
946 EVEX_W_0F381A, EVEX_W_0F381B, EVEX_W_0F385A, EVEX_W_0F385B,
947 EVEX_W_0F38C7_R_1_M_0, EVEX_W_0F38C7_R_2_M_0,
948 EVEX_W_0F38C7_R_5_M_0, EVEX_W_0F38C7_R_6_M_0,
949 EVEX_W_0F3A18, EVEX_W_0F3A19, EVEX_W_0F3A1A, EVEX_W_0F3A1B,
950 EVEX_W_0F3A23, EVEX_W_0F3A38, EVEX_W_0F3A39, EVEX_W_0F3A3A,
951 EVEX_W_0F3A3B, EVEX_W_0F3A43): Delete.
952 REG_EVEX_0F38C6_M_0_L_2, REG_EVEX_0F38C7_M_0_L_2_W_0,
953 REG_EVEX_0F38C7_M_0_L_2_W_1, MOD_EVEX_0F381A,
954 MOD_EVEX_0F381B, MOD_EVEX_0F385A, MOD_EVEX_0F385B,
955 MOD_EVEX_0F38C6, MOD_EVEX_0F38C7 EVEX_LEN_0F3819,
956 EVEX_LEN_0F381A_M_0, EVEX_LEN_0F381B_M_0,
957 EVEX_LEN_0F385A_M_0, EVEX_LEN_0F385B_M_0,
958 EVEX_LEN_0F38C6_M_0, EVEX_LEN_0F38C7_M_0,
959 EVEX_LEN_0F3A18, EVEX_LEN_0F3A19, EVEX_LEN_0F3A1A,
960 EVEX_LEN_0F3A1B, EVEX_LEN_0F3A23, EVEX_LEN_0F3A38,
961 EVEX_LEN_0F3A39, EVEX_LEN_0F3A3A, EVEX_LEN_0F3A3B,
962 EVEX_LEN_0F3A43, EVEX_W_0F3819_L_n, EVEX_W_0F381A_M_0_L_n,
963 EVEX_W_0F381B_M_0_L_2, EVEX_W_0F385A_M_0_L_n,
964 EVEX_W_0F385B_M_0_L_2, EVEX_W_0F38C7_M_0_L_2,
965 EVEX_W_0F3A18_L_n, EVEX_W_0F3A19_L_n, EVEX_W_0F3A1A_L_2,
966 EVEX_W_0F3A1B_L_2, EVEX_W_0F3A23_L_n, EVEX_W_0F3A38_L_n,
967 EVEX_W_0F3A39_L_n, EVEX_W_0F3A3A_L_2, EVEX_W_0F3A3B_L_2,
968 EVEX_W_0F3A43_L_n): New.
969 * i386-dis-evex.h (evex_table): Adjust opcode 0F3819, 0F381A,
970 0F381B, 0F385A, 0F385B, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B,
971 0F3A23, 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43 entries.
972 * i386-dis-evex-len.h (evex_len_table): Link to vex_w_table[]
973 for opcodes 0F3819, 0F381A, 0F381B, 0F385A, 0F385B, 0F38C7,
974 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23, 0F3A38, 0F3A39, 0F3A3A,
975 0F3A3B, and 0F3A43. Link to reg_table[] for opcodes 0F38C6.
976 * i386-dis-evex-mod.h: Adjust opcode 0F381A, 0F381B, 0F385A,
977 0F385B, 0F38C6, and 0F38C7 entries.
978 * i386-dis-evex-reg.h: No longer link to mod_table[] for opcodes
980 * i386-dis-evex-w.h: No longer link to evex_len_table[] for
981 opcodes 0F3819, 0F38C7, 0F3A18, 0F3A19, 0F3A1A, 0F3A1B, 0F3A23,
982 0F3A38, 0F3A39, 0F3A3A, 0F3A3B, and 0F3A43. No longer link to
983 evex_len_table[] for opcodes 0F381A, 0F381B, 0F385A, and 0F385B.
985 2021-03-10 Jan Beulich <jbeulich@suse.com>
987 * opcodes/i386-dis.c (MOD_VEX_W_0_0F41_P_0_LEN_1,
988 MOD_VEX_W_1_0F41_P_0_LEN_1, MOD_VEX_W_0_0F41_P_2_LEN_1,
989 MOD_VEX_W_1_0F41_P_2_LEN_1, MOD_VEX_W_0_0F42_P_0_LEN_1,
990 MOD_VEX_W_1_0F42_P_0_LEN_1, MOD_VEX_W_0_0F42_P_2_LEN_1,
991 MOD_VEX_W_1_0F42_P_2_LEN_1, MOD_VEX_W_0_0F44_P_0_LEN_1,
992 MOD_VEX_W_1_0F44_P_0_LEN_1, MOD_VEX_W_0_0F44_P_2_LEN_1,
993 MOD_VEX_W_1_0F44_P_2_LEN_1, MOD_VEX_W_0_0F45_P_0_LEN_1,
994 MOD_VEX_W_1_0F45_P_0_LEN_1, MOD_VEX_W_0_0F45_P_2_LEN_1,
995 MOD_VEX_W_1_0F45_P_2_LEN_1, MOD_VEX_W_0_0F46_P_0_LEN_1,
996 MOD_VEX_W_1_0F46_P_0_LEN_1, MOD_VEX_W_0_0F46_P_2_LEN_1,
997 MOD_VEX_W_1_0F46_P_2_LEN_1, MOD_VEX_W_0_0F47_P_0_LEN_1,
998 MOD_VEX_W_1_0F47_P_0_LEN_1, MOD_VEX_W_0_0F47_P_2_LEN_1,
999 MOD_VEX_W_1_0F47_P_2_LEN_1, MOD_VEX_W_0_0F4A_P_0_LEN_1,
1000 MOD_VEX_W_1_0F4A_P_0_LEN_1, MOD_VEX_W_0_0F4A_P_2_LEN_1,
1001 MOD_VEX_W_1_0F4A_P_2_LEN_1, MOD_VEX_W_0_0F4B_P_0_LEN_1,
1002 MOD_VEX_W_1_0F4B_P_0_LEN_1, MOD_VEX_W_0_0F4B_P_2_LEN_1,
1003 MOD_VEX_W_0_0F91_P_0_LEN_0, MOD_VEX_W_1_0F91_P_0_LEN_0,
1004 MOD_VEX_W_0_0F91_P_2_LEN_0, MOD_VEX_W_1_0F91_P_2_LEN_0,
1005 MOD_VEX_W_0_0F92_P_0_LEN_0, MOD_VEX_W_0_0F92_P_2_LEN_0,
1006 MOD_VEX_0F92_P_3_LEN_0, MOD_VEX_W_0_0F93_P_0_LEN_0,
1007 MOD_VEX_W_0_0F93_P_2_LEN_0, MOD_VEX_0F93_P_3_LEN_0,
1008 MOD_VEX_W_0_0F98_P_0_LEN_0, MOD_VEX_W_1_0F98_P_0_LEN_0,
1009 MOD_VEX_W_0_0F98_P_2_LEN_0, MOD_VEX_W_1_0F98_P_2_LEN_0,
1010 MOD_VEX_W_0_0F99_P_0_LEN_0, MOD_VEX_W_1_0F99_P_0_LEN_0,
1011 MOD_VEX_W_0_0F99_P_2_LEN_0, MOD_VEX_W_1_0F99_P_2_LEN_0,
1012 PREFIX_VEX_0F41, PREFIX_VEX_0F42, PREFIX_VEX_0F44,
1013 PREFIX_VEX_0F45, PREFIX_VEX_0F46, PREFIX_VEX_0F47,
1014 PREFIX_VEX_0F4A, PREFIX_VEX_0F4B, PREFIX_VEX_0F90,
1015 PREFIX_VEX_0F91, PREFIX_VEX_0F92, PREFIX_VEX_0F93,
1016 PREFIX_VEX_0F98, PREFIX_VEX_0F99, VEX_LEN_0F41_P_0,
1017 VEX_LEN_0F41_P_2, VEX_LEN_0F42_P_0, VEX_LEN_0F42_P_2,
1018 VEX_LEN_0F44_P_0, VEX_LEN_0F44_P_2, VEX_LEN_0F45_P_0,
1019 VEX_LEN_0F45_P_2, VEX_LEN_0F46_P_0, VEX_LEN_0F46_P_2,
1020 VEX_LEN_0F47_P_0, VEX_LEN_0F47_P_2, VEX_LEN_0F4A_P_0,
1021 VEX_LEN_0F4A_P_2, VEX_LEN_0F4B_P_0, VEX_LEN_0F4B_P_2,
1022 VEX_LEN_0F90_P_0, VEX_LEN_0F90_P_2, VEX_LEN_0F91_P_0,
1023 VEX_LEN_0F91_P_2, VEX_LEN_0F92_P_0, VEX_LEN_0F92_P_2,
1024 VEX_LEN_0F92_P_3, VEX_LEN_0F93_P_0, VEX_LEN_0F93_P_2,
1025 VEX_LEN_0F93_P_3, VEX_LEN_0F98_P_0, VEX_LEN_0F98_P_2,
1026 VEX_LEN_0F99_P_0, VEX_LEN_0F99_P_2, VEX_W_0F41_P_0_LEN_1,
1027 VEX_W_0F41_P_2_LEN_1, VEX_W_0F42_P_0_LEN_1,
1028 VEX_W_0F42_P_2_LEN_1, VEX_W_0F44_P_0_LEN_0,
1029 VEX_W_0F44_P_2_LEN_0, VEX_W_0F45_P_0_LEN_1,
1030 VEX_W_0F45_P_2_LEN_1, VEX_W_0F46_P_0_LEN_1,
1031 VEX_W_0F46_P_2_LEN_1, VEX_W_0F47_P_0_LEN_1,
1032 VEX_W_0F47_P_2_LEN_1, VEX_W_0F4A_P_0_LEN_1,
1033 VEX_W_0F4A_P_2_LEN_1, VEX_W_0F4B_P_0_LEN_1,
1034 VEX_W_0F4B_P_2_LEN_1, VEX_W_0F90_P_0_LEN_0,
1035 VEX_W_0F90_P_2_LEN_0, VEX_W_0F91_P_0_LEN_0,
1036 VEX_W_0F91_P_2_LEN_0, VEX_W_0F92_P_0_LEN_0,
1037 VEX_W_0F92_P_2_LEN_0, VEX_W_0F93_P_0_LEN_0,
1038 VEX_W_0F93_P_2_LEN_0, VEX_W_0F98_P_0_LEN_0,
1039 VEX_W_0F98_P_2_LEN_0, VEX_W_0F99_P_0_LEN_0,
1040 VEX_W_0F99_P_2_LEN_0): Delete.
1041 MOD_VEX_0F41_L_1, MOD_VEX_0F42_L_1, MOD_VEX_0F44_L_0,
1042 MOD_VEX_0F45_L_1, MOD_VEX_0F46_L_1, MOD_VEX_0F47_L_1,
1043 MOD_VEX_0F4A_L_1, MOD_VEX_0F4B_L_1, MOD_VEX_0F91_L_0,
1044 MOD_VEX_0F92_L_0, MOD_VEX_0F93_L_0, MOD_VEX_0F98_L_0,
1045 MOD_VEX_0F99_L_0, PREFIX_VEX_0F41_L_1_M_1_W_0,
1046 PREFIX_VEX_0F41_L_1_M_1_W_1, PREFIX_VEX_0F42_L_1_M_1_W_0,
1047 PREFIX_VEX_0F42_L_1_M_1_W_1, PREFIX_VEX_0F44_L_0_M_1_W_0,
1048 PREFIX_VEX_0F44_L_0_M_1_W_1, PREFIX_VEX_0F45_L_1_M_1_W_0,
1049 PREFIX_VEX_0F45_L_1_M_1_W_1, PREFIX_VEX_0F46_L_1_M_1_W_0,
1050 PREFIX_VEX_0F46_L_1_M_1_W_1, PREFIX_VEX_0F47_L_1_M_1_W_0,
1051 PREFIX_VEX_0F47_L_1_M_1_W_1, PREFIX_VEX_0F4A_L_1_M_1_W_0,
1052 PREFIX_VEX_0F4A_L_1_M_1_W_1, PREFIX_VEX_0F4B_L_1_M_1_W_0,
1053 PREFIX_VEX_0F4B_L_1_M_1_W_1, PREFIX_VEX_0F90_L_0_W_0,
1054 PREFIX_VEX_0F90_L_0_W_1, PREFIX_VEX_0F91_L_0_M_0_W_0,
1055 PREFIX_VEX_0F91_L_0_M_0_W_1, PREFIX_VEX_0F92_L_0_M_1_W_0,
1056 PREFIX_VEX_0F92_L_0_M_1_W_1, PREFIX_VEX_0F93_L_0_M_1_W_0,
1057 PREFIX_VEX_0F93_L_0_M_1_W_1, PREFIX_VEX_0F98_L_0_M_1_W_0,
1058 PREFIX_VEX_0F98_L_0_M_1_W_1, PREFIX_VEX_0F99_L_0_M_1_W_0,
1059 PREFIX_VEX_0F99_L_0_M_1_W_1, VEX_LEN_0F41, VEX_LEN_0F42,
1060 VEX_LEN_0F44, VEX_LEN_0F45, VEX_LEN_0F46, VEX_LEN_0F47,
1061 VEX_LEN_0F4A, VEX_LEN_0F4B, VEX_LEN_0F90, VEX_LEN_0F91,
1062 VEX_LEN_0F92, VEX_LEN_0F93, VEX_LEN_0F98, VEX_LEN_0F99,
1063 VEX_W_0F41_L_1_M_1, VEX_W_0F42_L_1_M_1, VEX_W_0F44_L_0_M_1,
1064 VEX_W_0F45_L_1_M_1, VEX_W_0F46_L_1_M_1, VEX_W_0F47_L_1_M_1,
1065 VEX_W_0F4A_L_1_M_1, VEX_W_0F4B_L_1_M_1, VEX_W_0F90_L_0,
1066 VEX_W_0F91_L_0_M_0, VEX_W_0F92_L_0_M_1, VEX_W_0F93_L_0_M_1,
1067 VEX_W_0F98_L_0_M_1, VEX_W_0F99_L_0_M_1): New.
1068 (prefix_table): No longer link to vex_len_table[] for opcodes
1069 0F41, 0F42, 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91,
1070 0F92, 0F93, 0F98, and 0F99.
1071 (vex_table): Link to vex_len_table[] for opcodes 0F41, 0F42,
1072 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1074 (vex_len_table): Link to mod_table[] for opcodes 0F41, 0F42,
1075 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1077 (vex_w_table): Link to prefix_table[] for opcodes 0F41, 0F42,
1078 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1080 (mod_table): Link to vex_w_table[] for opcodes 0F41, 0F42,
1081 0F44, 0F45, 0F46, 0F47, 0F4A, 0F4B, 0F90, 0F91, 0F92, 0F93,
1084 2021-03-10 Jan Beulich <jbeulich@suse.com>
1086 * opcodes/i386-dis.c (VEX_REG_0F71, VEX_REG_0F72, VEX_REG_0F73):
1087 Rename to REG_VEX_0F71_M_0, REG_VEX_0F72_M_0, and
1088 REG_VEX_0F73_M_0 respectively.
1089 (MOD_VEX_0F71_REG_2, MOD_VEX_0F71_REG_4, MOD_VEX_0F71_REG_6,
1090 MOD_VEX_0F72_REG_2, MOD_VEX_0F72_REG_4, MOD_VEX_0F72_REG_6,
1091 MOD_VEX_0F73_REG_2, MOD_VEX_0F73_REG_3, MOD_VEX_0F73_REG_6,
1092 MOD_VEX_0F73_REG_7): Delete.
1093 (MOD_VEX_0F71, MOD_VEX_0F72, MOD_VEX_0F73): New.
1094 (PREFIX_VEX_0F38F5, PREFIX_VEX_0F38F6, PREFIX_VEX_0F38F7,
1095 PREFIX_VEX_0F3AF0): Rename to PREFIX_VEX_0F38F5_L_0,
1096 PREFIX_VEX_0F38F6_L_0, PREFIX_VEX_0F38F7_L_0,
1097 PREFIX_VEX_0F3AF0_L_0 respectively.
1098 (VEX_LEN_0F38F3_R_1, VEX_LEN_0F38F3_R_2, VEX_LEN_0F38F3_R_3,
1099 VEX_LEN_0F38F5_P_0, VEX_LEN_0F38F5_P_1, VEX_LEN_0F38F5_P_3,
1100 VEX_LEN_0F38F6_P_3, VEX_LEN_0F38F7_P_0, VEX_LEN_0F38F7_P_1,
1101 VEX_LEN_0F38F7_P_2, VEX_LEN_0F38F7_P_3): Delete.
1102 (VEX_LEN_0F38F3, VEX_LEN_0F38F5, VEX_LEN_0F38F6,
1103 VEX_LEN_0F38F7): New.
1104 (VEX_LEN_0F3AF0_P_3): Rename to VEX_LEN_0F3AF0.
1105 (reg_table): No longer link to mod_table[] for VEX opcodes 0F71,
1106 0F72, and 0F73. No longer link to vex_len_table[] for opcode
1108 (prefix_table): No longer link to vex_len_table[] for opcodes
1109 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1110 (vex_table): Link to mod_table[] for opcodes 0F71, 0F72, and
1111 0F73. Link to vex_len_table[] for opcodes 0F38F3, 0F38F5,
1112 0F38F6, 0F38F7, and 0F3AF0.
1113 (vex_len_table): Link to reg_table[] for opcode 0F38F3. Link to
1114 prefix_table[] for opcodes 0F38F5, 0F38F6, 0F38F7, and 0F3AF0.
1115 (mod_table): Link to reg_table[] for VEX opcodes 0F71, 0F72, and
1118 2021-03-10 Jan Beulich <jbeulich@suse.com>
1120 * opcodes/i386-dis.c (REG_0F71, REG_0F72, REG_0F73): Rename to
1121 REG_0F71_MOD_0, REG_0F72_MOD_0, and REG_0F73_MOD_0 respectively.
1122 (MOD_0F71_REG_2, MOD_0F71_REG_4, MOD_0F71_REG_6, MOD_0F72_REG_2,
1123 MOD_0F72_REG_4, MOD_0F72_REG_6, MOD_0F73_REG_2, MOD_0F73_REG_3,
1124 MOD_0F73_REG_6, MOD_0F73_REG_7): Delete.
1125 (MOD_0F71, MOD_0F72, MOD_0F73): New.
1126 (dis386_twobyte): Link to mod_table[] for opcodes 71, 72, and
1128 (reg_table): No longer link to mod_table[] for opcodes 0F71,
1130 (mod_table): Link to reg_table[] for opcodes 0F71, 0F72, and
1133 2021-03-10 Jan Beulich <jbeulich@suse.com>
1135 * opcodes/i386-dis.c (MOD_0F18_REG_4, MOD_0F18_REG_5,
1136 MOD_0F18_REG_6, MOD_0F18_REG_7): Delete.
1137 (reg_table): Don't link to mod_table[] where not needed. Add
1138 PREFIX_IGNORED to nop entries.
1139 (prefix_table): Replace PREFIX_OPCODE in nop entries.
1140 (mod_table): Add nop entries next to prefetch ones. Drop
1141 MOD_0F18_REG_4, MOD_0F18_REG_5, MOD_0F18_REG_6, and
1142 MOD_0F18_REG_7 entries. Add PREFIX_IGNORED to nop entries.
1143 (rm_table): Add PREFIX_IGNORED to nop entries. Drop
1144 PREFIX_OPCODE from endbr* entries.
1145 (get_valid_dis386): Also consider entry's name when zapping
1147 (print_insn): Handle PREFIX_IGNORED.
1149 2021-03-09 Jan Beulich <jbeulich@suse.com>
1151 * opcodes/i386-gen.c (opcode_modifiers): Delete NoTrackPrefixOk,
1152 IsLockable, RepPrefixOk, and HLEPrefixOk elements. Add PrefixOk
1154 * opcodes/i386-opc.h (NoTrackPrefixOk, IsLockable, HLEPrefixNone,
1155 HLEPrefixLock, HLEPrefixAny, HLEPrefixRelease): Delete.
1156 (PrefixNone, PrefixRep, PrefixHLERelease, PrefixNoTrack,
1157 PrefixLock, PrefixHLELock, PrefixHLEAny): Define.
1158 (struct i386_opcode_modifier): Delete notrackprefixok,
1159 islockable, hleprefixok, and repprefixok fields. Add prefixok
1161 * opcodes/i386-opc.tbl (RepPrefixOk, LockPrefixOk, HLEPrefixAny,
1162 HLEPrefixLock, HLEPrefixRelease, NoTrackPrefixOk): Define.
1163 (mov, xchg, add, inc, sub, dec, sbb, and, or, xor, adc, neg,
1164 not, btc, btr, bts, xadd, cmpxchg, cmpxchg8b, movq, cmpxchg16b):
1165 Replace HLEPrefixOk.
1166 * opcodes/i386-tbl.h: Re-generate.
1168 2021-03-09 Jan Beulich <jbeulich@suse.com>
1170 * opcodes/i386-dis.c (dis386_twobyte): Add %LQ to sysexit.
1171 * opcodes/i386-opc.tbl (sysexit): Drop No_lSuf and No_qSuf from
1173 * opcodes/i386-tbl.h: Re-generate.
1175 2021-03-03 Jan Beulich <jbeulich@suse.com>
1177 * i386-gen.c (output_i386_opcode): Don't get operand count. Look
1178 for {} instead of {0}. Don't look for '0'.
1179 * i386-opc.tbl: Drop operand count field. Drop redundant operand
1182 2021-02-19 Nelson Chu <nelson.chu@sifive.com>
1185 * riscv-dis.c (print_insn_args): Updated encoding macros.
1186 * riscv-opc.c (MASK_RVC_IMM): defined to ENCODE_CITYPE_IMM.
1187 (match_c_addi16sp): Updated encoding macros.
1188 (match_c_lui): Likewise.
1189 (match_c_lui_with_hint): Likewise.
1190 (match_c_addi4spn): Likewise.
1191 (match_c_slli): Likewise.
1192 (match_slli_as_c_slli): Likewise.
1193 (match_c_slli64): Likewise.
1194 (match_srxi_as_c_srxi): Likewise.
1195 (riscv_insn_types): Added .insn css/cl/cs.
1197 2021-02-18 Nelson Chu <nelson.chu@sifive.com>
1199 * riscv-dis.c: Included cpu-riscv.h, and removed elfxx-riscv.h.
1200 (default_priv_spec): Updated type to riscv_spec_class.
1201 (parse_riscv_dis_option): Updated.
1202 * riscv-opc.c: Moved stuff and make the file tidy.
1204 2021-02-17 Alan Modra <amodra@gmail.com>
1206 * wasm32-dis.c: Include limits.h.
1207 (CHAR_BIT): Provide backup define.
1208 (wasm_read_leb128): Use CHAR_BIT to size "result" in bits.
1209 Correct signed overflow checking.
1211 2021-02-16 Jan Beulich <jbeulich@suse.com>
1213 * i386-opc.tbl: Split CVTPI2PD template. Add SSE2AVX variant.
1214 * i386-tbl.h: Re-generate.
1216 2021-02-16 Jan Beulich <jbeulich@suse.com>
1218 * i386-gen.c (set_bitfield): Don't look for CpuFP, Mmword, nor
1220 * i386-opc.tbl (CpuFP, Mmword, Oword): Define.
1222 2021-02-15 Andreas Krebbel <krebbel@linux.ibm.com>
1224 * s390-mkopc.c (main): Accept arch14 as cpu string.
1225 * s390-opc.txt: Add new arch14 instructions.
1227 2021-02-04 Nick Alcock <nick.alcock@oracle.com>
1229 * configure.ac (SHARED_LIBADD): Remove explicit -lintl population in
1231 * configure: Regenerated.
1233 2021-02-08 Mike Frysinger <vapier@gentoo.org>
1235 * tic54x-dis.c (sprint_mmr): Change to tic54x_mmregs.
1236 * tic54x-opc.c (regs): Rename to ...
1237 (tic54x_regs): ... this.
1238 (mmregs): Rename to ...
1239 (tic54x_mmregs): ... this.
1240 (condition_codes): Rename to ...
1241 (tic54x_condition_codes): ... this.
1242 (cc2_codes): Rename to ...
1243 (tic54x_cc2_codes): ... this.
1244 (cc3_codes): Rename to ...
1245 (tic54x_cc3_codes): ... this.
1246 (status_bits): Rename to ...
1247 (tic54x_status_bits): ... this.
1248 (misc_symbols): Rename to ...
1249 (tic54x_misc_symbols): ... this.
1251 2021-02-04 Nelson Chu <nelson.chu@sifive.com>
1253 * riscv-opc.c (MASK_RVB_IMM): Removed.
1254 (riscv_opcodes): Removed zb* instructions.
1255 (riscv_ext_version_table): Removed versions for zb*.
1257 2021-01-26 Alan Modra <amodra@gmail.com>
1259 * i386-gen.c (parse_template): Ensure entire template_instance
1262 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1264 * riscv-opc.c (riscv_gpr_names_abi): Aligned the code.
1265 (riscv_fpr_names_abi): Likewise.
1266 (riscv_opcodes): Likewise.
1267 (riscv_insn_types): Likewise.
1269 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1271 * riscv-dis.c (parse_riscv_dis_option): Fix typos of message.
1273 2021-01-15 Nelson Chu <nelson.chu@sifive.com>
1275 * riscv-dis.c: Comments tidy and improvement.
1276 * riscv-opc.c: Likewise.
1278 2021-01-13 Alan Modra <amodra@gmail.com>
1280 * Makefile.in: Regenerate.
1282 2021-01-12 H.J. Lu <hongjiu.lu@intel.com>
1285 * configure.ac: Use GNU_MAKE_JOBSERVER.
1286 * aclocal.m4: Regenerated.
1287 * configure: Likewise.
1289 2021-01-12 Nick Clifton <nickc@redhat.com>
1291 * po/sr.po: Updated Serbian translation.
1293 2021-01-11 H.J. Lu <hongjiu.lu@intel.com>
1296 * configure: Regenerated.
1298 2021-01-11 Kyrylo Tkachov <kyrylo.tkachov@arm.com>
1300 * aarch64-asm-2.c: Regenerate.
1301 * aarch64-dis-2.c: Likewise.
1302 * aarch64-opc-2.c: Likewise.
1303 * aarch64-opc.c (aarch64_print_operand):
1304 Delete handling of AARCH64_OPND_CSRE_CSR.
1305 * aarch64-tbl.h (aarch64_feature_csre): Delete.
1307 (_CSRE_INSN): Likewise.
1308 (aarch64_opcode_table): Delete csr.
1310 2021-01-11 Nick Clifton <nickc@redhat.com>
1312 * po/de.po: Updated German translation.
1313 * po/fr.po: Updated French translation.
1314 * po/pt_BR.po: Updated Brazilian Portuguese translation.
1315 * po/sv.po: Updated Swedish translation.
1316 * po/uk.po: Updated Ukranian translation.
1318 2021-01-09 H.J. Lu <hongjiu.lu@intel.com>
1320 * configure: Regenerated.
1322 2021-01-09 Nick Clifton <nickc@redhat.com>
1324 * configure: Regenerate.
1325 * po/opcodes.pot: Regenerate.
1327 2021-01-09 Nick Clifton <nickc@redhat.com>
1329 * 2.36 release branch crated.
1331 2021-01-08 Peter Bergner <bergner@linux.ibm.com>
1333 * ppc-opc.c (insert_dw, (extract_dw): New functions.
1334 (DW, (XRC_MASK): Define.
1335 (powerpc_opcodes) <hashchk, hashchkp, hashst, haststp>: New mnemonics.
1337 2021-01-09 Alan Modra <amodra@gmail.com>
1339 * configure: Regenerate.
1341 2021-01-08 Nick Clifton <nickc@redhat.com>
1343 * po/sv.po: Updated Swedish translation.
1345 2021-01-08 Nick Clifton <nickc@redhat.com>
1348 * aarch64-dis.c (determine_disassembling_preference): Move call to
1349 aarch64_match_operands_constraint outside of the assertion.
1350 * aarch64-asm.c (aarch64_ins_limm_1): Remove call to assert.
1351 Replace with a return of FALSE.
1354 * aarch64-opc.c (aarch64_sys_regs): Treat id_aa64mmfr2_el1 as a
1355 core system register.
1357 2021-01-07 Samuel Thibault <samuel.thibault@gnu.org>
1359 * configure: Regenerate.
1361 2021-01-07 Nick Clifton <nickc@redhat.com>
1363 * po/fr.po: Updated French translation.
1365 2021-01-07 Fredrik Noring <noring@nocrew.org>
1367 * m68k-opc.c (chkl): Change minimum architecture requirement to
1370 2021-01-07 Philipp Tomsich <prt@gnu.org>
1372 * riscv-opc.c (riscv_opcodes): Add pause hint instruction.
1374 2021-01-07 Claire Xenia Wolf <claire@symbioticeda.com>
1375 Jim Wilson <jimw@sifive.com>
1376 Andrew Waterman <andrew@sifive.com>
1377 Maxim Blinov <maxim.blinov@embecosm.com>
1378 Kito Cheng <kito.cheng@sifive.com>
1379 Nelson Chu <nelson.chu@sifive.com>
1381 * riscv-opc.c (riscv_opcodes): Add ZBA/ZBB/ZBC instructions.
1382 (MASK_RVB_IMM): Used for rev8 and orc.b encoding.
1384 2021-01-01 Alan Modra <amodra@gmail.com>
1386 Update year range in copyright notice of all files.
1388 For older changes see ChangeLog-2020
1390 Copyright (C) 2021-2023 Free Software Foundation, Inc.
1392 Copying and distribution of this file, with or without modification,
1393 are permitted in any medium without royalty provided the copyright
1394 notice and this notice are preserved.
1400 version-control: never