1 # Check 32bit AVX512{DQ,VL} instructions
6 vbroadcastf64x2
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
7 vbroadcastf64x2
(%ecx
), %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
8 vbroadcastf64x2
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
9 vbroadcastf64x2
2032(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
10 vbroadcastf64x2
2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
11 vbroadcastf64x2
-2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
12 vbroadcastf64x2
-2064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
13 vbroadcasti64x2
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
14 vbroadcasti64x2
(%ecx
), %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
15 vbroadcasti64x2
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
16 vbroadcasti64x2
2032(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
17 vbroadcasti64x2
2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
18 vbroadcasti64x2
-2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
19 vbroadcasti64x2
-2064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
20 vbroadcastf32x2
%xmm7
, %ymm6
{%k7
} # AVX512{DQ,VL}
21 vbroadcastf32x2
%xmm7
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
22 vbroadcastf32x2
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
23 vbroadcastf32x2
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
24 vbroadcastf32x2
1016(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
25 vbroadcastf32x2
1024(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
26 vbroadcastf32x2
-1024(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
27 vbroadcastf32x2
-1032(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
28 vcvtpd2qq
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
29 vcvtpd2qq
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
30 vcvtpd2qq
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
31 vcvtpd2qq
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
32 vcvtpd2qq
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
33 vcvtpd2qq
2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
34 vcvtpd2qq
2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
35 vcvtpd2qq
-2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
36 vcvtpd2qq
-2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
37 vcvtpd2qq
1016(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
38 vcvtpd2qq
1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
39 vcvtpd2qq
-1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
40 vcvtpd2qq
-1032(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
41 vcvtpd2qq
%ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
42 vcvtpd2qq
%ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
43 vcvtpd2qq
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
44 vcvtpd2qq
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
45 vcvtpd2qq
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
46 vcvtpd2qq
4064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
47 vcvtpd2qq
4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
48 vcvtpd2qq
-4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
49 vcvtpd2qq
-4128(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
50 vcvtpd2qq
1016(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
51 vcvtpd2qq
1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
52 vcvtpd2qq
-1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
53 vcvtpd2qq
-1032(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
54 vcvtpd2uqq
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
55 vcvtpd2uqq
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
56 vcvtpd2uqq
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
57 vcvtpd2uqq
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
58 vcvtpd2uqq
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
59 vcvtpd2uqq
2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
60 vcvtpd2uqq
2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
61 vcvtpd2uqq
-2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
62 vcvtpd2uqq
-2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
63 vcvtpd2uqq
1016(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
64 vcvtpd2uqq
1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
65 vcvtpd2uqq
-1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
66 vcvtpd2uqq
-1032(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
67 vcvtpd2uqq
%ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
68 vcvtpd2uqq
%ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
69 vcvtpd2uqq
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
70 vcvtpd2uqq
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
71 vcvtpd2uqq
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
72 vcvtpd2uqq
4064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
73 vcvtpd2uqq
4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
74 vcvtpd2uqq
-4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
75 vcvtpd2uqq
-4128(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
76 vcvtpd2uqq
1016(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
77 vcvtpd2uqq
1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
78 vcvtpd2uqq
-1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
79 vcvtpd2uqq
-1032(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
80 vcvtps2qq
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
81 vcvtps2qq
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
82 vcvtps2qq
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
83 vcvtps2qq
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
84 vcvtps2qq
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
85 vcvtps2qq
1016(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
86 vcvtps2qq
1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
87 vcvtps2qq
-1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
88 vcvtps2qq
-1032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
89 vcvtps2qq
508(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
90 vcvtps2qq
512(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
91 vcvtps2qq
-512(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
92 vcvtps2qq
-516(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
93 vcvtps2qq
%xmm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
94 vcvtps2qq
%xmm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
95 vcvtps2qq
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
96 vcvtps2qq
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
97 vcvtps2qq
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
98 vcvtps2qq
2032(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
99 vcvtps2qq
2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
100 vcvtps2qq
-2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
101 vcvtps2qq
-2064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
102 vcvtps2qq
508(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
103 vcvtps2qq
512(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
104 vcvtps2qq
-512(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
105 vcvtps2qq
-516(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
106 vcvtps2uqq
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
107 vcvtps2uqq
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
108 vcvtps2uqq
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
109 vcvtps2uqq
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
110 vcvtps2uqq
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
111 vcvtps2uqq
1016(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
112 vcvtps2uqq
1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
113 vcvtps2uqq
-1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
114 vcvtps2uqq
-1032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
115 vcvtps2uqq
508(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
116 vcvtps2uqq
512(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
117 vcvtps2uqq
-512(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
118 vcvtps2uqq
-516(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
119 vcvtps2uqq
%xmm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
120 vcvtps2uqq
%xmm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
121 vcvtps2uqq
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
122 vcvtps2uqq
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
123 vcvtps2uqq
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
124 vcvtps2uqq
2032(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
125 vcvtps2uqq
2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
126 vcvtps2uqq
-2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
127 vcvtps2uqq
-2064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
128 vcvtps2uqq
508(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
129 vcvtps2uqq
512(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
130 vcvtps2uqq
-512(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
131 vcvtps2uqq
-516(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
132 vcvtqq2pd
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
133 vcvtqq2pd
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
134 vcvtqq2pd
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
135 vcvtqq2pd
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
136 vcvtqq2pd
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
137 vcvtqq2pd
2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
138 vcvtqq2pd
2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
139 vcvtqq2pd
-2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
140 vcvtqq2pd
-2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
141 vcvtqq2pd
1016(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
142 vcvtqq2pd
1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
143 vcvtqq2pd
-1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
144 vcvtqq2pd
-1032(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
145 vcvtqq2pd
%ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
146 vcvtqq2pd
%ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
147 vcvtqq2pd
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
148 vcvtqq2pd
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
149 vcvtqq2pd
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
150 vcvtqq2pd
4064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
151 vcvtqq2pd
4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
152 vcvtqq2pd
-4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
153 vcvtqq2pd
-4128(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
154 vcvtqq2pd
1016(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
155 vcvtqq2pd
1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
156 vcvtqq2pd
-1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
157 vcvtqq2pd
-1032(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
158 vcvtqq2ps
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
159 vcvtqq2ps
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
160 vcvtqq2psx
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
161 vcvtqq2psx
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
162 vcvtqq2ps
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
163 vcvtqq2psx
2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
164 vcvtqq2psx
2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
165 vcvtqq2psx
-2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
166 vcvtqq2psx
-2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
167 vcvtqq2psx
1016(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
168 vcvtqq2psx
1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
169 vcvtqq2psx
-1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
170 vcvtqq2psx
-1032(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
171 vcvtqq2ps
%ymm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
172 vcvtqq2ps
%ymm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
173 vcvtqq2psy
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
174 vcvtqq2psy
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
175 vcvtqq2ps
(%eax
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL}
176 vcvtqq2psy
4064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
177 vcvtqq2psy
4096(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
178 vcvtqq2psy
-4096(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
179 vcvtqq2psy
-4128(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
180 vcvtqq2psy
1016(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
181 vcvtqq2psy
1024(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL}
182 vcvtqq2psy
-1024(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
183 vcvtqq2psy
-1032(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL}
184 vcvtuqq2pd
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
185 vcvtuqq2pd
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
186 vcvtuqq2pd
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
187 vcvtuqq2pd
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
188 vcvtuqq2pd
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
189 vcvtuqq2pd
2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
190 vcvtuqq2pd
2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
191 vcvtuqq2pd
-2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
192 vcvtuqq2pd
-2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
193 vcvtuqq2pd
1016(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
194 vcvtuqq2pd
1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
195 vcvtuqq2pd
-1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
196 vcvtuqq2pd
-1032(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
197 vcvtuqq2pd
%ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
198 vcvtuqq2pd
%ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
199 vcvtuqq2pd
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
200 vcvtuqq2pd
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
201 vcvtuqq2pd
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
202 vcvtuqq2pd
4064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
203 vcvtuqq2pd
4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
204 vcvtuqq2pd
-4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
205 vcvtuqq2pd
-4128(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
206 vcvtuqq2pd
1016(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
207 vcvtuqq2pd
1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
208 vcvtuqq2pd
-1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
209 vcvtuqq2pd
-1032(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
210 vcvtuqq2ps
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
211 vcvtuqq2ps
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
212 vcvtuqq2psx
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
213 vcvtuqq2psx
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
214 vcvtuqq2ps
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
215 vcvtuqq2psx
2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
216 vcvtuqq2psx
2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
217 vcvtuqq2psx
-2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
218 vcvtuqq2psx
-2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
219 vcvtuqq2psx
1016(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
220 vcvtuqq2psx
1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
221 vcvtuqq2psx
-1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
222 vcvtuqq2psx
-1032(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
223 vcvtuqq2ps
%ymm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
224 vcvtuqq2ps
%ymm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
225 vcvtuqq2psy
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
226 vcvtuqq2psy
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
227 vcvtuqq2ps
(%eax
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL}
228 vcvtuqq2psy
4064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
229 vcvtuqq2psy
4096(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
230 vcvtuqq2psy
-4096(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
231 vcvtuqq2psy
-4128(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
232 vcvtuqq2psy
1016(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
233 vcvtuqq2psy
1024(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL}
234 vcvtuqq2psy
-1024(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
235 vcvtuqq2psy
-1032(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL}
236 vextractf64x2 $
0xab, %ymm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
237 vextractf64x2 $
0xab, %ymm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
238 vextractf64x2 $
123, %ymm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
239 vextracti64x2 $
0xab, %ymm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
240 vextracti64x2 $
0xab, %ymm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
241 vextracti64x2 $
123, %ymm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
242 vfpclasspd $
0xab, %xmm6
, %k5
{%k7
} # AVX512{DQ,VL}
243 vfpclasspd $
123, %xmm6
, %k5
{%k7
} # AVX512{DQ,VL}
244 vfpclasspdx $
123, (%ecx
), %k5
{%k7
} # AVX512{DQ,VL}
245 vfpclasspdx $
123, -123456(%esp
,%esi
,8), %k5
{%k7
} # AVX512{DQ,VL}
246 vfpclasspd $
123, (%eax
){1to2
}, %k5
{%k7
} # AVX512{DQ,VL}
247 vfpclasspdx $
123, 2032(%edx
), %k5
{%k7
} # AVX512{DQ,VL} Disp8
248 vfpclasspdx $
123, 2048(%edx
), %k5
{%k7
} # AVX512{DQ,VL}
249 vfpclasspdx $
123, -2048(%edx
), %k5
{%k7
} # AVX512{DQ,VL} Disp8
250 vfpclasspdx $
123, -2064(%edx
), %k5
{%k7
} # AVX512{DQ,VL}
251 vfpclasspdx $
123, 1016(%edx
){1to2
}, %k5
{%k7
} # AVX512{DQ,VL} Disp8
252 vfpclasspdx $
123, 1024(%edx
){1to2
}, %k5
{%k7
} # AVX512{DQ,VL}
253 vfpclasspdx $
123, -1024(%edx
){1to2
}, %k5
{%k7
} # AVX512{DQ,VL} Disp8
254 vfpclasspdx $
123, -1032(%edx
){1to2
}, %k5
{%k7
} # AVX512{DQ,VL}
255 vfpclasspd $
0xab, %ymm6
, %k5
{%k7
} # AVX512{DQ,VL}
256 vfpclasspd $
123, %ymm6
, %k5
{%k7
} # AVX512{DQ,VL}
257 vfpclasspdy $
123, (%ecx
), %k5
{%k7
} # AVX512{DQ,VL}
258 vfpclasspdy $
123, -123456(%esp
,%esi
,8), %k5
{%k7
} # AVX512{DQ,VL}
259 vfpclasspd $
123, (%eax
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL}
260 vfpclasspdy $
123, 4064(%edx
), %k5
{%k7
} # AVX512{DQ,VL} Disp8
261 vfpclasspdy $
123, 4096(%edx
), %k5
{%k7
} # AVX512{DQ,VL}
262 vfpclasspdy $
123, -4096(%edx
), %k5
{%k7
} # AVX512{DQ,VL} Disp8
263 vfpclasspdy $
123, -4128(%edx
), %k5
{%k7
} # AVX512{DQ,VL}
264 vfpclasspdy $
123, 1016(%edx
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL} Disp8
265 vfpclasspdy $
123, 1024(%edx
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL}
266 vfpclasspdy $
123, -1024(%edx
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL} Disp8
267 vfpclasspdy $
123, -1032(%edx
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL}
268 vfpclassps $
0xab, %xmm6
, %k5
{%k7
} # AVX512{DQ,VL}
269 vfpclassps $
123, %xmm6
, %k5
{%k7
} # AVX512{DQ,VL}
270 vfpclasspsx $
123, (%ecx
), %k5
{%k7
} # AVX512{DQ,VL}
271 vfpclasspsx $
123, -123456(%esp
,%esi
,8), %k5
{%k7
} # AVX512{DQ,VL}
272 vfpclassps $
123, (%eax
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL}
273 vfpclasspsx $
123, 2032(%edx
), %k5
{%k7
} # AVX512{DQ,VL} Disp8
274 vfpclasspsx $
123, 2048(%edx
), %k5
{%k7
} # AVX512{DQ,VL}
275 vfpclasspsx $
123, -2048(%edx
), %k5
{%k7
} # AVX512{DQ,VL} Disp8
276 vfpclasspsx $
123, -2064(%edx
), %k5
{%k7
} # AVX512{DQ,VL}
277 vfpclasspsx $
123, 508(%edx
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL} Disp8
278 vfpclasspsx $
123, 512(%edx
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL}
279 vfpclasspsx $
123, -512(%edx
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL} Disp8
280 vfpclasspsx $
123, -516(%edx
){1to4
}, %k5
{%k7
} # AVX512{DQ,VL}
281 vfpclassps $
0xab, %ymm6
, %k5
{%k7
} # AVX512{DQ,VL}
282 vfpclassps $
123, %ymm6
, %k5
{%k7
} # AVX512{DQ,VL}
283 vfpclasspsy $
123, (%ecx
), %k5
{%k7
} # AVX512{DQ,VL}
284 vfpclasspsy $
123, -123456(%esp
,%esi
,8), %k5
{%k7
} # AVX512{DQ,VL}
285 vfpclassps $
123, (%eax
){1to8
}, %k5
{%k7
} # AVX512{DQ,VL}
286 vfpclasspsy $
123, 4064(%edx
), %k5
{%k7
} # AVX512{DQ,VL} Disp8
287 vfpclasspsy $
123, 4096(%edx
), %k5
{%k7
} # AVX512{DQ,VL}
288 vfpclasspsy $
123, -4096(%edx
), %k5
{%k7
} # AVX512{DQ,VL} Disp8
289 vfpclasspsy $
123, -4128(%edx
), %k5
{%k7
} # AVX512{DQ,VL}
290 vfpclasspsy $
123, 508(%edx
){1to8
}, %k5
{%k7
} # AVX512{DQ,VL} Disp8
291 vfpclasspsy $
123, 512(%edx
){1to8
}, %k5
{%k7
} # AVX512{DQ,VL}
292 vfpclasspsy $
123, -512(%edx
){1to8
}, %k5
{%k7
} # AVX512{DQ,VL} Disp8
293 vfpclasspsy $
123, -516(%edx
){1to8
}, %k5
{%k7
} # AVX512{DQ,VL}
294 vinsertf64x2 $
0xab, %xmm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
295 vinsertf64x2 $
0xab, %xmm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
296 vinsertf64x2 $
123, %xmm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
297 vinsertf64x2 $
123, (%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
298 vinsertf64x2 $
123, -123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
299 vinsertf64x2 $
123, 2032(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
300 vinsertf64x2 $
123, 2048(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
301 vinsertf64x2 $
123, -2048(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
302 vinsertf64x2 $
123, -2064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
303 vinserti64x2 $
0xab, %xmm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
304 vinserti64x2 $
0xab, %xmm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
305 vinserti64x2 $
123, %xmm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
306 vinserti64x2 $
123, (%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
307 vinserti64x2 $
123, -123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
308 vinserti64x2 $
123, 2032(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
309 vinserti64x2 $
123, 2048(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
310 vinserti64x2 $
123, -2048(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
311 vinserti64x2 $
123, -2064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
312 vbroadcasti32x2
%xmm7
, %xmm6
{%k7
} # AVX512{DQ,VL}
313 vbroadcasti32x2
%xmm7
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
314 vbroadcasti32x2
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
315 vbroadcasti32x2
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
316 vbroadcasti32x2
1016(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
317 vbroadcasti32x2
1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
318 vbroadcasti32x2
-1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
319 vbroadcasti32x2
-1032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
320 vbroadcasti32x2
%xmm7
, %ymm6
{%k7
} # AVX512{DQ,VL}
321 vbroadcasti32x2
%xmm7
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
322 vbroadcasti32x2
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
323 vbroadcasti32x2
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
324 vbroadcasti32x2
1016(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
325 vbroadcasti32x2
1024(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
326 vbroadcasti32x2
-1024(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
327 vbroadcasti32x2
-1032(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
328 vpmullq
%xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
329 vpmullq
%xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
330 vpmullq
(%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
331 vpmullq
-123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
332 vpmullq
(%eax
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
333 vpmullq
2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
334 vpmullq
2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
335 vpmullq
-2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
336 vpmullq
-2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
337 vpmullq
1016(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
338 vpmullq
1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
339 vpmullq
-1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
340 vpmullq
-1032(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
341 vpmullq
%ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
342 vpmullq
%ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
343 vpmullq
(%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
344 vpmullq
-123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
345 vpmullq
(%eax
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
346 vpmullq
4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
347 vpmullq
4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
348 vpmullq
-4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
349 vpmullq
-4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
350 vpmullq
1016(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
351 vpmullq
1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
352 vpmullq
-1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
353 vpmullq
-1032(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
354 vrangepd $
0xab, %xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
355 vrangepd $
0xab, %xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
356 vrangepd $
123, %xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
357 vrangepd $
123, (%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
358 vrangepd $
123, -123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
359 vrangepd $
123, (%eax
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
360 vrangepd $
123, 2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
361 vrangepd $
123, 2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
362 vrangepd $
123, -2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
363 vrangepd $
123, -2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
364 vrangepd $
123, 1016(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
365 vrangepd $
123, 1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
366 vrangepd $
123, -1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
367 vrangepd $
123, -1032(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
368 vrangepd $
0xab, %ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
369 vrangepd $
0xab, %ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
370 vrangepd $
123, %ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
371 vrangepd $
123, (%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
372 vrangepd $
123, -123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
373 vrangepd $
123, (%eax
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
374 vrangepd $
123, 4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
375 vrangepd $
123, 4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
376 vrangepd $
123, -4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
377 vrangepd $
123, -4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
378 vrangepd $
123, 1016(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
379 vrangepd $
123, 1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
380 vrangepd $
123, -1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
381 vrangepd $
123, -1032(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
382 vrangeps $
0xab, %xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
383 vrangeps $
0xab, %xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
384 vrangeps $
123, %xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
385 vrangeps $
123, (%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
386 vrangeps $
123, -123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
387 vrangeps $
123, (%eax
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
388 vrangeps $
123, 2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
389 vrangeps $
123, 2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
390 vrangeps $
123, -2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
391 vrangeps $
123, -2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
392 vrangeps $
123, 508(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
393 vrangeps $
123, 512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
394 vrangeps $
123, -512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
395 vrangeps $
123, -516(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
396 vrangeps $
0xab, %ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
397 vrangeps $
0xab, %ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
398 vrangeps $
123, %ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
399 vrangeps $
123, (%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
400 vrangeps $
123, -123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
401 vrangeps $
123, (%eax
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
402 vrangeps $
123, 4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
403 vrangeps $
123, 4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
404 vrangeps $
123, -4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
405 vrangeps $
123, -4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
406 vrangeps $
123, 508(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
407 vrangeps $
123, 512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
408 vrangeps $
123, -512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
409 vrangeps $
123, -516(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
410 vandpd
%xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
411 vandpd
%xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
412 vandpd
(%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
413 vandpd
-123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
414 vandpd
(%eax
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
415 vandpd
2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
416 vandpd
2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
417 vandpd
-2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
418 vandpd
-2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
419 vandpd
1016(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
420 vandpd
1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
421 vandpd
-1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
422 vandpd
-1032(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
423 vandpd
%ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
424 vandpd
%ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
425 vandpd
(%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
426 vandpd
-123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
427 vandpd
(%eax
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
428 vandpd
4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
429 vandpd
4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
430 vandpd
-4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
431 vandpd
-4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
432 vandpd
1016(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
433 vandpd
1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
434 vandpd
-1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
435 vandpd
-1032(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
436 vandps
%xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
437 vandps
%xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
438 vandps
(%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
439 vandps
-123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
440 vandps
(%eax
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
441 vandps
2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
442 vandps
2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
443 vandps
-2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
444 vandps
-2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
445 vandps
508(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
446 vandps
512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
447 vandps
-512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
448 vandps
-516(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
449 vandps
%ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
450 vandps
%ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
451 vandps
(%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
452 vandps
-123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
453 vandps
(%eax
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
454 vandps
4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
455 vandps
4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
456 vandps
-4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
457 vandps
-4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
458 vandps
508(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
459 vandps
512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
460 vandps
-512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
461 vandps
-516(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
462 vandnpd
%xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
463 vandnpd
%xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
464 vandnpd
(%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
465 vandnpd
-123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
466 vandnpd
(%eax
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
467 vandnpd
2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
468 vandnpd
2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
469 vandnpd
-2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
470 vandnpd
-2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
471 vandnpd
1016(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
472 vandnpd
1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
473 vandnpd
-1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
474 vandnpd
-1032(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
475 vandnpd
%ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
476 vandnpd
%ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
477 vandnpd
(%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
478 vandnpd
-123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
479 vandnpd
(%eax
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
480 vandnpd
4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
481 vandnpd
4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
482 vandnpd
-4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
483 vandnpd
-4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
484 vandnpd
1016(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
485 vandnpd
1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
486 vandnpd
-1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
487 vandnpd
-1032(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
488 vandnps
%xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
489 vandnps
%xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
490 vandnps
(%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
491 vandnps
-123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
492 vandnps
(%eax
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
493 vandnps
2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
494 vandnps
2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
495 vandnps
-2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
496 vandnps
-2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
497 vandnps
508(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
498 vandnps
512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
499 vandnps
-512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
500 vandnps
-516(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
501 vandnps
%ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
502 vandnps
%ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
503 vandnps
(%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
504 vandnps
-123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
505 vandnps
(%eax
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
506 vandnps
4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
507 vandnps
4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
508 vandnps
-4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
509 vandnps
-4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
510 vandnps
508(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
511 vandnps
512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
512 vandnps
-512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
513 vandnps
-516(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
514 vorpd
%xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
515 vorpd
%xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
516 vorpd
(%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
517 vorpd
-123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
518 vorpd
(%eax
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
519 vorpd
2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
520 vorpd
2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
521 vorpd
-2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
522 vorpd
-2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
523 vorpd
1016(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
524 vorpd
1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
525 vorpd
-1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
526 vorpd
-1032(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
527 vorpd
%ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
528 vorpd
%ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
529 vorpd
(%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
530 vorpd
-123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
531 vorpd
(%eax
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
532 vorpd
4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
533 vorpd
4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
534 vorpd
-4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
535 vorpd
-4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
536 vorpd
1016(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
537 vorpd
1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
538 vorpd
-1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
539 vorpd
-1032(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
540 vorps
%xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
541 vorps
%xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
542 vorps
(%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
543 vorps
-123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
544 vorps
(%eax
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
545 vorps
2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
546 vorps
2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
547 vorps
-2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
548 vorps
-2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
549 vorps
508(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
550 vorps
512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
551 vorps
-512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
552 vorps
-516(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
553 vorps
%ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
554 vorps
%ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
555 vorps
(%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
556 vorps
-123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
557 vorps
(%eax
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
558 vorps
4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
559 vorps
4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
560 vorps
-4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
561 vorps
-4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
562 vorps
508(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
563 vorps
512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
564 vorps
-512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
565 vorps
-516(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
566 vxorpd
%xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
567 vxorpd
%xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
568 vxorpd
(%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
569 vxorpd
-123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
570 vxorpd
(%eax
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
571 vxorpd
2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
572 vxorpd
2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
573 vxorpd
-2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
574 vxorpd
-2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
575 vxorpd
1016(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
576 vxorpd
1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
577 vxorpd
-1024(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
578 vxorpd
-1032(%edx
){1to2
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
579 vxorpd
%ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
580 vxorpd
%ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
581 vxorpd
(%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
582 vxorpd
-123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
583 vxorpd
(%eax
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
584 vxorpd
4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
585 vxorpd
4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
586 vxorpd
-4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
587 vxorpd
-4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
588 vxorpd
1016(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
589 vxorpd
1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
590 vxorpd
-1024(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
591 vxorpd
-1032(%edx
){1to4
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
592 vxorps
%xmm4
, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
593 vxorps
%xmm4
, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
594 vxorps
(%ecx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
595 vxorps
-123456(%esp
,%esi
,8), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
596 vxorps
(%eax
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
597 vxorps
2032(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
598 vxorps
2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
599 vxorps
-2048(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
600 vxorps
-2064(%edx
), %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
601 vxorps
508(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
602 vxorps
512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
603 vxorps
-512(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
604 vxorps
-516(%edx
){1to4
}, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
605 vxorps
%ymm4
, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
606 vxorps
%ymm4
, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
607 vxorps
(%ecx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
608 vxorps
-123456(%esp
,%esi
,8), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
609 vxorps
(%eax
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
610 vxorps
4064(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
611 vxorps
4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
612 vxorps
-4096(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
613 vxorps
-4128(%edx
), %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
614 vxorps
508(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
615 vxorps
512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
616 vxorps
-512(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
617 vxorps
-516(%edx
){1to8
}, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
618 vreducepd $
0xab, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
619 vreducepd $
0xab, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
620 vreducepd $
123, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
621 vreducepd $
123, (%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
622 vreducepd $
123, -123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
623 vreducepd $
123, (%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
624 vreducepd $
123, 2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
625 vreducepd $
123, 2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
626 vreducepd $
123, -2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
627 vreducepd $
123, -2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
628 vreducepd $
123, 1016(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
629 vreducepd $
123, 1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
630 vreducepd $
123, -1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
631 vreducepd $
123, -1032(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
632 vreducepd $
0xab, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
633 vreducepd $
0xab, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
634 vreducepd $
123, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
635 vreducepd $
123, (%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
636 vreducepd $
123, -123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
637 vreducepd $
123, (%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
638 vreducepd $
123, 4064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
639 vreducepd $
123, 4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
640 vreducepd $
123, -4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
641 vreducepd $
123, -4128(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
642 vreducepd $
123, 1016(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
643 vreducepd $
123, 1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
644 vreducepd $
123, -1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
645 vreducepd $
123, -1032(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
646 vreduceps $
0xab, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
647 vreduceps $
0xab, %xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
648 vreduceps $
123, %xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
649 vreduceps $
123, (%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
650 vreduceps $
123, -123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
651 vreduceps $
123, (%eax
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL}
652 vreduceps $
123, 2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
653 vreduceps $
123, 2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
654 vreduceps $
123, -2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
655 vreduceps $
123, -2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
656 vreduceps $
123, 508(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
657 vreduceps $
123, 512(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL}
658 vreduceps $
123, -512(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
659 vreduceps $
123, -516(%edx
){1to4
}, %xmm6
{%k7
} # AVX512{DQ,VL}
660 vreduceps $
0xab, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
661 vreduceps $
0xab, %ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
662 vreduceps $
123, %ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
663 vreduceps $
123, (%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
664 vreduceps $
123, -123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
665 vreduceps $
123, (%eax
){1to8
}, %ymm6
{%k7
} # AVX512{DQ,VL}
666 vreduceps $
123, 4064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
667 vreduceps $
123, 4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
668 vreduceps $
123, -4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
669 vreduceps $
123, -4128(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
670 vreduceps $
123, 508(%edx
){1to8
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
671 vreduceps $
123, 512(%edx
){1to8
}, %ymm6
{%k7
} # AVX512{DQ,VL}
672 vreduceps $
123, -512(%edx
){1to8
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
673 vreduceps $
123, -516(%edx
){1to8
}, %ymm6
{%k7
} # AVX512{DQ,VL}
674 vextractf64x2 $
0xab, %ymm5
, (%ecx
){%k7
} # AVX512{DQ,VL}
675 vextractf64x2 $
123, %ymm5
, (%ecx
){%k7
} # AVX512{DQ,VL}
676 vextractf64x2 $
123, %ymm5
, -123456(%esp
,%esi
,8){%k7
} # AVX512{DQ,VL}
677 vextractf64x2 $
123, %ymm5
, 2032(%edx
){%k7
} # AVX512{DQ,VL} Disp8
678 vextractf64x2 $
123, %ymm5
, 2048(%edx
){%k7
} # AVX512{DQ,VL}
679 vextractf64x2 $
123, %ymm5
, -2048(%edx
){%k7
} # AVX512{DQ,VL} Disp8
680 vextractf64x2 $
123, %ymm5
, -2064(%edx
){%k7
} # AVX512{DQ,VL}
681 vextracti64x2 $
0xab, %ymm5
, (%ecx
){%k7
} # AVX512{DQ,VL}
682 vextracti64x2 $
123, %ymm5
, (%ecx
){%k7
} # AVX512{DQ,VL}
683 vextracti64x2 $
123, %ymm5
, -123456(%esp
,%esi
,8){%k7
} # AVX512{DQ,VL}
684 vextracti64x2 $
123, %ymm5
, 2032(%edx
){%k7
} # AVX512{DQ,VL} Disp8
685 vextracti64x2 $
123, %ymm5
, 2048(%edx
){%k7
} # AVX512{DQ,VL}
686 vextracti64x2 $
123, %ymm5
, -2048(%edx
){%k7
} # AVX512{DQ,VL} Disp8
687 vextracti64x2 $
123, %ymm5
, -2064(%edx
){%k7
} # AVX512{DQ,VL}
688 vcvttpd2qq
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
689 vcvttpd2qq
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
690 vcvttpd2qq
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
691 vcvttpd2qq
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
692 vcvttpd2qq
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
693 vcvttpd2qq
2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
694 vcvttpd2qq
2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
695 vcvttpd2qq
-2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
696 vcvttpd2qq
-2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
697 vcvttpd2qq
1016(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
698 vcvttpd2qq
1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
699 vcvttpd2qq
-1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
700 vcvttpd2qq
-1032(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
701 vcvttpd2qq
%ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
702 vcvttpd2qq
%ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
703 vcvttpd2qq
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
704 vcvttpd2qq
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
705 vcvttpd2qq
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
706 vcvttpd2qq
4064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
707 vcvttpd2qq
4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
708 vcvttpd2qq
-4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
709 vcvttpd2qq
-4128(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
710 vcvttpd2qq
1016(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
711 vcvttpd2qq
1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
712 vcvttpd2qq
-1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
713 vcvttpd2qq
-1032(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
714 vcvttpd2uqq
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
715 vcvttpd2uqq
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
716 vcvttpd2uqq
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
717 vcvttpd2uqq
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
718 vcvttpd2uqq
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
719 vcvttpd2uqq
2032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
720 vcvttpd2uqq
2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
721 vcvttpd2uqq
-2048(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
722 vcvttpd2uqq
-2064(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
723 vcvttpd2uqq
1016(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
724 vcvttpd2uqq
1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
725 vcvttpd2uqq
-1024(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
726 vcvttpd2uqq
-1032(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
727 vcvttpd2uqq
%ymm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
728 vcvttpd2uqq
%ymm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
729 vcvttpd2uqq
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
730 vcvttpd2uqq
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
731 vcvttpd2uqq
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
732 vcvttpd2uqq
4064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
733 vcvttpd2uqq
4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
734 vcvttpd2uqq
-4096(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
735 vcvttpd2uqq
-4128(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
736 vcvttpd2uqq
1016(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
737 vcvttpd2uqq
1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
738 vcvttpd2uqq
-1024(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
739 vcvttpd2uqq
-1032(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
740 vcvttps2qq
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
741 vcvttps2qq
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
742 vcvttps2qq
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
743 vcvttps2qq
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
744 vcvttps2qq
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
745 vcvttps2qq
1016(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
746 vcvttps2qq
1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
747 vcvttps2qq
-1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
748 vcvttps2qq
-1032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
749 vcvttps2qq
508(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
750 vcvttps2qq
512(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
751 vcvttps2qq
-512(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
752 vcvttps2qq
-516(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
753 vcvttps2qq
%xmm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
754 vcvttps2qq
%xmm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
755 vcvttps2qq
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
756 vcvttps2qq
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
757 vcvttps2qq
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
758 vcvttps2qq
2032(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
759 vcvttps2qq
2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
760 vcvttps2qq
-2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
761 vcvttps2qq
-2064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
762 vcvttps2qq
508(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
763 vcvttps2qq
512(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
764 vcvttps2qq
-512(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
765 vcvttps2qq
-516(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
766 vcvttps2uqq
%xmm5
, %xmm6
{%k7
} # AVX512{DQ,VL}
767 vcvttps2uqq
%xmm5
, %xmm6
{%k7
}{z
} # AVX512{DQ,VL}
768 vcvttps2uqq
(%ecx
), %xmm6
{%k7
} # AVX512{DQ,VL}
769 vcvttps2uqq
-123456(%esp
,%esi
,8), %xmm6
{%k7
} # AVX512{DQ,VL}
770 vcvttps2uqq
(%eax
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
771 vcvttps2uqq
1016(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
772 vcvttps2uqq
1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
773 vcvttps2uqq
-1024(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
774 vcvttps2uqq
-1032(%edx
), %xmm6
{%k7
} # AVX512{DQ,VL}
775 vcvttps2uqq
508(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
776 vcvttps2uqq
512(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
777 vcvttps2uqq
-512(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL} Disp8
778 vcvttps2uqq
-516(%edx
){1to2
}, %xmm6
{%k7
} # AVX512{DQ,VL}
779 vcvttps2uqq
%xmm5
, %ymm6
{%k7
} # AVX512{DQ,VL}
780 vcvttps2uqq
%xmm5
, %ymm6
{%k7
}{z
} # AVX512{DQ,VL}
781 vcvttps2uqq
(%ecx
), %ymm6
{%k7
} # AVX512{DQ,VL}
782 vcvttps2uqq
-123456(%esp
,%esi
,8), %ymm6
{%k7
} # AVX512{DQ,VL}
783 vcvttps2uqq
(%eax
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
784 vcvttps2uqq
2032(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
785 vcvttps2uqq
2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
786 vcvttps2uqq
-2048(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
787 vcvttps2uqq
-2064(%edx
), %ymm6
{%k7
} # AVX512{DQ,VL}
788 vcvttps2uqq
508(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
789 vcvttps2uqq
512(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
790 vcvttps2uqq
-512(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL} Disp8
791 vcvttps2uqq
-516(%edx
){1to4
}, %ymm6
{%k7
} # AVX512{DQ,VL}
792 vpmovd2m
%xmm6
, %k5
# AVX512{DQ,VL}
793 vpmovd2m
%ymm6
, %k5
# AVX512{DQ,VL}
794 vpmovq2m
%xmm6
, %k5
# AVX512{DQ,VL}
795 vpmovq2m
%ymm6
, %k5
# AVX512{DQ,VL}
796 vpmovm2d
%k5
, %xmm6
# AVX512{DQ,VL}
797 vpmovm2d
%k5
, %ymm6
# AVX512{DQ,VL}
798 vpmovm2q
%k5
, %xmm6
# AVX512{DQ,VL}
799 vpmovm2q
%k5
, %ymm6
# AVX512{DQ,VL}
801 .intel_syntax noprefix
802 vbroadcastf64x2 ymm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
803 vbroadcastf64x2 ymm6
{k7
}{z
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
804 vbroadcastf64x2 ymm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
805 vbroadcastf64x2 ymm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
806 vbroadcastf64x2 ymm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
807 vbroadcastf64x2 ymm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
808 vbroadcastf64x2 ymm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
809 vbroadcasti64x2 ymm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
810 vbroadcasti64x2 ymm6
{k7
}{z
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
811 vbroadcasti64x2 ymm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
812 vbroadcasti64x2 ymm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
813 vbroadcasti64x2 ymm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
814 vbroadcasti64x2 ymm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
815 vbroadcasti64x2 ymm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
816 vbroadcastf32x2 ymm6
{k7
}, xmm7
# AVX512{DQ,VL}
817 vbroadcastf32x2 ymm6
{k7
}{z
}, xmm7
# AVX512{DQ,VL}
818 vbroadcastf32x2 ymm6
{k7
}, QWORD PTR
[ecx
] # AVX512{DQ,VL}
819 vbroadcastf32x2 ymm6
{k7
}, QWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
820 vbroadcastf32x2 ymm6
{k7
}, QWORD PTR
[edx+
1016] # AVX512{DQ,VL} Disp8
821 vbroadcastf32x2 ymm6
{k7
}, QWORD PTR
[edx+
1024] # AVX512{DQ,VL}
822 vbroadcastf32x2 ymm6
{k7
}, QWORD PTR
[edx-
1024] # AVX512{DQ,VL} Disp8
823 vbroadcastf32x2 ymm6
{k7
}, QWORD PTR
[edx-
1032] # AVX512{DQ,VL}
824 vcvtpd2qq xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
825 vcvtpd2qq xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
826 vcvtpd2qq xmm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
827 vcvtpd2qq xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
828 vcvtpd2qq xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
829 vcvtpd2qq xmm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
830 vcvtpd2qq xmm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
831 vcvtpd2qq xmm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
832 vcvtpd2qq xmm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
833 vcvtpd2qq xmm6
{k7
}, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
834 vcvtpd2qq xmm6
{k7
}, [edx+
1024]{1to2
} # AVX512{DQ,VL}
835 vcvtpd2qq xmm6
{k7
}, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
836 vcvtpd2qq xmm6
{k7
}, [edx-
1032]{1to2
} # AVX512{DQ,VL}
837 vcvtpd2qq ymm6
{k7
}, ymm5
# AVX512{DQ,VL}
838 vcvtpd2qq ymm6
{k7
}{z
}, ymm5
# AVX512{DQ,VL}
839 vcvtpd2qq ymm6
{k7
}, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
840 vcvtpd2qq ymm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
841 vcvtpd2qq ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
842 vcvtpd2qq ymm6
{k7
}, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
843 vcvtpd2qq ymm6
{k7
}, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
844 vcvtpd2qq ymm6
{k7
}, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
845 vcvtpd2qq ymm6
{k7
}, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
846 vcvtpd2qq ymm6
{k7
}, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
847 vcvtpd2qq ymm6
{k7
}, [edx+
1024]{1to4
} # AVX512{DQ,VL}
848 vcvtpd2qq ymm6
{k7
}, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
849 vcvtpd2qq ymm6
{k7
}, [edx-
1032]{1to4
} # AVX512{DQ,VL}
850 vcvtpd2uqq xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
851 vcvtpd2uqq xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
852 vcvtpd2uqq xmm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
853 vcvtpd2uqq xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
854 vcvtpd2uqq xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
855 vcvtpd2uqq xmm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
856 vcvtpd2uqq xmm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
857 vcvtpd2uqq xmm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
858 vcvtpd2uqq xmm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
859 vcvtpd2uqq xmm6
{k7
}, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
860 vcvtpd2uqq xmm6
{k7
}, [edx+
1024]{1to2
} # AVX512{DQ,VL}
861 vcvtpd2uqq xmm6
{k7
}, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
862 vcvtpd2uqq xmm6
{k7
}, [edx-
1032]{1to2
} # AVX512{DQ,VL}
863 vcvtpd2uqq ymm6
{k7
}, ymm5
# AVX512{DQ,VL}
864 vcvtpd2uqq ymm6
{k7
}{z
}, ymm5
# AVX512{DQ,VL}
865 vcvtpd2uqq ymm6
{k7
}, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
866 vcvtpd2uqq ymm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
867 vcvtpd2uqq ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
868 vcvtpd2uqq ymm6
{k7
}, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
869 vcvtpd2uqq ymm6
{k7
}, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
870 vcvtpd2uqq ymm6
{k7
}, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
871 vcvtpd2uqq ymm6
{k7
}, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
872 vcvtpd2uqq ymm6
{k7
}, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
873 vcvtpd2uqq ymm6
{k7
}, [edx+
1024]{1to4
} # AVX512{DQ,VL}
874 vcvtpd2uqq ymm6
{k7
}, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
875 vcvtpd2uqq ymm6
{k7
}, [edx-
1032]{1to4
} # AVX512{DQ,VL}
876 vcvtps2qq xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
877 vcvtps2qq xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
878 vcvtps2qq xmm6
{k7
}, QWORD PTR
[ecx
] # AVX512{DQ,VL}
879 vcvtps2qq xmm6
{k7
}, QWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
880 vcvtps2qq xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
881 vcvtps2qq xmm6
{k7
}, QWORD PTR
[edx+
1016] # AVX512{DQ,VL} Disp8
882 vcvtps2qq xmm6
{k7
}, QWORD PTR
[edx+
1024] # AVX512{DQ,VL}
883 vcvtps2qq xmm6
{k7
}, QWORD PTR
[edx-
1024] # AVX512{DQ,VL} Disp8
884 vcvtps2qq xmm6
{k7
}, QWORD PTR
[edx-
1032] # AVX512{DQ,VL}
885 vcvtps2qq xmm6
{k7
}, [edx+
508]{1to2
} # AVX512{DQ,VL} Disp8
886 vcvtps2qq xmm6
{k7
}, [edx+
512]{1to2
} # AVX512{DQ,VL}
887 vcvtps2qq xmm6
{k7
}, [edx-
512]{1to2
} # AVX512{DQ,VL} Disp8
888 vcvtps2qq xmm6
{k7
}, [edx-
516]{1to2
} # AVX512{DQ,VL}
889 vcvtps2qq xmm6
{k7
}, DWORD BCST
[edx+
508] # AVX512{DQ,VL} Disp8
890 vcvtps2qq ymm6
{k7
}, xmm5
# AVX512{DQ,VL}
891 vcvtps2qq ymm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
892 vcvtps2qq ymm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
893 vcvtps2qq ymm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
894 vcvtps2qq ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
895 vcvtps2qq ymm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
896 vcvtps2qq ymm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
897 vcvtps2qq ymm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
898 vcvtps2qq ymm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
899 vcvtps2qq ymm6
{k7
}, [edx+
508]{1to4
} # AVX512{DQ,VL} Disp8
900 vcvtps2qq ymm6
{k7
}, [edx+
512]{1to4
} # AVX512{DQ,VL}
901 vcvtps2qq ymm6
{k7
}, [edx-
512]{1to4
} # AVX512{DQ,VL} Disp8
902 vcvtps2qq ymm6
{k7
}, [edx-
516]{1to4
} # AVX512{DQ,VL}
903 vcvtps2qq ymm6
{k7
}, DWORD BCST
[edx+
508] # AVX512{DQ,VL} Disp8
904 vcvtps2uqq xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
905 vcvtps2uqq xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
906 vcvtps2uqq xmm6
{k7
}, QWORD PTR
[ecx
] # AVX512{DQ,VL}
907 vcvtps2uqq xmm6
{k7
}, QWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
908 vcvtps2uqq xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
909 vcvtps2uqq xmm6
{k7
}, QWORD PTR
[edx+
1016] # AVX512{DQ,VL} Disp8
910 vcvtps2uqq xmm6
{k7
}, QWORD PTR
[edx+
1024] # AVX512{DQ,VL}
911 vcvtps2uqq xmm6
{k7
}, QWORD PTR
[edx-
1024] # AVX512{DQ,VL} Disp8
912 vcvtps2uqq xmm6
{k7
}, QWORD PTR
[edx-
1032] # AVX512{DQ,VL}
913 vcvtps2uqq xmm6
{k7
}, [edx+
508]{1to2
} # AVX512{DQ,VL} Disp8
914 vcvtps2uqq xmm6
{k7
}, [edx+
512]{1to2
} # AVX512{DQ,VL}
915 vcvtps2uqq xmm6
{k7
}, [edx-
512]{1to2
} # AVX512{DQ,VL} Disp8
916 vcvtps2uqq xmm6
{k7
}, [edx-
516]{1to2
} # AVX512{DQ,VL}
917 vcvtps2uqq xmm6
{k7
}, DWORD BCST
[edx+
508] # AVX512{DQ,VL} Disp8
918 vcvtps2uqq ymm6
{k7
}, xmm5
# AVX512{DQ,VL}
919 vcvtps2uqq ymm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
920 vcvtps2uqq ymm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
921 vcvtps2uqq ymm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
922 vcvtps2uqq ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
923 vcvtps2uqq ymm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
924 vcvtps2uqq ymm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
925 vcvtps2uqq ymm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
926 vcvtps2uqq ymm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
927 vcvtps2uqq ymm6
{k7
}, [edx+
508]{1to4
} # AVX512{DQ,VL} Disp8
928 vcvtps2uqq ymm6
{k7
}, [edx+
512]{1to4
} # AVX512{DQ,VL}
929 vcvtps2uqq ymm6
{k7
}, [edx-
512]{1to4
} # AVX512{DQ,VL} Disp8
930 vcvtps2uqq ymm6
{k7
}, [edx-
516]{1to4
} # AVX512{DQ,VL}
931 vcvtps2uqq ymm6
{k7
}, DWORD BCST
[edx+
508] # AVX512{DQ,VL} Disp8
932 vcvtqq2pd xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
933 vcvtqq2pd xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
934 vcvtqq2pd xmm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
935 vcvtqq2pd xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
936 vcvtqq2pd xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
937 vcvtqq2pd xmm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
938 vcvtqq2pd xmm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
939 vcvtqq2pd xmm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
940 vcvtqq2pd xmm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
941 vcvtqq2pd xmm6
{k7
}, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
942 vcvtqq2pd xmm6
{k7
}, [edx+
1024]{1to2
} # AVX512{DQ,VL}
943 vcvtqq2pd xmm6
{k7
}, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
944 vcvtqq2pd xmm6
{k7
}, [edx-
1032]{1to2
} # AVX512{DQ,VL}
945 vcvtqq2pd ymm6
{k7
}, ymm5
# AVX512{DQ,VL}
946 vcvtqq2pd ymm6
{k7
}{z
}, ymm5
# AVX512{DQ,VL}
947 vcvtqq2pd ymm6
{k7
}, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
948 vcvtqq2pd ymm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
949 vcvtqq2pd ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
950 vcvtqq2pd ymm6
{k7
}, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
951 vcvtqq2pd ymm6
{k7
}, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
952 vcvtqq2pd ymm6
{k7
}, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
953 vcvtqq2pd ymm6
{k7
}, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
954 vcvtqq2pd ymm6
{k7
}, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
955 vcvtqq2pd ymm6
{k7
}, [edx+
1024]{1to4
} # AVX512{DQ,VL}
956 vcvtqq2pd ymm6
{k7
}, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
957 vcvtqq2pd ymm6
{k7
}, [edx-
1032]{1to4
} # AVX512{DQ,VL}
958 vcvtqq2ps xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
959 vcvtqq2ps xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
960 vcvtqq2ps xmm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
961 vcvtqq2ps xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
962 vcvtqq2ps xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
963 vcvtqq2ps xmm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
964 vcvtqq2ps xmm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
965 vcvtqq2ps xmm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
966 vcvtqq2ps xmm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
967 vcvtqq2ps xmm6
{k7
}, QWORD BCST
[edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
968 vcvtqq2ps xmm6
{k7
}, QWORD BCST
[edx+
1024]{1to2
} # AVX512{DQ,VL}
969 vcvtqq2ps xmm6
{k7
}, QWORD BCST
[edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
970 vcvtqq2ps xmm6
{k7
}, QWORD BCST
[edx-
1032]{1to2
} # AVX512{DQ,VL}
971 vcvtqq2ps xmm6
{k7
}, ymm5
# AVX512{DQ,VL}
972 vcvtqq2ps xmm6
{k7
}{z
}, ymm5
# AVX512{DQ,VL}
973 vcvtqq2ps xmm6
{k7
}, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
974 vcvtqq2ps xmm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
975 vcvtqq2ps xmm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
976 vcvtqq2ps xmm6
{k7
}, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
977 vcvtqq2ps xmm6
{k7
}, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
978 vcvtqq2ps xmm6
{k7
}, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
979 vcvtqq2ps xmm6
{k7
}, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
980 vcvtqq2ps xmm6
{k7
}, QWORD BCST
[edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
981 vcvtqq2ps xmm6
{k7
}, QWORD BCST
[edx+
1024]{1to4
} # AVX512{DQ,VL}
982 vcvtqq2ps xmm6
{k7
}, QWORD BCST
[edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
983 vcvtqq2ps xmm6
{k7
}, QWORD BCST
[edx-
1032]{1to4
} # AVX512{DQ,VL}
984 vcvtuqq2pd xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
985 vcvtuqq2pd xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
986 vcvtuqq2pd xmm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
987 vcvtuqq2pd xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
988 vcvtuqq2pd xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
989 vcvtuqq2pd xmm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
990 vcvtuqq2pd xmm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
991 vcvtuqq2pd xmm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
992 vcvtuqq2pd xmm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
993 vcvtuqq2pd xmm6
{k7
}, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
994 vcvtuqq2pd xmm6
{k7
}, [edx+
1024]{1to2
} # AVX512{DQ,VL}
995 vcvtuqq2pd xmm6
{k7
}, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
996 vcvtuqq2pd xmm6
{k7
}, [edx-
1032]{1to2
} # AVX512{DQ,VL}
997 vcvtuqq2pd ymm6
{k7
}, ymm5
# AVX512{DQ,VL}
998 vcvtuqq2pd ymm6
{k7
}{z
}, ymm5
# AVX512{DQ,VL}
999 vcvtuqq2pd ymm6
{k7
}, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1000 vcvtuqq2pd ymm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1001 vcvtuqq2pd ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
1002 vcvtuqq2pd ymm6
{k7
}, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1003 vcvtuqq2pd ymm6
{k7
}, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1004 vcvtuqq2pd ymm6
{k7
}, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1005 vcvtuqq2pd ymm6
{k7
}, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1006 vcvtuqq2pd ymm6
{k7
}, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
1007 vcvtuqq2pd ymm6
{k7
}, [edx+
1024]{1to4
} # AVX512{DQ,VL}
1008 vcvtuqq2pd ymm6
{k7
}, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
1009 vcvtuqq2pd ymm6
{k7
}, [edx-
1032]{1to4
} # AVX512{DQ,VL}
1010 vcvtuqq2ps xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
1011 vcvtuqq2ps xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
1012 vcvtuqq2ps xmm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1013 vcvtuqq2ps xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1014 vcvtuqq2ps xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
1015 vcvtuqq2ps xmm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1016 vcvtuqq2ps xmm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1017 vcvtuqq2ps xmm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1018 vcvtuqq2ps xmm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1019 vcvtuqq2ps xmm6
{k7
}, QWORD BCST
[edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
1020 vcvtuqq2ps xmm6
{k7
}, QWORD BCST
[edx+
1024]{1to2
} # AVX512{DQ,VL}
1021 vcvtuqq2ps xmm6
{k7
}, QWORD BCST
[edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
1022 vcvtuqq2ps xmm6
{k7
}, QWORD BCST
[edx-
1032]{1to2
} # AVX512{DQ,VL}
1023 vcvtuqq2ps xmm6
{k7
}, ymm5
# AVX512{DQ,VL}
1024 vcvtuqq2ps xmm6
{k7
}{z
}, ymm5
# AVX512{DQ,VL}
1025 vcvtuqq2ps xmm6
{k7
}, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1026 vcvtuqq2ps xmm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1027 vcvtuqq2ps xmm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
1028 vcvtuqq2ps xmm6
{k7
}, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1029 vcvtuqq2ps xmm6
{k7
}, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1030 vcvtuqq2ps xmm6
{k7
}, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1031 vcvtuqq2ps xmm6
{k7
}, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1032 vcvtuqq2ps xmm6
{k7
}, QWORD BCST
[edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
1033 vcvtuqq2ps xmm6
{k7
}, QWORD BCST
[edx+
1024]{1to4
} # AVX512{DQ,VL}
1034 vcvtuqq2ps xmm6
{k7
}, QWORD BCST
[edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
1035 vcvtuqq2ps xmm6
{k7
}, QWORD BCST
[edx-
1032]{1to4
} # AVX512{DQ,VL}
1036 vextractf64x2 xmm6
{k7
}, ymm5
, 0xab # AVX512{DQ,VL}
1037 vextractf64x2 xmm6
{k7
}{z
}, ymm5
, 0xab # AVX512{DQ,VL}
1038 vextractf64x2 xmm6
{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1039 vextracti64x2 xmm6
{k7
}, ymm5
, 0xab # AVX512{DQ,VL}
1040 vextracti64x2 xmm6
{k7
}{z
}, ymm5
, 0xab # AVX512{DQ,VL}
1041 vextracti64x2 xmm6
{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1042 vfpclasspd k5
{k7
}, xmm6
, 0xab # AVX512{DQ,VL}
1043 vfpclasspd k5
{k7
}, xmm6
, 123 # AVX512{DQ,VL}
1044 vfpclasspd k5
{k7
}, XMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1045 vfpclasspd k5
{k7
}, XMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1046 vfpclasspd k5
{k7
}, [eax
]{1to2
}, 123 # AVX512{DQ,VL}
1047 vfpclasspd k5
{k7
}, XMMWORD PTR
[edx+
2032], 123 # AVX512{DQ,VL} Disp8
1048 vfpclasspd k5
{k7
}, XMMWORD PTR
[edx+
2048], 123 # AVX512{DQ,VL}
1049 vfpclasspd k5
{k7
}, XMMWORD PTR
[edx-
2048], 123 # AVX512{DQ,VL} Disp8
1050 vfpclasspd k5
{k7
}, XMMWORD PTR
[edx-
2064], 123 # AVX512{DQ,VL}
1051 vfpclasspd k5
{k7
}, QWORD BCST
[edx+
1016]{1to2
}, 123 # AVX512{DQ,VL} Disp8
1052 vfpclasspd k5
{k7
}, QWORD BCST
[edx+
1024]{1to2
}, 123 # AVX512{DQ,VL}
1053 vfpclasspd k5
{k7
}, QWORD BCST
[edx-
1024]{1to2
}, 123 # AVX512{DQ,VL} Disp8
1054 vfpclasspd k5
{k7
}, QWORD BCST
[edx-
1032]{1to2
}, 123 # AVX512{DQ,VL}
1055 vfpclasspd k5
{k7
}, ymm6
, 0xab # AVX512{DQ,VL}
1056 vfpclasspd k5
{k7
}, ymm6
, 123 # AVX512{DQ,VL}
1057 vfpclasspd k5
{k7
}, YMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1058 vfpclasspd k5
{k7
}, YMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1059 vfpclasspd k5
{k7
}, [eax
]{1to4
}, 123 # AVX512{DQ,VL}
1060 vfpclasspd k5
{k7
}, YMMWORD PTR
[edx+
4064], 123 # AVX512{DQ,VL} Disp8
1061 vfpclasspd k5
{k7
}, YMMWORD PTR
[edx+
4096], 123 # AVX512{DQ,VL}
1062 vfpclasspd k5
{k7
}, YMMWORD PTR
[edx-
4096], 123 # AVX512{DQ,VL} Disp8
1063 vfpclasspd k5
{k7
}, YMMWORD PTR
[edx-
4128], 123 # AVX512{DQ,VL}
1064 vfpclasspd k5
{k7
}, QWORD BCST
[edx+
1016]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1065 vfpclasspd k5
{k7
}, QWORD BCST
[edx+
1024]{1to4
}, 123 # AVX512{DQ,VL}
1066 vfpclasspd k5
{k7
}, QWORD BCST
[edx-
1024]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1067 vfpclasspd k5
{k7
}, QWORD BCST
[edx-
1032]{1to4
}, 123 # AVX512{DQ,VL}
1068 vfpclassps k5
{k7
}, xmm6
, 0xab # AVX512{DQ,VL}
1069 vfpclassps k5
{k7
}, xmm6
, 123 # AVX512{DQ,VL}
1070 vfpclassps k5
{k7
}, XMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1071 vfpclassps k5
{k7
}, XMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1072 vfpclassps k5
{k7
}, [eax
]{1to4
}, 123 # AVX512{DQ,VL}
1073 vfpclassps k5
{k7
}, XMMWORD PTR
[edx+
2032], 123 # AVX512{DQ,VL} Disp8
1074 vfpclassps k5
{k7
}, XMMWORD PTR
[edx+
2048], 123 # AVX512{DQ,VL}
1075 vfpclassps k5
{k7
}, XMMWORD PTR
[edx-
2048], 123 # AVX512{DQ,VL} Disp8
1076 vfpclassps k5
{k7
}, XMMWORD PTR
[edx-
2064], 123 # AVX512{DQ,VL}
1077 vfpclassps k5
{k7
}, DWORD BCST
[edx+
508]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1078 vfpclassps k5
{k7
}, DWORD BCST
[edx+
512]{1to4
}, 123 # AVX512{DQ,VL}
1079 vfpclassps k5
{k7
}, DWORD BCST
[edx-
512]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1080 vfpclassps k5
{k7
}, DWORD BCST
[edx-
516]{1to4
}, 123 # AVX512{DQ,VL}
1081 vfpclassps k5
{k7
}, ymm6
, 0xab # AVX512{DQ,VL}
1082 vfpclassps k5
{k7
}, ymm6
, 123 # AVX512{DQ,VL}
1083 vfpclassps k5
{k7
}, YMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1084 vfpclassps k5
{k7
}, YMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1085 vfpclassps k5
{k7
}, [eax
]{1to8
}, 123 # AVX512{DQ,VL}
1086 vfpclassps k5
{k7
}, YMMWORD PTR
[edx+
4064], 123 # AVX512{DQ,VL} Disp8
1087 vfpclassps k5
{k7
}, YMMWORD PTR
[edx+
4096], 123 # AVX512{DQ,VL}
1088 vfpclassps k5
{k7
}, YMMWORD PTR
[edx-
4096], 123 # AVX512{DQ,VL} Disp8
1089 vfpclassps k5
{k7
}, YMMWORD PTR
[edx-
4128], 123 # AVX512{DQ,VL}
1090 vfpclassps k5
{k7
}, DWORD BCST
[edx+
508]{1to8
}, 123 # AVX512{DQ,VL} Disp8
1091 vfpclassps k5
{k7
}, DWORD BCST
[edx+
512]{1to8
}, 123 # AVX512{DQ,VL}
1092 vfpclassps k5
{k7
}, DWORD BCST
[edx-
512]{1to8
}, 123 # AVX512{DQ,VL} Disp8
1093 vfpclassps k5
{k7
}, DWORD BCST
[edx-
516]{1to8
}, 123 # AVX512{DQ,VL}
1094 vinsertf64x2 ymm6
{k7
}, ymm5
, xmm4
, 0xab # AVX512{DQ,VL}
1095 vinsertf64x2 ymm6
{k7
}{z
}, ymm5
, xmm4
, 0xab # AVX512{DQ,VL}
1096 vinsertf64x2 ymm6
{k7
}, ymm5
, xmm4
, 123 # AVX512{DQ,VL}
1097 vinsertf64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1098 vinsertf64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1099 vinsertf64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[edx+
2032], 123 # AVX512{DQ,VL} Disp8
1100 vinsertf64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[edx+
2048], 123 # AVX512{DQ,VL}
1101 vinsertf64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[edx-
2048], 123 # AVX512{DQ,VL} Disp8
1102 vinsertf64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[edx-
2064], 123 # AVX512{DQ,VL}
1103 vinserti64x2 ymm6
{k7
}, ymm5
, xmm4
, 0xab # AVX512{DQ,VL}
1104 vinserti64x2 ymm6
{k7
}{z
}, ymm5
, xmm4
, 0xab # AVX512{DQ,VL}
1105 vinserti64x2 ymm6
{k7
}, ymm5
, xmm4
, 123 # AVX512{DQ,VL}
1106 vinserti64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1107 vinserti64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1108 vinserti64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[edx+
2032], 123 # AVX512{DQ,VL} Disp8
1109 vinserti64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[edx+
2048], 123 # AVX512{DQ,VL}
1110 vinserti64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[edx-
2048], 123 # AVX512{DQ,VL} Disp8
1111 vinserti64x2 ymm6
{k7
}, ymm5
, XMMWORD PTR
[edx-
2064], 123 # AVX512{DQ,VL}
1112 vbroadcasti32x2 xmm6
{k7
}, xmm7
# AVX512{DQ,VL}
1113 vbroadcasti32x2 xmm6
{k7
}{z
}, xmm7
# AVX512{DQ,VL}
1114 vbroadcasti32x2 xmm6
{k7
}, QWORD PTR
[ecx
] # AVX512{DQ,VL}
1115 vbroadcasti32x2 xmm6
{k7
}, QWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1116 vbroadcasti32x2 xmm6
{k7
}, QWORD PTR
[edx+
1016] # AVX512{DQ,VL} Disp8
1117 vbroadcasti32x2 xmm6
{k7
}, QWORD PTR
[edx+
1024] # AVX512{DQ,VL}
1118 vbroadcasti32x2 xmm6
{k7
}, QWORD PTR
[edx-
1024] # AVX512{DQ,VL} Disp8
1119 vbroadcasti32x2 xmm6
{k7
}, QWORD PTR
[edx-
1032] # AVX512{DQ,VL}
1120 vbroadcasti32x2 ymm6
{k7
}, xmm7
# AVX512{DQ,VL}
1121 vbroadcasti32x2 ymm6
{k7
}{z
}, xmm7
# AVX512{DQ,VL}
1122 vbroadcasti32x2 ymm6
{k7
}, QWORD PTR
[ecx
] # AVX512{DQ,VL}
1123 vbroadcasti32x2 ymm6
{k7
}, QWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1124 vbroadcasti32x2 ymm6
{k7
}, QWORD PTR
[edx+
1016] # AVX512{DQ,VL} Disp8
1125 vbroadcasti32x2 ymm6
{k7
}, QWORD PTR
[edx+
1024] # AVX512{DQ,VL}
1126 vbroadcasti32x2 ymm6
{k7
}, QWORD PTR
[edx-
1024] # AVX512{DQ,VL} Disp8
1127 vbroadcasti32x2 ymm6
{k7
}, QWORD PTR
[edx-
1032] # AVX512{DQ,VL}
1128 vpmullq xmm6
{k7
}, xmm5
, xmm4
# AVX512{DQ,VL}
1129 vpmullq xmm6
{k7
}{z
}, xmm5
, xmm4
# AVX512{DQ,VL}
1130 vpmullq xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1131 vpmullq xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1132 vpmullq xmm6
{k7
}, xmm5
, [eax
]{1to2
} # AVX512{DQ,VL}
1133 vpmullq xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1134 vpmullq xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1135 vpmullq xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1136 vpmullq xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1137 vpmullq xmm6
{k7
}, xmm5
, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
1138 vpmullq xmm6
{k7
}, xmm5
, [edx+
1024]{1to2
} # AVX512{DQ,VL}
1139 vpmullq xmm6
{k7
}, xmm5
, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
1140 vpmullq xmm6
{k7
}, xmm5
, [edx-
1032]{1to2
} # AVX512{DQ,VL}
1141 vpmullq ymm6
{k7
}, ymm5
, ymm4
# AVX512{DQ,VL}
1142 vpmullq ymm6
{k7
}{z
}, ymm5
, ymm4
# AVX512{DQ,VL}
1143 vpmullq ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1144 vpmullq ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1145 vpmullq ymm6
{k7
}, ymm5
, [eax
]{1to4
} # AVX512{DQ,VL}
1146 vpmullq ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1147 vpmullq ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1148 vpmullq ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1149 vpmullq ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1150 vpmullq ymm6
{k7
}, ymm5
, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
1151 vpmullq ymm6
{k7
}, ymm5
, [edx+
1024]{1to4
} # AVX512{DQ,VL}
1152 vpmullq ymm6
{k7
}, ymm5
, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
1153 vpmullq ymm6
{k7
}, ymm5
, [edx-
1032]{1to4
} # AVX512{DQ,VL}
1154 vrangepd xmm6
{k7
}, xmm5
, xmm4
, 0xab # AVX512{DQ,VL}
1155 vrangepd xmm6
{k7
}{z
}, xmm5
, xmm4
, 0xab # AVX512{DQ,VL}
1156 vrangepd xmm6
{k7
}, xmm5
, xmm4
, 123 # AVX512{DQ,VL}
1157 vrangepd xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1158 vrangepd xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1159 vrangepd xmm6
{k7
}, xmm5
, [eax
]{1to2
}, 123 # AVX512{DQ,VL}
1160 vrangepd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032], 123 # AVX512{DQ,VL} Disp8
1161 vrangepd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048], 123 # AVX512{DQ,VL}
1162 vrangepd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048], 123 # AVX512{DQ,VL} Disp8
1163 vrangepd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064], 123 # AVX512{DQ,VL}
1164 vrangepd xmm6
{k7
}, xmm5
, [edx+
1016]{1to2
}, 123 # AVX512{DQ,VL} Disp8
1165 vrangepd xmm6
{k7
}, xmm5
, [edx+
1024]{1to2
}, 123 # AVX512{DQ,VL}
1166 vrangepd xmm6
{k7
}, xmm5
, [edx-
1024]{1to2
}, 123 # AVX512{DQ,VL} Disp8
1167 vrangepd xmm6
{k7
}, xmm5
, [edx-
1032]{1to2
}, 123 # AVX512{DQ,VL}
1168 vrangepd ymm6
{k7
}, ymm5
, ymm4
, 0xab # AVX512{DQ,VL}
1169 vrangepd ymm6
{k7
}{z
}, ymm5
, ymm4
, 0xab # AVX512{DQ,VL}
1170 vrangepd ymm6
{k7
}, ymm5
, ymm4
, 123 # AVX512{DQ,VL}
1171 vrangepd ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1172 vrangepd ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1173 vrangepd ymm6
{k7
}, ymm5
, [eax
]{1to4
}, 123 # AVX512{DQ,VL}
1174 vrangepd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064], 123 # AVX512{DQ,VL} Disp8
1175 vrangepd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096], 123 # AVX512{DQ,VL}
1176 vrangepd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096], 123 # AVX512{DQ,VL} Disp8
1177 vrangepd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128], 123 # AVX512{DQ,VL}
1178 vrangepd ymm6
{k7
}, ymm5
, [edx+
1016]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1179 vrangepd ymm6
{k7
}, ymm5
, [edx+
1024]{1to4
}, 123 # AVX512{DQ,VL}
1180 vrangepd ymm6
{k7
}, ymm5
, [edx-
1024]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1181 vrangepd ymm6
{k7
}, ymm5
, [edx-
1032]{1to4
}, 123 # AVX512{DQ,VL}
1182 vrangeps xmm6
{k7
}, xmm5
, xmm4
, 0xab # AVX512{DQ,VL}
1183 vrangeps xmm6
{k7
}{z
}, xmm5
, xmm4
, 0xab # AVX512{DQ,VL}
1184 vrangeps xmm6
{k7
}, xmm5
, xmm4
, 123 # AVX512{DQ,VL}
1185 vrangeps xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1186 vrangeps xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1187 vrangeps xmm6
{k7
}, xmm5
, [eax
]{1to4
}, 123 # AVX512{DQ,VL}
1188 vrangeps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032], 123 # AVX512{DQ,VL} Disp8
1189 vrangeps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048], 123 # AVX512{DQ,VL}
1190 vrangeps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048], 123 # AVX512{DQ,VL} Disp8
1191 vrangeps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064], 123 # AVX512{DQ,VL}
1192 vrangeps xmm6
{k7
}, xmm5
, [edx+
508]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1193 vrangeps xmm6
{k7
}, xmm5
, [edx+
512]{1to4
}, 123 # AVX512{DQ,VL}
1194 vrangeps xmm6
{k7
}, xmm5
, [edx-
512]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1195 vrangeps xmm6
{k7
}, xmm5
, [edx-
516]{1to4
}, 123 # AVX512{DQ,VL}
1196 vrangeps ymm6
{k7
}, ymm5
, ymm4
, 0xab # AVX512{DQ,VL}
1197 vrangeps ymm6
{k7
}{z
}, ymm5
, ymm4
, 0xab # AVX512{DQ,VL}
1198 vrangeps ymm6
{k7
}, ymm5
, ymm4
, 123 # AVX512{DQ,VL}
1199 vrangeps ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1200 vrangeps ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1201 vrangeps ymm6
{k7
}, ymm5
, [eax
]{1to8
}, 123 # AVX512{DQ,VL}
1202 vrangeps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064], 123 # AVX512{DQ,VL} Disp8
1203 vrangeps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096], 123 # AVX512{DQ,VL}
1204 vrangeps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096], 123 # AVX512{DQ,VL} Disp8
1205 vrangeps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128], 123 # AVX512{DQ,VL}
1206 vrangeps ymm6
{k7
}, ymm5
, [edx+
508]{1to8
}, 123 # AVX512{DQ,VL} Disp8
1207 vrangeps ymm6
{k7
}, ymm5
, [edx+
512]{1to8
}, 123 # AVX512{DQ,VL}
1208 vrangeps ymm6
{k7
}, ymm5
, [edx-
512]{1to8
}, 123 # AVX512{DQ,VL} Disp8
1209 vrangeps ymm6
{k7
}, ymm5
, [edx-
516]{1to8
}, 123 # AVX512{DQ,VL}
1210 vandpd xmm6
{k7
}, xmm5
, xmm4
# AVX512{DQ,VL}
1211 vandpd xmm6
{k7
}{z
}, xmm5
, xmm4
# AVX512{DQ,VL}
1212 vandpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1213 vandpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1214 vandpd xmm6
{k7
}, xmm5
, [eax
]{1to2
} # AVX512{DQ,VL}
1215 vandpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1216 vandpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1217 vandpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1218 vandpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1219 vandpd xmm6
{k7
}, xmm5
, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
1220 vandpd xmm6
{k7
}, xmm5
, [edx+
1024]{1to2
} # AVX512{DQ,VL}
1221 vandpd xmm6
{k7
}, xmm5
, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
1222 vandpd xmm6
{k7
}, xmm5
, [edx-
1032]{1to2
} # AVX512{DQ,VL}
1223 vandpd ymm6
{k7
}, ymm5
, ymm4
# AVX512{DQ,VL}
1224 vandpd ymm6
{k7
}{z
}, ymm5
, ymm4
# AVX512{DQ,VL}
1225 vandpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1226 vandpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1227 vandpd ymm6
{k7
}, ymm5
, [eax
]{1to4
} # AVX512{DQ,VL}
1228 vandpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1229 vandpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1230 vandpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1231 vandpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1232 vandpd ymm6
{k7
}, ymm5
, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
1233 vandpd ymm6
{k7
}, ymm5
, [edx+
1024]{1to4
} # AVX512{DQ,VL}
1234 vandpd ymm6
{k7
}, ymm5
, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
1235 vandpd ymm6
{k7
}, ymm5
, [edx-
1032]{1to4
} # AVX512{DQ,VL}
1236 vandps xmm6
{k7
}, xmm5
, xmm4
# AVX512{DQ,VL}
1237 vandps xmm6
{k7
}{z
}, xmm5
, xmm4
# AVX512{DQ,VL}
1238 vandps xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1239 vandps xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1240 vandps xmm6
{k7
}, xmm5
, [eax
]{1to4
} # AVX512{DQ,VL}
1241 vandps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1242 vandps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1243 vandps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1244 vandps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1245 vandps xmm6
{k7
}, xmm5
, [edx+
508]{1to4
} # AVX512{DQ,VL} Disp8
1246 vandps xmm6
{k7
}, xmm5
, [edx+
512]{1to4
} # AVX512{DQ,VL}
1247 vandps xmm6
{k7
}, xmm5
, [edx-
512]{1to4
} # AVX512{DQ,VL} Disp8
1248 vandps xmm6
{k7
}, xmm5
, [edx-
516]{1to4
} # AVX512{DQ,VL}
1249 vandps ymm6
{k7
}, ymm5
, ymm4
# AVX512{DQ,VL}
1250 vandps ymm6
{k7
}{z
}, ymm5
, ymm4
# AVX512{DQ,VL}
1251 vandps ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1252 vandps ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1253 vandps ymm6
{k7
}, ymm5
, [eax
]{1to8
} # AVX512{DQ,VL}
1254 vandps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1255 vandps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1256 vandps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1257 vandps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1258 vandps ymm6
{k7
}, ymm5
, [edx+
508]{1to8
} # AVX512{DQ,VL} Disp8
1259 vandps ymm6
{k7
}, ymm5
, [edx+
512]{1to8
} # AVX512{DQ,VL}
1260 vandps ymm6
{k7
}, ymm5
, [edx-
512]{1to8
} # AVX512{DQ,VL} Disp8
1261 vandps ymm6
{k7
}, ymm5
, [edx-
516]{1to8
} # AVX512{DQ,VL}
1262 vandnpd xmm6
{k7
}, xmm5
, xmm4
# AVX512{DQ,VL}
1263 vandnpd xmm6
{k7
}{z
}, xmm5
, xmm4
# AVX512{DQ,VL}
1264 vandnpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1265 vandnpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1266 vandnpd xmm6
{k7
}, xmm5
, [eax
]{1to2
} # AVX512{DQ,VL}
1267 vandnpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1268 vandnpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1269 vandnpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1270 vandnpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1271 vandnpd xmm6
{k7
}, xmm5
, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
1272 vandnpd xmm6
{k7
}, xmm5
, [edx+
1024]{1to2
} # AVX512{DQ,VL}
1273 vandnpd xmm6
{k7
}, xmm5
, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
1274 vandnpd xmm6
{k7
}, xmm5
, [edx-
1032]{1to2
} # AVX512{DQ,VL}
1275 vandnpd ymm6
{k7
}, ymm5
, ymm4
# AVX512{DQ,VL}
1276 vandnpd ymm6
{k7
}{z
}, ymm5
, ymm4
# AVX512{DQ,VL}
1277 vandnpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1278 vandnpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1279 vandnpd ymm6
{k7
}, ymm5
, [eax
]{1to4
} # AVX512{DQ,VL}
1280 vandnpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1281 vandnpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1282 vandnpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1283 vandnpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1284 vandnpd ymm6
{k7
}, ymm5
, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
1285 vandnpd ymm6
{k7
}, ymm5
, [edx+
1024]{1to4
} # AVX512{DQ,VL}
1286 vandnpd ymm6
{k7
}, ymm5
, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
1287 vandnpd ymm6
{k7
}, ymm5
, [edx-
1032]{1to4
} # AVX512{DQ,VL}
1288 vandnps xmm6
{k7
}, xmm5
, xmm4
# AVX512{DQ,VL}
1289 vandnps xmm6
{k7
}{z
}, xmm5
, xmm4
# AVX512{DQ,VL}
1290 vandnps xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1291 vandnps xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1292 vandnps xmm6
{k7
}, xmm5
, [eax
]{1to4
} # AVX512{DQ,VL}
1293 vandnps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1294 vandnps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1295 vandnps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1296 vandnps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1297 vandnps xmm6
{k7
}, xmm5
, [edx+
508]{1to4
} # AVX512{DQ,VL} Disp8
1298 vandnps xmm6
{k7
}, xmm5
, [edx+
512]{1to4
} # AVX512{DQ,VL}
1299 vandnps xmm6
{k7
}, xmm5
, [edx-
512]{1to4
} # AVX512{DQ,VL} Disp8
1300 vandnps xmm6
{k7
}, xmm5
, [edx-
516]{1to4
} # AVX512{DQ,VL}
1301 vandnps ymm6
{k7
}, ymm5
, ymm4
# AVX512{DQ,VL}
1302 vandnps ymm6
{k7
}{z
}, ymm5
, ymm4
# AVX512{DQ,VL}
1303 vandnps ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1304 vandnps ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1305 vandnps ymm6
{k7
}, ymm5
, [eax
]{1to8
} # AVX512{DQ,VL}
1306 vandnps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1307 vandnps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1308 vandnps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1309 vandnps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1310 vandnps ymm6
{k7
}, ymm5
, [edx+
508]{1to8
} # AVX512{DQ,VL} Disp8
1311 vandnps ymm6
{k7
}, ymm5
, [edx+
512]{1to8
} # AVX512{DQ,VL}
1312 vandnps ymm6
{k7
}, ymm5
, [edx-
512]{1to8
} # AVX512{DQ,VL} Disp8
1313 vandnps ymm6
{k7
}, ymm5
, [edx-
516]{1to8
} # AVX512{DQ,VL}
1314 vorpd xmm6
{k7
}, xmm5
, xmm4
# AVX512{DQ,VL}
1315 vorpd xmm6
{k7
}{z
}, xmm5
, xmm4
# AVX512{DQ,VL}
1316 vorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1317 vorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1318 vorpd xmm6
{k7
}, xmm5
, [eax
]{1to2
} # AVX512{DQ,VL}
1319 vorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1320 vorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1321 vorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1322 vorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1323 vorpd xmm6
{k7
}, xmm5
, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
1324 vorpd xmm6
{k7
}, xmm5
, [edx+
1024]{1to2
} # AVX512{DQ,VL}
1325 vorpd xmm6
{k7
}, xmm5
, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
1326 vorpd xmm6
{k7
}, xmm5
, [edx-
1032]{1to2
} # AVX512{DQ,VL}
1327 vorpd ymm6
{k7
}, ymm5
, ymm4
# AVX512{DQ,VL}
1328 vorpd ymm6
{k7
}{z
}, ymm5
, ymm4
# AVX512{DQ,VL}
1329 vorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1330 vorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1331 vorpd ymm6
{k7
}, ymm5
, [eax
]{1to4
} # AVX512{DQ,VL}
1332 vorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1333 vorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1334 vorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1335 vorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1336 vorpd ymm6
{k7
}, ymm5
, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
1337 vorpd ymm6
{k7
}, ymm5
, [edx+
1024]{1to4
} # AVX512{DQ,VL}
1338 vorpd ymm6
{k7
}, ymm5
, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
1339 vorpd ymm6
{k7
}, ymm5
, [edx-
1032]{1to4
} # AVX512{DQ,VL}
1340 vorps xmm6
{k7
}, xmm5
, xmm4
# AVX512{DQ,VL}
1341 vorps xmm6
{k7
}{z
}, xmm5
, xmm4
# AVX512{DQ,VL}
1342 vorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1343 vorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1344 vorps xmm6
{k7
}, xmm5
, [eax
]{1to4
} # AVX512{DQ,VL}
1345 vorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1346 vorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1347 vorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1348 vorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1349 vorps xmm6
{k7
}, xmm5
, [edx+
508]{1to4
} # AVX512{DQ,VL} Disp8
1350 vorps xmm6
{k7
}, xmm5
, [edx+
512]{1to4
} # AVX512{DQ,VL}
1351 vorps xmm6
{k7
}, xmm5
, [edx-
512]{1to4
} # AVX512{DQ,VL} Disp8
1352 vorps xmm6
{k7
}, xmm5
, [edx-
516]{1to4
} # AVX512{DQ,VL}
1353 vorps ymm6
{k7
}, ymm5
, ymm4
# AVX512{DQ,VL}
1354 vorps ymm6
{k7
}{z
}, ymm5
, ymm4
# AVX512{DQ,VL}
1355 vorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1356 vorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1357 vorps ymm6
{k7
}, ymm5
, [eax
]{1to8
} # AVX512{DQ,VL}
1358 vorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1359 vorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1360 vorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1361 vorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1362 vorps ymm6
{k7
}, ymm5
, [edx+
508]{1to8
} # AVX512{DQ,VL} Disp8
1363 vorps ymm6
{k7
}, ymm5
, [edx+
512]{1to8
} # AVX512{DQ,VL}
1364 vorps ymm6
{k7
}, ymm5
, [edx-
512]{1to8
} # AVX512{DQ,VL} Disp8
1365 vorps ymm6
{k7
}, ymm5
, [edx-
516]{1to8
} # AVX512{DQ,VL}
1366 vxorpd xmm6
{k7
}, xmm5
, xmm4
# AVX512{DQ,VL}
1367 vxorpd xmm6
{k7
}{z
}, xmm5
, xmm4
# AVX512{DQ,VL}
1368 vxorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1369 vxorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1370 vxorpd xmm6
{k7
}, xmm5
, [eax
]{1to2
} # AVX512{DQ,VL}
1371 vxorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1372 vxorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1373 vxorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1374 vxorpd xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1375 vxorpd xmm6
{k7
}, xmm5
, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
1376 vxorpd xmm6
{k7
}, xmm5
, [edx+
1024]{1to2
} # AVX512{DQ,VL}
1377 vxorpd xmm6
{k7
}, xmm5
, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
1378 vxorpd xmm6
{k7
}, xmm5
, [edx-
1032]{1to2
} # AVX512{DQ,VL}
1379 vxorpd ymm6
{k7
}, ymm5
, ymm4
# AVX512{DQ,VL}
1380 vxorpd ymm6
{k7
}{z
}, ymm5
, ymm4
# AVX512{DQ,VL}
1381 vxorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1382 vxorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1383 vxorpd ymm6
{k7
}, ymm5
, [eax
]{1to4
} # AVX512{DQ,VL}
1384 vxorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1385 vxorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1386 vxorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1387 vxorpd ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1388 vxorpd ymm6
{k7
}, ymm5
, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
1389 vxorpd ymm6
{k7
}, ymm5
, [edx+
1024]{1to4
} # AVX512{DQ,VL}
1390 vxorpd ymm6
{k7
}, ymm5
, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
1391 vxorpd ymm6
{k7
}, ymm5
, [edx-
1032]{1to4
} # AVX512{DQ,VL}
1392 vxorps xmm6
{k7
}, xmm5
, xmm4
# AVX512{DQ,VL}
1393 vxorps xmm6
{k7
}{z
}, xmm5
, xmm4
# AVX512{DQ,VL}
1394 vxorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1395 vxorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1396 vxorps xmm6
{k7
}, xmm5
, [eax
]{1to4
} # AVX512{DQ,VL}
1397 vxorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1398 vxorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1399 vxorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1400 vxorps xmm6
{k7
}, xmm5
, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1401 vxorps xmm6
{k7
}, xmm5
, [edx+
508]{1to4
} # AVX512{DQ,VL} Disp8
1402 vxorps xmm6
{k7
}, xmm5
, [edx+
512]{1to4
} # AVX512{DQ,VL}
1403 vxorps xmm6
{k7
}, xmm5
, [edx-
512]{1to4
} # AVX512{DQ,VL} Disp8
1404 vxorps xmm6
{k7
}, xmm5
, [edx-
516]{1to4
} # AVX512{DQ,VL}
1405 vxorps ymm6
{k7
}, ymm5
, ymm4
# AVX512{DQ,VL}
1406 vxorps ymm6
{k7
}{z
}, ymm5
, ymm4
# AVX512{DQ,VL}
1407 vxorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1408 vxorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1409 vxorps ymm6
{k7
}, ymm5
, [eax
]{1to8
} # AVX512{DQ,VL}
1410 vxorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1411 vxorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1412 vxorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1413 vxorps ymm6
{k7
}, ymm5
, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1414 vxorps ymm6
{k7
}, ymm5
, [edx+
508]{1to8
} # AVX512{DQ,VL} Disp8
1415 vxorps ymm6
{k7
}, ymm5
, [edx+
512]{1to8
} # AVX512{DQ,VL}
1416 vxorps ymm6
{k7
}, ymm5
, [edx-
512]{1to8
} # AVX512{DQ,VL} Disp8
1417 vxorps ymm6
{k7
}, ymm5
, [edx-
516]{1to8
} # AVX512{DQ,VL}
1418 vreducepd xmm6
{k7
}, xmm5
, 0xab # AVX512{DQ,VL}
1419 vreducepd xmm6
{k7
}{z
}, xmm5
, 0xab # AVX512{DQ,VL}
1420 vreducepd xmm6
{k7
}, xmm5
, 123 # AVX512{DQ,VL}
1421 vreducepd xmm6
{k7
}, XMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1422 vreducepd xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1423 vreducepd xmm6
{k7
}, [eax
]{1to2
}, 123 # AVX512{DQ,VL}
1424 vreducepd xmm6
{k7
}, XMMWORD PTR
[edx+
2032], 123 # AVX512{DQ,VL} Disp8
1425 vreducepd xmm6
{k7
}, XMMWORD PTR
[edx+
2048], 123 # AVX512{DQ,VL}
1426 vreducepd xmm6
{k7
}, XMMWORD PTR
[edx-
2048], 123 # AVX512{DQ,VL} Disp8
1427 vreducepd xmm6
{k7
}, XMMWORD PTR
[edx-
2064], 123 # AVX512{DQ,VL}
1428 vreducepd xmm6
{k7
}, [edx+
1016]{1to2
}, 123 # AVX512{DQ,VL} Disp8
1429 vreducepd xmm6
{k7
}, [edx+
1024]{1to2
}, 123 # AVX512{DQ,VL}
1430 vreducepd xmm6
{k7
}, [edx-
1024]{1to2
}, 123 # AVX512{DQ,VL} Disp8
1431 vreducepd xmm6
{k7
}, [edx-
1032]{1to2
}, 123 # AVX512{DQ,VL}
1432 vreducepd ymm6
{k7
}, ymm5
, 0xab # AVX512{DQ,VL}
1433 vreducepd ymm6
{k7
}{z
}, ymm5
, 0xab # AVX512{DQ,VL}
1434 vreducepd ymm6
{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1435 vreducepd ymm6
{k7
}, YMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1436 vreducepd ymm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1437 vreducepd ymm6
{k7
}, [eax
]{1to4
}, 123 # AVX512{DQ,VL}
1438 vreducepd ymm6
{k7
}, YMMWORD PTR
[edx+
4064], 123 # AVX512{DQ,VL} Disp8
1439 vreducepd ymm6
{k7
}, YMMWORD PTR
[edx+
4096], 123 # AVX512{DQ,VL}
1440 vreducepd ymm6
{k7
}, YMMWORD PTR
[edx-
4096], 123 # AVX512{DQ,VL} Disp8
1441 vreducepd ymm6
{k7
}, YMMWORD PTR
[edx-
4128], 123 # AVX512{DQ,VL}
1442 vreducepd ymm6
{k7
}, [edx+
1016]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1443 vreducepd ymm6
{k7
}, [edx+
1024]{1to4
}, 123 # AVX512{DQ,VL}
1444 vreducepd ymm6
{k7
}, [edx-
1024]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1445 vreducepd ymm6
{k7
}, [edx-
1032]{1to4
}, 123 # AVX512{DQ,VL}
1446 vreduceps xmm6
{k7
}, xmm5
, 0xab # AVX512{DQ,VL}
1447 vreduceps xmm6
{k7
}{z
}, xmm5
, 0xab # AVX512{DQ,VL}
1448 vreduceps xmm6
{k7
}, xmm5
, 123 # AVX512{DQ,VL}
1449 vreduceps xmm6
{k7
}, XMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1450 vreduceps xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1451 vreduceps xmm6
{k7
}, [eax
]{1to4
}, 123 # AVX512{DQ,VL}
1452 vreduceps xmm6
{k7
}, XMMWORD PTR
[edx+
2032], 123 # AVX512{DQ,VL} Disp8
1453 vreduceps xmm6
{k7
}, XMMWORD PTR
[edx+
2048], 123 # AVX512{DQ,VL}
1454 vreduceps xmm6
{k7
}, XMMWORD PTR
[edx-
2048], 123 # AVX512{DQ,VL} Disp8
1455 vreduceps xmm6
{k7
}, XMMWORD PTR
[edx-
2064], 123 # AVX512{DQ,VL}
1456 vreduceps xmm6
{k7
}, [edx+
508]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1457 vreduceps xmm6
{k7
}, [edx+
512]{1to4
}, 123 # AVX512{DQ,VL}
1458 vreduceps xmm6
{k7
}, [edx-
512]{1to4
}, 123 # AVX512{DQ,VL} Disp8
1459 vreduceps xmm6
{k7
}, [edx-
516]{1to4
}, 123 # AVX512{DQ,VL}
1460 vreduceps ymm6
{k7
}, ymm5
, 0xab # AVX512{DQ,VL}
1461 vreduceps ymm6
{k7
}{z
}, ymm5
, 0xab # AVX512{DQ,VL}
1462 vreduceps ymm6
{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1463 vreduceps ymm6
{k7
}, YMMWORD PTR
[ecx
], 123 # AVX512{DQ,VL}
1464 vreduceps ymm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456], 123 # AVX512{DQ,VL}
1465 vreduceps ymm6
{k7
}, [eax
]{1to8
}, 123 # AVX512{DQ,VL}
1466 vreduceps ymm6
{k7
}, YMMWORD PTR
[edx+
4064], 123 # AVX512{DQ,VL} Disp8
1467 vreduceps ymm6
{k7
}, YMMWORD PTR
[edx+
4096], 123 # AVX512{DQ,VL}
1468 vreduceps ymm6
{k7
}, YMMWORD PTR
[edx-
4096], 123 # AVX512{DQ,VL} Disp8
1469 vreduceps ymm6
{k7
}, YMMWORD PTR
[edx-
4128], 123 # AVX512{DQ,VL}
1470 vreduceps ymm6
{k7
}, [edx+
508]{1to8
}, 123 # AVX512{DQ,VL} Disp8
1471 vreduceps ymm6
{k7
}, [edx+
512]{1to8
}, 123 # AVX512{DQ,VL}
1472 vreduceps ymm6
{k7
}, [edx-
512]{1to8
}, 123 # AVX512{DQ,VL} Disp8
1473 vreduceps ymm6
{k7
}, [edx-
516]{1to8
}, 123 # AVX512{DQ,VL}
1474 vextractf64x2 XMMWORD PTR
[ecx
]{k7
}, ymm5
, 0xab # AVX512{DQ,VL}
1475 vextractf64x2 XMMWORD PTR
[ecx
]{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1476 vextractf64x2 XMMWORD PTR
[esp+esi
*8-123456]{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1477 vextractf64x2 XMMWORD PTR
[edx+
2032]{k7
}, ymm5
, 123 # AVX512{DQ,VL} Disp8
1478 vextractf64x2 XMMWORD PTR
[edx+
2048]{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1479 vextractf64x2 XMMWORD PTR
[edx-
2048]{k7
}, ymm5
, 123 # AVX512{DQ,VL} Disp8
1480 vextractf64x2 XMMWORD PTR
[edx-
2064]{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1481 vextracti64x2 XMMWORD PTR
[ecx
]{k7
}, ymm5
, 0xab # AVX512{DQ,VL}
1482 vextracti64x2 XMMWORD PTR
[ecx
]{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1483 vextracti64x2 XMMWORD PTR
[esp+esi
*8-123456]{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1484 vextracti64x2 XMMWORD PTR
[edx+
2032]{k7
}, ymm5
, 123 # AVX512{DQ,VL} Disp8
1485 vextracti64x2 XMMWORD PTR
[edx+
2048]{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1486 vextracti64x2 XMMWORD PTR
[edx-
2048]{k7
}, ymm5
, 123 # AVX512{DQ,VL} Disp8
1487 vextracti64x2 XMMWORD PTR
[edx-
2064]{k7
}, ymm5
, 123 # AVX512{DQ,VL}
1488 vcvttpd2qq xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
1489 vcvttpd2qq xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
1490 vcvttpd2qq xmm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1491 vcvttpd2qq xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1492 vcvttpd2qq xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
1493 vcvttpd2qq xmm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1494 vcvttpd2qq xmm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1495 vcvttpd2qq xmm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1496 vcvttpd2qq xmm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1497 vcvttpd2qq xmm6
{k7
}, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
1498 vcvttpd2qq xmm6
{k7
}, [edx+
1024]{1to2
} # AVX512{DQ,VL}
1499 vcvttpd2qq xmm6
{k7
}, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
1500 vcvttpd2qq xmm6
{k7
}, [edx-
1032]{1to2
} # AVX512{DQ,VL}
1501 vcvttpd2qq ymm6
{k7
}, ymm5
# AVX512{DQ,VL}
1502 vcvttpd2qq ymm6
{k7
}{z
}, ymm5
# AVX512{DQ,VL}
1503 vcvttpd2qq ymm6
{k7
}, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1504 vcvttpd2qq ymm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1505 vcvttpd2qq ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
1506 vcvttpd2qq ymm6
{k7
}, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1507 vcvttpd2qq ymm6
{k7
}, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1508 vcvttpd2qq ymm6
{k7
}, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1509 vcvttpd2qq ymm6
{k7
}, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1510 vcvttpd2qq ymm6
{k7
}, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
1511 vcvttpd2qq ymm6
{k7
}, [edx+
1024]{1to4
} # AVX512{DQ,VL}
1512 vcvttpd2qq ymm6
{k7
}, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
1513 vcvttpd2qq ymm6
{k7
}, [edx-
1032]{1to4
} # AVX512{DQ,VL}
1514 vcvttpd2uqq xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
1515 vcvttpd2uqq xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
1516 vcvttpd2uqq xmm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1517 vcvttpd2uqq xmm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1518 vcvttpd2uqq xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
1519 vcvttpd2uqq xmm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1520 vcvttpd2uqq xmm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1521 vcvttpd2uqq xmm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1522 vcvttpd2uqq xmm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1523 vcvttpd2uqq xmm6
{k7
}, [edx+
1016]{1to2
} # AVX512{DQ,VL} Disp8
1524 vcvttpd2uqq xmm6
{k7
}, [edx+
1024]{1to2
} # AVX512{DQ,VL}
1525 vcvttpd2uqq xmm6
{k7
}, [edx-
1024]{1to2
} # AVX512{DQ,VL} Disp8
1526 vcvttpd2uqq xmm6
{k7
}, [edx-
1032]{1to2
} # AVX512{DQ,VL}
1527 vcvttpd2uqq ymm6
{k7
}, ymm5
# AVX512{DQ,VL}
1528 vcvttpd2uqq ymm6
{k7
}{z
}, ymm5
# AVX512{DQ,VL}
1529 vcvttpd2uqq ymm6
{k7
}, YMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1530 vcvttpd2uqq ymm6
{k7
}, YMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1531 vcvttpd2uqq ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
1532 vcvttpd2uqq ymm6
{k7
}, YMMWORD PTR
[edx+
4064] # AVX512{DQ,VL} Disp8
1533 vcvttpd2uqq ymm6
{k7
}, YMMWORD PTR
[edx+
4096] # AVX512{DQ,VL}
1534 vcvttpd2uqq ymm6
{k7
}, YMMWORD PTR
[edx-
4096] # AVX512{DQ,VL} Disp8
1535 vcvttpd2uqq ymm6
{k7
}, YMMWORD PTR
[edx-
4128] # AVX512{DQ,VL}
1536 vcvttpd2uqq ymm6
{k7
}, [edx+
1016]{1to4
} # AVX512{DQ,VL} Disp8
1537 vcvttpd2uqq ymm6
{k7
}, [edx+
1024]{1to4
} # AVX512{DQ,VL}
1538 vcvttpd2uqq ymm6
{k7
}, [edx-
1024]{1to4
} # AVX512{DQ,VL} Disp8
1539 vcvttpd2uqq ymm6
{k7
}, [edx-
1032]{1to4
} # AVX512{DQ,VL}
1540 vcvttps2qq xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
1541 vcvttps2qq xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
1542 vcvttps2qq xmm6
{k7
}, QWORD PTR
[ecx
] # AVX512{DQ,VL}
1543 vcvttps2qq xmm6
{k7
}, QWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1544 vcvttps2qq xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
1545 vcvttps2qq xmm6
{k7
}, QWORD PTR
[edx+
1016] # AVX512{DQ,VL} Disp8
1546 vcvttps2qq xmm6
{k7
}, QWORD PTR
[edx+
1024] # AVX512{DQ,VL}
1547 vcvttps2qq xmm6
{k7
}, QWORD PTR
[edx-
1024] # AVX512{DQ,VL} Disp8
1548 vcvttps2qq xmm6
{k7
}, QWORD PTR
[edx-
1032] # AVX512{DQ,VL}
1549 vcvttps2qq xmm6
{k7
}, [edx+
508]{1to2
} # AVX512{DQ,VL} Disp8
1550 vcvttps2qq xmm6
{k7
}, [edx+
512]{1to2
} # AVX512{DQ,VL}
1551 vcvttps2qq xmm6
{k7
}, [edx-
512]{1to2
} # AVX512{DQ,VL} Disp8
1552 vcvttps2qq xmm6
{k7
}, [edx-
516]{1to2
} # AVX512{DQ,VL}
1553 vcvttps2qq xmm6
{k7
}, DWORD BCST
[edx+
508] # AVX512{DQ,VL} Disp8
1554 vcvttps2qq ymm6
{k7
}, xmm5
# AVX512{DQ,VL}
1555 vcvttps2qq ymm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
1556 vcvttps2qq ymm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1557 vcvttps2qq ymm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1558 vcvttps2qq ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
1559 vcvttps2qq ymm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1560 vcvttps2qq ymm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1561 vcvttps2qq ymm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1562 vcvttps2qq ymm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1563 vcvttps2qq ymm6
{k7
}, [edx+
508]{1to4
} # AVX512{DQ,VL} Disp8
1564 vcvttps2qq ymm6
{k7
}, [edx+
512]{1to4
} # AVX512{DQ,VL}
1565 vcvttps2qq ymm6
{k7
}, [edx-
512]{1to4
} # AVX512{DQ,VL} Disp8
1566 vcvttps2qq ymm6
{k7
}, [edx-
516]{1to4
} # AVX512{DQ,VL}
1567 vcvttps2qq ymm6
{k7
}, DWORD BCST
[edx+
508] # AVX512{DQ,VL} Disp8
1568 vcvttps2uqq xmm6
{k7
}, xmm5
# AVX512{DQ,VL}
1569 vcvttps2uqq xmm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
1570 vcvttps2uqq xmm6
{k7
}, QWORD PTR
[ecx
] # AVX512{DQ,VL}
1571 vcvttps2uqq xmm6
{k7
}, QWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1572 vcvttps2uqq xmm6
{k7
}, [eax
]{1to2
} # AVX512{DQ,VL}
1573 vcvttps2uqq xmm6
{k7
}, QWORD PTR
[edx+
1016] # AVX512{DQ,VL} Disp8
1574 vcvttps2uqq xmm6
{k7
}, QWORD PTR
[edx+
1024] # AVX512{DQ,VL}
1575 vcvttps2uqq xmm6
{k7
}, QWORD PTR
[edx-
1024] # AVX512{DQ,VL} Disp8
1576 vcvttps2uqq xmm6
{k7
}, QWORD PTR
[edx-
1032] # AVX512{DQ,VL}
1577 vcvttps2uqq xmm6
{k7
}, [edx+
508]{1to2
} # AVX512{DQ,VL} Disp8
1578 vcvttps2uqq xmm6
{k7
}, [edx+
512]{1to2
} # AVX512{DQ,VL}
1579 vcvttps2uqq xmm6
{k7
}, [edx-
512]{1to2
} # AVX512{DQ,VL} Disp8
1580 vcvttps2uqq xmm6
{k7
}, [edx-
516]{1to2
} # AVX512{DQ,VL}
1581 vcvttps2uqq xmm6
{k7
}, DWORD BCST
[edx+
508] # AVX512{DQ,VL} Disp8
1582 vcvttps2uqq ymm6
{k7
}, xmm5
# AVX512{DQ,VL}
1583 vcvttps2uqq ymm6
{k7
}{z
}, xmm5
# AVX512{DQ,VL}
1584 vcvttps2uqq ymm6
{k7
}, XMMWORD PTR
[ecx
] # AVX512{DQ,VL}
1585 vcvttps2uqq ymm6
{k7
}, XMMWORD PTR
[esp+esi
*8-123456] # AVX512{DQ,VL}
1586 vcvttps2uqq ymm6
{k7
}, [eax
]{1to4
} # AVX512{DQ,VL}
1587 vcvttps2uqq ymm6
{k7
}, XMMWORD PTR
[edx+
2032] # AVX512{DQ,VL} Disp8
1588 vcvttps2uqq ymm6
{k7
}, XMMWORD PTR
[edx+
2048] # AVX512{DQ,VL}
1589 vcvttps2uqq ymm6
{k7
}, XMMWORD PTR
[edx-
2048] # AVX512{DQ,VL} Disp8
1590 vcvttps2uqq ymm6
{k7
}, XMMWORD PTR
[edx-
2064] # AVX512{DQ,VL}
1591 vcvttps2uqq ymm6
{k7
}, [edx+
508]{1to4
} # AVX512{DQ,VL} Disp8
1592 vcvttps2uqq ymm6
{k7
}, [edx+
512]{1to4
} # AVX512{DQ,VL}
1593 vcvttps2uqq ymm6
{k7
}, [edx-
512]{1to4
} # AVX512{DQ,VL} Disp8
1594 vcvttps2uqq ymm6
{k7
}, [edx-
516]{1to4
} # AVX512{DQ,VL}
1595 vcvttps2uqq ymm6
{k7
}, DWORD BCST
[edx+
508] # AVX512{DQ,VL} Disp8
1596 vpmovd2m k5
, xmm6
# AVX512{DQ,VL}
1597 vpmovd2m k5
, ymm6
# AVX512{DQ,VL}
1598 vpmovq2m k5
, xmm6
# AVX512{DQ,VL}
1599 vpmovq2m k5
, ymm6
# AVX512{DQ,VL}
1600 vpmovm2d xmm6
, k5
# AVX512{DQ,VL}
1601 vpmovm2d ymm6
, k5
# AVX512{DQ,VL}
1602 vpmovm2q xmm6
, k5
# AVX512{DQ,VL}
1603 vpmovm2q ymm6
, k5
# AVX512{DQ,VL}