| blob | aa5a464fa61cd3a14f19165ebd2e439531c456f1 |
1 ; xstormy16 CPU core description. -*- Scheme -*-
2 ; Copyright 2011 Free Software Foundation, Inc.
3 ;
4 ; Contributed by Red Hat Inc;
5 ;
6 ; This file is part of the GNU Binutils.
7 ;
8 ; This program is free software; you can redistribute it and/or modify
9 ; it under the terms of the GNU General Public License as published by
10 ; the Free Software Foundation; either version 3 of the License, or
11 ; (at your option) any later version.
12 ;
13 ; This program is distributed in the hope that it will be useful,
14 ; but WITHOUT ANY WARRANTY; without even the implied warranty of
15 ; MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 ; GNU General Public License for more details.
17 ;
18 ; You should have received a copy of the GNU General Public License
19 ; along with this program; if not, write to the Free Software
20 ; Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
21 ; MA 02110-1301, USA.
23 (define-rtl-version 0 8)
25 (include "simplify.inc")
27 (define-arch
28 (name xstormy16)
29 (comment "Xstormy16 architecture")
30 (insn-lsb0? #f)
31 (machs xstormy16)
32 (isas xstormy16)
33 )
35 (define-isa
36 (name xstormy16)
37 (comment "Xstormy16 instruction set")
38 (default-insn-word-bitsize 32)
39 (default-insn-bitsize 32)
40 ; FIXME base-insn-bitsize should be 16 too, but at present CGEN has
41 ; no support for instruction sets with opcode bits past
42 ; base-insn-bitsize, so we must set it to at least 20.
43 (base-insn-bitsize 32)
44 )
46 (define-cpu
47 (name xstormy16)
48 (comment "Xstormy16 CPU core")
49 (endian little)
50 (insn-endian little)
51 (insn-chunk-bitsize 16)
52 (word-bitsize 32)
53 )
55 (define-mach
56 (name xstormy16)
57 (comment "Xstormy16 CPU core")
58 (cpu xstormy16)
59 (isas xstormy16)
60 )
62 (define-model
63 (name xstormy16)
64 (comment "Xstormy16 CPU core")
65 (unit u-exec "Execution Unit" ()
66 1 1 ; issue done
67 () () () ())
68 )
70 ; IDOC attribute for instruction documentation.
72 (define-attr
73 (for insn)
74 (type enum)
75 (name IDOC)
76 (comment "insn kind for documentation")
77 (attrs META)
78 (values
79 (MEM - () "Memory")
80 (ALU - () "ALU")
81 (FPU - () "FPU")
82 (BR - () "Branch")
83 (PRIV - () "Priviledged")
84 (MISC - () "Miscellaneous")
85 )
86 )
87 \f
88 ; Hardware elements.
90 (define-hardware
91 (name h-pc)
92 (comment "program counter")
93 (attrs PC)
94 (type pc)
95 (set (newval) (c-call "h_pc_set_handler" newval))
96 )
98 (define-keyword
99 (name gr-names)
100 (enum-prefix H-GR-)
101 (values (r0 0) (r1 1) (r2 2) (r3 3)
102 (r4 4) (r5 5) (r6 6) (r7 7)
103 (r8 8) (r9 9) (r10 10) (r11 11)
104 (r12 12) (r13 13) (r14 14) (r15 15)
105 (psw 14) (sp 15)))
107 (define-keyword
108 (name gr-Rb-names)
109 (enum-prefix H-RBJ-)
110 (values (r8 0) (r9 1) (r10 2) (r11 3)
111 (r12 4) (r13 5) (r14 6) (r15 7)
112 (psw 6) (sp 7)))
114 (define-hardware
115 (name h-gr)
116 (comment "registers")
117 (type register WI (16))
118 (indices extern-keyword gr-names)
119 (get (index) (and #xFFFF (raw-reg h-gr index)))
120 (set (index newval) (c-call "h_gr_set_handler" index newval))
121 )
123 (define-hardware
124 (name h-Rb)
125 (comment "Rb registers")
126 (attrs VIRTUAL)
127 (type register SI(8))
128 (indices extern-keyword gr-Rb-names)
129 (get (index) (reg h-gr (add index 8)))
130 (set (index newval) (set (reg h-gr (add index 8)) newval))
131 )
133 (define-hardware
134 (name h-Rbj)
135 (comment "Rbj registers")
136 (attrs VIRTUAL)
137 (type register SI(2))
138 (indices extern-keyword gr-Rb-names)
139 (get (index) (reg h-gr (add index 8)))
140 (set (index newval) (set (reg h-gr (add index 8)) newval))
141 )
143 (define-hardware
144 (name h-Rpsw)
145 (comment "Register number field of the PSW")
146 (attrs VIRTUAL)
147 (type register WI)
148 (get () (and #xF (srl psw 12)))
149 (set (newval) (set psw (or (and psw #xFFF)
150 (sll HI newval 12)))))
152 (define-pmacro (define-psw-field fnam hnam index)
153 (define-hardware
154 (name hnam)
155 (attrs VIRTUAL)
156 (type register SI)
157 (get () (and 1 (srl psw index)))
158 (set (newval) (set psw (or (and psw (inv (sll HI 1 index)))
159 (sll HI newval index)))))
160 ;(dnop fnam "" (SEM-ONLY) hnam f-nil)
161 )
162 (define-psw-field psw-z8 h-z8 0)
163 (dnop psw-z8 "" (SEM-ONLY) h-z8 f-nil)
164 (define-psw-field psw-z16 h-z16 1)
165 (dnop psw-z16 "" (SEM-ONLY) h-z16 f-nil)
166 (define-psw-field psw-cy h-cy 2)
167 (dnop psw-cy "" (SEM-ONLY) h-cy f-nil)
168 (define-psw-field psw-hc h-hc 3)
169 (dnop psw-hc "" (SEM-ONLY) h-hc f-nil)
170 (define-psw-field psw-ov h-ov 4)
171 (dnop psw-ov "" (SEM-ONLY) h-ov f-nil)
172 (define-psw-field psw-pt h-pt 5)
173 (dnop psw-pt "" (SEM-ONLY) h-pt f-nil)
174 (define-psw-field psw-s h-s 6)
175 (dnop psw-s "" (SEM-ONLY) h-s f-nil)
177 (define-hardware
178 (name h-branchcond)
179 (comment "Condition of a branch instruction")
180 (type immediate (UINT 4))
181 (values keyword ""
182 (("ge" 0) ("nc" 1) ("lt" 2) ("c" 3)
183 ("gt" 4) ("hi" 5) ("le" 6) ("ls" 7)
184 ("pl" 8) ("nv" 9) ("mi" 10) ("v" 11)
185 ("nz.b" 12) ("nz" 13) ("z.b" 14) ("z" 15)))
186 )
188 (define-hardware
189 (name h-wordsize)
190 (comment "Data size")
191 (type immediate (UINT 1))
192 (values keyword "" ((".b" 0) (".w" 1) ("" 1)))
193 )
195 \f
196 ; Instruction fields, and the corresponding operands.
197 ; Register fields
199 (dnf f-Rd "general register destination" () 12 4)
200 (dnop Rd "general register destination" () h-gr f-Rd)
202 (dnf f-Rdm "general register destination" () 13 3)
203 (dnop Rdm "general register destination" () h-gr f-Rdm)
205 (dnf f-Rm "general register for memory" () 4 3)
206 (dnop Rm "general register for memory" () h-gr f-Rm)
208 (dnf f-Rs "general register source" () 8 4)
209 (dnop Rs "general register source" () h-gr f-Rs)
211 (dnf f-Rb "base register" () 17 3)
212 (dnop Rb "base register" () h-Rb f-Rb)
214 (dnf f-Rbj "base register for jump" () 11 1)
215 (dnop Rbj "base register for jump" () h-Rbj f-Rbj)
217 ; Main opcodes in 4 bit chunks
219 (dnf f-op1 "opcode" () 0 4)
220 (define-normal-insn-enum insn-op1 "insn op enums" () OP1_ f-op1
221 ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" ))
223 (dnf f-op2 "opcode" () 4 4)
224 (define-normal-insn-enum insn-op2 "insn op enums" () OP2_ f-op2
225 ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" ))
226 (dnop bcond2 "branch condition opcode" () h-branchcond f-op2)
228 (dnf f-op2a "opcode" () 4 3)
229 (define-normal-insn-enum insn-op2a "insn op enums" () OP2A_ f-op2a
230 ( "0" "2" "4" "6" "8" "A" "C" "E" ))
232 (dnf f-op2m "opcode" () 7 1)
233 (define-normal-insn-enum insn-op2m "insn op enums" () OP2M_ f-op2m
234 ( "0" "1" ))
235 (dnop ws2 "word size opcode" () h-wordsize f-op2m)
237 (dnf f-op3 "opcode" () 8 4)
238 (define-normal-insn-enum insn-op3 "insn op enums" () OP3_ f-op3
239 ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" ))
241 (dnf f-op3a "opcode" () 8 2)
242 (define-normal-insn-enum insn-op3a "insn op enums" () OP3A_ f-op3a
243 ( "0" "1" "2" "3" ))
245 (dnf f-op3b "opcode" () 8 3)
246 (define-normal-insn-enum insn-op3b "insn op enums" () OP3B_ f-op3b
247 ( "0" "2" "4" "6" "8" "A" "C" "E" ))
249 (dnf f-op4 "opcode" () 12 4)
250 (define-normal-insn-enum insn-op4 "insn op enums" () OP4_ f-op4
251 ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" ))
253 (dnf f-op4m "opcode" () 12 1)
254 (define-normal-insn-enum insn-op4m "insn op enums" () OP4M_ f-op4m
255 ( "0" "1" ))
257 (dnf f-op4b "opcode" () 15 1)
258 (define-normal-insn-enum insn-op4b "insn op enums" () OP4B_ f-op4b
259 ( "0" "1" ))
261 (dnf f-op5 "opcode" () 16 4)
262 (define-normal-insn-enum insn-op5 "insn op enums" () OP5_ f-op5
263 ( "0" "1" "2" "3" "4" "5" "6" "7" "8" "9" "A" "B" "C" "D" "E" "F" ))
264 (dnop bcond5 "branch condition opcode" () h-branchcond f-op5)
266 (dnf f-op5a "opcode" () 16 1)
267 (define-normal-insn-enum insn-op5a "insn op enums" () OP5A_ f-op5a
268 ( "0" "1" ))
270 ; The whole first word
271 (dnf f-op "opcode" () 0 16)
273 ; Immediate fields
275 (dnf f-imm2 "2 bit unsigned" () 10 2)
276 (dnop imm2 "2 bit unsigned immediate" () h-uint f-imm2)
278 (dnf f-imm3 "3 bit unsigned" () 4 3)
279 (dnop imm3 "3 bit unsigned immediate" () h-uint f-imm3)
280 (dnf f-imm3b "3 bit unsigned for bit tests" () 17 3)
281 (dnop imm3b "3 bit unsigned immediate for bit tests" () h-uint f-imm3b)
283 (dnf f-imm4 "4 bit unsigned" () 8 4)
284 (define-operand
285 (name imm4)
286 (comment "4 bit unsigned immediate")
287 (attrs)
288 (type h-uint)
289 (index f-imm4)
290 (handlers (parse "small_immediate"))
291 )
293 (dnf f-imm8 "8 bit unsigned" () 8 8)
294 (dnop imm8 "8 bit unsigned immediate" () h-uint f-imm8)
295 (define-operand
296 (name imm8small)
297 (comment "8 bit unsigned immediate")
298 (attrs)
299 (type h-uint)
300 (index f-imm8)
301 (handlers (parse "small_immediate"))
302 )
304 (define-ifield
305 (name f-imm12)
306 (comment "12 bit signed")
307 (attrs)
308 (start 20)
309 (length 12)
310 (mode INT)
311 )
312 (dnop imm12 "12 bit signed immediate" () h-sint f-imm12)
314 (dnf f-imm16 "16 bit" (SIGN-OPT) 16 16)
315 (define-operand
316 (name imm16)
317 (comment "16 bit immediate")
318 (attrs)
319 (type h-uint)
320 (index f-imm16)
321 (handlers (parse "immediate16"))
322 )
324 (dnf f-lmem8 "8 bit unsigned low memory" (ABS-ADDR) 8 8)
325 (define-operand
326 (name lmem8)
327 (comment "8 bit unsigned immediate low memory")
328 (attrs)
329 (type h-uint)
330 (index f-lmem8)
331 (handlers (parse "mem8"))
332 )
333 (define-ifield
334 (name f-hmem8)
335 (comment "8 bit unsigned high memory")
336 (attrs ABS-ADDR)
337 (start 8)
338 (length 8)
339 (mode UINT)
340 (encode (value pc) (sub HI value #x7F00))
341 (decode (value pc) (add HI value #x7F00))
342 )
343 (define-operand
344 (name hmem8)
345 (comment "8 bit unsigned immediate high memory")
346 (attrs)
347 (type h-uint)
348 (index f-hmem8)
349 (handlers (parse "mem8"))
350 )
352 (define-ifield
353 (name f-rel8-2)
354 (comment "8 bit relative address for 2-byte instruction")
355 (attrs PCREL-ADDR)
356 (start 8)
357 (length 8)
358 (mode INT)
359 (encode (value pc) (sub SI value (add SI pc 2)))
360 (decode (value pc) (add SI value (add SI pc 2)))
361 )
362 (dnop rel8-2 "8 bit relative address" () h-uint f-rel8-2)
364 (define-ifield
365 (name f-rel8-4)
366 (comment "8 bit relative address for 4-byte instruction")
367 (attrs PCREL-ADDR)
368 (start 8)
369 (length 8)
370 (mode INT)
371 (encode (value pc) (sub SI value (add SI pc 4)))
372 (decode (value pc) (add SI value (add SI pc 4)))
373 )
374 (dnop rel8-4 "8 bit relative address" () h-uint f-rel8-4)
376 (define-ifield
377 (name f-rel12)
378 (comment "12 bit relative address")
379 (attrs PCREL-ADDR)
380 (start 20)
381 (length 12)
382 (mode INT)
383 (encode (value pc) (sub SI value (add SI pc 4)))
384 (decode (value pc) (add SI value (add SI pc 4)))
385 )
386 (dnop rel12 "12 bit relative address" () h-uint f-rel12)
388 (define-ifield
389 (name f-rel12a)
390 (comment "12 bit relative address")
391 (attrs PCREL-ADDR)
392 (start 4)
393 (length 11)
394 (mode INT)
395 (encode (value pc) (sra SI (sub SI value (add SI pc 2)) 1))
396 (decode (value pc) (add SI (mul value 2) (add SI pc 2)))
397 )
398 (dnop rel12a "12 bit relative address" () h-uint f-rel12a)
400 (dnf f-abs24-1 "abs24 low part" () 8 8)
401 (dnf f-abs24-2 "abs24 high part" () 16 16)
402 (define-multi-ifield
403 (name f-abs24)
404 (comment "Absolute address for jmpf instruction")
405 (attrs ABS-ADDR)
406 (mode UINT)
407 (subfields f-abs24-1 f-abs24-2)
408 (insert (sequence ()
409 (set (ifield f-abs24-1) (and (ifield f-abs24) #xFF))
410 (set (ifield f-abs24-2) (srl (ifield f-abs24) 8))))
411 (extract (set (ifield f-abs24) (or (sll (ifield f-abs24-2) 8) f-abs24-1)))
412 )
413 (dnop abs24 "24 bit absolute address" () h-uint f-abs24)
415 ; Names for registers
416 (dnop psw "program status word" (SEM-ONLY) h-gr 14)
417 (dnop Rpsw "N0-N3 of the program status word" (SEM-ONLY) h-Rpsw f-nil)
418 (dnop sp "stack pointer" (SEM-ONLY) h-gr 15)
419 (dnop R0 "R0" (SEM-ONLY) h-gr 0)
420 (dnop R1 "R1" (SEM-ONLY) h-gr 1)
421 (dnop R2 "R2" (SEM-ONLY) h-gr 2)
422 (dnop R8 "R8" (SEM-ONLY) h-gr 8)
423 \f
424 ; Useful macros.
426 ; THe Z8, Z16, PT, and S flags of the PSW.
427 (define-pmacro (basic-psw value ws)
428 (or (or (zflag (and value #xFF))
429 (sll HI (zflag HI value) 1))
430 (or (sll HI (c-call BI "parity" value) 5)
431 (sll HI (nflag QI (srl value (mul ws 8))) 6))))
434 ; Update the PSW for destination register Rd, set Rd to value.
435 (define-pmacro (set-psw Rd index value ws)
436 (sequence ((HI nvalue))
437 (set nvalue value)
438 (set (reg HI h-gr index) nvalue)
439 (set psw (or (and psw #x0F9C)
440 (or (sll index 12)
441 (basic-psw nvalue ws))))))
443 ; Update the PSW for destination register Rd.
444 (define-pmacro (set-psw-nowrite index value ws)
445 (sequence ((HI nvalue))
446 (set nvalue value)
447 (set psw (or (and psw #x0F9C)
448 (or (sll index 12)
449 (basic-psw nvalue ws))))))
451 ; Update the PSW for destination non-register dest, set dest to value.
452 (define-pmacro (set-mem-psw dest value ws)
453 (sequence ((HI nvalue))
454 (set nvalue value)
455 (set psw (or (and psw #xFF9C)
456 (basic-psw nvalue ws)))
457 (set dest nvalue)))
459 ; Update the PSW as with set-psw, but also set the carry flag.
460 (define-pmacro (set-psw-carry Rd index value carry ws)
461 (sequence ((HI nvalue) (HI newpsw))
462 (set nvalue value)
463 (set newpsw (or (or (and psw #x0F98)
464 (sll (and carry #x1) 2))
465 (or (sll index 12)
466 (basic-psw nvalue ws))))
467 (set (reg HI h-gr index) nvalue)
468 (set psw newpsw)
469 ))
471 ; The all-purpose addition operation.
472 (define-pmacro (set-psw-add Rd index a b c)
473 (sequence ((HI value) (HI newpsw))
474 (set value (addc a b c))
475 (set newpsw (or (or (and psw #x0F80)
476 (basic-psw value 1))
477 (or (or (sll HI (add-oflag HI a b c) 4)
478 (sll HI (add-cflag HI a b c) 2))
479 (or (and (srl HI (addc HI (and a #xF) (and b #xF) c)
480 1) #x8)
481 (sll index 12)))))
482 (set (reg HI h-gr index) value)
483 (set psw newpsw)
484 ))
486 ; Set the PSW for a subtraction of a-b into Rd, but don't actually
487 ; do the subtract.
488 (define-pmacro (set-psw-cmp Rd index a b)
489 (sequence ((HI value))
490 (set value (sub a b))
491 (set psw (or (or (and psw #x0F80)
492 (basic-psw value 1))
493 (or (or (sll HI (sub-oflag HI a b 0) 4)
494 (sll HI (sub-cflag HI a b 0) 2))
495 (or (and (srl HI (sub HI (and a #xF) (and b #xF))
496 1) #x8)
497 (sll index 12)))))))
499 ; Likewise, for subtraction
500 ; (this chip has a borrow for subtraction, rather than
501 ; just using a carry for both).
502 (define-pmacro (set-psw-sub Rd index a b c)
503 (sequence ((HI value) (HI newpsw))
504 (set value (subc a b c))
505 (set newpsw (or (or (and psw #x0F80)
506 (basic-psw value 1))
507 (or (or (sll HI (sub-oflag HI a b c) 4)
508 (sll HI (sub-cflag HI a b c) 2))
509 (or (and (srl HI (subc HI (and a #xF) (and b #xF) c)
510 1) #x8)
511 (sll index 12)))))
512 (set (reg HI h-gr index) value)
513 (set psw newpsw)
514 ))
516 ; A 17-bit rotate-left operation
517 (define-pmacro (set-psw-rotate17 Rd index src c rot)
518 (sequence ((SI tmpfoo))
519 (set tmpfoo (or (or (and (sll SI src 15) #x7FFE0000)
520 src)
521 (or (sll SI c 31)
522 (sll SI c 16))))
523 (set tmpfoo (rol tmpfoo (and rot #x1F)))
524 (set-psw-carry (reg HI h-gr index) index (trunc HI tmpfoo) (and (srl tmpfoo 16) 1) 1)))
526 ; A 17-bit rotate-right operation
527 (define-pmacro (set-psw-rrotate17 Rd index src c rot)
528 (sequence ((SI tmpfoo))
529 (set tmpfoo (or (or (and (sll SI src 17) #xFFFE0000)
530 src)
531 (sll SI c 16)))
532 (set tmpfoo (ror tmpfoo (and rot #x0F)))
533 (set-psw-carry (reg HI h-gr index) index (trunc HI tmpfoo) (and (srl tmpfoo 16) 1) 1)))
535 \f
536 ; Move Operations
538 (define-pmacro (alignfix-mem where)
539 (mem HI (and where #xFFFE)))
541 (define-pmacro (set-alignfix-mem where what)
542 (set (mem HI (and where #xFFFE)) what))
544 (define-pmacro (alignfix-mem-far where)
545 (mem HI (and where #xFFFFFFFE)))
547 (define-pmacro (set-alignfix-mem-far where what)
548 (set (mem HI (and where #xFFFFFFFE)) what))
550 (dni movlmemimm
551 "Move immediate to low memory"
552 ()
553 ("mov$ws2 $lmem8,#$imm16")
554 (+ OP1_7 OP2A_8 ws2 lmem8 imm16)
555 (if ws2
556 (set-mem-psw (mem HI (and lmem8 #xFFFE)) imm16 ws2)
557 (set-mem-psw (mem QI lmem8) (and imm16 #xFF) ws2))
558 ()
559 )
560 (dni movhmemimm
561 "Move immediate to high memory"
562 ()
563 ("mov$ws2 $hmem8,#$imm16")
564 (+ OP1_7 OP2A_A ws2 hmem8 imm16)
565 (if ws2
566 (set-mem-psw (mem HI (and hmem8 #xFFFE)) imm16 ws2)
567 (set-mem-psw (mem QI hmem8) (and imm16 #xFF) ws2))
568 ()
569 )
571 (dni movlgrmem
572 "Move low memory to register"
573 ()
574 ("mov$ws2 $Rm,$lmem8")
575 (+ OP1_8 Rm ws2 lmem8)
576 (if ws2
577 (set-psw Rm (index-of Rm) (alignfix-mem lmem8) ws2)
578 (set-psw Rm (index-of Rm) (mem QI lmem8) ws2))
579 ()
580 )
581 (dni movhgrmem
582 "Move high memory to register"
583 ()
584 ("mov$ws2 $Rm,$hmem8")
585 (+ OP1_A Rm ws2 hmem8)
586 (if ws2
587 (set-psw Rm (index-of Rm) (alignfix-mem hmem8) ws2)
588 (set-psw Rm (index-of Rm) (mem QI hmem8) ws2))
589 ()
590 )
592 (dni movlmemgr
593 "Move low memory register to byte"
594 ()
595 ("mov$ws2 $lmem8,$Rm")
596 (+ OP1_9 Rm ws2 lmem8)
597 (if ws2
598 (set-mem-psw (mem HI (and lmem8 #xFFFE)) Rm ws2)
599 (set-mem-psw (mem QI lmem8) Rm ws2))
600 ()
601 )
602 (dni movhmemgr
603 "Move high memory register to byte"
604 ()
605 ("mov$ws2 $hmem8,$Rm")
606 (+ OP1_B Rm ws2 hmem8)
607 (if ws2
608 (set-mem-psw (mem HI (and hmem8 #xFFFE)) Rm ws2)
609 (set-mem-psw (mem QI hmem8) Rm ws2))
610 ()
611 )
613 (dni movgrgri
614 "Move memory addressed by register to register"
615 ()
616 ("mov$ws2 $Rdm,($Rs)")
617 (+ OP1_7 OP2A_0 ws2 Rs OP4M_0 Rdm)
618 (if ws2
619 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
620 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
621 ()
622 )
624 (dni movgrgripostinc
625 "Move memory addressed by postincrement register to register"
626 ()
627 ("mov$ws2 $Rdm,($Rs++)")
628 (+ OP1_6 OP2A_0 ws2 Rs OP4M_0 Rdm)
629 (sequence ()
630 (if ws2
631 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
632 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2))
633 (set Rs (add Rs (add 1 ws2))))
634 ()
635 )
637 (dni movgrgripredec
638 "Move memory addressed by predecrement register to register"
639 ()
640 ("mov$ws2 $Rdm,(--$Rs)")
641 (+ OP1_6 OP2A_8 ws2 Rs OP4M_0 Rdm)
642 (sequence ()
643 (set Rs (sub Rs (add 1 ws2)))
644 (if ws2
645 (set-psw Rdm (index-of Rdm) (alignfix-mem Rs) ws2)
646 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI Rs)) ws2)))
647 ()
648 )
650 (dni movgrigr
651 "Move register to memory addressed by register"
652 ()
653 ("mov$ws2 ($Rs),$Rdm")
654 (+ OP1_7 OP2A_2 ws2 Rs OP4M_0 Rdm)
655 (sequence ()
656 (if ws2
657 (set-alignfix-mem Rs Rdm)
658 (set (mem QI Rs) Rdm))
659 (set-psw-nowrite (index-of Rdm) Rdm ws2))
660 ()
661 )
663 (dni movgripostincgr
664 "Move register to memory addressed by postincrement register"
665 ()
666 ("mov$ws2 ($Rs++),$Rdm")
667 (+ OP1_6 OP2A_2 ws2 Rs OP4M_0 Rdm)
668 (sequence ()
669 (if ws2
670 (set-alignfix-mem Rs Rdm)
671 (set (mem QI Rs) Rdm))
672 (set-psw-nowrite (index-of Rdm) Rdm ws2)
673 (set Rs (add Rs (add ws2 1))))
674 ()
675 )
677 (dni movgripredecgr
678 "Move register to memory addressed by predecrement register"
679 ()
680 ("mov$ws2 (--$Rs),$Rdm")
681 (+ OP1_6 OP2A_A ws2 Rs OP4M_0 Rdm)
682 (sequence ()
683 (set Rs (sub Rs (add ws2 1)))
684 (set-psw-nowrite (index-of Rdm) Rdm ws2)
685 (if ws2
686 (set-alignfix-mem Rs Rdm)
687 (set (mem QI Rs) Rdm)))
688 ()
689 )
691 (dni movgrgrii
692 "Move memory addressed by indexed register to register"
693 ()
694 ("mov$ws2 $Rdm,($Rs,$imm12)")
695 (+ OP1_7 OP2A_0 ws2 Rs OP4M_1 Rdm OP5_0 imm12)
696 (if ws2
697 (set-psw Rdm (index-of Rdm) (alignfix-mem (add Rs imm12)) ws2)
698 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add Rs imm12))) ws2))
699 ()
700 )
702 (dni movgrgriipostinc
703 "Move memory addressed by indexed register postincrement to register"
704 ()
705 ("mov$ws2 $Rdm,($Rs++,$imm12)")
706 (+ OP1_6 OP2A_0 ws2 Rs OP4M_1 Rdm OP5_0 imm12)
707 (sequence ()
708 (if ws2
709 (set-psw Rdm (index-of Rdm) (alignfix-mem (add Rs imm12)) ws2)
710 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add Rs imm12))) ws2))
711 (set Rs (add Rs (add ws2 1))))
712 ()
713 )
715 (dni movgrgriipredec
716 "Move memory addressed by indexed register predecrement to register"
717 ()
718 ("mov$ws2 $Rdm,(--$Rs,$imm12)")
719 (+ OP1_6 OP2A_8 ws2 Rs OP4M_1 Rdm OP5_0 imm12)
720 (sequence ()
721 (set Rs (sub Rs (add ws2 1)))
722 (if ws2
723 (set-psw Rdm (index-of Rdm) (alignfix-mem (add Rs imm12)) ws2)
724 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add Rs imm12))) ws2)))
725 ()
726 )
728 (dni movgriigr
729 "Move register to memory addressed by indexed register"
730 ()
731 ("mov$ws2 ($Rs,$imm12),$Rdm")
732 (+ OP1_7 OP2A_2 ws2 Rs OP4M_1 Rdm OP5_0 imm12)
733 (sequence ()
734 (if ws2
735 (set-alignfix-mem (add Rs imm12) Rdm)
736 (set (mem QI (add Rs imm12)) Rdm))
737 (set-psw-nowrite (index-of Rdm) Rdm ws2))
738 ()
739 )
741 (dni movgriipostincgr
742 "Move register to memory addressed by indexed register postincrement"
743 ()
744 ("mov$ws2 ($Rs++,$imm12),$Rdm")
745 (+ OP1_6 OP2A_2 ws2 Rs OP4M_1 Rdm OP5_0 imm12)
746 (sequence ()
747 (if ws2
748 (set-alignfix-mem (add Rs imm12) Rdm)
749 (set (mem QI (add Rs imm12)) Rdm))
750 (set-psw-nowrite (index-of Rdm) Rdm ws2)
751 (set Rs (add Rs (add ws2 1))))
752 ()
753 )
755 (dni movgriipredecgr
756 "Move register to memory addressed by indexed register predecrement"
757 ()
758 ("mov$ws2 (--$Rs,$imm12),$Rdm")
759 (+ OP1_6 OP2A_A ws2 Rs OP4M_1 Rdm OP5_0 imm12)
760 (sequence ()
761 (set Rs (sub Rs (add ws2 1)))
762 (set-psw-nowrite (index-of Rdm) Rdm ws2)
763 (if ws2
764 (set-alignfix-mem (add Rs imm12) Rdm)
765 (set (mem QI (add Rs imm12)) Rdm)))
766 ()
767 )
769 (dni movgrgr
770 "Move general register to general register"
771 ()
772 ("mov $Rd,$Rs")
773 (+ OP1_4 OP2_6 Rs Rd)
774 (set-psw Rd (index-of Rd) Rs 1)
775 ()
776 )
778 (dnmi movimm8
779 "Move 8-bit immediate"
780 ()
781 ("mov Rx,#$imm8")
782 (emit movwimm8 imm8)
783 )
785 (dni movwimm8
786 "Move 8-bit immediate"
787 ()
788 ("mov.w Rx,#$imm8")
789 (+ OP1_4 OP2_7 imm8)
790 (set-psw (reg HI h-gr Rpsw) Rpsw imm8 1)
791 ()
792 )
794 (dnmi movgrimm8
795 "Move 8-bit immediate to general register"
796 ()
797 ("mov $Rm,#$imm8small")
798 (emit movwgrimm8 Rm imm8small)
799 )
801 (dni movwgrimm8
802 "Move 8-bit immediate to general register"
803 ()
804 ("mov.w $Rm,#$imm8small")
805 (+ OP1_2 Rm OP2M_1 imm8small)
806 (set-psw Rm (index-of Rm) imm8small 1)
807 ()
808 )
810 (dnmi movgrimm16
811 "Move 16-bit immediate to general register"
812 ()
813 ("mov $Rd,#$imm16")
814 (emit movwgrimm16 Rd imm16)
815 )
817 (dni movwgrimm16
818 "Move 16-bit immediate to general register"
819 ()
820 ("mov.w $Rd,#$imm16")
821 (+ OP1_3 OP2_1 OP3_3 Rd imm16)
822 (set-psw Rd (index-of Rd) imm16 1)
823 ()
824 )
826 (dni movlowgr
827 "Move 8 low bits to general register"
828 ()
829 ("mov.b $Rd,RxL")
830 (+ OP1_3 OP2_0 OP3_C Rd)
831 (set-psw Rd (index-of Rd) (or (and Rd #xFF00) (and (reg HI h-gr Rpsw) #xFF)) 0)
832 ()
833 )
835 (dni movhighgr
836 "Move 8 high bits to general register"
837 ()
838 ("mov.b $Rd,RxH")
839 (+ OP1_3 OP2_0 OP3_D Rd)
840 (set-psw Rd (index-of Rd) (or (and Rd #x00FF) (and (reg HI h-gr Rpsw) #xFF00)) 1)
841 ()
842 )
844 (dni movfgrgri
845 "Move far memory addressed by register to register"
846 ()
847 ("movf$ws2 $Rdm,($Rs)")
848 (+ OP1_7 OP2A_4 ws2 Rs OP4M_0 Rdm)
849 (if ws2
850 (set-psw Rdm (index-of Rdm) (alignfix-mem-far (or (sll SI R8 16) Rs)) ws2)
851 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (or (sll SI R8 16) Rs))) ws2))
852 ()
853 )
855 (dni movfgrgripostinc
856 "Move far memory addressed by postincrement register to register"
857 ()
858 ("movf$ws2 $Rdm,($Rs++)")
859 (+ OP1_6 OP2A_4 ws2 Rs OP4M_0 Rdm)
860 (sequence ()
861 (if ws2
862 (set-psw Rdm (index-of Rdm) (alignfix-mem-far (join SI HI R8 Rs)) ws2)
863 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (join SI HI R8 Rs))) ws2))
864 (set Rs (add Rs (add ws2 1))))
865 ()
866 )
868 (dni movfgrgripredec
869 "Move far memory addressed by predecrement register to register"
870 ()
871 ("movf$ws2 $Rdm,(--$Rs)")
872 (+ OP1_6 OP2A_C ws2 Rs OP4M_0 Rdm)
873 (sequence ()
874 (set Rs (sub Rs (add ws2 1)))
875 (if ws2
876 (set-psw Rdm (index-of Rdm) (alignfix-mem-far (join SI HI R8 Rs)) ws2)
877 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (join SI HI R8 Rs))) ws2)))
878 ()
879 )
881 (dni movfgrigr
882 "Move far register to memory addressed by register"
883 ()
884 ("movf$ws2 ($Rs),$Rdm")
885 (+ OP1_7 OP2A_6 ws2 Rs OP4M_0 Rdm)
886 (sequence ()
887 (if ws2
888 (set-alignfix-mem-far (join SI HI R8 Rs) Rdm)
889 (set (mem QI (join SI HI R8 Rs)) Rdm))
890 (set-psw-nowrite (index-of Rdm) Rdm ws2))
891 ()
892 )
894 (dni movfgripostincgr
895 "Move far register to memory addressed by postincrement register"
896 ()
897 ("movf$ws2 ($Rs++),$Rdm")
898 (+ OP1_6 OP2A_6 ws2 Rs OP4M_0 Rdm)
899 (sequence ()
900 (if ws2
901 (set-alignfix-mem-far (join SI HI R8 Rs) Rdm)
902 (set (mem QI (join SI HI R8 Rs)) Rdm))
903 (set-psw-nowrite (index-of Rdm) Rdm ws2)
904 (set Rs (add Rs (add ws2 1))))
905 ()
906 )
908 (dni movfgripredecgr
909 "Move far register to memory addressed by predecrement register"
910 ()
911 ("movf$ws2 (--$Rs),$Rdm")
912 (+ OP1_6 OP2A_E ws2 Rs OP4M_0 Rdm)
913 (sequence ()
914 (set-psw-nowrite (index-of Rdm) Rdm ws2)
915 (set Rs (sub Rs (add ws2 1)))
916 (if ws2
917 (set-alignfix-mem-far (join SI HI R8 Rs) Rdm)
918 (set (mem QI (join SI HI R8 Rs)) Rdm)))
919 ()
920 )
922 (dni movfgrgrii
923 "Move far memory addressed by indexed register to register"
924 ()
925 ("movf$ws2 $Rdm,($Rb,$Rs,$imm12)")
926 (+ OP1_7 OP2A_4 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
927 (if ws2
928 (set-psw Rdm (index-of Rdm) (alignfix-mem-far (add (join SI HI Rb Rs) imm12)) ws2)
929 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2))
930 ()
931 )
933 (dni movfgrgriipostinc
934 "Move far memory addressed by indexed register postincrement to register"
935 ()
936 ("movf$ws2 $Rdm,($Rb,$Rs++,$imm12)")
937 (+ OP1_6 OP2A_4 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
938 (sequence ()
939 (if ws2
940 (set-psw Rdm (index-of Rdm) (alignfix-mem-far (add (join SI HI Rb Rs) imm12)) ws2)
941 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2))
942 (set Rs (add Rs (add ws2 1)))
943 ; Note - despite the XStormy16 ISA documentation the
944 ; addition *is* propogated into the base register.
945 (if (eq Rs 0) (set Rb (add Rb 1)))
946 )
947 ()
948 )
950 (dni movfgrgriipredec
951 "Move far memory addressed by indexed register predecrement to register"
952 ()
953 ("movf$ws2 $Rdm,($Rb,--$Rs,$imm12)")
954 (+ OP1_6 OP2A_C ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
955 (sequence ()
956 ; Note - despite the XStormy16 ISA documentation the
957 ; subtraction *is* propogated into the base register.
958 (if (eq Rs 0) (set Rb (sub Rb 1)))
959 (set Rs (sub Rs (add ws2 1)))
960 (if ws2
961 (set-psw Rdm (index-of Rdm) (alignfix-mem-far (add (join SI HI Rb Rs) imm12)) ws2)
962 (set-psw Rdm (index-of Rdm) (and #xFF (mem QI (add (join SI HI Rb Rs) imm12))) ws2)))
963 ()
964 )
966 (dni movfgriigr
967 "Move far register to memory addressed by indexed register"
968 ()
969 ("movf$ws2 ($Rb,$Rs,$imm12),$Rdm")
970 (+ OP1_7 OP2A_6 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
971 (sequence ()
972 (if ws2
973 (set (mem HI (and (add (join SI HI Rb Rs) imm12) #xFFFFFFFE))
974 Rdm)
975 (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm))
976 (set-psw-nowrite (index-of Rdm) Rdm ws2))
977 ()
978 )
981 (dni movfgriipostincgr
982 "Move far register to memory addressed by indexed register postincrement"
983 ()
984 ("movf$ws2 ($Rb,$Rs++,$imm12),$Rdm")
985 (+ OP1_6 OP2A_6 ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
986 (sequence ()
987 (if ws2
988 (set (mem HI (and (add (join SI HI Rb Rs) imm12) #xFFFFFFFE)) Rdm)
989 (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm))
990 (set-psw-nowrite (index-of Rdm) Rdm ws2)
991 (set Rs (add Rs (add ws2 1)))
992 ; Note - despite the XStormy16 ISA documentation the
993 ; addition *is* propogated into the base register.
994 (if (eq Rs 0) (set Rb (add Rb 1)))
995 )
996 ()
997 )
999 (dni movfgriipredecgr
1000 "Move far register to memory addressed by indexed register predecrement"
1001 ()
1002 ("movf$ws2 ($Rb,--$Rs,$imm12),$Rdm")
1003 (+ OP1_6 OP2A_E ws2 Rs OP4M_1 Rdm OP5A_0 Rb imm12)
1004 (sequence ()
1005 ; Note - despite the XStormy16 ISA documentation the
1006 ; subtraction *is* propogated into the base register.
1007 (if (eq Rs 0) (set Rb (sub Rb 1)))
1008 (set Rs (sub Rs (add ws2 1)))
1009 (set-psw-nowrite (index-of Rdm) Rdm ws2)
1010 (if ws2
1011 (set (mem HI (and (add (join SI HI Rb Rs) imm12) #xFFFFFFFE)) Rdm)
1012 (set (mem QI (add (join SI HI Rb Rs) imm12)) Rdm)))
1013 ()
1014 )
1016 (dni maskgrgr
1017 "Mask insert controlled by general register"
1018 ()
1019 ("mask $Rd,$Rs")
1020 (+ OP1_3 OP2_3 Rs Rd)
1021 (set-psw Rd (index-of Rd) (or HI (and HI Rd (inv HI Rs)) (and (reg HI h-gr Rpsw) Rs)) 1)
1022 ()
1023 )
1025 (dni maskgrimm16
1026 "Mask insert controlled by immediate value"
1027 ()
1028 ("mask $Rd,#$imm16")
1029 (+ OP1_3 OP2_0 OP3_E Rd imm16)
1030 (set-psw Rd (index-of Rd) (or (and Rd (inv imm16)) (and (reg HI h-gr Rpsw) imm16)) 1)
1031 ()
1032 )
1033 \f
1034 ; Push, Pop
1035 (dni pushgr
1036 "Push register"
1037 ()
1038 ("push $Rd")
1039 (+ OP1_0 OP2_0 OP3_8 Rd)
1040 (sequence ()
1041 (set (mem HI sp) Rd)
1042 (set sp (add sp 2)))
1043 ()
1044 )
1046 (dni popgr
1047 "Pop into a register"
1048 ()
1049 ("pop $Rd")
1050 (+ OP1_0 OP2_0 OP3_9 Rd)
1051 (sequence ()
1052 (set sp (add sp -2))
1053 (set Rd (mem HI sp)))
1054 ()
1055 )
1057 ; Swap
1058 (dni swpn
1059 "Swap low nibbles"
1060 ()
1061 ("swpn $Rd")
1062 (+ OP1_3 OP2_0 OP3_9 Rd)
1063 (set-psw Rd (index-of Rd) (or (or (and (sll Rd 4) #xF0)
1064 (and (srl Rd 4) #x0F))
1065 (and Rd #xFF00)) 0)
1066 ()
1067 )
1069 (dni swpb
1070 "Swap bytes"
1071 ()
1072 ("swpb $Rd")
1073 (+ OP1_3 OP2_0 OP3_8 Rd)
1074 (set-psw Rd (index-of Rd) (or (sll Rd 8) (srl Rd 8)) 1)
1075 ()
1076 )
1078 (dni swpw
1079 "Swap words"
1080 ()
1081 ("swpw $Rd,$Rs")
1082 (+ OP1_3 OP2_2 Rs Rd)
1083 (sequence ((HI foo))
1084 (set foo Rs)
1085 (set Rs Rd)
1086 (set-psw Rd (index-of Rd) foo 1))
1087 ()
1088 )
1089 \f
1090 ; Logical Operations
1091 (dni andgrgr
1092 "AND general register with general register"
1093 ()
1094 ("and $Rd,$Rs")
1095 (+ OP1_4 OP2_0 Rs Rd)
1096 (set-psw Rd (index-of Rd) (and Rd Rs) 1)
1097 ()
1098 )
1100 (dni andimm8
1101 "AND with 8-bit immediate"
1102 ()
1103 ("and Rx,#$imm8")
1104 (+ OP1_4 OP2_1 imm8)
1105 (set-psw (reg HI h-gr Rpsw) Rpsw (and (reg HI h-gr Rpsw) imm8) 1)
1106 ()
1107 )
1109 (dni andgrimm16
1110 "AND general register with 16-bit immediate"
1111 ()
1112 ("and $Rd,#$imm16")
1113 (+ OP1_3 OP2_1 OP3_0 Rd imm16)
1114 (set-psw Rd (index-of Rd) (and Rd imm16) 1)
1115 ()
1116 )
1118 (dni orgrgr
1119 "OR general register with general register"
1120 ()
1121 ("or $Rd,$Rs")
1122 (+ OP1_4 OP2_2 Rs Rd)
1123 (set-psw Rd (index-of Rd) (or Rd Rs) 1)
1124 ()
1125 )
1127 (dni orimm8
1128 "OR with 8-bit immediate"
1129 ()
1130 ("or Rx,#$imm8")
1131 (+ OP1_4 OP2_3 imm8)
1132 (set-psw (reg HI h-gr Rpsw) Rpsw (or (reg HI h-gr Rpsw) imm8) 1)
1133 ()
1134 )
1136 (dni orgrimm16
1137 "OR general register with 16-bit immediate"
1138 ()
1139 ("or $Rd,#$imm16")
1140 (+ OP1_3 OP2_1 OP3_1 Rd imm16)
1141 (set-psw Rd (index-of Rd) (or Rd imm16) 1)
1142 ()
1143 )
1145 (dni xorgrgr
1146 "XOR general register with general register"
1147 ()
1148 ("xor $Rd,$Rs")
1149 (+ OP1_4 OP2_4 Rs Rd)
1150 (set-psw Rd (index-of Rd) (xor Rd Rs) 1)
1151 ()
1152 )
1154 (dni xorimm8
1155 "XOR with 8-bit immediate"
1156 ()
1157 ("xor Rx,#$imm8")
1158 (+ OP1_4 OP2_5 imm8)
1159 (set-psw (reg HI h-gr Rpsw) Rpsw (xor (reg HI h-gr Rpsw) imm8) 1)
1160 ()
1161 )
1163 (dni xorgrimm16
1164 "XOR general register with 16-bit immediate"
1165 ()
1166 ("xor $Rd,#$imm16")
1167 (+ OP1_3 OP2_1 OP3_2 Rd imm16)
1168 (set-psw Rd (index-of Rd) (xor Rd imm16) 1)
1169 ()
1170 )
1172 (dni notgr
1173 "NOT general register"
1174 ()
1175 ("not $Rd")
1176 (+ OP1_3 OP2_0 OP3_B Rd)
1177 (set-psw Rd (index-of Rd) (inv Rd) 1)
1178 ()
1179 )
1180 \f
1181 ; Arithmetic operations
1182 (dni addgrgr
1183 "ADD general register to general register"
1184 ()
1185 ("add $Rd,$Rs")
1186 (+ OP1_4 OP2_9 Rs Rd)
1187 (set-psw-add Rd (index-of Rd) Rd Rs 0)
1188 ()
1189 )
1191 (dni addgrimm4
1192 "ADD 4-bit immediate to general register"
1193 ()
1194 ("add $Rd,#$imm4")
1195 (+ OP1_5 OP2_1 imm4 Rd)
1196 (set-psw-add Rd (index-of Rd) Rd imm4 0)
1197 ()
1198 )
1200 (dni addimm8
1201 "ADD 8-bit immediate"
1202 ()
1203 ("add Rx,#$imm8")
1204 (+ OP1_5 OP2_9 imm8)
1205 (set-psw-add (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 0)
1206 ()
1207 )
1209 (dni addgrimm16
1210 "ADD 16-bit immediate to general register"
1211 ()
1212 ("add $Rd,#$imm16")
1213 (+ OP1_3 OP2_1 OP3_4 Rd imm16)
1214 (set-psw-add Rd (index-of Rd) Rd imm16 0)
1215 ()
1216 )
1218 (dni adcgrgr
1219 "ADD carry and general register to general register"
1220 ()
1221 ("adc $Rd,$Rs")
1222 (+ OP1_4 OP2_B Rs Rd)
1223 (set-psw-add Rd (index-of Rd) Rd Rs psw-cy)
1224 ()
1225 )
1227 (dni adcgrimm4
1228 "ADD carry and 4-bit immediate to general register"
1229 ()
1230 ("adc $Rd,#$imm4")
1231 (+ OP1_5 OP2_3 imm4 Rd)
1232 (set-psw-add Rd (index-of Rd) Rd imm4 psw-cy)
1233 ()
1234 )
1236 (dni adcimm8
1237 "ADD carry and 8-bit immediate"
1238 ()
1239 ("adc Rx,#$imm8")
1240 (+ OP1_5 OP2_B imm8)
1241 (set-psw-add (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 psw-cy)
1242 ()
1243 )
1245 (dni adcgrimm16
1246 "ADD carry and 16-bit immediate to general register"
1247 ()
1248 ("adc $Rd,#$imm16")
1249 (+ OP1_3 OP2_1 OP3_5 Rd imm16)
1250 (set-psw-add Rd (index-of Rd) Rd imm16 psw-cy)
1251 ()
1252 )
1254 (dni subgrgr
1255 "SUB general register from general register"
1256 ()
1257 ("sub $Rd,$Rs")
1258 (+ OP1_4 OP2_D Rs Rd)
1259 (set-psw-sub Rd (index-of Rd) Rd Rs 0)
1260 ()
1261 )
1263 (dni subgrimm4
1264 "SUB 4-bit immediate from general register"
1265 ()
1266 ("sub $Rd,#$imm4")
1267 (+ OP1_5 OP2_5 imm4 Rd)
1268 (set-psw-sub Rd (index-of Rd) Rd imm4 0)
1269 ()
1270 )
1272 (dni subimm8
1273 "SUB 8-bit immediate"
1274 ()
1275 ("sub Rx,#$imm8")
1276 (+ OP1_5 OP2_D imm8)
1277 (set-psw-sub (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 0)
1278 ()
1279 )
1281 (dni subgrimm16
1282 "SUB 16-bit immediate from general register"
1283 ()
1284 ("sub $Rd,#$imm16")
1285 (+ OP1_3 OP2_1 OP3_6 Rd imm16)
1286 (set-psw-sub Rd (index-of Rd) Rd imm16 0)
1287 ()
1288 )
1290 (dni sbcgrgr
1291 "SUB carry and general register from general register"
1292 ()
1293 ("sbc $Rd,$Rs")
1294 (+ OP1_4 OP2_F Rs Rd)
1295 (set-psw-sub Rd (index-of Rd) Rd Rs psw-cy)
1296 ()
1297 )
1299 (dni sbcgrimm4
1300 "SUB carry and 4-bit immediate from general register"
1301 ()
1302 ("sbc $Rd,#$imm4")
1303 (+ OP1_5 OP2_7 imm4 Rd)
1304 (set-psw-sub Rd (index-of Rd) Rd imm4 psw-cy)
1305 ()
1306 )
1308 (dni sbcgrimm8
1309 "SUB carry and 8-bit immediate"
1310 ()
1311 ("sbc Rx,#$imm8")
1312 (+ OP1_5 OP2_F imm8)
1313 (set-psw-sub (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm8 psw-cy)
1314 ()
1315 )
1317 (dni sbcgrimm16
1318 "SUB carry and 16-bit immediate from general register"
1319 ()
1320 ("sbc $Rd,#$imm16")
1321 (+ OP1_3 OP2_1 OP3_7 Rd imm16)
1322 (set-psw-sub Rd (index-of Rd) Rd imm16 psw-cy)
1323 ()
1324 )
1326 (dnmi incgr
1327 "Increment general register"
1328 ()
1329 ("inc $Rd")
1330 (emit incgrimm2 Rd (imm2 0))
1331 )
1333 (dni incgrimm2
1334 "Increment general register by 2-bit immediate"
1335 ()
1336 ("inc $Rd,#$imm2")
1337 (+ OP1_3 OP2_0 OP3A_0 imm2 Rd)
1338 (set-psw Rd (index-of Rd) (add Rd (add imm2 1)) 1)
1339 ()
1340 )
1342 (dnmi decgr
1343 "Decrement general register"
1344 ()
1345 ("dec $Rd")
1346 (emit decgrimm2 Rd (imm2 0))
1347 )
1349 (dni decgrimm2
1350 "Decrement general register by 2-bit immediate"
1351 ()
1352 ("dec $Rd,#$imm2")
1353 (+ OP1_3 OP2_0 OP3A_1 imm2 Rd)
1354 (set-psw Rd (index-of Rd) (sub Rd (add imm2 1)) 1)
1355 ()
1356 )
1357 \f
1358 ; Logical Shift
1359 (dni rrcgrgr
1360 "Rotate right general register by general register"
1361 ()
1362 ("rrc $Rd,$Rs")
1363 (+ OP1_3 OP2_8 Rs Rd)
1364 (set-psw-rrotate17 Rd (index-of Rd) Rd psw-cy Rs)
1365 ()
1366 )
1368 (dni rrcgrimm4
1369 "Rotate right general register by immediate"
1370 ()
1371 ("rrc $Rd,#$imm4")
1372 (+ OP1_3 OP2_9 imm4 Rd)
1373 (set-psw-rrotate17 Rd (index-of Rd) Rd psw-cy imm4)
1374 ()
1375 )
1377 (dni rlcgrgr
1378 "Rotate left general register by general register"
1379 ()
1380 ("rlc $Rd,$Rs")
1381 (+ OP1_3 OP2_A Rs Rd)
1382 (set-psw-rotate17 Rd (index-of Rd) Rd psw-cy (and Rs #xF))
1383 ()
1384 )
1386 (dni rlcgrimm4
1387 "Rotate left general register by immediate"
1388 ()
1389 ("rlc $Rd,#$imm4")
1390 (+ OP1_3 OP2_B imm4 Rd)
1391 (set-psw-rotate17 Rd (index-of Rd) Rd psw-cy imm4)
1392 ()
1393 )
1395 (dni shrgrgr
1396 "Shift right general register by general register"
1397 ()
1398 ("shr $Rd,$Rs")
1399 (+ OP1_3 OP2_C Rs Rd)
1400 (set-psw-carry Rd (index-of Rd)
1401 (srl Rd (and Rs #xF))
1402 (and SI (if SI (eq (and Rs #xF) 0)
1403 psw-cy
1404 (srl Rd (sub (and Rs #xF) 1)))
1405 1) 1)
1406 ()
1407 )
1409 (dni shrgrimm
1410 "Shift right general register by immediate"
1411 ()
1412 ("shr $Rd,#$imm4")
1413 (+ OP1_3 OP2_D imm4 Rd)
1414 (set-psw-carry Rd (index-of Rd)
1415 (srl Rd imm4)
1416 (and SI (if SI (eq imm4 0)
1417 psw-cy
1418 (srl Rd (sub imm4 1)))
1419 1) 1)
1420 ()
1421 )
1423 (dni shlgrgr
1424 "Shift left general register by general register"
1425 ()
1426 ("shl $Rd,$Rs")
1427 (+ OP1_3 OP2_E Rs Rd)
1428 (set-psw-carry Rd (index-of Rd)
1429 (sll Rd (and Rs #xF))
1430 (srl SI (if SI (eq (and Rs #xF) 0)
1431 (sll psw-cy 15)
1432 (sll Rd (sub (and Rs #xF) 1)))
1433 15) 1)
1434 ()
1435 )
1437 (dni shlgrimm
1438 "Shift left general register by immediate"
1439 ()
1440 ("shl $Rd,#$imm4")
1441 (+ OP1_3 OP2_F imm4 Rd)
1442 (set-psw-carry Rd (index-of Rd)
1443 (sll Rd imm4)
1444 (srl SI (if SI (eq imm4 0)
1445 (sll psw-cy 15)
1446 (sll Rd (sub imm4 1)))
1447 15) 1)
1448 ()
1449 )
1451 (dni asrgrgr
1452 "Arithmetic shift right general register by general register"
1453 ()
1454 ("asr $Rd,$Rs")
1455 (+ OP1_3 OP2_6 Rs Rd)
1456 (set-psw-carry Rd (index-of Rd)
1457 (sra HI Rd (and Rs #xF))
1458 (and SI (if SI (eq (and Rs #xF) 0)
1459 psw-cy
1460 (srl Rd (sub (and Rs #xF) 1)))
1461 1) 1)
1462 ()
1463 )
1465 (dni asrgrimm
1466 "Arithmetic shift right general register by immediate"
1467 ()
1468 ("asr $Rd,#$imm4")
1469 (+ OP1_3 OP2_7 imm4 Rd)
1470 (set-psw-carry Rd (index-of Rd)
1471 (sra HI Rd imm4)
1472 (and SI (if SI (eq imm4 0)
1473 psw-cy
1474 (srl Rd (sub imm4 1)))
1475 1) 1)
1476 ()
1477 )
1478 \f
1479 ; Bitwise operations
1480 (dni set1grimm
1481 "Set bit in general register by immediate"
1482 ()
1483 ("set1 $Rd,#$imm4")
1484 (+ OP1_0 OP2_9 imm4 Rd)
1485 (set-psw Rd (index-of Rd) (or Rd (sll 1 imm4)) 1)
1486 ()
1487 )
1489 (dni set1grgr
1490 "Set bit in general register by general register"
1491 ()
1492 ("set1 $Rd,$Rs")
1493 (+ OP1_0 OP2_B Rs Rd)
1494 (set-psw Rd (index-of Rd) (or Rd (sll 1 (and Rs #xF))) 1)
1495 ()
1496 )
1498 (dni set1lmemimm
1499 "Set bit in low memory by immediate"
1500 ()
1501 ("set1 $lmem8,#$imm3")
1502 (+ OP1_E imm3 OP2M_1 lmem8)
1503 (set-mem-psw (mem QI lmem8) (or (mem QI lmem8) (sll 1 imm3)) 0)
1504 ()
1505 )
1506 (dni set1hmemimm
1507 "Set bit in high memory by immediate"
1508 ()
1509 ("set1 $hmem8,#$imm3")
1510 (+ OP1_F imm3 OP2M_1 hmem8)
1511 (set-mem-psw (mem QI hmem8) (or (mem QI hmem8) (sll 1 imm3)) 0)
1512 ()
1513 )
1515 (dni clr1grimm
1516 "Clear bit in general register by immediate"
1517 ()
1518 ("clr1 $Rd,#$imm4")
1519 (+ OP1_0 OP2_8 imm4 Rd)
1520 (set-psw Rd (index-of Rd) (and Rd (inv (sll 1 imm4))) 1)
1521 ()
1522 )
1524 (dni clr1grgr
1525 "Clear bit in general register by general register"
1526 ()
1527 ("clr1 $Rd,$Rs")
1528 (+ OP1_0 OP2_A Rs Rd)
1529 (set-psw Rd (index-of Rd) (and Rd (inv (sll 1 (and Rs #xF)))) 1)
1530 ()
1531 )
1533 (dni clr1lmemimm
1534 "Clear bit in low memory"
1535 ()
1536 ("clr1 $lmem8,#$imm3")
1537 (+ OP1_E imm3 OP2M_0 lmem8)
1538 (set-mem-psw (mem QI lmem8) (and (mem QI lmem8) (inv (sll 1 imm3))) 0)
1539 ()
1540 )
1541 (dni clr1hmemimm
1542 "Clear bit in high memory"
1543 ()
1544 ("clr1 $hmem8,#$imm3")
1545 (+ OP1_F imm3 OP2M_0 hmem8)
1546 (set-mem-psw (mem QI hmem8) (and (mem QI hmem8) (inv (sll 1 imm3))) 0)
1547 ()
1548 )
1550 ; Data conversion
1552 (dni cbwgr
1553 "Sign-extend byte in general register"
1554 ()
1555 ("cbw $Rd")
1556 (+ OP1_3 OP2_0 OP3_A Rd)
1557 (set-psw Rd (index-of Rd) (ext HI (trunc QI Rd)) 1)
1558 ()
1559 )
1561 (dni revgr
1562 "Reverse bit pattern in general register"
1563 ()
1564 ("rev $Rd")
1565 (+ OP1_3 OP2_0 OP3_F Rd)
1566 (set-psw Rd (index-of Rd)
1567 (or (sll (and Rd #x0001) 15)
1568 (or (sll (and Rd #x0002) 13)
1569 (or (sll (and Rd #x0004) 11)
1570 (or (sll (and Rd #x0008) 9)
1571 (or (sll (and Rd #x0010) 7)
1572 (or (sll (and Rd #x0020) 5)
1573 (or (sll (and Rd #x0040) 3)
1574 (or (sll (and Rd #x0080) 1)
1575 (or (srl (and Rd #x0100) 1)
1576 (or (srl (and Rd #x0200) 3)
1577 (or (srl (and Rd #x0400) 5)
1578 (or (srl (and Rd #x0800) 7)
1579 (or (srl (and Rd #x1000) 9)
1580 (or (srl (and Rd #x2000) 11)
1581 (or (srl (and Rd #x4000) 13)
1582 (srl (and Rd #x8000) 15))))))))))))))))
1583 1)
1584 ()
1585 )
1587 ; Conditional Branches
1589 (define-pmacro (cbranch cond dest)
1590 (sequence ((BI tmp))
1591 (case cond
1592 ((0) (set tmp (not (xor psw-s psw-ov)))) ; ge
1593 ((1) (set tmp (not psw-cy))) ; nc
1594 ((2) (set tmp (xor psw-s psw-ov))) ; lt
1595 ((3) (set tmp psw-cy)) ; c
1596 ((4) (set tmp (not (or (xor psw-s psw-ov) psw-z16)))) ; gt
1597 ((5) (set tmp (not (or psw-cy psw-z16)))) ; hi
1598 ((6) (set tmp (or (xor psw-s psw-ov) psw-z16))) ; le
1599 ((7) (set tmp (or psw-cy psw-z16))) ; ls
1600 ((8) (set tmp (not psw-s))) ; pl
1601 ((9) (set tmp (not psw-ov))) ; nv
1602 ((10) (set tmp psw-s)) ; mi
1603 ((11) (set tmp psw-ov)) ; v
1604 ((12) (set tmp (not psw-z8))) ; nz.b
1605 ((13) (set tmp (not psw-z16))) ; nz
1606 ((14) (set tmp psw-z8)) ; z.b
1607 ((15) (set tmp psw-z16))) ; z
1608 (if tmp (set pc dest)))
1609 )
1611 (dni bccgrgr
1612 "Conditional branch comparing general register with general register"
1613 ()
1614 ("b$bcond5 $Rd,$Rs,$rel12")
1615 (+ OP1_0 OP2_D Rs Rd bcond5 rel12)
1616 (sequence ()
1617 (set-psw-cmp Rd (index-of Rd) Rd Rs)
1618 (cbranch bcond5 rel12))
1619 ()
1620 )
1622 ; 4 bytes
1623 (dni bccgrimm8
1624 "Conditional branch comparing general register with 8-bit immediate"
1625 ()
1626 ("b$bcond5 $Rm,#$imm8,$rel12")
1627 (+ OP1_2 OP2M_0 Rm imm8 bcond5 rel12)
1628 (sequence ()
1629 (set-psw-cmp Rm (index-of Rm) Rm imm8)
1630 (cbranch bcond5 rel12))
1631 ()
1632 )
1634 ; 4 bytes
1635 (dni bccimm16
1636 "Conditional branch comparing general register with 16-bit immediate"
1637 ()
1638 ("b$bcond2 Rx,#$imm16,${rel8-4}")
1639 (+ OP1_C bcond2 rel8-4 imm16)
1640 (sequence ()
1641 (set-psw-cmp (reg HI h-gr Rpsw) Rpsw (reg HI h-gr Rpsw) imm16)
1642 (cbranch bcond2 rel8-4))
1643 ()
1644 )
1646 (dni bngrimm4
1647 "Test bit in general register by immediate and branch if 0"
1648 ()
1649 ("bn $Rd,#$imm4,$rel12")
1650 (+ OP1_0 OP2_4 imm4 Rd OP5_0 rel12)
1651 (sequence ()
1652 (set Rpsw (index-of Rd))
1653 (if (eq (and Rd (sll 1 imm4)) 0)
1654 (set pc rel12)))
1655 ()
1656 )
1658 (dni bngrgr
1659 "Test bit in general register by general register and branch if 0"
1660 ()
1661 ("bn $Rd,$Rs,$rel12")
1662 (+ OP1_0 OP2_6 Rs Rd OP5_0 rel12)
1663 (sequence ()
1664 (set Rpsw (index-of Rd))
1665 (if (eq (and Rd (sll 1 Rs)) 0)
1666 (set pc rel12)))
1667 ()
1668 )
1670 (dni bnlmemimm
1671 "Test bit in memory by immediate and branch if 0"
1672 ()
1673 ("bn $lmem8,#$imm3b,$rel12")
1674 (+ OP1_7 OP2_C lmem8 OP5A_0 imm3b rel12)
1675 (if (eq (and (mem QI lmem8) (sll 1 imm3b)) 0)
1676 (set pc rel12))
1677 ()
1678 )
1680 (dni bnhmemimm
1681 "Test bit in memory by immediate and branch if 0"
1682 ()
1683 ("bn $hmem8,#$imm3b,$rel12")
1684 (+ OP1_7 OP2_E hmem8 OP5A_0 imm3b rel12)
1685 (if (eq (and (mem QI hmem8) (sll 1 imm3b)) 0)
1686 (set pc rel12))
1687 ()
1688 )
1690 (dni bpgrimm4
1691 "Test bit in general register by immediate and branch if 1"
1692 ()
1693 ("bp $Rd,#$imm4,$rel12")
1694 (+ OP1_0 OP2_5 imm4 Rd OP5_0 rel12)
1695 (sequence ()
1696 (set Rpsw (index-of Rd))
1697 (if (ne (and Rd (sll 1 imm4)) 0)
1698 (set pc rel12)))
1699 ()
1700 )
1702 (dni bpgrgr
1703 "Test bit in general register by general register and branch if 1"
1704 ()
1705 ("bp $Rd,$Rs,$rel12")
1706 (+ OP1_0 OP2_7 Rs Rd OP5_0 rel12)
1707 (sequence ()
1708 (set Rpsw (index-of Rd))
1709 (if (ne (and Rd (sll 1 Rs)) 0)
1710 (set pc rel12)))
1711 ()
1712 )
1714 (dni bplmemimm
1715 "Test bit in memory by immediate and branch if 1"
1716 ()
1717 ("bp $lmem8,#$imm3b,$rel12")
1718 (+ OP1_7 OP2_D lmem8 OP5A_0 imm3b rel12)
1719 (if (ne (and (mem QI lmem8) (sll 1 imm3b)) 0)
1720 (set pc rel12))
1721 ()
1722 )
1724 (dni bphmemimm
1725 "Test bit in memory by immediate and branch if 1"
1726 ()
1727 ("bp $hmem8,#$imm3b,$rel12")
1728 (+ OP1_7 OP2_F hmem8 OP5A_0 imm3b rel12)
1729 (if (ne (and (mem QI hmem8) (sll 1 imm3b)) 0)
1730 (set pc rel12))
1731 ()
1732 )
1734 (dni bcc
1735 "Conditional branch on flag registers"
1736 ()
1737 ("b$bcond2 ${rel8-2}")
1738 (+ OP1_D bcond2 rel8-2)
1739 (cbranch bcond2 rel8-2)
1740 ()
1741 )
1743 ; Unconditional Branching
1745 (dni bgr
1746 "Branch to register"
1747 ()
1748 ("br $Rd")
1749 (+ OP1_0 OP2_0 OP3_2 Rd)
1750 (set pc (add (add pc 2) Rd))
1751 ()
1752 )
1754 (dni br
1755 "Branch"
1756 ()
1757 ("br $rel12a")
1758 (+ OP1_1 rel12a OP4B_0)
1759 (set pc rel12a)
1760 ()
1761 )
1763 (dni jmp
1764 "Jump"
1765 ()
1766 ("jmp $Rbj,$Rd")
1767 (+ OP1_0 OP2_0 OP3B_4 Rbj Rd)
1768 (set pc (join SI HI Rbj Rd))
1769 ()
1770 )
1772 (dni jmpf
1773 "Jump far"
1774 ()
1775 ("jmpf $abs24")
1776 (+ OP1_0 OP2_2 abs24)
1777 (set pc abs24)
1778 ()
1779 )
1781 ; Call instructions
1782 (define-pmacro (do-call dest ilen)
1783 (sequence ()
1784 (set (mem SI sp) (add pc ilen))
1785 (set sp (add sp 4))
1786 (set pc dest)))
1788 (dni callrgr
1789 "Call relative to general register"
1790 ()
1791 ("callr $Rd")
1792 (+ OP1_0 OP2_0 OP3_1 Rd)
1793 (do-call (add Rd (add pc 2)) 2)
1794 ()
1795 )
1797 (dni callrimm
1798 "Call relative to immediate address"
1799 ()
1800 ("callr $rel12a")
1801 (+ OP1_1 rel12a OP4B_1)
1802 (do-call rel12a 2)
1803 ()
1804 )
1806 (dni callgr
1807 "Call to general registers"
1808 ()
1809 ("call $Rbj,$Rd")
1810 (+ OP1_0 OP2_0 OP3B_A Rbj Rd)
1811 (do-call (join SI HI Rbj Rd) 2)
1812 ()
1813 )
1815 (dni callfimm
1816 "Call far to absolute address"
1817 ()
1818 ("callf $abs24")
1819 (+ OP1_0 OP2_1 abs24)
1820 (do-call abs24 4)
1821 ()
1822 )
1824 (define-pmacro (do-calli dest ilen)
1825 (sequence ()
1826 (set (mem SI sp) (add pc ilen))
1827 (set (mem HI (add sp 4)) psw)
1828 (set sp (add sp 6))
1829 (set pc dest)))
1831 (dni icallrgr
1832 "Call interrupt to general registers pc-relative"
1833 ()
1834 ("icallr $Rd")
1835 (+ OP1_0 OP2_0 OP3_3 Rd)
1836 (do-calli (add Rd (add pc 2)) 2)
1837 ()
1838 )
1840 (dni icallgr
1841 "Call interrupt to general registers"
1842 ()
1843 ("icall $Rbj,$Rd")
1844 (+ OP1_0 OP2_0 OP3B_6 Rbj Rd)
1845 (do-calli (join SI HI Rbj Rd) 2)
1846 ()
1847 )
1849 (dni icallfimm
1850 "Call interrupt far to absolute address"
1851 ()
1852 ("icallf $abs24")
1853 (+ OP1_0 OP2_3 abs24)
1854 (do-calli abs24 4)
1855 ()
1856 )
1858 ; Return instructions
1859 (dni iret
1860 "Return from interrupt"
1861 ()
1862 ("iret")
1863 (+ (f-op #x0002))
1864 (sequence ()
1865 (set sp (sub sp 6))
1866 (set pc (mem SI sp))
1867 (set psw (mem HI (add sp 4))))
1868 ()
1869 )
1871 (dni ret
1872 "Return"
1873 ()
1874 ("ret")
1875 (+ (f-op #x0003))
1876 (sequence ()
1877 (set sp (sub sp 4))
1878 (set pc (mem SI sp)))
1879 ()
1880 )
1882 ; Multiply and Divide instructions
1884 (dni mul
1885 "Multiply"
1886 ()
1887 ("mul")
1888 (+ (f-op #x00D0))
1889 (sequence ((SI value))
1890 (set value (mul SI (and SI R0 #xFFFF) (and SI R2 #xFFFF)))
1891 (set psw (or (and psw #xFF9C)
1892 (basic-psw (trunc HI value) 1)))
1893 (set R0 (trunc HI value))
1894 (set R1 (trunc HI (srl value 16))))
1895 ()
1896 )
1897 (dni div
1898 "Divide"
1899 ()
1900 ("div")
1901 (+ (f-op #x00C0))
1902 (sequence ()
1903 (set R1 (umod R0 R2))
1904 (set-mem-psw R0 (udiv R0 R2) 1))
1905 ()
1906 )
1907 (dni sdiv
1908 "Signed Divide"
1909 ()
1910 ("sdiv")
1911 (+ (f-op #x00C8))
1912 (sequence ()
1913 (set R1 (mod HI R0 R2))
1914 (set-mem-psw R0 (div HI R0 R2) 1))
1915 ()
1916 )
1917 (dni sdivlh
1918 "Divide 32/16"
1919 ()
1920 ("sdivlh")
1921 (+ (f-op #x00E8))
1922 (sequence ((SI value))
1923 (set value (add SI (sll SI (and SI R1 #xffff) #x10) (and SI R0 #xffff)))
1924 (set R1 (mod SI value (ext SI (trunc HI R2))))
1925 (set-mem-psw R0 (div SI value (ext SI (trunc HI R2))) 1))
1926 ()
1927 )
1928 (dni divlh
1929 "Divide 32/16"
1930 ()
1931 ("divlh")
1932 (+ (f-op #x00E0))
1933 (sequence ((SI value))
1934 (set value (add SI (sll SI (and SI R1 #xffff) #x10) (and SI R0 #xffff)))
1935 (set R1 (umod SI value R2))
1936 (set-mem-psw R0 (udiv SI value R2) 1))
1937 ()
1938 )
1940 ; System Control
1942 ; added per sanyo's req -- eq to nop for the moment, but can
1943 ; add function later
1944 (dni reset "reset" () ("reset") (+ (f-op #x000f)) (nop) ())
1946 (dni nop "nop" () ("nop") (+ (f-op #x0000)) (nop) ())
1948 (dni halt "halt" () ("halt") (+ (f-op #x0008)) (c-call VOID "do_halt") ())
1950 (dni hold "hold" () ("hold") (+ (f-op #x000A)) (c-call VOID "do_hold") ())
1952 (dni holdx "holdx" () ("holdx") (+ (f-op #x000B)) (c-call VOID "do_holdx") ())
1954 (dni brk "brk" () ("brk") (+ (f-op #x0005)) (c-call VOID "do_brk") ())
1956 ; An instruction for test instrumentation.
1957 ; Using a reserved opcode.
1958 (dni syscall
1959 "simulator system call"
1960 ()
1961 ("--unused--")
1962 (+ (f-op #x0001))
1963 (c-call VOID "syscall")
1964 ()
1965 )