gdb/v850-tdep.c

   1 /* Target-dependent code for the NEC V850 for GDB, the GNU debugger.
   2
   3    Copyright (C) 1996-2014 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "defs.h"
  21 #include "frame.h"
  22 #include "frame-base.h"
  23 #include "trad-frame.h"
  24 #include "frame-unwind.h"
  25 #include "dwarf2-frame.h"
  26 #include "gdbtypes.h"
  27 #include "inferior.h"
  28 #include <string.h>
  29 #include "gdb_assert.h"
  30 #include "gdbcore.h"
  31 #include "arch-utils.h"
  32 #include "regcache.h"
  33 #include "dis-asm.h"
  34 #include "osabi.h"
  35 #include "elf-bfd.h"
  36 #include "elf/v850.h"
  37
  38 enum
  39   {
  40     /* General purpose registers.  */
  41     E_R0_REGNUM,
  42     E_R1_REGNUM,
  43     E_R2_REGNUM,
  44     E_R3_REGNUM, E_SP_REGNUM = E_R3_REGNUM,
  45     E_R4_REGNUM,
  46     E_R5_REGNUM,
  47     E_R6_REGNUM, E_ARG0_REGNUM = E_R6_REGNUM,
  48     E_R7_REGNUM,
  49     E_R8_REGNUM,
  50     E_R9_REGNUM, E_ARGLAST_REGNUM = E_R9_REGNUM,
  51     E_R10_REGNUM, E_V0_REGNUM = E_R10_REGNUM,
  52     E_R11_REGNUM, E_V1_REGNUM = E_R11_REGNUM,
  53     E_R12_REGNUM,
  54     E_R13_REGNUM,
  55     E_R14_REGNUM,
  56     E_R15_REGNUM,
  57     E_R16_REGNUM,
  58     E_R17_REGNUM,
  59     E_R18_REGNUM,
  60     E_R19_REGNUM,
  61     E_R20_REGNUM,
  62     E_R21_REGNUM,
  63     E_R22_REGNUM,
  64     E_R23_REGNUM,
  65     E_R24_REGNUM,
  66     E_R25_REGNUM,
  67     E_R26_REGNUM,
  68     E_R27_REGNUM,
  69     E_R28_REGNUM,
  70     E_R29_REGNUM, E_FP_REGNUM = E_R29_REGNUM,
  71     E_R30_REGNUM, E_EP_REGNUM = E_R30_REGNUM,
  72     E_R31_REGNUM, E_LP_REGNUM = E_R31_REGNUM,
  73
  74     /* System registers - main banks.  */
  75     E_R32_REGNUM, E_SR0_REGNUM = E_R32_REGNUM,
  76     E_R33_REGNUM,
  77     E_R34_REGNUM,
  78     E_R35_REGNUM,
  79     E_R36_REGNUM,
  80     E_R37_REGNUM, E_PS_REGNUM = E_R37_REGNUM,
  81     E_R38_REGNUM,
  82     E_R39_REGNUM,
  83     E_R40_REGNUM,
  84     E_R41_REGNUM,
  85     E_R42_REGNUM,
  86     E_R43_REGNUM,
  87     E_R44_REGNUM,
  88     E_R45_REGNUM,
  89     E_R46_REGNUM,
  90     E_R47_REGNUM,
  91     E_R48_REGNUM,
  92     E_R49_REGNUM,
  93     E_R50_REGNUM,
  94     E_R51_REGNUM,
  95     E_R52_REGNUM, E_CTBP_REGNUM = E_R52_REGNUM,
  96     E_R53_REGNUM,
  97     E_R54_REGNUM,
  98     E_R55_REGNUM,
  99     E_R56_REGNUM,
 100     E_R57_REGNUM,
 101     E_R58_REGNUM,
 102     E_R59_REGNUM,
 103     E_R60_REGNUM,
 104     E_R61_REGNUM,
 105     E_R62_REGNUM,
 106     E_R63_REGNUM,
 107
 108     /* PC.  */
 109     E_R64_REGNUM, E_PC_REGNUM = E_R64_REGNUM,
 110     E_R65_REGNUM,
 111     E_NUM_OF_V850_REGS,
 112     E_NUM_OF_V850E_REGS = E_NUM_OF_V850_REGS,
 113
 114     /* System registers - MPV (PROT00) bank.  */
 115     E_R66_REGNUM = E_NUM_OF_V850_REGS,
 116     E_R67_REGNUM,
 117     E_R68_REGNUM,
 118     E_R69_REGNUM,
 119     E_R70_REGNUM,
 120     E_R71_REGNUM,
 121     E_R72_REGNUM,
 122     E_R73_REGNUM,
 123     E_R74_REGNUM,
 124     E_R75_REGNUM,
 125     E_R76_REGNUM,
 126     E_R77_REGNUM,
 127     E_R78_REGNUM,
 128     E_R79_REGNUM,
 129     E_R80_REGNUM,
 130     E_R81_REGNUM,
 131     E_R82_REGNUM,
 132     E_R83_REGNUM,
 133     E_R84_REGNUM,
 134     E_R85_REGNUM,
 135     E_R86_REGNUM,
 136     E_R87_REGNUM,
 137     E_R88_REGNUM,
 138     E_R89_REGNUM,
 139     E_R90_REGNUM,
 140     E_R91_REGNUM,
 141     E_R92_REGNUM,
 142     E_R93_REGNUM,
 143
 144     /* System registers - MPU (PROT01) bank.  */
 145     E_R94_REGNUM,
 146     E_R95_REGNUM,
 147     E_R96_REGNUM,
 148     E_R97_REGNUM,
 149     E_R98_REGNUM,
 150     E_R99_REGNUM,
 151     E_R100_REGNUM,
 152     E_R101_REGNUM,
 153     E_R102_REGNUM,
 154     E_R103_REGNUM,
 155     E_R104_REGNUM,
 156     E_R105_REGNUM,
 157     E_R106_REGNUM,
 158     E_R107_REGNUM,
 159     E_R108_REGNUM,
 160     E_R109_REGNUM,
 161     E_R110_REGNUM,
 162     E_R111_REGNUM,
 163     E_R112_REGNUM,
 164     E_R113_REGNUM,
 165     E_R114_REGNUM,
 166     E_R115_REGNUM,
 167     E_R116_REGNUM,
 168     E_R117_REGNUM,
 169     E_R118_REGNUM,
 170     E_R119_REGNUM,
 171     E_R120_REGNUM,
 172     E_R121_REGNUM,
 173
 174     /* FPU system registers.  */
 175     E_R122_REGNUM,
 176     E_R123_REGNUM,
 177     E_R124_REGNUM,
 178     E_R125_REGNUM,
 179     E_R126_REGNUM,
 180     E_R127_REGNUM,
 181     E_R128_REGNUM, E_FPSR_REGNUM = E_R128_REGNUM,
 182     E_R129_REGNUM, E_FPEPC_REGNUM = E_R129_REGNUM,
 183     E_R130_REGNUM, E_FPST_REGNUM = E_R130_REGNUM,
 184     E_R131_REGNUM, E_FPCC_REGNUM = E_R131_REGNUM,
 185     E_R132_REGNUM, E_FPCFG_REGNUM = E_R132_REGNUM,
 186     E_R133_REGNUM,
 187     E_R134_REGNUM,
 188     E_R135_REGNUM,
 189     E_R136_REGNUM,
 190     E_R137_REGNUM,
 191     E_R138_REGNUM,
 192     E_R139_REGNUM,
 193     E_R140_REGNUM,
 194     E_R141_REGNUM,
 195     E_R142_REGNUM,
 196     E_R143_REGNUM,
 197     E_R144_REGNUM,
 198     E_R145_REGNUM,
 199     E_R146_REGNUM,
 200     E_R147_REGNUM,
 201     E_R148_REGNUM,
 202     E_R149_REGNUM,
 203     E_NUM_OF_V850E2_REGS,
 204
 205     /* v850e3v5 system registers, selID 1 thru 7.  */
 206     E_SELID_1_R0_REGNUM = E_NUM_OF_V850E2_REGS,
 207     E_SELID_1_R31_REGNUM = E_SELID_1_R0_REGNUM + 31,
 208
 209     E_SELID_2_R0_REGNUM,
 210     E_SELID_2_R31_REGNUM = E_SELID_2_R0_REGNUM + 31,
 211
 212     E_SELID_3_R0_REGNUM,
 213     E_SELID_3_R31_REGNUM = E_SELID_3_R0_REGNUM + 31,
 214
 215     E_SELID_4_R0_REGNUM,
 216     E_SELID_4_R31_REGNUM = E_SELID_4_R0_REGNUM + 31,
 217
 218     E_SELID_5_R0_REGNUM,
 219     E_SELID_5_R31_REGNUM = E_SELID_5_R0_REGNUM + 31,
 220
 221     E_SELID_6_R0_REGNUM,
 222     E_SELID_6_R31_REGNUM = E_SELID_6_R0_REGNUM + 31,
 223
 224     E_SELID_7_R0_REGNUM,
 225     E_SELID_7_R31_REGNUM = E_SELID_7_R0_REGNUM + 31,
 226
 227     /* v850e3v5 vector registers.  */
 228     E_VR0_REGNUM,
 229     E_VR31_REGNUM = E_VR0_REGNUM + 31,
 230
 231     E_NUM_OF_V850E3V5_REGS,
 232
 233     /* Total number of possible registers.  */
 234     E_NUM_REGS = E_NUM_OF_V850E3V5_REGS
 235   };
 236
 237 enum
 238 {
 239   v850_reg_size = 4
 240 };
 241
 242 /* Size of return datatype which fits into all return registers.  */
 243 enum
 244 {
 245   E_MAX_RETTYPE_SIZE_IN_REGS = 2 * v850_reg_size
 246 };
 247
 248 /* When v850 support was added to GCC in the late nineties, the intention
 249    was to follow the Green Hills ABI for v850.  In fact, the authors of
 250    that support at the time thought that they were doing so.  As far as
 251    I can tell, the calling conventions are correct, but the return value
 252    conventions were not quite right.  Over time, the return value code
 253    in this file was modified to mostly reflect what GCC was actually
 254    doing instead of to actually follow the Green Hills ABI as it did
 255    when the code was first written.
 256
 257    Renesas defined the RH850 ABI which they use in their compiler.  It
 258    is similar to the original Green Hills ABI with some minor
 259    differences.  */
 260
 261 enum v850_abi
 262 {
 263   V850_ABI_GCC,
 264   V850_ABI_RH850
 265 };
 266
 267 /* Architecture specific data.  */
 268
 269 struct gdbarch_tdep
 270 {
 271   /* Fields from the ELF header.  */
 272   int e_flags;
 273   int e_machine;
 274
 275   /* Which ABI are we using?  */
 276   enum v850_abi abi;
 277   int eight_byte_align;
 278 };
 279
 280 struct v850_frame_cache
 281 {
 282   /* Base address.  */
 283   CORE_ADDR base;
 284   LONGEST sp_offset;
 285   CORE_ADDR pc;
 286
 287   /* Flag showing that a frame has been created in the prologue code.  */
 288   int uses_fp;
 289
 290   /* Saved registers.  */
 291   struct trad_frame_saved_reg *saved_regs;
 292 };
 293
 294 /* Info gleaned from scanning a function's prologue.  */
 295 struct pifsr            /* Info about one saved register.  */
 296 {
 297   int offset;           /* Offset from sp or fp.  */
 298   int cur_frameoffset;  /* Current frameoffset.  */
 299   int reg;              /* Saved register number.  */
 300 };
 301
 302 static const char *
 303 v850_register_name (struct gdbarch *gdbarch, int regnum)
 304 {
 305   static const char *v850_reg_names[] =
 306   { "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 307     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 308     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 309     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 310     "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
 311     "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
 312     "sr16", "sr17", "sr18", "sr19", "sr20", "sr21", "sr22", "sr23",
 313     "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
 314     "pc", "fp"
 315   };
 316   if (regnum < 0 || regnum > E_NUM_OF_V850_REGS)
 317     return NULL;
 318   return v850_reg_names[regnum];
 319 }
 320
 321 static const char *
 322 v850e_register_name (struct gdbarch *gdbarch, int regnum)
 323 {
 324   static const char *v850e_reg_names[] =
 325   {
 326     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 327     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 328     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 329     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 330     "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "sr6", "sr7",
 331     "sr8", "sr9", "sr10", "sr11", "sr12", "sr13", "sr14", "sr15",
 332     "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "sr21", "sr22", "sr23",
 333     "sr24", "sr25", "sr26", "sr27", "sr28", "sr29", "sr30", "sr31",
 334     "pc", "fp"
 335   };
 336   if (regnum < 0 || regnum > E_NUM_OF_V850E_REGS)
 337     return NULL;
 338   return v850e_reg_names[regnum];
 339 }
 340
 341 static const char *
 342 v850e2_register_name (struct gdbarch *gdbarch, int regnum)
 343 {
 344   static const char *v850e2_reg_names[] =
 345   {
 346     /* General purpose registers.  */
 347     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 348     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 349     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 350     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 351
 352     /* System registers - main banks.  */
 353     "eipc", "eipsw", "fepc", "fepsw", "ecr", "psw", "pid", "cfg",
 354     "", "", "", "sccfg", "scbp", "eiic", "feic", "dbic",
 355     "ctpc", "ctpsw", "dbpc", "dbpsw", "ctbp", "dir", "", "",
 356     "", "", "", "", "eiwr", "fewr", "dbwr", "bsel",
 357
 358
 359     /* PC.  */
 360     "pc", "",
 361
 362     /* System registers - MPV (PROT00) bank.  */
 363     "vsecr", "vstid", "vsadr", "", "vmecr", "vmtid", "vmadr", "",
 364     "vpecr", "vptid", "vpadr", "", "", "", "", "",
 365     "", "", "", "", "", "", "", "",
 366     "mca", "mcs", "mcc", "mcr",
 367
 368     /* System registers - MPU (PROT01) bank.  */
 369     "mpm", "mpc", "tid", "", "", "", "ipa0l", "ipa0u",
 370     "ipa1l", "ipa1u", "ipa2l", "ipa2u", "ipa3l", "ipa3u", "ipa4l", "ipa4u",
 371     "dpa0l", "dpa0u", "dpa1l", "dpa1u", "dpa2l", "dpa2u", "dpa3l", "dpa3u",
 372     "dpa4l", "dpa4u", "dpa5l", "dpa5u",
 373
 374     /* FPU system registers.  */
 375     "", "", "", "", "", "", "fpsr", "fpepc",
 376     "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
 377     "", "", "", "", "", "", "", "",
 378     "", "", "", "fpspc"
 379   };
 380   if (regnum < 0 || regnum >= E_NUM_OF_V850E2_REGS)
 381     return NULL;
 382   return v850e2_reg_names[regnum];
 383 }
 384
 385 /* Implement the "register_name" gdbarch method for v850e3v5.  */
 386
 387 static const char *
 388 v850e3v5_register_name (struct gdbarch *gdbarch, int regnum)
 389 {
 390   static const char *v850e3v5_reg_names[] =
 391   {
 392     /* General purpose registers.  */
 393     "r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
 394     "r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
 395     "r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
 396     "r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
 397
 398     /* selID 0, not including FPU registers.  The FPU registers are
 399        listed later on.  */
 400     "eipc", "eipsw", "fepc", "fepsw",
 401     "", "psw", "" /* fpsr */, "" /* fpepc */,
 402     "" /* fpst */, "" /* fpcc */, "" /* fpcfg */, "" /* fpec */,
 403     "sesr", "eiic", "feic", "",
 404     "ctpc", "ctpsw", "", "", "ctbp", "", "", "",
 405     "", "", "", "", "eiwr", "fewr", "", "bsel",
 406
 407
 408     /* PC.  */
 409     "pc", "",
 410
 411     /* v850e2 MPV bank.  */
 412     "", "", "", "", "", "", "", "",
 413     "", "", "", "", "", "", "", "",
 414     "", "", "", "", "", "", "", "",
 415     "", "", "", "",
 416
 417     /* Skip v850e2 MPU bank.  It's tempting to reuse these, but we need
 418        32 entries for this bank.  */
 419     "", "", "", "", "", "", "", "",
 420     "", "", "", "", "", "", "", "",
 421     "", "", "", "", "", "", "", "",
 422     "", "", "", "",
 423
 424     /* FPU system registers.  These are actually in selID 0, but
 425        are placed here to preserve register numbering compatibility
 426        with previous architectures.  */
 427     "", "", "", "", "", "", "fpsr", "fpepc",
 428     "fpst", "fpcc", "fpcfg", "fpec", "", "", "", "",
 429     "", "", "", "", "", "", "", "",
 430     "", "", "", "",
 431
 432     /* selID 1.  */
 433     "mcfg0", "mcfg1", "rbase", "ebase", "intbp", "mctl", "pid", "fpipr",
 434     "", "", "tcsel", "sccfg", "scbp", "hvccfg", "hvcbp", "vsel",
 435     "vmprt0", "vmprt1", "vmprt2", "", "", "", "", "vmscctl",
 436     "vmsctbl0", "vmsctbl1", "vmsctbl2", "vmsctbl3", "", "", "", "",
 437
 438     /* selID 2.  */
 439     "htcfg0", "", "", "", "", "htctl", "mea", "asid",
 440     "mei", "ispr", "pmr", "icsr", "intcfg", "", "", "",
 441     "tlbsch", "", "", "", "", "", "", "htscctl",
 442     "htsctbl0", "htsctbl1", "htsctbl2", "htsctbl3",
 443     "htsctbl4", "htsctbl5", "htsctbl6", "htsctbl7",
 444
 445     /* selID 3.  */
 446     "", "", "", "", "", "", "", "",
 447     "", "", "", "", "", "", "", "",
 448     "", "", "", "", "", "", "", "",
 449     "", "", "", "", "", "", "", "",
 450
 451     /* selID 4.  */
 452     "tlbidx", "", "", "", "telo0", "telo1", "tehi0", "tehi1",
 453     "", "", "tlbcfg", "", "bwerrl", "bwerrh", "brerrl", "brerrh",
 454     "ictagl", "ictagh", "icdatl", "icdath",
 455     "dctagl", "dctagh", "dcdatl", "dcdath",
 456     "icctrl", "dcctrl", "iccfg", "dccfg", "icerr", "dcerr", "", "",
 457
 458     /* selID 5.  */
 459     "mpm", "mprc", "", "", "mpbrgn", "mptrgn", "", "",
 460     "mca", "mcs", "mcc", "mcr", "", "", "", "",
 461     "", "", "", "", "mpprt0", "mpprt1", "mpprt2", "",
 462     "", "", "", "", "", "", "", "",
 463
 464     /* selID 6.  */
 465     "mpla0", "mpua0", "mpat0", "", "mpla1", "mpua1", "mpat1", "",
 466     "mpla2", "mpua2", "mpat2", "", "mpla3", "mpua3", "mpat3", "",
 467     "mpla4", "mpua4", "mpat4", "", "mpla5", "mpua5", "mpat5", "",
 468     "mpla6", "mpua6", "mpat6", "", "mpla7", "mpua7", "mpat7", "",
 469
 470     /* selID 7.  */
 471     "mpla8", "mpua8", "mpat8", "", "mpla9", "mpua9", "mpat9", "",
 472     "mpla10", "mpua10", "mpat10", "", "mpla11", "mpua11", "mpat11", "",
 473     "mpla12", "mpua12", "mpat12", "", "mpla13", "mpua13", "mpat13", "",
 474     "mpla14", "mpua14", "mpat14", "", "mpla15", "mpua15", "mpat15", "",
 475
 476     /* Vector Registers */
 477     "vr0", "vr1", "vr2", "vr3", "vr4", "vr5", "vr6", "vr7",
 478     "vr8", "vr9", "vr10", "vr11", "vr12", "vr13", "vr14", "vr15",
 479     "vr16", "vr17", "vr18", "vr19", "vr20", "vr21", "vr22", "vr23",
 480     "vr24", "vr25", "vr26", "vr27", "vr28", "vr29", "vr30", "vr31",
 481   };
 482
 483   if (regnum < 0 || regnum >= E_NUM_OF_V850E3V5_REGS)
 484     return NULL;
 485   return v850e3v5_reg_names[regnum];
 486 }
 487
 488 /* Returns the default type for register N.  */
 489
 490 static struct type *
 491 v850_register_type (struct gdbarch *gdbarch, int regnum)
 492 {
 493   if (regnum == E_PC_REGNUM)
 494     return builtin_type (gdbarch)->builtin_func_ptr;
 495   else if (E_VR0_REGNUM <= regnum && regnum <= E_VR31_REGNUM)
 496     return builtin_type (gdbarch)->builtin_uint64;
 497   return builtin_type (gdbarch)->builtin_int32;
 498 }
 499
 500 static int
 501 v850_type_is_scalar (struct type *t)
 502 {
 503   return (TYPE_CODE (t) != TYPE_CODE_STRUCT
 504           && TYPE_CODE (t) != TYPE_CODE_UNION
 505           && TYPE_CODE (t) != TYPE_CODE_ARRAY);
 506 }
 507
 508 /* Should call_function allocate stack space for a struct return?  */
 509
 510 static int
 511 v850_use_struct_convention (struct gdbarch *gdbarch, struct type *type)
 512 {
 513   int i;
 514   struct type *fld_type, *tgt_type;
 515
 516   if (gdbarch_tdep (gdbarch)->abi == V850_ABI_RH850)
 517     {
 518       if (v850_type_is_scalar (type) && TYPE_LENGTH(type) <= 8)
 519         return 0;
 520
 521       /* Structs are never returned in registers for this ABI.  */
 522       return 1;
 523     }
 524   /* 1. The value is greater than 8 bytes -> returned by copying.  */
 525   if (TYPE_LENGTH (type) > 8)
 526     return 1;
 527
 528   /* 2. The value is a single basic type -> returned in register.  */
 529   if (v850_type_is_scalar (type))
 530     return 0;
 531
 532   /* The value is a structure or union with a single element and that
 533      element is either a single basic type or an array of a single basic
 534      type whose size is greater than or equal to 4 -> returned in register.  */
 535   if ((TYPE_CODE (type) == TYPE_CODE_STRUCT
 536        || TYPE_CODE (type) == TYPE_CODE_UNION)
 537        && TYPE_NFIELDS (type) == 1)
 538     {
 539       fld_type = TYPE_FIELD_TYPE (type, 0);
 540       if (v850_type_is_scalar (fld_type) && TYPE_LENGTH (fld_type) >= 4)
 541         return 0;
 542
 543       if (TYPE_CODE (fld_type) == TYPE_CODE_ARRAY)
 544         {
 545           tgt_type = TYPE_TARGET_TYPE (fld_type);
 546           if (v850_type_is_scalar (tgt_type) && TYPE_LENGTH (tgt_type) >= 4)
 547             return 0;
 548         }
 549     }
 550
 551   /* The value is a structure whose first element is an integer or a float,
 552      and which contains no arrays of more than two elements -> returned in
 553      register.  */
 554   if (TYPE_CODE (type) == TYPE_CODE_STRUCT
 555       && v850_type_is_scalar (TYPE_FIELD_TYPE (type, 0))
 556       && TYPE_LENGTH (TYPE_FIELD_TYPE (type, 0)) == 4)
 557     {
 558       for (i = 1; i < TYPE_NFIELDS (type); ++i)
 559         {
 560           fld_type = TYPE_FIELD_TYPE (type, 0);
 561           if (TYPE_CODE (fld_type) == TYPE_CODE_ARRAY)
 562             {
 563               tgt_type = TYPE_TARGET_TYPE (fld_type);
 564               if (TYPE_LENGTH (fld_type) >= 0 && TYPE_LENGTH (tgt_type) >= 0
 565                   && TYPE_LENGTH (fld_type) / TYPE_LENGTH (tgt_type) > 2)
 566                 return 1;
 567             }
 568         }
 569       return 0;
 570     }
 571
 572   /* The value is a union which contains at least one field which
 573      would be returned in registers according to these rules ->
 574      returned in register.  */
 575   if (TYPE_CODE (type) == TYPE_CODE_UNION)
 576     {
 577       for (i = 0; i < TYPE_NFIELDS (type); ++i)
 578         {
 579           fld_type = TYPE_FIELD_TYPE (type, 0);
 580           if (!v850_use_struct_convention (gdbarch, fld_type))
 581             return 0;
 582         }
 583     }
 584
 585   return 1;
 586 }
 587
 588 /* Structure for mapping bits in register lists to register numbers.  */
 589
 590 struct reg_list
 591 {
 592   long mask;
 593   int regno;
 594 };
 595
 596 /* Helper function for v850_scan_prologue to handle prepare instruction.  */
 597
 598 static void
 599 v850_handle_prepare (int insn, int insn2, CORE_ADDR * current_pc_ptr,
 600                      struct v850_frame_cache *pi, struct pifsr **pifsr_ptr)
 601 {
 602   CORE_ADDR current_pc = *current_pc_ptr;
 603   struct pifsr *pifsr = *pifsr_ptr;
 604   long next = insn2 & 0xffff;
 605   long list12 = ((insn & 1) << 16) + (next & 0xffe0);
 606   long offset = (insn & 0x3e) << 1;
 607   static struct reg_list reg_table[] =
 608   {
 609     {0x00800, 20},              /* r20 */
 610     {0x00400, 21},              /* r21 */
 611     {0x00200, 22},              /* r22 */
 612     {0x00100, 23},              /* r23 */
 613     {0x08000, 24},              /* r24 */
 614     {0x04000, 25},              /* r25 */
 615     {0x02000, 26},              /* r26 */
 616     {0x01000, 27},              /* r27 */
 617     {0x00080, 28},              /* r28 */
 618     {0x00040, 29},              /* r29 */
 619     {0x10000, 30},              /* ep */
 620     {0x00020, 31},              /* lp */
 621     {0, 0}                      /* end of table */
 622   };
 623   int i;
 624
 625   if ((next & 0x1f) == 0x0b)            /* skip imm16 argument */
 626     current_pc += 2;
 627   else if ((next & 0x1f) == 0x13)       /* skip imm16 argument */
 628     current_pc += 2;
 629   else if ((next & 0x1f) == 0x1b)       /* skip imm32 argument */
 630     current_pc += 4;
 631
 632   /* Calculate the total size of the saved registers, and add it to the
 633      immediate value used to adjust SP.  */
 634   for (i = 0; reg_table[i].mask != 0; i++)
 635     if (list12 & reg_table[i].mask)
 636       offset += v850_reg_size;
 637   pi->sp_offset -= offset;
 638
 639   /* Calculate the offsets of the registers relative to the value the SP
 640      will have after the registers have been pushed and the imm5 value has
 641      been subtracted from it.  */
 642   if (pifsr)
 643     {
 644       for (i = 0; reg_table[i].mask != 0; i++)
 645         {
 646           if (list12 & reg_table[i].mask)
 647             {
 648               int reg = reg_table[i].regno;
 649               offset -= v850_reg_size;
 650               pifsr->reg = reg;
 651               pifsr->offset = offset;
 652               pifsr->cur_frameoffset = pi->sp_offset;
 653               pifsr++;
 654             }
 655         }
 656     }
 657
 658   /* Set result parameters.  */
 659   *current_pc_ptr = current_pc;
 660   *pifsr_ptr = pifsr;
 661 }
 662
 663
 664 /* Helper function for v850_scan_prologue to handle pushm/pushl instructions.
 665    The SR bit of the register list is not supported.  gcc does not generate
 666    this bit.  */
 667
 668 static void
 669 v850_handle_pushm (int insn, int insn2, struct v850_frame_cache *pi,
 670                    struct pifsr **pifsr_ptr)
 671 {
 672   struct pifsr *pifsr = *pifsr_ptr;
 673   long list12 = ((insn & 0x0f) << 16) + (insn2 & 0xfff0);
 674   long offset = 0;
 675   static struct reg_list pushml_reg_table[] =
 676   {
 677     {0x80000, E_PS_REGNUM},     /* PSW */
 678     {0x40000, 1},               /* r1 */
 679     {0x20000, 2},               /* r2 */
 680     {0x10000, 3},               /* r3 */
 681     {0x00800, 4},               /* r4 */
 682     {0x00400, 5},               /* r5 */
 683     {0x00200, 6},               /* r6 */
 684     {0x00100, 7},               /* r7 */
 685     {0x08000, 8},               /* r8 */
 686     {0x04000, 9},               /* r9 */
 687     {0x02000, 10},              /* r10 */
 688     {0x01000, 11},              /* r11 */
 689     {0x00080, 12},              /* r12 */
 690     {0x00040, 13},              /* r13 */
 691     {0x00020, 14},              /* r14 */
 692     {0x00010, 15},              /* r15 */
 693     {0, 0}                      /* end of table */
 694   };
 695   static struct reg_list pushmh_reg_table[] =
 696   {
 697     {0x80000, 16},              /* r16 */
 698     {0x40000, 17},              /* r17 */
 699     {0x20000, 18},              /* r18 */
 700     {0x10000, 19},              /* r19 */
 701     {0x00800, 20},              /* r20 */
 702     {0x00400, 21},              /* r21 */
 703     {0x00200, 22},              /* r22 */
 704     {0x00100, 23},              /* r23 */
 705     {0x08000, 24},              /* r24 */
 706     {0x04000, 25},              /* r25 */
 707     {0x02000, 26},              /* r26 */
 708     {0x01000, 27},              /* r27 */
 709     {0x00080, 28},              /* r28 */
 710     {0x00040, 29},              /* r29 */
 711     {0x00010, 30},              /* r30 */
 712     {0x00020, 31},              /* r31 */
 713     {0, 0}                      /* end of table */
 714   };
 715   struct reg_list *reg_table;
 716   int i;
 717
 718   /* Is this a pushml or a pushmh?  */
 719   if ((insn2 & 7) == 1)
 720     reg_table = pushml_reg_table;
 721   else
 722     reg_table = pushmh_reg_table;
 723
 724   /* Calculate the total size of the saved registers, and add it to the
 725      immediate value used to adjust SP.  */
 726   for (i = 0; reg_table[i].mask != 0; i++)
 727     if (list12 & reg_table[i].mask)
 728       offset += v850_reg_size;
 729   pi->sp_offset -= offset;
 730
 731   /* Calculate the offsets of the registers relative to the value the SP
 732      will have after the registers have been pushed and the imm5 value is
 733      subtracted from it.  */
 734   if (pifsr)
 735     {
 736       for (i = 0; reg_table[i].mask != 0; i++)
 737         {
 738           if (list12 & reg_table[i].mask)
 739             {
 740               int reg = reg_table[i].regno;
 741               offset -= v850_reg_size;
 742               pifsr->reg = reg;
 743               pifsr->offset = offset;
 744               pifsr->cur_frameoffset = pi->sp_offset;
 745               pifsr++;
 746             }
 747         }
 748     }
 749
 750   /* Set result parameters.  */
 751   *pifsr_ptr = pifsr;
 752 }
 753
 754 /* Helper function to evaluate if register is one of the "save" registers.
 755    This allows to simplify conditionals in v850_analyze_prologue a lot.  */
 756
 757 static int
 758 v850_is_save_register (int reg)
 759 {
 760  /* The caller-save registers are R2, R20 - R29 and R31.  All other
 761     registers are either special purpose (PC, SP), argument registers,
 762     or just considered free for use in the caller.  */
 763  return reg == E_R2_REGNUM
 764         || (reg >= E_R20_REGNUM && reg <= E_R29_REGNUM)
 765         || reg == E_R31_REGNUM;
 766 }
 767
 768 /* Scan the prologue of the function that contains PC, and record what
 769    we find in PI.  Returns the pc after the prologue.  Note that the
 770    addresses saved in frame->saved_regs are just frame relative (negative
 771    offsets from the frame pointer).  This is because we don't know the
 772    actual value of the frame pointer yet.  In some circumstances, the
 773    frame pointer can't be determined till after we have scanned the
 774    prologue.  */
 775
 776 static CORE_ADDR
 777 v850_analyze_prologue (struct gdbarch *gdbarch,
 778                        CORE_ADDR func_addr, CORE_ADDR pc,
 779                        struct v850_frame_cache *pi, ULONGEST ctbp)
 780 {
 781   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
 782   CORE_ADDR prologue_end, current_pc;
 783   struct pifsr pifsrs[E_NUM_REGS + 1];
 784   struct pifsr *pifsr, *pifsr_tmp;
 785   int ep_used;
 786   int reg;
 787   CORE_ADDR save_pc, save_end;
 788   int regsave_func_p;
 789   int r12_tmp;
 790
 791   memset (&pifsrs, 0, sizeof pifsrs);
 792   pifsr = &pifsrs[0];
 793
 794   prologue_end = pc;
 795
 796   /* Now, search the prologue looking for instructions that setup fp, save
 797      rp, adjust sp and such.  We also record the frame offset of any saved
 798      registers.  */
 799
 800   pi->sp_offset = 0;
 801   pi->uses_fp = 0;
 802   ep_used = 0;
 803   regsave_func_p = 0;
 804   save_pc = 0;
 805   save_end = 0;
 806   r12_tmp = 0;
 807
 808   for (current_pc = func_addr; current_pc < prologue_end;)
 809     {
 810       int insn;
 811       int insn2 = -1; /* dummy value */
 812
 813       insn = read_memory_integer (current_pc, 2, byte_order);
 814       current_pc += 2;
 815       if ((insn & 0x0780) >= 0x0600)    /* Four byte instruction?  */
 816         {
 817           insn2 = read_memory_integer (current_pc, 2, byte_order);
 818           current_pc += 2;
 819         }
 820
 821       if ((insn & 0xffc0) == ((10 << 11) | 0x0780) && !regsave_func_p)
 822         {                       /* jarl <func>,10 */
 823           long low_disp = insn2 & ~(long) 1;
 824           long disp = (((((insn & 0x3f) << 16) + low_disp)
 825                         & ~(long) 1) ^ 0x00200000) - 0x00200000;
 826
 827           save_pc = current_pc;
 828           save_end = prologue_end;
 829           regsave_func_p = 1;
 830           current_pc += disp - 4;
 831           prologue_end = (current_pc
 832                           + (2 * 3)     /* moves to/from ep */
 833                           + 4           /* addi <const>,sp,sp */
 834                           + 2           /* jmp [r10] */
 835                           + (2 * 12)    /* sst.w to save r2, r20-r29, r31 */
 836                           + 20);        /* slop area */
 837         }
 838       else if ((insn & 0xffc0) == 0x0200 && !regsave_func_p)
 839         {                       /* callt <imm6> */
 840           long adr = ctbp + ((insn & 0x3f) << 1);
 841
 842           save_pc = current_pc;
 843           save_end = prologue_end;
 844           regsave_func_p = 1;
 845           current_pc = ctbp + (read_memory_unsigned_integer (adr, 2, byte_order)
 846                                & 0xffff);
 847           prologue_end = (current_pc
 848                           + (2 * 3)     /* prepare list2,imm5,sp/imm */
 849                           + 4           /* ctret */
 850                           + 20);        /* slop area */
 851           continue;
 852         }
 853       else if ((insn & 0xffc0) == 0x0780)       /* prepare list2,imm5 */
 854         {
 855           v850_handle_prepare (insn, insn2, &current_pc, pi, &pifsr);
 856           continue;
 857         }
 858       else if (insn == 0x07e0 && regsave_func_p && insn2 == 0x0144)
 859         {                       /* ctret after processing register save.  */
 860           current_pc = save_pc;
 861           prologue_end = save_end;
 862           regsave_func_p = 0;
 863           continue;
 864         }
 865       else if ((insn & 0xfff0) == 0x07e0 && (insn2 & 5) == 1)
 866         {                       /* pushml, pushmh */
 867           v850_handle_pushm (insn, insn2, pi, &pifsr);
 868           continue;
 869         }
 870       else if ((insn & 0xffe0) == 0x0060 && regsave_func_p)
 871         {                       /* jmp after processing register save.  */
 872           current_pc = save_pc;
 873           prologue_end = save_end;
 874           regsave_func_p = 0;
 875           continue;
 876         }
 877       else if ((insn & 0x07c0) == 0x0780        /* jarl or jr */
 878                || (insn & 0xffe0) == 0x0060     /* jmp */
 879                || (insn & 0x0780) == 0x0580)    /* branch */
 880         {
 881           break;                /* Ran into end of prologue.  */
 882         }
 883
 884       else if ((insn & 0xffe0) == ((E_SP_REGNUM << 11) | 0x0240))
 885         /* add <imm>,sp */
 886         pi->sp_offset += ((insn & 0x1f) ^ 0x10) - 0x10;
 887       else if (insn == ((E_SP_REGNUM << 11) | 0x0600 | E_SP_REGNUM))
 888         /* addi <imm>,sp,sp */
 889         pi->sp_offset += insn2;
 890       else if (insn == ((E_FP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
 891         /* mov sp,fp */
 892         pi->uses_fp = 1;
 893       else if (insn == ((E_R12_REGNUM << 11) | 0x0640 | E_R0_REGNUM))
 894         /* movhi hi(const),r0,r12 */
 895         r12_tmp = insn2 << 16;
 896       else if (insn == ((E_R12_REGNUM << 11) | 0x0620 | E_R12_REGNUM))
 897         /* movea lo(const),r12,r12 */
 898         r12_tmp += insn2;
 899       else if (insn == ((E_SP_REGNUM << 11) | 0x01c0 | E_R12_REGNUM) && r12_tmp)
 900         /* add r12,sp */
 901         pi->sp_offset += r12_tmp;
 902       else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_SP_REGNUM))
 903         /* mov sp,ep */
 904         ep_used = 1;
 905       else if (insn == ((E_EP_REGNUM << 11) | 0x0000 | E_R1_REGNUM))
 906         /* mov r1,ep */
 907         ep_used = 0;
 908       else if (((insn & 0x07ff) == (0x0760 | E_SP_REGNUM)
 909                 || (pi->uses_fp
 910                     && (insn & 0x07ff) == (0x0760 | E_FP_REGNUM)))
 911                && pifsr
 912                && v850_is_save_register (reg = (insn >> 11) & 0x1f))
 913         {
 914           /* st.w <reg>,<offset>[sp] or st.w <reg>,<offset>[fp] */
 915           pifsr->reg = reg;
 916           pifsr->offset = insn2 & ~1;
 917           pifsr->cur_frameoffset = pi->sp_offset;
 918           pifsr++;
 919         }
 920       else if (ep_used
 921                && ((insn & 0x0781) == 0x0501)
 922                && pifsr
 923                && v850_is_save_register (reg = (insn >> 11) & 0x1f))
 924         {
 925           /* sst.w <reg>,<offset>[ep] */
 926           pifsr->reg = reg;
 927           pifsr->offset = (insn & 0x007e) << 1;
 928           pifsr->cur_frameoffset = pi->sp_offset;
 929           pifsr++;
 930         }
 931     }
 932
 933   /* Fix up any offsets to the final offset.  If a frame pointer was created,
 934      use it instead of the stack pointer.  */
 935   for (pifsr_tmp = pifsrs; pifsr_tmp != pifsr; pifsr_tmp++)
 936     {
 937       pifsr_tmp->offset -= pi->sp_offset - pifsr_tmp->cur_frameoffset;
 938       pi->saved_regs[pifsr_tmp->reg].addr = pifsr_tmp->offset;
 939     }
 940
 941   return current_pc;
 942 }
 943
 944 /* Return the address of the first code past the prologue of the function.  */
 945
 946 static CORE_ADDR
 947 v850_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
 948 {
 949   CORE_ADDR func_addr, func_end;
 950
 951   /* See what the symbol table says.  */
 952
 953   if (find_pc_partial_function (pc, NULL, &func_addr, &func_end))
 954     {
 955       struct symtab_and_line sal;
 956
 957       sal = find_pc_line (func_addr, 0);
 958       if (sal.line != 0 && sal.end < func_end)
 959         return sal.end;
 960
 961       /* Either there's no line info, or the line after the prologue is after
 962          the end of the function.  In this case, there probably isn't a
 963          prologue.  */
 964       return pc;
 965     }
 966
 967   /* We can't find the start of this function, so there's nothing we
 968      can do.  */
 969   return pc;
 970 }
 971
 972 /* Return 1 if the data structure has any 8-byte fields that'll require
 973    the entire data structure to be aligned.  Otherwise, return 0.  */
 974
 975 static int
 976 v850_eight_byte_align_p (struct type *type)
 977 {
 978   type = check_typedef (type);
 979
 980   if (v850_type_is_scalar (type))
 981     return (TYPE_LENGTH (type) == 8);
 982   else
 983     {
 984       int i;
 985
 986       for (i = 0; i < TYPE_NFIELDS (type); i++)
 987         {
 988           if (v850_eight_byte_align_p (TYPE_FIELD_TYPE (type, i)))
 989             return 1;
 990         }
 991     }
 992   return 0;
 993 }
 994
 995 static CORE_ADDR
 996 v850_frame_align (struct gdbarch *ignore, CORE_ADDR sp)
 997 {
 998   return sp & ~3;
 999 }
1000
1001 /* Setup arguments and LP for a call to the target.  First four args
1002    go in R6->R9, subsequent args go into sp + 16 -> sp + ...  Structs
1003    are passed by reference.  64 bit quantities (doubles and long longs)
1004    may be split between the regs and the stack.  When calling a function
1005    that returns a struct, a pointer to the struct is passed in as a secret
1006    first argument (always in R6).
1007
1008    Stack space for the args has NOT been allocated: that job is up to us.  */
1009
1010 static CORE_ADDR
1011 v850_push_dummy_call (struct gdbarch *gdbarch,
1012                       struct value *function,
1013                       struct regcache *regcache,
1014                       CORE_ADDR bp_addr,
1015                       int nargs,
1016                       struct value **args,
1017                       CORE_ADDR sp,
1018                       int struct_return,
1019                       CORE_ADDR struct_addr)
1020 {
1021   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1022   int argreg;
1023   int argnum;
1024   int len = 0;
1025   int stack_offset;
1026
1027   if (gdbarch_tdep (gdbarch)->abi == V850_ABI_RH850)
1028     stack_offset = 0;
1029   else
1030   /* The offset onto the stack at which we will start copying parameters
1031      (after the registers are used up) begins at 16 rather than at zero.
1032      That's how the ABI is defined, though there's no indication that these
1033      16 bytes are used for anything, not even for saving incoming
1034      argument registers.  */
1035   stack_offset = 16;
1036
1037   /* Now make space on the stack for the args.  */
1038   for (argnum = 0; argnum < nargs; argnum++)
1039     len += ((TYPE_LENGTH (value_type (args[argnum])) + 3) & ~3);
1040   sp -= len + stack_offset;
1041
1042   argreg = E_ARG0_REGNUM;
1043   /* The struct_return pointer occupies the first parameter register.  */
1044   if (struct_return)
1045     regcache_cooked_write_unsigned (regcache, argreg++, struct_addr);
1046
1047   /* Now load as many as possible of the first arguments into
1048      registers, and push the rest onto the stack.  There are 16 bytes
1049      in four registers available.  Loop thru args from first to last.  */
1050   for (argnum = 0; argnum < nargs; argnum++)
1051     {
1052       int len;
1053       gdb_byte *val;
1054       gdb_byte valbuf[v850_reg_size];
1055
1056       if (!v850_type_is_scalar (value_type (*args))
1057          && gdbarch_tdep (gdbarch)->abi == V850_ABI_GCC
1058           && TYPE_LENGTH (value_type (*args)) > E_MAX_RETTYPE_SIZE_IN_REGS)
1059         {
1060           store_unsigned_integer (valbuf, 4, byte_order,
1061                                   value_address (*args));
1062           len = 4;
1063           val = valbuf;
1064         }
1065       else
1066         {
1067           len = TYPE_LENGTH (value_type (*args));
1068           val = (gdb_byte *) value_contents (*args);
1069         }
1070
1071       if (gdbarch_tdep (gdbarch)->eight_byte_align
1072           && v850_eight_byte_align_p (value_type (*args)))
1073         {
1074           if (argreg <= E_ARGLAST_REGNUM && (argreg & 1))
1075             argreg++;
1076           else if (stack_offset & 0x4)
1077             stack_offset += 4;
1078         }
1079
1080       while (len > 0)
1081         if (argreg <= E_ARGLAST_REGNUM)
1082           {
1083             CORE_ADDR regval;
1084
1085             regval = extract_unsigned_integer (val, v850_reg_size, byte_order);
1086             regcache_cooked_write_unsigned (regcache, argreg, regval);
1087
1088             len -= v850_reg_size;
1089             val += v850_reg_size;
1090             argreg++;
1091           }
1092         else
1093           {
1094             write_memory (sp + stack_offset, val, 4);
1095
1096             len -= 4;
1097             val += 4;
1098             stack_offset += 4;
1099           }
1100       args++;
1101     }
1102
1103   /* Store return address.  */
1104   regcache_cooked_write_unsigned (regcache, E_LP_REGNUM, bp_addr);
1105
1106   /* Update stack pointer.  */
1107   regcache_cooked_write_unsigned (regcache, E_SP_REGNUM, sp);
1108
1109   return sp;
1110 }
1111
1112 static void
1113 v850_extract_return_value (struct type *type, struct regcache *regcache,
1114                            gdb_byte *valbuf)
1115 {
1116   struct gdbarch *gdbarch = get_regcache_arch (regcache);
1117   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1118   int len = TYPE_LENGTH (type);
1119
1120   if (len <= v850_reg_size)
1121     {
1122       ULONGEST val;
1123
1124       regcache_cooked_read_unsigned (regcache, E_V0_REGNUM, &val);
1125       store_unsigned_integer (valbuf, len, byte_order, val);
1126     }
1127   else if (len <= 2 * v850_reg_size)
1128     {
1129       int i, regnum = E_V0_REGNUM;
1130       gdb_byte buf[v850_reg_size];
1131       for (i = 0; len > 0; i += 4, len -= 4)
1132         {
1133           regcache_raw_read (regcache, regnum++, buf);
1134           memcpy (valbuf + i, buf, len > 4 ? 4 : len);
1135         }
1136     }
1137 }
1138
1139 static void
1140 v850_store_return_value (struct type *type, struct regcache *regcache,
1141                          const gdb_byte *valbuf)
1142 {
1143   struct gdbarch *gdbarch = get_regcache_arch (regcache);
1144   enum bfd_endian byte_order = gdbarch_byte_order (gdbarch);
1145   int len = TYPE_LENGTH (type);
1146
1147   if (len <= v850_reg_size)
1148       regcache_cooked_write_unsigned
1149         (regcache, E_V0_REGNUM,
1150          extract_unsigned_integer (valbuf, len, byte_order));
1151   else if (len <= 2 * v850_reg_size)
1152     {
1153       int i, regnum = E_V0_REGNUM;
1154       for (i = 0; i < len; i += 4)
1155         regcache_raw_write (regcache, regnum++, valbuf + i);
1156     }
1157 }
1158
1159 static enum return_value_convention
1160 v850_return_value (struct gdbarch *gdbarch, struct value *function,
1161                    struct type *type, struct regcache *regcache,
1162                    gdb_byte *readbuf, const gdb_byte *writebuf)
1163 {
1164   if (v850_use_struct_convention (gdbarch, type))
1165     return RETURN_VALUE_STRUCT_CONVENTION;
1166   if (writebuf)
1167     v850_store_return_value (type, regcache, writebuf);
1168   else if (readbuf)
1169     v850_extract_return_value (type, regcache, readbuf);
1170   return RETURN_VALUE_REGISTER_CONVENTION;
1171 }
1172
1173 static const unsigned char *
1174 v850_breakpoint_from_pc (struct gdbarch *gdbarch, CORE_ADDR *pcptr,
1175                          int *lenptr)
1176 {
1177   static unsigned char breakpoint[] = { 0x85, 0x05 };
1178
1179   *lenptr = sizeof (breakpoint);
1180   return breakpoint;
1181 }
1182
1183 /* Implement software breakpoints by using the dbtrap instruction.
1184    Older architectures had no such instruction.  For those, an
1185    unconditional branch to self instruction is used.  */
1186
1187 static const unsigned char *
1188 v850_dbtrap_breakpoint_from_pc (struct gdbarch *gdbarch,
1189                                 CORE_ADDR *pcptr, int *lenptr)
1190 {
1191   static unsigned char breakpoint[] = { 0x40, 0xf8 };
1192
1193   *lenptr = sizeof (breakpoint);
1194   return breakpoint;
1195 }
1196
1197 static struct v850_frame_cache *
1198 v850_alloc_frame_cache (struct frame_info *this_frame)
1199 {
1200   struct v850_frame_cache *cache;
1201
1202   cache = FRAME_OBSTACK_ZALLOC (struct v850_frame_cache);
1203   cache->saved_regs = trad_frame_alloc_saved_regs (this_frame);
1204
1205   /* Base address.  */
1206   cache->base = 0;
1207   cache->sp_offset = 0;
1208   cache->pc = 0;
1209
1210   /* Frameless until proven otherwise.  */
1211   cache->uses_fp = 0;
1212
1213   return cache;
1214 }
1215
1216 static struct v850_frame_cache *
1217 v850_frame_cache (struct frame_info *this_frame, void **this_cache)
1218 {
1219   struct gdbarch *gdbarch = get_frame_arch (this_frame);
1220   struct v850_frame_cache *cache;
1221   CORE_ADDR current_pc;
1222   int i;
1223
1224   if (*this_cache)
1225     return *this_cache;
1226
1227   cache = v850_alloc_frame_cache (this_frame);
1228   *this_cache = cache;
1229
1230   /* In principle, for normal frames, fp holds the frame pointer,
1231      which holds the base address for the current stack frame.
1232      However, for functions that don't need it, the frame pointer is
1233      optional.  For these "frameless" functions the frame pointer is
1234      actually the frame pointer of the calling frame.  */
1235   cache->base = get_frame_register_unsigned (this_frame, E_FP_REGNUM);
1236   if (cache->base == 0)
1237     return cache;
1238
1239   cache->pc = get_frame_func (this_frame);
1240   current_pc = get_frame_pc (this_frame);
1241   if (cache->pc != 0)
1242     {
1243       ULONGEST ctbp;
1244       ctbp = get_frame_register_unsigned (this_frame, E_CTBP_REGNUM);
1245       v850_analyze_prologue (gdbarch, cache->pc, current_pc, cache, ctbp);
1246     }
1247
1248   if (!cache->uses_fp)
1249     {
1250       /* We didn't find a valid frame, which means that CACHE->base
1251          currently holds the frame pointer for our calling frame.  If
1252          we're at the start of a function, or somewhere half-way its
1253          prologue, the function's frame probably hasn't been fully
1254          setup yet.  Try to reconstruct the base address for the stack
1255          frame by looking at the stack pointer.  For truly "frameless"
1256          functions this might work too.  */
1257       cache->base = get_frame_register_unsigned (this_frame, E_SP_REGNUM);
1258     }
1259
1260   /* Now that we have the base address for the stack frame we can
1261      calculate the value of sp in the calling frame.  */
1262   trad_frame_set_value (cache->saved_regs, E_SP_REGNUM,
1263                         cache->base - cache->sp_offset);
1264
1265   /* Adjust all the saved registers such that they contain addresses
1266      instead of offsets.  */
1267   for (i = 0; i < gdbarch_num_regs (gdbarch); i++)
1268     if (trad_frame_addr_p (cache->saved_regs, i))
1269       cache->saved_regs[i].addr += cache->base;
1270
1271   /* The call instruction moves the caller's PC in the callee's LP.
1272      Since this is an unwind, do the reverse.  Copy the location of LP
1273      into PC (the address / regnum) so that a request for PC will be
1274      converted into a request for the LP.  */
1275
1276   cache->saved_regs[E_PC_REGNUM] = cache->saved_regs[E_LP_REGNUM];
1277
1278   return cache;
1279 }
1280
1281
1282 static struct value *
1283 v850_frame_prev_register (struct frame_info *this_frame,
1284                           void **this_cache, int regnum)
1285 {
1286   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
1287
1288   gdb_assert (regnum >= 0);
1289
1290   return trad_frame_get_prev_register (this_frame, cache->saved_regs, regnum);
1291 }
1292
1293 static void
1294 v850_frame_this_id (struct frame_info *this_frame, void **this_cache,
1295                     struct frame_id *this_id)
1296 {
1297   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
1298
1299   /* This marks the outermost frame.  */
1300   if (cache->base == 0)
1301     return;
1302
1303   *this_id = frame_id_build (cache->saved_regs[E_SP_REGNUM].addr, cache->pc);
1304 }
1305
1306 static const struct frame_unwind v850_frame_unwind = {
1307   NORMAL_FRAME,
1308   default_frame_unwind_stop_reason,
1309   v850_frame_this_id,
1310   v850_frame_prev_register,
1311   NULL,
1312   default_frame_sniffer
1313 };
1314
1315 static CORE_ADDR
1316 v850_unwind_sp (struct gdbarch *gdbarch, struct frame_info *next_frame)
1317 {
1318   return frame_unwind_register_unsigned (next_frame,
1319                                          gdbarch_sp_regnum (gdbarch));
1320 }
1321
1322 static CORE_ADDR
1323 v850_unwind_pc (struct gdbarch *gdbarch, struct frame_info *next_frame)
1324 {
1325   return frame_unwind_register_unsigned (next_frame,
1326                                          gdbarch_pc_regnum (gdbarch));
1327 }
1328
1329 static struct frame_id
1330 v850_dummy_id (struct gdbarch *gdbarch, struct frame_info *this_frame)
1331 {
1332   CORE_ADDR sp = get_frame_register_unsigned (this_frame,
1333                                               gdbarch_sp_regnum (gdbarch));
1334   return frame_id_build (sp, get_frame_pc (this_frame));
1335 }
1336
1337 static CORE_ADDR
1338 v850_frame_base_address (struct frame_info *this_frame, void **this_cache)
1339 {
1340   struct v850_frame_cache *cache = v850_frame_cache (this_frame, this_cache);
1341
1342   return cache->base;
1343 }
1344
1345 static const struct frame_base v850_frame_base = {
1346   &v850_frame_unwind,
1347   v850_frame_base_address,
1348   v850_frame_base_address,
1349   v850_frame_base_address
1350 };
1351
1352 static struct gdbarch *
1353 v850_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
1354 {
1355   struct gdbarch *gdbarch;
1356   struct gdbarch_tdep *tdep;
1357   int e_flags, e_machine;
1358
1359   /* Extract the elf_flags if available.  */
1360   if (info.abfd != NULL
1361       && bfd_get_flavour (info.abfd) == bfd_target_elf_flavour)
1362     {
1363       e_flags = elf_elfheader (info.abfd)->e_flags;
1364       e_machine = elf_elfheader (info.abfd)->e_machine;
1365     }
1366   else
1367     {
1368       e_flags = 0;
1369       e_machine = 0;
1370     }
1371
1372
1373   /* Try to find the architecture in the list of already defined
1374      architectures.  */
1375   for (arches = gdbarch_list_lookup_by_info (arches, &info);
1376        arches != NULL;
1377        arches = gdbarch_list_lookup_by_info (arches->next, &info))
1378     {
1379       if (gdbarch_tdep (arches->gdbarch)->e_flags != e_flags
1380           || gdbarch_tdep (arches->gdbarch)->e_machine != e_machine)
1381         continue;
1382
1383       return arches->gdbarch;
1384     }
1385   tdep = (struct gdbarch_tdep *) xmalloc (sizeof (struct gdbarch_tdep));
1386   tdep->e_flags = e_flags;
1387   tdep->e_machine = e_machine;
1388
1389   switch (tdep->e_machine)
1390     {
1391     case EM_V800:
1392       tdep->abi = V850_ABI_RH850;
1393       break;
1394     default:
1395       tdep->abi = V850_ABI_GCC;
1396       break;
1397     }
1398
1399   tdep->eight_byte_align = (tdep->e_flags & EF_RH850_DATA_ALIGN8) ? 1 : 0;
1400   gdbarch = gdbarch_alloc (&info, tdep);
1401
1402   switch (info.bfd_arch_info->mach)
1403     {
1404     case bfd_mach_v850:
1405       set_gdbarch_register_name (gdbarch, v850_register_name);
1406       set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850_REGS);
1407       break;
1408     case bfd_mach_v850e:
1409     case bfd_mach_v850e1:
1410       set_gdbarch_register_name (gdbarch, v850e_register_name);
1411       set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E_REGS);
1412       break;
1413     case bfd_mach_v850e2:
1414     case bfd_mach_v850e2v3:
1415       set_gdbarch_register_name (gdbarch, v850e2_register_name);
1416       set_gdbarch_num_regs (gdbarch, E_NUM_REGS);
1417       break;
1418     case bfd_mach_v850e3v5:
1419       set_gdbarch_register_name (gdbarch, v850e3v5_register_name);
1420       set_gdbarch_num_regs (gdbarch, E_NUM_OF_V850E3V5_REGS);
1421       break;
1422     }
1423
1424   set_gdbarch_num_pseudo_regs (gdbarch, 0);
1425   set_gdbarch_sp_regnum (gdbarch, E_SP_REGNUM);
1426   set_gdbarch_pc_regnum (gdbarch, E_PC_REGNUM);
1427   set_gdbarch_fp0_regnum (gdbarch, -1);
1428
1429   set_gdbarch_register_type (gdbarch, v850_register_type);
1430
1431   set_gdbarch_char_signed (gdbarch, 1);
1432   set_gdbarch_short_bit (gdbarch, 2 * TARGET_CHAR_BIT);
1433   set_gdbarch_int_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1434   set_gdbarch_long_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1435   set_gdbarch_long_long_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1436
1437   set_gdbarch_float_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1438   set_gdbarch_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1439   set_gdbarch_long_double_bit (gdbarch, 8 * TARGET_CHAR_BIT);
1440
1441   set_gdbarch_ptr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1442   set_gdbarch_addr_bit (gdbarch, 4 * TARGET_CHAR_BIT);
1443
1444   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
1445   switch (info.bfd_arch_info->mach)
1446     {
1447     case bfd_mach_v850e2:
1448     case bfd_mach_v850e2v3:
1449     case bfd_mach_v850e3v5:
1450       set_gdbarch_breakpoint_from_pc (gdbarch, v850_dbtrap_breakpoint_from_pc);
1451       break;
1452     default:
1453       set_gdbarch_breakpoint_from_pc (gdbarch, v850_breakpoint_from_pc);
1454       break;
1455     }
1456
1457   set_gdbarch_return_value (gdbarch, v850_return_value);
1458   set_gdbarch_push_dummy_call (gdbarch, v850_push_dummy_call);
1459   set_gdbarch_skip_prologue (gdbarch, v850_skip_prologue);
1460
1461   set_gdbarch_print_insn (gdbarch, print_insn_v850);
1462
1463   set_gdbarch_frame_align (gdbarch, v850_frame_align);
1464   set_gdbarch_unwind_sp (gdbarch, v850_unwind_sp);
1465   set_gdbarch_unwind_pc (gdbarch, v850_unwind_pc);
1466   set_gdbarch_dummy_id (gdbarch, v850_dummy_id);
1467   frame_base_set_default (gdbarch, &v850_frame_base);
1468
1469   /* Hook in ABI-specific overrides, if they have been registered.  */
1470   gdbarch_init_osabi (info, gdbarch);
1471
1472   dwarf2_append_unwinders (gdbarch);
1473   frame_unwind_append_unwinder (gdbarch, &v850_frame_unwind);
1474
1475   return gdbarch;
1476 }
1477
1478 extern initialize_file_ftype _initialize_v850_tdep; /* -Wmissing-prototypes */
1479
1480 void
1481 _initialize_v850_tdep (void)
1482 {
1483   register_gdbarch_init (bfd_arch_v850, v850_gdbarch_init);
1484   register_gdbarch_init (bfd_arch_v850_rh850, v850_gdbarch_init);
1485 }