opcodes/bpf-desc.c

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data for bpf.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2023 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include <stdlib.h>
  30 #include "ansidecl.h"
  31 #include "bfd.h"
  32 #include "symcat.h"
  33 #include "bpf-desc.h"
  34 #include "bpf-opc.h"
  35 #include "opintl.h"
  36 #include "libiberty.h"
  37 #include "xregex.h"
  38
  39 /* Attributes.  */
  40
  41 static const CGEN_ATTR_ENTRY bool_attr[] =
  42 {
  43   { "#f", 0 },
  44   { "#t", 1 },
  45   { 0, 0 }
  46 };
  47
  48 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  49 {
  50   { "base", MACH_BASE },
  51   { "bpf", MACH_BPF },
  52   { "xbpf", MACH_XBPF },
  53   { "max", MACH_MAX },
  54   { 0, 0 }
  55 };
  56
  57 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  58 {
  59   { "ebpfle", ISA_EBPFLE },
  60   { "ebpfbe", ISA_EBPFBE },
  61   { "xbpfle", ISA_XBPFLE },
  62   { "xbpfbe", ISA_XBPFBE },
  63   { "max", ISA_MAX },
  64   { 0, 0 }
  65 };
  66
  67 const CGEN_ATTR_TABLE bpf_cgen_ifield_attr_table[] =
  68 {
  69   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  70   { "ISA", & ISA_attr[0], & ISA_attr[0] },
  71   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  72   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  73   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  74   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  75   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  76   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  77   { 0, 0, 0 }
  78 };
  79
  80 const CGEN_ATTR_TABLE bpf_cgen_hardware_attr_table[] =
  81 {
  82   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  83   { "ISA", & ISA_attr[0], & ISA_attr[0] },
  84   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  85   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  86   { "PC", &bool_attr[0], &bool_attr[0] },
  87   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  88   { 0, 0, 0 }
  89 };
  90
  91 const CGEN_ATTR_TABLE bpf_cgen_operand_attr_table[] =
  92 {
  93   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  94   { "ISA", & ISA_attr[0], & ISA_attr[0] },
  95   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  96   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  97   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  98   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  99   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 100   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 101   { "RELAX", &bool_attr[0], &bool_attr[0] },
 102   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 103   { 0, 0, 0 }
 104 };
 105
 106 const CGEN_ATTR_TABLE bpf_cgen_insn_attr_table[] =
 107 {
 108   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 109   { "ISA", & ISA_attr[0], & ISA_attr[0] },
 110   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 111   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 112   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 113   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 114   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 115   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 116   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 117   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 118   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 119   { "PBB", &bool_attr[0], &bool_attr[0] },
 120   { 0, 0, 0 }
 121 };
 122
 123 /* Instruction set variants.  */
 124
 125 static const CGEN_ISA bpf_cgen_isa_table[] = {
 126   { "ebpfle", 64, 64, 64, 128 },
 127   { "ebpfbe", 64, 64, 64, 128 },
 128   { "xbpfle", 64, 64, 64, 128 },
 129   { "xbpfbe", 64, 64, 64, 128 },
 130   { 0, 0, 0, 0, 0 }
 131 };
 132
 133 /* Machine variants.  */
 134
 135 static const CGEN_MACH bpf_cgen_mach_table[] = {
 136   { "bpf", "bpf", MACH_BPF, 0 },
 137   { "xbpf", "xbpf", MACH_XBPF, 0 },
 138   { 0, 0, 0, 0 }
 139 };
 140
 141 static CGEN_KEYWORD_ENTRY bpf_cgen_opval_h_gpr_entries[] =
 142 {
 143   { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 144   { "%r1", 1, {0, {{{0, 0}}}}, 0, 0 },
 145   { "%r2", 2, {0, {{{0, 0}}}}, 0, 0 },
 146   { "%r3", 3, {0, {{{0, 0}}}}, 0, 0 },
 147   { "%r4", 4, {0, {{{0, 0}}}}, 0, 0 },
 148   { "%r5", 5, {0, {{{0, 0}}}}, 0, 0 },
 149   { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
 150   { "%r7", 7, {0, {{{0, 0}}}}, 0, 0 },
 151   { "%r8", 8, {0, {{{0, 0}}}}, 0, 0 },
 152   { "%r9", 9, {0, {{{0, 0}}}}, 0, 0 },
 153   { "%fp", 10, {0, {{{0, 0}}}}, 0, 0 },
 154   { "%r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 155   { "%r6", 6, {0, {{{0, 0}}}}, 0, 0 },
 156   { "%r10", 10, {0, {{{0, 0}}}}, 0, 0 }
 157 };
 158
 159 CGEN_KEYWORD bpf_cgen_opval_h_gpr =
 160 {
 161   & bpf_cgen_opval_h_gpr_entries[0],
 162   14,
 163   0, 0, 0, 0, ""
 164 };
 165
 166
 167 /* The hardware table.  */
 168
 169 #define A(a) (1 << CGEN_HW_##a)
 170
 171 const CGEN_HW_ENTRY bpf_cgen_hw_table[] =
 172 {
 173   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
 174   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
 175   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
 176   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
 177   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
 178   { "h-gpr", HW_H_GPR, CGEN_ASM_KEYWORD, & bpf_cgen_opval_h_gpr, { 0, { { { (1<<MACH_BPF)|(1<<MACH_XBPF), 0 } }, { { 1, "\xf0" } } } } },
 179   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
 180   { "h-sint64", HW_H_SINT64, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } } },
 181   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 182 };
 183
 184 #undef A
 185
 186
 187 /* The instruction field table.  */
 188
 189 #define A(a) (1 << CGEN_IFLD_##a)
 190
 191 const CGEN_IFLD bpf_cgen_ifld_table[] =
 192 {
 193   { BPF_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 194   { BPF_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 195   { BPF_F_OP_CODE, "f-op-code", 0, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 196   { BPF_F_OP_SRC, "f-op-src", 0, 8, 3, 1, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 197   { BPF_F_OP_CLASS, "f-op-class", 0, 8, 2, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 198   { BPF_F_OP_MODE, "f-op-mode", 0, 8, 7, 3, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 199   { BPF_F_OP_SIZE, "f-op-size", 0, 8, 4, 2, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 200   { BPF_F_DSTLE, "f-dstle", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }  },
 201   { BPF_F_SRCLE, "f-srcle", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }  },
 202   { BPF_F_DSTBE, "f-dstbe", 8, 8, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }  },
 203   { BPF_F_SRCBE, "f-srcbe", 8, 8, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }  },
 204   { BPF_F_REGS, "f-regs", 8, 8, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 205   { BPF_F_OFFSET16, "f-offset16", 16, 16, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 206   { BPF_F_IMM32, "f-imm32", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 207   { BPF_F_IMM64_A, "f-imm64-a", 32, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 208   { BPF_F_IMM64_B, "f-imm64-b", 64, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 209   { BPF_F_IMM64_C, "f-imm64-c", 96, 32, 31, 32, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 210   { BPF_F_IMM64, "f-imm64", 0, 0, 0, 0,{ 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 211   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 212 };
 213
 214 #undef A
 215
 216
 217
 218 /* multi ifield declarations */
 219
 220 const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [];
 221
 222
 223 /* multi ifield definitions */
 224
 225 const CGEN_MAYBE_MULTI_IFLD BPF_F_IMM64_MULTI_IFIELD [] =
 226 {
 227     { 0, { &bpf_cgen_ifld_table[BPF_F_IMM64_A] } },
 228     { 0, { &bpf_cgen_ifld_table[BPF_F_IMM64_B] } },
 229     { 0, { &bpf_cgen_ifld_table[BPF_F_IMM64_C] } },
 230     { 0, { 0 } }
 231 };
 232
 233 /* The operand table.  */
 234
 235 #define A(a) (1 << CGEN_OPERAND_##a)
 236 #define OPERAND(op) BPF_OPERAND_##op
 237
 238 const CGEN_OPERAND bpf_cgen_operand_table[] =
 239 {
 240 /* pc: program counter */
 241   { "pc", BPF_OPERAND_PC, HW_H_PC, 0, 0,
 242     { 0, { &bpf_cgen_ifld_table[BPF_F_NIL] } },
 243     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 244 /* dstle: destination register */
 245   { "dstle", BPF_OPERAND_DSTLE, HW_H_GPR, 3, 4,
 246     { 0, { &bpf_cgen_ifld_table[BPF_F_DSTLE] } },
 247     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }  },
 248 /* srcle: source register */
 249   { "srcle", BPF_OPERAND_SRCLE, HW_H_GPR, 7, 4,
 250     { 0, { &bpf_cgen_ifld_table[BPF_F_SRCLE] } },
 251     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }  },
 252 /* dstbe: destination register */
 253   { "dstbe", BPF_OPERAND_DSTBE, HW_H_GPR, 7, 4,
 254     { 0, { &bpf_cgen_ifld_table[BPF_F_DSTBE] } },
 255     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }  },
 256 /* srcbe: source register */
 257   { "srcbe", BPF_OPERAND_SRCBE, HW_H_GPR, 3, 4,
 258     { 0, { &bpf_cgen_ifld_table[BPF_F_SRCBE] } },
 259     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }  },
 260 /* disp16: 16-bit PC-relative address */
 261   { "disp16", BPF_OPERAND_DISP16, HW_H_SINT, 15, 16,
 262     { 0, { &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
 263     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 264 /* disp32: 32-bit PC-relative address */
 265   { "disp32", BPF_OPERAND_DISP32, HW_H_SINT, 31, 32,
 266     { 0, { &bpf_cgen_ifld_table[BPF_F_IMM32] } },
 267     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 268 /* imm32: 32-bit immediate */
 269   { "imm32", BPF_OPERAND_IMM32, HW_H_SINT, 31, 32,
 270     { 0, { &bpf_cgen_ifld_table[BPF_F_IMM32] } },
 271     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 272 /* offset16: 16-bit offset */
 273   { "offset16", BPF_OPERAND_OFFSET16, HW_H_SINT, 15, 16,
 274     { 0, { &bpf_cgen_ifld_table[BPF_F_OFFSET16] } },
 275     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 276 /* imm64: 64-bit immediate */
 277   { "imm64", BPF_OPERAND_IMM64, HW_H_SINT64, 31, 96,
 278     { 3, { &BPF_F_IMM64_MULTI_IFIELD[0] } },
 279     { 0|A(VIRTUAL), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 280 /* endsize: endianness size immediate: 16, 32 or 64 */
 281   { "endsize", BPF_OPERAND_ENDSIZE, HW_H_UINT, 31, 32,
 282     { 0, { &bpf_cgen_ifld_table[BPF_F_IMM32] } },
 283     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }  },
 284 /* sentinel */
 285   { 0, 0, 0, 0, 0,
 286     { 0, { 0 } },
 287     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } }
 288 };
 289
 290 #undef A
 291
 292
 293 /* The instruction table.  */
 294
 295 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 296 #define A(a) (1 << CGEN_INSN_##a)
 297
 298 static const CGEN_IBASE bpf_cgen_insn_table[MAX_INSNS] =
 299 {
 300   /* Special null first entry.
 301      A `num' value of zero is thus invalid.
 302      Also, the special `invalid' insn resides here.  */
 303   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x80" } } } } },
 304 /* add $dstle,$imm32 */
 305   {
 306     BPF_INSN_ADDILE, "addile", "add", 64,
 307     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 308   },
 309 /* add $dstle,$srcle */
 310   {
 311     BPF_INSN_ADDRLE, "addrle", "add", 64,
 312     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 313   },
 314 /* add32 $dstle,$imm32 */
 315   {
 316     BPF_INSN_ADD32ILE, "add32ile", "add32", 64,
 317     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 318   },
 319 /* add32 $dstle,$srcle */
 320   {
 321     BPF_INSN_ADD32RLE, "add32rle", "add32", 64,
 322     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 323   },
 324 /* sub $dstle,$imm32 */
 325   {
 326     BPF_INSN_SUBILE, "subile", "sub", 64,
 327     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 328   },
 329 /* sub $dstle,$srcle */
 330   {
 331     BPF_INSN_SUBRLE, "subrle", "sub", 64,
 332     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 333   },
 334 /* sub32 $dstle,$imm32 */
 335   {
 336     BPF_INSN_SUB32ILE, "sub32ile", "sub32", 64,
 337     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 338   },
 339 /* sub32 $dstle,$srcle */
 340   {
 341     BPF_INSN_SUB32RLE, "sub32rle", "sub32", 64,
 342     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 343   },
 344 /* mul $dstle,$imm32 */
 345   {
 346     BPF_INSN_MULILE, "mulile", "mul", 64,
 347     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 348   },
 349 /* mul $dstle,$srcle */
 350   {
 351     BPF_INSN_MULRLE, "mulrle", "mul", 64,
 352     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 353   },
 354 /* mul32 $dstle,$imm32 */
 355   {
 356     BPF_INSN_MUL32ILE, "mul32ile", "mul32", 64,
 357     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 358   },
 359 /* mul32 $dstle,$srcle */
 360   {
 361     BPF_INSN_MUL32RLE, "mul32rle", "mul32", 64,
 362     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 363   },
 364 /* div $dstle,$imm32 */
 365   {
 366     BPF_INSN_DIVILE, "divile", "div", 64,
 367     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 368   },
 369 /* div $dstle,$srcle */
 370   {
 371     BPF_INSN_DIVRLE, "divrle", "div", 64,
 372     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 373   },
 374 /* div32 $dstle,$imm32 */
 375   {
 376     BPF_INSN_DIV32ILE, "div32ile", "div32", 64,
 377     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 378   },
 379 /* div32 $dstle,$srcle */
 380   {
 381     BPF_INSN_DIV32RLE, "div32rle", "div32", 64,
 382     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 383   },
 384 /* or $dstle,$imm32 */
 385   {
 386     BPF_INSN_ORILE, "orile", "or", 64,
 387     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 388   },
 389 /* or $dstle,$srcle */
 390   {
 391     BPF_INSN_ORRLE, "orrle", "or", 64,
 392     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 393   },
 394 /* or32 $dstle,$imm32 */
 395   {
 396     BPF_INSN_OR32ILE, "or32ile", "or32", 64,
 397     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 398   },
 399 /* or32 $dstle,$srcle */
 400   {
 401     BPF_INSN_OR32RLE, "or32rle", "or32", 64,
 402     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 403   },
 404 /* and $dstle,$imm32 */
 405   {
 406     BPF_INSN_ANDILE, "andile", "and", 64,
 407     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 408   },
 409 /* and $dstle,$srcle */
 410   {
 411     BPF_INSN_ANDRLE, "andrle", "and", 64,
 412     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 413   },
 414 /* and32 $dstle,$imm32 */
 415   {
 416     BPF_INSN_AND32ILE, "and32ile", "and32", 64,
 417     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 418   },
 419 /* and32 $dstle,$srcle */
 420   {
 421     BPF_INSN_AND32RLE, "and32rle", "and32", 64,
 422     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 423   },
 424 /* lsh $dstle,$imm32 */
 425   {
 426     BPF_INSN_LSHILE, "lshile", "lsh", 64,
 427     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 428   },
 429 /* lsh $dstle,$srcle */
 430   {
 431     BPF_INSN_LSHRLE, "lshrle", "lsh", 64,
 432     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 433   },
 434 /* lsh32 $dstle,$imm32 */
 435   {
 436     BPF_INSN_LSH32ILE, "lsh32ile", "lsh32", 64,
 437     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 438   },
 439 /* lsh32 $dstle,$srcle */
 440   {
 441     BPF_INSN_LSH32RLE, "lsh32rle", "lsh32", 64,
 442     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 443   },
 444 /* rsh $dstle,$imm32 */
 445   {
 446     BPF_INSN_RSHILE, "rshile", "rsh", 64,
 447     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 448   },
 449 /* rsh $dstle,$srcle */
 450   {
 451     BPF_INSN_RSHRLE, "rshrle", "rsh", 64,
 452     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 453   },
 454 /* rsh32 $dstle,$imm32 */
 455   {
 456     BPF_INSN_RSH32ILE, "rsh32ile", "rsh32", 64,
 457     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 458   },
 459 /* rsh32 $dstle,$srcle */
 460   {
 461     BPF_INSN_RSH32RLE, "rsh32rle", "rsh32", 64,
 462     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 463   },
 464 /* mod $dstle,$imm32 */
 465   {
 466     BPF_INSN_MODILE, "modile", "mod", 64,
 467     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 468   },
 469 /* mod $dstle,$srcle */
 470   {
 471     BPF_INSN_MODRLE, "modrle", "mod", 64,
 472     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 473   },
 474 /* mod32 $dstle,$imm32 */
 475   {
 476     BPF_INSN_MOD32ILE, "mod32ile", "mod32", 64,
 477     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 478   },
 479 /* mod32 $dstle,$srcle */
 480   {
 481     BPF_INSN_MOD32RLE, "mod32rle", "mod32", 64,
 482     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 483   },
 484 /* xor $dstle,$imm32 */
 485   {
 486     BPF_INSN_XORILE, "xorile", "xor", 64,
 487     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 488   },
 489 /* xor $dstle,$srcle */
 490   {
 491     BPF_INSN_XORRLE, "xorrle", "xor", 64,
 492     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 493   },
 494 /* xor32 $dstle,$imm32 */
 495   {
 496     BPF_INSN_XOR32ILE, "xor32ile", "xor32", 64,
 497     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 498   },
 499 /* xor32 $dstle,$srcle */
 500   {
 501     BPF_INSN_XOR32RLE, "xor32rle", "xor32", 64,
 502     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 503   },
 504 /* arsh $dstle,$imm32 */
 505   {
 506     BPF_INSN_ARSHILE, "arshile", "arsh", 64,
 507     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 508   },
 509 /* arsh $dstle,$srcle */
 510   {
 511     BPF_INSN_ARSHRLE, "arshrle", "arsh", 64,
 512     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 513   },
 514 /* arsh32 $dstle,$imm32 */
 515   {
 516     BPF_INSN_ARSH32ILE, "arsh32ile", "arsh32", 64,
 517     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 518   },
 519 /* arsh32 $dstle,$srcle */
 520   {
 521     BPF_INSN_ARSH32RLE, "arsh32rle", "arsh32", 64,
 522     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 523   },
 524 /* sdiv $dstle,$imm32 */
 525   {
 526     BPF_INSN_SDIVILE, "sdivile", "sdiv", 64,
 527     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
 528   },
 529 /* sdiv $dstle,$srcle */
 530   {
 531     BPF_INSN_SDIVRLE, "sdivrle", "sdiv", 64,
 532     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
 533   },
 534 /* sdiv32 $dstle,$imm32 */
 535   {
 536     BPF_INSN_SDIV32ILE, "sdiv32ile", "sdiv32", 64,
 537     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
 538   },
 539 /* sdiv32 $dstle,$srcle */
 540   {
 541     BPF_INSN_SDIV32RLE, "sdiv32rle", "sdiv32", 64,
 542     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
 543   },
 544 /* smod $dstle,$imm32 */
 545   {
 546     BPF_INSN_SMODILE, "smodile", "smod", 64,
 547     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
 548   },
 549 /* smod $dstle,$srcle */
 550   {
 551     BPF_INSN_SMODRLE, "smodrle", "smod", 64,
 552     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
 553   },
 554 /* smod32 $dstle,$imm32 */
 555   {
 556     BPF_INSN_SMOD32ILE, "smod32ile", "smod32", 64,
 557     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
 558   },
 559 /* smod32 $dstle,$srcle */
 560   {
 561     BPF_INSN_SMOD32RLE, "smod32rle", "smod32", 64,
 562     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
 563   },
 564 /* neg $dstle */
 565   {
 566     BPF_INSN_NEGLE, "negle", "neg", 64,
 567     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 568   },
 569 /* neg32 $dstle */
 570   {
 571     BPF_INSN_NEG32LE, "neg32le", "neg32", 64,
 572     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 573   },
 574 /* mov $dstle,$imm32 */
 575   {
 576     BPF_INSN_MOVILE, "movile", "mov", 64,
 577     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 578   },
 579 /* mov $dstle,$srcle */
 580   {
 581     BPF_INSN_MOVRLE, "movrle", "mov", 64,
 582     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 583   },
 584 /* mov32 $dstle,$imm32 */
 585   {
 586     BPF_INSN_MOV32ILE, "mov32ile", "mov32", 64,
 587     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 588   },
 589 /* mov32 $dstle,$srcle */
 590   {
 591     BPF_INSN_MOV32RLE, "mov32rle", "mov32", 64,
 592     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 593   },
 594 /* add $dstbe,$imm32 */
 595   {
 596     BPF_INSN_ADDIBE, "addibe", "add", 64,
 597     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 598   },
 599 /* add $dstbe,$srcbe */
 600   {
 601     BPF_INSN_ADDRBE, "addrbe", "add", 64,
 602     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 603   },
 604 /* add32 $dstbe,$imm32 */
 605   {
 606     BPF_INSN_ADD32IBE, "add32ibe", "add32", 64,
 607     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 608   },
 609 /* add32 $dstbe,$srcbe */
 610   {
 611     BPF_INSN_ADD32RBE, "add32rbe", "add32", 64,
 612     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 613   },
 614 /* sub $dstbe,$imm32 */
 615   {
 616     BPF_INSN_SUBIBE, "subibe", "sub", 64,
 617     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 618   },
 619 /* sub $dstbe,$srcbe */
 620   {
 621     BPF_INSN_SUBRBE, "subrbe", "sub", 64,
 622     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 623   },
 624 /* sub32 $dstbe,$imm32 */
 625   {
 626     BPF_INSN_SUB32IBE, "sub32ibe", "sub32", 64,
 627     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 628   },
 629 /* sub32 $dstbe,$srcbe */
 630   {
 631     BPF_INSN_SUB32RBE, "sub32rbe", "sub32", 64,
 632     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 633   },
 634 /* mul $dstbe,$imm32 */
 635   {
 636     BPF_INSN_MULIBE, "mulibe", "mul", 64,
 637     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 638   },
 639 /* mul $dstbe,$srcbe */
 640   {
 641     BPF_INSN_MULRBE, "mulrbe", "mul", 64,
 642     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 643   },
 644 /* mul32 $dstbe,$imm32 */
 645   {
 646     BPF_INSN_MUL32IBE, "mul32ibe", "mul32", 64,
 647     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 648   },
 649 /* mul32 $dstbe,$srcbe */
 650   {
 651     BPF_INSN_MUL32RBE, "mul32rbe", "mul32", 64,
 652     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 653   },
 654 /* div $dstbe,$imm32 */
 655   {
 656     BPF_INSN_DIVIBE, "divibe", "div", 64,
 657     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 658   },
 659 /* div $dstbe,$srcbe */
 660   {
 661     BPF_INSN_DIVRBE, "divrbe", "div", 64,
 662     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 663   },
 664 /* div32 $dstbe,$imm32 */
 665   {
 666     BPF_INSN_DIV32IBE, "div32ibe", "div32", 64,
 667     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 668   },
 669 /* div32 $dstbe,$srcbe */
 670   {
 671     BPF_INSN_DIV32RBE, "div32rbe", "div32", 64,
 672     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 673   },
 674 /* or $dstbe,$imm32 */
 675   {
 676     BPF_INSN_ORIBE, "oribe", "or", 64,
 677     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 678   },
 679 /* or $dstbe,$srcbe */
 680   {
 681     BPF_INSN_ORRBE, "orrbe", "or", 64,
 682     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 683   },
 684 /* or32 $dstbe,$imm32 */
 685   {
 686     BPF_INSN_OR32IBE, "or32ibe", "or32", 64,
 687     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 688   },
 689 /* or32 $dstbe,$srcbe */
 690   {
 691     BPF_INSN_OR32RBE, "or32rbe", "or32", 64,
 692     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 693   },
 694 /* and $dstbe,$imm32 */
 695   {
 696     BPF_INSN_ANDIBE, "andibe", "and", 64,
 697     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 698   },
 699 /* and $dstbe,$srcbe */
 700   {
 701     BPF_INSN_ANDRBE, "andrbe", "and", 64,
 702     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 703   },
 704 /* and32 $dstbe,$imm32 */
 705   {
 706     BPF_INSN_AND32IBE, "and32ibe", "and32", 64,
 707     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 708   },
 709 /* and32 $dstbe,$srcbe */
 710   {
 711     BPF_INSN_AND32RBE, "and32rbe", "and32", 64,
 712     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 713   },
 714 /* lsh $dstbe,$imm32 */
 715   {
 716     BPF_INSN_LSHIBE, "lshibe", "lsh", 64,
 717     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 718   },
 719 /* lsh $dstbe,$srcbe */
 720   {
 721     BPF_INSN_LSHRBE, "lshrbe", "lsh", 64,
 722     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 723   },
 724 /* lsh32 $dstbe,$imm32 */
 725   {
 726     BPF_INSN_LSH32IBE, "lsh32ibe", "lsh32", 64,
 727     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 728   },
 729 /* lsh32 $dstbe,$srcbe */
 730   {
 731     BPF_INSN_LSH32RBE, "lsh32rbe", "lsh32", 64,
 732     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 733   },
 734 /* rsh $dstbe,$imm32 */
 735   {
 736     BPF_INSN_RSHIBE, "rshibe", "rsh", 64,
 737     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 738   },
 739 /* rsh $dstbe,$srcbe */
 740   {
 741     BPF_INSN_RSHRBE, "rshrbe", "rsh", 64,
 742     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 743   },
 744 /* rsh32 $dstbe,$imm32 */
 745   {
 746     BPF_INSN_RSH32IBE, "rsh32ibe", "rsh32", 64,
 747     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 748   },
 749 /* rsh32 $dstbe,$srcbe */
 750   {
 751     BPF_INSN_RSH32RBE, "rsh32rbe", "rsh32", 64,
 752     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 753   },
 754 /* mod $dstbe,$imm32 */
 755   {
 756     BPF_INSN_MODIBE, "modibe", "mod", 64,
 757     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 758   },
 759 /* mod $dstbe,$srcbe */
 760   {
 761     BPF_INSN_MODRBE, "modrbe", "mod", 64,
 762     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 763   },
 764 /* mod32 $dstbe,$imm32 */
 765   {
 766     BPF_INSN_MOD32IBE, "mod32ibe", "mod32", 64,
 767     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 768   },
 769 /* mod32 $dstbe,$srcbe */
 770   {
 771     BPF_INSN_MOD32RBE, "mod32rbe", "mod32", 64,
 772     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 773   },
 774 /* xor $dstbe,$imm32 */
 775   {
 776     BPF_INSN_XORIBE, "xoribe", "xor", 64,
 777     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 778   },
 779 /* xor $dstbe,$srcbe */
 780   {
 781     BPF_INSN_XORRBE, "xorrbe", "xor", 64,
 782     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 783   },
 784 /* xor32 $dstbe,$imm32 */
 785   {
 786     BPF_INSN_XOR32IBE, "xor32ibe", "xor32", 64,
 787     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 788   },
 789 /* xor32 $dstbe,$srcbe */
 790   {
 791     BPF_INSN_XOR32RBE, "xor32rbe", "xor32", 64,
 792     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 793   },
 794 /* arsh $dstbe,$imm32 */
 795   {
 796     BPF_INSN_ARSHIBE, "arshibe", "arsh", 64,
 797     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 798   },
 799 /* arsh $dstbe,$srcbe */
 800   {
 801     BPF_INSN_ARSHRBE, "arshrbe", "arsh", 64,
 802     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 803   },
 804 /* arsh32 $dstbe,$imm32 */
 805   {
 806     BPF_INSN_ARSH32IBE, "arsh32ibe", "arsh32", 64,
 807     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 808   },
 809 /* arsh32 $dstbe,$srcbe */
 810   {
 811     BPF_INSN_ARSH32RBE, "arsh32rbe", "arsh32", 64,
 812     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 813   },
 814 /* sdiv $dstbe,$imm32 */
 815   {
 816     BPF_INSN_SDIVIBE, "sdivibe", "sdiv", 64,
 817     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
 818   },
 819 /* sdiv $dstbe,$srcbe */
 820   {
 821     BPF_INSN_SDIVRBE, "sdivrbe", "sdiv", 64,
 822     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
 823   },
 824 /* sdiv32 $dstbe,$imm32 */
 825   {
 826     BPF_INSN_SDIV32IBE, "sdiv32ibe", "sdiv32", 64,
 827     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
 828   },
 829 /* sdiv32 $dstbe,$srcbe */
 830   {
 831     BPF_INSN_SDIV32RBE, "sdiv32rbe", "sdiv32", 64,
 832     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
 833   },
 834 /* smod $dstbe,$imm32 */
 835   {
 836     BPF_INSN_SMODIBE, "smodibe", "smod", 64,
 837     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
 838   },
 839 /* smod $dstbe,$srcbe */
 840   {
 841     BPF_INSN_SMODRBE, "smodrbe", "smod", 64,
 842     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
 843   },
 844 /* smod32 $dstbe,$imm32 */
 845   {
 846     BPF_INSN_SMOD32IBE, "smod32ibe", "smod32", 64,
 847     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
 848   },
 849 /* smod32 $dstbe,$srcbe */
 850   {
 851     BPF_INSN_SMOD32RBE, "smod32rbe", "smod32", 64,
 852     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
 853   },
 854 /* neg $dstbe */
 855   {
 856     BPF_INSN_NEGBE, "negbe", "neg", 64,
 857     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 858   },
 859 /* neg32 $dstbe */
 860   {
 861     BPF_INSN_NEG32BE, "neg32be", "neg32", 64,
 862     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 863   },
 864 /* mov $dstbe,$imm32 */
 865   {
 866     BPF_INSN_MOVIBE, "movibe", "mov", 64,
 867     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 868   },
 869 /* mov $dstbe,$srcbe */
 870   {
 871     BPF_INSN_MOVRBE, "movrbe", "mov", 64,
 872     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 873   },
 874 /* mov32 $dstbe,$imm32 */
 875   {
 876     BPF_INSN_MOV32IBE, "mov32ibe", "mov32", 64,
 877     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 878   },
 879 /* mov32 $dstbe,$srcbe */
 880   {
 881     BPF_INSN_MOV32RBE, "mov32rbe", "mov32", 64,
 882     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 883   },
 884 /* endle $dstle,$endsize */
 885   {
 886     BPF_INSN_ENDLELE, "endlele", "endle", 64,
 887     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 888   },
 889 /* endbe $dstle,$endsize */
 890   {
 891     BPF_INSN_ENDBELE, "endbele", "endbe", 64,
 892     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 893   },
 894 /* endle $dstbe,$endsize */
 895   {
 896     BPF_INSN_ENDLEBE, "endlebe", "endle", 64,
 897     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 898   },
 899 /* endbe $dstbe,$endsize */
 900   {
 901     BPF_INSN_ENDBEBE, "endbebe", "endbe", 64,
 902     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 903   },
 904 /* lddw $dstle,$imm64 */
 905   {
 906     BPF_INSN_LDDWLE, "lddwle", "lddw", 128,
 907     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 908   },
 909 /* lddw $dstbe,$imm64 */
 910   {
 911     BPF_INSN_LDDWBE, "lddwbe", "lddw", 128,
 912     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 913   },
 914 /* ldabsw $imm32 */
 915   {
 916     BPF_INSN_LDABSW, "ldabsw", "ldabsw", 64,
 917     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
 918   },
 919 /* ldabsh $imm32 */
 920   {
 921     BPF_INSN_LDABSH, "ldabsh", "ldabsh", 64,
 922     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
 923   },
 924 /* ldabsb $imm32 */
 925   {
 926     BPF_INSN_LDABSB, "ldabsb", "ldabsb", 64,
 927     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
 928   },
 929 /* ldabsdw $imm32 */
 930   {
 931     BPF_INSN_LDABSDW, "ldabsdw", "ldabsdw", 64,
 932     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
 933   },
 934 /* ldindw $srcle,$imm32 */
 935   {
 936     BPF_INSN_LDINDWLE, "ldindwle", "ldindw", 64,
 937     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 938   },
 939 /* ldindh $srcle,$imm32 */
 940   {
 941     BPF_INSN_LDINDHLE, "ldindhle", "ldindh", 64,
 942     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 943   },
 944 /* ldindb $srcle,$imm32 */
 945   {
 946     BPF_INSN_LDINDBLE, "ldindble", "ldindb", 64,
 947     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 948   },
 949 /* ldinddw $srcle,$imm32 */
 950   {
 951     BPF_INSN_LDINDDWLE, "ldinddwle", "ldinddw", 64,
 952     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 953   },
 954 /* ldindw $srcbe,$imm32 */
 955   {
 956     BPF_INSN_LDINDWBE, "ldindwbe", "ldindw", 64,
 957     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 958   },
 959 /* ldindh $srcbe,$imm32 */
 960   {
 961     BPF_INSN_LDINDHBE, "ldindhbe", "ldindh", 64,
 962     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 963   },
 964 /* ldindb $srcbe,$imm32 */
 965   {
 966     BPF_INSN_LDINDBBE, "ldindbbe", "ldindb", 64,
 967     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 968   },
 969 /* ldinddw $srcbe,$imm32 */
 970   {
 971     BPF_INSN_LDINDDWBE, "ldinddwbe", "ldinddw", 64,
 972     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
 973   },
 974 /* ldxw $dstle,[$srcle+$offset16] */
 975   {
 976     BPF_INSN_LDXWLE, "ldxwle", "ldxw", 64,
 977     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 978   },
 979 /* ldxh $dstle,[$srcle+$offset16] */
 980   {
 981     BPF_INSN_LDXHLE, "ldxhle", "ldxh", 64,
 982     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 983   },
 984 /* ldxb $dstle,[$srcle+$offset16] */
 985   {
 986     BPF_INSN_LDXBLE, "ldxble", "ldxb", 64,
 987     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 988   },
 989 /* ldxdw $dstle,[$srcle+$offset16] */
 990   {
 991     BPF_INSN_LDXDWLE, "ldxdwle", "ldxdw", 64,
 992     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 993   },
 994 /* stxw [$dstle+$offset16],$srcle */
 995   {
 996     BPF_INSN_STXWLE, "stxwle", "stxw", 64,
 997     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
 998   },
 999 /* stxh [$dstle+$offset16],$srcle */
1000   {
1001     BPF_INSN_STXHLE, "stxhle", "stxh", 64,
1002     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1003   },
1004 /* stxb [$dstle+$offset16],$srcle */
1005   {
1006     BPF_INSN_STXBLE, "stxble", "stxb", 64,
1007     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1008   },
1009 /* stxdw [$dstle+$offset16],$srcle */
1010   {
1011     BPF_INSN_STXDWLE, "stxdwle", "stxdw", 64,
1012     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1013   },
1014 /* ldxw $dstbe,[$srcbe+$offset16] */
1015   {
1016     BPF_INSN_LDXWBE, "ldxwbe", "ldxw", 64,
1017     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1018   },
1019 /* ldxh $dstbe,[$srcbe+$offset16] */
1020   {
1021     BPF_INSN_LDXHBE, "ldxhbe", "ldxh", 64,
1022     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1023   },
1024 /* ldxb $dstbe,[$srcbe+$offset16] */
1025   {
1026     BPF_INSN_LDXBBE, "ldxbbe", "ldxb", 64,
1027     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1028   },
1029 /* ldxdw $dstbe,[$srcbe+$offset16] */
1030   {
1031     BPF_INSN_LDXDWBE, "ldxdwbe", "ldxdw", 64,
1032     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1033   },
1034 /* stxw [$dstbe+$offset16],$srcbe */
1035   {
1036     BPF_INSN_STXWBE, "stxwbe", "stxw", 64,
1037     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1038   },
1039 /* stxh [$dstbe+$offset16],$srcbe */
1040   {
1041     BPF_INSN_STXHBE, "stxhbe", "stxh", 64,
1042     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1043   },
1044 /* stxb [$dstbe+$offset16],$srcbe */
1045   {
1046     BPF_INSN_STXBBE, "stxbbe", "stxb", 64,
1047     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1048   },
1049 /* stxdw [$dstbe+$offset16],$srcbe */
1050   {
1051     BPF_INSN_STXDWBE, "stxdwbe", "stxdw", 64,
1052     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1053   },
1054 /* stb [$dstle+$offset16],$imm32 */
1055   {
1056     BPF_INSN_STBLE, "stble", "stb", 64,
1057     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1058   },
1059 /* sth [$dstle+$offset16],$imm32 */
1060   {
1061     BPF_INSN_STHLE, "sthle", "sth", 64,
1062     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1063   },
1064 /* stw [$dstle+$offset16],$imm32 */
1065   {
1066     BPF_INSN_STWLE, "stwle", "stw", 64,
1067     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1068   },
1069 /* stdw [$dstle+$offset16],$imm32 */
1070   {
1071     BPF_INSN_STDWLE, "stdwle", "stdw", 64,
1072     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1073   },
1074 /* stb [$dstbe+$offset16],$imm32 */
1075   {
1076     BPF_INSN_STBBE, "stbbe", "stb", 64,
1077     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1078   },
1079 /* sth [$dstbe+$offset16],$imm32 */
1080   {
1081     BPF_INSN_STHBE, "sthbe", "sth", 64,
1082     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1083   },
1084 /* stw [$dstbe+$offset16],$imm32 */
1085   {
1086     BPF_INSN_STWBE, "stwbe", "stw", 64,
1087     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1088   },
1089 /* stdw [$dstbe+$offset16],$imm32 */
1090   {
1091     BPF_INSN_STDWBE, "stdwbe", "stdw", 64,
1092     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1093   },
1094 /* jeq $dstle,$imm32,$disp16 */
1095   {
1096     BPF_INSN_JEQILE, "jeqile", "jeq", 64,
1097     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1098   },
1099 /* jeq $dstle,$srcle,$disp16 */
1100   {
1101     BPF_INSN_JEQRLE, "jeqrle", "jeq", 64,
1102     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1103   },
1104 /* jeq32 $dstle,$imm32,$disp16 */
1105   {
1106     BPF_INSN_JEQ32ILE, "jeq32ile", "jeq32", 64,
1107     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1108   },
1109 /* jeq32 $dstle,$srcle,$disp16 */
1110   {
1111     BPF_INSN_JEQ32RLE, "jeq32rle", "jeq32", 64,
1112     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1113   },
1114 /* jgt $dstle,$imm32,$disp16 */
1115   {
1116     BPF_INSN_JGTILE, "jgtile", "jgt", 64,
1117     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1118   },
1119 /* jgt $dstle,$srcle,$disp16 */
1120   {
1121     BPF_INSN_JGTRLE, "jgtrle", "jgt", 64,
1122     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1123   },
1124 /* jgt32 $dstle,$imm32,$disp16 */
1125   {
1126     BPF_INSN_JGT32ILE, "jgt32ile", "jgt32", 64,
1127     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1128   },
1129 /* jgt32 $dstle,$srcle,$disp16 */
1130   {
1131     BPF_INSN_JGT32RLE, "jgt32rle", "jgt32", 64,
1132     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1133   },
1134 /* jge $dstle,$imm32,$disp16 */
1135   {
1136     BPF_INSN_JGEILE, "jgeile", "jge", 64,
1137     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1138   },
1139 /* jge $dstle,$srcle,$disp16 */
1140   {
1141     BPF_INSN_JGERLE, "jgerle", "jge", 64,
1142     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1143   },
1144 /* jge32 $dstle,$imm32,$disp16 */
1145   {
1146     BPF_INSN_JGE32ILE, "jge32ile", "jge32", 64,
1147     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1148   },
1149 /* jge32 $dstle,$srcle,$disp16 */
1150   {
1151     BPF_INSN_JGE32RLE, "jge32rle", "jge32", 64,
1152     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1153   },
1154 /* jlt $dstle,$imm32,$disp16 */
1155   {
1156     BPF_INSN_JLTILE, "jltile", "jlt", 64,
1157     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1158   },
1159 /* jlt $dstle,$srcle,$disp16 */
1160   {
1161     BPF_INSN_JLTRLE, "jltrle", "jlt", 64,
1162     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1163   },
1164 /* jlt32 $dstle,$imm32,$disp16 */
1165   {
1166     BPF_INSN_JLT32ILE, "jlt32ile", "jlt32", 64,
1167     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1168   },
1169 /* jlt32 $dstle,$srcle,$disp16 */
1170   {
1171     BPF_INSN_JLT32RLE, "jlt32rle", "jlt32", 64,
1172     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1173   },
1174 /* jle $dstle,$imm32,$disp16 */
1175   {
1176     BPF_INSN_JLEILE, "jleile", "jle", 64,
1177     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1178   },
1179 /* jle $dstle,$srcle,$disp16 */
1180   {
1181     BPF_INSN_JLERLE, "jlerle", "jle", 64,
1182     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1183   },
1184 /* jle32 $dstle,$imm32,$disp16 */
1185   {
1186     BPF_INSN_JLE32ILE, "jle32ile", "jle32", 64,
1187     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1188   },
1189 /* jle32 $dstle,$srcle,$disp16 */
1190   {
1191     BPF_INSN_JLE32RLE, "jle32rle", "jle32", 64,
1192     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1193   },
1194 /* jset $dstle,$imm32,$disp16 */
1195   {
1196     BPF_INSN_JSETILE, "jsetile", "jset", 64,
1197     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1198   },
1199 /* jset $dstle,$srcle,$disp16 */
1200   {
1201     BPF_INSN_JSETRLE, "jsetrle", "jset", 64,
1202     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1203   },
1204 /* jset32 $dstle,$imm32,$disp16 */
1205   {
1206     BPF_INSN_JSET32ILE, "jset32ile", "jset32", 64,
1207     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1208   },
1209 /* jset32 $dstle,$srcle,$disp16 */
1210   {
1211     BPF_INSN_JSET32RLE, "jset32rle", "jset32", 64,
1212     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1213   },
1214 /* jne $dstle,$imm32,$disp16 */
1215   {
1216     BPF_INSN_JNEILE, "jneile", "jne", 64,
1217     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1218   },
1219 /* jne $dstle,$srcle,$disp16 */
1220   {
1221     BPF_INSN_JNERLE, "jnerle", "jne", 64,
1222     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1223   },
1224 /* jne32 $dstle,$imm32,$disp16 */
1225   {
1226     BPF_INSN_JNE32ILE, "jne32ile", "jne32", 64,
1227     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1228   },
1229 /* jne32 $dstle,$srcle,$disp16 */
1230   {
1231     BPF_INSN_JNE32RLE, "jne32rle", "jne32", 64,
1232     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1233   },
1234 /* jsgt $dstle,$imm32,$disp16 */
1235   {
1236     BPF_INSN_JSGTILE, "jsgtile", "jsgt", 64,
1237     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1238   },
1239 /* jsgt $dstle,$srcle,$disp16 */
1240   {
1241     BPF_INSN_JSGTRLE, "jsgtrle", "jsgt", 64,
1242     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1243   },
1244 /* jsgt32 $dstle,$imm32,$disp16 */
1245   {
1246     BPF_INSN_JSGT32ILE, "jsgt32ile", "jsgt32", 64,
1247     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1248   },
1249 /* jsgt32 $dstle,$srcle,$disp16 */
1250   {
1251     BPF_INSN_JSGT32RLE, "jsgt32rle", "jsgt32", 64,
1252     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1253   },
1254 /* jsge $dstle,$imm32,$disp16 */
1255   {
1256     BPF_INSN_JSGEILE, "jsgeile", "jsge", 64,
1257     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1258   },
1259 /* jsge $dstle,$srcle,$disp16 */
1260   {
1261     BPF_INSN_JSGERLE, "jsgerle", "jsge", 64,
1262     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1263   },
1264 /* jsge32 $dstle,$imm32,$disp16 */
1265   {
1266     BPF_INSN_JSGE32ILE, "jsge32ile", "jsge32", 64,
1267     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1268   },
1269 /* jsge32 $dstle,$srcle,$disp16 */
1270   {
1271     BPF_INSN_JSGE32RLE, "jsge32rle", "jsge32", 64,
1272     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1273   },
1274 /* jslt $dstle,$imm32,$disp16 */
1275   {
1276     BPF_INSN_JSLTILE, "jsltile", "jslt", 64,
1277     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1278   },
1279 /* jslt $dstle,$srcle,$disp16 */
1280   {
1281     BPF_INSN_JSLTRLE, "jsltrle", "jslt", 64,
1282     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1283   },
1284 /* jslt32 $dstle,$imm32,$disp16 */
1285   {
1286     BPF_INSN_JSLT32ILE, "jslt32ile", "jslt32", 64,
1287     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1288   },
1289 /* jslt32 $dstle,$srcle,$disp16 */
1290   {
1291     BPF_INSN_JSLT32RLE, "jslt32rle", "jslt32", 64,
1292     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1293   },
1294 /* jsle $dstle,$imm32,$disp16 */
1295   {
1296     BPF_INSN_JSLEILE, "jsleile", "jsle", 64,
1297     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1298   },
1299 /* jsle $dstle,$srcle,$disp16 */
1300   {
1301     BPF_INSN_JSLERLE, "jslerle", "jsle", 64,
1302     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1303   },
1304 /* jsle32 $dstle,$imm32,$disp16 */
1305   {
1306     BPF_INSN_JSLE32ILE, "jsle32ile", "jsle32", 64,
1307     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1308   },
1309 /* jsle32 $dstle,$srcle,$disp16 */
1310   {
1311     BPF_INSN_JSLE32RLE, "jsle32rle", "jsle32", 64,
1312     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1313   },
1314 /* jeq $dstbe,$imm32,$disp16 */
1315   {
1316     BPF_INSN_JEQIBE, "jeqibe", "jeq", 64,
1317     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1318   },
1319 /* jeq $dstbe,$srcbe,$disp16 */
1320   {
1321     BPF_INSN_JEQRBE, "jeqrbe", "jeq", 64,
1322     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1323   },
1324 /* jeq32 $dstbe,$imm32,$disp16 */
1325   {
1326     BPF_INSN_JEQ32IBE, "jeq32ibe", "jeq32", 64,
1327     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1328   },
1329 /* jeq32 $dstbe,$srcbe,$disp16 */
1330   {
1331     BPF_INSN_JEQ32RBE, "jeq32rbe", "jeq32", 64,
1332     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1333   },
1334 /* jgt $dstbe,$imm32,$disp16 */
1335   {
1336     BPF_INSN_JGTIBE, "jgtibe", "jgt", 64,
1337     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1338   },
1339 /* jgt $dstbe,$srcbe,$disp16 */
1340   {
1341     BPF_INSN_JGTRBE, "jgtrbe", "jgt", 64,
1342     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1343   },
1344 /* jgt32 $dstbe,$imm32,$disp16 */
1345   {
1346     BPF_INSN_JGT32IBE, "jgt32ibe", "jgt32", 64,
1347     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1348   },
1349 /* jgt32 $dstbe,$srcbe,$disp16 */
1350   {
1351     BPF_INSN_JGT32RBE, "jgt32rbe", "jgt32", 64,
1352     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1353   },
1354 /* jge $dstbe,$imm32,$disp16 */
1355   {
1356     BPF_INSN_JGEIBE, "jgeibe", "jge", 64,
1357     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1358   },
1359 /* jge $dstbe,$srcbe,$disp16 */
1360   {
1361     BPF_INSN_JGERBE, "jgerbe", "jge", 64,
1362     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1363   },
1364 /* jge32 $dstbe,$imm32,$disp16 */
1365   {
1366     BPF_INSN_JGE32IBE, "jge32ibe", "jge32", 64,
1367     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1368   },
1369 /* jge32 $dstbe,$srcbe,$disp16 */
1370   {
1371     BPF_INSN_JGE32RBE, "jge32rbe", "jge32", 64,
1372     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1373   },
1374 /* jlt $dstbe,$imm32,$disp16 */
1375   {
1376     BPF_INSN_JLTIBE, "jltibe", "jlt", 64,
1377     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1378   },
1379 /* jlt $dstbe,$srcbe,$disp16 */
1380   {
1381     BPF_INSN_JLTRBE, "jltrbe", "jlt", 64,
1382     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1383   },
1384 /* jlt32 $dstbe,$imm32,$disp16 */
1385   {
1386     BPF_INSN_JLT32IBE, "jlt32ibe", "jlt32", 64,
1387     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1388   },
1389 /* jlt32 $dstbe,$srcbe,$disp16 */
1390   {
1391     BPF_INSN_JLT32RBE, "jlt32rbe", "jlt32", 64,
1392     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1393   },
1394 /* jle $dstbe,$imm32,$disp16 */
1395   {
1396     BPF_INSN_JLEIBE, "jleibe", "jle", 64,
1397     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1398   },
1399 /* jle $dstbe,$srcbe,$disp16 */
1400   {
1401     BPF_INSN_JLERBE, "jlerbe", "jle", 64,
1402     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1403   },
1404 /* jle32 $dstbe,$imm32,$disp16 */
1405   {
1406     BPF_INSN_JLE32IBE, "jle32ibe", "jle32", 64,
1407     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1408   },
1409 /* jle32 $dstbe,$srcbe,$disp16 */
1410   {
1411     BPF_INSN_JLE32RBE, "jle32rbe", "jle32", 64,
1412     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1413   },
1414 /* jset $dstbe,$imm32,$disp16 */
1415   {
1416     BPF_INSN_JSETIBE, "jsetibe", "jset", 64,
1417     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1418   },
1419 /* jset $dstbe,$srcbe,$disp16 */
1420   {
1421     BPF_INSN_JSETRBE, "jsetrbe", "jset", 64,
1422     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1423   },
1424 /* jset32 $dstbe,$imm32,$disp16 */
1425   {
1426     BPF_INSN_JSET32IBE, "jset32ibe", "jset32", 64,
1427     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1428   },
1429 /* jset32 $dstbe,$srcbe,$disp16 */
1430   {
1431     BPF_INSN_JSET32RBE, "jset32rbe", "jset32", 64,
1432     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1433   },
1434 /* jne $dstbe,$imm32,$disp16 */
1435   {
1436     BPF_INSN_JNEIBE, "jneibe", "jne", 64,
1437     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1438   },
1439 /* jne $dstbe,$srcbe,$disp16 */
1440   {
1441     BPF_INSN_JNERBE, "jnerbe", "jne", 64,
1442     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1443   },
1444 /* jne32 $dstbe,$imm32,$disp16 */
1445   {
1446     BPF_INSN_JNE32IBE, "jne32ibe", "jne32", 64,
1447     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1448   },
1449 /* jne32 $dstbe,$srcbe,$disp16 */
1450   {
1451     BPF_INSN_JNE32RBE, "jne32rbe", "jne32", 64,
1452     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1453   },
1454 /* jsgt $dstbe,$imm32,$disp16 */
1455   {
1456     BPF_INSN_JSGTIBE, "jsgtibe", "jsgt", 64,
1457     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1458   },
1459 /* jsgt $dstbe,$srcbe,$disp16 */
1460   {
1461     BPF_INSN_JSGTRBE, "jsgtrbe", "jsgt", 64,
1462     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1463   },
1464 /* jsgt32 $dstbe,$imm32,$disp16 */
1465   {
1466     BPF_INSN_JSGT32IBE, "jsgt32ibe", "jsgt32", 64,
1467     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1468   },
1469 /* jsgt32 $dstbe,$srcbe,$disp16 */
1470   {
1471     BPF_INSN_JSGT32RBE, "jsgt32rbe", "jsgt32", 64,
1472     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1473   },
1474 /* jsge $dstbe,$imm32,$disp16 */
1475   {
1476     BPF_INSN_JSGEIBE, "jsgeibe", "jsge", 64,
1477     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1478   },
1479 /* jsge $dstbe,$srcbe,$disp16 */
1480   {
1481     BPF_INSN_JSGERBE, "jsgerbe", "jsge", 64,
1482     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1483   },
1484 /* jsge32 $dstbe,$imm32,$disp16 */
1485   {
1486     BPF_INSN_JSGE32IBE, "jsge32ibe", "jsge32", 64,
1487     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1488   },
1489 /* jsge32 $dstbe,$srcbe,$disp16 */
1490   {
1491     BPF_INSN_JSGE32RBE, "jsge32rbe", "jsge32", 64,
1492     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1493   },
1494 /* jslt $dstbe,$imm32,$disp16 */
1495   {
1496     BPF_INSN_JSLTIBE, "jsltibe", "jslt", 64,
1497     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1498   },
1499 /* jslt $dstbe,$srcbe,$disp16 */
1500   {
1501     BPF_INSN_JSLTRBE, "jsltrbe", "jslt", 64,
1502     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1503   },
1504 /* jslt32 $dstbe,$imm32,$disp16 */
1505   {
1506     BPF_INSN_JSLT32IBE, "jslt32ibe", "jslt32", 64,
1507     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1508   },
1509 /* jslt32 $dstbe,$srcbe,$disp16 */
1510   {
1511     BPF_INSN_JSLT32RBE, "jslt32rbe", "jslt32", 64,
1512     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1513   },
1514 /* jsle $dstbe,$imm32,$disp16 */
1515   {
1516     BPF_INSN_JSLEIBE, "jsleibe", "jsle", 64,
1517     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1518   },
1519 /* jsle $dstbe,$srcbe,$disp16 */
1520   {
1521     BPF_INSN_JSLERBE, "jslerbe", "jsle", 64,
1522     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1523   },
1524 /* jsle32 $dstbe,$imm32,$disp16 */
1525   {
1526     BPF_INSN_JSLE32IBE, "jsle32ibe", "jsle32", 64,
1527     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1528   },
1529 /* jsle32 $dstbe,$srcbe,$disp16 */
1530   {
1531     BPF_INSN_JSLE32RBE, "jsle32rbe", "jsle32", 64,
1532     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1533   },
1534 /* call $disp32 */
1535   {
1536     BPF_INSN_CALLLE, "callle", "call", 64,
1537     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1538   },
1539 /* call $disp32 */
1540   {
1541     BPF_INSN_CALLBE, "callbe", "call", 64,
1542     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1543   },
1544 /* call $dstle */
1545   {
1546     BPF_INSN_CALLRLE, "callrle", "call", 64,
1547     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x20" } } } }
1548   },
1549 /* call $dstbe */
1550   {
1551     BPF_INSN_CALLRBE, "callrbe", "call", 64,
1552     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x10" } } } }
1553   },
1554 /* ja $disp16 */
1555   {
1556     BPF_INSN_JA, "ja", "ja", 64,
1557     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
1558   },
1559 /* exit */
1560   {
1561     BPF_INSN_EXIT, "exit", "exit", 64,
1562     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
1563   },
1564 /* xadddw [$dstle+$offset16],$srcle */
1565   {
1566     BPF_INSN_XADDDWLE, "xadddwle", "xadddw", 64,
1567     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1568   },
1569 /* xaddw [$dstle+$offset16],$srcle */
1570   {
1571     BPF_INSN_XADDWLE, "xaddwle", "xaddw", 64,
1572     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xa0" } } } }
1573   },
1574 /* xadddw [$dstbe+$offset16],$srcbe */
1575   {
1576     BPF_INSN_XADDDWBE, "xadddwbe", "xadddw", 64,
1577     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1578   },
1579 /* xaddw [$dstbe+$offset16],$srcbe */
1580   {
1581     BPF_INSN_XADDWBE, "xaddwbe", "xaddw", 64,
1582     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\x50" } } } }
1583   },
1584 /* brkpt */
1585   {
1586     BPF_INSN_BRKPT, "brkpt", "brkpt", 64,
1587     { 0, { { { (1<<MACH_BASE), 0 } }, { { 1, "\xf0" } } } }
1588   },
1589 };
1590
1591 #undef OP
1592 #undef A
1593
1594 /* Initialize anything needed to be done once, before any cpu_open call.  */
1595
1596 static void
1597 init_tables (void)
1598 {
1599 }
1600
1601 #ifndef opcodes_error_handler
1602 #define opcodes_error_handler(...) \
1603   fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
1604 #endif
1605
1606 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
1607 static void build_hw_table      (CGEN_CPU_TABLE *);
1608 static void build_ifield_table  (CGEN_CPU_TABLE *);
1609 static void build_operand_table (CGEN_CPU_TABLE *);
1610 static void build_insn_table    (CGEN_CPU_TABLE *);
1611 static void bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *);
1612
1613 /* Subroutine of bpf_cgen_cpu_open to look up a mach via its bfd name.  */
1614
1615 static const CGEN_MACH *
1616 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
1617 {
1618   while (table->name)
1619     {
1620       if (strcmp (name, table->bfd_name) == 0)
1621         return table;
1622       ++table;
1623     }
1624   return NULL;
1625 }
1626
1627 /* Subroutine of bpf_cgen_cpu_open to build the hardware table.  */
1628
1629 static void
1630 build_hw_table (CGEN_CPU_TABLE *cd)
1631 {
1632   int i;
1633   int machs = cd->machs;
1634   const CGEN_HW_ENTRY *init = & bpf_cgen_hw_table[0];
1635   /* MAX_HW is only an upper bound on the number of selected entries.
1636      However each entry is indexed by it's enum so there can be holes in
1637      the table.  */
1638   const CGEN_HW_ENTRY **selected =
1639     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1640
1641   cd->hw_table.init_entries = init;
1642   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1643   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1644   /* ??? For now we just use machs to determine which ones we want.  */
1645   for (i = 0; init[i].name != NULL; ++i)
1646     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1647         & machs)
1648       selected[init[i].type] = &init[i];
1649   cd->hw_table.entries = selected;
1650   cd->hw_table.num_entries = MAX_HW;
1651 }
1652
1653 /* Subroutine of bpf_cgen_cpu_open to build the hardware table.  */
1654
1655 static void
1656 build_ifield_table (CGEN_CPU_TABLE *cd)
1657 {
1658   cd->ifld_table = & bpf_cgen_ifld_table[0];
1659 }
1660
1661 /* Subroutine of bpf_cgen_cpu_open to build the hardware table.  */
1662
1663 static void
1664 build_operand_table (CGEN_CPU_TABLE *cd)
1665 {
1666   int i;
1667   int machs = cd->machs;
1668   const CGEN_OPERAND *init = & bpf_cgen_operand_table[0];
1669   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1670      However each entry is indexed by it's enum so there can be holes in
1671      the table.  */
1672   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1673
1674   cd->operand_table.init_entries = init;
1675   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1676   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1677   /* ??? For now we just use mach to determine which ones we want.  */
1678   for (i = 0; init[i].name != NULL; ++i)
1679     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1680         & machs)
1681       selected[init[i].type] = &init[i];
1682   cd->operand_table.entries = selected;
1683   cd->operand_table.num_entries = MAX_OPERANDS;
1684 }
1685
1686 /* Subroutine of bpf_cgen_cpu_open to build the hardware table.
1687    ??? This could leave out insns not supported by the specified mach/isa,
1688    but that would cause errors like "foo only supported by bar" to become
1689    "unknown insn", so for now we include all insns and require the app to
1690    do the checking later.
1691    ??? On the other hand, parsing of such insns may require their hardware or
1692    operand elements to be in the table [which they mightn't be].  */
1693
1694 static void
1695 build_insn_table (CGEN_CPU_TABLE *cd)
1696 {
1697   int i;
1698   const CGEN_IBASE *ib = & bpf_cgen_insn_table[0];
1699   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1700
1701   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1702   for (i = 0; i < MAX_INSNS; ++i)
1703     insns[i].base = &ib[i];
1704   cd->insn_table.init_entries = insns;
1705   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1706   cd->insn_table.num_init_entries = MAX_INSNS;
1707 }
1708
1709 /* Subroutine of bpf_cgen_cpu_open to rebuild the tables.  */
1710
1711 static void
1712 bpf_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1713 {
1714   int i;
1715   CGEN_BITSET *isas = cd->isas;
1716   unsigned int machs = cd->machs;
1717
1718   cd->int_insn_p = CGEN_INT_INSN_P;
1719
1720   /* Data derived from the isa spec.  */
1721 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1722   cd->default_insn_bitsize = UNSET;
1723   cd->base_insn_bitsize = UNSET;
1724   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1725   cd->max_insn_bitsize = 0;
1726   for (i = 0; i < MAX_ISAS; ++i)
1727     if (cgen_bitset_contains (isas, i))
1728       {
1729         const CGEN_ISA *isa = & bpf_cgen_isa_table[i];
1730
1731         /* Default insn sizes of all selected isas must be
1732            equal or we set the result to 0, meaning "unknown".  */
1733         if (cd->default_insn_bitsize == UNSET)
1734           cd->default_insn_bitsize = isa->default_insn_bitsize;
1735         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1736           ; /* This is ok.  */
1737         else
1738           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1739
1740         /* Base insn sizes of all selected isas must be equal
1741            or we set the result to 0, meaning "unknown".  */
1742         if (cd->base_insn_bitsize == UNSET)
1743           cd->base_insn_bitsize = isa->base_insn_bitsize;
1744         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1745           ; /* This is ok.  */
1746         else
1747           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1748
1749         /* Set min,max insn sizes.  */
1750         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1751           cd->min_insn_bitsize = isa->min_insn_bitsize;
1752         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1753           cd->max_insn_bitsize = isa->max_insn_bitsize;
1754       }
1755
1756   /* Data derived from the mach spec.  */
1757   for (i = 0; i < MAX_MACHS; ++i)
1758     if (((1 << i) & machs) != 0)
1759       {
1760         const CGEN_MACH *mach = & bpf_cgen_mach_table[i];
1761
1762         if (mach->insn_chunk_bitsize != 0)
1763         {
1764           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1765             {
1766               opcodes_error_handler
1767                 (/* xgettext:c-format */
1768                  _("internal error: bpf_cgen_rebuild_tables: "
1769                    "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
1770                  cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1771               abort ();
1772             }
1773
1774           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1775         }
1776       }
1777
1778   /* Determine which hw elements are used by MACH.  */
1779   build_hw_table (cd);
1780
1781   /* Build the ifield table.  */
1782   build_ifield_table (cd);
1783
1784   /* Determine which operands are used by MACH/ISA.  */
1785   build_operand_table (cd);
1786
1787   /* Build the instruction table.  */
1788   build_insn_table (cd);
1789 }
1790
1791 /* Initialize a cpu table and return a descriptor.
1792    It's much like opening a file, and must be the first function called.
1793    The arguments are a set of (type/value) pairs, terminated with
1794    CGEN_CPU_OPEN_END.
1795
1796    Currently supported values:
1797    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1798    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1799    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1800    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1801    CGEN_CPU_OPEN_INSN_ENDIAN: specify instruction endian choice
1802    CGEN_CPU_OPEN_END:     terminates arguments
1803
1804    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1805    precluded.  */
1806
1807 CGEN_CPU_DESC
1808 bpf_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1809 {
1810   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1811   static int init_p;
1812   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1813   unsigned int machs = 0; /* 0 = "unspecified" */
1814   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1815   enum cgen_endian insn_endian = CGEN_ENDIAN_UNKNOWN;
1816   va_list ap;
1817
1818   if (! init_p)
1819     {
1820       init_tables ();
1821       init_p = 1;
1822     }
1823
1824   memset (cd, 0, sizeof (*cd));
1825
1826   va_start (ap, arg_type);
1827   while (arg_type != CGEN_CPU_OPEN_END)
1828     {
1829       switch (arg_type)
1830         {
1831         case CGEN_CPU_OPEN_ISAS :
1832           isas = va_arg (ap, CGEN_BITSET *);
1833           break;
1834         case CGEN_CPU_OPEN_MACHS :
1835           machs = va_arg (ap, unsigned int);
1836           break;
1837         case CGEN_CPU_OPEN_BFDMACH :
1838           {
1839             const char *name = va_arg (ap, const char *);
1840             const CGEN_MACH *mach =
1841               lookup_mach_via_bfd_name (bpf_cgen_mach_table, name);
1842
1843             if (mach != NULL)
1844               machs |= 1 << mach->num;
1845             break;
1846           }
1847         case CGEN_CPU_OPEN_ENDIAN :
1848           endian = va_arg (ap, enum cgen_endian);
1849           break;
1850         case CGEN_CPU_OPEN_INSN_ENDIAN :
1851           insn_endian = va_arg (ap, enum cgen_endian);
1852           break;
1853         default :
1854           opcodes_error_handler
1855             (/* xgettext:c-format */
1856              _("internal error: bpf_cgen_cpu_open: "
1857                "unsupported argument `%d'"),
1858              arg_type);
1859           abort (); /* ??? return NULL? */
1860         }
1861       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1862     }
1863   va_end (ap);
1864
1865   /* Mach unspecified means "all".  */
1866   if (machs == 0)
1867     machs = (1 << MAX_MACHS) - 1;
1868   /* Base mach is always selected.  */
1869   machs |= 1;
1870   if (endian == CGEN_ENDIAN_UNKNOWN)
1871     {
1872       /* ??? If target has only one, could have a default.  */
1873       opcodes_error_handler
1874         (/* xgettext:c-format */
1875          _("internal error: bpf_cgen_cpu_open: no endianness specified"));
1876       abort ();
1877     }
1878
1879   cd->isas = cgen_bitset_copy (isas);
1880   cd->machs = machs;
1881   cd->endian = endian;
1882   cd->insn_endian
1883     = (insn_endian == CGEN_ENDIAN_UNKNOWN ? endian : insn_endian);
1884
1885   /* Table (re)builder.  */
1886   cd->rebuild_tables = bpf_cgen_rebuild_tables;
1887   bpf_cgen_rebuild_tables (cd);
1888
1889   /* Default to not allowing signed overflow.  */
1890   cd->signed_overflow_ok_p = 0;
1891
1892   return (CGEN_CPU_DESC) cd;
1893 }
1894
1895 /* Cover fn to bpf_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1896    MACH_NAME is the bfd name of the mach.  */
1897
1898 CGEN_CPU_DESC
1899 bpf_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1900 {
1901   return bpf_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1902                                CGEN_CPU_OPEN_ENDIAN, endian,
1903                                CGEN_CPU_OPEN_END);
1904 }
1905
1906 /* Close a cpu table.
1907    ??? This can live in a machine independent file, but there's currently
1908    no place to put this file (there's no libcgen).  libopcodes is the wrong
1909    place as some simulator ports use this but they don't use libopcodes.  */
1910
1911 void
1912 bpf_cgen_cpu_close (CGEN_CPU_DESC cd)
1913 {
1914   unsigned int i;
1915   const CGEN_INSN *insns;
1916
1917   if (cd->macro_insn_table.init_entries)
1918     {
1919       insns = cd->macro_insn_table.init_entries;
1920       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1921         if (CGEN_INSN_RX ((insns)))
1922           regfree (CGEN_INSN_RX (insns));
1923     }
1924
1925   if (cd->insn_table.init_entries)
1926     {
1927       insns = cd->insn_table.init_entries;
1928       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1929         if (CGEN_INSN_RX (insns))
1930           regfree (CGEN_INSN_RX (insns));
1931     }
1932
1933   free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1934   free ((CGEN_INSN *) cd->insn_table.init_entries);
1935   free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1936   free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1937   free (cd);
1938 }
1939