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[binutils-gdb.git] / gdb / mips-linux-nat.c
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1 /* Native-dependent code for GNU/Linux on MIPS processors.
3 Copyright (C) 2001-2024 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
20 #include "command.h"
21 #include "cli/cli-cmds.h"
22 #include "inferior.h"
23 #include "mips-tdep.h"
24 #include "target.h"
25 #include "regcache.h"
26 #include "linux-nat-trad.h"
27 #include "mips-linux-tdep.h"
28 #include "target-descriptions.h"
30 #include "gdb_proc_service.h"
31 #include "gregset.h"
33 #include <sgidefs.h>
34 #include "nat/gdb_ptrace.h"
35 #include <asm/ptrace.h>
36 #include "inf-ptrace.h"
38 #include "nat/mips-linux-watch.h"
40 #ifndef PTRACE_GET_THREAD_AREA
41 #define PTRACE_GET_THREAD_AREA 25
42 #endif
44 class mips_linux_nat_target final : public linux_nat_trad_target
46 public:
47 /* Add our register access methods. */
48 void fetch_registers (struct regcache *, int) override;
49 void store_registers (struct regcache *, int) override;
51 void close () override;
53 int can_use_hw_breakpoint (enum bptype, int, int) override;
55 int remove_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
56 struct expression *) override;
58 int insert_watchpoint (CORE_ADDR, int, enum target_hw_bp_type,
59 struct expression *) override;
61 bool stopped_by_watchpoint () override;
63 bool stopped_data_address (CORE_ADDR *) override;
65 int region_ok_for_hw_watchpoint (CORE_ADDR, int) override;
67 const struct target_desc *read_description () override;
69 protected:
70 /* Override linux_nat_trad_target methods. */
71 CORE_ADDR register_u_offset (struct gdbarch *gdbarch,
72 int regno, int store_p) override;
74 /* Override linux_nat_target low methods. */
75 void low_new_thread (struct lwp_info *lp) override;
77 private:
78 /* Helpers. See definitions. */
79 void mips64_regsets_store_registers (struct regcache *regcache,
80 int regno);
81 void mips64_regsets_fetch_registers (struct regcache *regcache,
82 int regno);
85 static mips_linux_nat_target the_mips_linux_nat_target;
87 /* Assume that we have PTRACE_GETREGS et al. support. If we do not,
88 we'll clear this and use PTRACE_PEEKUSER instead. */
89 static int have_ptrace_regsets = 1;
91 /* Map gdb internal register number to ptrace ``address''.
92 These ``addresses'' are normally defined in <asm/ptrace.h>.
94 ptrace does not provide a way to read (or set) MIPS_PS_REGNUM,
95 and there's no point in reading or setting MIPS_ZERO_REGNUM.
96 We also can not set BADVADDR, CAUSE, or FCRIR via ptrace(). */
98 static CORE_ADDR
99 mips_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
101 CORE_ADDR regaddr;
103 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
104 error (_("Bogon register number %d."), regno);
106 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
107 regaddr = regno;
108 else if ((regno >= mips_regnum (gdbarch)->fp0)
109 && (regno < mips_regnum (gdbarch)->fp0 + 32))
110 regaddr = FPR_BASE + (regno - mips_regnum (gdbarch)->fp0);
111 else if (regno == mips_regnum (gdbarch)->pc)
112 regaddr = PC;
113 else if (regno == mips_regnum (gdbarch)->cause)
114 regaddr = store? (CORE_ADDR) -1 : CAUSE;
115 else if (regno == mips_regnum (gdbarch)->badvaddr)
116 regaddr = store? (CORE_ADDR) -1 : BADVADDR;
117 else if (regno == mips_regnum (gdbarch)->lo)
118 regaddr = MMLO;
119 else if (regno == mips_regnum (gdbarch)->hi)
120 regaddr = MMHI;
121 else if (regno == mips_regnum (gdbarch)->fp_control_status)
122 regaddr = FPC_CSR;
123 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
124 regaddr = store? (CORE_ADDR) -1 : FPC_EIR;
125 else if (mips_regnum (gdbarch)->dspacc != -1
126 && regno >= mips_regnum (gdbarch)->dspacc
127 && regno < mips_regnum (gdbarch)->dspacc + 6)
128 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
129 else if (regno == mips_regnum (gdbarch)->dspctl)
130 regaddr = DSP_CONTROL;
131 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
132 regaddr = 0;
133 else
134 regaddr = (CORE_ADDR) -1;
136 return regaddr;
139 static CORE_ADDR
140 mips64_linux_register_addr (struct gdbarch *gdbarch, int regno, int store)
142 CORE_ADDR regaddr;
144 if (regno < 0 || regno >= gdbarch_num_regs (gdbarch))
145 error (_("Bogon register number %d."), regno);
147 /* On n32 we can't access 64-bit registers via PTRACE_PEEKUSR
148 or PTRACE_POKEUSR. */
149 if (register_size (gdbarch, regno) > sizeof (PTRACE_TYPE_RET))
150 return (CORE_ADDR) -1;
152 if (regno > MIPS_ZERO_REGNUM && regno < MIPS_ZERO_REGNUM + 32)
153 regaddr = regno;
154 else if ((regno >= mips_regnum (gdbarch)->fp0)
155 && (regno < mips_regnum (gdbarch)->fp0 + 32))
156 regaddr = MIPS64_FPR_BASE + (regno - gdbarch_fp0_regnum (gdbarch));
157 else if (regno == mips_regnum (gdbarch)->pc)
158 regaddr = MIPS64_PC;
159 else if (regno == mips_regnum (gdbarch)->cause)
160 regaddr = store? (CORE_ADDR) -1 : MIPS64_CAUSE;
161 else if (regno == mips_regnum (gdbarch)->badvaddr)
162 regaddr = store? (CORE_ADDR) -1 : MIPS64_BADVADDR;
163 else if (regno == mips_regnum (gdbarch)->lo)
164 regaddr = MIPS64_MMLO;
165 else if (regno == mips_regnum (gdbarch)->hi)
166 regaddr = MIPS64_MMHI;
167 else if (regno == mips_regnum (gdbarch)->fp_control_status)
168 regaddr = MIPS64_FPC_CSR;
169 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
170 regaddr = store? (CORE_ADDR) -1 : MIPS64_FPC_EIR;
171 else if (mips_regnum (gdbarch)->dspacc != -1
172 && regno >= mips_regnum (gdbarch)->dspacc
173 && regno < mips_regnum (gdbarch)->dspacc + 6)
174 regaddr = DSP_BASE + (regno - mips_regnum (gdbarch)->dspacc);
175 else if (regno == mips_regnum (gdbarch)->dspctl)
176 regaddr = DSP_CONTROL;
177 else if (mips_linux_restart_reg_p (gdbarch) && regno == MIPS_RESTART_REGNUM)
178 regaddr = 0;
179 else
180 regaddr = (CORE_ADDR) -1;
182 return regaddr;
185 /* Fetch the thread-local storage pointer for libthread_db. */
187 ps_err_e
188 ps_get_thread_area (struct ps_prochandle *ph,
189 lwpid_t lwpid, int idx, void **base)
191 if (ptrace (PTRACE_GET_THREAD_AREA, lwpid, NULL, base) != 0)
192 return PS_ERR;
194 /* IDX is the bias from the thread pointer to the beginning of the
195 thread descriptor. It has to be subtracted due to implementation
196 quirks in libthread_db. */
197 *base = (void *) ((char *)*base - idx);
199 return PS_OK;
202 /* Wrapper functions. These are only used by libthread_db. */
204 void
205 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
207 if (mips_isa_regsize (regcache->arch ()) == 4)
208 mips_supply_gregset (regcache, (const mips_elf_gregset_t *) gregsetp);
209 else
210 mips64_supply_gregset (regcache, (const mips64_elf_gregset_t *) gregsetp);
213 void
214 fill_gregset (const struct regcache *regcache,
215 gdb_gregset_t *gregsetp, int regno)
217 if (mips_isa_regsize (regcache->arch ()) == 4)
218 mips_fill_gregset (regcache, (mips_elf_gregset_t *) gregsetp, regno);
219 else
220 mips64_fill_gregset (regcache, (mips64_elf_gregset_t *) gregsetp, regno);
223 void
224 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
226 mips64_supply_fpregset (regcache, (const mips64_elf_fpregset_t *) fpregsetp);
229 void
230 fill_fpregset (const struct regcache *regcache,
231 gdb_fpregset_t *fpregsetp, int regno)
233 mips64_fill_fpregset (regcache, (mips64_elf_fpregset_t *) fpregsetp, regno);
237 /* Fetch REGNO (or all registers if REGNO == -1) from the target
238 using PTRACE_GETREGS et al. */
240 void
241 mips_linux_nat_target::mips64_regsets_fetch_registers
242 (struct regcache *regcache, int regno)
244 struct gdbarch *gdbarch = regcache->arch ();
245 int is_fp, is_dsp;
246 int have_dsp;
247 int regi;
248 int tid;
250 if (regno >= mips_regnum (gdbarch)->fp0
251 && regno <= mips_regnum (gdbarch)->fp0 + 32)
252 is_fp = 1;
253 else if (regno == mips_regnum (gdbarch)->fp_control_status)
254 is_fp = 1;
255 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
256 is_fp = 1;
257 else
258 is_fp = 0;
260 /* DSP registers are optional and not a part of any set. */
261 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
262 if (!have_dsp)
263 is_dsp = 0;
264 else if (regno >= mips_regnum (gdbarch)->dspacc
265 && regno < mips_regnum (gdbarch)->dspacc + 6)
266 is_dsp = 1;
267 else if (regno == mips_regnum (gdbarch)->dspctl)
268 is_dsp = 1;
269 else
270 is_dsp = 0;
272 tid = get_ptrace_pid (regcache->ptid ());
274 if (regno == -1 || (!is_fp && !is_dsp))
276 mips64_elf_gregset_t regs;
278 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
280 if (errno == EIO)
282 have_ptrace_regsets = 0;
283 return;
285 perror_with_name (_("Couldn't get registers"));
288 mips64_supply_gregset (regcache,
289 (const mips64_elf_gregset_t *) &regs);
292 if (regno == -1 || is_fp)
294 mips64_elf_fpregset_t fp_regs;
296 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
297 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
299 if (errno == EIO)
301 have_ptrace_regsets = 0;
302 return;
304 perror_with_name (_("Couldn't get FP registers"));
307 mips64_supply_fpregset (regcache,
308 (const mips64_elf_fpregset_t *) &fp_regs);
311 if (is_dsp)
312 linux_nat_trad_target::fetch_registers (regcache, regno);
313 else if (regno == -1 && have_dsp)
315 for (regi = mips_regnum (gdbarch)->dspacc;
316 regi < mips_regnum (gdbarch)->dspacc + 6;
317 regi++)
318 linux_nat_trad_target::fetch_registers (regcache, regi);
319 linux_nat_trad_target::fetch_registers (regcache,
320 mips_regnum (gdbarch)->dspctl);
324 /* Store REGNO (or all registers if REGNO == -1) to the target
325 using PTRACE_SETREGS et al. */
327 void
328 mips_linux_nat_target::mips64_regsets_store_registers
329 (struct regcache *regcache, int regno)
331 struct gdbarch *gdbarch = regcache->arch ();
332 int is_fp, is_dsp;
333 int have_dsp;
334 int regi;
335 int tid;
337 if (regno >= mips_regnum (gdbarch)->fp0
338 && regno <= mips_regnum (gdbarch)->fp0 + 32)
339 is_fp = 1;
340 else if (regno == mips_regnum (gdbarch)->fp_control_status)
341 is_fp = 1;
342 else if (regno == mips_regnum (gdbarch)->fp_implementation_revision)
343 is_fp = 1;
344 else
345 is_fp = 0;
347 /* DSP registers are optional and not a part of any set. */
348 have_dsp = mips_regnum (gdbarch)->dspctl != -1;
349 if (!have_dsp)
350 is_dsp = 0;
351 else if (regno >= mips_regnum (gdbarch)->dspacc
352 && regno < mips_regnum (gdbarch)->dspacc + 6)
353 is_dsp = 1;
354 else if (regno == mips_regnum (gdbarch)->dspctl)
355 is_dsp = 1;
356 else
357 is_dsp = 0;
359 tid = get_ptrace_pid (regcache->ptid ());
361 if (regno == -1 || (!is_fp && !is_dsp))
363 mips64_elf_gregset_t regs;
365 if (ptrace (PTRACE_GETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
366 perror_with_name (_("Couldn't get registers"));
368 mips64_fill_gregset (regcache, &regs, regno);
370 if (ptrace (PTRACE_SETREGS, tid, 0L, (PTRACE_TYPE_ARG3) &regs) == -1)
371 perror_with_name (_("Couldn't set registers"));
374 if (regno == -1 || is_fp)
376 mips64_elf_fpregset_t fp_regs;
378 if (ptrace (PTRACE_GETFPREGS, tid, 0L,
379 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
380 perror_with_name (_("Couldn't get FP registers"));
382 mips64_fill_fpregset (regcache, &fp_regs, regno);
384 if (ptrace (PTRACE_SETFPREGS, tid, 0L,
385 (PTRACE_TYPE_ARG3) &fp_regs) == -1)
386 perror_with_name (_("Couldn't set FP registers"));
389 if (is_dsp)
390 linux_nat_trad_target::store_registers (regcache, regno);
391 else if (regno == -1 && have_dsp)
393 for (regi = mips_regnum (gdbarch)->dspacc;
394 regi < mips_regnum (gdbarch)->dspacc + 6;
395 regi++)
396 linux_nat_trad_target::store_registers (regcache, regi);
397 linux_nat_trad_target::store_registers (regcache,
398 mips_regnum (gdbarch)->dspctl);
402 /* Fetch REGNO (or all registers if REGNO == -1) from the target
403 using any working method. */
405 void
406 mips_linux_nat_target::fetch_registers (struct regcache *regcache, int regnum)
408 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
409 if (have_ptrace_regsets)
410 mips64_regsets_fetch_registers (regcache, regnum);
412 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
413 back to PTRACE_PEEKUSER. */
414 if (!have_ptrace_regsets)
416 linux_nat_trad_target::fetch_registers (regcache, regnum);
418 /* Fill the inaccessible zero register with zero. */
419 if (regnum == MIPS_ZERO_REGNUM || regnum == -1)
420 regcache->raw_supply_zeroed (MIPS_ZERO_REGNUM);
424 /* Store REGNO (or all registers if REGNO == -1) to the target
425 using any working method. */
427 void
428 mips_linux_nat_target::store_registers (struct regcache *regcache, int regnum)
430 /* Unless we already know that PTRACE_GETREGS does not work, try it. */
431 if (have_ptrace_regsets)
432 mips64_regsets_store_registers (regcache, regnum);
434 /* If we know, or just found out, that PTRACE_GETREGS does not work, fall
435 back to PTRACE_PEEKUSER. */
436 if (!have_ptrace_regsets)
437 linux_nat_trad_target::store_registers (regcache, regnum);
440 /* Return the address in the core dump or inferior of register
441 REGNO. */
443 CORE_ADDR
444 mips_linux_nat_target::register_u_offset (struct gdbarch *gdbarch,
445 int regno, int store_p)
447 if (mips_abi_regsize (gdbarch) == 8)
448 return mips64_linux_register_addr (gdbarch, regno, store_p);
449 else
450 return mips_linux_register_addr (gdbarch, regno, store_p);
453 const struct target_desc *
454 mips_linux_nat_target::read_description ()
456 static int have_dsp = -1;
458 if (have_dsp < 0)
460 /* Assume no DSP if there is no inferior to inspect with ptrace. */
461 if (inferior_ptid == null_ptid)
462 return _MIPS_SIM == _ABIO32 ? tdesc_mips_linux : tdesc_mips64_linux;
464 int tid = get_ptrace_pid (inferior_ptid);
466 errno = 0;
467 ptrace (PTRACE_PEEKUSER, tid, DSP_CONTROL, 0);
468 switch (errno)
470 case 0:
471 have_dsp = 1;
472 break;
473 case EIO:
474 have_dsp = 0;
475 break;
476 default:
477 perror_with_name (_("Couldn't check DSP support"));
478 break;
482 /* Report that target registers are a size we know for sure
483 that we can get from ptrace. */
484 if (_MIPS_SIM == _ABIO32)
485 return have_dsp ? tdesc_mips_dsp_linux : tdesc_mips_linux;
486 else
487 return have_dsp ? tdesc_mips64_dsp_linux : tdesc_mips64_linux;
490 /* -1 if the kernel and/or CPU do not support watch registers.
491 1 if watch_readback is valid and we can read style, num_valid
492 and the masks.
493 0 if we need to read the watch_readback. */
495 static int watch_readback_valid;
497 /* Cached watch register read values. */
499 static struct pt_watch_regs watch_readback;
501 static struct mips_watchpoint *current_watches;
503 /* The current set of watch register values for writing the
504 registers. */
506 static struct pt_watch_regs watch_mirror;
508 static void
509 mips_show_dr (const char *func, CORE_ADDR addr,
510 int len, enum target_hw_bp_type type)
512 int i;
514 gdb_puts (func, gdb_stdlog);
515 if (addr || len)
516 gdb_printf (gdb_stdlog,
517 " (addr=%s, len=%d, type=%s)",
518 paddress (current_inferior ()->arch (), addr), len,
519 type == hw_write ? "data-write"
520 : (type == hw_read ? "data-read"
521 : (type == hw_access ? "data-read/write"
522 : (type == hw_execute ? "instruction-execute"
523 : "??unknown??"))));
524 gdb_puts (":\n", gdb_stdlog);
526 for (i = 0; i < MAX_DEBUG_REGISTER; i++)
527 gdb_printf (gdb_stdlog, "\tDR%d: lo=%s, hi=%s\n", i,
528 paddress (current_inferior ()->arch (),
529 mips_linux_watch_get_watchlo (&watch_mirror,
530 i)),
531 paddress (current_inferior ()->arch (),
532 mips_linux_watch_get_watchhi (&watch_mirror,
533 i)));
536 /* Target to_can_use_hw_breakpoint implementation. Return 1 if we can
537 handle the specified watch type. */
540 mips_linux_nat_target::can_use_hw_breakpoint (enum bptype type,
541 int cnt, int ot)
543 int i;
544 uint32_t wanted_mask, irw_mask;
546 if (!mips_linux_read_watch_registers (inferior_ptid.lwp (),
547 &watch_readback,
548 &watch_readback_valid, 0))
549 return 0;
551 switch (type)
553 case bp_hardware_watchpoint:
554 wanted_mask = W_MASK;
555 break;
556 case bp_read_watchpoint:
557 wanted_mask = R_MASK;
558 break;
559 case bp_access_watchpoint:
560 wanted_mask = R_MASK | W_MASK;
561 break;
562 default:
563 return 0;
566 for (i = 0;
567 i < mips_linux_watch_get_num_valid (&watch_readback) && cnt;
568 i++)
570 irw_mask = mips_linux_watch_get_irw_mask (&watch_readback, i);
571 if ((irw_mask & wanted_mask) == wanted_mask)
572 cnt--;
574 return (cnt == 0) ? 1 : 0;
577 /* Target to_stopped_by_watchpoint implementation. Return 1 if
578 stopped by watchpoint. The watchhi R and W bits indicate the watch
579 register triggered. */
581 bool
582 mips_linux_nat_target::stopped_by_watchpoint ()
584 int n;
585 int num_valid;
587 if (!mips_linux_read_watch_registers (inferior_ptid.lwp (),
588 &watch_readback,
589 &watch_readback_valid, 1))
590 return false;
592 num_valid = mips_linux_watch_get_num_valid (&watch_readback);
594 for (n = 0; n < MAX_DEBUG_REGISTER && n < num_valid; n++)
595 if (mips_linux_watch_get_watchhi (&watch_readback, n) & (R_MASK | W_MASK))
596 return true;
598 return false;
601 /* Target to_stopped_data_address implementation. Set the address
602 where the watch triggered (if known). Return 1 if the address was
603 known. */
605 bool
606 mips_linux_nat_target::stopped_data_address (CORE_ADDR *paddr)
608 /* On mips we don't know the low order 3 bits of the data address,
609 so we must return false. */
610 return false;
613 /* Target to_region_ok_for_hw_watchpoint implementation. Return 1 if
614 the specified region can be covered by the watch registers. */
617 mips_linux_nat_target::region_ok_for_hw_watchpoint (CORE_ADDR addr, int len)
619 struct pt_watch_regs dummy_regs;
620 int i;
622 if (!mips_linux_read_watch_registers (inferior_ptid.lwp (),
623 &watch_readback,
624 &watch_readback_valid, 0))
625 return 0;
627 dummy_regs = watch_readback;
628 /* Clear them out. */
629 for (i = 0; i < mips_linux_watch_get_num_valid (&dummy_regs); i++)
630 mips_linux_watch_set_watchlo (&dummy_regs, i, 0);
631 return mips_linux_watch_try_one_watch (&dummy_regs, addr, len, 0);
634 /* Write the mirrored watch register values for each thread. */
636 static int
637 write_watchpoint_regs (void)
639 for (const lwp_info *lp : all_lwps ())
641 int tid = lp->ptid.lwp ();
642 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
643 perror_with_name (_("Couldn't write debug register"));
645 return 0;
648 /* linux_nat_target::low_new_thread implementation. Write the
649 mirrored watch register values for the new thread. */
651 void
652 mips_linux_nat_target::low_new_thread (struct lwp_info *lp)
654 long tid = lp->ptid.lwp ();
656 if (!mips_linux_read_watch_registers (tid,
657 &watch_readback,
658 &watch_readback_valid, 0))
659 return;
661 if (ptrace (PTRACE_SET_WATCH_REGS, tid, &watch_mirror, NULL) == -1)
662 perror_with_name (_("Couldn't write debug register"));
665 /* Target to_insert_watchpoint implementation. Try to insert a new
666 watch. Return zero on success. */
669 mips_linux_nat_target::insert_watchpoint (CORE_ADDR addr, int len,
670 enum target_hw_bp_type type,
671 struct expression *cond)
673 struct pt_watch_regs regs;
674 struct mips_watchpoint *new_watch;
675 struct mips_watchpoint **pw;
677 int retval;
679 if (!mips_linux_read_watch_registers (inferior_ptid.lwp (),
680 &watch_readback,
681 &watch_readback_valid, 0))
682 return -1;
684 if (len <= 0)
685 return -1;
687 regs = watch_readback;
688 /* Add the current watches. */
689 mips_linux_watch_populate_regs (current_watches, &regs);
691 /* Now try to add the new watch. */
692 if (!mips_linux_watch_try_one_watch (&regs, addr, len,
693 mips_linux_watch_type_to_irw (type)))
694 return -1;
696 /* It fit. Stick it on the end of the list. */
697 new_watch = XNEW (struct mips_watchpoint);
698 new_watch->addr = addr;
699 new_watch->len = len;
700 new_watch->type = type;
701 new_watch->next = NULL;
703 pw = &current_watches;
704 while (*pw != NULL)
705 pw = &(*pw)->next;
706 *pw = new_watch;
708 watch_mirror = regs;
709 retval = write_watchpoint_regs ();
711 if (show_debug_regs)
712 mips_show_dr ("insert_watchpoint", addr, len, type);
714 return retval;
717 /* Target to_remove_watchpoint implementation. Try to remove a watch.
718 Return zero on success. */
721 mips_linux_nat_target::remove_watchpoint (CORE_ADDR addr, int len,
722 enum target_hw_bp_type type,
723 struct expression *cond)
725 int retval;
726 int deleted_one;
728 struct mips_watchpoint **pw;
729 struct mips_watchpoint *w;
731 /* Search for a known watch that matches. Then unlink and free
732 it. */
733 deleted_one = 0;
734 pw = &current_watches;
735 while ((w = *pw))
737 if (w->addr == addr && w->len == len && w->type == type)
739 *pw = w->next;
740 xfree (w);
741 deleted_one = 1;
742 break;
744 pw = &(w->next);
747 if (!deleted_one)
748 return -1; /* We don't know about it, fail doing nothing. */
750 /* At this point watch_readback is known to be valid because we
751 could not have added the watch without reading it. */
752 gdb_assert (watch_readback_valid == 1);
754 watch_mirror = watch_readback;
755 mips_linux_watch_populate_regs (current_watches, &watch_mirror);
757 retval = write_watchpoint_regs ();
759 if (show_debug_regs)
760 mips_show_dr ("remove_watchpoint", addr, len, type);
762 return retval;
765 /* Target to_close implementation. Free any watches and call the
766 super implementation. */
768 void
769 mips_linux_nat_target::close ()
771 struct mips_watchpoint *w;
772 struct mips_watchpoint *nw;
774 /* Clean out the current_watches list. */
775 w = current_watches;
776 while (w)
778 nw = w->next;
779 xfree (w);
780 w = nw;
782 current_watches = NULL;
784 linux_nat_trad_target::close ();
787 void _initialize_mips_linux_nat ();
788 void
789 _initialize_mips_linux_nat ()
791 add_setshow_boolean_cmd ("show-debug-regs", class_maintenance,
792 &show_debug_regs, _("\
793 Set whether to show variables that mirror the mips debug registers."), _("\
794 Show whether to show variables that mirror the mips debug registers."), _("\
795 Use \"on\" to enable, \"off\" to disable.\n\
796 If enabled, the debug registers values are shown when GDB inserts\n\
797 or removes a hardware breakpoint or watchpoint, and when the inferior\n\
798 triggers a breakpoint or watchpoint."),
799 NULL,
800 NULL,
801 &maintenance_set_cmdlist,
802 &maintenance_show_cmdlist);
804 linux_target = &the_mips_linux_nat_target;
805 add_inf_child_target (&the_mips_linux_nat_target);