gdb/aarch64-ravenscar-thread.c

   1 /* Ravenscar Aarch64 target support.
   2
   3    Copyright (C) 2017-2024 Free Software Foundation, Inc.
   4
   5    This file is part of GDB.
   6
   7    This program is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3 of the License, or
  10    (at your option) any later version.
  11
  12    This program is distributed in the hope that it will be useful,
  13    but WITHOUT ANY WARRANTY; without even the implied warranty of
  14    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15    GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  19
  20 #include "gdbcore.h"
  21 #include "regcache.h"
  22 #include "aarch64-tdep.h"
  23 #include "inferior.h"
  24 #include "ravenscar-thread.h"
  25 #include "aarch64-ravenscar-thread.h"
  26 #include "gdbarch.h"
  27
  28 #define NO_OFFSET -1
  29
  30 /* See aarch64-tdep.h for register numbers.  */
  31
  32 static const int aarch64_context_offsets[] =
  33 {
  34   /* X0 - X28 */
  35   NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  36   NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  37   NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  38   NO_OFFSET, NO_OFFSET, NO_OFFSET, NO_OFFSET,
  39   NO_OFFSET, NO_OFFSET, NO_OFFSET, 0,
  40   8,         16,        24,        32,
  41   40,        48,        56,        64,
  42   72,
  43
  44   /* FP, LR, SP, PC, CPSR */
  45   /* Note that as task switch is synchronous, PC is in fact the LR here */
  46   80,        88,        96,        88,
  47   NO_OFFSET,
  48
  49   /* V0 - V31 */
  50   128,       144,       160,       176,
  51   192,       208,       224,       240,
  52   256,       272,       288,       304,
  53   320,       336,       352,       368,
  54   384,       400,       416,       432,
  55   448,       464,       480,       496,
  56   512,       528,       544,       560,
  57   576,       592,       608,       624,
  58
  59   /* FPSR, FPCR */
  60   112,       116,
  61 };
  62
  63 #define V_INIT_OFFSET 640
  64
  65 /* The ravenscar_arch_ops vector for most Aarch64 targets.  */
  66
  67 static struct ravenscar_arch_ops aarch64_ravenscar_ops
  68      (aarch64_context_offsets,
  69       -1, -1,
  70       V_INIT_OFFSET,
  71       /* The FPU context buffer starts with the FPSR register.  */
  72       aarch64_context_offsets[AARCH64_FPSR_REGNUM],
  73       AARCH64_V0_REGNUM, AARCH64_FPCR_REGNUM);
  74
  75 /* Register aarch64_ravenscar_ops in GDBARCH.  */
  76
  77 void
  78 register_aarch64_ravenscar_ops (struct gdbarch *gdbarch)
  79 {
  80   set_gdbarch_ravenscar_ops (gdbarch, &aarch64_ravenscar_ops);
  81 }