| blob | 779c7081c53698fc9e703e18377eb6619f92e97c |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2024 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
34 /* Return the relocation section associated with NAME. HTAB is the
35 bfd's elf32_arm_link_hash_entry. */
36 #define RELOC_SECTION(HTAB, NAME) \
39 /* Return size of a relocation entry. HTAB is the bfd's
40 elf32_arm_link_hash_entry. */
41 #define RELOC_SIZE(HTAB) \
42 ((HTAB)->use_rel \
43 ? sizeof (Elf32_External_Rel) \
44 : sizeof (Elf32_External_Rela))
46 /* Return function to swap relocations in. HTAB is the bfd's
47 elf32_arm_link_hash_entry. */
48 #define SWAP_RELOC_IN(HTAB) \
49 ((HTAB)->use_rel \
50 ? bfd_elf32_swap_reloc_in \
51 : bfd_elf32_swap_reloca_in)
53 /* Return function to swap relocations out. HTAB is the bfd's
54 elf32_arm_link_hash_entry. */
55 #define SWAP_RELOC_OUT(HTAB) \
56 ((HTAB)->use_rel \
57 ? bfd_elf32_swap_reloc_out \
58 : bfd_elf32_swap_reloca_out)
60 #define elf_info_to_howto NULL
61 #define elf_info_to_howto_rel elf32_arm_info_to_howto
63 #define ARM_ELF_ABI_VERSION 0
64 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
66 /* The Adjusted Place, as defined by AAELF. */
67 #define Pa(X) ((X) & 0xfffffffc)
74 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
75 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
76 in that slot. */
79 {
80 /* No relocation. */
109 /* 32 bit absolute */
124 /* standard 32bit pc-relative reloc */
139 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
154 /* 16 bit absolute */
169 /* 12 bit absolute */
198 /* 8 bit absolute */
297 /* BLX instruction for the ARM. */
312 /* BLX instruction for the Thumb. */
327 /* Dynamic TLS relocations. */
371 /* Relocs used in ARM Linux */
835 /* These are declared as 13-bit signed relocations because we can
836 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
837 versa. */
894 /* Group relocations. */
1274 /* End of group relocations. */
1488 /* GNU extension to record C++ vtable member usage */
1503 /* GNU extension to record C++ vtable hierarchy */
1546 /* TLS relocations */
1659 /* 112-127 private relocations. */
1677 /* R_ARM_ME_TOO, obsolete. */
1747 /* Relocations for Armv8.1-M Mainline. */
1787 };
1789 /* 160 onwards: */
1791 {
1896 };
1898 /* 249-255 extended, currently unused, relocations: */
1900 {
1956 };
1960 {
1973 }
1975 static bool
1978 {
1983 {
1984 /* xgettext:c-format */
1989 }
1991 }
1993 struct elf32_arm_reloc_map
1994 {
1995 bfd_reloc_code_real_type bfd_reloc_val;
1997 };
1999 /* All entries in this list must also be present in elf32_arm_howto_table. */
2001 {
2102 };
2106 bfd_reloc_code_real_type code)
2107 {
2115 }
2120 {
2139 }
2141 /* Support for core dump NOTE sections. */
2143 static bool
2145 {
2150 {
2155 /* pr_cursig */
2158 /* pr_pid */
2161 /* pr_reg */
2166 }
2168 /* Make a ".reg/999" section. */
2171 }
2173 static bool
2175 {
2177 {
2188 }
2190 /* Note that for some reason, a spurious space is tacked
2191 onto the end of the args in some (at least one anyway)
2192 implementations, so strip it off if it exists. */
2193 {
2199 }
2202 }
2207 {
2209 {
2214 {
2221 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2222 DIAGNOSTIC_PUSH;
2223 /* GCC 8.0 and 8.1 warn about 80 equals destination size with
2224 -Wstringop-truncation:
2225 https://gcc.gnu.org/bugzilla/show_bug.cgi?id=85643
2226 */
2227 DIAGNOSTIC_IGNORE_STRINGOP_TRUNCATION;
2228 #endif
2230 #if GCC_VERSION == 8000 || GCC_VERSION == 8001
2231 DIAGNOSTIC_POP;
2232 #endif
2237 }
2240 {
2259 }
2260 }
2261 }
2263 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2265 #define TARGET_BIG_SYM arm_elf32_be_vec
2268 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2269 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2270 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2275 /* In lieu of proper flags, assume all EABIv4 or later objects are
2276 interworkable. */
2277 #define INTERWORK_FLAG(abfd) \
2278 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2279 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2280 || ((abfd)->flags & BFD_LINKER_CREATED))
2282 /* The linker script knows the section names for placement.
2283 The entry_names are used to do simple name mangling on the stubs.
2284 Given a function name, and its type, the stub can be found. The
2285 name can be changed. The only requirement is the %s be present. */
2307 /* The name of the dynamic interpreter. This is put in the .interp
2308 section. */
2311 /* FDPIC default stack size. */
2312 #define DEFAULT_STACK_SIZE 0x8000
2315 {
2319 };
2322 {
2330 + dl_tlsdesc_lazy_resolver(GOT) */
2332 };
2334 /* NOTE: [Thumb nop sequence]
2335 When adding code that transitions from Thumb to Arm the instruction that
2336 should be used for the alignment padding should be 0xe7fd (b .-2) instead of
2337 a nop for performance reasons. */
2339 /* ARM FDPIC PLT entry. */
2340 /* The last 5 words contain PLT lazy fragment code and data. */
2342 {
2353 };
2355 /* Thumb FDPIC PLT entry. */
2356 /* The last 5 words contain PLT lazy fragment code and data. */
2358 {
2369 };
2371 #ifdef FOUR_WORD_PLT
2373 /* The first entry in a procedure linkage table looks like
2374 this. It is set up so that any shared library function that is
2375 called before the relocation has been set up calls the dynamic
2376 linker first. */
2378 {
2383 };
2385 /* Subsequent entries in a procedure linkage table look like
2386 this. */
2388 {
2393 };
2397 /* The first entry in a procedure linkage table looks like
2398 this. It is set up so that any shared library function that is
2399 called before the relocation has been set up calls the dynamic
2400 linker first. */
2402 {
2408 };
2410 /* By default subsequent entries in a procedure linkage table look like
2411 this. Offsets that don't fit into 28 bits will cause link error. */
2413 {
2417 };
2419 /* When explicitly asked, we'll use this "long" entry format
2420 which can cope with arbitrary displacements. */
2422 {
2427 };
2433 /* The first entry in a procedure linkage table looks like this.
2434 It is set up so that any shared library function that is called before the
2435 relocation has been set up calls the dynamic linker first. */
2437 {
2438 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2439 an instruction maybe encoded to one or two array elements. */
2442 /* add lr, pc */
2445 };
2447 /* Subsequent entries in a procedure linkage table for thumb only target
2448 look like this. */
2450 {
2451 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2452 an instruction maybe encoded to one or two array elements. */
2457 /* b .-4 */
2458 };
2460 /* The format of the first entry in the procedure linkage table
2461 for a VxWorks executable. */
2463 {
2468 };
2470 /* The format of subsequent entries in a VxWorks executable. */
2472 {
2479 };
2481 /* The format of entries in a VxWorks shared library. */
2483 {
2490 };
2492 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2493 #define PLT_THUMB_STUB_SIZE 4
2495 {
2498 };
2500 /* The first entry in a procedure linkage table looks like
2501 this. It is set up so that any shared library function that is
2502 called before the relocation has been set up calls the dynamic
2503 linker first. */
2505 {
2506 /* First bundle: */
2511 /* Second bundle: */
2516 /* Third bundle: */
2520 /* .Lplt_tail: */
2522 /* Fourth bundle: */
2527 };
2528 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2530 /* Subsequent entries in a procedure linkage table look like this. */
2532 {
2537 };
2539 /* PR 28924:
2540 There was a bug due to too high values of THM_MAX_FWD_BRANCH_OFFSET and
2541 THM2_MAX_FWD_BRANCH_OFFSET. The first macro concerns the case when Thumb-2
2542 is not available, and second macro when Thumb-2 is available. Among other
2543 things, they affect the range of branches represented as BLX instructions
2544 in Encoding T2 defined in Section A8.8.25 of the ARM Architecture
2545 Reference Manual ARMv7-A and ARMv7-R edition issue C.d. Such branches are
2546 specified there to have a maximum forward offset that is a multiple of 4.
2547 Previously, the respective values defined here were multiples of 2 but not
2548 4 and they are included in comments for reference. */
2549 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2550 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2551 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 4 + 4)
2552 /* #def THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) - 2 + 4) */
2553 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2554 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 4) + 4)
2555 /* #def THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4) */
2556 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2557 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2558 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2560 enum stub_insn_type
2561 {
2563 THUMB32_TYPE,
2564 ARM_TYPE,
2565 DATA_TYPE
2566 };
2568 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2569 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2570 is inserted in arm_build_one_stub(). */
2571 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2572 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2573 #define THUMB32_MOVT(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVT_ABS, 0}
2574 #define THUMB32_MOVW(X) {(X), THUMB32_TYPE, R_ARM_THM_MOVW_ABS_NC, 0}
2575 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2576 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2577 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2578 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2581 {
2582 bfd_vma data;
2588 /* See note [Thumb nop sequence] when adding a veneer. */
2590 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2591 to reach the stub if necessary. */
2593 {
2596 };
2598 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2599 available. */
2601 {
2605 };
2607 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2609 {
2617 };
2619 /* Thumb -> Thumb long branch stub in thumb2 encoding. Used on armv7. */
2621 {
2624 };
2626 /* Thumb -> Thumb long branch stub. Used for PureCode sections on Thumb2
2627 M-profile architectures. */
2629 {
2633 };
2635 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2636 allowed. */
2638 {
2644 };
2646 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2647 available. */
2649 {
2654 };
2656 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2657 one, when the destination is close enough. */
2659 {
2663 };
2665 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2666 blx to reach the stub if necessary. */
2668 {
2672 };
2674 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2675 blx to reach the stub if necessary. We can not add into pc;
2676 it is not guaranteed to mode switch (different in ARMv6 and
2677 ARMv7). */
2679 {
2684 };
2686 /* V4T ARM -> ARM long branch stub, PIC. */
2688 {
2693 };
2695 /* V4T Thumb -> ARM long branch stub, PIC. */
2697 {
2703 };
2705 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2706 architectures. */
2708 {
2716 };
2718 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2719 allowed. */
2721 {
2728 };
2730 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2731 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2733 {
2737 };
2739 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2740 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2742 {
2748 };
2750 /* NaCl ARM -> ARM long branch stub. */
2752 {
2761 };
2763 /* NaCl ARM -> ARM long branch stub, PIC. */
2765 {
2774 };
2776 /* Stub used for transition to secure state (aka SG veneer). */
2778 {
2781 };
2784 /* Cortex-A8 erratum-workaround stubs. */
2786 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2787 can't use a conditional branch to reach this stub). */
2790 {
2794 };
2796 /* Stub used for b.w and bl.w instructions. */
2799 {
2801 };
2804 {
2806 };
2808 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2809 instruction (which switches to ARM mode) to point to this stub. Jump to the
2810 real destination using an ARM-mode branch. */
2813 {
2815 };
2817 /* For each section group there can be a specially created linker section
2818 to hold the stubs for that group. The name of the stub section is based
2819 upon the name of another section within that group with the suffix below
2820 applied.
2822 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2823 create what appeared to be a linker stub section when it actually
2824 contained user code/data. For example, consider this fragment:
2826 const char * stubborn_problems[] = { "np" };
2828 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2829 section called:
2831 .data.rel.local.stubborn_problems
2833 This then causes problems in arm32_arm_build_stubs() as it triggers:
2835 // Ignore non-stub sections.
2836 if (!strstr (stub_sec->name, STUB_SUFFIX))
2837 continue;
2839 And so the section would be ignored instead of being processed. Hence
2840 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2841 C identifier. */
2844 /* One entry per long/short branch stub defined above. */
2845 #define DEF_STUBS \
2846 DEF_STUB (long_branch_any_any) \
2847 DEF_STUB (long_branch_v4t_arm_thumb) \
2848 DEF_STUB (long_branch_thumb_only) \
2849 DEF_STUB (long_branch_v4t_thumb_thumb) \
2850 DEF_STUB (long_branch_v4t_thumb_arm) \
2851 DEF_STUB (short_branch_v4t_thumb_arm) \
2852 DEF_STUB (long_branch_any_arm_pic) \
2853 DEF_STUB (long_branch_any_thumb_pic) \
2854 DEF_STUB (long_branch_v4t_thumb_thumb_pic) \
2855 DEF_STUB (long_branch_v4t_arm_thumb_pic) \
2856 DEF_STUB (long_branch_v4t_thumb_arm_pic) \
2857 DEF_STUB (long_branch_thumb_only_pic) \
2858 DEF_STUB (long_branch_any_tls_pic) \
2859 DEF_STUB (long_branch_v4t_thumb_tls_pic) \
2860 DEF_STUB (long_branch_arm_nacl) \
2861 DEF_STUB (long_branch_arm_nacl_pic) \
2862 DEF_STUB (cmse_branch_thumb_only) \
2863 DEF_STUB (a8_veneer_b_cond) \
2864 DEF_STUB (a8_veneer_b) \
2865 DEF_STUB (a8_veneer_bl) \
2866 DEF_STUB (a8_veneer_blx) \
2867 DEF_STUB (long_branch_thumb2_only) \
2868 DEF_STUB (long_branch_thumb2_only_pure)
2870 #define DEF_STUB(x) arm_stub_##x,
2871 enum elf32_arm_stub_type
2872 {
2873 arm_stub_none,
2874 DEF_STUBS
2875 max_stub_type
2876 };
2877 #undef DEF_STUB
2879 /* Note the first a8_veneer type. */
2883 {
2888 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2890 {
2892 DEF_STUBS
2893 };
2895 struct elf32_arm_stub_hash_entry
2896 {
2897 /* Base hash table entry structure. */
2900 /* The stub section. */
2903 /* Offset within stub_sec of the beginning of this stub. */
2904 bfd_vma stub_offset;
2906 /* Given the symbol's value and its section we can determine its final
2907 value when building the stubs (so the stub knows where to jump). */
2908 bfd_vma target_value;
2911 /* Same as above but for the source of the branch to the stub. Used for
2912 Cortex-A8 erratum workaround to patch it to branch to the stub. As
2913 such, source section does not need to be recorded since Cortex-A8 erratum
2914 workaround stubs are only generated when both source and target are in the
2915 same section. */
2916 bfd_vma source_value;
2918 /* The instruction which caused this stub to be generated (only valid for
2919 Cortex-A8 erratum workaround stubs at present). */
2922 /* The stub type. */
2924 /* Its encoding size in bytes. */
2926 /* Its template. */
2928 /* The size of the template (number of entries). */
2931 /* The symbol table entry, if any, that this was derived from. */
2934 /* Type of branch. */
2937 /* Where this stub is being called from, or, in the case of combined
2938 stub sections, the first input section in the group. */
2941 /* The name for the local symbol at the start of this stub. The
2942 stub name in the hash table has to be unique; this does not, so
2943 it can be friendlier. */
2945 };
2947 /* Used to build a map of a section. This is required for mixed-endian
2948 code/data. */
2951 {
2952 bfd_vma vma;
2954 }
2955 elf32_arm_section_map;
2957 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2960 {
2961 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2962 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2963 VFP11_ERRATUM_ARM_VENEER,
2964 VFP11_ERRATUM_THUMB_VENEER
2965 }
2966 elf32_vfp11_erratum_type;
2969 {
2971 bfd_vma vma;
2972 union
2973 {
2974 struct
2975 {
2979 struct
2980 {
2985 elf32_vfp11_erratum_type type;
2986 }
2987 elf32_vfp11_erratum_list;
2989 /* Information about a STM32L4XX erratum veneer, or a branch to such a
2990 veneer. */
2992 {
2993 STM32L4XX_ERRATUM_BRANCH_TO_VENEER,
2994 STM32L4XX_ERRATUM_VENEER
2995 }
2996 elf32_stm32l4xx_erratum_type;
2999 {
3001 bfd_vma vma;
3002 union
3003 {
3004 struct
3005 {
3009 struct
3010 {
3015 elf32_stm32l4xx_erratum_type type;
3016 }
3017 elf32_stm32l4xx_erratum_list;
3020 {
3021 DELETE_EXIDX_ENTRY,
3022 INSERT_EXIDX_CANTUNWIND_AT_END
3023 }
3024 arm_unwind_edit_type;
3026 /* A (sorted) list of edits to apply to an unwind table. */
3028 {
3029 arm_unwind_edit_type type;
3030 /* Note: we sometimes want to insert an unwind entry corresponding to a
3031 section different from the one we're currently writing out, so record the
3032 (text) section this edit relates to here. */
3036 }
3037 arm_unwind_table_edit;
3040 {
3041 /* Information about mapping symbols. */
3046 /* Information about CPU errata. */
3052 /* Information about unwind tables. */
3053 union
3054 {
3055 /* Unwind info attached to a text section. */
3056 struct
3057 {
3061 /* Unwind info attached to an .ARM.exidx section. */
3062 struct
3063 {
3068 }
3069 _arm_elf_section_data;
3071 #define elf32_arm_section_data(sec) \
3072 ((_arm_elf_section_data *) elf_section_data (sec))
3074 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
3075 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
3076 so may be created multiple times: we use an array of these entries whilst
3077 relaxing which we can refresh easily, then create stubs for each potentially
3078 erratum-triggering instruction once we've settled on a solution. */
3080 struct a8_erratum_fix
3081 {
3084 bfd_vma offset;
3085 bfd_vma target_offset;
3090 };
3092 /* A table of relocs applied to branches which might trigger Cortex-A8
3093 erratum. */
3095 struct a8_erratum_reloc
3096 {
3097 bfd_vma from;
3098 bfd_vma destination;
3104 };
3106 /* The size of the thread control block. */
3107 #define TCB_SIZE 8
3109 /* ARM-specific information about a PLT entry, over and above the usual
3110 gotplt_union. */
3111 struct arm_plt_info
3112 {
3113 /* We reference count Thumb references to a PLT entry separately,
3114 so that we can emit the Thumb trampoline only if needed. */
3115 bfd_signed_vma thumb_refcount;
3117 /* Some references from Thumb code may be eliminated by BL->BLX
3118 conversion, so record them separately. */
3119 bfd_signed_vma maybe_thumb_refcount;
3121 /* How many of the recorded PLT accesses were from non-call relocations.
3122 This information is useful when deciding whether anything takes the
3123 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
3124 non-call references to the function should resolve directly to the
3125 real runtime target. */
3128 /* Since PLT entries have variable size if the Thumb prologue is
3129 used, we need to record the index into .got.plt instead of
3130 recomputing it from the PLT offset. */
3131 bfd_signed_vma got_offset;
3132 };
3134 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
3135 struct arm_local_iplt_info
3136 {
3137 /* The information that is usually found in the generic ELF part of
3138 the hash table entry. */
3141 /* The information that is usually found in the ARM-specific part of
3142 the hash table entry. */
3145 /* A list of all potential dynamic relocations against this symbol. */
3147 };
3149 /* Structure to handle FDPIC support for local functions. */
3150 struct fdpic_local
3151 {
3155 };
3157 struct elf_arm_obj_tdata
3158 {
3161 /* Zero to warn when linking objects with incompatible enum sizes. */
3164 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
3167 /* The number of entries in each of the arrays in this strcuture.
3168 Used to avoid buffer overruns. */
3169 bfd_size_type num_entries;
3171 /* tls_type for each local got entry. */
3174 /* GOTPLT entries for TLS descriptors. */
3177 /* Information for local symbols that need entries in .iplt. */
3180 /* Maintains FDPIC counters and funcdesc info. */
3182 };
3184 #define elf_arm_tdata(bfd) \
3185 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
3187 #define elf32_arm_num_entries(bfd) \
3188 (elf_arm_tdata (bfd)->num_entries)
3190 #define elf32_arm_local_got_tls_type(bfd) \
3191 (elf_arm_tdata (bfd)->local_got_tls_type)
3193 #define elf32_arm_local_tlsdesc_gotent(bfd) \
3194 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
3196 #define elf32_arm_local_iplt(bfd) \
3197 (elf_arm_tdata (bfd)->local_iplt)
3199 #define elf32_arm_local_fdpic_cnts(bfd) \
3200 (elf_arm_tdata (bfd)->local_fdpic_cnts)
3202 #define is_arm_elf(bfd) \
3203 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
3204 && elf_tdata (bfd) != NULL \
3205 && elf_object_id (bfd) == ARM_ELF_DATA)
3207 static bool
3209 {
3211 ARM_ELF_DATA);
3212 }
3214 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
3216 /* Structure to handle FDPIC support for extern functions. */
3223 };
3225 /* Arm ELF linker hash entry. */
3226 struct elf32_arm_link_hash_entry
3227 {
3230 /* ARM-specific PLT information. */
3233 #define GOT_UNKNOWN 0
3234 #define GOT_NORMAL 1
3235 #define GOT_TLS_GD 2
3236 #define GOT_TLS_IE 4
3237 #define GOT_TLS_GDESC 8
3238 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
3241 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
3246 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
3247 starting at the end of the jump table. */
3248 bfd_vma tlsdesc_got;
3250 /* The symbol marking the real symbol location for exported thumb
3251 symbols with Arm stubs. */
3254 /* A pointer to the most recently used stub hash entry against this
3255 symbol. */
3258 /* Counter for FDPIC relocations against this symbol. */
3260 };
3262 /* Traverse an arm ELF linker hash table. */
3263 #define elf32_arm_link_hash_traverse(table, func, info) \
3264 (elf_link_hash_traverse \
3265 (&(table)->root, \
3266 (bool (*) (struct elf_link_hash_entry *, void *)) (func), \
3267 (info)))
3269 /* Get the ARM elf linker hash table from a link_info structure. */
3270 #define elf32_arm_hash_table(p) \
3271 ((is_elf_hash_table ((p)->hash) \
3272 && elf_hash_table_id (elf_hash_table (p)) == ARM_ELF_DATA) \
3273 ? (struct elf32_arm_link_hash_table *) (p)->hash : NULL)
3275 #define arm_stub_hash_lookup(table, string, create, copy) \
3276 ((struct elf32_arm_stub_hash_entry *) \
3277 bfd_hash_lookup ((table), (string), (create), (copy)))
3279 /* Array to keep track of which stub sections have been created, and
3280 information on stub grouping. */
3281 struct map_stub
3282 {
3283 /* This is the section to which stubs in the group will be
3284 attached. */
3286 /* The stub section. */
3288 };
3290 #define elf32_arm_compute_jump_table_size(htab) \
3291 ((htab)->next_tls_desc_index * 4)
3293 /* ARM ELF linker hash table. */
3294 struct elf32_arm_link_hash_table
3295 {
3296 /* The main hash table. */
3299 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
3300 bfd_size_type thumb_glue_size;
3302 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
3303 bfd_size_type arm_glue_size;
3305 /* The size in bytes of section containing the ARMv4 BX veneers. */
3306 bfd_size_type bx_glue_size;
3308 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
3309 veneer has been populated. */
3312 /* The size in bytes of the section containing glue for VFP11 erratum
3313 veneers. */
3314 bfd_size_type vfp11_erratum_glue_size;
3316 /* The size in bytes of the section containing glue for STM32L4XX erratum
3317 veneers. */
3318 bfd_size_type stm32l4xx_erratum_glue_size;
3320 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
3321 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
3322 elf32_arm_write_section(). */
3326 /* An arbitrary input BFD chosen to hold the glue sections. */
3329 /* Nonzero to output a BE8 image. */
3332 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
3333 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
3336 /* The relocation to use for R_ARM_TARGET2 relocations. */
3339 /* 0 = Ignore R_ARM_V4BX.
3340 1 = Convert BX to MOV PC.
3341 2 = Generate v4 interworing stubs. */
3344 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
3347 /* Whether we should fix the ARM1176 BLX immediate issue. */
3350 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
3353 /* What sort of code sequences we should look for which may trigger the
3354 VFP11 denorm erratum. */
3355 bfd_arm_vfp11_fix vfp11_fix;
3357 /* Global counter for the number of fixes we have emitted. */
3360 /* What sort of code sequences we should look for which may trigger the
3361 STM32L4XX erratum. */
3362 bfd_arm_stm32l4xx_fix stm32l4xx_fix;
3364 /* Global counter for the number of fixes we have emitted. */
3367 /* Nonzero to force PIC branch veneers. */
3370 /* The number of bytes in the initial entry in the PLT. */
3371 bfd_size_type plt_header_size;
3373 /* The number of bytes in the subsequent PLT etries. */
3374 bfd_size_type plt_entry_size;
3376 /* True if the target uses REL relocations. */
3379 /* Nonzero if import library must be a secure gateway import library
3380 as per ARMv8-M Security Extensions. */
3383 /* The import library whose symbols' address must remain stable in
3384 the import library generated. */
3387 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3388 bfd_vma next_tls_desc_index;
3390 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3391 bfd_vma num_tls_desc;
3393 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3396 /* Offset in .plt section of tls_arm_trampoline. */
3397 bfd_vma tls_trampoline;
3399 /* Data for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
3400 union
3401 {
3402 bfd_signed_vma refcount;
3403 bfd_vma offset;
3406 /* For convenience in allocate_dynrelocs. */
3409 /* The amount of space used by the reserved portion of the sgotplt
3410 section, plus whatever space is used by the jump slots. */
3411 bfd_vma sgotplt_jump_table_size;
3413 /* The stub hash table. */
3416 /* Linker stub bfd. */
3419 /* Linker call-backs. */
3424 /* Array to keep track of which stub sections have been created, and
3425 information on stub grouping. */
3428 /* Input stub section holding secure gateway veneers. */
3431 /* Offset in cmse_stub_sec where new SG veneers (not in input import library)
3432 start to be allocated. */
3433 bfd_vma new_cmse_stub_offset;
3435 /* Number of elements in stub_group. */
3438 /* Assorted information used by elf32_arm_size_stubs. */
3443 /* True if the target system uses FDPIC. */
3446 /* Fixup section. Used for FDPIC. */
3448 };
3450 /* Add an FDPIC read-only fixup. */
3451 static void
3453 {
3454 bfd_vma fixup_offset;
3459 }
3463 {
3464 #if GCC_VERSION >= 3004
3466 #else
3470 {
3474 }
3476 #endif
3477 }
3481 {
3482 #if GCC_VERSION >= 3004
3484 #else
3489 {
3491 sum++;
3493 }
3495 #endif
3496 }
3501 static void
3507 bfd_vma addr,
3508 bfd_vma dynreloc_value,
3509 bfd_vma seg)
3510 {
3512 {
3517 {
3519 Elf_Internal_Rela outrel;
3528 }
3529 else
3530 {
3544 }
3546 }
3547 }
3549 /* Create an entry in an ARM ELF linker hash table. */
3555 {
3559 /* Allocate the structure if it has not already been allocated by a
3560 subclass. */
3567 /* Call the allocation method of the superclass. */
3572 {
3589 }
3592 }
3594 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3595 symbols. */
3597 static bool
3599 {
3601 {
3602 bfd_size_type num_syms;
3606 /* Whilst it might be tempting to allocate a single block of memory and
3607 then divide it up amoungst the arrays in the elf_arm_obj_tdata
3608 structure, this interferes with the work of memory checkers looking
3609 for buffer overruns. So allocate each array individually. */
3645 #if GCC_VERSION >= 3000
3654 #endif
3655 }
3657 }
3659 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3660 to input bfd ABFD. Create the information if it doesn't already exist.
3661 Return null if an allocation fails. */
3665 {
3677 }
3679 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3680 in ABFD's symbol table. If the symbol is global, H points to its
3681 hash table entry, otherwise H is null.
3683 Return true if the symbol does have PLT information. When returning
3684 true, point *ROOT_PLT at the target-independent reference count/offset
3685 union and *ARM_PLT at the ARM-specific information. */
3687 static bool
3692 {
3699 {
3703 }
3718 }
3722 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3723 before it. */
3725 static bool
3728 {
3735 }
3737 /* Return a pointer to the head of the dynamic reloc list that should
3738 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3739 ABFD's symbol table. Return null if an error occurs. */
3744 {
3746 {
3753 }
3754 else
3755 {
3756 /* Track dynamic relocs needed for local syms too.
3757 We really need local syms available to do this
3758 easily. Oh well. */
3768 }
3769 }
3771 /* Initialize an entry in the stub hash table. */
3777 {
3778 /* Allocate the structure if it has not already been allocated by a
3779 subclass. */
3781 {
3786 }
3788 /* Call the allocation method of the superclass. */
3791 {
3794 /* Initialize the local fields. */
3809 }
3812 }
3814 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3815 shortcuts to them in our hash table. */
3817 static bool
3819 {
3829 /* Also create .rofixup. */
3831 {
3838 }
3841 }
3843 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3845 static bool
3847 {
3852 flagword flags;
3860 {
3867 }
3870 {
3878 }
3881 {
3887 }
3889 }
3891 /* Determine if we're dealing with a Thumb only architecture. */
3893 static bool
3895 {
3898 Tag_CPU_arch_profile);
3905 /* Force return logic to be reviewed for each new architecture. */
3917 }
3919 /* Determine if we're dealing with a Thumb-2 object. */
3921 static bool
3923 {
3926 Tag_THUMB_ISA_use);
3928 /* No use of thumb permitted, or a legacy thumb-1/2 definition. */
3932 /* Variant of thumb is described by the architecture tag. */
3935 /* Force return logic to be reviewed for each new architecture. */
3945 }
3947 /* Determine whether Thumb-2 BL instruction is available. */
3949 static bool
3951 {
3955 /* Force return logic to be reviewed for each new architecture. */
3958 /* Architecture was introduced after ARMv6T2 (eg. ARMv6-M). */
3961 }
3963 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3964 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3965 hash table. */
3967 static bool
3969 {
3983 {
3988 {
3990 htab->plt_entry_size
3992 }
3993 else
3994 {
3995 htab->plt_header_size
3997 htab->plt_entry_size
3999 }
4003 }
4004 else
4005 {
4006 /* PR ld/16017
4007 Test for thumb only architectures. Note - we cannot just call
4008 using_thumb_only() as the attributes in the output bfd have not been
4009 initialised at this point, so instead we use the input bfd. */
4014 {
4017 }
4019 }
4025 else
4027 }
4036 }
4038 /* Copy the extra info we tack onto an elf_link_hash_entry. */
4040 static void
4044 {
4051 {
4052 /* Copy over PLT info. */
4060 /* Copy FDPIC counters. */
4065 /* We should only allocate a function to .iplt once the final
4066 symbol information is known. */
4070 {
4073 }
4074 }
4077 }
4079 /* Destroy an ARM elf linker hash table. */
4081 static void
4083 {
4089 }
4091 /* Create an ARM elf linker hash table. */
4095 {
4104 elf32_arm_link_hash_newfunc,
4106 ARM_ELF_DATA))
4107 {
4110 }
4114 #ifdef FOUR_WORD_PLT
4117 #else
4120 #endif
4127 {
4130 }
4134 }
4136 /* Determine what kind of NOPs are available. */
4138 static bool
4140 {
4142 Tag_CPU_arch);
4144 /* Force return logic to be reviewed for each new architecture. */
4153 }
4155 static bool
4157 {
4159 {
4176 }
4177 }
4179 /* Determine the type of stub needed, if any, for a call. */
4181 static enum elf32_arm_stub_type
4188 bfd_vma destination,
4192 {
4193 bfd_vma location;
4194 bfd_signed_vma branch_offset;
4219 /* True for architectures that implement the thumb2 movw instruction. */
4222 /* Determine where the call point is. */
4229 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
4230 are considering a function call relocation. */
4236 /* For TLS call relocs, it is the caller's responsibility to provide
4237 the address of the appropriate trampoline. */
4244 {
4249 else
4252 {
4255 /* Note when dealing with PLT entries: the main PLT stub is in
4256 ARM mode, so if the branch is in Thumb mode, another
4257 Thumb->ARM stub will be inserted later just before the ARM
4258 PLT stub. If a long branch stub is needed, we'll add a
4259 Thumb->Arm one and branch directly to the ARM PLT entry.
4260 Here, we have to check if a pre-PLT Thumb->ARM stub
4261 is needed and if it will be close enough. */
4268 /* Thumb branch/call to PLT: it can become a branch to ARM
4269 or to Thumb. We must perform the same checks and
4270 corrections as in elf32_arm_final_link_relocate. */
4273 {
4277 {
4278 /* If the Thumb BLX instruction is available, convert
4279 the BL to a BLX instruction to call the ARM-mode
4280 PLT entry. */
4282 }
4283 else
4284 {
4286 /* Target the Thumb stub before the ARM PLT entry. */
4289 }
4290 }
4291 else
4292 {
4294 }
4295 }
4296 }
4297 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
4304 {
4305 /* Handle cases where:
4306 - this call goes too far (different Thumb/Thumb2 max
4307 distance)
4308 - it's a Thumb->Arm call and blx is not available, or it's a
4309 Thumb->Arm branch (not bl). A stub is needed in this case,
4310 but only if this call is not through a PLT entry. Indeed,
4311 PLT stubs handle mode switching already. */
4315 || (thumb2_bl
4318 || (thumb2
4328 {
4329 /* If we need to insert a Thumb-Thumb long branch stub to a
4330 PLT, use one that branches directly to the ARM PLT
4331 stub. If we pretended we'd use the pre-PLT Thumb->ARM
4332 stub, undo this now. */
4334 {
4337 }
4340 {
4341 /* Thumb to thumb. */
4343 {
4345 _bfd_error_handler
4347 " section with SHF_ARM_PURECODE section"
4348 " attribute is only supported for M-profile"
4353 /* PIC stubs. */
4356 /* V5T and above. Stub starts with ARM code, so
4357 we must be able to switch mode before
4358 reaching it, which is only possible for 'bl'
4359 (ie R_ARM_THM_CALL relocation). */
4360 ? arm_stub_long_branch_any_thumb_pic
4361 /* On V4T, use Thumb code only. */
4364 /* non-PIC stubs. */
4367 /* V5T and above. */
4368 ? arm_stub_long_branch_any_any
4369 /* V4T. */
4371 }
4372 else
4373 {
4376 else
4377 {
4379 _bfd_error_handler
4381 " section with SHF_ARM_PURECODE section"
4382 " attribute is only supported for M-profile"
4387 /* PIC stub. */
4388 ? arm_stub_long_branch_thumb_only_pic
4389 /* non-PIC stub. */
4392 }
4393 }
4394 }
4395 else
4396 {
4398 _bfd_error_handler
4400 " section with SHF_ARM_PURECODE section"
4405 /* Thumb to arm. */
4409 {
4410 _bfd_error_handler
4414 }
4416 stub_type =
4418 /* PIC stubs. */
4420 /* TLS PIC stubs. */
4424 /* V5T PIC and above. */
4425 ? arm_stub_long_branch_any_arm_pic
4426 /* V4T PIC stub. */
4429 /* non-PIC stubs. */
4431 /* V5T and above. */
4432 ? arm_stub_long_branch_any_any
4433 /* V4T. */
4436 /* Handle v4t short branches. */
4441 }
4442 }
4443 }
4448 {
4450 _bfd_error_handler
4452 " section with SHF_ARM_PURECODE section"
4453 " attribute is only supported for M-profile"
4457 {
4458 /* Arm to thumb. */
4463 {
4464 _bfd_error_handler
4468 }
4470 /* We have an extra 2-bytes reach because of
4471 the mode change (bit 24 (H) of BLX encoding). */
4477 {
4479 /* PIC stubs. */
4481 /* V5T and above. */
4482 ? arm_stub_long_branch_any_thumb_pic
4483 /* V4T stub. */
4486 /* non-PIC stubs. */
4488 /* V5T and above. */
4489 ? arm_stub_long_branch_any_any
4490 /* V4T. */
4492 }
4493 }
4494 else
4495 {
4496 /* Arm to arm. */
4499 {
4500 stub_type =
4502 /* PIC stubs. */
4504 /* TLS PIC Stub. */
4505 ? arm_stub_long_branch_any_tls_pic
4507 ? arm_stub_long_branch_arm_nacl_pic
4509 /* non-PIC stubs. */
4511 ? arm_stub_long_branch_arm_nacl
4513 }
4514 }
4515 }
4517 /* If a stub is needed, record the actual destination type. */
4522 }
4524 /* Build a name for an entry in the stub hash table. */
4532 {
4534 bfd_size_type len;
4537 {
4546 }
4547 else
4548 {
4560 }
4563 }
4565 /* Look up an entry in the stub hash. Stub entries are cached because
4566 creating the stub name takes a bit of time. */
4575 {
4583 /* If the input section is the CMSE stubs one and it needs a long
4584 branch stub to reach it's final destination, give up with an
4585 error message: this is not supported. See PR ld/24709. */
4587 {
4593 CMSE_STUB_NAME,
4599 /* Exit, rather than leave incompletely processed
4600 relocations. */
4602 }
4604 /* If this input section is part of a group of sections sharing one
4605 stub section, then use the id of the first section in the group.
4606 Stub names need to include a section id, as there may well be
4607 more than one stub used to reach say, printf, and we need to
4608 distinguish between them. */
4616 {
4618 }
4619 else
4620 {
4633 }
4636 }
4638 /* Whether veneers of type STUB_TYPE require to be in a dedicated output
4639 section. */
4641 static bool
4643 {
4648 {
4654 }
4657 }
4659 /* Required alignment (as a power of 2) for the dedicated section holding
4660 veneers of type STUB_TYPE, or 0 if veneers of this type are interspersed
4661 with input sections. */
4663 static int
4664 arm_dedicated_stub_output_section_required_alignment
4666 {
4671 {
4672 /* Vectors of Secure Gateway veneers must be aligned on 32byte
4673 boundary. */
4680 }
4683 }
4685 /* Name of the dedicated output section to put veneers of type STUB_TYPE, or
4686 NULL if veneers of this type are interspersed with input sections. */
4690 {
4695 {
4702 }
4705 }
4707 /* If veneers of type STUB_TYPE should go in a dedicated output section,
4708 returns the address of the hash table field in HTAB holding a pointer to the
4709 corresponding input section. Otherwise, returns NULL. */
4714 {
4719 {
4726 }
4729 }
4731 /* Find or create a stub section to contain a stub of type STUB_TYPE. SECTION
4732 is the section that branch into veneer and can be NULL if stub should go in
4733 a dedicated output section. Returns a pointer to the stub section, and the
4734 section to which the stub section will be attached (in *LINK_SEC_P).
4735 LINK_SEC_P may be NULL. */
4741 {
4749 {
4759 {
4763 }
4764 }
4765 else
4766 {
4776 }
4779 {
4781 bfd_size_type len;
4793 align);
4800 }
4809 }
4811 /* Add a new stub entry to the stub hash. Not all fields of the new
4812 stub entry are initialised. */
4818 {
4824 stub_type);
4828 /* Enter this entry into the linker stub hash table. */
4832 {
4838 }
4845 }
4847 /* Store an Arm insn into an output section not processed by
4848 elf32_arm_write_section. */
4850 static void
4853 {
4856 else
4858 }
4860 /* Store a 16-bit Thumb insn into an output section not processed by
4861 elf32_arm_write_section. */
4863 static void
4866 {
4869 else
4871 }
4873 /* Store a Thumb2 insn into an output section not processed by
4874 elf32_arm_write_section. */
4876 static void
4879 {
4880 /* T2 instructions are 16-bit streamed. */
4882 {
4885 }
4886 else
4887 {
4890 }
4891 }
4893 /* If it's possible to change R_TYPE to a more efficient access
4894 model, return the new reloc type. */
4896 static unsigned
4899 {
4906 /* We do not support relaxations for Old TLS models. */
4908 {
4915 }
4918 }
4920 static bfd_reloc_status_type elf32_arm_final_link_relocate
4926 static unsigned int
4928 {
4930 {
4962 }
4963 }
4965 /* Returns whether stubs of type STUB_TYPE take over the symbol they are
4966 veneering (TRUE) or have their own symbol (FALSE). */
4968 static bool
4970 {
4975 {
4981 }
4984 }
4986 /* Returns the padding needed for the dedicated section used stubs of type
4987 STUB_TYPE. */
4989 static int
4991 {
4996 {
5002 }
5005 }
5007 /* If veneers of type STUB_TYPE should go in a dedicated output section,
5008 returns the address of the hash table field in HTAB holding the offset at
5009 which new veneers should be layed out in the stub section. */
5014 {
5016 {
5023 }
5024 }
5026 static bool
5029 {
5030 #define MAXRELOCS 3
5038 bfd_vma sym_value;
5048 /* Massage our args to the form they really have. */
5052 /* Fail if the target section could not be assigned to an output
5053 section. The user should fix his linker script. */
5068 /* We have to do less-strictly-aligned fixes last. */
5071 /* Assign a slot at the end of section if none assigned yet. */
5073 {
5076 }
5081 /* This is the address of the stub destination. */
5091 {
5093 {
5095 {
5098 {
5099 /* We've borrowed the reloc_addend field to mean we should
5100 insert a condition code into this (Thumb-1 branch)
5101 instruction. See THUMB16_BCOND_INSN. */
5104 }
5107 }
5117 {
5120 }
5127 /* Handle cases where the target is encoded within the
5128 instruction. */
5130 {
5133 }
5147 }
5148 }
5153 /* Stub size has already been computed in arm_size_one_stub. Check
5154 consistency. */
5157 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
5161 /* Assume non empty slots have at least one and at most MAXRELOCS entries
5162 to relocate in each stub. */
5163 removed_sg_veneer =
5168 {
5169 Elf_Internal_Rela rel;
5172 bfd_vma points_to =
5181 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
5182 template should refer back to the instruction after the original
5183 branch. We use target_section as Cortex-A8 erratum workaround stubs
5184 are only generated when both source and target are in the same
5185 section. */
5197 }
5200 #undef MAXRELOCS
5201 }
5203 /* Calculate the template, template size and instruction size for a stub.
5204 Return value is the instruction size. */
5206 static unsigned int
5210 {
5225 {
5227 {
5241 }
5242 }
5245 }
5247 /* As above, but don't actually build the stub. Just bump offset so
5248 we know stub section sizes. */
5250 static bool
5253 {
5258 /* Massage our args to the form they really have. */
5267 /* Initialized to -1. Null size indicates an empty slot full of zeros. */
5269 {
5273 }
5275 /* Already accounted for. */
5283 }
5285 /* External entry points for sizing and building linker stubs. */
5287 /* Set up various things so that we can make a list of input sections
5288 for each output section included in the link. Returns -1 on error,
5289 0 when no stubs will be needed, and 1 on success. */
5291 int
5294 {
5306 /* Count the number of input BFDs and find the top input section id. */
5310 {
5315 {
5318 }
5319 }
5328 /* We can't use output_bfd->section_count here to find the top output
5329 section index as some sections may have been removed, and
5330 _bfd_strip_section_from_output doesn't renumber the indices. */
5334 {
5337 }
5346 /* For sections we aren't interested in, mark their entries with a
5347 value we can check later. */
5349 do
5356 {
5359 }
5362 }
5364 /* The linker repeatedly calls this function for each input section,
5365 in the order that input sections are linked into output sections.
5366 Build lists of input sections to determine groupings between which
5367 we may insert linker stubs. */
5369 void
5372 {
5379 {
5383 {
5384 /* Steal the link_sec pointer for our list. */
5385 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
5386 /* This happens to make the list in reverse order,
5387 which we reverse later. */
5390 }
5391 }
5392 }
5394 /* See whether we can group stub sections together. Grouping stub
5395 sections may result in fewer stubs. More importantly, we need to
5396 put all .init* and .fini* stubs at the end of the .init or
5397 .fini output sections respectively, because glibc splits the
5398 _init and _fini functions into multiple parts. Putting a stub in
5399 the middle of a function is not a good idea. */
5401 static void
5403 bfd_size_type stub_group_size,
5405 {
5408 do
5409 {
5416 /* Reverse the list: we must avoid placing stubs at the
5417 beginning of the section because the beginning of the text
5418 section may be required for an interrupt vector in bare metal
5419 code. */
5420 #define NEXT_SEC PREV_SEC
5423 {
5424 /* Pop from tail. */
5428 /* Push on head. */
5431 }
5434 {
5438 bfd_vma end_of_next;
5442 {
5446 /* End of NEXT is too far from start, so stop. */
5448 /* Add NEXT to the group. */
5450 }
5452 /* OK, the size from the start to the start of CURR is less
5453 than stub_group_size and thus can be handled by one stub
5454 section. (Or the head section is itself larger than
5455 stub_group_size, in which case we may be toast.)
5456 We should really be keeping track of the total size of
5457 stubs added here, as stubs contribute to the final output
5458 section size. */
5459 do
5460 {
5462 /* Set up this stub group. */
5464 }
5467 /* But wait, there's more! Input sections up to stub_group_size
5468 bytes after the stub section can be handled by it too. */
5470 {
5474 {
5477 /* End of NEXT is too far from stubs, so stop. */
5479 /* Add NEXT to the stub group. */
5483 }
5484 }
5486 }
5487 }
5491 #undef PREV_SEC
5492 #undef NEXT_SEC
5493 }
5495 /* Comparison function for sorting/searching relocations relating to Cortex-A8
5496 erratum fix. */
5498 static int
5500 {
5508 else
5510 }
5515 /* Helper function to scan code for sequences which might trigger the Cortex-A8
5516 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
5517 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
5518 otherwise. */
5520 static bool
5530 {
5543 {
5547 bfd_vma base_vma;
5566 {
5577 /* Span is entirely within a single 4KB region: skip scanning. */
5582 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
5584 * The opcode is BLX.W, BL.W, B.W, Bcc.W
5585 * The branch target is in the same 4KB region as the
5586 first half of the branch.
5587 * The instruction before the branch is a 32-bit
5588 length non-branch instruction. */
5590 {
5599 {
5600 /* Load the rest of the insn (in manual-friendly order). */
5603 /* Encoding T4: B<c>.W. */
5605 /* Encoding T1: BL<c>.W. */
5607 /* Encoding T2: BLX<c>.W. */
5609 /* Encoding T3: B<c>.W (not permitted in IT block). */
5612 }
5617 && insn_32bit
5618 && is_32bit_branch
5619 && last_was_32bit
5621 {
5625 bfd_vma target;
5637 {
5641 /* We don't care about the error returned from this
5642 function, only if there is glue or not. */
5649 /* Keep a simpler condition, for the sake of clarity. */
5655 {
5659 else
5661 }
5662 }
5664 /* Check if we have an offending branch instruction. */
5667 /* We've already made a stub for this instruction, e.g.
5668 it's a long branch or a Thumb->ARM stub. Assume that
5669 stub will suffice to work around the A8 erratum (see
5670 setting of always_after_branch above). */
5671 ;
5673 {
5682 }
5684 {
5704 }
5707 {
5710 /* The original instruction is a BL, but the target is
5711 an ARM instruction. If we were not making a stub,
5712 the BL would have been converted to a BLX. Use the
5713 BLX stub instead in that case. */
5716 {
5720 }
5721 /* Conversely, if the original instruction was
5722 BLX but the target is Thumb mode, use the BL
5723 stub. */
5726 {
5730 }
5735 /* If we found a relocation, use the proper destination,
5736 not the offset in the (unrelocated) instruction.
5737 Note this is always done if we switched the stub type
5738 above. */
5740 offset =
5743 /* If the stub will use a Thumb-mode branch to a
5744 PLT target, redirect it to the preceding Thumb
5745 entry point. */
5751 /* The BLX stub is ARM-mode code. Adjust the offset to
5752 take the different PC value (+8 instead of +4) into
5753 account. */
5758 {
5762 {
5768 }
5771 {
5772 /* If we're doing a subsequent scan,
5773 check if we've found the same fix as
5774 before, and try and reuse the stub
5775 name. */
5779 {
5783 }
5784 }
5787 {
5791 }
5804 num_a8_fixes++;
5805 }
5806 }
5807 }
5812 }
5813 }
5817 }
5824 }
5826 /* Create or update a stub entry depending on whether the stub can already be
5827 found in HTAB. The stub is identified by:
5828 - its type STUB_TYPE
5829 - its source branch (note that several can share the same stub) whose
5830 section and relocation (if any) are given by SECTION and IRELA
5831 respectively
5832 - its target symbol whose input section, hash, name, value and branch type
5833 are given in SYM_SEC, HASH, SYM_NAME, SYM_VALUE and BRANCH_TYPE
5834 respectively
5836 If found, the value of the stub's target symbol is updated from SYM_VALUE
5837 and *NEW_STUB is set to FALSE. Otherwise, *NEW_STUB is set to
5838 TRUE and the stub entry is initialized.
5840 Returns the stub that was created or updated, or NULL if an error
5841 occurred. */
5850 {
5862 else
5863 {
5868 /* Support for grouping stub sections. */
5871 /* Get the name of this stub. */
5873 stub_type);
5876 }
5880 /* The proper stub has already been created, just update its value. */
5882 {
5887 }
5891 {
5895 }
5905 else
5906 {
5913 {
5916 }
5918 /* For historical reasons, use the existing names for ARM-to-Thumb and
5919 Thumb-to-ARM stubs. */
5930 else
5932 }
5936 }
5938 /* Scan symbols in INPUT_BFD to identify secure entry functions needing a
5939 gateway veneer to transition from non secure to secure state and create them
5940 accordingly.
5942 "ARMv8-M Security Extensions: Requirements on Development Tools" document
5943 defines the conditions that govern Secure Gateway veneer creation for a
5944 given symbol <SYM> as follows:
5945 - it has function type
5946 - it has non local binding
5947 - a symbol named __acle_se_<SYM> (called special symbol) exists with the
5948 same type, binding and value as <SYM> (called normal symbol).
5949 An entry function can handle secure state transition itself in which case
5950 its special symbol would have a different value from the normal symbol.
5952 OUT_ATTR gives the output attributes, SYM_HASHES the symbol index to hash
5953 entry mapping while HTAB gives the name to hash entry mapping.
5954 *CMSE_STUB_CREATED is increased by the number of secure gateway veneer
5955 created.
5957 The return value gives whether a stub failed to be allocated. */
5959 static bool
5963 {
5971 bfd_vma sym_value;
5987 NULL);
5991 /* Scan symbols. */
5993 {
5997 {
6005 /* Special symbol with local binding. */
6007 }
6008 else
6009 {
6018 /* Special symbol has incorrect binding or type. */
6023 }
6026 {
6032 }
6035 {
6042 }
6048 /* No associated normal symbol or it is neither global nor weak. */
6053 {
6054 /* Initialize here to avoid warning about use of possibly
6055 uninitialized variable. */
6059 {
6060 /* Searching for a normal symbol with local binding. */
6062 {
6063 lsym_name =
6069 }
6070 }
6073 {
6074 _bfd_error_handler
6078 }
6079 else
6080 _bfd_error_handler
6085 }
6091 {
6092 _bfd_error_handler
6096 }
6100 /* If this section is a link-once section that will be discarded, then
6101 don't create any stubs. */
6103 {
6104 _bfd_error_handler
6107 }
6110 {
6111 _bfd_error_handler
6114 }
6119 stub_entry
6126 else
6127 {
6130 }
6131 }
6136 }
6138 /* Return TRUE iff a symbol identified by its linker HASH entry is a secure
6139 code entry function, ie can be called from non secure code without using a
6140 veneer. */
6142 static bool
6144 {
6148 file_ptr offset;
6151 /* Defined symbol of function type. */
6158 /* Read first instruction. */
6168 /* Starts by SG instruction. */
6170 }
6172 /* Output the name (in symbol table) of the veneer GEN_ENTRY if it is a new
6173 secure gateway veneers (ie. the veneers was not in the input import library)
6174 and there is no output import library (GEN_INFO->out_implib_bfd is NULL. */
6176 static bool
6178 {
6182 /* Massage our args to the form they really have. */
6196 }
6198 /* Set offset of each secure gateway veneers so that its address remain
6199 identical to the one in the input import library referred by
6200 HTAB->in_implib_bfd. A warning is issued for veneers that disappeared
6201 (present in input import library but absent from the executable being
6202 linked) or if new veneers appeared and there is no output import library
6203 (INFO->out_implib_bfd is NULL and *CMSE_STUB_CREATED is bigger than the
6204 number of secure gateway veneers found in the input import library.
6206 The function returns whether an error occurred. If no error occurred,
6207 *CMSE_STUB_CREATED gives the number of SG veneers created by both cmse_scan
6208 and this function and HTAB->new_cmse_stub_offset is set to the biggest
6209 veneer observed set for new veneers to be layed out after. */
6211 static bool
6215 {
6218 flagword flags;
6225 bfd_size_type cmse_stub_size;
6234 /* No input secure gateway import library. */
6240 {
6244 }
6246 /* Get symbol table size. */
6251 /* Read in the input secure gateway import library's symbol table. */
6258 {
6261 }
6264 cmse_stub_size =
6268 out_sec_name =
6270 stub_out_sec =
6275 /* Set addresses of veneers mentionned in input secure gateway import
6276 library's symbol table. */
6278 {
6289 {
6291 "symbol should be absolute, global and "
6296 }
6305 /* Stub entry should have been created by cmse_scan or the symbol be of
6306 a secure function callable from non secure code. */
6308 {
6311 _bfd_error_handler
6315 stub_entry
6322 else
6323 {
6325 new_cmse_stubs_created++;
6327 }
6330 }
6331 /* Symbol found is not callable from non secure code. */
6333 {
6335 {
6337 sym_name);
6339 }
6341 }
6342 else
6343 {
6344 /* Only stubs for SG veneers should have been created. */
6347 /* Check visibility hasn't changed. */
6350 _bfd_error_handler
6352 sym_name);
6355 }
6357 /* Size should match that of a SG veneer. */
6359 {
6363 }
6365 /* Previous veneer address is before current SG veneer section. */
6367 {
6368 /* Avoid offset underflow. */
6373 }
6375 /* Complain if stub offset not a multiple of stub size. */
6377 {
6378 _bfd_error_handler
6382 }
6387 new_cmse_stubs_created--;
6393 }
6396 {
6398 _bfd_error_handler
6402 }
6405 {
6406 _bfd_error_handler
6408 out_sec_name);
6410 }
6412 free_sym_buf:
6415 }
6417 /* Determine and set the size of the stub section for a final link.
6419 The basic idea here is to examine all the relocations looking for
6420 PC-relative calls to a target that is unreachable with a "bl"
6421 instruction. */
6423 bool
6427 bfd_signed_vma group_size,
6429 asection *,
6432 {
6436 bfd_size_type stub_group_size;
6448 {
6453 }
6455 /* Propagate mach to stub bfd, because it may not have been
6456 finalized when we created stub_bfd. */
6460 /* Stash our params away. */
6469 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
6470 as the first half of a 32-bit branch straddling two 4K pages. This is a
6471 crude way of enforcing that. */
6477 else
6481 {
6482 /* Default values. */
6483 /* Thumb branch range is +-4MB has to be used as the default
6484 maximum size (a given section can contain both ARM and Thumb
6485 code, so the worst case has to be taken into account).
6487 This value is 24K less than that, which allows for 2025
6488 12-byte stubs. If we exceed that, then we will fail to link.
6489 The user will have to relink with an explicit group size
6490 option. */
6492 }
6496 /* If we're applying the cortex A8 fix, we need to determine the
6497 program header size now, because we cannot change it later --
6498 that could alter section placements. Notice the A8 erratum fix
6499 ends up requiring the section addresses to remain unchanged
6500 modulo the page size. That's something we cannot represent
6501 inside BFD, and we don't want to force the section alignment to
6502 be the page size. */
6507 {
6519 {
6533 /* We'll need the symbol table in a second. */
6538 /* Limit scan of symbols to object file whose profile is
6539 Microcontroller to not hinder performance in the general case. */
6541 {
6551 }
6553 /* Walk over each section attached to the input bfd. */
6557 {
6560 /* If there aren't any relocs, then there's nothing more
6561 to do. */
6567 /* If this section is a link-once section that will be
6568 discarded, then don't create any stubs. */
6573 /* Get the relocs. */
6574 internal_relocs
6580 /* Now examine each relocation. */
6584 {
6587 bfd_vma sym_value;
6588 bfd_vma destination;
6599 {
6601 error_ret_free_internal:
6604 /* Fall through. */
6605 error_ret_free_local:
6609 }
6613 hash = elf32_arm_hash_entry
6617 /* Only look for stubs on branch instructions, or
6618 non-relaxed TLSCALL */
6632 : (elf32_arm_local_got_tls_type
6637 /* Now determine the call target, its name, value,
6638 section. */
6646 {
6647 /* A non-relaxed TLS call. The target is the
6648 plt-resident trampoline and nothing to do
6649 with the symbol. */
6656 }
6658 {
6659 /* It's a local symbol. */
6663 {
6664 local_syms
6667 local_syms
6673 }
6682 else
6683 sym_sec =
6687 /* This is an undefined symbol. It can never
6688 be resolved. */
6697 branch_type =
6699 sym_name
6703 }
6704 else
6705 {
6706 /* It's an external symbol. */
6714 {
6721 /* For a destination in a shared library,
6722 use the PLT stub as target address to
6723 decide whether a branch stub is
6724 needed. */
6729 {
6733 destination = (sym_value
6736 }
6741 }
6744 {
6745 /* For a shared library, use the PLT stub as
6746 target address to decide whether a long
6747 branch stub is needed.
6748 For absolute code, they cannot be handled. */
6756 {
6760 destination = (sym_value
6763 }
6764 else
6766 }
6767 else
6768 {
6771 }
6773 branch_type =
6776 }
6778 do
6779 {
6783 /* Determine what (if any) linker stub is needed. */
6791 /* We've either created a stub for this reloc already,
6792 or we are about to. */
6793 stub_entry =
6804 else
6806 }
6809 /* Look for relocations which might trigger Cortex-A8
6810 erratum. */
6816 {
6822 {
6823 /* Found a candidate. Note we haven't checked the
6824 destination is within 4K here: if we do so (and
6825 don't create an entry in a8_relocs) we can't tell
6826 that a branch should have been relocated when
6827 scanning later. */
6829 {
6835 }
6845 num_a8_relocs++;
6846 }
6847 }
6848 }
6850 /* We're done with the internal relocs, free them. */
6853 }
6856 {
6857 /* Sort relocs which might apply to Cortex-A8 erratum. */
6862 /* Scan for branches which might trigger Cortex-A8 erratum. */
6869 }
6873 {
6876 else
6878 }
6879 }
6892 /* OK, we've added some stubs. Find out the new size of the
6893 stub sections. */
6897 {
6898 /* Ignore non-stub sections. */
6903 }
6905 /* Add new SG veneers after those already in the input import
6906 library. */
6908 stub_type++)
6909 {
6921 }
6923 /* Compute stub section size, considering padding. */
6926 stub_type++)
6927 {
6933 /* Skip if no stub input section or no stub section padding
6934 required. */
6937 /* Stub section padding required but no dedicated section. */
6943 }
6945 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
6948 {
6955 stub_sec->size
6957 NULL);
6958 }
6961 /* Ask the linker to do its stuff. */
6964 }
6966 /* Add stubs for Cortex-A8 erratum fixes now. */
6968 {
6970 {
6983 {
6987 }
7006 }
7008 /* Stash the Cortex-A8 erratum fix array for use later in
7009 elf32_arm_write_section(). */
7012 }
7013 else
7014 {
7017 }
7019 }
7021 /* Build all the stubs associated with the current output file. The
7022 stubs are kept in a hash table attached to the main linker hash
7023 table. We also set up the .plt entries for statically linked PIC
7024 functions here. This function is called via arm_elf_finish in the
7025 linker. */
7027 bool
7029 {
7042 {
7043 bfd_size_type size;
7045 /* Ignore non-stub sections. */
7049 /* Allocate memory to hold the linker stubs. Zeroing the stub sections
7050 must at least be done for stub section requiring padding and for SG
7051 veneers to ensure that a non secure code branching to a removed SG
7052 veneer causes an error. */
7059 }
7061 /* Add new SG veneers after those already in the input import library. */
7063 {
7075 }
7077 /* Build the stubs as directed by the stub hash table. */
7081 {
7082 /* Place the cortex a8 stubs last. */
7085 }
7088 }
7090 /* Locate the Thumb encoded calling stub for NAME. */
7096 {
7101 /* We need a pointer to the armelf specific hash table. */
7113 hash = elf_link_hash_lookup
7117 {
7122 }
7127 }
7129 /* Locate the ARM encoded calling stub for NAME. */
7135 {
7140 /* We need a pointer to the elfarm specific hash table. */
7151 myh = elf_link_hash_lookup
7155 {
7160 }
7164 }
7166 /* ARM->Thumb glue (static images):
7168 .arm
7169 __func_from_arm:
7170 ldr r12, __func_addr
7171 bx r12
7172 __func_addr:
7173 .word func @ behave as if you saw a ARM_32 reloc.
7175 (v5t static images)
7176 .arm
7177 __func_from_arm:
7178 ldr pc, __func_addr
7179 __func_addr:
7180 .word func @ behave as if you saw a ARM_32 reloc.
7182 (relocatable images)
7183 .arm
7184 __func_from_arm:
7185 ldr r12, __func_offset
7186 add r12, r12, pc
7187 bx r12
7188 __func_offset:
7189 .word func - . */
7191 #define ARM2THUMB_STATIC_GLUE_SIZE 12
7196 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
7200 #define ARM2THUMB_PIC_GLUE_SIZE 16
7205 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
7207 .thumb .thumb
7208 .align 2 .align 2
7209 __func_from_thumb: __func_from_thumb:
7210 bx pc push {r6, lr}
7211 nop ldr r6, __func_addr
7212 .arm mov lr, pc
7213 b func bx r6
7214 .arm
7215 ;; back_to_thumb
7216 ldmia r13! {r6, lr}
7217 bx lr
7218 __func_addr:
7219 .word func */
7221 #define THUMB2ARM_GLUE_SIZE 8
7226 #define VFP11_ERRATUM_VENEER_SIZE 8
7227 #define STM32L4XX_ERRATUM_LDM_VENEER_SIZE 16
7228 #define STM32L4XX_ERRATUM_VLDM_VENEER_SIZE 24
7230 #define ARM_BX_VENEER_SIZE 12
7235 #ifndef ELFARM_NABI_C_INCLUDED
7236 static void
7238 {
7243 {
7244 /* Do not include empty glue sections in the output. */
7246 {
7250 }
7252 }
7263 }
7265 bool
7267 {
7275 ARM2THUMB_GLUE_SECTION_NAME);
7279 THUMB2ARM_GLUE_SECTION_NAME);
7283 VFP11_ERRATUM_VENEER_SECTION_NAME);
7287 STM32L4XX_ERRATUM_VENEER_SECTION_NAME);
7291 ARM_BX_GLUE_SECTION_NAME);
7294 }
7296 /* Allocate space and symbols for calling a Thumb function from Arm mode.
7297 returns the symbol identifying the stub. */
7302 {
7309 bfd_vma val;
7310 bfd_size_type size;
7316 s = bfd_get_linker_section
7327 myh = elf_link_hash_lookup
7331 {
7332 /* We've already seen this guy. */
7335 }
7337 /* The only trick here is using hash_table->arm_glue_size as the value.
7338 Even though the section isn't allocated yet, this is where we will be
7339 putting it. The +1 on the value marks that the stub has not been
7340 output yet - not that it is a Thumb function. */
7358 else
7365 }
7367 /* Allocate space for ARMv4 BX veneers. */
7369 static void
7371 {
7377 bfd_vma val;
7379 /* BX PC does not need a veneer. */
7387 /* Check if this veneer has already been allocated. */
7391 s = bfd_get_linker_section
7396 /* Add symbol for veneer. */
7403 myh = elf_link_hash_lookup
7421 }
7424 /* Add an entry to the code/data map for section SEC. */
7426 static void
7428 {
7433 {
7438 }
7443 {
7448 }
7451 {
7454 }
7455 }
7458 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
7459 veneers are handled for now. */
7461 static bfd_vma
7467 {
7473 bfd_vma val;
7481 s = bfd_get_linker_section
7495 myh = elf_link_hash_lookup
7510 /* Link veneer back to calling location. */
7524 /* A symbol for the return from the veneer. */
7528 myh = elf_link_hash_lookup
7545 /* Generate a mapping symbol for the veneer section, and explicitly add an
7546 entry for that symbol to the code/data map for the section. */
7548 {
7550 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
7551 ever requires this erratum fix. */
7561 /* The elf32_arm_init_maps function only cares about symbols from input
7562 BFDs. We must make a note of this generated mapping symbol
7563 ourselves so that code byteswapping works properly in
7564 elf32_arm_write_section. */
7566 }
7572 /* The offset of the veneer. */
7574 }
7576 /* Record information about a STM32L4XX STM erratum veneer. Only THUMB-mode
7577 veneers need to be handled because used only in Cortex-M. */
7579 static bfd_vma
7585 bfd_size_type veneer_size)
7586 {
7592 bfd_vma val;
7600 s = bfd_get_linker_section
7614 myh = elf_link_hash_lookup
7629 /* Link veneer back to calling location. */
7643 /* A symbol for the return from the veneer. */
7647 myh = elf_link_hash_lookup
7664 /* Generate a mapping symbol for the veneer section, and explicitly add an
7665 entry for that symbol to the code/data map for the section. */
7667 {
7669 /* Creates a THUMB symbol since there is no other choice. */
7679 /* The elf32_arm_init_maps function only cares about symbols from input
7680 BFDs. We must make a note of this generated mapping symbol
7681 ourselves so that code byteswapping works properly in
7682 elf32_arm_write_section. */
7684 }
7690 /* The offset of the veneer. */
7692 }
7694 #define ARM_GLUE_SECTION_FLAGS \
7695 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
7696 | SEC_READONLY | SEC_LINKER_CREATED)
7698 /* Create a fake section for use by the ARM backend of the linker. */
7700 static bool
7702 {
7707 /* Already made. */
7716 /* Set the gc mark to prevent the section from being removed by garbage
7717 collection, despite the fact that no relocs refer to this section. */
7721 }
7723 /* Set size of .plt entries. This function is called from the
7724 linker scripts in ld/emultempl/{armelf}.em. */
7726 void
7728 {
7730 }
7732 /* Add the glue sections to ABFD. This function is called from the
7733 linker scripts in ld/emultempl/{armelf}.em. */
7735 bool
7738 {
7744 /* If we are only performing a partial
7745 link do not bother adding the glue. */
7757 return addglue
7759 }
7761 /* Mark output sections of veneers needing a dedicated one with SEC_KEEP. This
7762 ensures they are not marked for deletion by
7763 strip_excluded_output_sections () when veneers are going to be created
7764 later. Not doing so would trigger assert on empty section size in
7765 lang_size_sections_1 (). */
7767 void
7769 {
7772 /* If we are only performing a partial
7773 link do not bother adding the glue. */
7778 {
7789 }
7790 }
7792 /* Select a BFD to be used to hold the sections used by the glue code.
7793 This function is called from the linker scripts in ld/emultempl/
7794 {armelf/pe}.em. */
7796 bool
7798 {
7801 /* If we are only performing a partial link
7802 do not bother getting a bfd to hold the glue. */
7806 /* Make sure we don't attach the glue sections to a dynamic object. */
7815 /* Save the bfd for later use. */
7819 }
7821 static void
7823 {
7827 Tag_CPU_arch);
7830 {
7833 }
7834 else
7835 {
7838 }
7839 }
7841 bool
7844 {
7853 /* If we are only performing a partial link do not bother
7854 to construct any glue. */
7858 /* Here we have a bfd that is to be included on the link. We have a
7859 hook to do reloc rummaging, before section sizes are nailed down. */
7866 {
7868 abfd);
7870 }
7872 /* PR 5398: If we have not decided to include any loadable sections in
7873 the output then we will not have a glue owner bfd. This is OK, it
7874 just means that there is nothing else for us to do here. */
7878 /* Rummage around all the relocs and map the glue vectors. */
7885 {
7895 /* Load the relocs. */
7896 internal_relocs
7904 {
7913 /* These are the only relocation types we care about. */
7918 /* Get the section contents if we haven't done so already. */
7920 {
7921 /* Get cached copy if it exists. */
7924 else
7925 {
7926 /* Go get them off disk. */
7929 }
7930 }
7933 {
7939 }
7941 /* If the relocation is not against a symbol it cannot concern us. */
7944 /* We don't care about local symbols. */
7948 /* This is an external symbol. */
7953 /* If the relocation is against a static symbol it must be within
7954 the current section and so cannot be a cross ARM/Thumb relocation. */
7958 /* If the call will go through a PLT entry then we do not need
7959 glue. */
7964 {
7966 /* This one is a call from arm code. We need to look up
7967 the target of the call. If it is a thumb target, we
7968 insert glue. */
7976 }
7977 }
7986 }
7990 error_return:
7997 }
7998 #endif
8001 /* Initialise maps of ARM/Thumb/data for input BFDs. */
8003 void
8005 {
8010 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
8020 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
8021 should contain the number of local symbols, which should come before any
8022 global symbols. Mapping symbols are always local. */
8024 NULL);
8026 /* No internal symbols read? Skip this BFD. */
8031 {
8038 {
8043 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
8045 }
8046 }
8047 }
8050 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
8051 say what they wanted. */
8053 void
8055 {
8063 {
8064 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
8069 else
8071 }
8072 }
8075 void
8077 {
8083 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
8085 {
8087 {
8094 /* Give a warning, but do as the user requests anyway. */
8097 }
8098 }
8100 /* For earlier architectures, we might need the workaround, but do not
8101 enable it by default. If users is running with broken hardware, they
8102 must enable the erratum fix explicitly. */
8104 }
8106 void
8108 {
8115 /* We assume only Cortex-M4 may require the fix. */
8118 {
8120 /* Give a warning, but do as the user requests anyway. */
8121 _bfd_error_handler
8124 }
8125 }
8127 enum bfd_arm_vfp11_pipe
8128 {
8129 VFP11_FMAC,
8130 VFP11_LS,
8131 VFP11_DS,
8132 VFP11_BAD
8133 };
8135 /* Return a VFP register number. This is encoded as RX:X for single-precision
8136 registers, or X:RX for double-precision registers, where RX is the group of
8137 four bits in the instruction encoding and X is the single extension bit.
8138 RX and X fields are specified using their lowest (starting) bit. The return
8139 value is:
8141 0...31: single-precision registers s0...s31
8142 32...63: double-precision registers d0...d31.
8144 Although X should be zero for VFP11 (encoding d0...d15 only), we might
8145 encounter VFP3 instructions, so we allow the full range for DP registers. */
8147 static unsigned int
8150 {
8153 else
8155 }
8157 /* Set bits in *WMASK according to a register number REG as encoded by
8158 bfd_arm_vfp11_regno(). Ignore d16-d31. */
8160 static void
8162 {
8167 }
8169 /* Return TRUE if WMASK overwrites anything in REGS. */
8171 static bool
8173 {
8177 {
8190 }
8193 }
8195 /* In this function, we're interested in two things: finding input registers
8196 for VFP data-processing instructions, and finding the set of registers which
8197 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
8198 hold the written set, so FLDM etc. are easy to deal with (we're only
8199 interested in 32 SP registers or 16 dp registers, due to the VFP version
8200 implemented by the chip in question). DP registers are marked by setting
8201 both SP registers in the write mask). */
8203 static enum bfd_arm_vfp11_pipe
8206 {
8211 {
8221 {
8243 vfp_binop:
8251 {
8256 {
8270 /* These instructions will not bounce due to underflow. */
8276 /* fsqrt cannot underflow, but it can (perhaps) overwrite
8277 registers to cause the erratum in previous instructions. */
8283 {
8288 /* Only FCVTSD can underflow. */
8295 }
8300 }
8301 }
8306 }
8307 }
8308 /* Two-register transfer. */
8310 {
8314 {
8317 else
8318 {
8321 }
8322 }
8325 }
8327 {
8332 {
8339 {
8347 }
8357 }
8360 }
8361 /* Single-register transfer. Note L==0. */
8363 {
8368 {
8371 /* Mark fmdhr and fmdlr as writing to the whole of the DP
8372 destination register. I don't know if this is exactly right,
8373 but it is the conservative choice. */
8379 }
8382 }
8385 }
8391 /* Look for potentially-troublesome code sequences which might trigger the
8392 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
8393 (available from ARM) for details of the erratum. A short version is
8394 described in ld.texinfo. */
8396 bool
8398 {
8409 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
8410 The states transition as follows:
8412 0 -> 1 (vector) or 0 -> 2 (scalar)
8413 A VFP FMAC-pipeline instruction has been seen. Fill
8414 regs[0]..regs[numregs-1] with its input operands. Remember this
8415 instruction in 'first_fmac'.
8417 1 -> 2
8418 Any instruction, except for a VFP instruction which overwrites
8419 regs[*].
8421 1 -> 3 [ -> 0 ] or
8422 2 -> 3 [ -> 0 ]
8423 A VFP instruction has been seen which overwrites any of regs[*].
8424 We must make a veneer! Reset state to 0 before examining next
8425 instruction.
8427 2 -> 0
8428 If we fail to match anything in state 2, reset to state 0 and reset
8429 the instruction pointer to the instruction after 'first_fmac'.
8431 If the VFP11 vector mode is in use, there must be at least two unrelated
8432 instructions between anti-dependent VFP11 instructions to properly avoid
8433 triggering the erratum, hence the use of the extra state 1. */
8435 /* If we are only performing a partial link do not bother
8436 to construct any glue. */
8440 /* Skip if this bfd does not correspond to an ELF image. */
8444 /* We should have chosen a fix type by the time we get here. */
8450 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8455 {
8459 /* If we don't have executable progbits, we're not interested in this
8460 section. Also skip if section is to be excluded. */
8480 elf32_arm_compare_mapping);
8483 {
8489 /* FIXME: Only ARM mode is supported at present. We may need to
8490 support Thumb-2 mode also at some point. */
8495 {
8510 {
8514 /* I'm assuming the VFP11 erratum can trigger with denorm
8515 operands on either the FMAC or the DS pipeline. This might
8516 lead to slightly overenthusiastic veneer insertion. */
8518 {
8522 }
8526 {
8529 other_regs,
8533 numregs))
8535 else
8537 }
8541 {
8544 other_regs,
8548 numregs))
8550 else
8551 {
8554 }
8555 }
8560 }
8563 {
8572 {
8579 }
8582 first_fmac);
8590 }
8593 }
8594 }
8599 }
8603 error_return:
8608 }
8610 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
8611 after sections have been laid out, using specially-named symbols. */
8613 void
8616 {
8624 /* Skip if this bfd does not correspond to an ELF image. */
8637 {
8642 {
8644 bfd_vma vma;
8647 {
8650 /* Find veneer symbol. */
8654 myh = elf_link_hash_lookup
8670 /* Find return location. */
8674 myh = elf_link_hash_lookup
8690 }
8691 }
8692 }
8695 }
8697 /* Find virtual-memory addresses for STM32L4XX erratum veneers and
8698 return locations after sections have been laid out, using
8699 specially-named symbols. */
8701 void
8704 {
8712 /* Skip if this bfd does not correspond to an ELF image. */
8725 {
8730 {
8732 bfd_vma vma;
8735 {
8737 /* Find veneer symbol. */
8741 myh = elf_link_hash_lookup
8756 /* Find return location. */
8760 myh = elf_link_hash_lookup
8776 }
8777 }
8778 }
8781 }
8785 {
8786 /* Encoding T2: LDM<c>.W <Rn>{!},<registers>
8787 1110 - 1000 - 10W1 - rrrr - PM (0) l - llll - llll - llll. */
8789 }
8793 {
8794 /* Encoding T1: LDMDB<c> <Rn>{!},<registers>
8795 1110 - 1001 - 00W1 - rrrr - PM (0) l - llll - llll - llll. */
8797 }
8801 {
8802 /* A6.5 Extension register load or store instruction
8803 A7.7.229
8804 We look for SP 32-bit and DP 64-bit registers.
8805 Encoding T1 VLDM{mode}<c> <Rn>{!}, <list>
8806 <list> is consecutive 64-bit registers
8807 1110 - 110P - UDW1 - rrrr - vvvv - 1011 - iiii - iiii
8808 Encoding T2 VLDM{mode}<c> <Rn>{!}, <list>
8809 <list> is consecutive 32-bit registers
8810 1110 - 110P - UDW1 - rrrr - vvvv - 1010 - iiii - iiii
8811 if P==0 && U==1 && W==1 && Rn=1101 VPOP
8812 if PUW=010 || PUW=011 || PUW=101 VLDM. */
8813 return
8818 /* (IA with !), includes VPOP (when reg number is SP). */
8820 /* (DB with !). */
8822 }
8824 /* STM STM32L4XX erratum : This function assumes that it receives an LDM or
8825 VLDM opcode and:
8826 - computes the number and the mode of memory accesses
8827 - decides if the replacement should be done:
8828 . replaces only if > 8-word accesses
8829 . or (testing purposes only) replaces all accesses. */
8831 static bool
8833 bfd_arm_stm32l4xx_fix stm32l4xx_fix)
8834 {
8837 /* The field encoding the register list is the same for both LDMIA
8838 and LDMDB encodings. */
8844 /* DEFAULT mode accounts for the real bug condition situation,
8845 ALL mode inserts stubs for each LDM/VLDM instruction (testing). */
8849 }
8851 /* Look for potentially-troublesome code sequences which might trigger
8852 the STM STM32L4XX erratum. */
8854 bool
8857 {
8865 /* If we are only performing a partial link do not bother
8866 to construct any glue. */
8870 /* Skip if this bfd does not correspond to an ELF image. */
8877 /* Skip this BFD if it corresponds to an executable or dynamic object. */
8882 {
8886 /* If we don't have executable progbits, we're not interested in this
8887 section. Also skip if section is to be excluded. */
8907 elf32_arm_compare_mapping);
8910 {
8917 /* Only Thumb2 mode need be supported with this CM4 specific
8918 code, we should not encounter any arm mode eg span_type
8919 != 'a'. */
8924 {
8931 /* The first 16-bits of all 32-bit thumb2 instructions start
8932 with opcode[15..13]=0b111 and the encoded op1 can be anything
8933 except opcode[12..11]!=0b00.
8934 See 32-bit Thumb instruction encoding. */
8938 /* Compute the predicate that tells if the instruction
8939 is concerned by the IT block
8940 - Creates an error if there is a ldm that is not
8941 last in the IT block thus cannot be replaced
8942 - Otherwise we can create a branch at the end of the
8943 IT block, it will be controlled naturally by IT
8944 with the proper pseudo-predicate
8945 - So the only interesting predicate is the one that
8946 tells that we are not on the last item of an IT
8947 block. */
8952 {
8953 /* Load the rest of the insn (in manual-friendly order). */
8958 /* Veneers are created for (v)ldm depending on
8959 option flags and memory accesses conditions; but
8960 if the instruction is not the last instruction of
8961 an IT block, we cannot create a jump there, so we
8962 bail out. */
8964 && stm32l4xx_need_create_replacing_stub
8966 {
8968 {
8969 _bfd_error_handler
8970 /* xgettext:c-format */
8972 " in non-last IT block instruction:"
8973 " STM32L4XX veneer cannot be generated; "
8974 "use gcc option -mrestrict-it to generate"
8977 }
8978 else
8979 {
8982 bfd_zmalloc
8988 /* We create only thumb branches. */
8990 STM32L4XX_ERRATUM_BRANCH_TO_VENEER;
8991 record_stm32l4xx_erratum_veneer
8993 i,
8994 is_ldm ?
8995 STM32L4XX_ERRATUM_LDM_VENEER_SIZE:
8996 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
9000 }
9001 }
9002 }
9003 else
9004 {
9005 /* A7.7.37 IT p208
9006 IT blocks are only encoded in T1
9007 Encoding T1: IT{x{y{z}}} <firstcond>
9008 1 0 1 1 - 1 1 1 1 - firstcond - mask
9009 if mask = '0000' then see 'related encodings'
9010 We don't deal with UNPREDICTABLE, just ignore these.
9011 There can be no nested IT blocks so an IT block
9012 is naturally a new one for which it is worth
9013 computing its size. */
9016 /* If we have a new IT block we compute its size. */
9018 {
9019 /* Compute the number of instructions controlled
9020 by the IT block, it will be used to decide
9021 whether we are inside an IT block or not. */
9024 }
9025 }
9028 }
9029 }
9034 }
9038 error_return:
9043 }
9045 /* Set target relocation values needed during linking. */
9047 void
9051 {
9067 else
9068 {
9071 }
9078 else
9090 }
9092 /* Replace the target offset of a Thumb bl or b.w instruction. */
9094 static void
9096 {
9097 bfd_vma upper;
9098 bfd_vma lower;
9115 }
9117 /* Thumb code calling an ARM function. */
9119 static int
9127 bfd_vma offset,
9128 bfd_signed_vma addend,
9129 bfd_vma val,
9131 {
9133 bfd_vma my_offset;
9149 THUMB2ARM_GLUE_SECTION_NAME);
9156 {
9160 {
9161 _bfd_error_handler
9167 }
9178 ret_offset =
9179 /* Address of destination of the stub. */
9182 /* Offset from the start of the current section
9183 to the start of the stubs. */
9185 /* Offset of the start of this stub from the start of the stubs. */
9186 + my_offset
9187 /* Address of the start of the current section. */
9189 /* The branch instruction is 4 bytes into the stub. */
9191 /* ARM branches work from the pc of the instruction + 8. */
9197 }
9201 /* Now go back and fix up the original BL insn to point to here. */
9202 ret_offset =
9203 /* Address of where the stub is located. */
9205 /* Address of where the BL is located. */
9208 /* Addend in the relocation. */
9209 - addend
9210 /* Biassing for PC-relative addressing. */
9216 }
9218 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
9226 bfd_vma val,
9229 {
9230 bfd_vma my_offset;
9246 {
9250 {
9251 _bfd_error_handler
9255 }
9262 {
9263 /* For relocatable objects we can't use absolute addresses,
9264 so construct the address from a relative offset. */
9265 /* TODO: If the offset is small it's probably worth
9266 constructing the address with adds. */
9273 /* Adjust the offset by 4 for the position of the add,
9274 and 8 for the pipeline offset. */
9281 }
9283 {
9287 /* It's a thumb address. Add the low order bit. */
9290 }
9291 else
9292 {
9299 /* It's a thumb address. Add the low order bit. */
9304 }
9305 }
9310 }
9312 /* Arm code calling a Thumb function. */
9314 static int
9322 bfd_vma offset,
9323 bfd_signed_vma addend,
9324 bfd_vma val,
9326 {
9328 bfd_vma my_offset;
9339 ARM2THUMB_GLUE_SECTION_NAME);
9353 /* Somehow these are both 4 too far, so subtract 8. */
9355 + my_offset
9367 }
9369 /* Populate Arm stub for an exported Thumb function. */
9371 static bool
9373 {
9380 bfd_vma val;
9384 /* Allocate stubs for exported Thumb functions on v4t. */
9393 ARM2THUMB_GLUE_SECTION_NAME);
9411 }
9413 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
9415 static bfd_vma
9417 {
9419 bfd_vma glue_addr;
9428 ARM_BX_GLUE_SECTION_NAME);
9438 {
9444 }
9447 }
9449 /* Generate Arm stubs for exported Thumb symbols. */
9450 static void
9453 {
9457 /* Ignore this if we are not called by the ELF backend linker. */
9464 /* If blx is available then exported Thumb symbols are OK and there is
9465 nothing to do. */
9470 link_info);
9471 }
9473 /* Reserve space for COUNT dynamic relocations in relocation selection
9474 SRELOC. */
9476 static void
9478 bfd_size_type count)
9479 {
9487 }
9489 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
9490 dynamic, the relocations should go in SRELOC, otherwise they should
9491 go in the special .rel.iplt section. */
9493 static void
9495 bfd_size_type count)
9496 {
9502 else
9503 {
9506 }
9507 }
9509 /* Add relocation REL to the end of relocation section SRELOC. */
9511 static void
9514 {
9529 }
9531 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
9532 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
9533 to .plt. */
9535 static void
9540 {
9548 {
9552 /* NaCl uses a special first entry in .iplt too. */
9556 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
9558 }
9559 else
9560 {
9565 {
9566 /* Allocate room for R_ARM_FUNCDESC_VALUE. */
9567 /* For lazy binding, relocations will be put into .rel.plt, in
9568 .rel.got otherwise. */
9569 /* FIXME: today we don't support lazy binding so put it in .rel.got */
9572 else
9574 }
9575 else
9576 {
9577 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
9579 }
9581 /* If this is the first .plt entry, make room for the special
9582 first entry. */
9587 }
9589 /* Allocate the PLT entry itself, including any leading Thumb stub. */
9595 /* We also need to make an entry in the .got.plt section, which
9596 will be placed in the .got section by the linker script. */
9599 else
9602 /* Function descriptor takes 64 bits in GOT. */
9604 else
9606 }
9608 static bfd_vma
9610 {
9612 }
9614 static bfd_vma
9616 {
9618 }
9620 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
9621 the entry lives in .iplt and resolves to (*SYM_VALUE)().
9622 Otherwise, DYNINDX is the index of the symbol in the dynamic
9623 symbol table and SYM_VALUE is undefined.
9625 ROOT_PLT points to the offset of the PLT entry from the start of its
9626 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
9627 bookkeeping information.
9629 Returns FALSE if there was a problem. */
9631 static bool
9636 {
9642 bfd_vma plt_index;
9643 Elf_Internal_Rela rel;
9644 bfd_vma got_header_size;
9648 /* Pick the appropriate sections and sizes. */
9650 {
9655 /* There are no reserved entries in .igot.plt, and no special
9656 first entry in .iplt. */
9658 }
9659 else
9660 {
9666 }
9675 /* Get the offset into the .(i)got.plt table of the entry that
9676 corresponds to this function. */
9679 /* Get the index in the procedure linkage table which
9680 corresponds to this symbol. This is the index of this symbol
9681 in all the symbols for which we are making plt entries.
9682 After the reserved .got.plt entries, all symbols appear in
9683 the same order as in .plt. */
9685 /* Function descriptor takes 8 bytes. */
9687 else
9690 /* Calculate the address of the GOT entry. */
9695 /* ...and the address of the PLT entry. */
9702 {
9704 bfd_vma val;
9707 {
9715 else
9717 }
9718 }
9720 {
9722 bfd_vma val;
9725 {
9735 else
9737 }
9742 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
9743 referencing the GOT for this PLT entry. */
9750 /* Create the R_ARM_ABS32 relocation referencing the
9751 beginning of the PLT for this GOT entry. */
9756 }
9758 {
9759 /* Calculate the displacement between the PLT slot and the
9760 common tail that's part of the special initial PLT slot. */
9761 int32_t tail_displacement
9771 /* Calculate the displacement between the PLT slot and the entry
9772 in the GOT. The offset accounts for the value produced by
9773 adding to pc in the penultimate instruction of the PLT stub. */
9774 got_displacement = (got_address
9777 /* NaCl does not support interworking at all. */
9795 }
9797 {
9799 ? elf32_arm_fdpic_thumb_plt_entry
9802 /* Fill-up Thumb stub if needed. */
9804 {
9809 }
9810 /* As we are using 32 bit instructions even for the Thumb
9811 version, we have to use 'put_arm_insn' instead of
9812 'put_thumb_insn'. */
9820 {
9821 /* funcdesc_value_reloc_offset. */
9829 }
9830 }
9832 {
9833 /* PR ld/16017: Generate thumb only PLT entries. */
9835 {
9836 /* FIXME: We ought to be able to generate thumb-1 PLT
9837 instructions... */
9839 output_bfd);
9841 }
9843 /* Calculate the displacement between the PLT slot and the entry in
9844 the GOT. The 12-byte offset accounts for the value produced by
9845 adding to pc in the 3rd instruction of the PLT stub. */
9848 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
9849 instead of 'put_thumb_insn'. */
9870 }
9871 else
9872 {
9873 /* Calculate the displacement between the PLT slot and the
9874 entry in the GOT. The eight-byte offset accounts for the
9875 value produced by adding to pc in the first instruction
9876 of the PLT stub. */
9880 {
9885 }
9888 {
9903 #ifdef FOUR_WORD_PLT
9905 #endif
9906 }
9907 else
9908 {
9925 }
9926 }
9928 /* Fill in the entry in the .rel(a).(i)plt section. */
9932 {
9933 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
9934 The dynamic linker or static executable then calls SYM_VALUE
9935 to determine the correct run-time value of the .igot.plt entry. */
9938 }
9939 else
9940 {
9941 /* For FDPIC we will have to resolve a R_ARM_FUNCDESC_VALUE
9942 used by PLT entry. */
9944 {
9947 }
9948 else
9949 {
9954 /* PR ld/16017
9955 When thumb only we need to set the LSB for any address that
9956 will be used with an interworking branch instruction. */
9959 }
9960 }
9962 /* Fill in the entry in the global offset table. */
9967 {
9968 /* Setup initial funcdesc value. */
9969 /* FIXME: we don't support lazy binding because there is a
9970 race condition between both words getting written and
9971 some other thread attempting to read them. The ARM
9972 architecture does not have an atomic 64 bit load/store
9973 instruction that could be used to prevent it; it is
9974 recommended that threaded FDPIC applications run with the
9975 LD_BIND_NOW environment variable set. */
9980 }
9984 else
9985 {
9987 {
9988 /* For FDPIC we put PLT relocationss into .rel.got when not
9989 lazy binding otherwise we put them in .rel.plt. For now,
9990 we don't support lazy binding so put it in .rel.got. */
9993 else
9995 }
9996 else
9997 {
10000 }
10001 }
10004 }
10006 /* Some relocations map to different relocations depending on the
10007 target. Return the real relocation. */
10009 static int
10012 {
10014 {
10018 else
10026 }
10027 }
10029 /* Return the base VMA address which should be subtracted from real addresses
10030 when resolving @dtpoff relocation.
10031 This is PT_TLS segment p_vaddr. */
10033 static bfd_vma
10035 {
10036 /* If tls_sec is NULL, we should have signalled an error already. */
10040 }
10042 /* Return the relocation value for @tpoff relocation
10043 if STT_TLS virtual address is ADDRESS. */
10045 static bfd_vma
10047 {
10049 bfd_vma base;
10051 /* If tls_sec is NULL, we should have signalled an error already. */
10056 }
10058 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
10059 VALUE is the relocation value. */
10061 static bfd_reloc_status_type
10063 {
10070 }
10072 /* Handle TLS relaxations. Relaxing is possible for symbols that use
10073 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
10074 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
10076 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
10077 is to then call final_link_relocate. Return other values in the
10078 case of error.
10080 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
10081 the pre-relaxed code. It would be nice if the relocs were updated
10082 to match the optimization. */
10084 static bfd_reloc_status_type
10088 {
10092 {
10099 else
10100 {
10104 else
10106 }
10111 /* Thumb insn. */
10114 {
10116 /* nop */
10118 }
10120 {
10122 /* nop */
10124 else
10125 /* ldr rx,[ry] */
10127 }
10129 {
10131 /* nop */
10133 else
10134 /* mov r0, rx */
10137 }
10138 else
10139 {
10141 /* It's a 32 bit instruction, fetch the rest of it for
10142 error generation. */
10145 _bfd_error_handler
10146 /* xgettext:c-format */
10152 }
10156 /* arm insn. */
10159 {
10161 /* mov rx, ry */
10164 }
10166 {
10168 /* nop */
10170 else
10171 /* ldr rx,[ry] */
10174 }
10176 {
10178 /* nop */
10180 else
10181 /* mov r0, rx */
10184 }
10185 else
10186 {
10187 _bfd_error_handler
10188 /* xgettext:c-format */
10194 }
10198 /* GD->IE relaxation, turn the instruction into 'nop' or
10199 'ldr r0, [pc,r0]' */
10205 /* GD->IE relaxation. */
10207 /* add r0,pc; ldr r0, [r0] */
10210 /* nop.w */
10212 else
10213 /* nop; nop */
10219 }
10221 }
10223 /* For a given value of n, calculate the value of G_n as required to
10224 deal with group relocations. We return it in the form of an
10225 encoded constant-and-rotation, together with the final residual. If n is
10226 specified as less than zero, then final_residual is filled with the
10227 input value and no further action is performed. */
10229 static bfd_vma
10231 {
10233 bfd_vma g_n;
10238 {
10241 /* Calculate which part of the value to mask. */
10244 else
10245 {
10248 /* Determine the most significant bit in the residual and
10249 align the resulting value to a 2-bit boundary. */
10254 /* The desired shift is now (msb - 6), or zero, whichever
10255 is the greater. */
10259 }
10261 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
10266 /* Calculate the residual for the next time around. */
10268 }
10273 }
10275 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
10276 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
10278 static int
10280 {
10290 }
10292 /* Perform a relocation as part of a final link. */
10294 static bfd_reloc_status_type
10301 bfd_vma value,
10310 {
10320 bfd_vma addend;
10321 bfd_signed_vma signed_addend;
10323 bfd_vma dynreloc_value;
10328 bfd_vma plt_offset;
10329 bfd_vma gotplt_offset;
10340 /* Some relocation types map to different relocations depending on the
10341 target. We pick the right one here. */
10344 /* It is possible to have linker relaxations on some TLS access
10345 models. Update our information here. */
10358 else
10364 {
10365 bfd_vma sign;
10368 {
10373 }
10374 /* Note: the addend and signed_addend calculated here are
10375 incorrect for any split field. */
10381 }
10382 else
10385 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
10386 are resolving a function call relocation. */
10393 /* Record the symbol information that should be used in dynamic
10394 relocations. */
10400 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
10401 VALUE appropriately for relocations that we resolve at link time. */
10406 {
10411 {
10415 /* Populate .iplt entries here, because not all of them will
10416 be seen by finish_dynamic_symbol. The lower bit is set if
10417 we have already populated the entry. */
10419 plt_offset--;
10420 else
10421 {
10425 else
10427 }
10429 /* Static relocations always resolve to the .iplt entry. */
10436 /* If there are non-call relocations that resolve to the .iplt
10437 entry, then all dynamic ones must too. */
10439 {
10442 }
10443 }
10444 else
10445 /* We populate the .plt entry in finish_dynamic_symbol. */
10447 }
10448 else
10449 {
10453 }
10459 {
10461 /* We don't need to find a value for this symbol. It's just a
10462 marker. */
10469 /* Fall through. */
10481 /* Handle relocations which should use the PLT entry. ABS32/REL32
10482 will use the symbol's value, which may point to a PLT entry, but we
10483 don't need to handle that here. If we created a PLT entry, all
10484 branches in this object should go to it, except if the PLT is too
10485 far away, in which case a long branch stub should be inserted. */
10492 {
10493 /* If we've created a .plt section, and assigned a PLT entry
10494 to this function, it must either be a STT_GNU_IFUNC reference
10495 or not be known to bind locally. In other cases, we should
10496 have cleared the PLT entry by now. */
10506 }
10508 /* When generating a shared library or PIE, these relocations
10509 are copied into the output file to be resolved at run time. */
10529 {
10530 Elf_Internal_Rela outrel;
10536 {
10542 _bfd_error_handler
10547 }
10552 {
10558 }
10583 else
10584 {
10587 /* This symbol is local, or marked to become local. */
10590 /* On SVR4-ish systems, the dynamic loader cannot
10591 relocate the text and data segments independently,
10592 so the symbol does not matter. */
10595 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
10596 to the .iplt entry. Instead, every non-call reference
10597 must use an R_ARM_IRELATIVE relocation to obtain the
10598 correct run-time address. */
10602 else
10606 else
10608 }
10612 else
10615 /* If this reloc is against an external symbol, we do not want to
10616 fiddle with the addend. Otherwise, we need to include the symbol
10617 value so that it becomes an addend for the dynamic reloc. */
10624 }
10626 {
10635 {
10639 {
10640 /* Check for Arm calling Arm function. */
10641 /* FIXME: Should we translate the instruction into a BL
10642 instruction instead ? */
10644 _bfd_error_handler
10649 }
10651 {
10652 /* Check for Arm calling Thumb function. */
10654 {
10659 error_message))
10661 else
10663 }
10664 }
10666 /* Check if a stub has to be inserted because the
10667 destination is too far or we are changing mode. */
10671 {
10682 {
10683 /* The target is out of reach, so redirect the
10684 branch to the local stub for this function. */
10688 stub_type);
10689 {
10697 }
10698 }
10699 else
10700 {
10701 /* If the call goes through a PLT entry, make sure to
10702 check distance to the right destination address. */
10704 {
10709 /* The PLT entry is in ARM mode, regardless of the
10710 target function. */
10712 }
10713 }
10714 }
10716 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
10717 where:
10718 S is the address of the symbol in the relocation.
10719 P is address of the instruction being relocated.
10720 A is the addend (extracted from the instruction) in bytes.
10722 S is held in 'value'.
10723 P is the base address of the section containing the
10724 instruction plus the offset of the reloc into that
10725 section, ie:
10726 (input_section->output_section->vma +
10727 input_section->output_offset +
10728 rel->r_offset).
10729 A is the addend, converted into bytes, ie:
10730 (signed_addend * 4)
10732 Note: None of these operations have knowledge of the pipeline
10733 size of the processor, thus it is up to the assembler to
10734 encode this information into the addend. */
10743 /* A branch to an undefined weak symbol is turned into a jump to
10744 the next instruction unless a PLT entry will be created.
10745 Do the same for local undefined symbols (but not for STN_UNDEF).
10746 The jump to the next instruction is optimized as a NOP depending
10747 on the architecture. */
10751 {
10756 else
10758 }
10759 else
10760 {
10761 /* Perform a signed range check. */
10772 {
10773 /* Set the H bit in the BLX instruction. */
10775 {
10778 else
10780 }
10782 /* Select the correct instruction (BL or BLX). */
10783 /* Only if we are not handling a BL to a stub. In this
10784 case, mode switching is performed by the stub. */
10788 {
10791 }
10792 }
10793 }
10794 }
10826 {
10827 /* Check for overflow. */
10830 }
10836 }
10844 /* There is no way to tell whether the user intended to use a signed or
10845 unsigned addend. When checking for overflow we accept either,
10846 as specified by the AAELF. */
10856 /* See comment for R_ARM_ABS8. */
10864 /* Support ldr and str instructions for the thumb. */
10866 {
10867 /* Need to refetch addend. */
10869 /* ??? Need to determine shift amount from operand size. */
10871 }
10874 /* ??? Isn't value unsigned? */
10878 /* ??? Value needs to be properly shifted into place first. */
10884 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
10885 {
10886 bfd_vma insn;
10887 bfd_signed_vma relocation;
10893 {
10898 }
10905 /* PR 21523: Use an absolute value. The user of this reloc will
10906 have already selected an ADD or SUB insn appropriately. */
10912 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
10926 }
10929 /* PR 10073: This reloc is not generated by the GNU toolchain,
10930 but it is supported for compatibility with third party libraries
10931 generated by other compilers, specifically the ARM/IAR. */
10932 {
10933 bfd_vma insn;
10934 bfd_signed_vma relocation;
10948 /* We do not check for overflow of this reloc. Although strictly
10949 speaking this is incorrect, it appears to be necessary in order
10950 to work with IAR generated relocs. Since GCC and GAS do not
10951 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
10952 a problem for them. */
10960 }
10963 /* Corresponds to: ldr.w reg, [pc, #offset]. */
10964 {
10965 bfd_vma insn;
10966 bfd_signed_vma relocation;
10972 {
10976 }
10996 }
11001 /* Thumb BL (branch long instruction). */
11002 {
11003 bfd_vma relocation;
11004 bfd_vma reloc_sign;
11008 bfd_signed_vma reloc_signed_max;
11009 bfd_signed_vma reloc_signed_min;
11010 bfd_vma check;
11011 bfd_signed_vma signed_check;
11016 /* A branch to an undefined weak symbol is turned into a jump to
11017 the next instruction unless a PLT entry will be created.
11018 The jump to the next instruction is optimized as a NOP.W for
11019 Thumb-2 enabled architectures. */
11022 {
11024 {
11027 }
11028 else
11029 {
11032 }
11034 }
11036 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
11037 with Thumb-1) involving the J1 and J2 bits. */
11039 {
11049 /* Sign extend. */
11053 }
11056 {
11057 /* Check for Thumb to Thumb call. */
11058 /* FIXME: Should we translate the instruction into a BL
11059 instruction instead ? */
11061 _bfd_error_handler
11066 }
11067 else
11068 {
11069 /* If it is not a call to Thumb, assume call to Arm.
11070 If it is a call relative to a section name, then it is not a
11071 function call at all, but rather a long jump. Calls through
11072 the PLT do not require stubs. */
11074 {
11076 {
11077 /* Convert BL to BLX. */
11079 }
11082 {
11086 error_message))
11088 else
11090 }
11091 }
11095 {
11096 /* Make sure this is a BL. */
11098 }
11099 }
11103 {
11104 /* Check if a stub has to be inserted because the destination
11105 is too far. */
11117 {
11118 /* The target is out of reach or we are changing modes, so
11119 redirect the branch to the local stub for this
11120 function. */
11124 stub_type);
11126 {
11133 }
11135 /* If this call becomes a call to Arm, force BLX. */
11137 {
11142 }
11143 }
11144 }
11146 /* Handle calls via the PLT. */
11148 {
11156 {
11157 /* If the Thumb BLX instruction is available, convert
11158 the BL to a BLX instruction to call the ARM-mode
11159 PLT entry. */
11162 }
11163 else
11164 {
11166 /* Target the Thumb stub before the ARM PLT entry. */
11169 }
11171 }
11181 /* If this is a signed value, the rightshift just dropped
11182 leading 1 bits (assuming twos complement). */
11185 else
11188 /* Calculate the permissable maximum and minimum values for
11189 this relocation according to whether we're relocating for
11190 Thumb-2 or not. */
11197 /* Assumes two's complement. */
11202 /* For a BLX instruction, make sure that the relocation is rounded up
11203 to a word boundary. This follows the semantics of the instruction
11204 which specifies that bit 1 of the target address will come from bit
11205 1 of the base address. */
11208 /* Put RELOCATION back into the insn. Assumes two's complement.
11209 We use the Thumb-2 encoding, which is safe even if dealing with
11210 a Thumb-1 instruction by virtue of our overflow check above. */
11220 /* Put the relocated value back in the object file: */
11225 }
11229 /* Thumb32 conditional branch instruction. */
11230 {
11231 bfd_vma relocation;
11237 bfd_signed_vma signed_check;
11242 /* Need to refetch the addend, reconstruct the top three bits,
11243 and squish the two 11 bit pieces together. */
11245 {
11259 }
11261 /* Handle calls via the PLT. */
11263 {
11267 /* Target the Thumb stub before the ARM PLT entry. */
11270 }
11279 {
11283 stub_type);
11285 {
11289 }
11290 }
11301 /* Put RELOCATION back into the insn. */
11302 {
11311 }
11313 /* Put the relocated value back in the object file: */
11318 }
11323 /* Thumb B (branch) instruction). */
11324 {
11325 bfd_signed_vma relocation;
11328 bfd_signed_vma signed_check;
11330 /* CZB cannot jump backward. */
11332 {
11336 }
11349 else
11355 /* Assumes two's complement. */
11360 }
11365 {
11366 bfd_vma insn;
11367 bfd_vma relocation;
11371 {
11372 /* Extract the addend. */
11375 }
11385 }
11393 /* Relocation is relative to the start of the
11394 global offset table. */
11400 /* If we are addressing a Thumb function, we need to adjust the
11401 address by one, so that attempts to call the function pointer will
11402 correctly interpret it as Thumb code. */
11406 /* Note that sgot->output_offset is not involved in this
11407 calculation. We always want the start of .got. If we
11408 define _GLOBAL_OFFSET_TABLE in a different way, as is
11409 permitted by the ABI, we might have to change this
11410 calculation. */
11417 /* Use global offset table as symbol value. */
11431 /* Relocation is to the entry for this symbol in the
11432 global offset table. */
11439 {
11440 /* We have a relocation against a locally-binding STT_GNU_IFUNC
11441 symbol, and the relocation resolves directly to the runtime
11442 target rather than to the .iplt entry. This means that any
11443 .got entry would be the same value as the .igot.plt entry,
11444 so there's no point creating both. */
11447 }
11449 {
11450 bfd_vma off;
11455 {
11456 /* We have already processsed one GOT relocation against
11457 this symbol. */
11462 }
11463 else
11464 {
11465 Elf_Internal_Rela outrel;
11470 {
11471 /* If the symbol doesn't resolve locally in a static
11472 object, we have an undefined reference. If the
11473 symbol doesn't resolve locally in a dynamic object,
11474 it should be resolved by the dynamic linker. */
11476 {
11479 }
11480 else
11483 }
11484 else
11485 {
11491 else
11492 {
11496 }
11498 }
11500 /* The GOT entry is initialized to zero by default.
11501 See if we should install a different value. */
11504 {
11508 }
11517 {
11522 }
11525 }
11527 }
11528 else
11529 {
11530 bfd_vma off;
11537 /* The offset must always be a multiple of 4. We use the
11538 least significant bit to record whether we have already
11539 generated the necessary reloc. */
11542 else
11543 {
11544 Elf_Internal_Rela outrel;
11551 else
11552 {
11556 }
11558 /* The GOT entry is initialized to zero by default.
11559 See if we should install a different value. */
11570 {
11576 }
11579 }
11582 }
11599 {
11600 bfd_vma off;
11609 else
11610 {
11611 /* If we don't know the module number, create a relocation
11612 for it. */
11614 {
11615 Elf_Internal_Rela outrel;
11630 }
11631 else
11635 }
11638 {
11644 }
11645 else
11646 {
11654 }
11655 }
11666 {
11674 {
11679 h)
11682 {
11685 }
11689 }
11690 else
11691 {
11695 {
11698 input_bfd,
11700 r_symndx);
11702 }
11706 }
11708 /* Linker relaxations happens from one of the
11709 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
11717 else
11718 {
11720 Elf_Internal_Rela outrel;
11723 /* The GOT entries have not been initialized yet. Do it
11724 now, and emit any relocations. If both an IE GOT and a
11725 GD GOT are necessary, we emit the GD first. */
11732 {
11735 }
11738 {
11741 /* We should have relaxed, unless this is an undefined
11742 weak symbol. */
11751 + offplt
11763 /* For globals, the first word in the relocation gets
11764 the relocation index and the top bit set, or zero,
11765 if we're binding now. For locals, it gets the
11766 symbol's offset in the tls section. */
11774 /* Second word in the relocation is always zero. */
11778 }
11780 {
11782 {
11798 else
11799 {
11802 R_ARM_TLS_DTPOFF32);
11811 }
11812 }
11813 else
11814 {
11815 /* If we are not emitting relocations for a
11816 general dynamic reference, then we must be in a
11817 static link or an executable link with the
11818 symbol binding locally. Mark it as belonging
11819 to module 1, the executable. */
11824 }
11827 }
11830 {
11832 {
11835 else
11847 }
11848 else
11852 }
11856 else
11858 }
11867 {
11868 bfd_signed_vma offset;
11869 /* TLS stubs are arm mode. The original symbol is a
11870 data object, so branch_type is bogus. */
11872 enum elf32_arm_stub_type stub_type
11880 {
11882 = elf32_arm_get_stub_entry
11888 }
11889 else
11895 {
11905 }
11906 else
11907 {
11908 /* Thumb blx encodes the offset in a complicated
11909 fashion. */
11919 {
11921 }
11922 else
11923 {
11925 /* Round up the offset to a word boundary. */
11927 }
11939 }
11940 }
11941 /* These relocations needs special care, as besides the fact
11942 they point somewhere in .gotplt, the addend must be
11943 adjusted accordingly depending on the type of instruction
11944 we refer to. */
11946 {
11955 {
11962 /* bl/blx */
11965 /* add */
11967 else
11968 {
11969 _bfd_error_handler
11970 /* xgettext:c-format */
11972 "unexpected %s instruction '%#lx' "
11977 }
11978 }
11979 else
11980 {
11984 {
11995 _bfd_error_handler
11996 /* xgettext:c-format */
11998 "unexpected %s instruction '%#lx' "
12003 }
12004 }
12012 }
12013 else
12021 {
12022 /* For FDPIC relocations, resolve to the offset of the GOT
12023 entry from the start of GOT. */
12029 }
12030 else
12031 {
12035 }
12036 }
12040 {
12041 _bfd_error_handler
12042 /* xgettext:c-format */
12047 }
12048 else
12057 {
12060 /* Ensure that we have a BX instruction. */
12064 {
12065 /* Branch to veneer. */
12066 bfd_vma glue_addr;
12073 }
12074 else
12075 {
12076 /* Preserve Rm (lowest four bits) and the condition code
12077 (highest four bits). Other bits encode MOV PC,Rm. */
12079 }
12082 }
12089 /* Until we properly support segment-base-relative addressing then
12090 we assume the segment base to be zero, as for the group relocations.
12091 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
12092 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
12096 {
12100 {
12103 }
12125 }
12132 /* Until we properly support segment-base-relative addressing then
12133 we assume the segment base to be zero, as for the above relocations.
12134 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
12135 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
12136 as R_ARM_THM_MOVT_ABS. */
12140 {
12141 bfd_vma insn;
12147 {
12153 }
12179 }
12192 {
12196 /* sb is the origin of the *segment* containing the symbol. */
12198 bfd_vma residual;
12199 bfd_vma g_n;
12200 bfd_signed_vma signed_value;
12203 /* Determine which group of bits to select. */
12205 {
12227 }
12229 /* If REL, extract the addend from the insn. If RELA, it will
12230 have already been fetched for us. */
12232 {
12239 else
12240 {
12241 /* Compensate for the fact that in the instruction, the
12242 rotation is stored in multiples of 2 bits. */
12245 /* Rotate "constant" right by "rotation" bits. */
12248 }
12250 /* Determine if the instruction is an ADD or a SUB.
12251 (For REL, this determines the sign of the addend.) */
12254 {
12255 _bfd_error_handler
12256 /* xgettext:c-format */
12261 }
12264 }
12266 /* Compute the value (X) to go in the place. */
12272 /* PC relative. */
12274 else
12275 /* Section base relative. */
12278 /* If the target symbol is a Thumb function, then set the
12279 Thumb bit in the address. */
12283 /* Calculate the value of the relevant G_n, in encoded
12284 constant-with-rotation format. */
12288 /* Check for overflow if required. */
12295 {
12296 _bfd_error_handler
12297 /* xgettext:c-format */
12304 }
12306 /* Mask out the value and the ADD/SUB part of the opcode; take care
12307 not to destroy the S bit. */
12310 /* Set the opcode according to whether the value to go in the
12311 place is negative. */
12314 else
12317 /* Encode the offset. */
12321 }
12330 {
12334 /* sb is the origin of the *segment* containing the symbol. */
12336 bfd_vma residual;
12337 bfd_signed_vma signed_value;
12340 /* Determine which groups of bits to calculate. */
12342 {
12360 }
12362 /* If REL, extract the addend from the insn. If RELA, it will
12363 have already been fetched for us. */
12365 {
12368 }
12370 /* Compute the value (X) to go in the place. */
12374 /* PC relative. */
12376 else
12377 /* Section base relative. */
12380 /* Calculate the value of the relevant G_{n-1} to obtain
12381 the residual at that stage. */
12385 /* Check for overflow. */
12387 {
12388 _bfd_error_handler
12389 /* xgettext:c-format */
12396 }
12398 /* Mask out the value and U bit. */
12401 /* Set the U bit if the value to go in the place is non-negative. */
12405 /* Encode the offset. */
12409 }
12418 {
12422 /* sb is the origin of the *segment* containing the symbol. */
12424 bfd_vma residual;
12425 bfd_signed_vma signed_value;
12428 /* Determine which groups of bits to calculate. */
12430 {
12448 }
12450 /* If REL, extract the addend from the insn. If RELA, it will
12451 have already been fetched for us. */
12453 {
12456 }
12458 /* Compute the value (X) to go in the place. */
12462 /* PC relative. */
12464 else
12465 /* Section base relative. */
12468 /* Calculate the value of the relevant G_{n-1} to obtain
12469 the residual at that stage. */
12473 /* Check for overflow. */
12475 {
12476 _bfd_error_handler
12477 /* xgettext:c-format */
12484 }
12486 /* Mask out the value and U bit. */
12489 /* Set the U bit if the value to go in the place is non-negative. */
12493 /* Encode the offset. */
12497 }
12506 {
12510 /* sb is the origin of the *segment* containing the symbol. */
12512 bfd_vma residual;
12513 bfd_signed_vma signed_value;
12516 /* Determine which groups of bits to calculate. */
12518 {
12536 }
12538 /* If REL, extract the addend from the insn. If RELA, it will
12539 have already been fetched for us. */
12541 {
12544 }
12546 /* Compute the value (X) to go in the place. */
12550 /* PC relative. */
12552 else
12553 /* Section base relative. */
12556 /* Calculate the value of the relevant G_{n-1} to obtain
12557 the residual at that stage. */
12561 /* Check for overflow. (The absolute value to go in the place must be
12562 divisible by four and, after having been divided by four, must
12563 fit in eight bits.) */
12565 {
12566 _bfd_error_handler
12567 /* xgettext:c-format */
12574 }
12576 /* Mask out the value and U bit. */
12579 /* Set the U bit if the value to go in the place is non-negative. */
12583 /* Encode the offset. */
12587 }
12594 {
12600 /* Compute address. */
12606 /* Clean imm8 insn. */
12608 /* And update with correct part of address. */
12610 /* Update insn. */
12612 }
12618 {
12620 {
12625 {
12628 }
12635 {
12638 }
12640 /* Resolve relocation. */
12643 /* Emit R_ARM_FUNCDESC_VALUE or two fixups on funcdesc if
12644 not done yet. */
12648 }
12649 else
12650 {
12653 bfd_vma addr;
12656 /* For static binaries, sym_sec can be null. */
12658 {
12661 }
12662 else
12663 {
12666 }
12669 {
12672 }
12674 /* This case cannot occur since funcdesc is allocated by
12675 the dynamic loader so we cannot resolve the relocation. */
12677 {
12680 }
12682 /* Resolve relocation. */
12685 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12689 }
12690 }
12695 {
12697 {
12698 Elf_Internal_Rela outrel;
12700 /* Resolve relocation. */
12704 /* Add funcdesc and associated R_ARM_FUNCDESC_VALUE. */
12706 {
12709 bfd_vma addr;
12712 /* For static binaries sym_sec can be null. */
12714 {
12717 }
12718 else
12719 {
12722 }
12724 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12728 }
12730 /* Add a dynamic relocation on GOT entry if not already done. */
12732 {
12734 {
12739 else
12743 sgot->contents
12745 }
12746 else
12747 {
12749 }
12757 else
12760 else
12763 }
12764 }
12765 else
12766 {
12767 /* Such relocation on static function should not have been
12768 emitted by the compiler. */
12770 }
12771 }
12776 {
12778 {
12780 Elf_Internal_Rela outrel;
12784 {
12787 }
12794 {
12797 }
12799 /* Replace static FUNCDESC relocation with a
12800 R_ARM_RELATIVE dynamic relocation or with a rofixup for
12801 executable. */
12808 else
12814 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12818 }
12819 else
12820 {
12822 {
12825 bfd_vma addr;
12827 Elf_Internal_Rela outrel;
12829 /* For static binaries sym_sec can be null. */
12831 {
12834 }
12835 else
12836 {
12839 }
12844 /* Replace static FUNCDESC relocation with a
12845 R_ARM_RELATIVE dynamic relocation. */
12852 else
12858 /* Emit R_ARM_FUNCDESC_VALUE on funcdesc if not done yet. */
12862 }
12863 else
12864 {
12865 Elf_Internal_Rela outrel;
12867 /* Add a dynamic relocation. */
12873 }
12874 }
12875 }
12880 {
12881 bfd_vma relocation;
12886 {
12894 /* Sign extend. */
12896 }
12903 /* Put RELOCATION back into the insn. */
12904 {
12911 }
12913 /* Put the relocated value back in the object file: */
12918 }
12921 {
12922 bfd_vma relocation;
12927 {
12935 /* Sign extend. */
12938 }
12945 /* Put RELOCATION back into the insn. */
12946 {
12953 }
12955 /* Put the relocated value back in the object file: */
12960 }
12963 {
12964 bfd_vma relocation;
12969 {
12977 /* Sign extend. */
12980 }
12987 /* Put RELOCATION back into the insn. */
12988 {
12995 }
12997 /* Put the relocated value back in the object file: */
13002 }
13006 }
13007 }
13009 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
13010 static void
13014 bfd_signed_vma increment)
13015 {
13016 bfd_signed_vma addend;
13020 {
13038 }
13039 else
13040 {
13041 bfd_vma contents;
13045 /* Get the (signed) value from the instruction. */
13048 {
13049 bfd_signed_vma mask;
13054 }
13056 /* Add in the increment, (which is a byte value). */
13058 {
13070 /* Should we check for overflow here ? */
13072 /* Drop any undesired bits. */
13075 }
13080 }
13081 }
13083 #define IS_ARM_TLS_RELOC(R_TYPE) \
13084 ((R_TYPE) == R_ARM_TLS_GD32 \
13085 || (R_TYPE) == R_ARM_TLS_GD32_FDPIC \
13086 || (R_TYPE) == R_ARM_TLS_LDO32 \
13087 || (R_TYPE) == R_ARM_TLS_LDM32 \
13088 || (R_TYPE) == R_ARM_TLS_LDM32_FDPIC \
13089 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
13090 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
13091 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
13092 || (R_TYPE) == R_ARM_TLS_LE32 \
13093 || (R_TYPE) == R_ARM_TLS_IE32 \
13094 || (R_TYPE) == R_ARM_TLS_IE32_FDPIC \
13095 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
13097 /* Specific set of relocations for the gnu tls dialect. */
13098 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
13099 ((R_TYPE) == R_ARM_TLS_GOTDESC \
13100 || (R_TYPE) == R_ARM_TLS_CALL \
13101 || (R_TYPE) == R_ARM_THM_TLS_CALL \
13102 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
13103 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
13105 /* Relocate an ARM ELF section. */
13107 static int
13116 {
13134 {
13141 bfd_vma relocation;
13142 bfd_reloc_status_type r;
13143 arelent bfd_reloc;
13166 {
13171 /* An object file might have a reference to a local
13172 undefined symbol. This is a daft object file, but we
13173 should at least do something about it. V4BX & NONE
13174 relocations do not use the symbol and are explicitly
13175 allowed to use the undefined symbol, so allow those.
13176 Likewise for relocations against STN_UNDEF. */
13189 {
13196 {
13201 {
13223 {
13224 _bfd_error_handler
13225 /* xgettext:c-format */
13231 }
13235 /* Get the (signed) value from the instruction. */
13238 {
13239 bfd_signed_vma mask;
13244 }
13246 }
13249 addend =
13254 /* Cases here must match those in the preceding
13255 switch statement. */
13257 {
13280 }
13281 }
13282 }
13283 else
13285 }
13286 else
13287 {
13296 }
13303 {
13304 /* This is a relocatable link. We don't have to change
13305 anything, unless the reloc is against a section symbol,
13306 in which case we have to adjust according to where the
13307 section symbol winds up in the output section. */
13309 {
13313 else
13315 }
13317 }
13321 else
13322 {
13323 name = (bfd_elf_string_from_elf_section
13327 }
13335 {
13336 _bfd_error_handler
13338 /* xgettext:c-format */
13340 /* xgettext:c-format */
13342 input_bfd,
13343 input_section,
13346 name);
13347 }
13349 /* We call elf32_arm_final_link_relocate unless we're completely
13350 done, i.e., the relaxation produced the final output we want,
13351 and we won't let anybody mess with it. Also, we have to do
13352 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
13353 both in relaxed and non-relaxed cases. */
13359 {
13362 /* This may have been marked unresolved because it came from
13363 a shared library. But we've just dealt with that. */
13365 }
13366 else
13370 {
13381 }
13383 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
13384 because such sections are not SEC_ALLOC and thus ld.so will
13385 not process them. */
13391 {
13392 _bfd_error_handler
13393 /* xgettext:c-format */
13396 input_bfd,
13397 input_section,
13402 }
13405 {
13407 {
13409 /* If the overflowing reloc was to an undefined symbol,
13410 we have already printed one error message and there
13411 is no point complaining again. */
13432 /* error_message should already be set. */
13437 /* Fall through. */
13439 common_error:
13444 }
13445 }
13446 }
13449 }
13451 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
13452 adds the edit to the start of the list. (The list must be built in order of
13453 ascending TINDEX: the function's callers are primarily responsible for
13454 maintaining that condition). */
13456 static void
13459 arm_unwind_edit_type type,
13462 {
13471 {
13481 }
13482 else
13483 {
13490 }
13491 }
13495 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
13497 static void
13499 {
13507 /* Adjust size of output section. */
13509 }
13511 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
13513 static void
13515 {
13519 add_unwind_table_edit
13527 }
13529 /* Scan .ARM.exidx tables, and create a list describing edits which should be
13530 made to those tables, such that:
13532 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
13533 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
13534 codes which have been inlined into the index).
13536 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
13538 The edits are applied when the tables are written
13539 (in elf32_arm_write_section). */
13541 bool
13546 {
13553 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
13554 text sections. */
13556 {
13560 {
13568 {
13569 Elf_Internal_Shdr *linked_hdr
13577 /* Link this .ARM.exidx section back from the text section it
13578 describes. */
13580 }
13581 }
13582 }
13584 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
13585 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
13586 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
13589 {
13596 bfd_vma j;
13607 {
13608 /* Section has no unwind data. */
13612 /* Ignore zero sized sections. */
13619 }
13621 /* Skip /DISCARD/ sections. */
13638 /* An error? */
13642 {
13644 /* Add cantunwind if first unwind item does not match section
13645 start. */
13647 {
13650 }
13651 }
13654 {
13659 /* An EXIDX_CANTUNWIND entry. */
13661 {
13665 }
13666 /* Inlined unwinding data. Merge if equal to previous. */
13668 {
13674 }
13675 /* Normal table entry. In theory we could merge these too,
13676 but duplicate entries are likely to be much less common. */
13677 else
13681 {
13686 }
13689 }
13691 /* Free contents if we allocated it ourselves. */
13695 /* Record edits to be applied later (in elf32_arm_write_section). */
13704 }
13706 /* Add terminating CANTUNWIND entry. */
13712 }
13714 static bool
13717 {
13733 }
13735 static bool
13737 {
13744 /* Invoke the regular ELF backend linker to do all the work. */
13748 /* Process stub sections (eg BE8 encoding, ...). */
13752 {
13754 /* Only process it once, in its link_sec slot. */
13756 {
13762 }
13763 }
13765 /* Write out any glue sections now that we have created all the
13766 stubs. */
13768 {
13771 ARM2THUMB_GLUE_SECTION_NAME))
13776 THUMB2ARM_GLUE_SECTION_NAME))
13781 VFP11_ERRATUM_VENEER_SECTION_NAME))
13786 STM32L4XX_ERRATUM_VENEER_SECTION_NAME))
13791 ARM_BX_GLUE_SECTION_NAME))
13793 }
13796 }
13798 /* Return a best guess for the machine number based on the attributes. */
13800 static unsigned int
13802 {
13806 {
13813 {
13820 {
13828 {
13834 {
13838 }
13839 }
13840 }
13843 }
13877 /* Force entry to be added for any new known Tag_CPU_arch value. */
13880 /* Unknown Tag_CPU_arch value. */
13882 }
13883 }
13885 /* Set the right machine number. */
13887 static bool
13889 {
13895 {
13898 else
13900 }
13904 }
13906 /* Function to keep ARM specific flags in the ELF header. */
13908 static bool
13910 {
13913 {
13915 {
13917 _bfd_error_handler
13918 (_("warning: not setting interworking flag of %pB since it has already been specified as non-interworking"),
13919 abfd);
13920 else
13921 _bfd_error_handler
13923 abfd);
13924 }
13925 }
13926 else
13927 {
13930 }
13933 }
13935 /* Copy backend specific data from one object module to another. */
13937 static bool
13939 {
13940 flagword in_flags;
13941 flagword out_flags;
13952 {
13953 /* Cannot mix APCS26 and APCS32 code. */
13957 /* Cannot mix float APCS and non-float APCS code. */
13961 /* If the src and dest have different interworking flags
13962 then turn off the interworking bit. */
13964 {
13966 _bfd_error_handler
13967 (_("warning: clearing the interworking flag of %pB because non-interworking code in %pB has been linked with it"),
13971 }
13973 /* Likewise for PIC, though don't warn for this case. */
13976 }
13982 }
13984 /* Values for Tag_ABI_PCS_R9_use. */
13985 enum
13986 {
13987 AEABI_R9_V6,
13988 AEABI_R9_SB,
13989 AEABI_R9_TLS,
13990 AEABI_R9_unused
13991 };
13993 /* Values for Tag_ABI_PCS_RW_data. */
13994 enum
13995 {
13996 AEABI_PCS_RW_data_absolute,
13997 AEABI_PCS_RW_data_PCrel,
13998 AEABI_PCS_RW_data_SBrel,
13999 AEABI_PCS_RW_data_unused
14000 };
14002 /* Values for Tag_ABI_enum_size. */
14003 enum
14004 {
14005 AEABI_enum_unused,
14006 AEABI_enum_short,
14007 AEABI_enum_wide,
14008 AEABI_enum_forced_wide
14009 };
14011 /* Determine whether an object attribute tag takes an integer, a
14012 string or both. */
14014 static int
14016 {
14025 else
14027 }
14029 /* The ABI defines that Tag_conformance should be emitted first, and that
14030 Tag_nodefaults should be second (if either is defined). This sets those
14031 two positions, and bumps up the position of all the remaining tags to
14032 compensate. */
14033 static int
14035 {
14045 }
14047 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
14048 static bool
14050 {
14052 {
14053 _bfd_error_handler
14058 }
14059 else
14060 {
14061 _bfd_error_handler
14065 }
14066 }
14068 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
14069 Returns -1 if no architecture could be read. */
14071 static int
14073 {
14077 /* Note: the tag and its argument below are uleb128 values, though
14078 currently-defined values fit in one byte for each. */
14085 /* This tag is "safely ignorable", so don't complain if it looks funny. */
14087 }
14089 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
14090 The tag is removed if ARCH is -1. */
14092 static void
14094 {
14099 {
14102 }
14104 /* Note: the tag and its argument below are uleb128 values, though
14105 currently-defined values fit in one byte for each. */
14111 }
14113 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
14114 into account. */
14116 static int
14119 {
14120 #define T(X) TAG_CPU_ARCH_##X
14123 {
14133 };
14135 {
14146 };
14148 {
14160 };
14162 {
14175 };
14177 {
14191 };
14193 {
14208 };
14210 {
14233 };
14235 {
14252 };
14254 {
14272 };
14274 {
14293 };
14295 {
14318 };
14320 {
14344 };
14346 {
14371 };
14373 {
14374 v6t2,
14375 v6k,
14376 v7,
14377 v6_m,
14378 v6s_m,
14379 v7e_m,
14380 v8,
14381 v8r,
14382 v8m_baseline,
14383 v8m_mainline,
14384 NULL,
14385 NULL,
14386 NULL,
14387 v8_1m_mainline,
14388 v9,
14389 /* Pseudo-architecture. */
14390 v4t_plus_v6_m
14391 };
14393 /* Check we've not got a higher architecture than we know about. */
14396 {
14399 }
14401 /* Override old tag if we have a Tag_also_compatible_with on the output. */
14407 /* And override the new tag if we have a Tag_also_compatible_with on the
14408 input. */
14417 /* Architectures before V6KZ add features monotonically. */
14423 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
14424 as the canonical version. */
14426 {
14429 }
14430 else
14434 {
14438 }
14441 #undef T
14442 }
14444 /* Query attributes object to see if integer divide instructions may be
14445 present in an object. */
14446 static bool
14448 {
14453 {
14455 /* Integer divide allowed if instruction contained in archetecture. */
14460 else
14464 /* Integer divide explicitly prohibited. */
14468 /* Unrecognised case - treat as allowing divide everywhere. */
14470 /* Integer divide allowed in ARM state. */
14472 }
14473 }
14475 /* Query attributes object to see if integer divide instructions are
14476 forbidden to be in the object. This is not the inverse of
14477 elf32_arm_attributes_accept_div. */
14478 static bool
14480 {
14482 }
14484 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
14485 are conflicting attributes. */
14487 static bool
14489 {
14493 /* Some tags have 0 = don't care, 1 = strong requirement,
14494 2 = weak requirement. */
14500 /* Skip the linker stubs file. This preserves previous behavior
14501 of accepting unknown attributes in the first input file - but
14502 is that a bug? */
14506 /* Skip any input that hasn't attribute section.
14507 This enables to link object files without attribute section with
14508 any others. */
14513 {
14514 /* This is the first object. Copy the attributes. */
14519 /* Use the Tag_null value to indicate the attributes have been
14520 initialized. */
14523 /* We do not output objects with Tag_MPextension_use_legacy - we move
14524 the attribute's value to Tag_MPextension_use. */
14526 {
14530 {
14531 _bfd_error_handler
14535 }
14541 }
14543 /* PR 28859 and 28848: Handle the case where the first input file,
14544 eg crti.o, has a Tag_ABI_HardFP_use of 3 but no Tag_FP_arch set.
14545 Using Tag_ABI_HardFP_use in this way is deprecated, so reset the
14546 attribute to zero.
14547 FIXME: Should we handle other non-zero values of Tag_ABI_HardFO_use ? */
14552 }
14556 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
14558 {
14559 /* Ignore mismatches if the object doesn't use floating point or is
14560 floating point ABI independent. */
14567 {
14568 _bfd_error_handler
14573 }
14574 }
14577 {
14578 /* Merge this attribute with existing attributes. */
14580 {
14583 /* These are merged after Tag_CPU_arch. */
14588 /* Use the first value seen. */
14592 {
14597 {
14598 /* These aren't real CPU names, but we can't guess
14599 that from the architecture version alone. */
14623 };
14625 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
14631 secondary_compat,
14632 name_table);
14634 /* Return with error if failed to merge. */
14642 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
14646 {
14647 /* The output architecture has been changed to match the
14648 input architecture. Use the input names. */
14655 }
14656 else
14657 {
14660 }
14662 /* If we still don't have a value for Tag_CPU_name,
14663 make one up now. Tag_CPU_raw_name remains blank. */
14668 }
14675 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
14689 /* Use the largest value specified. */
14696 /* Use the smallest value specified. */
14705 {
14706 /* This error message should be enabled once all non-conformant
14707 binaries in the toolchain have had the attributes set
14708 properly.
14709 _bfd_error_handler
14710 (_("error: %pB: 8-byte data alignment conflicts with %pB"),
14711 obfd, ibfd);
14712 result = false; */
14713 }
14714 /* Fall through. */
14717 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
14718 value if greater than 2 (for future-proofing). */
14726 /* The virtualization tag effectively stores two bits of
14727 information: the intended use of TrustZone (in bit 0), and the
14728 intended use of Virtualization (in bit 1). */
14733 {
14736 else
14737 {
14738 _bfd_error_handler
14743 }
14744 }
14749 {
14750 /* 0 will merge with anything.
14751 'A' and 'S' merge to 'A'.
14752 'R' and 'S' merge to 'R'.
14753 'M' and 'A|R|S' is an error. */
14762 else
14763 {
14764 _bfd_error_handler
14766 ibfd,
14770 }
14771 }
14775 /* No need to change output value if any of:
14776 - pre (<=) ARMv5T input architecture (do not have DSP)
14777 - M input profile not ARMv7E-M and do not have DSP. */
14783 /* Output value should be 0 if DSP part of architecture, ie.
14784 - post (>=) ARMv5te architecture output
14785 - A, R or S profile output or ARMv7E-M output architecture. */
14792 /* Otherwise, DSP instructions are added and not part of output
14793 architecture. */
14794 else
14799 {
14800 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
14801 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
14802 when it's 0. It might mean absence of FP hardware if
14803 Tag_FP_arch is zero. */
14805 #define VFP_VERSION_COUNT 9
14806 static const struct
14807 {
14811 {
14821 };
14826 /* If the output has no requirement about FP hardware,
14827 follow the requirement of the input. */
14829 {
14830 /* This assert is still reasonable, we shouldn't
14831 produce the suspicious build attribute
14832 combination (See below for in_attr). */
14838 }
14839 /* If the input has no requirement about FP hardware, do
14840 nothing. */
14842 {
14843 /* We used to assert that Tag_ABI_HardFP_use was
14844 zero here, but we should never assert when
14845 consuming an object file that has suspicious
14846 build attributes. The single precision variant
14847 of 'no FP architecture' is still 'no FP
14848 architecture', so we just ignore the tag in this
14849 case. */
14851 }
14853 /* Both the input and the output have nonzero Tag_FP_arch.
14854 So Tag_ABI_HardFP_use is implied by Tag_FP_arch when it's zero. */
14856 /* If both the input and the output have zero Tag_ABI_HardFP_use,
14857 do nothing. */
14860 ;
14861 /* If the input and the output have different Tag_ABI_HardFP_use,
14862 the combination of them is 0 (implied by Tag_FP_arch). */
14867 /* Now we can handle Tag_FP_arch. */
14869 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
14870 pick the biggest. */
14873 {
14876 }
14877 /* The output uses the superset of input features
14878 (ISA version) and registers. */
14885 /* This assumes all possible supersets are also a valid
14886 options. */
14888 {
14892 }
14894 }
14900 {
14901 /* It's sometimes ok to mix different configs, so this is only
14902 a warning. */
14903 _bfd_error_handler
14905 }
14911 {
14912 _bfd_error_handler
14915 }
14923 {
14924 _bfd_error_handler
14926 ibfd);
14928 }
14929 /* Use the smallest value specified. */
14936 {
14937 _bfd_error_handler
14938 (_("warning: %pB uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
14940 }
14946 {
14949 {
14950 /* The existing object is compatible with anything.
14951 Use whatever requirements the new object has. */
14953 }
14957 {
14968 _bfd_error_handler
14969 (_("warning: %pB uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
14971 }
14972 }
14975 /* Aready done. */
14979 {
14980 _bfd_error_handler
14984 }
14987 /* Merged in target-independent code. */
14990 /* This is handled along with Tag_FP_arch. */
14994 {
14996 {
14997 _bfd_error_handler
15001 }
15002 }
15008 /* A value of zero on input means that the divide instruction may
15009 be used if available in the base architecture as specified via
15010 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
15011 the user did not want divide instructions. A value of 2
15012 explicitly means that divide instructions were allowed in ARM
15013 and Thumb state. */
15027 /* We don't output objects with Tag_MPextension_use_legacy - we
15028 move the value to Tag_MPextension_use. */
15030 {
15032 {
15033 _bfd_error_handler
15036 ibfd);
15038 }
15039 }
15047 /* This tag is set if it exists, but the value is unused (and is
15048 typically zero). We don't actually need to do anything here -
15049 the merge happens automatically when the type flags are merged
15050 below. */
15053 /* Already done in Tag_CPU_arch. */
15056 /* Keep the attribute if it matches. Throw it away otherwise.
15057 No attribute means no claim to conform. */
15064 result
15066 }
15068 /* If out_attr was copied from in_attr then it won't have a type yet. */
15071 }
15073 /* Merge Tag_compatibility attributes and any common GNU ones. */
15077 /* Check for any attributes not known on ARM. */
15081 }
15084 /* Return TRUE if the two EABI versions are incompatible. */
15086 static bool
15088 {
15089 /* v4 and v5 are the same spec before and after it was released,
15090 so allow mixing them. */
15096 }
15098 /* Merge backend specific data from an object file to the output
15099 object file when linking. */
15101 static bool
15104 /* Display the flags field. */
15106 static bool
15108 {
15114 /* Print normal ELF private data. */
15118 /* Ignore init flag - it may not be set, despite the flags field
15119 containing valid data. */
15124 {
15126 /* The following flag bits are GNU extensions and not part of the
15127 official ARM ELF extended ABI. Hence they are only decoded if
15128 the EABI version is not set. */
15134 else
15141 else
15170 else
15181 else
15213 eabi:
15226 }
15247 }
15249 static int
15251 {
15253 {
15258 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
15259 This allows us to distinguish between data used by Thumb instructions
15260 and non-data (which is probably code) inside Thumb regions of an
15261 executable. */
15268 }
15271 }
15279 {
15282 {
15286 }
15289 }
15291 /* Look through the relocs for a section during the first phase. */
15293 static bool
15296 {
15333 {
15345 /* PR 9934: It is possible to have relocations that do not
15346 refer to symbols, thus it is also possible to have an
15347 object file containing relocations but no symbol table. */
15349 {
15351 r_symndx);
15353 }
15358 {
15360 {
15361 /* A local symbol. */
15366 }
15367 else
15368 {
15373 }
15374 }
15382 /* Could be done earlier, if h were already available. */
15385 {
15387 {
15389 {
15396 }
15397 else
15398 {
15400 }
15401 }
15405 {
15407 {
15408 /* Such a relocation is not supposed to be generated
15409 by gcc on a static function. */
15410 /* Anyway if needed it could be handled. */
15412 }
15413 else
15414 {
15416 }
15417 }
15421 {
15423 {
15430 }
15431 else
15432 {
15434 }
15435 }
15449 /* This symbol requires a global offset table entry. */
15450 {
15454 {
15467 }
15473 {
15476 }
15477 else
15478 {
15479 /* This is a global offset table entry for a local symbol. */
15483 {
15485 r_symndx);
15487 }
15491 }
15493 /* If a variable is accessed with both tls methods, two
15494 slots may be created. */
15499 /* We will already have issued an error message if there
15500 is a TLS/non-TLS mismatch, based on the symbol
15501 type. So just combine any TLS types needed. */
15506 /* If the symbol is accessed in both IE and GDESC
15507 method, we're able to relax. Turn off the GDESC flag,
15508 without messing up with any other kind of tls types
15509 that may be involved. */
15514 {
15517 else
15519 }
15520 }
15521 /* Fall through. */
15527 /* Fall through. */
15549 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
15550 ldr __GOTT_INDEX__ offsets. */
15552 {
15555 }
15558 /* Fall through. */
15565 {
15566 _bfd_error_handler
15567 (_("%pB: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
15572 }
15574 /* Fall through. */
15577 jump_over:
15579 {
15581 }
15582 /* Fall through. */
15590 /* Should the interworking branches be listed here? */
15594 {
15597 {
15598 /* In shared libraries and relocatable executables,
15599 we treat local relative references as calls;
15600 see the related SYMBOL_CALLS_LOCAL code in
15601 allocate_dynrelocs. */
15604 }
15605 else
15606 /* We are creating a shared library or relocatable
15607 executable, and this is a reloc against a global symbol,
15608 or a non-PC-relative reloc against a local symbol.
15609 We may need to copy the reloc into the output. */
15611 }
15612 else
15616 /* This relocation describes the C++ object vtable hierarchy.
15617 Reconstruct it for later use during GC. */
15623 /* This relocation describes which C++ vtable entries are actually
15624 used. Record for later use during GC. */
15629 }
15632 {
15634 /* We may need a .plt entry if the function this reloc
15635 refers to is in a different object, regardless of the
15636 symbol's type. We can't tell for sure yet, because
15637 something later might force the symbol local. */
15640 /* If this reloc is in a read-only section, we might
15641 need a copy reloc. We can't check reliably at this
15642 stage whether the section is read-only, as input
15643 sections have not yet been mapped to output sections.
15644 Tentatively set the flag for now, and correct in
15645 adjust_dynamic_symbol. */
15647 }
15651 {
15657 {
15660 }
15661 else
15662 {
15668 }
15670 /* If the symbol is a function that doesn't bind locally,
15671 this relocation will need a PLT entry. */
15678 /* It's too early to use htab->use_blx here, so we have to
15679 record possible blx references separately from
15680 relocs that definitely need a thumb stub. */
15688 }
15691 {
15694 /* Create a reloc section in dynobj. */
15696 {
15697 sreloc = _bfd_elf_make_dynamic_reloc_section
15702 }
15704 /* If this is a global symbol, count the number of
15705 relocations we need for this symbol. */
15708 else
15709 {
15713 }
15717 {
15728 }
15735 {
15736 /* Here we only support R_ARM_ABS32 and R_ARM_ABS32_NOI
15737 that will become rofixup. */
15738 /* This is due to the fact that we suppose all will become rofixup. */
15739 _bfd_error_handler
15744 }
15745 }
15746 }
15749 }
15751 static void
15754 {
15776 {
15779 }
15781 {
15784 }
15785 else
15797 {
15800 {
15803 irela++;
15804 count++;
15805 }
15807 {
15811 bfd_size_type j;
15812 bfd_vma offset;
15828 else
15832 {
15834 {
15836 bfd_vma bias;
15837 bfd_vma reloc_index;
15847 {
15848 bias++;
15850 }
15854 {
15856 irela++;
15857 count++;
15858 }
15861 }
15864 {
15865 /* New relocation entity. */
15874 irela++;
15875 count++;
15876 }
15877 }
15878 else
15879 {
15881 {
15884 irela++;
15885 }
15888 }
15889 }
15890 }
15898 {
15901 irela++;
15902 count--;
15903 }
15907 /* Hashes are no longer valid. */
15910 }
15912 /* Unwinding tables are not referenced directly. This pass marks them as
15913 required if the corresponding code section is marked. Similarly, ARMv8-M
15914 secure entry functions can only be referenced by SG veneers which are
15915 created after the GC process. They need to be marked in case they reside in
15916 their own section (as would be the case if code was compiled with
15917 -ffunction-sections). */
15919 static bool
15921 elf_gc_mark_hook_fn gc_mark_hook)
15922 {
15942 /* Marking EH data may cause additional code sections to be marked,
15943 requiring multiple passes. */
15946 {
15949 {
15957 {
15966 {
15970 }
15971 }
15973 /* Mark section holding ARMv8-M secure entry functions. We mark all
15974 of them so no need for a second browsing. */
15976 {
15985 /* Scan symbols. */
15987 {
15992 /* Assume it is a special symbol. If not, cmse_scan will
15993 warn about it and user can do something about it. */
15995 CMSE_PREFIX))
15996 {
16001 /* The debug sections related to these secure entry
16002 functions are marked on enabling below flag. */
16004 }
16005 }
16008 {
16009 /* Looping over all the sections of the object file containing
16010 Armv8-M secure entry functions and marking all the debug
16011 sections. */
16013 {
16014 /* If not a debug sections, skip it. */
16016 {
16019 }
16020 }
16022 }
16023 }
16024 }
16027 }
16029 /* PR 30354: If we have added extra marks then make sure that any
16030 dependencies of the newly marked sections are also marked. */
16035 }
16037 /* Treat mapping symbols as special target symbols. */
16039 static bool
16041 {
16043 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
16044 }
16046 /* If the ELF symbol SYM might be a function in SEC, return the
16047 function size and set *CODE_OFF to the function's entry point,
16048 otherwise return zero. */
16050 static bfd_size_type
16053 {
16054 bfd_size_type size;
16066 {
16068 /* Ignore symbols created by the annobin plugin for gcc and clang.
16069 These symbols are hidden, local, notype and have a size of 0. */
16074 /* Fall through. */
16077 /* FIXME: Allow STT_GNU_IFUNC as well ? */
16081 }
16085 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
16090 /* Do not return 0 for the function's size. */
16093 }
16095 static bool
16100 {
16106 }
16108 /* Adjust a symbol defined by a dynamic object and referenced by a
16109 regular object. The current definition is in some section of the
16110 dynamic object, but we're not including those sections. We have to
16111 change the definition to something the rest of the link can
16112 understand. */
16114 static bool
16117 {
16129 /* Make sure we know what is going on here. */
16140 /* If this is a function, put it in the procedure linkage table. We
16141 will fill in the contents of the procedure linkage table later,
16142 when we know the address of the .got section. */
16144 {
16145 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
16146 symbol binds locally. */
16152 {
16153 /* This case can occur if we saw a PLT32 reloc in an input
16154 file, but the symbol was never referred to by a dynamic
16155 object, or if all references were garbage collected. In
16156 such a case, we don't actually need to build a procedure
16157 linkage table, and we can just do a PC24 reloc instead. */
16163 }
16166 }
16167 else
16168 {
16169 /* It's possible that we incorrectly decided a .plt reloc was
16170 needed for an R_ARM_PC24 or similar reloc to a non-function sym
16171 in check_relocs. We can't decide accurately between function
16172 and non-function syms in check-relocs; Objects loaded later in
16173 the link may change h->type. So fix it now. */
16178 }
16180 /* If this is a weak symbol, and there is a real definition, the
16181 processor independent code will have arranged for us to see the
16182 real definition first, and we can just use the same value. */
16184 {
16190 }
16192 /* If there are no non-GOT references, we do not need a copy
16193 relocation. */
16197 /* This is a reference to a symbol defined by a dynamic object which
16198 is not a function. */
16200 /* If we are creating a shared library, we must presume that the
16201 only references to the symbol are via the global offset table.
16202 For such cases we need not do anything here; the relocations will
16203 be handled correctly by relocate_section. */
16207 /* We must allocate the symbol in our .dynbss section, which will
16208 become part of the .bss section of the executable. There will be
16209 an entry for this symbol in the .dynsym section. The dynamic
16210 object will contain position independent code, so all references
16211 from the dynamic object to this symbol will go through the global
16212 offset table. The dynamic linker will use the .dynsym entry to
16213 determine the address it must put in the global offset table, so
16214 both the dynamic object and the regular object will refer to the
16215 same memory location for the variable. */
16216 /* If allowed, we must generate a R_ARM_COPY reloc to tell the dynamic
16217 linker to copy the initial value out of the dynamic object and into
16218 the runtime process image. We need to remember the offset into the
16219 .rel(a).bss section we are going to use. */
16221 {
16224 }
16225 else
16226 {
16229 }
16233 {
16236 }
16239 }
16241 /* Allocate space in .plt, .got and associated reloc sections for
16242 dynamic relocs. */
16244 static bool
16246 {
16264 {
16265 /* Make sure this symbol is output as a dynamic symbol.
16266 Undefined weak syms won't yet be marked as dynamic. */
16269 {
16272 }
16274 /* If the call in the PLT entry binds locally, the associated
16275 GOT entry should use an R_ARM_IRELATIVE relocation instead of
16276 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
16277 than the .plt section. */
16279 {
16283 /* All non-call references can be resolved directly.
16284 This means that they can (and in some cases, must)
16285 resolve directly to the run-time target, rather than
16286 to the PLT. That in turns means that any .got entry
16287 would be equal to the .igot.plt entry, so there's
16288 no point having both. */
16290 }
16295 {
16298 /* If this symbol is not defined in a regular file, and we are
16299 not generating a shared library, then set the symbol to this
16300 location in the .plt. This is required to make function
16301 pointers compare as equal between the normal executable and
16302 the shared library. */
16305 {
16309 /* Make sure the function is not marked as Thumb, in case
16310 it is the target of an ABS32 relocation, which will
16311 point to the PLT entry. */
16313 }
16315 /* VxWorks executables have a second set of relocations for
16316 each PLT entry. They go in a separate relocation section,
16317 which is processed by the kernel loader. */
16319 {
16320 /* There is a relocation for the initial PLT entry:
16321 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
16325 /* There are two extra relocations for each subsequent
16326 PLT entry: an R_ARM_32 relocation for the GOT entry,
16327 and an R_ARM_32 relocation for the PLT entry. */
16329 }
16330 }
16331 else
16332 {
16335 }
16336 }
16337 else
16338 {
16341 }
16347 {
16353 /* Make sure this symbol is output as a dynamic symbol.
16354 Undefined weak syms won't yet be marked as dynamic. */
16359 {
16362 }
16371 /* Non-TLS symbols need one GOT slot. */
16373 else
16374 {
16376 {
16377 /* R_ARM_TLS_DESC needs 2 GOT slots. */
16378 eh->tlsdesc_got
16383 /* plt.got_offset needs to know there's a TLS_DESC
16384 reloc in the middle of .got.plt. */
16386 }
16389 {
16390 /* R_ARM_TLS_GD32 and R_ARM_TLS_GD32_FDPIC need two
16391 consecutive GOT slots. If the symbol is both GD
16392 and GDESC, got.offset may have been
16393 overwritten. */
16396 }
16399 /* R_ARM_TLS_IE32/R_ARM_TLS_IE32_FDPIC need one GOT
16400 slot. */
16402 }
16416 {
16424 {
16426 /* GDESC needs a trampoline to jump to. */
16428 }
16430 /* Only GD needs it. GDESC just emits one relocation per
16431 2 entries. */
16434 }
16437 {
16439 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
16441 }
16444 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
16445 they all resolve dynamically instead. Reserve room for the
16446 GOT entry's R_ARM_IRELATIVE relocation. */
16450 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
16453 /* Reserve room for rofixup for FDPIC executable. */
16454 /* TLS relocs do not need space since they are completely
16455 resolved. */
16457 }
16458 else
16461 /* FDPIC support. */
16463 {
16464 /* Symbol musn't be exported. */
16468 /* We only allocate one function descriptor with its associated
16469 relocation. */
16471 {
16476 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16479 else
16481 }
16482 }
16485 {
16494 {
16495 /* We only allocate one function descriptor with its
16496 associated relocation. */
16498 {
16502 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16503 rofixups. */
16506 else
16508 }
16509 }
16511 /* Add one entry into the GOT and a R_ARM_FUNCDESC or
16512 R_ARM_RELATIVE/rofixup relocation on it. */
16517 else
16519 }
16522 {
16529 {
16530 /* We only allocate one function descriptor with its
16531 associated relocation. */
16533 {
16538 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two
16539 rofixups. */
16542 else
16544 }
16545 }
16547 {
16548 /* For FDPIC executable we replace R_ARM_RELATIVE with a rofixup. */
16550 }
16551 else
16552 {
16553 /* Will need one dynamic reloc per reference. will be either
16554 R_ARM_FUNCDESC or R_ARM_RELATIVE for hidden symbols. */
16557 }
16558 }
16560 /* Allocate stubs for exported Thumb functions on v4t. */
16565 {
16572 /* Create a new symbol to regist the real location of the function. */
16586 /* Point the symbol at the stub. */
16591 }
16596 /* In the shared -Bsymbolic case, discard space allocated for
16597 dynamic pc-relative relocs against symbols which turn out to be
16598 defined in regular objects. For the normal shared case, discard
16599 space for pc-relative relocs that have become local due to symbol
16600 visibility changes. */
16604 {
16605 /* Relocs that use pc_count are PC-relative forms, which will appear
16606 on something like ".long foo - ." or "movw REG, foo - .". We want
16607 calls to protected symbols to resolve directly to the function
16608 rather than going via the plt. If people want function pointer
16609 comparisons to work as expected then they should avoid writing
16610 assembly like ".long foo - .". */
16612 {
16616 {
16621 else
16623 }
16624 }
16627 {
16631 {
16634 else
16636 }
16637 }
16639 /* Also discard relocs on undefined weak syms with non-default
16640 visibility. */
16643 {
16648 /* Make sure undefined weak symbols are output as a dynamic
16649 symbol in PIEs. */
16652 {
16655 }
16656 }
16657 }
16658 else
16659 {
16660 /* For the non-shared case, discard space for relocs against
16661 symbols which turn out to need copy relocs or are not
16662 dynamic. */
16670 {
16671 /* Make sure this symbol is output as a dynamic symbol.
16672 Undefined weak syms won't yet be marked as dynamic. */
16675 {
16678 }
16680 /* If that succeeded, we know we'll be keeping all the
16681 relocs. */
16684 }
16688 keep: ;
16689 }
16691 /* Finally, allocate space. */
16693 {
16705 else
16707 }
16710 }
16712 void
16715 {
16723 }
16725 /* Set the sizes of the dynamic sections. */
16727 static bool
16730 {
16746 {
16747 /* Set the contents of the .interp section to the interpreter. */
16749 {
16754 }
16755 }
16757 /* Set up .got offsets for local syms, and space for local dynamic
16758 relocs. */
16760 {
16766 bfd_size_type locsymcount;
16776 {
16781 {
16784 {
16785 /* Input section has been discarded, either because
16786 it is a copy of a linkonce section or due to
16787 linker script /DISCARD/, so we'll be discarding
16788 the relocs too. */
16789 }
16793 {
16794 /* Relocations in vxworks .tls_vars sections are
16795 handled specially by the loader. */
16796 }
16798 {
16802 else
16806 }
16807 }
16808 }
16827 {
16834 /* FDPIC support. */
16836 {
16838 {
16842 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16845 else
16847 }
16848 }
16851 {
16853 {
16857 /* We will add an R_ARM_FUNCDESC_VALUE relocation or two rofixups. */
16860 else
16862 }
16864 /* We will add n R_ARM_RELATIVE relocations or n rofixups. */
16867 else
16869 }
16872 {
16876 {
16881 /* All references to the PLT are calls, so all
16882 non-call references can resolve directly to the
16883 run-time target. This means that the .got entry
16884 would be the same as the .igot.plt entry, so there's
16885 no point creating both. */
16887 }
16888 else
16889 {
16892 }
16895 {
16901 else
16903 }
16904 }
16906 {
16911 /* TLS_GD relocs need an 8-byte structure in the GOT. */
16914 {
16919 /* plt.got_offset needs to know there's a TLS_DESC
16920 reloc in the middle of .got.plt. */
16922 }
16927 {
16928 /* If the symbol is both GD and GDESC, *local_got
16929 may have been overwritten. */
16932 }
16935 symndx);
16939 /* If all references to an STT_GNU_IFUNC PLT are calls,
16940 then all non-call references, including this GOT entry,
16941 resolve directly to the run-time target. */
16947 {
16955 {
16959 }
16960 }
16961 }
16962 else
16964 }
16965 }
16968 {
16969 /* Allocate two GOT entries and one dynamic relocation (if necessary)
16970 for R_ARM_TLS_LDM32/R_ARM_TLS_LDM32_FDPIC relocations. */
16975 }
16976 else
16979 /* At the very end of the .rofixup section is a pointer to the GOT,
16980 reserve space for it. */
16984 /* Allocate global sym .plt and .got entries, and space for global
16985 sym dynamic relocs. */
16988 /* Here we rummage through the found bfds to collect glue information. */
16990 {
16994 /* Initialise mapping tables for code/data. */
17001 }
17003 /* Allocate space for the glue sections now that we've sized them. */
17006 /* For every jump slot reserved in the sgotplt, reloc_count is
17007 incremented. However, when we reserve space for TLS descriptors,
17008 it's not incremented, so in order to compute the space reserved
17009 for them, it suffices to multiply the reloc count by the jump
17010 slot size. */
17015 {
17022 /* If we're not using lazy TLS relocations, don't generate the
17023 PLT and GOT entries they require. */
17026 else
17027 {
17033 }
17034 }
17036 /* The check_relocs and adjust_dynamic_symbol entry points have
17037 determined the sizes of the various dynamic sections. Allocate
17038 memory for them. */
17041 {
17047 /* It's OK to base decisions on the section name, because none
17048 of the dynobj section names depend upon the input files. */
17052 {
17053 /* Remember whether there is a PLT. */
17054 ;
17055 }
17057 {
17059 {
17060 /* Remember whether there are any reloc sections other
17061 than .rel(a).plt and .rela.plt.unloaded. */
17065 /* We use the reloc_count field as a counter if we need
17066 to copy relocs into the output file. */
17068 }
17069 }
17077 {
17078 /* It's not one of our sections, so don't allocate space. */
17080 }
17083 {
17084 /* If we don't need this section, strip it from the
17085 output file. This is mostly to handle .rel(a).bss and
17086 .rel(a).plt. We must create both sections in
17087 create_dynamic_sections, because they must be created
17088 before the linker maps input sections to output
17089 sections. The linker does that before
17090 adjust_dynamic_symbol is called, and it is that
17091 function which decides whether anything needs to go
17092 into these sections. */
17095 }
17100 /* Allocate memory for the section contents. */
17104 }
17107 relocs);
17108 }
17110 /* Size sections even though they're not dynamic. We use it to setup
17111 _TLS_MODULE_BASE_, if needed. */
17113 static bool
17116 {
17128 {
17131 tlsbase = elf_link_hash_lookup
17135 {
17151 }
17152 }
17160 }
17162 /* Finish up dynamic symbol handling. We set the contents of various
17163 dynamic sections here. */
17165 static bool
17170 {
17179 {
17181 {
17186 }
17189 {
17190 /* Mark the symbol as undefined, rather than as defined in
17191 the .plt section. */
17193 /* If the symbol is weak we need to clear the value.
17194 Otherwise, the PLT entry would provide a definition for
17195 the symbol even if the symbol wasn't defined anywhere,
17196 and so the symbol would never be NULL. Leave the value if
17197 there were any relocations where pointer equality matters
17198 (this is a clue for the dynamic linker, to make function
17199 pointer comparisons work between an application and shared
17200 library). */
17203 }
17205 {
17206 /* At least one non-call relocation references this .iplt entry,
17207 so the .iplt entry is the function's canonical address. */
17215 }
17216 }
17219 {
17221 Elf_Internal_Rela rel;
17223 /* This symbol needs a copy reloc. Set it up. */
17235 else
17238 }
17240 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
17241 and for FDPIC, the _GLOBAL_OFFSET_TABLE_ symbol is not absolute:
17242 it is relative to the ".got" section. */
17250 }
17252 static void
17256 {
17260 {
17263 /* Emit mov pc,rx if bx is not permitted. */
17267 }
17268 }
17270 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
17271 other variants, NaCl needs this entry in a static executable's
17272 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
17273 zero. For .iplt really only the last bundle is useful, and .iplt
17274 could have a shorter first entry, with each individual PLT entry's
17275 relative branch calculated differently so it targets the last
17276 bundle instead of the instruction before it (labelled .Lplt_tail
17277 above). But it's simpler to keep the size and layout of PLT0
17278 consistent with the dynamic case, at the cost of some dead code at
17279 the start of .iplt and the one dead store to the stack at the start
17280 of .Lplt_tail. */
17281 static void
17284 {
17300 }
17302 /* Finish up the dynamic sections. */
17304 static bool
17306 {
17319 /* A broken linker script might have discarded the dynamic sections.
17320 Catch this here so that we do not seg-fault later on. */
17326 {
17338 {
17339 Elf_Internal_Dyn dyn;
17346 {
17366 get_vma:
17369 {
17370 _bfd_error_handler
17374 }
17406 /* Set the bottom bit of DT_INIT/FINI if the
17407 corresponding function is Thumb. */
17413 get_sym:
17414 /* If it wasn't set by elf_bfd_final_link
17415 then there is nothing to adjust. */
17417 {
17425 {
17428 }
17429 }
17431 }
17432 }
17434 /* Fill in the first entry in the procedure linkage table. */
17436 {
17440 /* Calculate the addresses of the GOT and PLT. */
17445 {
17446 /* The VxWorks GOT is relocated by the dynamic linker.
17447 Therefore, we must emit relocations rather than simply
17448 computing the values now. */
17449 Elf_Internal_Rela rel;
17460 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
17466 }
17471 {
17483 }
17484 else
17485 {
17498 #ifdef FOUR_WORD_PLT
17499 /* The displacement value goes in the otherwise-unused
17500 last word of the second entry. */
17502 #else
17504 #endif
17505 }
17506 }
17508 /* UnixWare sets the entsize of .plt to 4, although that doesn't
17509 really seem like the right value. */
17514 {
17515 bfd_vma got_address
17519 bfd_vma plt_address
17535 }
17538 {
17542 #ifdef FOUR_WORD_PLT
17545 #endif
17546 }
17551 {
17552 /* Correct the .rel(a).plt.unloaded relocations. They will have
17553 incorrect symbol indexes. */
17562 {
17563 Elf_Internal_Rela rel;
17574 }
17575 }
17576 }
17581 /* NaCl uses a special first entry in .iplt too. */
17584 /* Fill in the first three entries in the global offset table. */
17586 {
17588 {
17591 else
17597 }
17600 }
17602 /* At the very end of the .rofixup section is a pointer to the GOT. */
17604 {
17613 /* Make sure we allocated and generated the same number of fixups. */
17615 }
17618 }
17620 static bool
17622 {
17637 {
17644 }
17648 {
17652 else
17654 }
17656 /* Scan segment to set p_flags attribute if it contains only sections with
17657 SHF_ARM_PURECODE flag. */
17659 {
17665 {
17668 }
17670 {
17673 }
17674 }
17676 }
17678 static enum elf_reloc_type_class
17682 {
17687 {
17688 /* Check relocation against STT_GNU_IFUNC symbol if there are
17689 dynamic symbols. */
17694 {
17695 Elf_Internal_Sym sym;
17700 {
17701 /* xgettext:c-format */
17705 /* Ideally an error class should be returned here. */
17706 }
17709 }
17710 }
17713 {
17724 }
17725 }
17727 static void
17729 {
17731 }
17733 static bool
17735 {
17738 }
17740 /* Return TRUE if this is an unwinding table entry. */
17742 static bool
17744 {
17747 }
17750 /* Set the type and flags for an ARM section. We do this by
17751 the section name, which is a hack, but ought to work. */
17753 static bool
17755 {
17761 {
17764 }
17770 }
17772 /* Handle an ARM specific section when reading an object file. This is
17773 called when bfd_section_from_shdr finds a section with an unknown
17774 type. */
17776 static bool
17781 {
17782 /* There ought to be a place to keep ELF backend specific flags, but
17783 at the moment there isn't one. We just keep track of the
17784 sections by their name, instead. Fortunately, the ABI gives
17785 names for all the ARM specific sections, so we will probably get
17786 away with this. */
17788 {
17796 }
17802 }
17806 {
17809 else
17811 }
17814 {
17823 enum map_symbol_type
17824 {
17825 ARM_MAP_ARM,
17826 ARM_MAP_THUMB,
17827 ARM_MAP_DATA
17828 };
17831 /* Output a single mapping symbol. */
17833 static bool
17836 bfd_vma offset)
17837 {
17839 Elf_Internal_Sym sym;
17851 }
17853 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
17854 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
17856 static bool
17861 {
17873 {
17876 }
17877 else
17878 {
17881 }
17887 {
17896 }
17898 {
17901 }
17903 {
17905 ? ARM_MAP_THUMB
17918 }
17920 {
17923 }
17924 else
17925 {
17930 {
17933 }
17934 #ifdef FOUR_WORD_PLT
17939 #else
17940 /* A three-word PLT with no Thumb thunk contains only Arm code,
17941 so only need to output a mapping symbol for the first PLT entry and
17942 entries with thumb thunks. */
17944 {
17947 }
17948 #endif
17949 }
17952 }
17954 /* Output mapping symbols for PLT entries associated with H. */
17956 static bool
17958 {
17966 /* When warning symbols are created, they **replace** the "real"
17967 entry in the hash table, thus we never get to see the real
17968 symbol in a hash traversal. So look at it now. */
17974 }
17976 /* Bind a veneered symbol to its veneer identified by its hash entry
17977 STUB_ENTRY. The veneered location thus loose its symbol. */
17979 static void
17981 {
17988 }
17990 /* Output a single local symbol for a generated stub. */
17992 static bool
17995 {
17996 Elf_Internal_Sym sym;
18007 }
18009 static bool
18012 {
18015 bfd_vma addr;
18024 /* Massage our args to the form they really have. */
18030 /* Ensure this stub is attached to the current section being
18031 processed. */
18040 else
18041 {
18044 {
18059 }
18060 }
18065 {
18067 {
18084 }
18087 {
18091 }
18094 {
18111 }
18112 }
18115 }
18117 /* Output mapping symbols for linker generated sections,
18118 and for those data-only sections that do not have a
18119 $d. */
18121 static bool
18126 Elf_Internal_Sym *,
18127 asection *,
18129 {
18130 output_arch_syminfo osi;
18132 bfd_vma offset;
18133 bfd_size_type size;
18151 /* Add a $d mapping symbol to data-only sections that
18152 don't have any mapping symbol. This may result in (harmless) redundant
18153 mapping symbols. */
18157 {
18162 {
18167 == SEC_HAS_CONTENTS
18172 {
18177 }
18178 }
18179 }
18181 /* ARM->Thumb glue. */
18183 {
18185 ARM2THUMB_GLUE_SECTION_NAME);
18194 else
18198 {
18201 }
18202 }
18204 /* Thumb->ARM glue. */
18206 {
18208 THUMB2ARM_GLUE_SECTION_NAME);
18215 {
18218 }
18219 }
18221 /* ARMv4 BX veneers. */
18223 {
18225 ARM_BX_GLUE_SECTION_NAME);
18231 }
18233 /* Long calls stubs. */
18235 {
18241 {
18242 /* Ignore non-stub sections. */
18252 }
18253 }
18255 /* Finally, output mapping symbols for the PLT. */
18257 {
18262 /* Output mapping symbols for the plt header. */
18264 {
18265 /* VxWorks shared libraries have no PLT header. */
18267 {
18272 }
18273 }
18275 {
18278 }
18280 {
18287 }
18289 {
18292 #ifndef FOUR_WORD_PLT
18295 #endif
18296 }
18297 }
18301 {
18302 /* NaCl uses a special first entry in .iplt too. */
18308 }
18311 {
18316 {
18322 {
18325 {
18328 input_bfd,
18330 num_syms);
18332 }
18339 }
18340 }
18341 }
18343 {
18344 /* Mapping symbols for the lazy tls trampoline. */
18352 }
18354 {
18355 /* Mapping symbols for the tls trampoline. */
18358 #ifdef FOUR_WORD_PLT
18362 #endif
18363 }
18366 }
18368 /* Filter normal symbols of CMSE entry functions of ABFD to include in
18369 the import library. All SYMCOUNT symbols of ABFD can be examined
18370 from their pointers in SYMS. Pointers of symbols to keep should be
18371 stored continuously at the beginning of that array.
18373 Returns the number of symbols to keep. */
18375 static unsigned int
18379 {
18394 {
18397 flagword flags;
18412 {
18416 }
18428 }
18434 }
18436 /* Filter symbols of ABFD to include in the import library. All
18437 SYMCOUNT symbols of ABFD can be examined from their pointers in
18438 SYMS. Pointers of symbols to keep should be stored continuously at
18439 the beginning of that array.
18441 Returns the number of symbols to keep. */
18443 static unsigned int
18447 {
18450 /* Requirement 8 of "ARM v8-M Security Extensions: Requirements on
18451 Development Tools" (ARM-ECM-0359818) mandates Secure Gateway import
18452 library to be a relocatable object file. */
18456 else
18458 }
18460 /* Allocate target specific section data. */
18462 static bool
18464 {
18466 {
18474 }
18477 }
18480 /* Used to order a list of mapping symbols by address. */
18482 static int
18484 {
18493 /* Ensure results do not depend on the host qsort for objects with
18494 multiple mapping symbols at the same address by sorting on type
18495 after vma. */
18499 else
18501 }
18503 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
18505 static unsigned long
18507 {
18509 }
18511 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
18512 relocations. */
18514 static void
18516 {
18520 /* High bit of first word is supposed to be zero. */
18524 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
18525 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
18531 }
18533 /* Data for make_branch_to_a8_stub(). */
18535 struct a8_branch_to_stub_data
18536 {
18539 };
18542 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
18543 places for a particular section. */
18545 static bool
18548 {
18554 bfd_signed_vma branch_offset;
18567 /* We use target_section as Cortex-A8 erratum workaround stubs are only
18568 generated when both source and target are in the same section. */
18585 /* We attempt to avoid this condition by setting stubs_always_after_branch
18586 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
18587 This check is just to be on the safe side... */
18589 {
18593 }
18596 {
18607 {
18612 jump24:
18614 {
18615 /* There's not much we can do apart from complain if this
18616 happens. */
18620 }
18622 /* i1 = not(j1 eor s), so:
18623 not i1 = j1 eor s
18624 j1 = (not i1) eor s. */
18636 }
18642 }
18648 }
18650 /* Beginning of stm32l4xx work-around. */
18652 /* Functions encoding instructions necessary for the emission of the
18653 fix-stm32l4xx-629360.
18654 Encoding is extracted from the
18655 ARM (C) Architecture Reference Manual
18656 ARMv7-A and ARMv7-R edition
18657 ARM DDI 0406C.b (ID072512). */
18661 {
18662 /* A8.8.18 B (A8-334)
18663 B target_address (Encoding T4). */
18664 /* 1111 - 0Sii - iiii - iiii - 10J1 - Jiii - iiii - iiii. */
18665 /* jump offset is: S:I1:I2:imm10:imm11:0. */
18666 /* with : I1 = NOT (J1 EOR S) I2 = NOT (J2 EOR S). */
18683 }
18687 {
18688 /* A8.8.57 LDM/LDMIA/LDMFD (A8-396)
18689 LDMIA Rn!, {Ra, Rb, Rc, ...} (Encoding T2). */
18696 }
18700 {
18701 /* A8.8.60 LDMDB/LDMEA (A8-402)
18702 LDMDB Rn!, {Ra, Rb, Rc, ...} (Encoding T1). */
18709 }
18713 {
18714 /* A8.8.103 MOV (register) (A8-486)
18715 MOV Rd, Rm (Encoding T1). */
18722 }
18726 {
18727 /* A8.8.221 SUB (immediate) (A8-708)
18728 SUB Rd, Rn, #value (Encoding T3). */
18738 }
18743 {
18744 /* A8.8.332 VLDM (A8-922)
18745 VLMD{MODE} Rn{!}, {list} (Encoding T1 or T2). */
18754 }
18759 {
18760 /* A8.8.332 VLDM (A8-922)
18761 VLMD{MODE} Rn!, {} (Encoding T1 or T2). */
18769 }
18773 {
18774 /* A8.8.247 UDF (A8-758)
18775 Undefined (Encoding T2). */
18781 }
18785 {
18786 /* A8.8.247 UDF (A8-758)
18787 Undefined (Encoding T1). */
18792 }
18794 /* Functions writing an instruction in memory, returning the next
18795 memory position to write to. */
18800 {
18803 }
18808 {
18811 }
18813 /* Function filling up a region in memory with T1 and T2 UDFs taking
18814 care of alignment. */
18822 {
18825 /* Fill the remaining of the stub with deterministic contents : UDF
18826 instructions.
18827 Check if realignment is needed on modulo 4 frontier using T1, to
18828 further use T2. */
18832 current_stub_contents =
18837 current_stub_contents =
18842 }
18844 /* Functions writing the stream of instructions equivalent to the
18845 derived sequence for ldmia, ldmdb, vldm respectively. */
18847 static void
18853 {
18866 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
18867 smaller than 8 registers load sequences that do not cause the
18868 hardware issue. */
18870 {
18871 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
18872 current_stub_contents =
18874 initial_insn);
18876 /* B initial_insn_addr+4. */
18878 current_stub_contents =
18880 create_instruction_branch_absolute
18883 /* Fill the remaining of the stub with deterministic contents. */
18884 current_stub_contents =
18887 base_stub_contents +
18888 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18891 }
18893 /* - reg_list[13] == 0. */
18896 /* - reg_list[14] & reg_list[15] != 1. */
18899 /* - if (wback==1) reg_list[rn] == 0. */
18902 /* - nb_registers > 8. */
18905 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
18907 /* In the following algorithm, we split this wide LDM using 2 LDM insns:
18908 - One with the 7 lowest registers (register mask 0x007F)
18909 This LDM will finally contain between 2 and 7 registers
18910 - One with the 7 highest registers (register mask 0xDF80)
18911 This ldm will finally contain between 2 and 7 registers. */
18915 /* A spare register may be needed during this veneer to temporarily
18916 handle the base register. This register will be restored with the
18917 last LDM operation.
18918 The usable register may be any general purpose register (that
18919 excludes PC, SP, LR : register mask is 0x1FFF). */
18922 /* Generate the stub function. */
18924 {
18925 /* LDMIA Rn!, {R-low-register-list} : (Encoding T2). */
18926 current_stub_contents =
18928 create_instruction_ldmia
18931 /* LDMIA Rn!, {R-high-register-list} : (Encoding T2). */
18932 current_stub_contents =
18934 create_instruction_ldmia
18937 {
18938 /* B initial_insn_addr+4. */
18939 current_stub_contents =
18941 create_instruction_branch_absolute
18943 }
18944 }
18946 {
18949 /* If Rn is not part of the high-register-list, move it there. */
18951 {
18952 /* Choose a Ri in the high-register-list that will be restored. */
18955 /* MOV Ri, Rn. */
18956 current_stub_contents =
18959 }
18961 /* LDMIA Ri!, {R-low-register-list} : (Encoding T2). */
18962 current_stub_contents =
18964 create_instruction_ldmia
18967 /* LDMIA Ri, {R-high-register-list} : (Encoding T2). */
18968 current_stub_contents =
18970 create_instruction_ldmia
18974 {
18975 /* B initial_insn_addr+4. */
18976 current_stub_contents =
18978 create_instruction_branch_absolute
18980 }
18981 }
18983 /* Fill the remaining of the stub with deterministic contents. */
18984 current_stub_contents =
18987 base_stub_contents +
18988 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
18989 }
18991 static void
18997 {
19010 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19011 smaller than 8 registers load sequences that do not cause the
19012 hardware issue. */
19014 {
19015 /* UNTOUCHED : LDMIA Rn{!}, {R-all-register-list}. */
19016 current_stub_contents =
19018 initial_insn);
19020 /* B initial_insn_addr+4. */
19021 current_stub_contents =
19023 create_instruction_branch_absolute
19026 /* Fill the remaining of the stub with deterministic contents. */
19027 current_stub_contents =
19030 base_stub_contents +
19031 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19034 }
19036 /* - reg_list[13] == 0. */
19039 /* - reg_list[14] & reg_list[15] != 1. */
19042 /* - if (wback==1) reg_list[rn] == 0. */
19045 /* - nb_registers > 8. */
19048 /* At this point, LDMxx initial insn loads between 9 and 14 registers. */
19050 /* In the following algorithm, we split this wide LDM using 2 LDM insn:
19051 - One with the 7 lowest registers (register mask 0x007F)
19052 This LDM will finally contain between 2 and 7 registers
19053 - One with the 7 highest registers (register mask 0xDF80)
19054 This ldm will finally contain between 2 and 7 registers. */
19058 /* A spare register may be needed during this veneer to temporarily
19059 handle the base register. This register will be restored with
19060 the last LDM operation.
19061 The usable register may be any general purpose register (that excludes
19062 PC, SP, LR : register mask is 0x1FFF). */
19065 /* Generate the stub function. */
19067 {
19068 /* Choose a Ri in the low-register-list that will be restored. */
19071 /* MOV Ri, Rn. */
19072 current_stub_contents =
19076 /* LDMDB Ri!, {R-high-register-list}. */
19077 current_stub_contents =
19079 create_instruction_ldmdb
19082 /* LDMDB Ri, {R-low-register-list}. */
19083 current_stub_contents =
19085 create_instruction_ldmdb
19088 /* B initial_insn_addr+4. */
19089 current_stub_contents =
19091 create_instruction_branch_absolute
19093 }
19095 {
19096 /* LDMDB Rn!, {R-high-register-list}. */
19097 current_stub_contents =
19099 create_instruction_ldmdb
19102 /* LDMDB Rn!, {R-low-register-list}. */
19103 current_stub_contents =
19105 create_instruction_ldmdb
19108 /* B initial_insn_addr+4. */
19109 current_stub_contents =
19111 create_instruction_branch_absolute
19113 }
19115 {
19116 /* Choose a Ri in the high-register-list that will be restored. */
19119 /* SUB Ri, Rn, #(4*nb_registers). */
19120 current_stub_contents =
19124 /* LDMIA Ri!, {R-low-register-list}. */
19125 current_stub_contents =
19127 create_instruction_ldmia
19130 /* LDMIA Ri, {R-high-register-list}. */
19131 current_stub_contents =
19133 create_instruction_ldmia
19135 }
19137 {
19138 /* Choose a Ri in the high-register-list that will be restored. */
19141 /* SUB Rn, Rn, #(4*nb_registers) */
19142 current_stub_contents =
19146 /* MOV Ri, Rn. */
19147 current_stub_contents =
19151 /* LDMIA Ri!, {R-low-register-list}. */
19152 current_stub_contents =
19154 create_instruction_ldmia
19157 /* LDMIA Ri, {R-high-register-list}. */
19158 current_stub_contents =
19160 create_instruction_ldmia
19162 }
19164 {
19167 {
19168 /* Choose a Ri in the low-register-list that will be restored. */
19171 /* MOV Ri, Rn. */
19172 current_stub_contents =
19175 }
19177 /* LDMDB Ri!, {R-high-register-list}. */
19178 current_stub_contents =
19180 create_instruction_ldmdb
19183 /* LDMDB Ri, {R-low-register-list}. */
19184 current_stub_contents =
19186 create_instruction_ldmdb
19189 /* B initial_insn_addr+4. */
19190 current_stub_contents =
19192 create_instruction_branch_absolute
19194 }
19196 {
19199 {
19200 /* Choose a Ri in the high-register-list that will be restored. */
19202 }
19204 /* SUB Ri, Rn, #(4*nb_registers). */
19205 current_stub_contents =
19209 /* LDMIA Ri!, {R-low-register-list}. */
19210 current_stub_contents =
19212 create_instruction_ldmia
19215 /* LDMIA Ri, {R-high-register-list}. */
19216 current_stub_contents =
19218 create_instruction_ldmia
19220 }
19222 {
19223 /* The assembler should not have accepted to encode this. */
19226 }
19228 /* Fill the remaining of the stub with deterministic contents. */
19229 current_stub_contents =
19232 base_stub_contents +
19233 STM32L4XX_ERRATUM_LDM_VENEER_SIZE);
19235 }
19237 static void
19243 {
19249 /* In BFD_ARM_STM32L4XX_FIX_ALL mode we may have to deal with
19250 smaller than 8 words load sequences that do not cause the
19251 hardware issue. */
19253 {
19254 /* Untouched instruction. */
19255 current_stub_contents =
19257 initial_insn);
19259 /* B initial_insn_addr+4. */
19260 current_stub_contents =
19262 create_instruction_branch_absolute
19264 }
19265 else
19266 {
19276 /* d = UInt (Vd:D);. */
19280 /* Compute the number of 8-words chunks needed to split. */
19284 /* The test coverage has been done assuming the following
19285 hypothesis that exactly one of the previous is_ predicates is
19286 true. */
19290 /* We treat the cutting of the words in one pass for all
19291 cases, then we emit the adjustments:
19293 vldm rx, {...}
19294 -> vldm rx!, {8_words_or_less} for each needed 8_word
19295 -> sub rx, rx, #size (list)
19297 vldm rx!, {...}
19298 -> vldm rx!, {8_words_or_less} for each needed 8_word
19299 This also handles vpop instruction (when rx is sp)
19301 vldmd rx!, {...}
19302 -> vldmb rx!, {8_words_or_less} for each needed 8_word. */
19304 {
19308 {
19309 new_insn = create_instruction_vldmia
19311 is_dp,
19316 }
19318 {
19319 new_insn = create_instruction_vldmdb
19321 is_dp,
19325 }
19328 current_stub_contents =
19330 new_insn);
19331 }
19333 /* Only this case requires the base register compensation
19334 subtract. */
19336 {
19337 current_stub_contents =
19339 create_instruction_sub
19341 }
19343 /* B initial_insn_addr+4. */
19344 current_stub_contents =
19346 create_instruction_branch_absolute
19348 }
19350 /* Fill the remaining of the stub with deterministic contents. */
19351 current_stub_contents =
19354 base_stub_contents +
19355 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE);
19356 }
19358 static void
19364 {
19368 stub_contents);
19372 stub_contents);
19376 stub_contents);
19377 }
19379 /* End of stm32l4xx work-around. */
19382 /* Do code byteswapping. Return FALSE afterwards so that the section is
19383 written out as normal. */
19385 static bool
19390 {
19397 bfd_vma ptr;
19398 bfd_vma end;
19400 bfd_byte tmp;
19406 /* If this section has not been allocated an _arm_elf_section_data
19407 structure then we cannot record anything. */
19417 {
19422 {
19426 {
19428 {
19429 bfd_vma branch_to_veneer;
19430 /* Original condition code of instruction, plus bit mask for
19431 ARM B instruction. */
19435 /* The instruction is before the label. */
19438 /* Above offset included in -4 below. */
19452 }
19456 {
19457 bfd_vma branch_from_veneer;
19460 /* Take size of veneer into account. */
19469 /* Original instruction. */
19476 /* Branch back to insn after original insn. */
19482 }
19487 }
19488 }
19489 }
19492 {
19496 {
19500 {
19502 {
19504 bfd_vma branch_to_veneer =
19509 {
19510 bfd_vma out_of_range =
19516 _bfd_error_handler
19518 "cannot create STM32L4XX veneer; "
19521 output_bfd,
19525 }
19527 insn = create_instruction_branch_absolute
19530 /* The instruction is before the label. */
19535 }
19539 {
19545 veneer_r = veneer
19550 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE >
19551 STM32L4XX_ERRATUM_LDM_VENEER_SIZE ?
19552 STM32L4XX_ERRATUM_VLDM_VENEER_SIZE :
19555 {
19559 }
19561 /* Original instruction. */
19564 stm32l4xx_create_replacing_stub
19566 }
19571 }
19572 }
19573 }
19576 {
19577 arm_unwind_table_edit *edit_node
19579 /* Now, sec->size is the size of the section we will write. The original
19580 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
19581 markers) was sec->rawsize. (This isn't the case if we perform no
19582 edits, then rawsize will be zero and we should use size). */
19591 {
19593 {
19597 {
19600 out_index++;
19601 in_index++;
19602 }
19606 {
19608 {
19610 in_index++;
19615 {
19623 /* Note: this is meant to be equivalent to an
19624 R_ARM_PREL31 relocation. These synthetic
19625 EXIDX_CANTUNWIND markers are not relocated by the
19626 usual BFD method. */
19630 {
19631 /* Here relocation for new EXIDX_CANTUNWIND is
19632 created, so there is no need to
19633 adjust offset by hand. */
19636 }
19638 /* First address we can't unwind. */
19642 /* Code for EXIDX_CANTUNWIND. */
19646 out_index++;
19648 }
19650 }
19653 }
19654 }
19655 else
19656 {
19657 /* No more edits, copy remaining entries verbatim. */
19660 out_index++;
19661 in_index++;
19662 }
19663 }
19667 edited_contents,
19671 }
19673 /* Fix code to point to Cortex-A8 erratum stubs. */
19675 {
19683 }
19689 {
19694 {
19697 else
19701 {
19703 /* Byte swap code words. */
19705 {
19713 }
19717 /* Byte swap code halfwords. */
19719 {
19724 }
19728 /* Leave data alone. */
19730 }
19732 }
19733 }
19741 }
19743 /* Mangle thumb function symbols as we read them in. */
19745 static bool
19750 {
19755 /* New EABI objects mark thumb function symbols by setting the low bit of
19756 the address. */
19759 {
19761 {
19764 ST_BRANCH_TO_THUMB);
19765 }
19766 else
19768 }
19770 {
19773 }
19776 else
19780 }
19783 /* Mangle thumb function symbols as we write them out. */
19785 static void
19790 {
19791 Elf_Internal_Sym newsym;
19793 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
19794 of the address set, as per the new EABI. We do this unconditionally
19795 because objcopy does not set the elf header flags until after
19796 it writes out the symbol table. */
19798 {
19803 {
19804 /* Do this only for defined symbols. At link type, the static
19805 linker will simulate the work of dynamic linker of resolving
19806 symbols and will carry over the thumbness of found symbols to
19807 the output symbol table. It's not clear how it happens, but
19808 the thumbness of undefined symbols can well be different at
19809 runtime, and writing '1' for them will be confusing for users
19810 and possibly for dynamic linker itself.
19811 */
19813 }
19816 }
19818 }
19820 /* Add the PT_ARM_EXIDX program header. */
19822 static bool
19825 {
19831 {
19832 /* If there is already a PT_ARM_EXIDX header, then we do not
19833 want to add another one. This situation arises when running
19834 "strip"; the input binary already has the header. */
19839 {
19850 }
19851 }
19854 }
19856 /* We may add a PT_ARM_EXIDX program header. */
19858 static int
19861 {
19867 else
19869 }
19871 /* Hook called by the linker routine which adds symbols from an object
19872 file. */
19874 static bool
19878 {
19888 }
19890 /* We use this to override swap_symbol_in and swap_symbol_out. */
19892 {
19905 bfd_elf32_write_out_phdrs,
19906 bfd_elf32_write_shdrs_and_ehdr,
19907 bfd_elf32_checksum_contents,
19908 bfd_elf32_write_relocs,
19909 elf32_arm_swap_symbol_in,
19910 elf32_arm_swap_symbol_out,
19911 bfd_elf32_slurp_reloc_table,
19912 bfd_elf32_slurp_symbol_table,
19913 bfd_elf32_swap_dyn_in,
19914 bfd_elf32_swap_dyn_out,
19915 bfd_elf32_swap_reloc_in,
19916 bfd_elf32_swap_reloc_out,
19917 bfd_elf32_swap_reloca_in,
19918 bfd_elf32_swap_reloca_out
19919 };
19921 static bfd_vma
19923 {
19924 /* V7 BE8 code is always little endian. */
19929 }
19931 static bfd_vma
19933 {
19934 /* V7 BE8 code is always little endian. */
19939 }
19941 /* Return size of plt0 entry starting at ADDR
19942 or (bfd_vma) -1 if size can not be determined. */
19944 static bfd_vma
19946 bfd_size_type data_size)
19947 {
19948 bfd_vma first_word;
19949 bfd_vma plt0_size;
19960 else
19961 /* We don't yet handle this PLT format. */
19965 }
19967 /* Return size of plt entry starting at offset OFFSET
19968 of plt section located at address START
19969 or (bfd_vma) -1 if size can not be determined. */
19971 static bfd_vma
19973 bfd_size_type data_size)
19974 {
19975 bfd_vma first_insn;
19978 /* PLT entry size if fixed on Thumb-only platforms. */
19982 /* Respect Thumb stub if necessary. */
19986 {
19988 }
19990 /* Strip immediate from first add. */
19995 #ifdef FOUR_WORD_PLT
19998 #else
20003 #endif
20004 else
20005 /* We don't yet handle this PLT format. */
20009 }
20011 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
20013 static long
20020 {
20029 bfd_vma offset;
20064 {
20068 }
20073 {
20076 }
20082 {
20090 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
20091 we are defining a symbol, ensure one of them is set. */
20103 {
20110 ;
20114 }
20119 }
20123 }
20125 static bool
20127 {
20131 }
20133 static flagword
20135 {
20140 }
20142 static unsigned int
20144 {
20149 }
20151 /* Called to set the sh_flags, sh_link and sh_info fields of OSECTION which
20152 has a type >= SHT_LOOS. Returns TRUE if these fields were initialised
20153 FALSE otherwise. ISECTION is the best guess matching section from the
20154 input bfd IBFD, but it might be NULL. */
20156 static bool
20161 {
20163 {
20165 {
20173 /* The sh_link field must be set to the text section associated with
20174 this index section. Unfortunately the ARM EHABI does not specify
20175 exactly how to determine this association. Our caller does try
20176 to match up OSECTION with its corresponding input section however
20177 so that is a good first guess. */
20188 )
20189 {
20194 }
20197 {
20198 /* Failing that we have to find a matching section ourselves. If
20199 we had the output section name available we could compare that
20200 with input section names. Unfortunately we don't. So instead
20201 we use a simple heuristic and look for the nearest executable
20202 section before this one. */
20214 }
20217 {
20219 /* If the text section was part of a group
20220 then the index section should be too. */
20224 }
20225 }
20237 }
20240 }
20242 /* Returns TRUE if NAME is an ARM mapping symbol.
20243 Traditionally the symbols $a, $d and $t have been used.
20244 The ARM ELF standard also defines $x (for A64 code). It also allows a
20245 period initiated suffix to be added to the symbol: "$[adtx]\.[:sym_char]+".
20246 Other tools might also produce $b (Thumb BL), $f, $p, $m and $v, but we do
20247 not support them here. $t.x indicates the start of ThumbEE instructions. */
20249 static bool
20251 {
20254 the mapping symbols could have acquired a prefix.
20255 We do not support this here, since such symbols no
20256 longer conform to the ARM ELF ABI. */
20259 /* FIXME: Strictly speaking the symbol is only a valid mapping symbol if
20260 any characters that follow the period are legal characters for the body
20261 of a symbol's name. For now we just assume that this is the case. */
20262 }
20264 /* Make sure that mapping symbols in object files are not removed via the
20265 "strip --strip-unneeded" tool. These symbols are needed in order to
20266 correctly generate interworking veneers, and for byte swapping code
20267 regions. Once an object file has been linked, it is safe to remove the
20268 symbols as they will no longer be needed. */
20270 static void
20272 {
20277 }
20279 #undef elf_backend_copy_special_section_fields
20280 #define elf_backend_copy_special_section_fields elf32_arm_copy_special_section_fields
20282 #define ELF_ARCH bfd_arch_arm
20283 #define ELF_TARGET_ID ARM_ELF_DATA
20284 #define ELF_MACHINE_CODE EM_ARM
20285 #define ELF_MAXPAGESIZE 0x1000
20286 #define ELF_COMMONPAGESIZE 0x1000
20288 #define bfd_elf32_mkobject elf32_arm_mkobject
20290 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
20291 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
20292 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
20293 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
20294 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
20295 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
20296 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
20297 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
20298 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
20299 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
20300 #define bfd_elf32_bfd_final_link elf32_arm_final_link
20301 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
20303 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
20304 #define elf_backend_maybe_function_sym elf32_arm_maybe_function_sym
20305 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
20306 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
20307 #define elf_backend_check_relocs elf32_arm_check_relocs
20308 #define elf_backend_update_relocs elf32_arm_update_relocs
20309 #define elf_backend_relocate_section elf32_arm_relocate_section
20310 #define elf_backend_write_section elf32_arm_write_section
20311 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
20312 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
20313 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
20314 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
20315 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
20316 #define elf_backend_always_size_sections elf32_arm_always_size_sections
20317 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
20318 #define elf_backend_init_file_header elf32_arm_init_file_header
20319 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
20320 #define elf_backend_object_p elf32_arm_object_p
20321 #define elf_backend_fake_sections elf32_arm_fake_sections
20322 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
20323 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20324 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
20325 #define elf_backend_size_info elf32_arm_size_info
20326 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20327 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
20328 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
20329 #define elf_backend_filter_implib_symbols elf32_arm_filter_implib_symbols
20330 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
20331 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
20332 #define elf_backend_count_additional_relocs elf32_arm_count_additional_relocs
20333 #define elf_backend_symbol_processing elf32_arm_backend_symbol_processing
20335 #define elf_backend_can_refcount 1
20336 #define elf_backend_can_gc_sections 1
20337 #define elf_backend_plt_readonly 1
20338 #define elf_backend_want_got_plt 1
20339 #define elf_backend_want_plt_sym 0
20340 #define elf_backend_want_dynrelro 1
20341 #define elf_backend_may_use_rel_p 1
20342 #define elf_backend_may_use_rela_p 0
20343 #define elf_backend_default_use_rela_p 0
20344 #define elf_backend_dtrel_excludes_plt 1
20346 #define elf_backend_got_header_size 12
20347 #define elf_backend_extern_protected_data 0
20349 #undef elf_backend_obj_attrs_vendor
20351 #undef elf_backend_obj_attrs_section
20353 #undef elf_backend_obj_attrs_arg_type
20354 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
20355 #undef elf_backend_obj_attrs_section_type
20356 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
20357 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
20358 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
20360 #undef elf_backend_section_flags
20361 #define elf_backend_section_flags elf32_arm_section_flags
20362 #undef elf_backend_lookup_section_flags_hook
20363 #define elf_backend_lookup_section_flags_hook elf32_arm_lookup_section_flags
20365 #define elf_backend_linux_prpsinfo32_ugid16 true
20369 /* Native Client targets. */
20371 #undef TARGET_LITTLE_SYM
20372 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
20373 #undef TARGET_LITTLE_NAME
20375 #undef TARGET_BIG_SYM
20376 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
20377 #undef TARGET_BIG_NAME
20380 /* Like elf32_arm_link_hash_table_create -- but overrides
20381 appropriately for NaCl. */
20385 {
20390 {
20396 }
20398 }
20400 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
20401 really need to use elf32_arm_modify_segment_map. But we do it
20402 anyway just to reduce gratuitous differences with the stock ARM backend. */
20404 static bool
20406 {
20409 }
20411 static bool
20413 {
20416 }
20418 static bfd_vma
20421 {
20425 }
20427 #undef elf32_bed
20428 #define elf32_bed elf32_arm_nacl_bed
20429 #undef bfd_elf32_bfd_link_hash_table_create
20430 #define bfd_elf32_bfd_link_hash_table_create \
20431 elf32_arm_nacl_link_hash_table_create
20432 #undef elf_backend_plt_alignment
20433 #define elf_backend_plt_alignment 4
20434 #undef elf_backend_modify_segment_map
20435 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
20436 #undef elf_backend_modify_headers
20437 #define elf_backend_modify_headers nacl_modify_headers
20438 #undef elf_backend_final_write_processing
20439 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
20440 #undef bfd_elf32_get_synthetic_symtab
20441 #undef elf_backend_plt_sym_val
20442 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
20443 #undef elf_backend_copy_special_section_fields
20445 #undef ELF_MINPAGESIZE
20446 #undef ELF_COMMONPAGESIZE
20448 #undef ELF_TARGET_OS
20449 #define ELF_TARGET_OS is_nacl
20453 /* Reset to defaults. */
20454 #undef elf_backend_plt_alignment
20455 #undef elf_backend_modify_segment_map
20456 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
20457 #undef elf_backend_modify_headers
20458 #undef elf_backend_final_write_processing
20459 #define elf_backend_final_write_processing elf32_arm_final_write_processing
20460 #undef ELF_MINPAGESIZE
20461 #undef ELF_COMMONPAGESIZE
20462 #define ELF_COMMONPAGESIZE 0x1000
20465 /* FDPIC Targets. */
20467 #undef TARGET_LITTLE_SYM
20468 #define TARGET_LITTLE_SYM arm_elf32_fdpic_le_vec
20469 #undef TARGET_LITTLE_NAME
20471 #undef TARGET_BIG_SYM
20472 #define TARGET_BIG_SYM arm_elf32_fdpic_be_vec
20473 #undef TARGET_BIG_NAME
20475 #undef elf_match_priority
20476 #define elf_match_priority 128
20477 #undef ELF_OSABI
20478 #define ELF_OSABI ELFOSABI_ARM_FDPIC
20480 /* Like elf32_arm_link_hash_table_create -- but overrides
20481 appropriately for FDPIC. */
20485 {
20490 {
20494 }
20496 }
20498 /* We need dynamic symbols for every section, since segments can
20499 relocate independently. */
20500 static bool
20503 ATTRIBUTE_UNUSED,
20505 {
20507 {
20510 /* If sh_type is yet undecided, assume it could be
20511 SHT_PROGBITS/SHT_NOBITS. */
20515 /* There shouldn't be section relative relocations
20516 against any other section. */
20519 }
20520 }
20522 #undef elf32_bed
20523 #define elf32_bed elf32_arm_fdpic_bed
20525 #undef bfd_elf32_bfd_link_hash_table_create
20526 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_fdpic_link_hash_table_create
20528 #undef elf_backend_omit_section_dynsym
20529 #define elf_backend_omit_section_dynsym elf32_arm_fdpic_omit_section_dynsym
20531 #undef ELF_TARGET_OS
20535 #undef elf_match_priority
20536 #undef ELF_OSABI
20537 #undef elf_backend_omit_section_dynsym
20539 /* VxWorks Targets. */
20541 #undef TARGET_LITTLE_SYM
20542 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
20543 #undef TARGET_LITTLE_NAME
20545 #undef TARGET_BIG_SYM
20546 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
20547 #undef TARGET_BIG_NAME
20550 /* Like elf32_arm_link_hash_table_create -- but overrides
20551 appropriately for VxWorks. */
20555 {
20560 {
20564 }
20566 }
20568 static bool
20570 {
20573 }
20575 #undef elf32_bed
20576 #define elf32_bed elf32_arm_vxworks_bed
20578 #undef bfd_elf32_bfd_link_hash_table_create
20579 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
20580 #undef elf_backend_final_write_processing
20581 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
20582 #undef elf_backend_emit_relocs
20583 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
20585 #undef elf_backend_may_use_rel_p
20586 #define elf_backend_may_use_rel_p 0
20587 #undef elf_backend_may_use_rela_p
20588 #define elf_backend_may_use_rela_p 1
20589 #undef elf_backend_default_use_rela_p
20590 #define elf_backend_default_use_rela_p 1
20591 #undef elf_backend_want_plt_sym
20592 #define elf_backend_want_plt_sym 1
20593 #undef ELF_MAXPAGESIZE
20594 #define ELF_MAXPAGESIZE 0x1000
20595 #undef ELF_TARGET_OS
20596 #define ELF_TARGET_OS is_vxworks
20601 /* Merge backend specific data from an object file to the output
20602 object file when linking. */
20604 static bool
20606 {
20608 flagword out_flags;
20609 flagword in_flags;
20613 /* Check if we have the same endianness. */
20623 /* The input BFD must have had its flags initialised. */
20624 /* The following seems bogus to me -- The flags are initialized in
20625 the assembler but I don't think an elf_flags_init field is
20626 written into the object. */
20627 /* BFD_ASSERT (elf_flags_init (ibfd)); */
20632 /* In theory there is no reason why we couldn't handle this. However
20633 in practice it isn't even close to working and there is no real
20634 reason to want it. */
20638 {
20640 ibfd);
20642 }
20645 {
20646 /* If the input has no flags set, then do not set the output flags.
20647 This will allow future bfds to determine the desired output flags.
20648 If no input bfds have any flags set, then neither will the output bfd.
20650 Note - we used to restrict this test to when the input architecture
20651 variant was the default variant, but this does not allow for
20652 linker scripts which override the default. See PR 28910 for an
20653 example. */
20665 }
20667 /* Determine what should happen if the input ARM architecture
20668 does not match the output ARM architecture. */
20672 /* Identical flags must be compatible. */
20676 /* Check to see if the input BFD actually contains any sections. If
20677 not, its flags may not have been initialised either, but it
20678 cannot actually cause any incompatiblity. Do not short-circuit
20679 dynamic objects; their section list may be emptied by
20680 elf_link_add_object_symbols.
20682 Also check to see if there are no code sections in the input.
20683 In this case there is no need to check for code specific flags.
20684 XXX - do we need to worry about floating-point format compatability
20685 in data sections ? */
20687 {
20692 {
20693 /* Ignore synthetic glue sections. */
20696 {
20704 }
20705 }
20709 }
20711 /* Complain about various flag mismatches. */
20714 {
20715 _bfd_error_handler
20720 }
20722 /* Not sure what needs to be checked for EABI versions >= 1. */
20723 /* VxWorks libraries do not use these flags. */
20727 {
20729 {
20730 _bfd_error_handler
20735 }
20738 {
20740 _bfd_error_handler
20741 (_("error: %pB passes floats in float registers, whereas %pB passes them in integer registers"),
20743 else
20744 _bfd_error_handler
20745 (_("error: %pB passes floats in integer registers, whereas %pB passes them in float registers"),
20749 }
20752 {
20754 _bfd_error_handler
20757 else
20758 _bfd_error_handler
20763 }
20766 {
20768 _bfd_error_handler
20771 else
20772 _bfd_error_handler
20777 }
20779 #ifdef EF_ARM_SOFT_FLOAT
20781 {
20782 /* We can allow interworking between code that is VFP format
20783 layout, and uses either soft float or integer regs for
20784 passing floating point arguments and results. We already
20785 know that the APCS_FLOAT flags match; similarly for VFP
20786 flags. */
20789 {
20791 _bfd_error_handler
20794 else
20795 _bfd_error_handler
20800 }
20801 }
20802 #endif
20804 /* Interworking mismatch is only a warning. */
20806 {
20808 {
20809 _bfd_error_handler
20812 }
20813 else
20814 {
20815 _bfd_error_handler
20818 }
20819 }
20820 }
20823 }