gdb/aarch64-linux-nat.c

   1 /* Native-dependent code for GNU/Linux AArch64.
   2
   3    Copyright (C) 2011-2024 Free Software Foundation, Inc.
   4    Contributed by ARM Ltd.
   5
   6    This file is part of GDB.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21
  22 #include "inferior.h"
  23 #include "gdbcore.h"
  24 #include "regcache.h"
  25 #include "linux-nat.h"
  26 #include "target-descriptions.h"
  27 #include "auxv.h"
  28 #include "gdbcmd.h"
  29 #include "aarch64-nat.h"
  30 #include "aarch64-tdep.h"
  31 #include "aarch64-linux-tdep.h"
  32 #include "aarch32-linux-nat.h"
  33 #include "aarch32-tdep.h"
  34 #include "arch/arm.h"
  35 #include "nat/aarch64-linux.h"
  36 #include "nat/aarch64-linux-hw-point.h"
  37 #include "nat/aarch64-scalable-linux-ptrace.h"
  38
  39 #include "elf/external.h"
  40 #include "elf/common.h"
  41
  42 #include "nat/gdb_ptrace.h"
  43 #include <sys/utsname.h>
  44 #include <asm/ptrace.h>
  45
  46 #include "gregset.h"
  47 #include "linux-tdep.h"
  48 #include "arm-tdep.h"
  49
  50 /* Defines ps_err_e, struct ps_prochandle.  */
  51 #include "gdb_proc_service.h"
  52 #include "arch-utils.h"
  53
  54 #include "arch/aarch64-mte-linux.h"
  55
  56 #include "nat/aarch64-mte-linux-ptrace.h"
  57 #include "arch/aarch64-scalable-linux.h"
  58
  59 #include <string.h>
  60
  61 #ifndef TRAP_HWBKPT
  62 #define TRAP_HWBKPT 0x0004
  63 #endif
  64
  65 class aarch64_linux_nat_target final
  66   : public aarch64_nat_target<linux_nat_target>
  67 {
  68 public:
  69   /* Add our register access methods.  */
  70   void fetch_registers (struct regcache *, int) override;
  71   void store_registers (struct regcache *, int) override;
  72
  73   const struct target_desc *read_description () override;
  74
  75   /* Add our hardware breakpoint and watchpoint implementation.  */
  76   bool stopped_by_watchpoint () override;
  77   bool stopped_data_address (CORE_ADDR *) override;
  78
  79   int can_do_single_step () override;
  80
  81   /* Override the GNU/Linux inferior startup hook.  */
  82   void post_startup_inferior (ptid_t) override;
  83
  84   /* Override the GNU/Linux post attach hook.  */
  85   void post_attach (int pid) override;
  86
  87   /* These three defer to common nat/ code.  */
  88   void low_new_thread (struct lwp_info *lp) override
  89   { aarch64_linux_new_thread (lp); }
  90   void low_delete_thread (struct arch_lwp_info *lp) override
  91   { aarch64_linux_delete_thread (lp); }
  92   void low_prepare_to_resume (struct lwp_info *lp) override
  93   { aarch64_linux_prepare_to_resume (lp); }
  94
  95   void low_new_fork (struct lwp_info *parent, pid_t child_pid) override;
  96   void low_forget_process (pid_t pid) override;
  97
  98   /* Add our siginfo layout converter.  */
  99   bool low_siginfo_fixup (siginfo_t *ptrace, gdb_byte *inf, int direction)
 100     override;
 101
 102   struct gdbarch *thread_architecture (ptid_t) override;
 103
 104   bool supports_memory_tagging () override;
 105
 106   /* Read memory allocation tags from memory via PTRACE.  */
 107   bool fetch_memtags (CORE_ADDR address, size_t len,
 108                       gdb::byte_vector &tags, int type) override;
 109
 110   /* Write allocation tags to memory via PTRACE.  */
 111   bool store_memtags (CORE_ADDR address, size_t len,
 112                       const gdb::byte_vector &tags, int type) override;
 113 };
 114
 115 static aarch64_linux_nat_target the_aarch64_linux_nat_target;
 116
 117 /* Called whenever GDB is no longer debugging process PID.  It deletes
 118    data structures that keep track of debug register state.  */
 119
 120 void
 121 aarch64_linux_nat_target::low_forget_process (pid_t pid)
 122 {
 123   aarch64_remove_debug_reg_state (pid);
 124 }
 125
 126 /* Fill GDB's register array with the general-purpose register values
 127    from the current thread.  */
 128
 129 static void
 130 fetch_gregs_from_thread (struct regcache *regcache)
 131 {
 132   int ret, tid;
 133   struct gdbarch *gdbarch = regcache->arch ();
 134   elf_gregset_t regs;
 135   struct iovec iovec;
 136
 137   /* Make sure REGS can hold all registers contents on both aarch64
 138      and arm.  */
 139   static_assert (sizeof (regs) >= 18 * 4);
 140
 141   tid = regcache->ptid ().lwp ();
 142
 143   iovec.iov_base = &regs;
 144   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 145     iovec.iov_len = 18 * 4;
 146   else
 147     iovec.iov_len = sizeof (regs);
 148
 149   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
 150   if (ret < 0)
 151     perror_with_name (_("Unable to fetch general registers"));
 152
 153   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 154     aarch32_gp_regcache_supply (regcache, (uint32_t *) regs, 1);
 155   else
 156     {
 157       int regno;
 158
 159       for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
 160         regcache->raw_supply (regno, &regs[regno - AARCH64_X0_REGNUM]);
 161     }
 162 }
 163
 164 /* Store to the current thread the valid general-purpose register
 165    values in the GDB's register array.  */
 166
 167 static void
 168 store_gregs_to_thread (const struct regcache *regcache)
 169 {
 170   int ret, tid;
 171   elf_gregset_t regs;
 172   struct iovec iovec;
 173   struct gdbarch *gdbarch = regcache->arch ();
 174
 175   /* Make sure REGS can hold all registers contents on both aarch64
 176      and arm.  */
 177   static_assert (sizeof (regs) >= 18 * 4);
 178   tid = regcache->ptid ().lwp ();
 179
 180   iovec.iov_base = &regs;
 181   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 182     iovec.iov_len = 18 * 4;
 183   else
 184     iovec.iov_len = sizeof (regs);
 185
 186   ret = ptrace (PTRACE_GETREGSET, tid, NT_PRSTATUS, &iovec);
 187   if (ret < 0)
 188     perror_with_name (_("Unable to fetch general registers"));
 189
 190   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 191     aarch32_gp_regcache_collect (regcache, (uint32_t *) regs, 1);
 192   else
 193     {
 194       int regno;
 195
 196       for (regno = AARCH64_X0_REGNUM; regno <= AARCH64_CPSR_REGNUM; regno++)
 197         if (REG_VALID == regcache->get_register_status (regno))
 198           regcache->raw_collect (regno, &regs[regno - AARCH64_X0_REGNUM]);
 199     }
 200
 201   ret = ptrace (PTRACE_SETREGSET, tid, NT_PRSTATUS, &iovec);
 202   if (ret < 0)
 203     perror_with_name (_("Unable to store general registers"));
 204 }
 205
 206 /* Fill GDB's register array with the fp/simd register values
 207    from the current thread.  */
 208
 209 static void
 210 fetch_fpregs_from_thread (struct regcache *regcache)
 211 {
 212   int ret, tid;
 213   elf_fpregset_t regs;
 214   struct iovec iovec;
 215   struct gdbarch *gdbarch = regcache->arch ();
 216
 217   /* Make sure REGS can hold all VFP registers contents on both aarch64
 218      and arm.  */
 219   static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
 220
 221   tid = regcache->ptid ().lwp ();
 222
 223   iovec.iov_base = &regs;
 224
 225   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 226     {
 227       iovec.iov_len = ARM_VFP3_REGS_SIZE;
 228
 229       ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 230       if (ret < 0)
 231         perror_with_name (_("Unable to fetch VFP registers"));
 232
 233       aarch32_vfp_regcache_supply (regcache, (gdb_byte *) &regs, 32);
 234     }
 235   else
 236     {
 237       int regno;
 238
 239       iovec.iov_len = sizeof (regs);
 240
 241       ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
 242       if (ret < 0)
 243         perror_with_name (_("Unable to fetch vFP/SIMD registers"));
 244
 245       for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
 246         regcache->raw_supply (regno, &regs.vregs[regno - AARCH64_V0_REGNUM]);
 247
 248       regcache->raw_supply (AARCH64_FPSR_REGNUM, &regs.fpsr);
 249       regcache->raw_supply (AARCH64_FPCR_REGNUM, &regs.fpcr);
 250     }
 251 }
 252
 253 /* Store to the current thread the valid fp/simd register
 254    values in the GDB's register array.  */
 255
 256 static void
 257 store_fpregs_to_thread (const struct regcache *regcache)
 258 {
 259   int ret, tid;
 260   elf_fpregset_t regs;
 261   struct iovec iovec;
 262   struct gdbarch *gdbarch = regcache->arch ();
 263
 264   /* Make sure REGS can hold all VFP registers contents on both aarch64
 265      and arm.  */
 266   static_assert (sizeof regs >= ARM_VFP3_REGS_SIZE);
 267   tid = regcache->ptid ().lwp ();
 268
 269   iovec.iov_base = &regs;
 270
 271   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 272     {
 273       iovec.iov_len = ARM_VFP3_REGS_SIZE;
 274
 275       ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 276       if (ret < 0)
 277         perror_with_name (_("Unable to fetch VFP registers"));
 278
 279       aarch32_vfp_regcache_collect (regcache, (gdb_byte *) &regs, 32);
 280     }
 281   else
 282     {
 283       int regno;
 284
 285       iovec.iov_len = sizeof (regs);
 286
 287       ret = ptrace (PTRACE_GETREGSET, tid, NT_FPREGSET, &iovec);
 288       if (ret < 0)
 289         perror_with_name (_("Unable to fetch FP/SIMD registers"));
 290
 291       for (regno = AARCH64_V0_REGNUM; regno <= AARCH64_V31_REGNUM; regno++)
 292         if (REG_VALID == regcache->get_register_status (regno))
 293           regcache->raw_collect
 294             (regno, (char *) &regs.vregs[regno - AARCH64_V0_REGNUM]);
 295
 296       if (REG_VALID == regcache->get_register_status (AARCH64_FPSR_REGNUM))
 297         regcache->raw_collect (AARCH64_FPSR_REGNUM, (char *) &regs.fpsr);
 298       if (REG_VALID == regcache->get_register_status (AARCH64_FPCR_REGNUM))
 299         regcache->raw_collect (AARCH64_FPCR_REGNUM, (char *) &regs.fpcr);
 300     }
 301
 302   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 303     {
 304       ret = ptrace (PTRACE_SETREGSET, tid, NT_ARM_VFP, &iovec);
 305       if (ret < 0)
 306         perror_with_name (_("Unable to store VFP registers"));
 307     }
 308   else
 309     {
 310       ret = ptrace (PTRACE_SETREGSET, tid, NT_FPREGSET, &iovec);
 311       if (ret < 0)
 312         perror_with_name (_("Unable to store FP/SIMD registers"));
 313     }
 314 }
 315
 316 /* Fill GDB's REGCACHE with the valid SVE register values from the thread
 317    associated with REGCACHE.
 318
 319    This function handles reading data from SVE or SSVE states, depending
 320    on which state is active at the moment.  */
 321
 322 static void
 323 fetch_sveregs_from_thread (struct regcache *regcache)
 324 {
 325   /* Fetch SVE state from the thread and copy it into the register cache.  */
 326   aarch64_sve_regs_copy_to_reg_buf (regcache->ptid ().lwp (), regcache);
 327 }
 328
 329 /* Store the valid SVE register values from GDB's REGCACHE to the thread
 330    associated with REGCACHE.
 331
 332    This function handles writing data to SVE or SSVE states, depending
 333    on which state is active at the moment.  */
 334
 335 static void
 336 store_sveregs_to_thread (struct regcache *regcache)
 337 {
 338   /* Fetch SVE state from the register cache and update the thread TID with
 339      it.  */
 340   aarch64_sve_regs_copy_from_reg_buf (regcache->ptid ().lwp (), regcache);
 341 }
 342
 343 /* Fill GDB's REGCACHE with the ZA register set contents from the
 344    thread associated with REGCACHE.  If there is no active ZA register state,
 345    make the ZA register contents zero.  */
 346
 347 static void
 348 fetch_za_from_thread (struct regcache *regcache)
 349 {
 350   aarch64_gdbarch_tdep *tdep
 351     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 352
 353   /* Read ZA state from the thread to the register cache.  */
 354   aarch64_za_regs_copy_to_reg_buf (regcache->ptid ().lwp (),
 355                                    regcache,
 356                                    tdep->sme_za_regnum,
 357                                    tdep->sme_svg_regnum,
 358                                    tdep->sme_svcr_regnum);
 359 }
 360
 361 /* Store the NT_ARM_ZA register set contents from GDB's REGCACHE to the thread
 362    associated with REGCACHE.  */
 363
 364 static void
 365 store_za_to_thread (struct regcache *regcache)
 366 {
 367   aarch64_gdbarch_tdep *tdep
 368     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 369
 370   /* Write ZA state from the register cache to the thread.  */
 371   aarch64_za_regs_copy_from_reg_buf (regcache->ptid ().lwp (),
 372                                      regcache,
 373                                      tdep->sme_za_regnum,
 374                                      tdep->sme_svg_regnum,
 375                                      tdep->sme_svcr_regnum);
 376 }
 377
 378 /* Fill GDB's REGCACHE with the ZT register set contents from the
 379    thread associated with REGCACHE.  If there is no active ZA register state,
 380    make the ZT register contents zero.  */
 381
 382 static void
 383 fetch_zt_from_thread (struct regcache *regcache)
 384 {
 385   aarch64_gdbarch_tdep *tdep
 386     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 387
 388   /* Read ZT state from the thread to the register cache.  */
 389   aarch64_zt_regs_copy_to_reg_buf (regcache->ptid ().lwp (),
 390                                    regcache,
 391                                    tdep->sme2_zt0_regnum);
 392 }
 393
 394 /* Store the NT_ARM_ZT register set contents from GDB's REGCACHE to the
 395    thread associated with REGCACHE.  */
 396
 397 static void
 398 store_zt_to_thread (struct regcache *regcache)
 399 {
 400   aarch64_gdbarch_tdep *tdep
 401     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 402
 403   /* Write ZT state from the register cache to the thread.  */
 404   aarch64_zt_regs_copy_from_reg_buf (regcache->ptid ().lwp (),
 405                                      regcache,
 406                                      tdep->sme2_zt0_regnum);
 407 }
 408
 409 /* Fill GDB's register array with the pointer authentication mask values from
 410    the current thread.  */
 411
 412 static void
 413 fetch_pauth_masks_from_thread (struct regcache *regcache)
 414 {
 415   aarch64_gdbarch_tdep *tdep
 416     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 417   int ret;
 418   struct iovec iovec;
 419   uint64_t pauth_regset[2] = {0, 0};
 420   int tid = regcache->ptid ().lwp ();
 421
 422   iovec.iov_base = &pauth_regset;
 423   iovec.iov_len = sizeof (pauth_regset);
 424
 425   ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_PAC_MASK, &iovec);
 426   if (ret != 0)
 427     perror_with_name (_("unable to fetch pauth registers"));
 428
 429   regcache->raw_supply (AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base),
 430                         &pauth_regset[0]);
 431   regcache->raw_supply (AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base),
 432                         &pauth_regset[1]);
 433 }
 434
 435 /* Fill GDB's register array with the MTE register values from
 436    the current thread.  */
 437
 438 static void
 439 fetch_mteregs_from_thread (struct regcache *regcache)
 440 {
 441   aarch64_gdbarch_tdep *tdep
 442     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 443   int regno = tdep->mte_reg_base;
 444
 445   gdb_assert (regno != -1);
 446
 447   uint64_t tag_ctl = 0;
 448   struct iovec iovec;
 449
 450   iovec.iov_base = &tag_ctl;
 451   iovec.iov_len = sizeof (tag_ctl);
 452
 453   int tid = get_ptrace_pid (regcache->ptid ());
 454   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
 455       perror_with_name (_("unable to fetch MTE registers"));
 456
 457   regcache->raw_supply (regno, &tag_ctl);
 458 }
 459
 460 /* Store to the current thread the valid MTE register set in the GDB's
 461    register array.  */
 462
 463 static void
 464 store_mteregs_to_thread (struct regcache *regcache)
 465 {
 466   aarch64_gdbarch_tdep *tdep
 467     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 468   int regno = tdep->mte_reg_base;
 469
 470   gdb_assert (regno != -1);
 471
 472   uint64_t tag_ctl = 0;
 473
 474   if (REG_VALID != regcache->get_register_status (regno))
 475     return;
 476
 477   regcache->raw_collect (regno, (char *) &tag_ctl);
 478
 479   struct iovec iovec;
 480
 481   iovec.iov_base = &tag_ctl;
 482   iovec.iov_len = sizeof (tag_ctl);
 483
 484   int tid = get_ptrace_pid (regcache->ptid ());
 485   if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TAGGED_ADDR_CTRL, &iovec) != 0)
 486     perror_with_name (_("unable to store MTE registers"));
 487 }
 488
 489 /* Fill GDB's register array with the TLS register values from
 490    the current thread.  */
 491
 492 static void
 493 fetch_tlsregs_from_thread (struct regcache *regcache)
 494 {
 495   aarch64_gdbarch_tdep *tdep
 496     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 497   int regno = tdep->tls_regnum_base;
 498
 499   gdb_assert (regno != -1);
 500   gdb_assert (tdep->tls_register_count > 0);
 501
 502   uint64_t tpidrs[tdep->tls_register_count];
 503   memset(tpidrs, 0, sizeof(tpidrs));
 504
 505   struct iovec iovec;
 506   iovec.iov_base = tpidrs;
 507   iovec.iov_len = sizeof (tpidrs);
 508
 509   int tid = get_ptrace_pid (regcache->ptid ());
 510   if (ptrace (PTRACE_GETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
 511       perror_with_name (_("unable to fetch TLS registers"));
 512
 513   for (int i = 0; i < tdep->tls_register_count; i++)
 514     regcache->raw_supply (regno + i, &tpidrs[i]);
 515 }
 516
 517 /* Store to the current thread the valid TLS register set in GDB's
 518    register array.  */
 519
 520 static void
 521 store_tlsregs_to_thread (struct regcache *regcache)
 522 {
 523   aarch64_gdbarch_tdep *tdep
 524     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 525   int regno = tdep->tls_regnum_base;
 526
 527   gdb_assert (regno != -1);
 528   gdb_assert (tdep->tls_register_count > 0);
 529
 530   uint64_t tpidrs[tdep->tls_register_count];
 531   memset(tpidrs, 0, sizeof(tpidrs));
 532
 533   for (int i = 0; i < tdep->tls_register_count; i++)
 534     {
 535       if (REG_VALID != regcache->get_register_status (regno + i))
 536         continue;
 537
 538       regcache->raw_collect (regno + i, (char *) &tpidrs[i]);
 539     }
 540
 541   struct iovec iovec;
 542   iovec.iov_base = &tpidrs;
 543   iovec.iov_len = sizeof (tpidrs);
 544
 545   int tid = get_ptrace_pid (regcache->ptid ());
 546   if (ptrace (PTRACE_SETREGSET, tid, NT_ARM_TLS, &iovec) != 0)
 547     perror_with_name (_("unable to store TLS register"));
 548 }
 549
 550 /* The AArch64 version of the "fetch_registers" target_ops method.  Fetch
 551    REGNO from the target and place the result into REGCACHE.  */
 552
 553 static void
 554 aarch64_fetch_registers (struct regcache *regcache, int regno)
 555 {
 556   aarch64_gdbarch_tdep *tdep
 557     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 558
 559   /* Do we need to fetch all registers?  */
 560   if (regno == -1)
 561     {
 562       fetch_gregs_from_thread (regcache);
 563
 564       /* We attempt to fetch SVE registers if there is support for either
 565          SVE or SME (due to the SSVE state of SME).  */
 566       if (tdep->has_sve () || tdep->has_sme ())
 567         fetch_sveregs_from_thread (regcache);
 568       else
 569         fetch_fpregs_from_thread (regcache);
 570
 571       if (tdep->has_pauth ())
 572         fetch_pauth_masks_from_thread (regcache);
 573
 574       if (tdep->has_mte ())
 575         fetch_mteregs_from_thread (regcache);
 576
 577       if (tdep->has_tls ())
 578         fetch_tlsregs_from_thread (regcache);
 579
 580       if (tdep->has_sme ())
 581         fetch_za_from_thread (regcache);
 582
 583       if (tdep->has_sme2 ())
 584         fetch_zt_from_thread (regcache);
 585     }
 586   /* General purpose register?  */
 587   else if (regno < AARCH64_V0_REGNUM)
 588     fetch_gregs_from_thread (regcache);
 589   /* SVE register?  */
 590   else if ((tdep->has_sve () || tdep->has_sme ())
 591            && regno <= AARCH64_SVE_VG_REGNUM)
 592     fetch_sveregs_from_thread (regcache);
 593   /* FPSIMD register?  */
 594   else if (regno <= AARCH64_FPCR_REGNUM)
 595     fetch_fpregs_from_thread (regcache);
 596   /* PAuth register?  */
 597   else if (tdep->has_pauth ()
 598            && (regno == AARCH64_PAUTH_DMASK_REGNUM (tdep->pauth_reg_base)
 599                || regno == AARCH64_PAUTH_CMASK_REGNUM (tdep->pauth_reg_base)))
 600     fetch_pauth_masks_from_thread (regcache);
 601   /* SME register?  */
 602   else if (tdep->has_sme () && regno >= tdep->sme_reg_base
 603            && regno < tdep->sme_reg_base + 3)
 604     fetch_za_from_thread (regcache);
 605   /* SME2 register?  */
 606   else if (tdep->has_sme2 () && regno == tdep->sme2_zt0_regnum)
 607     fetch_zt_from_thread (regcache);
 608   /* MTE register?  */
 609   else if (tdep->has_mte ()
 610            && (regno == tdep->mte_reg_base))
 611     fetch_mteregs_from_thread (regcache);
 612   /* TLS register?  */
 613   else if (tdep->has_tls ()
 614            && regno >= tdep->tls_regnum_base
 615            && regno < tdep->tls_regnum_base + tdep->tls_register_count)
 616     fetch_tlsregs_from_thread (regcache);
 617 }
 618
 619 /* A version of the "fetch_registers" target_ops method used when running
 620    32-bit ARM code on an AArch64 target.  Fetch REGNO from the target and
 621    place the result into REGCACHE.  */
 622
 623 static void
 624 aarch32_fetch_registers (struct regcache *regcache, int regno)
 625 {
 626   arm_gdbarch_tdep *tdep
 627     = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ());
 628
 629   if (regno == -1)
 630     {
 631       fetch_gregs_from_thread (regcache);
 632       if (tdep->vfp_register_count > 0)
 633         fetch_fpregs_from_thread (regcache);
 634     }
 635   else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
 636     fetch_gregs_from_thread (regcache);
 637   else if (tdep->vfp_register_count > 0
 638            && regno >= ARM_D0_REGNUM
 639            && (regno < ARM_D0_REGNUM + tdep->vfp_register_count
 640                || regno == ARM_FPSCR_REGNUM))
 641     fetch_fpregs_from_thread (regcache);
 642 }
 643
 644 /* Implement the "fetch_registers" target_ops method.  */
 645
 646 void
 647 aarch64_linux_nat_target::fetch_registers (struct regcache *regcache,
 648                                            int regno)
 649 {
 650   if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
 651     aarch32_fetch_registers (regcache, regno);
 652   else
 653     aarch64_fetch_registers (regcache, regno);
 654 }
 655
 656 /* The AArch64 version of the "store_registers" target_ops method.  Copy
 657    the value of register REGNO from REGCACHE into the the target.  */
 658
 659 static void
 660 aarch64_store_registers (struct regcache *regcache, int regno)
 661 {
 662   aarch64_gdbarch_tdep *tdep
 663     = gdbarch_tdep<aarch64_gdbarch_tdep> (regcache->arch ());
 664
 665   /* Do we need to store all registers?  */
 666   if (regno == -1)
 667     {
 668       store_gregs_to_thread (regcache);
 669
 670       /* We attempt to store SVE registers if there is support for either
 671          SVE or SME (due to the SSVE state of SME).  */
 672       if (tdep->has_sve () || tdep->has_sme ())
 673         store_sveregs_to_thread (regcache);
 674       else
 675         store_fpregs_to_thread (regcache);
 676
 677       if (tdep->has_mte ())
 678         store_mteregs_to_thread (regcache);
 679
 680       if (tdep->has_tls ())
 681         store_tlsregs_to_thread (regcache);
 682
 683       if (tdep->has_sme ())
 684         store_za_to_thread (regcache);
 685
 686       if (tdep->has_sme2 ())
 687         store_zt_to_thread (regcache);
 688     }
 689   /* General purpose register?  */
 690   else if (regno < AARCH64_V0_REGNUM)
 691     store_gregs_to_thread (regcache);
 692   /* SVE register?  */
 693   else if ((tdep->has_sve () || tdep->has_sme ())
 694            && regno <= AARCH64_SVE_VG_REGNUM)
 695     store_sveregs_to_thread (regcache);
 696   /* FPSIMD register?  */
 697   else if (regno <= AARCH64_FPCR_REGNUM)
 698     store_fpregs_to_thread (regcache);
 699   /* SME register?  */
 700   else if (tdep->has_sme () && regno >= tdep->sme_reg_base
 701            && regno < tdep->sme_reg_base + 3)
 702     store_za_to_thread (regcache);
 703   else if (tdep->has_sme2 () && regno == tdep->sme2_zt0_regnum)
 704     store_zt_to_thread (regcache);
 705   /* MTE register?  */
 706   else if (tdep->has_mte ()
 707            && (regno == tdep->mte_reg_base))
 708     store_mteregs_to_thread (regcache);
 709   /* TLS register?  */
 710   else if (tdep->has_tls ()
 711            && regno >= tdep->tls_regnum_base
 712            && regno < tdep->tls_regnum_base + tdep->tls_register_count)
 713     store_tlsregs_to_thread (regcache);
 714
 715   /* PAuth registers are read-only.  */
 716 }
 717
 718 /* A version of the "store_registers" target_ops method used when running
 719    32-bit ARM code on an AArch64 target.  Copy the value of register REGNO
 720    from REGCACHE into the the target.  */
 721
 722 static void
 723 aarch32_store_registers (struct regcache *regcache, int regno)
 724 {
 725   arm_gdbarch_tdep *tdep
 726     = gdbarch_tdep<arm_gdbarch_tdep> (regcache->arch ());
 727
 728   if (regno == -1)
 729     {
 730       store_gregs_to_thread (regcache);
 731       if (tdep->vfp_register_count > 0)
 732         store_fpregs_to_thread (regcache);
 733     }
 734   else if (regno < ARM_F0_REGNUM || regno == ARM_PS_REGNUM)
 735     store_gregs_to_thread (regcache);
 736   else if (tdep->vfp_register_count > 0
 737            && regno >= ARM_D0_REGNUM
 738            && (regno < ARM_D0_REGNUM + tdep->vfp_register_count
 739                || regno == ARM_FPSCR_REGNUM))
 740     store_fpregs_to_thread (regcache);
 741 }
 742
 743 /* Implement the "store_registers" target_ops method.  */
 744
 745 void
 746 aarch64_linux_nat_target::store_registers (struct regcache *regcache,
 747                                            int regno)
 748 {
 749   if (gdbarch_bfd_arch_info (regcache->arch ())->bits_per_word == 32)
 750     aarch32_store_registers (regcache, regno);
 751   else
 752     aarch64_store_registers (regcache, regno);
 753 }
 754
 755 /* Fill register REGNO (if it is a general-purpose register) in
 756    *GREGSETPS with the value in GDB's register array.  If REGNO is -1,
 757    do this for all registers.  */
 758
 759 void
 760 fill_gregset (const struct regcache *regcache,
 761               gdb_gregset_t *gregsetp, int regno)
 762 {
 763   regcache_collect_regset (&aarch64_linux_gregset, regcache,
 764                            regno, (gdb_byte *) gregsetp,
 765                            AARCH64_LINUX_SIZEOF_GREGSET);
 766 }
 767
 768 /* Fill GDB's register array with the general-purpose register values
 769    in *GREGSETP.  */
 770
 771 void
 772 supply_gregset (struct regcache *regcache, const gdb_gregset_t *gregsetp)
 773 {
 774   regcache_supply_regset (&aarch64_linux_gregset, regcache, -1,
 775                           (const gdb_byte *) gregsetp,
 776                           AARCH64_LINUX_SIZEOF_GREGSET);
 777 }
 778
 779 /* Fill register REGNO (if it is a floating-point register) in
 780    *FPREGSETP with the value in GDB's register array.  If REGNO is -1,
 781    do this for all registers.  */
 782
 783 void
 784 fill_fpregset (const struct regcache *regcache,
 785                gdb_fpregset_t *fpregsetp, int regno)
 786 {
 787   regcache_collect_regset (&aarch64_linux_fpregset, regcache,
 788                            regno, (gdb_byte *) fpregsetp,
 789                            AARCH64_LINUX_SIZEOF_FPREGSET);
 790 }
 791
 792 /* Fill GDB's register array with the floating-point register values
 793    in *FPREGSETP.  */
 794
 795 void
 796 supply_fpregset (struct regcache *regcache, const gdb_fpregset_t *fpregsetp)
 797 {
 798   regcache_supply_regset (&aarch64_linux_fpregset, regcache, -1,
 799                           (const gdb_byte *) fpregsetp,
 800                           AARCH64_LINUX_SIZEOF_FPREGSET);
 801 }
 802
 803 /* linux_nat_new_fork hook.   */
 804
 805 void
 806 aarch64_linux_nat_target::low_new_fork (struct lwp_info *parent,
 807                                         pid_t child_pid)
 808 {
 809   pid_t parent_pid;
 810   struct aarch64_debug_reg_state *parent_state;
 811   struct aarch64_debug_reg_state *child_state;
 812
 813   /* NULL means no watchpoint has ever been set in the parent.  In
 814      that case, there's nothing to do.  */
 815   if (parent->arch_private == NULL)
 816     return;
 817
 818   /* GDB core assumes the child inherits the watchpoints/hw
 819      breakpoints of the parent, and will remove them all from the
 820      forked off process.  Copy the debug registers mirrors into the
 821      new process so that all breakpoints and watchpoints can be
 822      removed together.  */
 823
 824   parent_pid = parent->ptid.pid ();
 825   parent_state = aarch64_get_debug_reg_state (parent_pid);
 826   child_state = aarch64_get_debug_reg_state (child_pid);
 827   *child_state = *parent_state;
 828 }
 829 \f
 830
 831 /* Called by libthread_db.  Returns a pointer to the thread local
 832    storage (or its descriptor).  */
 833
 834 ps_err_e
 835 ps_get_thread_area (struct ps_prochandle *ph,
 836                     lwpid_t lwpid, int idx, void **base)
 837 {
 838   gdbarch *arch = current_inferior ()->arch ();
 839   int is_64bit_p = (gdbarch_bfd_arch_info (arch)->bits_per_word == 64);
 840
 841   return aarch64_ps_get_thread_area (ph, lwpid, idx, base, is_64bit_p);
 842 }
 843 \f
 844
 845 /* Implement the virtual inf_ptrace_target::post_startup_inferior method.  */
 846
 847 void
 848 aarch64_linux_nat_target::post_startup_inferior (ptid_t ptid)
 849 {
 850   low_forget_process (ptid.pid ());
 851   aarch64_linux_get_debug_reg_capacity (ptid.pid ());
 852   linux_nat_target::post_startup_inferior (ptid);
 853 }
 854
 855 /* Implement the "post_attach" target_ops method.  */
 856
 857 void
 858 aarch64_linux_nat_target::post_attach (int pid)
 859 {
 860   low_forget_process (pid);
 861   /* Set the hardware debug register capacity.  If
 862      aarch64_linux_get_debug_reg_capacity is not called
 863      (as it is in aarch64_linux_child_post_startup_inferior) then
 864      software watchpoints will be used instead of hardware
 865      watchpoints when attaching to a target.  */
 866   aarch64_linux_get_debug_reg_capacity (pid);
 867   linux_nat_target::post_attach (pid);
 868 }
 869
 870 /* Implement the "read_description" target_ops method.  */
 871
 872 const struct target_desc *
 873 aarch64_linux_nat_target::read_description ()
 874 {
 875   int ret, tid;
 876   gdb_byte regbuf[ARM_VFP3_REGS_SIZE];
 877   struct iovec iovec;
 878
 879   if (inferior_ptid == null_ptid)
 880     return this->beneath ()->read_description ();
 881
 882   tid = inferior_ptid.pid ();
 883
 884   iovec.iov_base = regbuf;
 885   iovec.iov_len = ARM_VFP3_REGS_SIZE;
 886
 887   ret = ptrace (PTRACE_GETREGSET, tid, NT_ARM_VFP, &iovec);
 888   if (ret == 0)
 889     return aarch32_read_description (false);
 890
 891   CORE_ADDR hwcap = linux_get_hwcap ();
 892   CORE_ADDR hwcap2 = linux_get_hwcap2 ();
 893
 894   aarch64_features features;
 895   /* SVE/SSVE check.  Reading VQ may return either the regular vector length
 896      or the streaming vector length, depending on whether streaming mode is
 897      active or not.  */
 898   features.vq = aarch64_sve_get_vq (tid);
 899   features.pauth = hwcap & AARCH64_HWCAP_PACA;
 900   features.mte = hwcap2 & HWCAP2_MTE;
 901   features.tls = aarch64_tls_register_count (tid);
 902   /* SME feature check.  */
 903   features.svq = aarch64_za_get_svq (tid);
 904
 905   /* Check for SME2 support.  */
 906   if ((hwcap2 & HWCAP2_SME2) || (hwcap2 & HWCAP2_SME2P1))
 907     features.sme2 = supports_zt_registers (tid);
 908
 909   return aarch64_read_description (features);
 910 }
 911
 912 /* Convert a native/host siginfo object, into/from the siginfo in the
 913    layout of the inferiors' architecture.  Returns true if any
 914    conversion was done; false otherwise.  If DIRECTION is 1, then copy
 915    from INF to NATIVE.  If DIRECTION is 0, copy from NATIVE to
 916    INF.  */
 917
 918 bool
 919 aarch64_linux_nat_target::low_siginfo_fixup (siginfo_t *native, gdb_byte *inf,
 920                                              int direction)
 921 {
 922   struct gdbarch *gdbarch = get_frame_arch (get_current_frame ());
 923
 924   /* Is the inferior 32-bit?  If so, then do fixup the siginfo
 925      object.  */
 926   if (gdbarch_bfd_arch_info (gdbarch)->bits_per_word == 32)
 927     {
 928       if (direction == 0)
 929         aarch64_compat_siginfo_from_siginfo ((struct compat_siginfo *) inf,
 930                                              native);
 931       else
 932         aarch64_siginfo_from_compat_siginfo (native,
 933                                              (struct compat_siginfo *) inf);
 934
 935       return true;
 936     }
 937
 938   return false;
 939 }
 940
 941 /* Implement the "stopped_data_address" target_ops method.  */
 942
 943 bool
 944 aarch64_linux_nat_target::stopped_data_address (CORE_ADDR *addr_p)
 945 {
 946   siginfo_t siginfo;
 947   struct aarch64_debug_reg_state *state;
 948
 949   if (!linux_nat_get_siginfo (inferior_ptid, &siginfo))
 950     return false;
 951
 952   /* This must be a hardware breakpoint.  */
 953   if (siginfo.si_signo != SIGTRAP
 954       || (siginfo.si_code & 0xffff) != TRAP_HWBKPT)
 955     return false;
 956
 957   /* Make sure to ignore the top byte, otherwise we may not recognize a
 958      hardware watchpoint hit.  The stopped data addresses coming from the
 959      kernel can potentially be tagged addresses.  */
 960   struct gdbarch *gdbarch = thread_architecture (inferior_ptid);
 961   const CORE_ADDR addr_trap
 962     = gdbarch_remove_non_address_bits (gdbarch, (CORE_ADDR) siginfo.si_addr);
 963
 964   /* Check if the address matches any watched address.  */
 965   state = aarch64_get_debug_reg_state (inferior_ptid.pid ());
 966   return aarch64_stopped_data_address (state, addr_trap, addr_p);
 967 }
 968
 969 /* Implement the "stopped_by_watchpoint" target_ops method.  */
 970
 971 bool
 972 aarch64_linux_nat_target::stopped_by_watchpoint ()
 973 {
 974   return stopped_data_address (nullptr);
 975 }
 976
 977 /* Implement the "can_do_single_step" target_ops method.  */
 978
 979 int
 980 aarch64_linux_nat_target::can_do_single_step ()
 981 {
 982   return 1;
 983 }
 984
 985 /* Implement the "thread_architecture" target_ops method.
 986
 987    Returns the gdbarch for the thread identified by PTID.  If the thread in
 988    question is a 32-bit ARM thread, then the architecture returned will be
 989    that of the process itself.
 990
 991    If the thread is an AArch64 thread then we need to check the current
 992    vector length; if the vector length has changed then we need to lookup a
 993    new gdbarch that matches the new vector length.  */
 994
 995 struct gdbarch *
 996 aarch64_linux_nat_target::thread_architecture (ptid_t ptid)
 997 {
 998   /* Find the current gdbarch the same way as process_stratum_target.  */
 999   inferior *inf = find_inferior_ptid (this, ptid);
1000   gdb_assert (inf != NULL);
1001
1002   /* If this is a 32-bit architecture, then this is ARM, not AArch64.
1003      There's no SVE vectors here, so just return the inferior
1004      architecture.  */
1005   if (gdbarch_bfd_arch_info (inf->arch ())->bits_per_word == 32)
1006     return inf->arch ();
1007
1008   /* Only return the inferior's gdbarch if both vq and svq match the ones in
1009      the tdep.  */
1010   aarch64_gdbarch_tdep *tdep
1011     = gdbarch_tdep<aarch64_gdbarch_tdep> (inf->arch ());
1012   uint64_t vq = aarch64_sve_get_vq (ptid.lwp ());
1013   uint64_t svq = aarch64_za_get_svq (ptid.lwp ());
1014   if (vq == tdep->vq && svq == tdep->sme_svq)
1015     return inf->arch ();
1016
1017   /* We reach here if any vector length for the thread is different from its
1018      value at process start.  Lookup gdbarch via info (potentially creating a
1019      new one) by using a target description that corresponds to the new vq/svq
1020      value and the current architecture features.  */
1021
1022   const struct target_desc *tdesc = gdbarch_target_desc (inf->arch ());
1023   aarch64_features features = aarch64_features_from_target_desc (tdesc);
1024   features.vq = vq;
1025   features.svq = svq;
1026
1027   /* Check for the SME2 feature.  */
1028   features.sme2 = supports_zt_registers (ptid.lwp ());
1029
1030   struct gdbarch_info info;
1031   info.bfd_arch_info = bfd_lookup_arch (bfd_arch_aarch64, bfd_mach_aarch64);
1032   info.target_desc = aarch64_read_description (features);
1033   return gdbarch_find_by_info (info);
1034 }
1035
1036 /* Implement the "supports_memory_tagging" target_ops method.  */
1037
1038 bool
1039 aarch64_linux_nat_target::supports_memory_tagging ()
1040 {
1041   return (linux_get_hwcap2 () & HWCAP2_MTE) != 0;
1042 }
1043
1044 /* Implement the "fetch_memtags" target_ops method.  */
1045
1046 bool
1047 aarch64_linux_nat_target::fetch_memtags (CORE_ADDR address, size_t len,
1048                                          gdb::byte_vector &tags, int type)
1049 {
1050   int tid = get_ptrace_pid (inferior_ptid);
1051
1052   /* Allocation tags?  */
1053   if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
1054     return aarch64_mte_fetch_memtags (tid, address, len, tags);
1055
1056   return false;
1057 }
1058
1059 /* Implement the "store_memtags" target_ops method.  */
1060
1061 bool
1062 aarch64_linux_nat_target::store_memtags (CORE_ADDR address, size_t len,
1063                                          const gdb::byte_vector &tags, int type)
1064 {
1065   int tid = get_ptrace_pid (inferior_ptid);
1066
1067   /* Allocation tags?  */
1068   if (type == static_cast<int> (aarch64_memtag_type::mte_allocation))
1069     return aarch64_mte_store_memtags (tid, address, len, tags);
1070
1071   return false;
1072 }
1073
1074 void _initialize_aarch64_linux_nat ();
1075 void
1076 _initialize_aarch64_linux_nat ()
1077 {
1078   aarch64_initialize_hw_point ();
1079
1080   /* Register the target.  */
1081   linux_target = &the_aarch64_linux_nat_target;
1082   add_inf_child_target (&the_aarch64_linux_nat_target);
1083 }