opcodes/i386-dis.c

   1 /* Print i386 instructions for GDB, the GNU debugger.
   2    Copyright (C) 1988-2024 Free Software Foundation, Inc.
   3
   4    This file is part of the GNU opcodes library.
   5
   6    This library is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    It is distributed in the hope that it will be useful, but WITHOUT
  12    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  13    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  14    License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21
  22 /* 80386 instruction printer by Pace Willisson (pace@prep.ai.mit.edu)
  23    July 1988
  24     modified by John Hassey (hassey@dg-rtp.dg.com)
  25     x86-64 support added by Jan Hubicka (jh@suse.cz)
  26     VIA PadLock support by Michal Ludvig (mludvig@suse.cz).  */
  27
  28 /* The main tables describing the instructions is essentially a copy
  29    of the "Opcode Map" chapter (Appendix A) of the Intel 80386
  30    Programmers Manual.  Usually, there is a capital letter, followed
  31    by a small letter.  The capital letter tell the addressing mode,
  32    and the small letter tells about the operand size.  Refer to
  33    the Intel manual for details.  */
  34
  35 #include "sysdep.h"
  36 #include "disassemble.h"
  37 #include "opintl.h"
  38 #include "opcode/i386.h"
  39 #include "libiberty.h"
  40 #include "safe-ctype.h"
  41
  42 typedef struct instr_info instr_info;
  43
  44 static bool dofloat (instr_info *, int);
  45 static int putop (instr_info *, const char *, int);
  46 static void oappend_with_style (instr_info *, const char *,
  47                                 enum disassembler_style);
  48
  49 static bool OP_E (instr_info *, int, int);
  50 static bool OP_E_memory (instr_info *, int, int);
  51 static bool OP_indirE (instr_info *, int, int);
  52 static bool OP_G (instr_info *, int, int);
  53 static bool OP_ST (instr_info *, int, int);
  54 static bool OP_STi (instr_info *, int, int);
  55 static bool OP_Skip_MODRM (instr_info *, int, int);
  56 static bool OP_REG (instr_info *, int, int);
  57 static bool OP_IMREG (instr_info *, int, int);
  58 static bool OP_I (instr_info *, int, int);
  59 static bool OP_I64 (instr_info *, int, int);
  60 static bool OP_sI (instr_info *, int, int);
  61 static bool OP_J (instr_info *, int, int);
  62 static bool OP_SEG (instr_info *, int, int);
  63 static bool OP_DIR (instr_info *, int, int);
  64 static bool OP_OFF (instr_info *, int, int);
  65 static bool OP_OFF64 (instr_info *, int, int);
  66 static bool OP_ESreg (instr_info *, int, int);
  67 static bool OP_DSreg (instr_info *, int, int);
  68 static bool OP_C (instr_info *, int, int);
  69 static bool OP_D (instr_info *, int, int);
  70 static bool OP_T (instr_info *, int, int);
  71 static bool OP_MMX (instr_info *, int, int);
  72 static bool OP_XMM (instr_info *, int, int);
  73 static bool OP_EM (instr_info *, int, int);
  74 static bool OP_EX (instr_info *, int, int);
  75 static bool OP_EMC (instr_info *, int,int);
  76 static bool OP_MXC (instr_info *, int,int);
  77 static bool OP_R (instr_info *, int, int);
  78 static bool OP_M (instr_info *, int, int);
  79 static bool OP_VEX (instr_info *, int, int);
  80 static bool OP_VexR (instr_info *, int, int);
  81 static bool OP_VexW (instr_info *, int, int);
  82 static bool OP_Rounding (instr_info *, int, int);
  83 static bool OP_REG_VexI4 (instr_info *, int, int);
  84 static bool OP_VexI4 (instr_info *, int, int);
  85 static bool OP_0f07 (instr_info *, int, int);
  86 static bool OP_Monitor (instr_info *, int, int);
  87 static bool OP_Mwait (instr_info *, int, int);
  88
  89 static bool PCLMUL_Fixup (instr_info *, int, int);
  90 static bool VPCMP_Fixup (instr_info *, int, int);
  91 static bool VPCOM_Fixup (instr_info *, int, int);
  92 static bool NOP_Fixup (instr_info *, int, int);
  93 static bool OP_3DNowSuffix (instr_info *, int, int);
  94 static bool CMP_Fixup (instr_info *, int, int);
  95 static bool REP_Fixup (instr_info *, int, int);
  96 static bool SEP_Fixup (instr_info *, int, int);
  97 static bool BND_Fixup (instr_info *, int, int);
  98 static bool NOTRACK_Fixup (instr_info *, int, int);
  99 static bool HLE_Fixup1 (instr_info *, int, int);
 100 static bool HLE_Fixup2 (instr_info *, int, int);
 101 static bool HLE_Fixup3 (instr_info *, int, int);
 102 static bool CMPXCHG8B_Fixup (instr_info *, int, int);
 103 static bool XMM_Fixup (instr_info *, int, int);
 104 static bool FXSAVE_Fixup (instr_info *, int, int);
 105 static bool MOVSXD_Fixup (instr_info *, int, int);
 106 static bool DistinctDest_Fixup (instr_info *, int, int);
 107 static bool PREFETCHI_Fixup (instr_info *, int, int);
 108 static bool PUSH2_POP2_Fixup (instr_info *, int, int);
 109 static bool JMPABS_Fixup (instr_info *, int, int);
 110
 111 static void ATTRIBUTE_PRINTF_3 i386_dis_printf (const disassemble_info *,
 112                                                 enum disassembler_style,
 113                                                 const char *, ...);
 114
 115 /* This character is used to encode style information within the output
 116    buffers.  See oappend_insert_style for more details.  */
 117 #define STYLE_MARKER_CHAR '\002'
 118
 119 /* The maximum operand buffer size.  */
 120 #define MAX_OPERAND_BUFFER_SIZE 128
 121
 122 enum address_mode
 123 {
 124   mode_16bit,
 125   mode_32bit,
 126   mode_64bit
 127 };
 128
 129 static const char *prefix_name (enum address_mode, uint8_t, int);
 130
 131 enum x86_64_isa
 132 {
 133   amd64 = 1,
 134   intel64
 135 };
 136
 137 enum evex_type
 138 {
 139   evex_default = 0,
 140   evex_from_legacy,
 141   evex_from_vex,
 142 };
 143
 144 struct instr_info
 145 {
 146   enum address_mode address_mode;
 147
 148   /* Flags for the prefixes for the current instruction.  See below.  */
 149   int prefixes;
 150
 151   /* REX prefix the current instruction.  See below.  */
 152   uint8_t rex;
 153   /* Bits of REX we've already used.  */
 154   uint8_t rex_used;
 155
 156   /* Record W R4 X4 B4 bits for rex2.  */
 157   unsigned char rex2;
 158   /* Bits of rex2 we've already used.  */
 159   unsigned char rex2_used;
 160   unsigned char rex2_payload;
 161
 162   bool need_modrm;
 163   unsigned char need_vex;
 164   bool has_sib;
 165
 166   /* Flags for ins->prefixes which we somehow handled when printing the
 167      current instruction.  */
 168   int used_prefixes;
 169
 170   /* Flags for EVEX bits which we somehow handled when printing the
 171      current instruction.  */
 172   int evex_used;
 173
 174   char obuf[MAX_OPERAND_BUFFER_SIZE];
 175   char *obufp;
 176   char *mnemonicendp;
 177   const uint8_t *start_codep;
 178   uint8_t *codep;
 179   const uint8_t *end_codep;
 180   unsigned char nr_prefixes;
 181   signed char last_lock_prefix;
 182   signed char last_repz_prefix;
 183   signed char last_repnz_prefix;
 184   signed char last_data_prefix;
 185   signed char last_addr_prefix;
 186   signed char last_rex_prefix;
 187   signed char last_rex2_prefix;
 188   signed char last_seg_prefix;
 189   signed char fwait_prefix;
 190   /* The active segment register prefix.  */
 191   unsigned char active_seg_prefix;
 192
 193 #define MAX_CODE_LENGTH 15
 194   /* We can up to 14 ins->prefixes since the maximum instruction length is
 195      15bytes.  */
 196   uint8_t all_prefixes[MAX_CODE_LENGTH - 1];
 197   disassemble_info *info;
 198
 199   struct
 200   {
 201     int mod;
 202     int reg;
 203     int rm;
 204   }
 205   modrm;
 206
 207   struct
 208   {
 209     int scale;
 210     int index;
 211     int base;
 212   }
 213   sib;
 214
 215   struct
 216   {
 217     int register_specifier;
 218     int length;
 219     int prefix;
 220     int mask_register_specifier;
 221     int ll;
 222     bool w;
 223     bool evex;
 224     bool v;
 225     bool zeroing;
 226     bool b;
 227     bool no_broadcast;
 228   }
 229   vex;
 230
 231 /* For APX EVEX-promoted prefix, EVEX.ND shares the same bit as vex.b.  */
 232 #define nd b
 233
 234   enum evex_type evex_type;
 235
 236   /* Remember if the current op is a jump instruction.  */
 237   bool op_is_jump;
 238
 239   bool two_source_ops;
 240
 241   /* Record whether EVEX masking is used incorrectly.  */
 242   bool illegal_masking;
 243
 244   /* Record whether the modrm byte has been skipped.  */
 245   bool has_skipped_modrm;
 246
 247   unsigned char op_ad;
 248   signed char op_index[MAX_OPERANDS];
 249   bool op_riprel[MAX_OPERANDS];
 250   char *op_out[MAX_OPERANDS];
 251   bfd_vma op_address[MAX_OPERANDS];
 252   bfd_vma start_pc;
 253
 254   /* On the 386's of 1988, the maximum length of an instruction is 15 bytes.
 255    *   (see topic "Redundant ins->prefixes" in the "Differences from 8086"
 256    *   section of the "Virtual 8086 Mode" chapter.)
 257    * 'pc' should be the address of this instruction, it will
 258    *   be used to print the target address if this is a relative jump or call
 259    * The function returns the length of this instruction in bytes.
 260    */
 261   char intel_syntax;
 262   bool intel_mnemonic;
 263   char open_char;
 264   char close_char;
 265   char separator_char;
 266   char scale_char;
 267
 268   enum x86_64_isa isa64;
 269 };
 270
 271 struct dis_private {
 272   bfd_vma insn_start;
 273   int orig_sizeflag;
 274
 275   /* Indexes first byte not fetched.  */
 276   unsigned int fetched;
 277   uint8_t the_buffer[2 * MAX_CODE_LENGTH - 1];
 278 };
 279
 280 /* Mark parts used in the REX prefix.  When we are testing for
 281    empty prefix (for 8bit register REX extension), just mask it
 282    out.  Otherwise test for REX bit is excuse for existence of REX
 283    only in case value is nonzero.  */
 284 #define USED_REX(value)                                 \
 285   {                                                     \
 286     if (value)                                          \
 287       {                                                 \
 288         if (ins->rex & value)                           \
 289           ins->rex_used |= (value) | REX_OPCODE;        \
 290         if (ins->rex2 & value)                          \
 291           {                                             \
 292             ins->rex2_used |= (value);                  \
 293             ins->rex_used |= REX_OPCODE;                \
 294           }                                             \
 295       }                                                 \
 296     else                                                \
 297       ins->rex_used |= REX_OPCODE;                      \
 298   }
 299
 300
 301 #define EVEX_b_used 1
 302 #define EVEX_len_used 2
 303
 304
 305 /* {rex2} is not printed when the REX2_SPECIAL is set.  */
 306 #define REX2_SPECIAL 16
 307
 308 /* Flags stored in PREFIXES.  */
 309 #define PREFIX_REPZ 1
 310 #define PREFIX_REPNZ 2
 311 #define PREFIX_CS 4
 312 #define PREFIX_SS 8
 313 #define PREFIX_DS 0x10
 314 #define PREFIX_ES 0x20
 315 #define PREFIX_FS 0x40
 316 #define PREFIX_GS 0x80
 317 #define PREFIX_LOCK 0x100
 318 #define PREFIX_DATA 0x200
 319 #define PREFIX_ADDR 0x400
 320 #define PREFIX_FWAIT 0x800
 321 #define PREFIX_REX2 0x1000
 322 #define PREFIX_NP_OR_DATA 0x2000
 323 #define NO_PREFIX   0x4000
 324
 325 /* Make sure that bytes from INFO->PRIVATE_DATA->BUFFER (inclusive)
 326    to ADDR (exclusive) are valid.  Returns true for success, false
 327    on error.  */
 328 static bool
 329 fetch_code (struct disassemble_info *info, const uint8_t *until)
 330 {
 331   int status = -1;
 332   struct dis_private *priv = info->private_data;
 333   bfd_vma start = priv->insn_start + priv->fetched;
 334   uint8_t *fetch_end = priv->the_buffer + priv->fetched;
 335   ptrdiff_t needed = until - fetch_end;
 336
 337   if (needed <= 0)
 338     return true;
 339
 340   if (priv->fetched + (size_t) needed <= ARRAY_SIZE (priv->the_buffer))
 341     status = (*info->read_memory_func) (start, fetch_end, needed, info);
 342   if (status != 0)
 343     {
 344       /* If we did manage to read at least one byte, then
 345          print_insn_i386 will do something sensible.  Otherwise, print
 346          an error.  We do that here because this is where we know
 347          STATUS.  */
 348       if (!priv->fetched)
 349         (*info->memory_error_func) (status, start, info);
 350       return false;
 351     }
 352
 353   priv->fetched += needed;
 354   return true;
 355 }
 356
 357 static bool
 358 fetch_modrm (instr_info *ins)
 359 {
 360   if (!fetch_code (ins->info, ins->codep + 1))
 361     return false;
 362
 363   ins->modrm.mod = (*ins->codep >> 6) & 3;
 364   ins->modrm.reg = (*ins->codep >> 3) & 7;
 365   ins->modrm.rm = *ins->codep & 7;
 366
 367   return true;
 368 }
 369
 370 static int
 371 fetch_error (const instr_info *ins)
 372 {
 373   /* Getting here means we tried for data but didn't get it.  That
 374      means we have an incomplete instruction of some sort.  Just
 375      print the first byte as a prefix or a .byte pseudo-op.  */
 376   const struct dis_private *priv = ins->info->private_data;
 377   const char *name = NULL;
 378
 379   if (ins->codep <= priv->the_buffer)
 380     return -1;
 381
 382   if (ins->prefixes || ins->fwait_prefix >= 0 || (ins->rex & REX_OPCODE))
 383     name = prefix_name (ins->address_mode, priv->the_buffer[0],
 384                         priv->orig_sizeflag);
 385   if (name != NULL)
 386     i386_dis_printf (ins->info, dis_style_mnemonic, "%s", name);
 387   else
 388     {
 389       /* Just print the first byte as a .byte instruction.  */
 390       i386_dis_printf (ins->info, dis_style_assembler_directive, ".byte ");
 391       i386_dis_printf (ins->info, dis_style_immediate, "%#x",
 392                        (unsigned int) priv->the_buffer[0]);
 393     }
 394
 395   return 1;
 396 }
 397
 398 /* Possible values for prefix requirement.  */
 399 #define PREFIX_IGNORED_SHIFT    16
 400 #define PREFIX_IGNORED_REPZ     (PREFIX_REPZ << PREFIX_IGNORED_SHIFT)
 401 #define PREFIX_IGNORED_REPNZ    (PREFIX_REPNZ << PREFIX_IGNORED_SHIFT)
 402 #define PREFIX_IGNORED_DATA     (PREFIX_DATA << PREFIX_IGNORED_SHIFT)
 403 #define PREFIX_IGNORED_ADDR     (PREFIX_ADDR << PREFIX_IGNORED_SHIFT)
 404 #define PREFIX_IGNORED_LOCK     (PREFIX_LOCK << PREFIX_IGNORED_SHIFT)
 405 #define PREFIX_REX2_ILLEGAL     (PREFIX_REX2 << PREFIX_IGNORED_SHIFT)
 406
 407 /* Opcode prefixes.  */
 408 #define PREFIX_OPCODE           (PREFIX_REPZ \
 409                                  | PREFIX_REPNZ \
 410                                  | PREFIX_DATA)
 411
 412 /* Prefixes ignored.  */
 413 #define PREFIX_IGNORED          (PREFIX_IGNORED_REPZ \
 414                                  | PREFIX_IGNORED_REPNZ \
 415                                  | PREFIX_IGNORED_DATA)
 416
 417 #define XX { NULL, 0 }
 418 #define Bad_Opcode NULL, { { NULL, 0 } }, 0
 419
 420 #define Eb { OP_E, b_mode }
 421 #define Ebnd { OP_E, bnd_mode }
 422 #define EbS { OP_E, b_swap_mode }
 423 #define EbndS { OP_E, bnd_swap_mode }
 424 #define Ev { OP_E, v_mode }
 425 #define Eva { OP_E, va_mode }
 426 #define Ev_bnd { OP_E, v_bnd_mode }
 427 #define EvS { OP_E, v_swap_mode }
 428 #define Ed { OP_E, d_mode }
 429 #define Edq { OP_E, dq_mode }
 430 #define Edb { OP_E, db_mode }
 431 #define Edw { OP_E, dw_mode }
 432 #define Eq { OP_E, q_mode }
 433 #define indirEv { OP_indirE, indir_v_mode }
 434 #define indirEp { OP_indirE, f_mode }
 435 #define stackEv { OP_E, stack_v_mode }
 436 #define Em { OP_E, m_mode }
 437 #define Ew { OP_E, w_mode }
 438 #define M { OP_M, 0 }           /* lea, lgdt, etc. */
 439 #define Ma { OP_M, a_mode }
 440 #define Mb { OP_M, b_mode }
 441 #define Md { OP_M, d_mode }
 442 #define Mdq { OP_M, dq_mode }
 443 #define Mo { OP_M, o_mode }
 444 #define Mp { OP_M, f_mode }             /* 32 or 48 bit memory operand for LDS, LES etc */
 445 #define Mq { OP_M, q_mode }
 446 #define Mv { OP_M, v_mode }
 447 #define Mv_bnd { OP_M, v_bndmk_mode }
 448 #define Mw { OP_M, w_mode }
 449 #define Mx { OP_M, x_mode }
 450 #define Mxmm { OP_M, xmm_mode }
 451 #define Mymm { OP_M, ymm_mode }
 452 #define Gb { OP_G, b_mode }
 453 #define Gbnd { OP_G, bnd_mode }
 454 #define Gv { OP_G, v_mode }
 455 #define Gd { OP_G, d_mode }
 456 #define Gdq { OP_G, dq_mode }
 457 #define Gq { OP_G, q_mode }
 458 #define Gm { OP_G, m_mode }
 459 #define Gva { OP_G, va_mode }
 460 #define Gw { OP_G, w_mode }
 461 #define Ib { OP_I, b_mode }
 462 #define sIb { OP_sI, b_mode }   /* sign extened byte */
 463 #define sIbT { OP_sI, b_T_mode } /* sign extened byte like 'T' */
 464 #define Iv { OP_I, v_mode }
 465 #define sIv { OP_sI, v_mode }
 466 #define Iv64 { OP_I64, v_mode }
 467 #define Id { OP_I, d_mode }
 468 #define Iw { OP_I, w_mode }
 469 #define I1 { OP_I, const_1_mode }
 470 #define Jb { OP_J, b_mode }
 471 #define Jv { OP_J, v_mode }
 472 #define Jdqw { OP_J, dqw_mode }
 473 #define Cm { OP_C, m_mode }
 474 #define Dm { OP_D, m_mode }
 475 #define Td { OP_T, d_mode }
 476 #define Skip_MODRM { OP_Skip_MODRM, 0 }
 477
 478 #define RMeAX { OP_REG, eAX_reg }
 479 #define RMeBX { OP_REG, eBX_reg }
 480 #define RMeCX { OP_REG, eCX_reg }
 481 #define RMeDX { OP_REG, eDX_reg }
 482 #define RMeSP { OP_REG, eSP_reg }
 483 #define RMeBP { OP_REG, eBP_reg }
 484 #define RMeSI { OP_REG, eSI_reg }
 485 #define RMeDI { OP_REG, eDI_reg }
 486 #define RMrAX { OP_REG, rAX_reg }
 487 #define RMrBX { OP_REG, rBX_reg }
 488 #define RMrCX { OP_REG, rCX_reg }
 489 #define RMrDX { OP_REG, rDX_reg }
 490 #define RMrSP { OP_REG, rSP_reg }
 491 #define RMrBP { OP_REG, rBP_reg }
 492 #define RMrSI { OP_REG, rSI_reg }
 493 #define RMrDI { OP_REG, rDI_reg }
 494 #define RMAL { OP_REG, al_reg }
 495 #define RMCL { OP_REG, cl_reg }
 496 #define RMDL { OP_REG, dl_reg }
 497 #define RMBL { OP_REG, bl_reg }
 498 #define RMAH { OP_REG, ah_reg }
 499 #define RMCH { OP_REG, ch_reg }
 500 #define RMDH { OP_REG, dh_reg }
 501 #define RMBH { OP_REG, bh_reg }
 502 #define RMAX { OP_REG, ax_reg }
 503 #define RMDX { OP_REG, dx_reg }
 504
 505 #define eAX { OP_IMREG, eAX_reg }
 506 #define AL { OP_IMREG, al_reg }
 507 #define CL { OP_IMREG, cl_reg }
 508 #define zAX { OP_IMREG, z_mode_ax_reg }
 509 #define indirDX { OP_IMREG, indir_dx_reg }
 510
 511 #define Sw { OP_SEG, w_mode }
 512 #define Sv { OP_SEG, v_mode }
 513 #define Ap { OP_DIR, 0 }
 514 #define Ob { OP_OFF64, b_mode }
 515 #define Ov { OP_OFF64, v_mode }
 516 #define Xb { OP_DSreg, eSI_reg }
 517 #define Xv { OP_DSreg, eSI_reg }
 518 #define Xz { OP_DSreg, eSI_reg }
 519 #define Yb { OP_ESreg, eDI_reg }
 520 #define Yv { OP_ESreg, eDI_reg }
 521 #define DSBX { OP_DSreg, eBX_reg }
 522
 523 #define es { OP_REG, es_reg }
 524 #define ss { OP_REG, ss_reg }
 525 #define cs { OP_REG, cs_reg }
 526 #define ds { OP_REG, ds_reg }
 527 #define fs { OP_REG, fs_reg }
 528 #define gs { OP_REG, gs_reg }
 529
 530 #define MX { OP_MMX, 0 }
 531 #define XM { OP_XMM, 0 }
 532 #define XMScalar { OP_XMM, scalar_mode }
 533 #define XMGatherD { OP_XMM, vex_vsib_d_w_dq_mode }
 534 #define XMGatherQ { OP_XMM, vex_vsib_q_w_dq_mode }
 535 #define XMM { OP_XMM, xmm_mode }
 536 #define TMM { OP_XMM, tmm_mode }
 537 #define XMxmmq { OP_XMM, xmmq_mode }
 538 #define EM { OP_EM, v_mode }
 539 #define EMS { OP_EM, v_swap_mode }
 540 #define EMd { OP_EM, d_mode }
 541 #define EMx { OP_EM, x_mode }
 542 #define EXbwUnit { OP_EX, bw_unit_mode }
 543 #define EXb { OP_EX, b_mode }
 544 #define EXw { OP_EX, w_mode }
 545 #define EXd { OP_EX, d_mode }
 546 #define EXdS { OP_EX, d_swap_mode }
 547 #define EXwS { OP_EX, w_swap_mode }
 548 #define EXq { OP_EX, q_mode }
 549 #define EXqS { OP_EX, q_swap_mode }
 550 #define EXdq { OP_EX, dq_mode }
 551 #define EXx { OP_EX, x_mode }
 552 #define EXxh { OP_EX, xh_mode }
 553 #define EXxS { OP_EX, x_swap_mode }
 554 #define EXxmm { OP_EX, xmm_mode }
 555 #define EXymm { OP_EX, ymm_mode }
 556 #define EXxmmq { OP_EX, xmmq_mode }
 557 #define EXxmmqh { OP_EX, evex_half_bcst_xmmqh_mode }
 558 #define EXEvexHalfBcstXmmq { OP_EX, evex_half_bcst_xmmq_mode }
 559 #define EXxmmdw { OP_EX, xmmdw_mode }
 560 #define EXxmmqd { OP_EX, xmmqd_mode }
 561 #define EXxmmqdh { OP_EX, evex_half_bcst_xmmqdh_mode }
 562 #define EXymmq { OP_EX, ymmq_mode }
 563 #define EXEvexXGscat { OP_EX, evex_x_gscat_mode }
 564 #define EXEvexXNoBcst { OP_EX, evex_x_nobcst_mode }
 565 #define Rd { OP_R, d_mode }
 566 #define Rdq { OP_R, dq_mode }
 567 #define Rq { OP_R, q_mode }
 568 #define Nq { OP_R, q_mm_mode }
 569 #define Ux { OP_R, x_mode }
 570 #define Uxmm { OP_R, xmm_mode }
 571 #define Rxmmq { OP_R, xmmq_mode }
 572 #define Rymm { OP_R, ymm_mode }
 573 #define Rtmm { OP_R, tmm_mode }
 574 #define EMCq { OP_EMC, q_mode }
 575 #define MXC { OP_MXC, 0 }
 576 #define OPSUF { OP_3DNowSuffix, 0 }
 577 #define SEP { SEP_Fixup, 0 }
 578 #define CMP { CMP_Fixup, 0 }
 579 #define XMM0 { XMM_Fixup, 0 }
 580 #define FXSAVE { FXSAVE_Fixup, 0 }
 581
 582 #define Vex { OP_VEX, x_mode }
 583 #define VexW { OP_VexW, x_mode }
 584 #define VexScalar { OP_VEX, scalar_mode }
 585 #define VexScalarR { OP_VexR, scalar_mode }
 586 #define VexGatherD { OP_VEX, vex_vsib_d_w_dq_mode }
 587 #define VexGatherQ { OP_VEX, vex_vsib_q_w_dq_mode }
 588 #define VexGdq { OP_VEX, dq_mode }
 589 #define VexGb { OP_VEX, b_mode }
 590 #define VexGv { OP_VEX, v_mode }
 591 #define VexTmm { OP_VEX, tmm_mode }
 592 #define XMVexI4 { OP_REG_VexI4, x_mode }
 593 #define XMVexScalarI4 { OP_REG_VexI4, scalar_mode }
 594 #define VexI4 { OP_VexI4, 0 }
 595 #define PCLMUL { PCLMUL_Fixup, 0 }
 596 #define VPCMP { VPCMP_Fixup, 0 }
 597 #define VPCOM { VPCOM_Fixup, 0 }
 598
 599 #define EXxEVexR { OP_Rounding, evex_rounding_mode }
 600 #define EXxEVexR64 { OP_Rounding, evex_rounding_64_mode }
 601 #define EXxEVexS { OP_Rounding, evex_sae_mode }
 602
 603 #define MaskG { OP_G, mask_mode }
 604 #define MaskE { OP_E, mask_mode }
 605 #define MaskR { OP_R, mask_mode }
 606 #define MaskBDE { OP_E, mask_bd_mode }
 607 #define MaskVex { OP_VEX, mask_mode }
 608
 609 #define MVexVSIBDWpX { OP_M, vex_vsib_d_w_dq_mode }
 610 #define MVexVSIBQWpX { OP_M, vex_vsib_q_w_dq_mode }
 611
 612 #define MVexSIBMEM { OP_M, vex_sibmem_mode }
 613
 614 /* Used handle "rep" prefix for string instructions.  */
 615 #define Xbr { REP_Fixup, eSI_reg }
 616 #define Xvr { REP_Fixup, eSI_reg }
 617 #define Ybr { REP_Fixup, eDI_reg }
 618 #define Yvr { REP_Fixup, eDI_reg }
 619 #define Yzr { REP_Fixup, eDI_reg }
 620 #define indirDXr { REP_Fixup, indir_dx_reg }
 621 #define ALr { REP_Fixup, al_reg }
 622 #define eAXr { REP_Fixup, eAX_reg }
 623
 624 /* Used handle HLE prefix for lockable instructions.  */
 625 #define Ebh1 { HLE_Fixup1, b_mode }
 626 #define Evh1 { HLE_Fixup1, v_mode }
 627 #define Ebh2 { HLE_Fixup2, b_mode }
 628 #define Evh2 { HLE_Fixup2, v_mode }
 629 #define Ebh3 { HLE_Fixup3, b_mode }
 630 #define Evh3 { HLE_Fixup3, v_mode }
 631
 632 #define BND { BND_Fixup, 0 }
 633 #define NOTRACK { NOTRACK_Fixup, 0 }
 634
 635 #define cond_jump_flag { NULL, cond_jump_mode }
 636 #define loop_jcxz_flag { NULL, loop_jcxz_mode }
 637
 638 /* bits in sizeflag */
 639 #define SUFFIX_ALWAYS 4
 640 #define AFLAG 2
 641 #define DFLAG 1
 642
 643 enum
 644 {
 645   /* byte operand */
 646   b_mode = 1,
 647   /* byte operand with operand swapped */
 648   b_swap_mode,
 649   /* byte operand, sign extend like 'T' suffix */
 650   b_T_mode,
 651   /* operand size depends on prefixes */
 652   v_mode,
 653   /* operand size depends on prefixes with operand swapped */
 654   v_swap_mode,
 655   /* operand size depends on address prefix */
 656   va_mode,
 657   /* word operand */
 658   w_mode,
 659   /* double word operand  */
 660   d_mode,
 661   /* word operand with operand swapped  */
 662   w_swap_mode,
 663   /* double word operand with operand swapped */
 664   d_swap_mode,
 665   /* quad word operand */
 666   q_mode,
 667   /* 8-byte MM operand */
 668   q_mm_mode,
 669   /* quad word operand with operand swapped */
 670   q_swap_mode,
 671   /* ten-byte operand */
 672   t_mode,
 673   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 674      broadcast enabled.  */
 675   x_mode,
 676   /* Similar to x_mode, but with different EVEX mem shifts.  */
 677   evex_x_gscat_mode,
 678   /* Similar to x_mode, but with yet different EVEX mem shifts.  */
 679   bw_unit_mode,
 680   /* Similar to x_mode, but with disabled broadcast.  */
 681   evex_x_nobcst_mode,
 682   /* Similar to x_mode, but with operands swapped and disabled broadcast
 683      in EVEX.  */
 684   x_swap_mode,
 685   /* 16-byte XMM, 32-byte YMM or 64-byte ZMM operand.  In EVEX with
 686      broadcast of 16bit enabled.  */
 687   xh_mode,
 688   /* 16-byte XMM operand */
 689   xmm_mode,
 690   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 691      memory operand (depending on vector length).  Broadcast isn't
 692      allowed.  */
 693   xmmq_mode,
 694   /* Same as xmmq_mode, but broadcast is allowed.  */
 695   evex_half_bcst_xmmq_mode,
 696   /* XMM, XMM or YMM register operand, or quad word, xmmword or ymmword
 697      memory operand (depending on vector length).  16bit broadcast.  */
 698   evex_half_bcst_xmmqh_mode,
 699   /* 16-byte XMM, word, double word or quad word operand.  */
 700   xmmdw_mode,
 701   /* 16-byte XMM, double word, quad word operand or xmm word operand.  */
 702   xmmqd_mode,
 703   /* 16-byte XMM, double word, quad word operand or xmm word operand.
 704      16bit broadcast.  */
 705   evex_half_bcst_xmmqdh_mode,
 706   /* 32-byte YMM operand */
 707   ymm_mode,
 708   /* quad word, ymmword or zmmword memory operand.  */
 709   ymmq_mode,
 710   /* TMM operand */
 711   tmm_mode,
 712   /* d_mode in 32bit, q_mode in 64bit mode.  */
 713   m_mode,
 714   /* pair of v_mode operands */
 715   a_mode,
 716   cond_jump_mode,
 717   loop_jcxz_mode,
 718   movsxd_mode,
 719   v_bnd_mode,
 720   /* like v_bnd_mode in 32bit, no RIP-rel in 64bit mode.  */
 721   v_bndmk_mode,
 722   /* operand size depends on REX.W / VEX.W.  */
 723   dq_mode,
 724   /* Displacements like v_mode without considering Intel64 ISA.  */
 725   dqw_mode,
 726   /* bounds operand */
 727   bnd_mode,
 728   /* bounds operand with operand swapped */
 729   bnd_swap_mode,
 730   /* 4- or 6-byte pointer operand */
 731   f_mode,
 732   const_1_mode,
 733   /* v_mode for indirect branch opcodes.  */
 734   indir_v_mode,
 735   /* v_mode for stack-related opcodes.  */
 736   stack_v_mode,
 737   /* non-quad operand size depends on prefixes */
 738   z_mode,
 739   /* 16-byte operand */
 740   o_mode,
 741   /* registers like d_mode, memory like b_mode.  */
 742   db_mode,
 743   /* registers like d_mode, memory like w_mode.  */
 744   dw_mode,
 745
 746   /* Operand size depends on the VEX.W bit, with VSIB dword indices.  */
 747   vex_vsib_d_w_dq_mode,
 748   /* Operand size depends on the VEX.W bit, with VSIB qword indices.  */
 749   vex_vsib_q_w_dq_mode,
 750   /* mandatory non-vector SIB.  */
 751   vex_sibmem_mode,
 752
 753   /* scalar, ignore vector length.  */
 754   scalar_mode,
 755
 756   /* Static rounding.  */
 757   evex_rounding_mode,
 758   /* Static rounding, 64-bit mode only.  */
 759   evex_rounding_64_mode,
 760   /* Supress all exceptions.  */
 761   evex_sae_mode,
 762
 763   /* Mask register operand.  */
 764   mask_mode,
 765   /* Mask register operand.  */
 766   mask_bd_mode,
 767
 768   es_reg,
 769   cs_reg,
 770   ss_reg,
 771   ds_reg,
 772   fs_reg,
 773   gs_reg,
 774
 775   eAX_reg,
 776   eCX_reg,
 777   eDX_reg,
 778   eBX_reg,
 779   eSP_reg,
 780   eBP_reg,
 781   eSI_reg,
 782   eDI_reg,
 783
 784   al_reg,
 785   cl_reg,
 786   dl_reg,
 787   bl_reg,
 788   ah_reg,
 789   ch_reg,
 790   dh_reg,
 791   bh_reg,
 792
 793   ax_reg,
 794   cx_reg,
 795   dx_reg,
 796   bx_reg,
 797   sp_reg,
 798   bp_reg,
 799   si_reg,
 800   di_reg,
 801
 802   rAX_reg,
 803   rCX_reg,
 804   rDX_reg,
 805   rBX_reg,
 806   rSP_reg,
 807   rBP_reg,
 808   rSI_reg,
 809   rDI_reg,
 810
 811   z_mode_ax_reg,
 812   indir_dx_reg
 813 };
 814
 815 enum
 816 {
 817   FLOATCODE = 1,
 818   USE_REG_TABLE,
 819   USE_MOD_TABLE,
 820   USE_RM_TABLE,
 821   USE_PREFIX_TABLE,
 822   USE_X86_64_TABLE,
 823   USE_X86_64_EVEX_FROM_VEX_TABLE,
 824   USE_3BYTE_TABLE,
 825   USE_XOP_8F_TABLE,
 826   USE_VEX_C4_TABLE,
 827   USE_VEX_C5_TABLE,
 828   USE_VEX_LEN_TABLE,
 829   USE_VEX_W_TABLE,
 830   USE_EVEX_TABLE,
 831   USE_EVEX_LEN_TABLE
 832 };
 833
 834 #define FLOAT                   NULL, { { NULL, FLOATCODE } }, 0
 835
 836 #define DIS386(T, I)            NULL, { { NULL, (T)}, { NULL,  (I) } }, 0
 837 #define REG_TABLE(I)            DIS386 (USE_REG_TABLE, (I))
 838 #define MOD_TABLE(I)            DIS386 (USE_MOD_TABLE, (I))
 839 #define RM_TABLE(I)             DIS386 (USE_RM_TABLE, (I))
 840 #define PREFIX_TABLE(I)         DIS386 (USE_PREFIX_TABLE, (I))
 841 #define X86_64_TABLE(I)         DIS386 (USE_X86_64_TABLE, (I))
 842 #define X86_64_EVEX_FROM_VEX_TABLE(I) \
 843   DIS386 (USE_X86_64_EVEX_FROM_VEX_TABLE, (I))
 844 #define THREE_BYTE_TABLE(I)     DIS386 (USE_3BYTE_TABLE, (I))
 845 #define XOP_8F_TABLE()          DIS386 (USE_XOP_8F_TABLE, 0)
 846 #define VEX_C4_TABLE()          DIS386 (USE_VEX_C4_TABLE, 0)
 847 #define VEX_C5_TABLE()          DIS386 (USE_VEX_C5_TABLE, 0)
 848 #define VEX_LEN_TABLE(I)        DIS386 (USE_VEX_LEN_TABLE, (I))
 849 #define VEX_W_TABLE(I)          DIS386 (USE_VEX_W_TABLE, (I))
 850 #define EVEX_TABLE()            DIS386 (USE_EVEX_TABLE, 0)
 851 #define EVEX_LEN_TABLE(I)       DIS386 (USE_EVEX_LEN_TABLE, (I))
 852
 853 enum
 854 {
 855   REG_80 = 0,
 856   REG_81,
 857   REG_83,
 858   REG_8F,
 859   REG_C0,
 860   REG_C1,
 861   REG_C6,
 862   REG_C7,
 863   REG_D0,
 864   REG_D1,
 865   REG_D2,
 866   REG_D3,
 867   REG_F6,
 868   REG_F7,
 869   REG_FE,
 870   REG_FF,
 871   REG_0F00,
 872   REG_0F01,
 873   REG_0F0D,
 874   REG_0F18,
 875   REG_0F1C_P_0_MOD_0,
 876   REG_0F1E_P_1_MOD_3,
 877   REG_0F38D8_PREFIX_1,
 878   REG_0F3A0F_P_1,
 879   REG_0F71,
 880   REG_0F72,
 881   REG_0F73,
 882   REG_0FA6,
 883   REG_0FA7,
 884   REG_0FAE,
 885   REG_0FBA,
 886   REG_0FC7,
 887   REG_VEX_0F71,
 888   REG_VEX_0F72,
 889   REG_VEX_0F73,
 890   REG_VEX_0FAE,
 891   REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0,
 892   REG_VEX_0F38F3_L_0_P_0,
 893   REG_VEX_MAP7_F8_L_0_W_0,
 894
 895   REG_XOP_09_01_L_0,
 896   REG_XOP_09_02_L_0,
 897   REG_XOP_09_12_L_0,
 898   REG_XOP_0A_12_L_0,
 899
 900   REG_EVEX_0F71,
 901   REG_EVEX_0F72,
 902   REG_EVEX_0F73,
 903   REG_EVEX_0F38C6_L_2,
 904   REG_EVEX_0F38C7_L_2,
 905   REG_EVEX_MAP4_80,
 906   REG_EVEX_MAP4_81,
 907   REG_EVEX_MAP4_83,
 908   REG_EVEX_MAP4_8F,
 909   REG_EVEX_MAP4_F6,
 910   REG_EVEX_MAP4_F7,
 911   REG_EVEX_MAP4_FE,
 912   REG_EVEX_MAP4_FF,
 913 };
 914
 915 enum
 916 {
 917   MOD_62_32BIT = 0,
 918   MOD_C4_32BIT,
 919   MOD_C5_32BIT,
 920   MOD_0F01_REG_0,
 921   MOD_0F01_REG_1,
 922   MOD_0F01_REG_2,
 923   MOD_0F01_REG_3,
 924   MOD_0F01_REG_5,
 925   MOD_0F01_REG_7,
 926   MOD_0F12_PREFIX_0,
 927   MOD_0F16_PREFIX_0,
 928   MOD_0F18_REG_0,
 929   MOD_0F18_REG_1,
 930   MOD_0F18_REG_2,
 931   MOD_0F18_REG_3,
 932   MOD_0F18_REG_6,
 933   MOD_0F18_REG_7,
 934   MOD_0F1A_PREFIX_0,
 935   MOD_0F1B_PREFIX_0,
 936   MOD_0F1B_PREFIX_1,
 937   MOD_0F1C_PREFIX_0,
 938   MOD_0F1E_PREFIX_1,
 939   MOD_0FAE_REG_0,
 940   MOD_0FAE_REG_1,
 941   MOD_0FAE_REG_2,
 942   MOD_0FAE_REG_3,
 943   MOD_0FAE_REG_4,
 944   MOD_0FAE_REG_5,
 945   MOD_0FAE_REG_6,
 946   MOD_0FAE_REG_7,
 947   MOD_0FC7_REG_6,
 948   MOD_0FC7_REG_7,
 949   MOD_0F38DC_PREFIX_1,
 950   MOD_0F38F8,
 951
 952   MOD_VEX_0F3849_X86_64_L_0_W_0,
 953 };
 954
 955 enum
 956 {
 957   RM_C6_REG_7 = 0,
 958   RM_C7_REG_7,
 959   RM_0F01_REG_0,
 960   RM_0F01_REG_1,
 961   RM_0F01_REG_2,
 962   RM_0F01_REG_3,
 963   RM_0F01_REG_5_MOD_3,
 964   RM_0F01_REG_7_MOD_3,
 965   RM_0F1E_P_1_MOD_3_REG_7,
 966   RM_0FAE_REG_6_MOD_3_P_0,
 967   RM_0FAE_REG_7_MOD_3,
 968   RM_0F3A0F_P_1_R_0,
 969
 970   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0,
 971   RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3,
 972 };
 973
 974 enum
 975 {
 976   PREFIX_90 = 0,
 977   PREFIX_0F00_REG_6_X86_64,
 978   PREFIX_0F01_REG_0_MOD_3_RM_6,
 979   PREFIX_0F01_REG_0_MOD_3_RM_7,
 980   PREFIX_0F01_REG_1_RM_2,
 981   PREFIX_0F01_REG_1_RM_4,
 982   PREFIX_0F01_REG_1_RM_5,
 983   PREFIX_0F01_REG_1_RM_6,
 984   PREFIX_0F01_REG_1_RM_7,
 985   PREFIX_0F01_REG_3_RM_1,
 986   PREFIX_0F01_REG_5_MOD_0,
 987   PREFIX_0F01_REG_5_MOD_3_RM_0,
 988   PREFIX_0F01_REG_5_MOD_3_RM_1,
 989   PREFIX_0F01_REG_5_MOD_3_RM_2,
 990   PREFIX_0F01_REG_5_MOD_3_RM_4,
 991   PREFIX_0F01_REG_5_MOD_3_RM_5,
 992   PREFIX_0F01_REG_5_MOD_3_RM_6,
 993   PREFIX_0F01_REG_5_MOD_3_RM_7,
 994   PREFIX_0F01_REG_7_MOD_3_RM_2,
 995   PREFIX_0F01_REG_7_MOD_3_RM_5,
 996   PREFIX_0F01_REG_7_MOD_3_RM_6,
 997   PREFIX_0F01_REG_7_MOD_3_RM_7,
 998   PREFIX_0F09,
 999   PREFIX_0F10,
1000   PREFIX_0F11,
1001   PREFIX_0F12,
1002   PREFIX_0F16,
1003   PREFIX_0F18_REG_6_MOD_0_X86_64,
1004   PREFIX_0F18_REG_7_MOD_0_X86_64,
1005   PREFIX_0F1A,
1006   PREFIX_0F1B,
1007   PREFIX_0F1C,
1008   PREFIX_0F1E,
1009   PREFIX_0F2A,
1010   PREFIX_0F2B,
1011   PREFIX_0F2C,
1012   PREFIX_0F2D,
1013   PREFIX_0F2E,
1014   PREFIX_0F2F,
1015   PREFIX_0F51,
1016   PREFIX_0F52,
1017   PREFIX_0F53,
1018   PREFIX_0F58,
1019   PREFIX_0F59,
1020   PREFIX_0F5A,
1021   PREFIX_0F5B,
1022   PREFIX_0F5C,
1023   PREFIX_0F5D,
1024   PREFIX_0F5E,
1025   PREFIX_0F5F,
1026   PREFIX_0F60,
1027   PREFIX_0F61,
1028   PREFIX_0F62,
1029   PREFIX_0F6F,
1030   PREFIX_0F70,
1031   PREFIX_0F78,
1032   PREFIX_0F79,
1033   PREFIX_0F7C,
1034   PREFIX_0F7D,
1035   PREFIX_0F7E,
1036   PREFIX_0F7F,
1037   PREFIX_0FAE_REG_0_MOD_3,
1038   PREFIX_0FAE_REG_1_MOD_3,
1039   PREFIX_0FAE_REG_2_MOD_3,
1040   PREFIX_0FAE_REG_3_MOD_3,
1041   PREFIX_0FAE_REG_4_MOD_0,
1042   PREFIX_0FAE_REG_4_MOD_3,
1043   PREFIX_0FAE_REG_5_MOD_3,
1044   PREFIX_0FAE_REG_6_MOD_0,
1045   PREFIX_0FAE_REG_6_MOD_3,
1046   PREFIX_0FAE_REG_7_MOD_0,
1047   PREFIX_0FB8,
1048   PREFIX_0FBC,
1049   PREFIX_0FBD,
1050   PREFIX_0FC2,
1051   PREFIX_0FC7_REG_6_MOD_0,
1052   PREFIX_0FC7_REG_6_MOD_3,
1053   PREFIX_0FC7_REG_7_MOD_3,
1054   PREFIX_0FD0,
1055   PREFIX_0FD6,
1056   PREFIX_0FE6,
1057   PREFIX_0FE7,
1058   PREFIX_0FF0,
1059   PREFIX_0FF7,
1060   PREFIX_0F38D8,
1061   PREFIX_0F38DC,
1062   PREFIX_0F38DD,
1063   PREFIX_0F38DE,
1064   PREFIX_0F38DF,
1065   PREFIX_0F38F0,
1066   PREFIX_0F38F1,
1067   PREFIX_0F38F6,
1068   PREFIX_0F38F8_M_0,
1069   PREFIX_0F38F8_M_1_X86_64,
1070   PREFIX_0F38FA,
1071   PREFIX_0F38FB,
1072   PREFIX_0F38FC,
1073   PREFIX_0F3A0F,
1074   PREFIX_VEX_0F12,
1075   PREFIX_VEX_0F16,
1076   PREFIX_VEX_0F2A,
1077   PREFIX_VEX_0F2C,
1078   PREFIX_VEX_0F2D,
1079   PREFIX_VEX_0F41_L_1_W_0,
1080   PREFIX_VEX_0F41_L_1_W_1,
1081   PREFIX_VEX_0F42_L_1_W_0,
1082   PREFIX_VEX_0F42_L_1_W_1,
1083   PREFIX_VEX_0F44_L_0_W_0,
1084   PREFIX_VEX_0F44_L_0_W_1,
1085   PREFIX_VEX_0F45_L_1_W_0,
1086   PREFIX_VEX_0F45_L_1_W_1,
1087   PREFIX_VEX_0F46_L_1_W_0,
1088   PREFIX_VEX_0F46_L_1_W_1,
1089   PREFIX_VEX_0F47_L_1_W_0,
1090   PREFIX_VEX_0F47_L_1_W_1,
1091   PREFIX_VEX_0F4A_L_1_W_0,
1092   PREFIX_VEX_0F4A_L_1_W_1,
1093   PREFIX_VEX_0F4B_L_1_W_0,
1094   PREFIX_VEX_0F4B_L_1_W_1,
1095   PREFIX_VEX_0F6F,
1096   PREFIX_VEX_0F70,
1097   PREFIX_VEX_0F7E,
1098   PREFIX_VEX_0F7F,
1099   PREFIX_VEX_0F90_L_0_W_0,
1100   PREFIX_VEX_0F90_L_0_W_1,
1101   PREFIX_VEX_0F91_L_0_W_0,
1102   PREFIX_VEX_0F91_L_0_W_1,
1103   PREFIX_VEX_0F92_L_0_W_0,
1104   PREFIX_VEX_0F92_L_0_W_1,
1105   PREFIX_VEX_0F93_L_0_W_0,
1106   PREFIX_VEX_0F93_L_0_W_1,
1107   PREFIX_VEX_0F98_L_0_W_0,
1108   PREFIX_VEX_0F98_L_0_W_1,
1109   PREFIX_VEX_0F99_L_0_W_0,
1110   PREFIX_VEX_0F99_L_0_W_1,
1111   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0,
1112   PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1,
1113   PREFIX_VEX_0F384B_X86_64_L_0_W_0,
1114   PREFIX_VEX_0F3850_W_0,
1115   PREFIX_VEX_0F3851_W_0,
1116   PREFIX_VEX_0F385C_X86_64_L_0_W_0,
1117   PREFIX_VEX_0F385E_X86_64_L_0_W_0,
1118   PREFIX_VEX_0F386C_X86_64_L_0_W_0,
1119   PREFIX_VEX_0F3872,
1120   PREFIX_VEX_0F38B0_W_0,
1121   PREFIX_VEX_0F38B1_W_0,
1122   PREFIX_VEX_0F38D2_W_0,
1123   PREFIX_VEX_0F38D3_W_0,
1124   PREFIX_VEX_0F38CB,
1125   PREFIX_VEX_0F38CC,
1126   PREFIX_VEX_0F38CD,
1127   PREFIX_VEX_0F38DA_W_0,
1128   PREFIX_VEX_0F38F2_L_0,
1129   PREFIX_VEX_0F38F3_L_0,
1130   PREFIX_VEX_0F38F5_L_0,
1131   PREFIX_VEX_0F38F6_L_0,
1132   PREFIX_VEX_0F38F7_L_0,
1133   PREFIX_VEX_0F3AF0_L_0,
1134   PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64,
1135
1136   PREFIX_EVEX_0F5B,
1137   PREFIX_EVEX_0F6F,
1138   PREFIX_EVEX_0F70,
1139   PREFIX_EVEX_0F78,
1140   PREFIX_EVEX_0F79,
1141   PREFIX_EVEX_0F7A,
1142   PREFIX_EVEX_0F7B,
1143   PREFIX_EVEX_0F7E,
1144   PREFIX_EVEX_0F7F,
1145   PREFIX_EVEX_0FC2,
1146   PREFIX_EVEX_0FE6,
1147   PREFIX_EVEX_0F3810,
1148   PREFIX_EVEX_0F3811,
1149   PREFIX_EVEX_0F3812,
1150   PREFIX_EVEX_0F3813,
1151   PREFIX_EVEX_0F3814,
1152   PREFIX_EVEX_0F3815,
1153   PREFIX_EVEX_0F3820,
1154   PREFIX_EVEX_0F3821,
1155   PREFIX_EVEX_0F3822,
1156   PREFIX_EVEX_0F3823,
1157   PREFIX_EVEX_0F3824,
1158   PREFIX_EVEX_0F3825,
1159   PREFIX_EVEX_0F3826,
1160   PREFIX_EVEX_0F3827,
1161   PREFIX_EVEX_0F3828,
1162   PREFIX_EVEX_0F3829,
1163   PREFIX_EVEX_0F382A,
1164   PREFIX_EVEX_0F3830,
1165   PREFIX_EVEX_0F3831,
1166   PREFIX_EVEX_0F3832,
1167   PREFIX_EVEX_0F3833,
1168   PREFIX_EVEX_0F3834,
1169   PREFIX_EVEX_0F3835,
1170   PREFIX_EVEX_0F3838,
1171   PREFIX_EVEX_0F3839,
1172   PREFIX_EVEX_0F383A,
1173   PREFIX_EVEX_0F3852,
1174   PREFIX_EVEX_0F3853,
1175   PREFIX_EVEX_0F3868,
1176   PREFIX_EVEX_0F3872,
1177   PREFIX_EVEX_0F389A,
1178   PREFIX_EVEX_0F389B,
1179   PREFIX_EVEX_0F38AA,
1180   PREFIX_EVEX_0F38AB,
1181
1182   PREFIX_EVEX_0F3A08,
1183   PREFIX_EVEX_0F3A0A,
1184   PREFIX_EVEX_0F3A26,
1185   PREFIX_EVEX_0F3A27,
1186   PREFIX_EVEX_0F3A56,
1187   PREFIX_EVEX_0F3A57,
1188   PREFIX_EVEX_0F3A66,
1189   PREFIX_EVEX_0F3A67,
1190   PREFIX_EVEX_0F3AC2,
1191
1192   PREFIX_EVEX_MAP4_D8,
1193   PREFIX_EVEX_MAP4_DA,
1194   PREFIX_EVEX_MAP4_DB,
1195   PREFIX_EVEX_MAP4_DC,
1196   PREFIX_EVEX_MAP4_DD,
1197   PREFIX_EVEX_MAP4_DE,
1198   PREFIX_EVEX_MAP4_DF,
1199   PREFIX_EVEX_MAP4_F0,
1200   PREFIX_EVEX_MAP4_F1,
1201   PREFIX_EVEX_MAP4_F2,
1202   PREFIX_EVEX_MAP4_F8,
1203
1204   PREFIX_EVEX_MAP5_10,
1205   PREFIX_EVEX_MAP5_11,
1206   PREFIX_EVEX_MAP5_1D,
1207   PREFIX_EVEX_MAP5_2A,
1208   PREFIX_EVEX_MAP5_2C,
1209   PREFIX_EVEX_MAP5_2D,
1210   PREFIX_EVEX_MAP5_2E,
1211   PREFIX_EVEX_MAP5_2F,
1212   PREFIX_EVEX_MAP5_51,
1213   PREFIX_EVEX_MAP5_58,
1214   PREFIX_EVEX_MAP5_59,
1215   PREFIX_EVEX_MAP5_5A,
1216   PREFIX_EVEX_MAP5_5B,
1217   PREFIX_EVEX_MAP5_5C,
1218   PREFIX_EVEX_MAP5_5D,
1219   PREFIX_EVEX_MAP5_5E,
1220   PREFIX_EVEX_MAP5_5F,
1221   PREFIX_EVEX_MAP5_78,
1222   PREFIX_EVEX_MAP5_79,
1223   PREFIX_EVEX_MAP5_7A,
1224   PREFIX_EVEX_MAP5_7B,
1225   PREFIX_EVEX_MAP5_7C,
1226   PREFIX_EVEX_MAP5_7D,
1227
1228   PREFIX_EVEX_MAP6_13,
1229   PREFIX_EVEX_MAP6_56,
1230   PREFIX_EVEX_MAP6_57,
1231   PREFIX_EVEX_MAP6_D6,
1232   PREFIX_EVEX_MAP6_D7,
1233 };
1234
1235 enum
1236 {
1237   X86_64_06 = 0,
1238   X86_64_07,
1239   X86_64_0E,
1240   X86_64_16,
1241   X86_64_17,
1242   X86_64_1E,
1243   X86_64_1F,
1244   X86_64_27,
1245   X86_64_2F,
1246   X86_64_37,
1247   X86_64_3F,
1248   X86_64_60,
1249   X86_64_61,
1250   X86_64_62,
1251   X86_64_63,
1252   X86_64_6D,
1253   X86_64_6F,
1254   X86_64_82,
1255   X86_64_9A,
1256   X86_64_C2,
1257   X86_64_C3,
1258   X86_64_C4,
1259   X86_64_C5,
1260   X86_64_CE,
1261   X86_64_D4,
1262   X86_64_D5,
1263   X86_64_E8,
1264   X86_64_E9,
1265   X86_64_EA,
1266   X86_64_0F00_REG_6,
1267   X86_64_0F01_REG_0,
1268   X86_64_0F01_REG_0_MOD_3_RM_6_P_1,
1269   X86_64_0F01_REG_0_MOD_3_RM_6_P_3,
1270   X86_64_0F01_REG_0_MOD_3_RM_7_P_0,
1271   X86_64_0F01_REG_1,
1272   X86_64_0F01_REG_1_RM_2_PREFIX_1,
1273   X86_64_0F01_REG_1_RM_2_PREFIX_3,
1274   X86_64_0F01_REG_1_RM_5_PREFIX_2,
1275   X86_64_0F01_REG_1_RM_6_PREFIX_2,
1276   X86_64_0F01_REG_1_RM_7_PREFIX_2,
1277   X86_64_0F01_REG_2,
1278   X86_64_0F01_REG_3,
1279   X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1,
1280   X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1,
1281   X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1,
1282   X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1,
1283   X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1,
1284   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1,
1285   X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3,
1286   X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1,
1287   X86_64_0F18_REG_6_MOD_0,
1288   X86_64_0F18_REG_7_MOD_0,
1289   X86_64_0F24,
1290   X86_64_0F26,
1291   X86_64_0F38F8_M_1,
1292   X86_64_0FC7_REG_6_MOD_3_PREFIX_1,
1293
1294   X86_64_VEX_0F3849,
1295   X86_64_VEX_0F384B,
1296   X86_64_VEX_0F385C,
1297   X86_64_VEX_0F385E,
1298   X86_64_VEX_0F386C,
1299   X86_64_VEX_0F38E0,
1300   X86_64_VEX_0F38E1,
1301   X86_64_VEX_0F38E2,
1302   X86_64_VEX_0F38E3,
1303   X86_64_VEX_0F38E4,
1304   X86_64_VEX_0F38E5,
1305   X86_64_VEX_0F38E6,
1306   X86_64_VEX_0F38E7,
1307   X86_64_VEX_0F38E8,
1308   X86_64_VEX_0F38E9,
1309   X86_64_VEX_0F38EA,
1310   X86_64_VEX_0F38EB,
1311   X86_64_VEX_0F38EC,
1312   X86_64_VEX_0F38ED,
1313   X86_64_VEX_0F38EE,
1314   X86_64_VEX_0F38EF,
1315
1316   X86_64_VEX_MAP7_F8_L_0_W_0_R_0,
1317
1318   X86_64_EVEX_0F90,
1319   X86_64_EVEX_0F91,
1320   X86_64_EVEX_0F92,
1321   X86_64_EVEX_0F93,
1322   X86_64_EVEX_0F38F2,
1323   X86_64_EVEX_0F38F3,
1324   X86_64_EVEX_0F38F5,
1325   X86_64_EVEX_0F38F6,
1326   X86_64_EVEX_0F38F7,
1327   X86_64_EVEX_0F3AF0,
1328 };
1329
1330 enum
1331 {
1332   THREE_BYTE_0F38 = 0,
1333   THREE_BYTE_0F3A
1334 };
1335
1336 enum
1337 {
1338   XOP_08 = 0,
1339   XOP_09,
1340   XOP_0A
1341 };
1342
1343 enum
1344 {
1345   VEX_0F = 0,
1346   VEX_0F38,
1347   VEX_0F3A,
1348   VEX_MAP7,
1349 };
1350
1351 enum
1352 {
1353   EVEX_0F = 0,
1354   EVEX_0F38,
1355   EVEX_0F3A,
1356   EVEX_MAP4,
1357   EVEX_MAP5,
1358   EVEX_MAP6,
1359 };
1360
1361 enum
1362 {
1363   VEX_LEN_0F12_P_0 = 0,
1364   VEX_LEN_0F12_P_2,
1365   VEX_LEN_0F13,
1366   VEX_LEN_0F16_P_0,
1367   VEX_LEN_0F16_P_2,
1368   VEX_LEN_0F17,
1369   VEX_LEN_0F41,
1370   VEX_LEN_0F42,
1371   VEX_LEN_0F44,
1372   VEX_LEN_0F45,
1373   VEX_LEN_0F46,
1374   VEX_LEN_0F47,
1375   VEX_LEN_0F4A,
1376   VEX_LEN_0F4B,
1377   VEX_LEN_0F6E,
1378   VEX_LEN_0F77,
1379   VEX_LEN_0F7E_P_1,
1380   VEX_LEN_0F7E_P_2,
1381   VEX_LEN_0F90,
1382   VEX_LEN_0F91,
1383   VEX_LEN_0F92,
1384   VEX_LEN_0F93,
1385   VEX_LEN_0F98,
1386   VEX_LEN_0F99,
1387   VEX_LEN_0FAE_R_2,
1388   VEX_LEN_0FAE_R_3,
1389   VEX_LEN_0FC4,
1390   VEX_LEN_0FD6,
1391   VEX_LEN_0F3816,
1392   VEX_LEN_0F3819,
1393   VEX_LEN_0F381A,
1394   VEX_LEN_0F3836,
1395   VEX_LEN_0F3841,
1396   VEX_LEN_0F3849_X86_64,
1397   VEX_LEN_0F384B_X86_64,
1398   VEX_LEN_0F385A,
1399   VEX_LEN_0F385C_X86_64,
1400   VEX_LEN_0F385E_X86_64,
1401   VEX_LEN_0F386C_X86_64,
1402   VEX_LEN_0F38CB_P_3_W_0,
1403   VEX_LEN_0F38CC_P_3_W_0,
1404   VEX_LEN_0F38CD_P_3_W_0,
1405   VEX_LEN_0F38DA_W_0_P_0,
1406   VEX_LEN_0F38DA_W_0_P_2,
1407   VEX_LEN_0F38DB,
1408   VEX_LEN_0F38F2,
1409   VEX_LEN_0F38F3,
1410   VEX_LEN_0F38F5,
1411   VEX_LEN_0F38F6,
1412   VEX_LEN_0F38F7,
1413   VEX_LEN_0F3A00,
1414   VEX_LEN_0F3A01,
1415   VEX_LEN_0F3A06,
1416   VEX_LEN_0F3A14,
1417   VEX_LEN_0F3A15,
1418   VEX_LEN_0F3A16,
1419   VEX_LEN_0F3A17,
1420   VEX_LEN_0F3A18,
1421   VEX_LEN_0F3A19,
1422   VEX_LEN_0F3A20,
1423   VEX_LEN_0F3A21,
1424   VEX_LEN_0F3A22,
1425   VEX_LEN_0F3A30,
1426   VEX_LEN_0F3A31,
1427   VEX_LEN_0F3A32,
1428   VEX_LEN_0F3A33,
1429   VEX_LEN_0F3A38,
1430   VEX_LEN_0F3A39,
1431   VEX_LEN_0F3A41,
1432   VEX_LEN_0F3A46,
1433   VEX_LEN_0F3A60,
1434   VEX_LEN_0F3A61,
1435   VEX_LEN_0F3A62,
1436   VEX_LEN_0F3A63,
1437   VEX_LEN_0F3ADE_W_0,
1438   VEX_LEN_0F3ADF,
1439   VEX_LEN_0F3AF0,
1440   VEX_LEN_MAP7_F8,
1441   VEX_LEN_XOP_08_85,
1442   VEX_LEN_XOP_08_86,
1443   VEX_LEN_XOP_08_87,
1444   VEX_LEN_XOP_08_8E,
1445   VEX_LEN_XOP_08_8F,
1446   VEX_LEN_XOP_08_95,
1447   VEX_LEN_XOP_08_96,
1448   VEX_LEN_XOP_08_97,
1449   VEX_LEN_XOP_08_9E,
1450   VEX_LEN_XOP_08_9F,
1451   VEX_LEN_XOP_08_A3,
1452   VEX_LEN_XOP_08_A6,
1453   VEX_LEN_XOP_08_B6,
1454   VEX_LEN_XOP_08_C0,
1455   VEX_LEN_XOP_08_C1,
1456   VEX_LEN_XOP_08_C2,
1457   VEX_LEN_XOP_08_C3,
1458   VEX_LEN_XOP_08_CC,
1459   VEX_LEN_XOP_08_CD,
1460   VEX_LEN_XOP_08_CE,
1461   VEX_LEN_XOP_08_CF,
1462   VEX_LEN_XOP_08_EC,
1463   VEX_LEN_XOP_08_ED,
1464   VEX_LEN_XOP_08_EE,
1465   VEX_LEN_XOP_08_EF,
1466   VEX_LEN_XOP_09_01,
1467   VEX_LEN_XOP_09_02,
1468   VEX_LEN_XOP_09_12,
1469   VEX_LEN_XOP_09_82_W_0,
1470   VEX_LEN_XOP_09_83_W_0,
1471   VEX_LEN_XOP_09_90,
1472   VEX_LEN_XOP_09_91,
1473   VEX_LEN_XOP_09_92,
1474   VEX_LEN_XOP_09_93,
1475   VEX_LEN_XOP_09_94,
1476   VEX_LEN_XOP_09_95,
1477   VEX_LEN_XOP_09_96,
1478   VEX_LEN_XOP_09_97,
1479   VEX_LEN_XOP_09_98,
1480   VEX_LEN_XOP_09_99,
1481   VEX_LEN_XOP_09_9A,
1482   VEX_LEN_XOP_09_9B,
1483   VEX_LEN_XOP_09_C1,
1484   VEX_LEN_XOP_09_C2,
1485   VEX_LEN_XOP_09_C3,
1486   VEX_LEN_XOP_09_C6,
1487   VEX_LEN_XOP_09_C7,
1488   VEX_LEN_XOP_09_CB,
1489   VEX_LEN_XOP_09_D1,
1490   VEX_LEN_XOP_09_D2,
1491   VEX_LEN_XOP_09_D3,
1492   VEX_LEN_XOP_09_D6,
1493   VEX_LEN_XOP_09_D7,
1494   VEX_LEN_XOP_09_DB,
1495   VEX_LEN_XOP_09_E1,
1496   VEX_LEN_XOP_09_E2,
1497   VEX_LEN_XOP_09_E3,
1498   VEX_LEN_XOP_0A_12,
1499 };
1500
1501 enum
1502 {
1503   EVEX_LEN_0F3816 = 0,
1504   EVEX_LEN_0F3819,
1505   EVEX_LEN_0F381A,
1506   EVEX_LEN_0F381B,
1507   EVEX_LEN_0F3836,
1508   EVEX_LEN_0F385A,
1509   EVEX_LEN_0F385B,
1510   EVEX_LEN_0F38C6,
1511   EVEX_LEN_0F38C7,
1512   EVEX_LEN_0F3A00,
1513   EVEX_LEN_0F3A01,
1514   EVEX_LEN_0F3A18,
1515   EVEX_LEN_0F3A19,
1516   EVEX_LEN_0F3A1A,
1517   EVEX_LEN_0F3A1B,
1518   EVEX_LEN_0F3A23,
1519   EVEX_LEN_0F3A38,
1520   EVEX_LEN_0F3A39,
1521   EVEX_LEN_0F3A3A,
1522   EVEX_LEN_0F3A3B,
1523   EVEX_LEN_0F3A43
1524 };
1525
1526 enum
1527 {
1528   VEX_W_0F41_L_1 = 0,
1529   VEX_W_0F42_L_1,
1530   VEX_W_0F44_L_0,
1531   VEX_W_0F45_L_1,
1532   VEX_W_0F46_L_1,
1533   VEX_W_0F47_L_1,
1534   VEX_W_0F4A_L_1,
1535   VEX_W_0F4B_L_1,
1536   VEX_W_0F90_L_0,
1537   VEX_W_0F91_L_0,
1538   VEX_W_0F92_L_0,
1539   VEX_W_0F93_L_0,
1540   VEX_W_0F98_L_0,
1541   VEX_W_0F99_L_0,
1542   VEX_W_0F380C,
1543   VEX_W_0F380D,
1544   VEX_W_0F380E,
1545   VEX_W_0F380F,
1546   VEX_W_0F3813,
1547   VEX_W_0F3816_L_1,
1548   VEX_W_0F3818,
1549   VEX_W_0F3819_L_1,
1550   VEX_W_0F381A_L_1,
1551   VEX_W_0F382C,
1552   VEX_W_0F382D,
1553   VEX_W_0F382E,
1554   VEX_W_0F382F,
1555   VEX_W_0F3836,
1556   VEX_W_0F3846,
1557   VEX_W_0F3849_X86_64_L_0,
1558   VEX_W_0F384B_X86_64_L_0,
1559   VEX_W_0F3850,
1560   VEX_W_0F3851,
1561   VEX_W_0F3852,
1562   VEX_W_0F3853,
1563   VEX_W_0F3858,
1564   VEX_W_0F3859,
1565   VEX_W_0F385A_L_0,
1566   VEX_W_0F385C_X86_64_L_0,
1567   VEX_W_0F385E_X86_64_L_0,
1568   VEX_W_0F386C_X86_64_L_0,
1569   VEX_W_0F3872_P_1,
1570   VEX_W_0F3878,
1571   VEX_W_0F3879,
1572   VEX_W_0F38B0,
1573   VEX_W_0F38B1,
1574   VEX_W_0F38B4,
1575   VEX_W_0F38B5,
1576   VEX_W_0F38CB_P_3,
1577   VEX_W_0F38CC_P_3,
1578   VEX_W_0F38CD_P_3,
1579   VEX_W_0F38CF,
1580   VEX_W_0F38D2,
1581   VEX_W_0F38D3,
1582   VEX_W_0F38DA,
1583   VEX_W_0F3A00_L_1,
1584   VEX_W_0F3A01_L_1,
1585   VEX_W_0F3A02,
1586   VEX_W_0F3A04,
1587   VEX_W_0F3A05,
1588   VEX_W_0F3A06_L_1,
1589   VEX_W_0F3A18_L_1,
1590   VEX_W_0F3A19_L_1,
1591   VEX_W_0F3A1D,
1592   VEX_W_0F3A38_L_1,
1593   VEX_W_0F3A39_L_1,
1594   VEX_W_0F3A46_L_1,
1595   VEX_W_0F3A4A,
1596   VEX_W_0F3A4B,
1597   VEX_W_0F3A4C,
1598   VEX_W_0F3ACE,
1599   VEX_W_0F3ACF,
1600   VEX_W_0F3ADE,
1601   VEX_W_MAP7_F8_L_0,
1602
1603   VEX_W_XOP_08_85_L_0,
1604   VEX_W_XOP_08_86_L_0,
1605   VEX_W_XOP_08_87_L_0,
1606   VEX_W_XOP_08_8E_L_0,
1607   VEX_W_XOP_08_8F_L_0,
1608   VEX_W_XOP_08_95_L_0,
1609   VEX_W_XOP_08_96_L_0,
1610   VEX_W_XOP_08_97_L_0,
1611   VEX_W_XOP_08_9E_L_0,
1612   VEX_W_XOP_08_9F_L_0,
1613   VEX_W_XOP_08_A6_L_0,
1614   VEX_W_XOP_08_B6_L_0,
1615   VEX_W_XOP_08_C0_L_0,
1616   VEX_W_XOP_08_C1_L_0,
1617   VEX_W_XOP_08_C2_L_0,
1618   VEX_W_XOP_08_C3_L_0,
1619   VEX_W_XOP_08_CC_L_0,
1620   VEX_W_XOP_08_CD_L_0,
1621   VEX_W_XOP_08_CE_L_0,
1622   VEX_W_XOP_08_CF_L_0,
1623   VEX_W_XOP_08_EC_L_0,
1624   VEX_W_XOP_08_ED_L_0,
1625   VEX_W_XOP_08_EE_L_0,
1626   VEX_W_XOP_08_EF_L_0,
1627
1628   VEX_W_XOP_09_80,
1629   VEX_W_XOP_09_81,
1630   VEX_W_XOP_09_82,
1631   VEX_W_XOP_09_83,
1632   VEX_W_XOP_09_C1_L_0,
1633   VEX_W_XOP_09_C2_L_0,
1634   VEX_W_XOP_09_C3_L_0,
1635   VEX_W_XOP_09_C6_L_0,
1636   VEX_W_XOP_09_C7_L_0,
1637   VEX_W_XOP_09_CB_L_0,
1638   VEX_W_XOP_09_D1_L_0,
1639   VEX_W_XOP_09_D2_L_0,
1640   VEX_W_XOP_09_D3_L_0,
1641   VEX_W_XOP_09_D6_L_0,
1642   VEX_W_XOP_09_D7_L_0,
1643   VEX_W_XOP_09_DB_L_0,
1644   VEX_W_XOP_09_E1_L_0,
1645   VEX_W_XOP_09_E2_L_0,
1646   VEX_W_XOP_09_E3_L_0,
1647
1648   EVEX_W_0F5B_P_0,
1649   EVEX_W_0F62,
1650   EVEX_W_0F66,
1651   EVEX_W_0F6A,
1652   EVEX_W_0F6B,
1653   EVEX_W_0F6C,
1654   EVEX_W_0F6D,
1655   EVEX_W_0F6F_P_1,
1656   EVEX_W_0F6F_P_2,
1657   EVEX_W_0F6F_P_3,
1658   EVEX_W_0F70_P_2,
1659   EVEX_W_0F72_R_2,
1660   EVEX_W_0F72_R_6,
1661   EVEX_W_0F73_R_2,
1662   EVEX_W_0F73_R_6,
1663   EVEX_W_0F76,
1664   EVEX_W_0F78_P_0,
1665   EVEX_W_0F78_P_2,
1666   EVEX_W_0F79_P_0,
1667   EVEX_W_0F79_P_2,
1668   EVEX_W_0F7A_P_1,
1669   EVEX_W_0F7A_P_2,
1670   EVEX_W_0F7A_P_3,
1671   EVEX_W_0F7B_P_2,
1672   EVEX_W_0F7E_P_1,
1673   EVEX_W_0F7F_P_1,
1674   EVEX_W_0F7F_P_2,
1675   EVEX_W_0F7F_P_3,
1676   EVEX_W_0FD2,
1677   EVEX_W_0FD3,
1678   EVEX_W_0FD4,
1679   EVEX_W_0FD6,
1680   EVEX_W_0FE6_P_1,
1681   EVEX_W_0FE7,
1682   EVEX_W_0FF2,
1683   EVEX_W_0FF3,
1684   EVEX_W_0FF4,
1685   EVEX_W_0FFA,
1686   EVEX_W_0FFB,
1687   EVEX_W_0FFE,
1688
1689   EVEX_W_0F3810_P_1,
1690   EVEX_W_0F3810_P_2,
1691   EVEX_W_0F3811_P_1,
1692   EVEX_W_0F3811_P_2,
1693   EVEX_W_0F3812_P_1,
1694   EVEX_W_0F3812_P_2,
1695   EVEX_W_0F3813_P_1,
1696   EVEX_W_0F3814_P_1,
1697   EVEX_W_0F3815_P_1,
1698   EVEX_W_0F3819_L_n,
1699   EVEX_W_0F381A_L_n,
1700   EVEX_W_0F381B_L_2,
1701   EVEX_W_0F381E,
1702   EVEX_W_0F381F,
1703   EVEX_W_0F3820_P_1,
1704   EVEX_W_0F3821_P_1,
1705   EVEX_W_0F3822_P_1,
1706   EVEX_W_0F3823_P_1,
1707   EVEX_W_0F3824_P_1,
1708   EVEX_W_0F3825_P_1,
1709   EVEX_W_0F3825_P_2,
1710   EVEX_W_0F3828_P_2,
1711   EVEX_W_0F3829_P_2,
1712   EVEX_W_0F382A_P_1,
1713   EVEX_W_0F382A_P_2,
1714   EVEX_W_0F382B,
1715   EVEX_W_0F3830_P_1,
1716   EVEX_W_0F3831_P_1,
1717   EVEX_W_0F3832_P_1,
1718   EVEX_W_0F3833_P_1,
1719   EVEX_W_0F3834_P_1,
1720   EVEX_W_0F3835_P_1,
1721   EVEX_W_0F3835_P_2,
1722   EVEX_W_0F3837,
1723   EVEX_W_0F383A_P_1,
1724   EVEX_W_0F3859,
1725   EVEX_W_0F385A_L_n,
1726   EVEX_W_0F385B_L_2,
1727   EVEX_W_0F3870,
1728   EVEX_W_0F3872_P_2,
1729   EVEX_W_0F387A,
1730   EVEX_W_0F387B,
1731   EVEX_W_0F3883,
1732
1733   EVEX_W_0F3A18_L_n,
1734   EVEX_W_0F3A19_L_n,
1735   EVEX_W_0F3A1A_L_2,
1736   EVEX_W_0F3A1B_L_2,
1737   EVEX_W_0F3A21,
1738   EVEX_W_0F3A23_L_n,
1739   EVEX_W_0F3A38_L_n,
1740   EVEX_W_0F3A39_L_n,
1741   EVEX_W_0F3A3A_L_2,
1742   EVEX_W_0F3A3B_L_2,
1743   EVEX_W_0F3A42,
1744   EVEX_W_0F3A43_L_n,
1745   EVEX_W_0F3A70,
1746   EVEX_W_0F3A72,
1747
1748   EVEX_W_MAP4_8F_R_0,
1749   EVEX_W_MAP4_FF_R_6,
1750
1751   EVEX_W_MAP5_5B_P_0,
1752   EVEX_W_MAP5_7A_P_3,
1753 };
1754
1755 typedef bool (*op_rtn) (instr_info *ins, int bytemode, int sizeflag);
1756
1757 struct dis386 {
1758   const char *name;
1759   struct
1760     {
1761       op_rtn rtn;
1762       int bytemode;
1763     } op[MAX_OPERANDS];
1764   unsigned int prefix_requirement;
1765 };
1766
1767 /* Upper case letters in the instruction names here are macros.
1768    'A' => print 'b' if no register operands or suffix_always is true
1769    'B' => print 'b' if suffix_always is true
1770    'C' => print 's' or 'l' ('w' or 'd' in Intel mode) depending on operand
1771           size prefix
1772    'D' => print 'w' if no register operands or 'w', 'l' or 'q', if
1773           suffix_always is true
1774    'E' => print 'e' if 32-bit form of jcxz
1775    'F' => print 'w' or 'l' depending on address size prefix (loop insns)
1776    'G' => print 'w' or 'l' depending on operand size prefix (i/o insns)
1777    'H' => print ",pt" or ",pn" branch hint
1778    'I' unused.
1779    'J' unused.
1780    'K' => print 'd' or 'q' if rex prefix is present.
1781    'L' => print 'l' or 'q' if suffix_always is true
1782    'M' => print 'r' if intel_mnemonic is false.
1783    'N' => print 'n' if instruction has no wait "prefix"
1784    'O' => print 'd' or 'o' (or 'q' in Intel mode)
1785    'P' => behave as 'T' except with register operand outside of suffix_always
1786           mode
1787    'Q' => print 'w', 'l' or 'q' for memory operand or suffix_always
1788           is true
1789    'R' => print 'w', 'l' or 'q' ('d' for 'l' and 'e' in Intel mode)
1790    'S' => print 'w', 'l' or 'q' if suffix_always is true
1791    'T' => print 'w', 'l'/'d', or 'q' if instruction has an operand size
1792           prefix or if suffix_always is true.
1793    'U' unused.
1794    'V' => print 'v' for VEX/EVEX and nothing for legacy encodings.
1795    'W' => print 'b', 'w' or 'l' ('d' in Intel mode)
1796    'X' => print 's', 'd' depending on data16 prefix (for XMM)
1797    'Y' => no output, mark EVEX.aaa != 0 as bad.
1798    'Z' => print 'q' in 64bit mode and 'l' otherwise, if suffix_always is true.
1799    '!' => change condition from true to false or from false to true.
1800    '%' => add 1 upper case letter to the macro.
1801    '^' => print 'w', 'l', or 'q' (Intel64 ISA only) depending on operand size
1802           prefix or suffix_always is true (lcall/ljmp).
1803    '@' => in 64bit mode for Intel64 ISA or if instruction
1804           has no operand sizing prefix, print 'q' if suffix_always is true or
1805           nothing otherwise; behave as 'P' in all other cases
1806
1807    2 upper case letter macros:
1808    "XY" => print 'x' or 'y' if suffix_always is true or no register
1809            operands and no broadcast.
1810    "XZ" => print 'x', 'y', or 'z' if suffix_always is true or no
1811            register operands and no broadcast.
1812    "XW" => print 's', 'd' depending on the VEX.W bit (for FMA)
1813    "XD" => print 'd' if !EVEX or EVEX.W=1, EVEX.W=0 is not a valid encoding
1814    "XH" => print 'h' if EVEX.W=0, EVEX.W=1 is not a valid encoding (for FP16)
1815    "XS" => print 's' if !EVEX or EVEX.W=0, EVEX.W=1 is not a valid encoding
1816    "XV" => print "{vex} " pseudo prefix
1817    "XE" => print "{evex} " pseudo prefix if no EVEX-specific functionality is
1818            is used by an EVEX-encoded (AVX512VL) instruction.
1819    "YK" keep unused, to avoid ambiguity with the combined use of Y and K.
1820    "YX" keep unused, to avoid ambiguity with the combined use of Y and X.
1821    "LQ" => print 'l' ('d' in Intel mode) or 'q' for memory operand, cond
1822            being false, or no operand at all in 64bit mode, or if suffix_always
1823            is true.
1824    "LB" => print "abs" in 64bit mode and behave as 'B' otherwise
1825    "LS" => print "abs" in 64bit mode and behave as 'S' otherwise
1826    "LV" => print "abs" for 64bit operand and behave as 'S' otherwise
1827    "DQ" => print 'd' or 'q' depending on the VEX.W bit
1828    "BW" => print 'b' or 'w' depending on the VEX.W bit
1829    "LP" => print 'w' or 'l' ('d' in Intel mode) if instruction has
1830            an operand size prefix, or suffix_always is true.  print
1831            'q' if rex prefix is present.
1832
1833    Many of the above letters print nothing in Intel mode.  See "putop"
1834    for the details.
1835
1836    Braces '{' and '}', and vertical bars '|', indicate alternative
1837    mnemonic strings for AT&T and Intel.  */
1838
1839 static const struct dis386 dis386[] = {
1840   /* 00 */
1841   { "addB",             { Ebh1, Gb }, 0 },
1842   { "addS",             { Evh1, Gv }, 0 },
1843   { "addB",             { Gb, EbS }, 0 },
1844   { "addS",             { Gv, EvS }, 0 },
1845   { "addB",             { AL, Ib }, 0 },
1846   { "addS",             { eAX, Iv }, 0 },
1847   { X86_64_TABLE (X86_64_06) },
1848   { X86_64_TABLE (X86_64_07) },
1849   /* 08 */
1850   { "orB",              { Ebh1, Gb }, 0 },
1851   { "orS",              { Evh1, Gv }, 0 },
1852   { "orB",              { Gb, EbS }, 0 },
1853   { "orS",              { Gv, EvS }, 0 },
1854   { "orB",              { AL, Ib }, 0 },
1855   { "orS",              { eAX, Iv }, 0 },
1856   { X86_64_TABLE (X86_64_0E) },
1857   { Bad_Opcode },       /* 0x0f extended opcode escape */
1858   /* 10 */
1859   { "adcB",             { Ebh1, Gb }, 0 },
1860   { "adcS",             { Evh1, Gv }, 0 },
1861   { "adcB",             { Gb, EbS }, 0 },
1862   { "adcS",             { Gv, EvS }, 0 },
1863   { "adcB",             { AL, Ib }, 0 },
1864   { "adcS",             { eAX, Iv }, 0 },
1865   { X86_64_TABLE (X86_64_16) },
1866   { X86_64_TABLE (X86_64_17) },
1867   /* 18 */
1868   { "sbbB",             { Ebh1, Gb }, 0 },
1869   { "sbbS",             { Evh1, Gv }, 0 },
1870   { "sbbB",             { Gb, EbS }, 0 },
1871   { "sbbS",             { Gv, EvS }, 0 },
1872   { "sbbB",             { AL, Ib }, 0 },
1873   { "sbbS",             { eAX, Iv }, 0 },
1874   { X86_64_TABLE (X86_64_1E) },
1875   { X86_64_TABLE (X86_64_1F) },
1876   /* 20 */
1877   { "andB",             { Ebh1, Gb }, 0 },
1878   { "andS",             { Evh1, Gv }, 0 },
1879   { "andB",             { Gb, EbS }, 0 },
1880   { "andS",             { Gv, EvS }, 0 },
1881   { "andB",             { AL, Ib }, 0 },
1882   { "andS",             { eAX, Iv }, 0 },
1883   { Bad_Opcode },       /* SEG ES prefix */
1884   { X86_64_TABLE (X86_64_27) },
1885   /* 28 */
1886   { "subB",             { Ebh1, Gb }, 0 },
1887   { "subS",             { Evh1, Gv }, 0 },
1888   { "subB",             { Gb, EbS }, 0 },
1889   { "subS",             { Gv, EvS }, 0 },
1890   { "subB",             { AL, Ib }, 0 },
1891   { "subS",             { eAX, Iv }, 0 },
1892   { Bad_Opcode },       /* SEG CS prefix */
1893   { X86_64_TABLE (X86_64_2F) },
1894   /* 30 */
1895   { "xorB",             { Ebh1, Gb }, 0 },
1896   { "xorS",             { Evh1, Gv }, 0 },
1897   { "xorB",             { Gb, EbS }, 0 },
1898   { "xorS",             { Gv, EvS }, 0 },
1899   { "xorB",             { AL, Ib }, 0 },
1900   { "xorS",             { eAX, Iv }, 0 },
1901   { Bad_Opcode },       /* SEG SS prefix */
1902   { X86_64_TABLE (X86_64_37) },
1903   /* 38 */
1904   { "cmpB",             { Eb, Gb }, 0 },
1905   { "cmpS",             { Ev, Gv }, 0 },
1906   { "cmpB",             { Gb, EbS }, 0 },
1907   { "cmpS",             { Gv, EvS }, 0 },
1908   { "cmpB",             { AL, Ib }, 0 },
1909   { "cmpS",             { eAX, Iv }, 0 },
1910   { Bad_Opcode },       /* SEG DS prefix */
1911   { X86_64_TABLE (X86_64_3F) },
1912   /* 40 */
1913   { "inc{S|}",          { RMeAX }, 0 },
1914   { "inc{S|}",          { RMeCX }, 0 },
1915   { "inc{S|}",          { RMeDX }, 0 },
1916   { "inc{S|}",          { RMeBX }, 0 },
1917   { "inc{S|}",          { RMeSP }, 0 },
1918   { "inc{S|}",          { RMeBP }, 0 },
1919   { "inc{S|}",          { RMeSI }, 0 },
1920   { "inc{S|}",          { RMeDI }, 0 },
1921   /* 48 */
1922   { "dec{S|}",          { RMeAX }, 0 },
1923   { "dec{S|}",          { RMeCX }, 0 },
1924   { "dec{S|}",          { RMeDX }, 0 },
1925   { "dec{S|}",          { RMeBX }, 0 },
1926   { "dec{S|}",          { RMeSP }, 0 },
1927   { "dec{S|}",          { RMeBP }, 0 },
1928   { "dec{S|}",          { RMeSI }, 0 },
1929   { "dec{S|}",          { RMeDI }, 0 },
1930   /* 50 */
1931   { "push!P",           { RMrAX }, 0 },
1932   { "push!P",           { RMrCX }, 0 },
1933   { "push!P",           { RMrDX }, 0 },
1934   { "push!P",           { RMrBX }, 0 },
1935   { "push!P",           { RMrSP }, 0 },
1936   { "push!P",           { RMrBP }, 0 },
1937   { "push!P",           { RMrSI }, 0 },
1938   { "push!P",           { RMrDI }, 0 },
1939   /* 58 */
1940   { "pop!P",            { RMrAX }, 0 },
1941   { "pop!P",            { RMrCX }, 0 },
1942   { "pop!P",            { RMrDX }, 0 },
1943   { "pop!P",            { RMrBX }, 0 },
1944   { "pop!P",            { RMrSP }, 0 },
1945   { "pop!P",            { RMrBP }, 0 },
1946   { "pop!P",            { RMrSI }, 0 },
1947   { "pop!P",            { RMrDI }, 0 },
1948   /* 60 */
1949   { X86_64_TABLE (X86_64_60) },
1950   { X86_64_TABLE (X86_64_61) },
1951   { X86_64_TABLE (X86_64_62) },
1952   { X86_64_TABLE (X86_64_63) },
1953   { Bad_Opcode },       /* seg fs */
1954   { Bad_Opcode },       /* seg gs */
1955   { Bad_Opcode },       /* op size prefix */
1956   { Bad_Opcode },       /* adr size prefix */
1957   /* 68 */
1958   { "pushP",            { sIv }, 0 },
1959   { "imulS",            { Gv, Ev, Iv }, 0 },
1960   { "pushP",            { sIbT }, 0 },
1961   { "imulS",            { Gv, Ev, sIb }, 0 },
1962   { "ins{b|}",          { Ybr, indirDX }, 0 },
1963   { X86_64_TABLE (X86_64_6D) },
1964   { "outs{b|}",         { indirDXr, Xb }, 0 },
1965   { X86_64_TABLE (X86_64_6F) },
1966   /* 70 */
1967   { "joH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1968   { "jnoH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1969   { "jbH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1970   { "jaeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1971   { "jeH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1972   { "jneH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1973   { "jbeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1974   { "jaH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1975   /* 78 */
1976   { "jsH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1977   { "jnsH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1978   { "jpH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1979   { "jnpH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1980   { "jlH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1981   { "jgeH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1982   { "jleH",             { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1983   { "jgH",              { Jb, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
1984   /* 80 */
1985   { REG_TABLE (REG_80) },
1986   { REG_TABLE (REG_81) },
1987   { X86_64_TABLE (X86_64_82) },
1988   { REG_TABLE (REG_83) },
1989   { "testB",            { Eb, Gb }, 0 },
1990   { "testS",            { Ev, Gv }, 0 },
1991   { "xchgB",            { Ebh2, Gb }, 0 },
1992   { "xchgS",            { Evh2, Gv }, 0 },
1993   /* 88 */
1994   { "movB",             { Ebh3, Gb }, 0 },
1995   { "movS",             { Evh3, Gv }, 0 },
1996   { "movB",             { Gb, EbS }, 0 },
1997   { "movS",             { Gv, EvS }, 0 },
1998   { "movD",             { Sv, Sw }, 0 },
1999   { "leaS",             { Gv, M }, 0 },
2000   { "movD",             { Sw, Sv }, 0 },
2001   { REG_TABLE (REG_8F) },
2002   /* 90 */
2003   { PREFIX_TABLE (PREFIX_90) },
2004   { "xchgS",            { RMeCX, eAX }, 0 },
2005   { "xchgS",            { RMeDX, eAX }, 0 },
2006   { "xchgS",            { RMeBX, eAX }, 0 },
2007   { "xchgS",            { RMeSP, eAX }, 0 },
2008   { "xchgS",            { RMeBP, eAX }, 0 },
2009   { "xchgS",            { RMeSI, eAX }, 0 },
2010   { "xchgS",            { RMeDI, eAX }, 0 },
2011   /* 98 */
2012   { "cW{t|}R",          { XX }, 0 },
2013   { "cR{t|}O",          { XX }, 0 },
2014   { X86_64_TABLE (X86_64_9A) },
2015   { Bad_Opcode },       /* fwait */
2016   { "pushfP",           { XX }, 0 },
2017   { "popfP",            { XX }, 0 },
2018   { "sahf",             { XX }, 0 },
2019   { "lahf",             { XX }, 0 },
2020   /* a0 */
2021   { "mov%LB",           { AL, Ob }, PREFIX_REX2_ILLEGAL },
2022   { "mov%LS",           { { JMPABS_Fixup, eAX_reg }, { JMPABS_Fixup, v_mode } }, PREFIX_REX2_ILLEGAL },
2023   { "mov%LB",           { Ob, AL }, PREFIX_REX2_ILLEGAL },
2024   { "mov%LS",           { Ov, eAX }, PREFIX_REX2_ILLEGAL },
2025   { "movs{b|}",         { Ybr, Xb }, PREFIX_REX2_ILLEGAL },
2026   { "movs{R|}",         { Yvr, Xv }, PREFIX_REX2_ILLEGAL },
2027   { "cmps{b|}",         { Xb, Yb }, PREFIX_REX2_ILLEGAL },
2028   { "cmps{R|}",         { Xv, Yv }, PREFIX_REX2_ILLEGAL },
2029   /* a8 */
2030   { "testB",            { AL, Ib }, PREFIX_REX2_ILLEGAL },
2031   { "testS",            { eAX, Iv }, PREFIX_REX2_ILLEGAL },
2032   { "stosB",            { Ybr, AL }, PREFIX_REX2_ILLEGAL },
2033   { "stosS",            { Yvr, eAX }, PREFIX_REX2_ILLEGAL },
2034   { "lodsB",            { ALr, Xb }, PREFIX_REX2_ILLEGAL },
2035   { "lodsS",            { eAXr, Xv }, PREFIX_REX2_ILLEGAL },
2036   { "scasB",            { AL, Yb }, PREFIX_REX2_ILLEGAL },
2037   { "scasS",            { eAX, Yv }, PREFIX_REX2_ILLEGAL },
2038   /* b0 */
2039   { "movB",             { RMAL, Ib }, 0 },
2040   { "movB",             { RMCL, Ib }, 0 },
2041   { "movB",             { RMDL, Ib }, 0 },
2042   { "movB",             { RMBL, Ib }, 0 },
2043   { "movB",             { RMAH, Ib }, 0 },
2044   { "movB",             { RMCH, Ib }, 0 },
2045   { "movB",             { RMDH, Ib }, 0 },
2046   { "movB",             { RMBH, Ib }, 0 },
2047   /* b8 */
2048   { "mov%LV",           { RMeAX, Iv64 }, 0 },
2049   { "mov%LV",           { RMeCX, Iv64 }, 0 },
2050   { "mov%LV",           { RMeDX, Iv64 }, 0 },
2051   { "mov%LV",           { RMeBX, Iv64 }, 0 },
2052   { "mov%LV",           { RMeSP, Iv64 }, 0 },
2053   { "mov%LV",           { RMeBP, Iv64 }, 0 },
2054   { "mov%LV",           { RMeSI, Iv64 }, 0 },
2055   { "mov%LV",           { RMeDI, Iv64 }, 0 },
2056   /* c0 */
2057   { REG_TABLE (REG_C0) },
2058   { REG_TABLE (REG_C1) },
2059   { X86_64_TABLE (X86_64_C2) },
2060   { X86_64_TABLE (X86_64_C3) },
2061   { X86_64_TABLE (X86_64_C4) },
2062   { X86_64_TABLE (X86_64_C5) },
2063   { REG_TABLE (REG_C6) },
2064   { REG_TABLE (REG_C7) },
2065   /* c8 */
2066   { "enterP",           { Iw, Ib }, 0 },
2067   { "leaveP",           { XX }, 0 },
2068   { "{l|}ret{|f}%LP",   { Iw }, 0 },
2069   { "{l|}ret{|f}%LP",   { XX }, 0 },
2070   { "int3",             { XX }, 0 },
2071   { "int",              { Ib }, 0 },
2072   { X86_64_TABLE (X86_64_CE) },
2073   { "iret%LP",          { XX }, 0 },
2074   /* d0 */
2075   { REG_TABLE (REG_D0) },
2076   { REG_TABLE (REG_D1) },
2077   { REG_TABLE (REG_D2) },
2078   { REG_TABLE (REG_D3) },
2079   { X86_64_TABLE (X86_64_D4) },
2080   { X86_64_TABLE (X86_64_D5) },
2081   { Bad_Opcode },
2082   { "xlat",             { DSBX }, 0 },
2083   /* d8 */
2084   { FLOAT },
2085   { FLOAT },
2086   { FLOAT },
2087   { FLOAT },
2088   { FLOAT },
2089   { FLOAT },
2090   { FLOAT },
2091   { FLOAT },
2092   /* e0 */
2093   { "loopneFH",         { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2094   { "loopeFH",          { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2095   { "loopFH",           { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2096   { "jEcxzH",           { Jb, XX, loop_jcxz_flag }, PREFIX_REX2_ILLEGAL },
2097   { "inB",              { AL, Ib }, PREFIX_REX2_ILLEGAL },
2098   { "inG",              { zAX, Ib }, PREFIX_REX2_ILLEGAL },
2099   { "outB",             { Ib, AL }, PREFIX_REX2_ILLEGAL },
2100   { "outG",             { Ib, zAX }, PREFIX_REX2_ILLEGAL },
2101   /* e8 */
2102   { X86_64_TABLE (X86_64_E8) },
2103   { X86_64_TABLE (X86_64_E9) },
2104   { X86_64_TABLE (X86_64_EA) },
2105   { "jmp",              { Jb, BND }, PREFIX_REX2_ILLEGAL },
2106   { "inB",              { AL, indirDX }, PREFIX_REX2_ILLEGAL },
2107   { "inG",              { zAX, indirDX }, PREFIX_REX2_ILLEGAL },
2108   { "outB",             { indirDX, AL }, PREFIX_REX2_ILLEGAL },
2109   { "outG",             { indirDX, zAX }, PREFIX_REX2_ILLEGAL },
2110   /* f0 */
2111   { Bad_Opcode },       /* lock prefix */
2112   { "int1",             { XX }, 0 },
2113   { Bad_Opcode },       /* repne */
2114   { Bad_Opcode },       /* repz */
2115   { "hlt",              { XX }, 0 },
2116   { "cmc",              { XX }, 0 },
2117   { REG_TABLE (REG_F6) },
2118   { REG_TABLE (REG_F7) },
2119   /* f8 */
2120   { "clc",              { XX }, 0 },
2121   { "stc",              { XX }, 0 },
2122   { "cli",              { XX }, 0 },
2123   { "sti",              { XX }, 0 },
2124   { "cld",              { XX }, 0 },
2125   { "std",              { XX }, 0 },
2126   { REG_TABLE (REG_FE) },
2127   { REG_TABLE (REG_FF) },
2128 };
2129
2130 static const struct dis386 dis386_twobyte[] = {
2131   /* 00 */
2132   { REG_TABLE (REG_0F00 ) },
2133   { REG_TABLE (REG_0F01 ) },
2134   { "larS",             { Gv, Sv }, 0 },
2135   { "lslS",             { Gv, Sv }, 0 },
2136   { Bad_Opcode },
2137   { "syscall",          { XX }, 0 },
2138   { "clts",             { XX }, 0 },
2139   { "sysret%LQ",                { XX }, 0 },
2140   /* 08 */
2141   { "invd",             { XX }, 0 },
2142   { PREFIX_TABLE (PREFIX_0F09) },
2143   { Bad_Opcode },
2144   { "ud2",              { XX }, 0 },
2145   { Bad_Opcode },
2146   { REG_TABLE (REG_0F0D) },
2147   { "femms",            { XX }, 0 },
2148   { "",                 { MX, EM, OPSUF }, 0 }, /* See OP_3DNowSuffix.  */
2149   /* 10 */
2150   { PREFIX_TABLE (PREFIX_0F10) },
2151   { PREFIX_TABLE (PREFIX_0F11) },
2152   { PREFIX_TABLE (PREFIX_0F12) },
2153   { "movlpX",           { Mq, XM }, PREFIX_OPCODE },
2154   { "unpcklpX",         { XM, EXx }, PREFIX_OPCODE },
2155   { "unpckhpX",         { XM, EXx }, PREFIX_OPCODE },
2156   { PREFIX_TABLE (PREFIX_0F16) },
2157   { "movhpX",           { Mq, XM }, PREFIX_OPCODE },
2158   /* 18 */
2159   { REG_TABLE (REG_0F18) },
2160   { "nopQ",             { Ev }, 0 },
2161   { PREFIX_TABLE (PREFIX_0F1A) },
2162   { PREFIX_TABLE (PREFIX_0F1B) },
2163   { PREFIX_TABLE (PREFIX_0F1C) },
2164   { "nopQ",             { Ev }, 0 },
2165   { PREFIX_TABLE (PREFIX_0F1E) },
2166   { "nopQ",             { Ev }, 0 },
2167   /* 20 */
2168   { "movZ",             { Em, Cm }, 0 },
2169   { "movZ",             { Em, Dm }, 0 },
2170   { "movZ",             { Cm, Em }, 0 },
2171   { "movZ",             { Dm, Em }, 0 },
2172   { X86_64_TABLE (X86_64_0F24) },
2173   { Bad_Opcode },
2174   { X86_64_TABLE (X86_64_0F26) },
2175   { Bad_Opcode },
2176   /* 28 */
2177   { "movapX",           { XM, EXx }, PREFIX_OPCODE },
2178   { "movapX",           { EXxS, XM }, PREFIX_OPCODE },
2179   { PREFIX_TABLE (PREFIX_0F2A) },
2180   { PREFIX_TABLE (PREFIX_0F2B) },
2181   { PREFIX_TABLE (PREFIX_0F2C) },
2182   { PREFIX_TABLE (PREFIX_0F2D) },
2183   { PREFIX_TABLE (PREFIX_0F2E) },
2184   { PREFIX_TABLE (PREFIX_0F2F) },
2185   /* 30 */
2186   { "wrmsr",            { XX }, PREFIX_REX2_ILLEGAL },
2187   { "rdtsc",            { XX }, PREFIX_REX2_ILLEGAL },
2188   { "rdmsr",            { XX }, PREFIX_REX2_ILLEGAL },
2189   { "rdpmc",            { XX }, PREFIX_REX2_ILLEGAL },
2190   { "sysenter",         { SEP }, PREFIX_REX2_ILLEGAL },
2191   { "sysexit%LQ",       { SEP }, PREFIX_REX2_ILLEGAL },
2192   { Bad_Opcode },
2193   { "getsec",           { XX }, 0 },
2194   /* 38 */
2195   { THREE_BYTE_TABLE (THREE_BYTE_0F38) },
2196   { Bad_Opcode },
2197   { THREE_BYTE_TABLE (THREE_BYTE_0F3A) },
2198   { Bad_Opcode },
2199   { Bad_Opcode },
2200   { Bad_Opcode },
2201   { Bad_Opcode },
2202   { Bad_Opcode },
2203   /* 40 */
2204   { "cmovoS",           { Gv, Ev }, 0 },
2205   { "cmovnoS",          { Gv, Ev }, 0 },
2206   { "cmovbS",           { Gv, Ev }, 0 },
2207   { "cmovaeS",          { Gv, Ev }, 0 },
2208   { "cmoveS",           { Gv, Ev }, 0 },
2209   { "cmovneS",          { Gv, Ev }, 0 },
2210   { "cmovbeS",          { Gv, Ev }, 0 },
2211   { "cmovaS",           { Gv, Ev }, 0 },
2212   /* 48 */
2213   { "cmovsS",           { Gv, Ev }, 0 },
2214   { "cmovnsS",          { Gv, Ev }, 0 },
2215   { "cmovpS",           { Gv, Ev }, 0 },
2216   { "cmovnpS",          { Gv, Ev }, 0 },
2217   { "cmovlS",           { Gv, Ev }, 0 },
2218   { "cmovgeS",          { Gv, Ev }, 0 },
2219   { "cmovleS",          { Gv, Ev }, 0 },
2220   { "cmovgS",           { Gv, Ev }, 0 },
2221   /* 50 */
2222   { "movmskpX",         { Gdq, Ux }, PREFIX_OPCODE },
2223   { PREFIX_TABLE (PREFIX_0F51) },
2224   { PREFIX_TABLE (PREFIX_0F52) },
2225   { PREFIX_TABLE (PREFIX_0F53) },
2226   { "andpX",            { XM, EXx }, PREFIX_OPCODE },
2227   { "andnpX",           { XM, EXx }, PREFIX_OPCODE },
2228   { "orpX",             { XM, EXx }, PREFIX_OPCODE },
2229   { "xorpX",            { XM, EXx }, PREFIX_OPCODE },
2230   /* 58 */
2231   { PREFIX_TABLE (PREFIX_0F58) },
2232   { PREFIX_TABLE (PREFIX_0F59) },
2233   { PREFIX_TABLE (PREFIX_0F5A) },
2234   { PREFIX_TABLE (PREFIX_0F5B) },
2235   { PREFIX_TABLE (PREFIX_0F5C) },
2236   { PREFIX_TABLE (PREFIX_0F5D) },
2237   { PREFIX_TABLE (PREFIX_0F5E) },
2238   { PREFIX_TABLE (PREFIX_0F5F) },
2239   /* 60 */
2240   { PREFIX_TABLE (PREFIX_0F60) },
2241   { PREFIX_TABLE (PREFIX_0F61) },
2242   { PREFIX_TABLE (PREFIX_0F62) },
2243   { "packsswb",         { MX, EM }, PREFIX_OPCODE },
2244   { "pcmpgtb",          { MX, EM }, PREFIX_OPCODE },
2245   { "pcmpgtw",          { MX, EM }, PREFIX_OPCODE },
2246   { "pcmpgtd",          { MX, EM }, PREFIX_OPCODE },
2247   { "packuswb",         { MX, EM }, PREFIX_OPCODE },
2248   /* 68 */
2249   { "punpckhbw",        { MX, EM }, PREFIX_OPCODE },
2250   { "punpckhwd",        { MX, EM }, PREFIX_OPCODE },
2251   { "punpckhdq",        { MX, EM }, PREFIX_OPCODE },
2252   { "packssdw",         { MX, EM }, PREFIX_OPCODE },
2253   { "punpcklqdq", { XM, EXx }, PREFIX_DATA },
2254   { "punpckhqdq", { XM, EXx }, PREFIX_DATA },
2255   { "movK",             { MX, Edq }, PREFIX_OPCODE },
2256   { PREFIX_TABLE (PREFIX_0F6F) },
2257   /* 70 */
2258   { PREFIX_TABLE (PREFIX_0F70) },
2259   { REG_TABLE (REG_0F71) },
2260   { REG_TABLE (REG_0F72) },
2261   { REG_TABLE (REG_0F73) },
2262   { "pcmpeqb",          { MX, EM }, PREFIX_OPCODE },
2263   { "pcmpeqw",          { MX, EM }, PREFIX_OPCODE },
2264   { "pcmpeqd",          { MX, EM }, PREFIX_OPCODE },
2265   { "emms",             { XX }, PREFIX_OPCODE },
2266   /* 78 */
2267   { PREFIX_TABLE (PREFIX_0F78) },
2268   { PREFIX_TABLE (PREFIX_0F79) },
2269   { Bad_Opcode },
2270   { Bad_Opcode },
2271   { PREFIX_TABLE (PREFIX_0F7C) },
2272   { PREFIX_TABLE (PREFIX_0F7D) },
2273   { PREFIX_TABLE (PREFIX_0F7E) },
2274   { PREFIX_TABLE (PREFIX_0F7F) },
2275   /* 80 */
2276   { "joH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2277   { "jnoH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2278   { "jbH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2279   { "jaeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2280   { "jeH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2281   { "jneH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2282   { "jbeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2283   { "jaH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2284   /* 88 */
2285   { "jsH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2286   { "jnsH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2287   { "jpH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2288   { "jnpH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2289   { "jlH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2290   { "jgeH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2291   { "jleH",             { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2292   { "jgH",              { Jv, BND, cond_jump_flag }, PREFIX_REX2_ILLEGAL },
2293   /* 90 */
2294   { "seto",             { Eb }, 0 },
2295   { "setno",            { Eb }, 0 },
2296   { "setb",             { Eb }, 0 },
2297   { "setae",            { Eb }, 0 },
2298   { "sete",             { Eb }, 0 },
2299   { "setne",            { Eb }, 0 },
2300   { "setbe",            { Eb }, 0 },
2301   { "seta",             { Eb }, 0 },
2302   /* 98 */
2303   { "sets",             { Eb }, 0 },
2304   { "setns",            { Eb }, 0 },
2305   { "setp",             { Eb }, 0 },
2306   { "setnp",            { Eb }, 0 },
2307   { "setl",             { Eb }, 0 },
2308   { "setge",            { Eb }, 0 },
2309   { "setle",            { Eb }, 0 },
2310   { "setg",             { Eb }, 0 },
2311   /* a0 */
2312   { "pushP",            { fs }, 0 },
2313   { "popP",             { fs }, 0 },
2314   { "cpuid",            { XX }, 0 },
2315   { "btS",              { Ev, Gv }, 0 },
2316   { "shldS",            { Ev, Gv, Ib }, 0 },
2317   { "shldS",            { Ev, Gv, CL }, 0 },
2318   { REG_TABLE (REG_0FA6) },
2319   { REG_TABLE (REG_0FA7) },
2320   /* a8 */
2321   { "pushP",            { gs }, 0 },
2322   { "popP",             { gs }, 0 },
2323   { "rsm",              { XX }, 0 },
2324   { "btsS",             { Evh1, Gv }, 0 },
2325   { "shrdS",            { Ev, Gv, Ib }, 0 },
2326   { "shrdS",            { Ev, Gv, CL }, 0 },
2327   { REG_TABLE (REG_0FAE) },
2328   { "imulS",            { Gv, Ev }, 0 },
2329   /* b0 */
2330   { "cmpxchgB",         { Ebh1, Gb }, 0 },
2331   { "cmpxchgS",         { Evh1, Gv }, 0 },
2332   { "lssS",             { Gv, Mp }, 0 },
2333   { "btrS",             { Evh1, Gv }, 0 },
2334   { "lfsS",             { Gv, Mp }, 0 },
2335   { "lgsS",             { Gv, Mp }, 0 },
2336   { "movz{bR|x}",       { Gv, Eb }, 0 },
2337   { "movz{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movzww ! */
2338   /* b8 */
2339   { PREFIX_TABLE (PREFIX_0FB8) },
2340   { "ud1S",             { Gv, Ev }, 0 },
2341   { REG_TABLE (REG_0FBA) },
2342   { "btcS",             { Evh1, Gv }, 0 },
2343   { PREFIX_TABLE (PREFIX_0FBC) },
2344   { PREFIX_TABLE (PREFIX_0FBD) },
2345   { "movs{bR|x}",       { Gv, Eb }, 0 },
2346   { "movs{wR|x}",       { Gv, Ew }, 0 }, /* yes, there really is movsww ! */
2347   /* c0 */
2348   { "xaddB",            { Ebh1, Gb }, 0 },
2349   { "xaddS",            { Evh1, Gv }, 0 },
2350   { PREFIX_TABLE (PREFIX_0FC2) },
2351   { "movntiS",          { Mdq, Gdq }, PREFIX_OPCODE },
2352   { "pinsrw",           { MX, Edw, Ib }, PREFIX_OPCODE },
2353   { "pextrw",           { Gd, Nq, Ib }, PREFIX_OPCODE },
2354   { "shufpX",           { XM, EXx, Ib }, PREFIX_OPCODE },
2355   { REG_TABLE (REG_0FC7) },
2356   /* c8 */
2357   { "bswap",            { RMeAX }, 0 },
2358   { "bswap",            { RMeCX }, 0 },
2359   { "bswap",            { RMeDX }, 0 },
2360   { "bswap",            { RMeBX }, 0 },
2361   { "bswap",            { RMeSP }, 0 },
2362   { "bswap",            { RMeBP }, 0 },
2363   { "bswap",            { RMeSI }, 0 },
2364   { "bswap",            { RMeDI }, 0 },
2365   /* d0 */
2366   { PREFIX_TABLE (PREFIX_0FD0) },
2367   { "psrlw",            { MX, EM }, PREFIX_OPCODE },
2368   { "psrld",            { MX, EM }, PREFIX_OPCODE },
2369   { "psrlq",            { MX, EM }, PREFIX_OPCODE },
2370   { "paddq",            { MX, EM }, PREFIX_OPCODE },
2371   { "pmullw",           { MX, EM }, PREFIX_OPCODE },
2372   { PREFIX_TABLE (PREFIX_0FD6) },
2373   { "pmovmskb",         { Gdq, Nq }, PREFIX_OPCODE },
2374   /* d8 */
2375   { "psubusb",          { MX, EM }, PREFIX_OPCODE },
2376   { "psubusw",          { MX, EM }, PREFIX_OPCODE },
2377   { "pminub",           { MX, EM }, PREFIX_OPCODE },
2378   { "pand",             { MX, EM }, PREFIX_OPCODE },
2379   { "paddusb",          { MX, EM }, PREFIX_OPCODE },
2380   { "paddusw",          { MX, EM }, PREFIX_OPCODE },
2381   { "pmaxub",           { MX, EM }, PREFIX_OPCODE },
2382   { "pandn",            { MX, EM }, PREFIX_OPCODE },
2383   /* e0 */
2384   { "pavgb",            { MX, EM }, PREFIX_OPCODE },
2385   { "psraw",            { MX, EM }, PREFIX_OPCODE },
2386   { "psrad",            { MX, EM }, PREFIX_OPCODE },
2387   { "pavgw",            { MX, EM }, PREFIX_OPCODE },
2388   { "pmulhuw",          { MX, EM }, PREFIX_OPCODE },
2389   { "pmulhw",           { MX, EM }, PREFIX_OPCODE },
2390   { PREFIX_TABLE (PREFIX_0FE6) },
2391   { PREFIX_TABLE (PREFIX_0FE7) },
2392   /* e8 */
2393   { "psubsb",           { MX, EM }, PREFIX_OPCODE },
2394   { "psubsw",           { MX, EM }, PREFIX_OPCODE },
2395   { "pminsw",           { MX, EM }, PREFIX_OPCODE },
2396   { "por",              { MX, EM }, PREFIX_OPCODE },
2397   { "paddsb",           { MX, EM }, PREFIX_OPCODE },
2398   { "paddsw",           { MX, EM }, PREFIX_OPCODE },
2399   { "pmaxsw",           { MX, EM }, PREFIX_OPCODE },
2400   { "pxor",             { MX, EM }, PREFIX_OPCODE },
2401   /* f0 */
2402   { PREFIX_TABLE (PREFIX_0FF0) },
2403   { "psllw",            { MX, EM }, PREFIX_OPCODE },
2404   { "pslld",            { MX, EM }, PREFIX_OPCODE },
2405   { "psllq",            { MX, EM }, PREFIX_OPCODE },
2406   { "pmuludq",          { MX, EM }, PREFIX_OPCODE },
2407   { "pmaddwd",          { MX, EM }, PREFIX_OPCODE },
2408   { "psadbw",           { MX, EM }, PREFIX_OPCODE },
2409   { PREFIX_TABLE (PREFIX_0FF7) },
2410   /* f8 */
2411   { "psubb",            { MX, EM }, PREFIX_OPCODE },
2412   { "psubw",            { MX, EM }, PREFIX_OPCODE },
2413   { "psubd",            { MX, EM }, PREFIX_OPCODE },
2414   { "psubq",            { MX, EM }, PREFIX_OPCODE },
2415   { "paddb",            { MX, EM }, PREFIX_OPCODE },
2416   { "paddw",            { MX, EM }, PREFIX_OPCODE },
2417   { "paddd",            { MX, EM }, PREFIX_OPCODE },
2418   { "ud0S",             { Gv, Ev }, 0 },
2419 };
2420
2421 static const bool onebyte_has_modrm[256] = {
2422   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2423   /*       -------------------------------        */
2424   /* 00 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 00 */
2425   /* 10 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 10 */
2426   /* 20 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 20 */
2427   /* 30 */ 1,1,1,1,0,0,0,0,1,1,1,1,0,0,0,0, /* 30 */
2428   /* 40 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 40 */
2429   /* 50 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 50 */
2430   /* 60 */ 0,0,1,1,0,0,0,0,0,1,0,1,0,0,0,0, /* 60 */
2431   /* 70 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 70 */
2432   /* 80 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 80 */
2433   /* 90 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 90 */
2434   /* a0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* a0 */
2435   /* b0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* b0 */
2436   /* c0 */ 1,1,0,0,1,1,1,1,0,0,0,0,0,0,0,0, /* c0 */
2437   /* d0 */ 1,1,1,1,0,0,0,0,1,1,1,1,1,1,1,1, /* d0 */
2438   /* e0 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* e0 */
2439   /* f0 */ 0,0,0,0,0,0,1,1,0,0,0,0,0,0,1,1  /* f0 */
2440   /*       -------------------------------        */
2441   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2442 };
2443
2444 static const bool twobyte_has_modrm[256] = {
2445   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2446   /*       -------------------------------        */
2447   /* 00 */ 1,1,1,1,0,0,0,0,0,0,0,0,0,1,0,1, /* 0f */
2448   /* 10 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 1f */
2449   /* 20 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 2f */
2450   /* 30 */ 0,0,0,0,0,0,0,0,1,0,1,0,0,0,0,0, /* 3f */
2451   /* 40 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 4f */
2452   /* 50 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 5f */
2453   /* 60 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 6f */
2454   /* 70 */ 1,1,1,1,1,1,1,0,1,1,1,1,1,1,1,1, /* 7f */
2455   /* 80 */ 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0, /* 8f */
2456   /* 90 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* 9f */
2457   /* a0 */ 0,0,0,1,1,1,1,1,0,0,0,1,1,1,1,1, /* af */
2458   /* b0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* bf */
2459   /* c0 */ 1,1,1,1,1,1,1,1,0,0,0,0,0,0,0,0, /* cf */
2460   /* d0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* df */
2461   /* e0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1, /* ef */
2462   /* f0 */ 1,1,1,1,1,1,1,1,1,1,1,1,1,1,1,1  /* ff */
2463   /*       -------------------------------        */
2464   /*       0 1 2 3 4 5 6 7 8 9 a b c d e f        */
2465 };
2466
2467
2468 struct op
2469   {
2470     const char *name;
2471     unsigned int len;
2472   };
2473
2474 /* If we are accessing mod/rm/reg without need_modrm set, then the
2475    values are stale.  Hitting this abort likely indicates that you
2476    need to update onebyte_has_modrm or twobyte_has_modrm.  */
2477 #define MODRM_CHECK  if (!ins->need_modrm) abort ()
2478
2479 static const char intel_index16[][6] = {
2480   "bx+si", "bx+di", "bp+si", "bp+di", "si", "di", "bp", "bx"
2481 };
2482
2483 static const char att_names64[][8] = {
2484   "%rax", "%rcx", "%rdx", "%rbx", "%rsp", "%rbp", "%rsi", "%rdi",
2485   "%r8", "%r9", "%r10", "%r11", "%r12", "%r13", "%r14", "%r15",
2486   "%r16", "%r17", "%r18", "%r19", "%r20", "%r21", "%r22", "%r23",
2487   "%r24", "%r25", "%r26", "%r27", "%r28", "%r29", "%r30", "%r31",
2488 };
2489 static const char att_names32[][8] = {
2490   "%eax", "%ecx", "%edx", "%ebx", "%esp", "%ebp", "%esi", "%edi",
2491   "%r8d", "%r9d", "%r10d", "%r11d", "%r12d", "%r13d", "%r14d", "%r15d",
2492   "%r16d", "%r17d", "%r18d", "%r19d", "%r20d", "%r21d", "%r22d", "%r23d",
2493   "%r24d", "%r25d", "%r26d", "%r27d", "%r28d", "%r29d", "%r30d", "%r31d",
2494 };
2495 static const char att_names16[][8] = {
2496   "%ax", "%cx", "%dx", "%bx", "%sp", "%bp", "%si", "%di",
2497   "%r8w", "%r9w", "%r10w", "%r11w", "%r12w", "%r13w", "%r14w", "%r15w",
2498   "%r16w", "%r17w", "%r18w", "%r19w", "%r20w", "%r21w", "%r22w", "%r23w",
2499   "%r24w", "%r25w", "%r26w", "%r27w", "%r28w", "%r29w", "%r30w", "%r31w",
2500 };
2501 static const char att_names8[][8] = {
2502   "%al", "%cl", "%dl", "%bl", "%ah", "%ch", "%dh", "%bh",
2503 };
2504 static const char att_names8rex[][8] = {
2505   "%al", "%cl", "%dl", "%bl", "%spl", "%bpl", "%sil", "%dil",
2506   "%r8b", "%r9b", "%r10b", "%r11b", "%r12b", "%r13b", "%r14b", "%r15b",
2507   "%r16b", "%r17b", "%r18b", "%r19b", "%r20b", "%r21b", "%r22b", "%r23b",
2508   "%r24b", "%r25b", "%r26b", "%r27b", "%r28b", "%r29b", "%r30b", "%r31b",
2509 };
2510 static const char att_names_seg[][4] = {
2511   "%es", "%cs", "%ss", "%ds", "%fs", "%gs", "%?", "%?",
2512 };
2513 static const char att_index64[] = "%riz";
2514 static const char att_index32[] = "%eiz";
2515 static const char att_index16[][8] = {
2516   "%bx,%si", "%bx,%di", "%bp,%si", "%bp,%di", "%si", "%di", "%bp", "%bx"
2517 };
2518
2519 static const char att_names_mm[][8] = {
2520   "%mm0", "%mm1", "%mm2", "%mm3",
2521   "%mm4", "%mm5", "%mm6", "%mm7"
2522 };
2523
2524 static const char att_names_bnd[][8] = {
2525   "%bnd0", "%bnd1", "%bnd2", "%bnd3"
2526 };
2527
2528 static const char att_names_xmm[][8] = {
2529   "%xmm0", "%xmm1", "%xmm2", "%xmm3",
2530   "%xmm4", "%xmm5", "%xmm6", "%xmm7",
2531   "%xmm8", "%xmm9", "%xmm10", "%xmm11",
2532   "%xmm12", "%xmm13", "%xmm14", "%xmm15",
2533   "%xmm16", "%xmm17", "%xmm18", "%xmm19",
2534   "%xmm20", "%xmm21", "%xmm22", "%xmm23",
2535   "%xmm24", "%xmm25", "%xmm26", "%xmm27",
2536   "%xmm28", "%xmm29", "%xmm30", "%xmm31"
2537 };
2538
2539 static const char att_names_ymm[][8] = {
2540   "%ymm0", "%ymm1", "%ymm2", "%ymm3",
2541   "%ymm4", "%ymm5", "%ymm6", "%ymm7",
2542   "%ymm8", "%ymm9", "%ymm10", "%ymm11",
2543   "%ymm12", "%ymm13", "%ymm14", "%ymm15",
2544   "%ymm16", "%ymm17", "%ymm18", "%ymm19",
2545   "%ymm20", "%ymm21", "%ymm22", "%ymm23",
2546   "%ymm24", "%ymm25", "%ymm26", "%ymm27",
2547   "%ymm28", "%ymm29", "%ymm30", "%ymm31"
2548 };
2549
2550 static const char att_names_zmm[][8] = {
2551   "%zmm0", "%zmm1", "%zmm2", "%zmm3",
2552   "%zmm4", "%zmm5", "%zmm6", "%zmm7",
2553   "%zmm8", "%zmm9", "%zmm10", "%zmm11",
2554   "%zmm12", "%zmm13", "%zmm14", "%zmm15",
2555   "%zmm16", "%zmm17", "%zmm18", "%zmm19",
2556   "%zmm20", "%zmm21", "%zmm22", "%zmm23",
2557   "%zmm24", "%zmm25", "%zmm26", "%zmm27",
2558   "%zmm28", "%zmm29", "%zmm30", "%zmm31"
2559 };
2560
2561 static const char att_names_tmm[][8] = {
2562   "%tmm0", "%tmm1", "%tmm2", "%tmm3",
2563   "%tmm4", "%tmm5", "%tmm6", "%tmm7"
2564 };
2565
2566 static const char att_names_mask[][8] = {
2567   "%k0", "%k1", "%k2", "%k3", "%k4", "%k5", "%k6", "%k7"
2568 };
2569
2570 static const char *const names_rounding[] =
2571 {
2572   "{rn-",
2573   "{rd-",
2574   "{ru-",
2575   "{rz-"
2576 };
2577
2578 static const struct dis386 reg_table[][8] = {
2579   /* REG_80 */
2580   {
2581     { "addA",   { Ebh1, Ib }, 0 },
2582     { "orA",    { Ebh1, Ib }, 0 },
2583     { "adcA",   { Ebh1, Ib }, 0 },
2584     { "sbbA",   { Ebh1, Ib }, 0 },
2585     { "andA",   { Ebh1, Ib }, 0 },
2586     { "subA",   { Ebh1, Ib }, 0 },
2587     { "xorA",   { Ebh1, Ib }, 0 },
2588     { "cmpA",   { Eb, Ib }, 0 },
2589   },
2590   /* REG_81 */
2591   {
2592     { "addQ",   { Evh1, Iv }, 0 },
2593     { "orQ",    { Evh1, Iv }, 0 },
2594     { "adcQ",   { Evh1, Iv }, 0 },
2595     { "sbbQ",   { Evh1, Iv }, 0 },
2596     { "andQ",   { Evh1, Iv }, 0 },
2597     { "subQ",   { Evh1, Iv }, 0 },
2598     { "xorQ",   { Evh1, Iv }, 0 },
2599     { "cmpQ",   { Ev, Iv }, 0 },
2600   },
2601   /* REG_83 */
2602   {
2603     { "addQ",   { Evh1, sIb }, 0 },
2604     { "orQ",    { Evh1, sIb }, 0 },
2605     { "adcQ",   { Evh1, sIb }, 0 },
2606     { "sbbQ",   { Evh1, sIb }, 0 },
2607     { "andQ",   { Evh1, sIb }, 0 },
2608     { "subQ",   { Evh1, sIb }, 0 },
2609     { "xorQ",   { Evh1, sIb }, 0 },
2610     { "cmpQ",   { Ev, sIb }, 0 },
2611   },
2612   /* REG_8F */
2613   {
2614     { "pop{P|}", { stackEv }, 0 },
2615     { XOP_8F_TABLE () },
2616     { Bad_Opcode },
2617     { Bad_Opcode },
2618     { Bad_Opcode },
2619     { XOP_8F_TABLE () },
2620   },
2621   /* REG_C0 */
2622   {
2623     { "rolA",   { VexGb, Eb, Ib }, NO_PREFIX },
2624     { "rorA",   { VexGb, Eb, Ib }, NO_PREFIX },
2625     { "rclA",   { VexGb, Eb, Ib }, NO_PREFIX },
2626     { "rcrA",   { VexGb, Eb, Ib }, NO_PREFIX },
2627     { "shlA",   { VexGb, Eb, Ib }, NO_PREFIX },
2628     { "shrA",   { VexGb, Eb, Ib }, NO_PREFIX },
2629     { "shlA",   { VexGb, Eb, Ib }, NO_PREFIX },
2630     { "sarA",   { VexGb, Eb, Ib }, NO_PREFIX },
2631   },
2632   /* REG_C1 */
2633   {
2634     { "rolQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2635     { "rorQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2636     { "rclQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2637     { "rcrQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2638     { "shlQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2639     { "shrQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2640     { "shlQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2641     { "sarQ",   { VexGv, Ev, Ib }, PREFIX_NP_OR_DATA },
2642   },
2643   /* REG_C6 */
2644   {
2645     { "movA",   { Ebh3, Ib }, 0 },
2646     { Bad_Opcode },
2647     { Bad_Opcode },
2648     { Bad_Opcode },
2649     { Bad_Opcode },
2650     { Bad_Opcode },
2651     { Bad_Opcode },
2652     { RM_TABLE (RM_C6_REG_7) },
2653   },
2654   /* REG_C7 */
2655   {
2656     { "movQ",   { Evh3, Iv }, 0 },
2657     { Bad_Opcode },
2658     { Bad_Opcode },
2659     { Bad_Opcode },
2660     { Bad_Opcode },
2661     { Bad_Opcode },
2662     { Bad_Opcode },
2663     { RM_TABLE (RM_C7_REG_7) },
2664   },
2665   /* REG_D0 */
2666   {
2667     { "rolA",   { VexGb, Eb, I1 }, NO_PREFIX },
2668     { "rorA",   { VexGb, Eb, I1 }, NO_PREFIX },
2669     { "rclA",   { VexGb, Eb, I1 }, NO_PREFIX },
2670     { "rcrA",   { VexGb, Eb, I1 }, NO_PREFIX },
2671     { "shlA",   { VexGb, Eb, I1 }, NO_PREFIX },
2672     { "shrA",   { VexGb, Eb, I1 }, NO_PREFIX },
2673     { "shlA",   { VexGb, Eb, I1 }, NO_PREFIX },
2674     { "sarA",   { VexGb, Eb, I1 }, NO_PREFIX },
2675   },
2676   /* REG_D1 */
2677   {
2678     { "rolQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2679     { "rorQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2680     { "rclQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2681     { "rcrQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2682     { "shlQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2683     { "shrQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2684     { "shlQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2685     { "sarQ",   { VexGv, Ev, I1 }, PREFIX_NP_OR_DATA },
2686   },
2687   /* REG_D2 */
2688   {
2689     { "rolA",   { VexGb, Eb, CL }, NO_PREFIX },
2690     { "rorA",   { VexGb, Eb, CL }, NO_PREFIX },
2691     { "rclA",   { VexGb, Eb, CL }, NO_PREFIX },
2692     { "rcrA",   { VexGb, Eb, CL }, NO_PREFIX },
2693     { "shlA",   { VexGb, Eb, CL }, NO_PREFIX },
2694     { "shrA",   { VexGb, Eb, CL }, NO_PREFIX },
2695     { "shlA",   { VexGb, Eb, CL }, NO_PREFIX },
2696     { "sarA",   { VexGb, Eb, CL }, NO_PREFIX },
2697   },
2698   /* REG_D3 */
2699   {
2700     { "rolQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2701     { "rorQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2702     { "rclQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2703     { "rcrQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2704     { "shlQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2705     { "shrQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2706     { "shlQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2707     { "sarQ",   { VexGv, Ev, CL }, PREFIX_NP_OR_DATA },
2708   },
2709   /* REG_F6 */
2710   {
2711     { "testA",  { Eb, Ib }, 0 },
2712     { "testA",  { Eb, Ib }, 0 },
2713     { "notA",   { Ebh1 }, 0 },
2714     { "negA",   { Ebh1 }, 0 },
2715     { "mulA",   { Eb }, 0 },    /* Don't print the implicit %al register,  */
2716     { "imulA",  { Eb }, 0 },    /* to distinguish these opcodes from other */
2717     { "divA",   { Eb }, 0 },    /* mul/imul opcodes.  Do the same for div  */
2718     { "idivA",  { Eb }, 0 },    /* and idiv for consistency.               */
2719   },
2720   /* REG_F7 */
2721   {
2722     { "testQ",  { Ev, Iv }, 0 },
2723     { "testQ",  { Ev, Iv }, 0 },
2724     { "notQ",   { Evh1 }, 0 },
2725     { "negQ",   { Evh1 }, 0 },
2726     { "mulQ",   { Ev }, 0 },    /* Don't print the implicit register.  */
2727     { "imulQ",  { Ev }, 0 },
2728     { "divQ",   { Ev }, 0 },
2729     { "idivQ",  { Ev }, 0 },
2730   },
2731   /* REG_FE */
2732   {
2733     { "incA",   { Ebh1 }, 0 },
2734     { "decA",   { Ebh1 }, 0 },
2735   },
2736   /* REG_FF */
2737   {
2738     { "incQ",   { Evh1 }, 0 },
2739     { "decQ",   { Evh1 }, 0 },
2740     { "call{@|}", { NOTRACK, indirEv, BND }, 0 },
2741     { "{l|}call^", { indirEp }, 0 },
2742     { "jmp{@|}", { NOTRACK, indirEv, BND }, 0 },
2743     { "{l|}jmp^", { indirEp }, 0 },
2744     { "push{P|}", { stackEv }, 0 },
2745     { Bad_Opcode },
2746   },
2747   /* REG_0F00 */
2748   {
2749     { "sldtD",  { Sv }, 0 },
2750     { "strD",   { Sv }, 0 },
2751     { "lldtD",  { Sv }, 0 },
2752     { "ltrD",   { Sv }, 0 },
2753     { "verrD",  { Sv }, 0 },
2754     { "verwD",  { Sv }, 0 },
2755     { X86_64_TABLE (X86_64_0F00_REG_6) },
2756     { Bad_Opcode },
2757   },
2758   /* REG_0F01 */
2759   {
2760     { MOD_TABLE (MOD_0F01_REG_0) },
2761     { MOD_TABLE (MOD_0F01_REG_1) },
2762     { MOD_TABLE (MOD_0F01_REG_2) },
2763     { MOD_TABLE (MOD_0F01_REG_3) },
2764     { "smswD",  { Sv }, 0 },
2765     { MOD_TABLE (MOD_0F01_REG_5) },
2766     { "lmsw",   { Ew }, 0 },
2767     { MOD_TABLE (MOD_0F01_REG_7) },
2768   },
2769   /* REG_0F0D */
2770   {
2771     { "prefetch",       { Mb }, 0 },
2772     { "prefetchw",      { Mb }, 0 },
2773     { "prefetchwt1",    { Mb }, 0 },
2774     { "prefetch",       { Mb }, 0 },
2775     { "prefetch",       { Mb }, 0 },
2776     { "prefetch",       { Mb }, 0 },
2777     { "prefetch",       { Mb }, 0 },
2778     { "prefetch",       { Mb }, 0 },
2779   },
2780   /* REG_0F18 */
2781   {
2782     { MOD_TABLE (MOD_0F18_REG_0) },
2783     { MOD_TABLE (MOD_0F18_REG_1) },
2784     { MOD_TABLE (MOD_0F18_REG_2) },
2785     { MOD_TABLE (MOD_0F18_REG_3) },
2786     { "nopQ",           { Ev }, 0 },
2787     { "nopQ",           { Ev }, 0 },
2788     { MOD_TABLE (MOD_0F18_REG_6) },
2789     { MOD_TABLE (MOD_0F18_REG_7) },
2790   },
2791   /* REG_0F1C_P_0_MOD_0 */
2792   {
2793     { "cldemote",       { Mb }, 0 },
2794     { "nopQ",           { Ev }, 0 },
2795     { "nopQ",           { Ev }, 0 },
2796     { "nopQ",           { Ev }, 0 },
2797     { "nopQ",           { Ev }, 0 },
2798     { "nopQ",           { Ev }, 0 },
2799     { "nopQ",           { Ev }, 0 },
2800     { "nopQ",           { Ev }, 0 },
2801   },
2802   /* REG_0F1E_P_1_MOD_3 */
2803   {
2804     { "nopQ",           { Ev }, PREFIX_IGNORED },
2805     { "rdsspK",         { Edq }, 0 },
2806     { "nopQ",           { Ev }, PREFIX_IGNORED },
2807     { "nopQ",           { Ev }, PREFIX_IGNORED },
2808     { "nopQ",           { Ev }, PREFIX_IGNORED },
2809     { "nopQ",           { Ev }, PREFIX_IGNORED },
2810     { "nopQ",           { Ev }, PREFIX_IGNORED },
2811     { RM_TABLE (RM_0F1E_P_1_MOD_3_REG_7) },
2812   },
2813   /* REG_0F38D8_PREFIX_1 */
2814   {
2815     { "aesencwide128kl",        { M }, 0 },
2816     { "aesdecwide128kl",        { M }, 0 },
2817     { "aesencwide256kl",        { M }, 0 },
2818     { "aesdecwide256kl",        { M }, 0 },
2819   },
2820   /* REG_0F3A0F_P_1 */
2821   {
2822     { RM_TABLE (RM_0F3A0F_P_1_R_0) },
2823   },
2824   /* REG_0F71 */
2825   {
2826     { Bad_Opcode },
2827     { Bad_Opcode },
2828     { "psrlw",          { Nq, Ib }, PREFIX_OPCODE },
2829     { Bad_Opcode },
2830     { "psraw",          { Nq, Ib }, PREFIX_OPCODE },
2831     { Bad_Opcode },
2832     { "psllw",          { Nq, Ib }, PREFIX_OPCODE },
2833   },
2834   /* REG_0F72 */
2835   {
2836     { Bad_Opcode },
2837     { Bad_Opcode },
2838     { "psrld",          { Nq, Ib }, PREFIX_OPCODE },
2839     { Bad_Opcode },
2840     { "psrad",          { Nq, Ib }, PREFIX_OPCODE },
2841     { Bad_Opcode },
2842     { "pslld",          { Nq, Ib }, PREFIX_OPCODE },
2843   },
2844   /* REG_0F73 */
2845   {
2846     { Bad_Opcode },
2847     { Bad_Opcode },
2848     { "psrlq",          { Nq, Ib }, PREFIX_OPCODE },
2849     { "psrldq",         { Ux, Ib }, PREFIX_DATA },
2850     { Bad_Opcode },
2851     { Bad_Opcode },
2852     { "psllq",          { Nq, Ib }, PREFIX_OPCODE },
2853     { "pslldq",         { Ux, Ib }, PREFIX_DATA },
2854   },
2855   /* REG_0FA6 */
2856   {
2857     { "montmul",        { { OP_0f07, 0 } }, 0 },
2858     { "xsha1",          { { OP_0f07, 0 } }, 0 },
2859     { "xsha256",        { { OP_0f07, 0 } }, 0 },
2860   },
2861   /* REG_0FA7 */
2862   {
2863     { "xstore-rng",     { { OP_0f07, 0 } }, 0 },
2864     { "xcrypt-ecb",     { { OP_0f07, 0 } }, 0 },
2865     { "xcrypt-cbc",     { { OP_0f07, 0 } }, 0 },
2866     { "xcrypt-ctr",     { { OP_0f07, 0 } }, 0 },
2867     { "xcrypt-cfb",     { { OP_0f07, 0 } }, 0 },
2868     { "xcrypt-ofb",     { { OP_0f07, 0 } }, 0 },
2869   },
2870   /* REG_0FAE */
2871   {
2872     { MOD_TABLE (MOD_0FAE_REG_0) },
2873     { MOD_TABLE (MOD_0FAE_REG_1) },
2874     { MOD_TABLE (MOD_0FAE_REG_2) },
2875     { MOD_TABLE (MOD_0FAE_REG_3) },
2876     { MOD_TABLE (MOD_0FAE_REG_4) },
2877     { MOD_TABLE (MOD_0FAE_REG_5) },
2878     { MOD_TABLE (MOD_0FAE_REG_6) },
2879     { MOD_TABLE (MOD_0FAE_REG_7) },
2880   },
2881   /* REG_0FBA */
2882   {
2883     { Bad_Opcode },
2884     { Bad_Opcode },
2885     { Bad_Opcode },
2886     { Bad_Opcode },
2887     { "btQ",    { Ev, Ib }, 0 },
2888     { "btsQ",   { Evh1, Ib }, 0 },
2889     { "btrQ",   { Evh1, Ib }, 0 },
2890     { "btcQ",   { Evh1, Ib }, 0 },
2891   },
2892   /* REG_0FC7 */
2893   {
2894     { Bad_Opcode },
2895     { "cmpxchg8b", { { CMPXCHG8B_Fixup, q_mode } }, 0 },
2896     { Bad_Opcode },
2897     { "xrstors", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2898     { "xsavec", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2899     { "xsaves", { FXSAVE }, PREFIX_REX2_ILLEGAL },
2900     { MOD_TABLE (MOD_0FC7_REG_6) },
2901     { MOD_TABLE (MOD_0FC7_REG_7) },
2902   },
2903   /* REG_VEX_0F71 */
2904   {
2905     { Bad_Opcode },
2906     { Bad_Opcode },
2907     { "vpsrlw",         { Vex, Ux, Ib }, PREFIX_DATA },
2908     { Bad_Opcode },
2909     { "vpsraw",         { Vex, Ux, Ib }, PREFIX_DATA },
2910     { Bad_Opcode },
2911     { "vpsllw",         { Vex, Ux, Ib }, PREFIX_DATA },
2912   },
2913   /* REG_VEX_0F72 */
2914   {
2915     { Bad_Opcode },
2916     { Bad_Opcode },
2917     { "vpsrld",         { Vex, Ux, Ib }, PREFIX_DATA },
2918     { Bad_Opcode },
2919     { "vpsrad",         { Vex, Ux, Ib }, PREFIX_DATA },
2920     { Bad_Opcode },
2921     { "vpslld",         { Vex, Ux, Ib }, PREFIX_DATA },
2922   },
2923   /* REG_VEX_0F73 */
2924   {
2925     { Bad_Opcode },
2926     { Bad_Opcode },
2927     { "vpsrlq",         { Vex, Ux, Ib }, PREFIX_DATA },
2928     { "vpsrldq",        { Vex, Ux, Ib }, PREFIX_DATA },
2929     { Bad_Opcode },
2930     { Bad_Opcode },
2931     { "vpsllq",         { Vex, Ux, Ib }, PREFIX_DATA },
2932     { "vpslldq",        { Vex, Ux, Ib }, PREFIX_DATA },
2933   },
2934   /* REG_VEX_0FAE */
2935   {
2936     { Bad_Opcode },
2937     { Bad_Opcode },
2938     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_2) },
2939     { VEX_LEN_TABLE (VEX_LEN_0FAE_R_3) },
2940   },
2941   /* REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0 */
2942   {
2943     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0) },
2944   },
2945   /* REG_VEX_0F38F3_L_0_P_0 */
2946   {
2947     { Bad_Opcode },
2948     { "blsrS",          { VexGdq, Edq }, 0 },
2949     { "blsmskS",        { VexGdq, Edq }, 0 },
2950     { "blsiS",          { VexGdq, Edq }, 0 },
2951   },
2952   /* REG_VEX_MAP7_F8_L_0_W_0 */
2953   {
2954     { X86_64_TABLE (X86_64_VEX_MAP7_F8_L_0_W_0_R_0) },
2955   },
2956   /* REG_XOP_09_01_L_0 */
2957   {
2958     { Bad_Opcode },
2959     { "blcfill",        { VexGdq, Edq }, 0 },
2960     { "blsfill",        { VexGdq, Edq }, 0 },
2961     { "blcs",   { VexGdq, Edq }, 0 },
2962     { "tzmsk",  { VexGdq, Edq }, 0 },
2963     { "blcic",  { VexGdq, Edq }, 0 },
2964     { "blsic",  { VexGdq, Edq }, 0 },
2965     { "t1mskc", { VexGdq, Edq }, 0 },
2966   },
2967   /* REG_XOP_09_02_L_0 */
2968   {
2969     { Bad_Opcode },
2970     { "blcmsk", { VexGdq, Edq }, 0 },
2971     { Bad_Opcode },
2972     { Bad_Opcode },
2973     { Bad_Opcode },
2974     { Bad_Opcode },
2975     { "blci",   { VexGdq, Edq }, 0 },
2976   },
2977   /* REG_XOP_09_12_L_0 */
2978   {
2979     { "llwpcb", { Rdq }, 0 },
2980     { "slwpcb", { Rdq }, 0 },
2981   },
2982   /* REG_XOP_0A_12_L_0 */
2983   {
2984     { "lwpins", { VexGdq, Ed, Id }, 0 },
2985     { "lwpval", { VexGdq, Ed, Id }, 0 },
2986   },
2987
2988 #include "i386-dis-evex-reg.h"
2989 };
2990
2991 static const struct dis386 prefix_table[][4] = {
2992   /* PREFIX_90 */
2993   {
2994     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2995     { "pause", { XX }, 0 },
2996     { "xchgS", { { NOP_Fixup, 0 }, { NOP_Fixup, 1 } }, 0 },
2997     { NULL, { { NULL, 0 } }, PREFIX_IGNORED }
2998   },
2999
3000   /* PREFIX_0F00_REG_6_X86_64 */
3001   {
3002     { Bad_Opcode },
3003     { Bad_Opcode },
3004     { Bad_Opcode },
3005     { "lkgsD", { Sv }, 0 },
3006   },
3007
3008   /* PREFIX_0F01_REG_0_MOD_3_RM_6 */
3009   {
3010     { "wrmsrns",        { Skip_MODRM }, 0 },
3011     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_1) },
3012     { Bad_Opcode },
3013     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_6_P_3) },
3014   },
3015
3016   /* PREFIX_0F01_REG_0_MOD_3_RM_7 */
3017   {
3018     { X86_64_TABLE (X86_64_0F01_REG_0_MOD_3_RM_7_P_0) },
3019   },
3020
3021   /* PREFIX_0F01_REG_1_RM_2 */
3022   {
3023     { "clac",           { Skip_MODRM }, 0 },
3024     { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_1) },
3025     { Bad_Opcode },
3026     { X86_64_TABLE (X86_64_0F01_REG_1_RM_2_PREFIX_3)},
3027   },
3028
3029   /* PREFIX_0F01_REG_1_RM_4 */
3030   {
3031     { Bad_Opcode },
3032     { Bad_Opcode },
3033     { "tdcall",         { Skip_MODRM }, 0 },
3034     { Bad_Opcode },
3035   },
3036
3037   /* PREFIX_0F01_REG_1_RM_5 */
3038   {
3039     { Bad_Opcode },
3040     { Bad_Opcode },
3041     { X86_64_TABLE (X86_64_0F01_REG_1_RM_5_PREFIX_2) },
3042     { Bad_Opcode },
3043   },
3044
3045   /* PREFIX_0F01_REG_1_RM_6 */
3046   {
3047     { Bad_Opcode },
3048     { Bad_Opcode },
3049     { X86_64_TABLE (X86_64_0F01_REG_1_RM_6_PREFIX_2) },
3050     { Bad_Opcode },
3051   },
3052
3053   /* PREFIX_0F01_REG_1_RM_7 */
3054   {
3055     { "encls",          { Skip_MODRM }, 0 },
3056     { Bad_Opcode },
3057     { X86_64_TABLE (X86_64_0F01_REG_1_RM_7_PREFIX_2) },
3058     { Bad_Opcode },
3059   },
3060
3061   /* PREFIX_0F01_REG_3_RM_1 */
3062   {
3063     { "vmmcall",        { Skip_MODRM }, 0 },
3064     { "vmgexit",        { Skip_MODRM }, 0 },
3065     { Bad_Opcode },
3066     { "vmgexit",        { Skip_MODRM }, 0 },
3067   },
3068
3069   /* PREFIX_0F01_REG_5_MOD_0 */
3070   {
3071     { Bad_Opcode },
3072     { "rstorssp",       { Mq }, PREFIX_OPCODE },
3073   },
3074
3075   /* PREFIX_0F01_REG_5_MOD_3_RM_0 */
3076   {
3077     { "serialize",      { Skip_MODRM }, PREFIX_OPCODE },
3078     { "setssbsy",       { Skip_MODRM }, PREFIX_OPCODE },
3079     { Bad_Opcode },
3080     { "xsusldtrk",      { Skip_MODRM }, PREFIX_OPCODE },
3081   },
3082
3083   /* PREFIX_0F01_REG_5_MOD_3_RM_1 */
3084   {
3085     { Bad_Opcode },
3086     { Bad_Opcode },
3087     { Bad_Opcode },
3088     { "xresldtrk",     { Skip_MODRM }, PREFIX_OPCODE },
3089   },
3090
3091   /* PREFIX_0F01_REG_5_MOD_3_RM_2 */
3092   {
3093     { Bad_Opcode },
3094     { "saveprevssp",    { Skip_MODRM }, PREFIX_OPCODE },
3095   },
3096
3097   /* PREFIX_0F01_REG_5_MOD_3_RM_4 */
3098   {
3099     { Bad_Opcode },
3100     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1) },
3101   },
3102
3103   /* PREFIX_0F01_REG_5_MOD_3_RM_5 */
3104   {
3105     { Bad_Opcode },
3106     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1) },
3107   },
3108
3109   /* PREFIX_0F01_REG_5_MOD_3_RM_6 */
3110   {
3111     { "rdpkru", { Skip_MODRM }, 0 },
3112     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1) },
3113   },
3114
3115   /* PREFIX_0F01_REG_5_MOD_3_RM_7 */
3116   {
3117     { "wrpkru", { Skip_MODRM }, 0 },
3118     { X86_64_TABLE (X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1) },
3119   },
3120
3121   /* PREFIX_0F01_REG_7_MOD_3_RM_2 */
3122   {
3123     { "monitorx",       { { OP_Monitor, 0 } }, 0  },
3124     { "mcommit",        { Skip_MODRM }, 0 },
3125   },
3126
3127   /* PREFIX_0F01_REG_7_MOD_3_RM_5 */
3128   {
3129     { "rdpru", { Skip_MODRM }, 0 },
3130     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1) },
3131   },
3132
3133   /* PREFIX_0F01_REG_7_MOD_3_RM_6 */
3134   {
3135     { "invlpgb",        { Skip_MODRM }, 0 },
3136     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1) },
3137     { Bad_Opcode },
3138     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3) },
3139   },
3140
3141   /* PREFIX_0F01_REG_7_MOD_3_RM_7 */
3142   {
3143     { "tlbsync",        { Skip_MODRM }, 0 },
3144     { X86_64_TABLE (X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1) },
3145     { Bad_Opcode },
3146     { "pvalidate",      { Skip_MODRM }, 0 },
3147   },
3148
3149   /* PREFIX_0F09 */
3150   {
3151     { "wbinvd",   { XX }, 0 },
3152     { "wbnoinvd", { XX }, 0 },
3153   },
3154
3155   /* PREFIX_0F10 */
3156   {
3157     { "%XEVmovupX",     { XM, EXEvexXNoBcst }, 0 },
3158     { "%XEVmovs%XS",    { XMScalar, VexScalarR, EXd }, 0 },
3159     { "%XEVmovupX",     { XM, EXEvexXNoBcst }, 0 },
3160     { "%XEVmovs%XD",    { XMScalar, VexScalarR, EXq }, 0 },
3161   },
3162
3163   /* PREFIX_0F11 */
3164   {
3165     { "%XEVmovupX",     { EXxS, XM }, 0 },
3166     { "%XEVmovs%XS",    { EXdS, VexScalarR, XMScalar }, 0 },
3167     { "%XEVmovupX",     { EXxS, XM }, 0 },
3168     { "%XEVmovs%XD",    { EXqS, VexScalarR, XMScalar }, 0 },
3169   },
3170
3171   /* PREFIX_0F12 */
3172   {
3173     { MOD_TABLE (MOD_0F12_PREFIX_0) },
3174     { "movsldup",       { XM, EXx }, 0 },
3175     { "%XEVmovlpYX",    { XM, Vex, Mq }, 0 },
3176     { "movddup",        { XM, EXq }, 0 },
3177   },
3178
3179   /* PREFIX_0F16 */
3180   {
3181     { MOD_TABLE (MOD_0F16_PREFIX_0) },
3182     { "movshdup",       { XM, EXx }, 0 },
3183     { "%XEVmovhpYX",    { XM, Vex, Mq }, 0 },
3184   },
3185
3186   /* PREFIX_0F18_REG_6_MOD_0_X86_64 */
3187   {
3188     { "prefetchit1",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3189     { "nopQ",           { Ev }, 0 },
3190     { "nopQ",           { Ev }, 0 },
3191     { "nopQ",           { Ev }, 0 },
3192   },
3193
3194   /* PREFIX_0F18_REG_7_MOD_0_X86_64 */
3195   {
3196     { "prefetchit0",    { { PREFETCHI_Fixup, b_mode } }, 0 },
3197     { "nopQ",           { Ev }, 0 },
3198     { "nopQ",           { Ev }, 0 },
3199     { "nopQ",           { Ev }, 0 },
3200   },
3201
3202   /* PREFIX_0F1A */
3203   {
3204     { MOD_TABLE (MOD_0F1A_PREFIX_0) },
3205     { "bndcl",  { Gbnd, Ev_bnd }, 0 },
3206     { "bndmov", { Gbnd, Ebnd }, 0 },
3207     { "bndcu",  { Gbnd, Ev_bnd }, 0 },
3208   },
3209
3210   /* PREFIX_0F1B */
3211   {
3212     { MOD_TABLE (MOD_0F1B_PREFIX_0) },
3213     { MOD_TABLE (MOD_0F1B_PREFIX_1) },
3214     { "bndmov", { EbndS, Gbnd }, 0 },
3215     { "bndcn",  { Gbnd, Ev_bnd }, 0 },
3216   },
3217
3218   /* PREFIX_0F1C */
3219   {
3220     { MOD_TABLE (MOD_0F1C_PREFIX_0) },
3221     { "nopQ",   { Ev }, PREFIX_IGNORED },
3222     { "nopQ",   { Ev }, 0 },
3223     { "nopQ",   { Ev }, PREFIX_IGNORED },
3224   },
3225
3226   /* PREFIX_0F1E */
3227   {
3228     { "nopQ",   { Ev }, 0 },
3229     { MOD_TABLE (MOD_0F1E_PREFIX_1) },
3230     { "nopQ",   { Ev }, 0 },
3231     { NULL,     { XX }, PREFIX_IGNORED },
3232   },
3233
3234   /* PREFIX_0F2A */
3235   {
3236     { "cvtpi2ps", { XM, EMCq }, PREFIX_OPCODE },
3237     { "cvtsi2ss{%LQ|}", { XM, Edq }, PREFIX_OPCODE },
3238     { "cvtpi2pd", { XM, EMCq }, PREFIX_OPCODE },
3239     { "cvtsi2sd{%LQ|}", { XM, Edq }, 0 },
3240   },
3241
3242   /* PREFIX_0F2B */
3243   {
3244     { "movntps", { Mx, XM }, 0 },
3245     { "movntss", { Md, XM }, 0 },
3246     { "movntpd", { Mx, XM }, 0 },
3247     { "movntsd", { Mq, XM }, 0 },
3248   },
3249
3250   /* PREFIX_0F2C */
3251   {
3252     { "cvttps2pi", { MXC, EXq }, PREFIX_OPCODE },
3253     { "cvttss2si", { Gdq, EXd }, PREFIX_OPCODE },
3254     { "cvttpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3255     { "cvttsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3256   },
3257
3258   /* PREFIX_0F2D */
3259   {
3260     { "cvtps2pi", { MXC, EXq }, PREFIX_OPCODE },
3261     { "cvtss2si", { Gdq, EXd }, PREFIX_OPCODE },
3262     { "cvtpd2pi", { MXC, EXx }, PREFIX_OPCODE },
3263     { "cvtsd2si", { Gdq, EXq }, PREFIX_OPCODE },
3264   },
3265
3266   /* PREFIX_0F2E */
3267   {
3268     { "%XEVucomisYX",   { XMScalar, EXd, EXxEVexS }, 0 },
3269     { Bad_Opcode },
3270     { "%XEVucomisYX",   { XMScalar, EXq, EXxEVexS }, 0 },
3271   },
3272
3273   /* PREFIX_0F2F */
3274   {
3275     { "%XEVcomisYX",    { XMScalar, EXd, EXxEVexS }, 0 },
3276     { Bad_Opcode },
3277     { "%XEVcomisYX",    { XMScalar, EXq, EXxEVexS }, 0 },
3278   },
3279
3280   /* PREFIX_0F51 */
3281   {
3282     { "%XEVsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3283     { "%XEVsqrts%XS",   { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3284     { "%XEVsqrtpX",     { XM, EXx, EXxEVexR }, 0 },
3285     { "%XEVsqrts%XD",   { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3286   },
3287
3288   /* PREFIX_0F52 */
3289   {
3290     { "Vrsqrtps",       { XM, EXx }, 0 },
3291     { "Vrsqrtss",       { XMScalar, VexScalar, EXd }, 0 },
3292   },
3293
3294   /* PREFIX_0F53 */
3295   {
3296     { "Vrcpps",         { XM, EXx }, 0 },
3297     { "Vrcpss",         { XMScalar, VexScalar, EXd }, 0 },
3298   },
3299
3300   /* PREFIX_0F58 */
3301   {
3302     { "%XEVaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3303     { "%XEVadds%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3304     { "%XEVaddpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3305     { "%XEVadds%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3306   },
3307
3308   /* PREFIX_0F59 */
3309   {
3310     { "%XEVmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3311     { "%XEVmuls%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3312     { "%XEVmulpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3313     { "%XEVmuls%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3314   },
3315
3316   /* PREFIX_0F5A */
3317   {
3318     { "%XEVcvtp%XS2pd", { XM, EXEvexHalfBcstXmmq, EXxEVexS }, 0 },
3319     { "%XEVcvts%XS2sd", { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3320     { "%XEVcvtp%XD2ps%XY", { XMxmmq, EXx, EXxEVexR }, 0 },
3321     { "%XEVcvts%XD2ss", { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3322   },
3323
3324   /* PREFIX_0F5B */
3325   {
3326     { "Vcvtdq2ps",      { XM, EXx }, 0 },
3327     { "Vcvttps2dq",     { XM, EXx }, 0 },
3328     { "Vcvtps2dq",      { XM, EXx }, 0 },
3329   },
3330
3331   /* PREFIX_0F5C */
3332   {
3333     { "%XEVsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3334     { "%XEVsubs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3335     { "%XEVsubpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3336     { "%XEVsubs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3337   },
3338
3339   /* PREFIX_0F5D */
3340   {
3341     { "%XEVminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3342     { "%XEVmins%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3343     { "%XEVminpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3344     { "%XEVmins%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3345   },
3346
3347   /* PREFIX_0F5E */
3348   {
3349     { "%XEVdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3350     { "%XEVdivs%XS",    { XMScalar, VexScalar, EXd, EXxEVexR }, 0 },
3351     { "%XEVdivpX",      { XM, Vex, EXx, EXxEVexR }, 0 },
3352     { "%XEVdivs%XD",    { XMScalar, VexScalar, EXq, EXxEVexR }, 0 },
3353   },
3354
3355   /* PREFIX_0F5F */
3356   {
3357     { "%XEVmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3358     { "%XEVmaxs%XS",    { XMScalar, VexScalar, EXd, EXxEVexS }, 0 },
3359     { "%XEVmaxpX",      { XM, Vex, EXx, EXxEVexS }, 0 },
3360     { "%XEVmaxs%XD",    { XMScalar, VexScalar, EXq, EXxEVexS }, 0 },
3361   },
3362
3363   /* PREFIX_0F60 */
3364   {
3365     { "punpcklbw",{ MX, EMd }, PREFIX_OPCODE },
3366     { Bad_Opcode },
3367     { "punpcklbw",{ MX, EMx }, PREFIX_OPCODE },
3368   },
3369
3370   /* PREFIX_0F61 */
3371   {
3372     { "punpcklwd",{ MX, EMd }, PREFIX_OPCODE },
3373     { Bad_Opcode },
3374     { "punpcklwd",{ MX, EMx }, PREFIX_OPCODE },
3375   },
3376
3377   /* PREFIX_0F62 */
3378   {
3379     { "punpckldq",{ MX, EMd }, PREFIX_OPCODE },
3380     { Bad_Opcode },
3381     { "punpckldq",{ MX, EMx }, PREFIX_OPCODE },
3382   },
3383
3384   /* PREFIX_0F6F */
3385   {
3386     { "movq",   { MX, EM }, PREFIX_OPCODE },
3387     { "movdqu", { XM, EXx }, PREFIX_OPCODE },
3388     { "movdqa", { XM, EXx }, PREFIX_OPCODE },
3389   },
3390
3391   /* PREFIX_0F70 */
3392   {
3393     { "pshufw", { MX, EM, Ib }, PREFIX_OPCODE },
3394     { "pshufhw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3395     { "pshufd", { XM, EXx, Ib }, PREFIX_OPCODE },
3396     { "pshuflw",{ XM, EXx, Ib }, PREFIX_OPCODE },
3397   },
3398
3399   /* PREFIX_0F78 */
3400   {
3401     {"vmread",  { Em, Gm }, 0 },
3402     { Bad_Opcode },
3403     {"extrq",   { Uxmm, Ib, Ib }, 0 },
3404     {"insertq", { XM, Uxmm, Ib, Ib }, 0 },
3405   },
3406
3407   /* PREFIX_0F79 */
3408   {
3409     {"vmwrite", { Gm, Em }, 0 },
3410     { Bad_Opcode },
3411     {"extrq",   { XM, Uxmm }, 0 },
3412     {"insertq", { XM, Uxmm }, 0 },
3413   },
3414
3415   /* PREFIX_0F7C */
3416   {
3417     { Bad_Opcode },
3418     { Bad_Opcode },
3419     { "Vhaddpd",        { XM, Vex, EXx }, 0 },
3420     { "Vhaddps",        { XM, Vex, EXx }, 0 },
3421   },
3422
3423   /* PREFIX_0F7D */
3424   {
3425     { Bad_Opcode },
3426     { Bad_Opcode },
3427     { "Vhsubpd",        { XM, Vex, EXx }, 0 },
3428     { "Vhsubps",        { XM, Vex, EXx }, 0 },
3429   },
3430
3431   /* PREFIX_0F7E */
3432   {
3433     { "movK",   { Edq, MX }, PREFIX_OPCODE },
3434     { "movq",   { XM, EXq }, PREFIX_OPCODE },
3435     { "movK",   { Edq, XM }, PREFIX_OPCODE },
3436   },
3437
3438   /* PREFIX_0F7F */
3439   {
3440     { "movq",   { EMS, MX }, PREFIX_OPCODE },
3441     { "movdqu", { EXxS, XM }, PREFIX_OPCODE },
3442     { "movdqa", { EXxS, XM }, PREFIX_OPCODE },
3443   },
3444
3445   /* PREFIX_0FAE_REG_0_MOD_3 */
3446   {
3447     { Bad_Opcode },
3448     { "rdfsbase", { Ev }, 0 },
3449   },
3450
3451   /* PREFIX_0FAE_REG_1_MOD_3 */
3452   {
3453     { Bad_Opcode },
3454     { "rdgsbase", { Ev }, 0 },
3455   },
3456
3457   /* PREFIX_0FAE_REG_2_MOD_3 */
3458   {
3459     { Bad_Opcode },
3460     { "wrfsbase", { Ev }, 0 },
3461   },
3462
3463   /* PREFIX_0FAE_REG_3_MOD_3 */
3464   {
3465     { Bad_Opcode },
3466     { "wrgsbase", { Ev }, 0 },
3467   },
3468
3469   /* PREFIX_0FAE_REG_4_MOD_0 */
3470   {
3471     { "xsave",  { FXSAVE }, PREFIX_REX2_ILLEGAL },
3472     { "ptwrite{%LQ|}", { Edq }, 0 },
3473   },
3474
3475   /* PREFIX_0FAE_REG_4_MOD_3 */
3476   {
3477     { Bad_Opcode },
3478     { "ptwrite{%LQ|}", { Edq }, 0 },
3479   },
3480
3481   /* PREFIX_0FAE_REG_5_MOD_3 */
3482   {
3483     { "lfence",         { Skip_MODRM }, 0 },
3484     { "incsspK",        { Edq }, PREFIX_OPCODE },
3485   },
3486
3487   /* PREFIX_0FAE_REG_6_MOD_0 */
3488   {
3489     { "xsaveopt",       { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
3490     { "clrssbsy",       { Mq }, PREFIX_OPCODE },
3491     { "clwb",   { Mb }, PREFIX_OPCODE },
3492   },
3493
3494   /* PREFIX_0FAE_REG_6_MOD_3 */
3495   {
3496     { RM_TABLE (RM_0FAE_REG_6_MOD_3_P_0) },
3497     { "umonitor",       { Eva }, PREFIX_OPCODE },
3498     { "tpause", { Edq }, PREFIX_OPCODE },
3499     { "umwait", { Edq }, PREFIX_OPCODE },
3500   },
3501
3502   /* PREFIX_0FAE_REG_7_MOD_0 */
3503   {
3504     { "clflush",        { Mb }, 0 },
3505     { Bad_Opcode },
3506     { "clflushopt",     { Mb }, 0 },
3507   },
3508
3509   /* PREFIX_0FB8 */
3510   {
3511     { Bad_Opcode },
3512     { "popcntS", { Gv, Ev }, 0 },
3513   },
3514
3515   /* PREFIX_0FBC */
3516   {
3517     { "bsfS",   { Gv, Ev }, 0 },
3518     { "tzcntS", { Gv, Ev }, 0 },
3519     { "bsfS",   { Gv, Ev }, 0 },
3520   },
3521
3522   /* PREFIX_0FBD */
3523   {
3524     { "bsrS",   { Gv, Ev }, 0 },
3525     { "lzcntS", { Gv, Ev }, 0 },
3526     { "bsrS",   { Gv, Ev }, 0 },
3527   },
3528
3529   /* PREFIX_0FC2 */
3530   {
3531     { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3532     { "Vcmpss", { XMScalar, VexScalar, EXd, CMP }, 0 },
3533     { "VcmppX", { XM, Vex, EXx, CMP }, 0 },
3534     { "Vcmpsd", { XMScalar, VexScalar, EXq, CMP }, 0 },
3535   },
3536
3537   /* PREFIX_0FC7_REG_6_MOD_0 */
3538   {
3539     { "vmptrld",{ Mq }, 0 },
3540     { "vmxon",  { Mq }, 0 },
3541     { "vmclear",{ Mq }, 0 },
3542   },
3543
3544   /* PREFIX_0FC7_REG_6_MOD_3 */
3545   {
3546     { "rdrand", { Ev }, 0 },
3547     { X86_64_TABLE (X86_64_0FC7_REG_6_MOD_3_PREFIX_1) },
3548     { "rdrand", { Ev }, 0 }
3549   },
3550
3551   /* PREFIX_0FC7_REG_7_MOD_3 */
3552   {
3553     { "rdseed", { Ev }, 0 },
3554     { "rdpid",  { Em }, 0 },
3555     { "rdseed", { Ev }, 0 },
3556   },
3557
3558   /* PREFIX_0FD0 */
3559   {
3560     { Bad_Opcode },
3561     { Bad_Opcode },
3562     { "VaddsubpX",      { XM, Vex, EXx }, 0 },
3563     { "VaddsubpX",      { XM, Vex, EXx }, 0 },
3564   },
3565
3566   /* PREFIX_0FD6 */
3567   {
3568     { Bad_Opcode },
3569     { "movq2dq",{ XM, Nq }, 0 },
3570     { "movq",   { EXqS, XM }, 0 },
3571     { "movdq2q",{ MX, Ux }, 0 },
3572   },
3573
3574   /* PREFIX_0FE6 */
3575   {
3576     { Bad_Opcode },
3577     { "Vcvtdq2pd",      { XM, EXxmmq }, 0 },
3578     { "Vcvttpd2dq%XY",  { XMM, EXx }, 0 },
3579     { "Vcvtpd2dq%XY",   { XMM, EXx }, 0 },
3580   },
3581
3582   /* PREFIX_0FE7 */
3583   {
3584     { "movntq",         { Mq, MX }, 0 },
3585     { Bad_Opcode },
3586     { "movntdq",        { Mx, XM }, 0 },
3587   },
3588
3589   /* PREFIX_0FF0 */
3590   {
3591     { Bad_Opcode },
3592     { Bad_Opcode },
3593     { Bad_Opcode },
3594     { "Vlddqu",         { XM, M }, 0 },
3595   },
3596
3597   /* PREFIX_0FF7 */
3598   {
3599     { "maskmovq", { MX, Nq }, PREFIX_OPCODE },
3600     { Bad_Opcode },
3601     { "maskmovdqu", { XM, Ux }, PREFIX_OPCODE },
3602   },
3603
3604   /* PREFIX_0F38D8 */
3605   {
3606     { Bad_Opcode },
3607     { REG_TABLE (REG_0F38D8_PREFIX_1) },
3608   },
3609
3610   /* PREFIX_0F38DC */
3611   {
3612     { Bad_Opcode },
3613     { MOD_TABLE (MOD_0F38DC_PREFIX_1) },
3614     { "aesenc", { XM, EXx }, 0 },
3615   },
3616
3617   /* PREFIX_0F38DD */
3618   {
3619     { Bad_Opcode },
3620     { "aesdec128kl", { XM, M }, 0 },
3621     { "aesenclast", { XM, EXx }, 0 },
3622   },
3623
3624   /* PREFIX_0F38DE */
3625   {
3626     { Bad_Opcode },
3627     { "aesenc256kl", { XM, M }, 0 },
3628     { "aesdec", { XM, EXx }, 0 },
3629   },
3630
3631   /* PREFIX_0F38DF */
3632   {
3633     { Bad_Opcode },
3634     { "aesdec256kl", { XM, M }, 0 },
3635     { "aesdeclast", { XM, EXx }, 0 },
3636   },
3637
3638   /* PREFIX_0F38F0 */
3639   {
3640     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3641     { Bad_Opcode },
3642     { "movbeS", { Gv, Mv }, PREFIX_OPCODE },
3643     { "crc32A", { Gdq, Eb }, PREFIX_OPCODE },
3644   },
3645
3646   /* PREFIX_0F38F1 */
3647   {
3648     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3649     { Bad_Opcode },
3650     { "movbeS", { Mv, Gv }, PREFIX_OPCODE },
3651     { "crc32Q", { Gdq, Ev }, PREFIX_OPCODE },
3652   },
3653
3654   /* PREFIX_0F38F6 */
3655   {
3656     { "wrssK",  { M, Gdq }, 0 },
3657     { "adoxL",  { VexGdq, Gdq, Edq }, 0 },
3658     { "adcxL",  { VexGdq, Gdq, Edq }, 0 },
3659     { Bad_Opcode },
3660   },
3661
3662   /* PREFIX_0F38F8_M_0 */
3663   {
3664     { Bad_Opcode },
3665     { "enqcmds", { Gva, M }, 0 },
3666     { "movdir64b", { Gva, M }, 0 },
3667     { "enqcmd", { Gva, M }, 0 },
3668   },
3669
3670   /* PREFIX_0F38F8_M_1_X86_64 */
3671   {
3672     { Bad_Opcode },
3673     { "uwrmsr",         { Gq, Rq }, 0 },
3674     { Bad_Opcode },
3675     { "urdmsr",         { Rq, Gq }, 0 },
3676   },
3677
3678   /* PREFIX_0F38FA */
3679   {
3680     { Bad_Opcode },
3681     { "encodekey128", { Gd, Rd }, 0 },
3682   },
3683
3684   /* PREFIX_0F38FB */
3685   {
3686     { Bad_Opcode },
3687     { "encodekey256", { Gd, Rd }, 0 },
3688   },
3689
3690   /* PREFIX_0F38FC */
3691   {
3692     { "aadd",   { Mdq, Gdq }, 0 },
3693     { "axor",   { Mdq, Gdq }, 0 },
3694     { "aand",   { Mdq, Gdq }, 0 },
3695     { "aor",    { Mdq, Gdq }, 0 },
3696   },
3697
3698   /* PREFIX_0F3A0F */
3699   {
3700     { Bad_Opcode },
3701     { REG_TABLE (REG_0F3A0F_P_1) },
3702   },
3703
3704   /* PREFIX_VEX_0F12 */
3705   {
3706     { VEX_LEN_TABLE (VEX_LEN_0F12_P_0) },
3707     { "%XEvmov%XSldup", { XM, EXEvexXNoBcst }, 0 },
3708     { VEX_LEN_TABLE (VEX_LEN_0F12_P_2) },
3709     { "%XEvmov%XDdup",  { XM, EXymmq }, 0 },
3710   },
3711
3712   /* PREFIX_VEX_0F16 */
3713   {
3714     { VEX_LEN_TABLE (VEX_LEN_0F16_P_0) },
3715     { "%XEvmov%XShdup", { XM, EXEvexXNoBcst }, 0 },
3716     { VEX_LEN_TABLE (VEX_LEN_0F16_P_2) },
3717   },
3718
3719   /* PREFIX_VEX_0F2A */
3720   {
3721     { Bad_Opcode },
3722     { "%XEvcvtsi2ssY{%LQ|}",    { XMScalar, VexScalar, EXxEVexR, Edq }, 0 },
3723     { Bad_Opcode },
3724     { "%XEvcvtsi2sdY{%LQ|}",    { XMScalar, VexScalar, EXxEVexR64, Edq }, 0 },
3725   },
3726
3727   /* PREFIX_VEX_0F2C */
3728   {
3729     { Bad_Opcode },
3730     { "%XEvcvttss2si",  { Gdq, EXd, EXxEVexS }, 0 },
3731     { Bad_Opcode },
3732     { "%XEvcvttsd2si",  { Gdq, EXq, EXxEVexS }, 0 },
3733   },
3734
3735   /* PREFIX_VEX_0F2D */
3736   {
3737     { Bad_Opcode },
3738     { "%XEvcvtss2si",   { Gdq, EXd, EXxEVexR }, 0 },
3739     { Bad_Opcode },
3740     { "%XEvcvtsd2si",   { Gdq, EXq, EXxEVexR }, 0 },
3741   },
3742
3743   /* PREFIX_VEX_0F41_L_1_W_0 */
3744   {
3745     { "kandw",          { MaskG, MaskVex, MaskR }, 0 },
3746     { Bad_Opcode },
3747     { "kandb",          { MaskG, MaskVex, MaskR }, 0 },
3748   },
3749
3750   /* PREFIX_VEX_0F41_L_1_W_1 */
3751   {
3752     { "kandq",          { MaskG, MaskVex, MaskR }, 0 },
3753     { Bad_Opcode },
3754     { "kandd",          { MaskG, MaskVex, MaskR }, 0 },
3755   },
3756
3757   /* PREFIX_VEX_0F42_L_1_W_0 */
3758   {
3759     { "kandnw",         { MaskG, MaskVex, MaskR }, 0 },
3760     { Bad_Opcode },
3761     { "kandnb",         { MaskG, MaskVex, MaskR }, 0 },
3762   },
3763
3764   /* PREFIX_VEX_0F42_L_1_W_1 */
3765   {
3766     { "kandnq",         { MaskG, MaskVex, MaskR }, 0 },
3767     { Bad_Opcode },
3768     { "kandnd",         { MaskG, MaskVex, MaskR }, 0 },
3769   },
3770
3771   /* PREFIX_VEX_0F44_L_0_W_0 */
3772   {
3773     { "knotw",          { MaskG, MaskR }, 0 },
3774     { Bad_Opcode },
3775     { "knotb",          { MaskG, MaskR }, 0 },
3776   },
3777
3778   /* PREFIX_VEX_0F44_L_0_W_1 */
3779   {
3780     { "knotq",          { MaskG, MaskR }, 0 },
3781     { Bad_Opcode },
3782     { "knotd",          { MaskG, MaskR }, 0 },
3783   },
3784
3785   /* PREFIX_VEX_0F45_L_1_W_0 */
3786   {
3787     { "korw",       { MaskG, MaskVex, MaskR }, 0 },
3788     { Bad_Opcode },
3789     { "korb",       { MaskG, MaskVex, MaskR }, 0 },
3790   },
3791
3792   /* PREFIX_VEX_0F45_L_1_W_1 */
3793   {
3794     { "korq",       { MaskG, MaskVex, MaskR }, 0 },
3795     { Bad_Opcode },
3796     { "kord",       { MaskG, MaskVex, MaskR }, 0 },
3797   },
3798
3799   /* PREFIX_VEX_0F46_L_1_W_0 */
3800   {
3801     { "kxnorw",     { MaskG, MaskVex, MaskR }, 0 },
3802     { Bad_Opcode },
3803     { "kxnorb",     { MaskG, MaskVex, MaskR }, 0 },
3804   },
3805
3806   /* PREFIX_VEX_0F46_L_1_W_1 */
3807   {
3808     { "kxnorq",     { MaskG, MaskVex, MaskR }, 0 },
3809     { Bad_Opcode },
3810     { "kxnord",     { MaskG, MaskVex, MaskR }, 0 },
3811   },
3812
3813   /* PREFIX_VEX_0F47_L_1_W_0 */
3814   {
3815     { "kxorw",      { MaskG, MaskVex, MaskR }, 0 },
3816     { Bad_Opcode },
3817     { "kxorb",      { MaskG, MaskVex, MaskR }, 0 },
3818   },
3819
3820   /* PREFIX_VEX_0F47_L_1_W_1 */
3821   {
3822     { "kxorq",      { MaskG, MaskVex, MaskR }, 0 },
3823     { Bad_Opcode },
3824     { "kxord",      { MaskG, MaskVex, MaskR }, 0 },
3825   },
3826
3827   /* PREFIX_VEX_0F4A_L_1_W_0 */
3828   {
3829     { "kaddw",          { MaskG, MaskVex, MaskR }, 0 },
3830     { Bad_Opcode },
3831     { "kaddb",          { MaskG, MaskVex, MaskR }, 0 },
3832   },
3833
3834   /* PREFIX_VEX_0F4A_L_1_W_1 */
3835   {
3836     { "kaddq",          { MaskG, MaskVex, MaskR }, 0 },
3837     { Bad_Opcode },
3838     { "kaddd",          { MaskG, MaskVex, MaskR }, 0 },
3839   },
3840
3841   /* PREFIX_VEX_0F4B_L_1_W_0 */
3842   {
3843     { "kunpckwd",   { MaskG, MaskVex, MaskR }, 0 },
3844     { Bad_Opcode },
3845     { "kunpckbw",   { MaskG, MaskVex, MaskR }, 0 },
3846   },
3847
3848   /* PREFIX_VEX_0F4B_L_1_W_1 */
3849   {
3850     { "kunpckdq",   { MaskG, MaskVex, MaskR }, 0 },
3851   },
3852
3853   /* PREFIX_VEX_0F6F */
3854   {
3855     { Bad_Opcode },
3856     { "vmovdqu",        { XM, EXx }, 0 },
3857     { "vmovdqa",        { XM, EXx }, 0 },
3858   },
3859
3860   /* PREFIX_VEX_0F70 */
3861   {
3862     { Bad_Opcode },
3863     { "vpshufhw",       { XM, EXx, Ib }, 0 },
3864     { "vpshufd",        { XM, EXx, Ib }, 0 },
3865     { "vpshuflw",       { XM, EXx, Ib }, 0 },
3866   },
3867
3868   /* PREFIX_VEX_0F7E */
3869   {
3870     { Bad_Opcode },
3871     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_1) },
3872     { VEX_LEN_TABLE (VEX_LEN_0F7E_P_2) },
3873   },
3874
3875   /* PREFIX_VEX_0F7F */
3876   {
3877     { Bad_Opcode },
3878     { "vmovdqu",        { EXxS, XM }, 0 },
3879     { "vmovdqa",        { EXxS, XM }, 0 },
3880   },
3881
3882   /* PREFIX_VEX_0F90_L_0_W_0 */
3883   {
3884     { "kmovw",          { MaskG, MaskE }, 0 },
3885     { Bad_Opcode },
3886     { "kmovb",          { MaskG, MaskBDE }, 0 },
3887   },
3888
3889   /* PREFIX_VEX_0F90_L_0_W_1 */
3890   {
3891     { "kmovq",          { MaskG, MaskE }, 0 },
3892     { Bad_Opcode },
3893     { "kmovd",          { MaskG, MaskBDE }, 0 },
3894   },
3895
3896   /* PREFIX_VEX_0F91_L_0_W_0 */
3897   {
3898     { "kmovw",          { Mw, MaskG }, 0 },
3899     { Bad_Opcode },
3900     { "kmovb",          { Mb, MaskG }, 0 },
3901   },
3902
3903   /* PREFIX_VEX_0F91_L_0_W_1 */
3904   {
3905     { "kmovq",          { Mq, MaskG }, 0 },
3906     { Bad_Opcode },
3907     { "kmovd",          { Md, MaskG }, 0 },
3908   },
3909
3910   /* PREFIX_VEX_0F92_L_0_W_0 */
3911   {
3912     { "kmovw",          { MaskG, Rdq }, 0 },
3913     { Bad_Opcode },
3914     { "kmovb",          { MaskG, Rdq }, 0 },
3915     { "kmovd",          { MaskG, Rdq }, 0 },
3916   },
3917
3918   /* PREFIX_VEX_0F92_L_0_W_1 */
3919   {
3920     { Bad_Opcode },
3921     { Bad_Opcode },
3922     { Bad_Opcode },
3923     { "kmovK",          { MaskG, Rdq }, 0 },
3924   },
3925
3926   /* PREFIX_VEX_0F93_L_0_W_0 */
3927   {
3928     { "kmovw",          { Gdq, MaskR }, 0 },
3929     { Bad_Opcode },
3930     { "kmovb",          { Gdq, MaskR }, 0 },
3931     { "kmovd",          { Gdq, MaskR }, 0 },
3932   },
3933
3934   /* PREFIX_VEX_0F93_L_0_W_1 */
3935   {
3936     { Bad_Opcode },
3937     { Bad_Opcode },
3938     { Bad_Opcode },
3939     { "kmovK",          { Gdq, MaskR }, 0 },
3940   },
3941
3942   /* PREFIX_VEX_0F98_L_0_W_0 */
3943   {
3944     { "kortestw", { MaskG, MaskR }, 0 },
3945     { Bad_Opcode },
3946     { "kortestb", { MaskG, MaskR }, 0 },
3947   },
3948
3949   /* PREFIX_VEX_0F98_L_0_W_1 */
3950   {
3951     { "kortestq", { MaskG, MaskR }, 0 },
3952     { Bad_Opcode },
3953     { "kortestd", { MaskG, MaskR }, 0 },
3954   },
3955
3956   /* PREFIX_VEX_0F99_L_0_W_0 */
3957   {
3958     { "ktestw", { MaskG, MaskR }, 0 },
3959     { Bad_Opcode },
3960     { "ktestb", { MaskG, MaskR }, 0 },
3961   },
3962
3963   /* PREFIX_VEX_0F99_L_0_W_1 */
3964   {
3965     { "ktestq", { MaskG, MaskR }, 0 },
3966     { Bad_Opcode },
3967     { "ktestd", { MaskG, MaskR }, 0 },
3968   },
3969
3970   /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0 */
3971   {
3972     { "ldtilecfg", { M }, 0 },
3973     { Bad_Opcode },
3974     { "sttilecfg", { M }, 0 },
3975   },
3976
3977   /* PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1 */
3978   {
3979     { REG_TABLE (REG_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0) },
3980     { Bad_Opcode },
3981     { Bad_Opcode },
3982     { RM_TABLE (RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3) },
3983   },
3984
3985   /* PREFIX_VEX_0F384B_X86_64_L_0_W_0 */
3986   {
3987     { Bad_Opcode },
3988     { "tilestored",     { MVexSIBMEM, TMM }, 0 },
3989     { "tileloaddt1",    { TMM, MVexSIBMEM }, 0 },
3990     { "tileloadd",      { TMM, MVexSIBMEM }, 0 },
3991   },
3992
3993   /* PREFIX_VEX_0F3850_W_0 */
3994   {
3995     { "vpdpbuud",       { XM, Vex, EXx }, 0 },
3996     { "vpdpbsud",       { XM, Vex, EXx }, 0 },
3997     { "%XVvpdpbusd",    { XM, Vex, EXx }, 0 },
3998     { "vpdpbssd",       { XM, Vex, EXx }, 0 },
3999   },
4000
4001   /* PREFIX_VEX_0F3851_W_0 */
4002   {
4003     { "vpdpbuuds",      { XM, Vex, EXx }, 0 },
4004     { "vpdpbsuds",      { XM, Vex, EXx }, 0 },
4005     { "%XVvpdpbusds",   { XM, Vex, EXx }, 0 },
4006     { "vpdpbssds",      { XM, Vex, EXx }, 0 },
4007   },
4008   /* PREFIX_VEX_0F385C_X86_64_L_0_W_0 */
4009   {
4010     { Bad_Opcode },
4011     { "tdpbf16ps", { TMM, Rtmm, VexTmm }, 0 },
4012     { Bad_Opcode },
4013     { "tdpfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4014   },
4015
4016   /* PREFIX_VEX_0F385E_X86_64_L_0_W_0 */
4017   {
4018     { "tdpbuud", {TMM, Rtmm, VexTmm }, 0 },
4019     { "tdpbsud", {TMM, Rtmm, VexTmm }, 0 },
4020     { "tdpbusd", {TMM, Rtmm, VexTmm }, 0 },
4021     { "tdpbssd", {TMM, Rtmm, VexTmm }, 0 },
4022   },
4023
4024   /* PREFIX_VEX_0F386C_X86_64_L_0_W_0 */
4025   {
4026     { "tcmmrlfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4027     { Bad_Opcode },
4028     { "tcmmimfp16ps", { TMM, Rtmm, VexTmm }, 0 },
4029   },
4030
4031   /* PREFIX_VEX_0F3872 */
4032   {
4033     { Bad_Opcode },
4034     { VEX_W_TABLE (VEX_W_0F3872_P_1) },
4035   },
4036
4037   /* PREFIX_VEX_0F38B0_W_0 */
4038   {
4039     { "vcvtneoph2ps", { XM, Mx }, 0 },
4040     { "vcvtneebf162ps", { XM, Mx }, 0 },
4041     { "vcvtneeph2ps", { XM, Mx }, 0 },
4042     { "vcvtneobf162ps", { XM, Mx }, 0 },
4043   },
4044
4045   /* PREFIX_VEX_0F38B1_W_0 */
4046   {
4047     { Bad_Opcode },
4048     { "vbcstnebf162ps", { XM, Mw }, 0 },
4049     { "vbcstnesh2ps", { XM, Mw }, 0 },
4050   },
4051
4052   /* PREFIX_VEX_0F38D2_W_0 */
4053   {
4054     { "vpdpwuud",       { XM, Vex, EXx }, 0 },
4055     { "vpdpwsud",       { XM, Vex, EXx }, 0 },
4056     { "vpdpwusd",       { XM, Vex, EXx }, 0 },
4057   },
4058
4059   /* PREFIX_VEX_0F38D3_W_0 */
4060   {
4061     { "vpdpwuuds",      { XM, Vex, EXx }, 0 },
4062     { "vpdpwsuds",      { XM, Vex, EXx }, 0 },
4063     { "vpdpwusds",      { XM, Vex, EXx }, 0 },
4064   },
4065
4066   /* PREFIX_VEX_0F38CB */
4067   {
4068     { Bad_Opcode },
4069     { Bad_Opcode },
4070     { Bad_Opcode },
4071     { VEX_W_TABLE (VEX_W_0F38CB_P_3) },
4072   },
4073
4074   /* PREFIX_VEX_0F38CC */
4075   {
4076     { Bad_Opcode },
4077     { Bad_Opcode },
4078     { Bad_Opcode },
4079     { VEX_W_TABLE (VEX_W_0F38CC_P_3) },
4080   },
4081
4082   /* PREFIX_VEX_0F38CD */
4083   {
4084     { Bad_Opcode },
4085     { Bad_Opcode },
4086     { Bad_Opcode },
4087     { VEX_W_TABLE (VEX_W_0F38CD_P_3) },
4088   },
4089
4090   /* PREFIX_VEX_0F38DA_W_0 */
4091   {
4092     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_0) },
4093     { "vsm4key4", { XM, Vex, EXx }, 0 },
4094     { VEX_LEN_TABLE (VEX_LEN_0F38DA_W_0_P_2) },
4095     { "vsm4rnds4", { XM, Vex, EXx }, 0 },
4096   },
4097
4098   /* PREFIX_VEX_0F38F2_L_0 */
4099   {
4100     { "andnS",          { Gdq, VexGdq, Edq }, 0 },
4101   },
4102
4103   /* PREFIX_VEX_0F38F3_L_0 */
4104   {
4105     { REG_TABLE (REG_VEX_0F38F3_L_0_P_0) },
4106   },
4107
4108   /* PREFIX_VEX_0F38F5_L_0 */
4109   {
4110     { "bzhiS",          { Gdq, Edq, VexGdq }, 0 },
4111     { "pextS",          { Gdq, VexGdq, Edq }, 0 },
4112     { Bad_Opcode },
4113     { "pdepS",          { Gdq, VexGdq, Edq }, 0 },
4114   },
4115
4116   /* PREFIX_VEX_0F38F6_L_0 */
4117   {
4118     { Bad_Opcode },
4119     { Bad_Opcode },
4120     { Bad_Opcode },
4121     { "mulxS",          { Gdq, VexGdq, Edq }, 0 },
4122   },
4123
4124   /* PREFIX_VEX_0F38F7_L_0 */
4125   {
4126     { "bextrS",         { Gdq, Edq, VexGdq }, 0 },
4127     { "sarxS",          { Gdq, Edq, VexGdq }, 0 },
4128     { "shlxS",          { Gdq, Edq, VexGdq }, 0 },
4129     { "shrxS",          { Gdq, Edq, VexGdq }, 0 },
4130   },
4131
4132   /* PREFIX_VEX_0F3AF0_L_0 */
4133   {
4134     { Bad_Opcode },
4135     { Bad_Opcode },
4136     { Bad_Opcode },
4137     { "rorxS",          { Gdq, Edq, Ib }, 0 },
4138   },
4139
4140   /* PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64 */
4141   {
4142     { Bad_Opcode },
4143     { "uwrmsr", { Skip_MODRM, Id, Rq }, 0 },
4144     { Bad_Opcode },
4145     { "urdmsr", { Rq, Id }, 0 },
4146   },
4147
4148 #include "i386-dis-evex-prefix.h"
4149 };
4150
4151 static const struct dis386 x86_64_table[][2] = {
4152   /* X86_64_06 */
4153   {
4154     { "pushP", { es }, 0 },
4155   },
4156
4157   /* X86_64_07 */
4158   {
4159     { "popP", { es }, 0 },
4160   },
4161
4162   /* X86_64_0E */
4163   {
4164     { "pushP", { cs }, 0 },
4165   },
4166
4167   /* X86_64_16 */
4168   {
4169     { "pushP", { ss }, 0 },
4170   },
4171
4172   /* X86_64_17 */
4173   {
4174     { "popP", { ss }, 0 },
4175   },
4176
4177   /* X86_64_1E */
4178   {
4179     { "pushP", { ds }, 0 },
4180   },
4181
4182   /* X86_64_1F */
4183   {
4184     { "popP", { ds }, 0 },
4185   },
4186
4187   /* X86_64_27 */
4188   {
4189     { "daa", { XX }, 0 },
4190   },
4191
4192   /* X86_64_2F */
4193   {
4194     { "das", { XX }, 0 },
4195   },
4196
4197   /* X86_64_37 */
4198   {
4199     { "aaa", { XX }, 0 },
4200   },
4201
4202   /* X86_64_3F */
4203   {
4204     { "aas", { XX }, 0 },
4205   },
4206
4207   /* X86_64_60 */
4208   {
4209     { "pushaP", { XX }, 0 },
4210   },
4211
4212   /* X86_64_61 */
4213   {
4214     { "popaP", { XX }, 0 },
4215   },
4216
4217   /* X86_64_62 */
4218   {
4219     { MOD_TABLE (MOD_62_32BIT) },
4220     { EVEX_TABLE () },
4221   },
4222
4223   /* X86_64_63 */
4224   {
4225     { "arplS", { Sv, Gv }, 0 },
4226     { "movs", { Gv, { MOVSXD_Fixup, movsxd_mode } }, 0 },
4227   },
4228
4229   /* X86_64_6D */
4230   {
4231     { "ins{R|}", { Yzr, indirDX }, 0 },
4232     { "ins{G|}", { Yzr, indirDX }, 0 },
4233   },
4234
4235   /* X86_64_6F */
4236   {
4237     { "outs{R|}", { indirDXr, Xz }, 0 },
4238     { "outs{G|}", { indirDXr, Xz }, 0 },
4239   },
4240
4241   /* X86_64_82 */
4242   {
4243     /* Opcode 0x82 is an alias of opcode 0x80 in 32-bit mode.  */
4244     { REG_TABLE (REG_80) },
4245   },
4246
4247   /* X86_64_9A */
4248   {
4249     { "{l|}call{P|}", { Ap }, 0 },
4250   },
4251
4252   /* X86_64_C2 */
4253   {
4254     { "retP",           { Iw, BND }, 0 },
4255     { "ret@",           { Iw, BND }, 0 },
4256   },
4257
4258   /* X86_64_C3 */
4259   {
4260     { "retP",           { BND }, 0 },
4261     { "ret@",           { BND }, 0 },
4262   },
4263
4264   /* X86_64_C4 */
4265   {
4266     { MOD_TABLE (MOD_C4_32BIT) },
4267     { VEX_C4_TABLE () },
4268   },
4269
4270   /* X86_64_C5 */
4271   {
4272     { MOD_TABLE (MOD_C5_32BIT) },
4273     { VEX_C5_TABLE () },
4274   },
4275
4276   /* X86_64_CE */
4277   {
4278     { "into", { XX }, 0 },
4279   },
4280
4281   /* X86_64_D4 */
4282   {
4283     { "aam", { Ib }, 0 },
4284   },
4285
4286   /* X86_64_D5 */
4287   {
4288     { "aad", { Ib }, 0 },
4289   },
4290
4291   /* X86_64_E8 */
4292   {
4293     { "callP",          { Jv, BND }, 0 },
4294     { "call@",          { Jv, BND }, PREFIX_REX2_ILLEGAL }
4295   },
4296
4297   /* X86_64_E9 */
4298   {
4299     { "jmpP",           { Jv, BND }, 0 },
4300     { "jmp@",           { Jv, BND }, PREFIX_REX2_ILLEGAL }
4301   },
4302
4303   /* X86_64_EA */
4304   {
4305     { "{l|}jmp{P|}", { Ap }, 0 },
4306   },
4307
4308   /* X86_64_0F00_REG_6 */
4309   {
4310     { Bad_Opcode },
4311     { PREFIX_TABLE (PREFIX_0F00_REG_6_X86_64) },
4312   },
4313
4314   /* X86_64_0F01_REG_0 */
4315   {
4316     { "sgdt{Q|Q}", { M }, 0 },
4317     { "sgdt", { M }, 0 },
4318   },
4319
4320   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_1 */
4321   {
4322     { Bad_Opcode },
4323     { "wrmsrlist",      { Skip_MODRM }, 0 },
4324   },
4325
4326   /* X86_64_0F01_REG_0_MOD_3_RM_6_P_3 */
4327   {
4328     { Bad_Opcode },
4329     { "rdmsrlist",      { Skip_MODRM }, 0 },
4330   },
4331
4332   /* X86_64_0F01_REG_0_MOD_3_RM_7_P_0 */
4333   {
4334     { Bad_Opcode },
4335     { "pbndkb",         { Skip_MODRM }, 0 },
4336   },
4337
4338   /* X86_64_0F01_REG_1 */
4339   {
4340     { "sidt{Q|Q}", { M }, 0 },
4341     { "sidt", { M }, 0 },
4342   },
4343
4344   /* X86_64_0F01_REG_1_RM_2_PREFIX_1 */
4345   {
4346     { Bad_Opcode },
4347     { "eretu",          { Skip_MODRM }, 0 },
4348   },
4349
4350   /* X86_64_0F01_REG_1_RM_2_PREFIX_3 */
4351   {
4352     { Bad_Opcode },
4353     { "erets",          { Skip_MODRM }, 0 },
4354   },
4355
4356   /* X86_64_0F01_REG_1_RM_5_PREFIX_2 */
4357   {
4358     { Bad_Opcode },
4359     { "seamret",        { Skip_MODRM }, 0 },
4360   },
4361
4362   /* X86_64_0F01_REG_1_RM_6_PREFIX_2 */
4363   {
4364     { Bad_Opcode },
4365     { "seamops",        { Skip_MODRM }, 0 },
4366   },
4367
4368   /* X86_64_0F01_REG_1_RM_7_PREFIX_2 */
4369   {
4370     { Bad_Opcode },
4371     { "seamcall",       { Skip_MODRM }, 0 },
4372   },
4373
4374   /* X86_64_0F01_REG_2 */
4375   {
4376     { "lgdt{Q|Q}", { M }, 0 },
4377     { "lgdt", { M }, 0 },
4378   },
4379
4380   /* X86_64_0F01_REG_3 */
4381   {
4382     { "lidt{Q|Q}", { M }, 0 },
4383     { "lidt", { M }, 0 },
4384   },
4385
4386   /* X86_64_0F01_REG_5_MOD_3_RM_4_PREFIX_1 */
4387   {
4388     { Bad_Opcode },
4389     { "uiret",  { Skip_MODRM }, 0 },
4390   },
4391
4392   /* X86_64_0F01_REG_5_MOD_3_RM_5_PREFIX_1 */
4393   {
4394     { Bad_Opcode },
4395     { "testui", { Skip_MODRM }, 0 },
4396   },
4397
4398   /* X86_64_0F01_REG_5_MOD_3_RM_6_PREFIX_1 */
4399   {
4400     { Bad_Opcode },
4401     { "clui",   { Skip_MODRM }, 0 },
4402   },
4403
4404   /* X86_64_0F01_REG_5_MOD_3_RM_7_PREFIX_1 */
4405   {
4406     { Bad_Opcode },
4407     { "stui",   { Skip_MODRM }, 0 },
4408   },
4409
4410   /* X86_64_0F01_REG_7_MOD_3_RM_5_PREFIX_1 */
4411   {
4412     { Bad_Opcode },
4413     { "rmpquery", { Skip_MODRM }, 0 },
4414   },
4415
4416   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_1 */
4417   {
4418     { Bad_Opcode },
4419     { "rmpadjust",      { Skip_MODRM }, 0 },
4420   },
4421
4422   /* X86_64_0F01_REG_7_MOD_3_RM_6_PREFIX_3 */
4423   {
4424     { Bad_Opcode },
4425     { "rmpupdate",      { Skip_MODRM }, 0 },
4426   },
4427
4428   /* X86_64_0F01_REG_7_MOD_3_RM_7_PREFIX_1 */
4429   {
4430     { Bad_Opcode },
4431     { "psmash", { Skip_MODRM }, 0 },
4432   },
4433
4434   /* X86_64_0F18_REG_6_MOD_0 */
4435   {
4436     { "nopQ",           { Ev }, 0 },
4437     { PREFIX_TABLE (PREFIX_0F18_REG_6_MOD_0_X86_64) },
4438   },
4439
4440   /* X86_64_0F18_REG_7_MOD_0 */
4441   {
4442     { "nopQ",           { Ev }, 0 },
4443     { PREFIX_TABLE (PREFIX_0F18_REG_7_MOD_0_X86_64) },
4444   },
4445
4446   {
4447     /* X86_64_0F24 */
4448     { "movZ",           { Em, Td }, 0 },
4449   },
4450
4451   {
4452     /* X86_64_0F26 */
4453     { "movZ",           { Td, Em }, 0 },
4454   },
4455
4456   {
4457     /* X86_64_0F38F8_M_1 */
4458     { Bad_Opcode },
4459     { PREFIX_TABLE (PREFIX_0F38F8_M_1_X86_64) },
4460   },
4461
4462   /* X86_64_0FC7_REG_6_MOD_3_PREFIX_1 */
4463   {
4464     { Bad_Opcode },
4465     { "senduipi",       { Eq }, 0 },
4466   },
4467
4468   /* X86_64_VEX_0F3849 */
4469   {
4470     { Bad_Opcode },
4471     { VEX_LEN_TABLE (VEX_LEN_0F3849_X86_64) },
4472   },
4473
4474   /* X86_64_VEX_0F384B */
4475   {
4476     { Bad_Opcode },
4477     { VEX_LEN_TABLE (VEX_LEN_0F384B_X86_64) },
4478   },
4479
4480   /* X86_64_VEX_0F385C */
4481   {
4482     { Bad_Opcode },
4483     { VEX_LEN_TABLE (VEX_LEN_0F385C_X86_64) },
4484   },
4485
4486   /* X86_64_VEX_0F385E */
4487   {
4488     { Bad_Opcode },
4489     { VEX_LEN_TABLE (VEX_LEN_0F385E_X86_64) },
4490   },
4491
4492   /* X86_64_VEX_0F386C */
4493   {
4494     { Bad_Opcode },
4495     { VEX_LEN_TABLE (VEX_LEN_0F386C_X86_64) },
4496   },
4497
4498   /* X86_64_VEX_0F38E0 */
4499   {
4500     { Bad_Opcode },
4501     { "cmpoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4502   },
4503
4504   /* X86_64_VEX_0F38E1 */
4505   {
4506     { Bad_Opcode },
4507     { "cmpnoxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4508   },
4509
4510   /* X86_64_VEX_0F38E2 */
4511   {
4512     { Bad_Opcode },
4513     { "cmpbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4514   },
4515
4516   /* X86_64_VEX_0F38E3 */
4517   {
4518     { Bad_Opcode },
4519     { "cmpnbxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4520   },
4521
4522   /* X86_64_VEX_0F38E4 */
4523   {
4524     { Bad_Opcode },
4525     { "cmpzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4526   },
4527
4528   /* X86_64_VEX_0F38E5 */
4529   {
4530     { Bad_Opcode },
4531     { "cmpnzxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4532   },
4533
4534   /* X86_64_VEX_0F38E6 */
4535   {
4536     { Bad_Opcode },
4537     { "cmpbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4538   },
4539
4540   /* X86_64_VEX_0F38E7 */
4541   {
4542     { Bad_Opcode },
4543     { "cmpnbexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4544   },
4545
4546   /* X86_64_VEX_0F38E8 */
4547   {
4548     { Bad_Opcode },
4549     { "cmpsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4550   },
4551
4552   /* X86_64_VEX_0F38E9 */
4553   {
4554     { Bad_Opcode },
4555     { "cmpnsxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4556   },
4557
4558   /* X86_64_VEX_0F38EA */
4559   {
4560     { Bad_Opcode },
4561     { "cmppxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4562   },
4563
4564   /* X86_64_VEX_0F38EB */
4565   {
4566     { Bad_Opcode },
4567     { "cmpnpxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4568   },
4569
4570   /* X86_64_VEX_0F38EC */
4571   {
4572     { Bad_Opcode },
4573     { "cmplxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4574   },
4575
4576   /* X86_64_VEX_0F38ED */
4577   {
4578     { Bad_Opcode },
4579     { "cmpnlxadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4580   },
4581
4582   /* X86_64_VEX_0F38EE */
4583   {
4584     { Bad_Opcode },
4585     { "cmplexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4586   },
4587
4588   /* X86_64_VEX_0F38EF */
4589   {
4590     { Bad_Opcode },
4591     { "cmpnlexadd", { Mdq, Gdq, VexGdq }, PREFIX_DATA },
4592   },
4593
4594   /* X86_64_VEX_MAP7_F8_L_0_W_0_R_0 */
4595   {
4596     { Bad_Opcode },
4597     { PREFIX_TABLE (PREFIX_VEX_MAP7_F8_L_0_W_0_R_0_X86_64) },
4598   },
4599
4600 #include "i386-dis-evex-x86-64.h"
4601 };
4602
4603 static const struct dis386 three_byte_table[][256] = {
4604
4605   /* THREE_BYTE_0F38 */
4606   {
4607     /* 00 */
4608     { "pshufb",         { MX, EM }, PREFIX_OPCODE },
4609     { "phaddw",         { MX, EM }, PREFIX_OPCODE },
4610     { "phaddd",         { MX, EM }, PREFIX_OPCODE },
4611     { "phaddsw",        { MX, EM }, PREFIX_OPCODE },
4612     { "pmaddubsw",      { MX, EM }, PREFIX_OPCODE },
4613     { "phsubw",         { MX, EM }, PREFIX_OPCODE },
4614     { "phsubd",         { MX, EM }, PREFIX_OPCODE },
4615     { "phsubsw",        { MX, EM }, PREFIX_OPCODE },
4616     /* 08 */
4617     { "psignb",         { MX, EM }, PREFIX_OPCODE },
4618     { "psignw",         { MX, EM }, PREFIX_OPCODE },
4619     { "psignd",         { MX, EM }, PREFIX_OPCODE },
4620     { "pmulhrsw",       { MX, EM }, PREFIX_OPCODE },
4621     { Bad_Opcode },
4622     { Bad_Opcode },
4623     { Bad_Opcode },
4624     { Bad_Opcode },
4625     /* 10 */
4626     { "pblendvb", { XM, EXx, XMM0 }, PREFIX_DATA },
4627     { Bad_Opcode },
4628     { Bad_Opcode },
4629     { Bad_Opcode },
4630     { "blendvps", { XM, EXx, XMM0 }, PREFIX_DATA },
4631     { "blendvpd", { XM, EXx, XMM0 }, PREFIX_DATA },
4632     { Bad_Opcode },
4633     { "ptest",  { XM, EXx }, PREFIX_DATA },
4634     /* 18 */
4635     { Bad_Opcode },
4636     { Bad_Opcode },
4637     { Bad_Opcode },
4638     { Bad_Opcode },
4639     { "pabsb",          { MX, EM }, PREFIX_OPCODE },
4640     { "pabsw",          { MX, EM }, PREFIX_OPCODE },
4641     { "pabsd",          { MX, EM }, PREFIX_OPCODE },
4642     { Bad_Opcode },
4643     /* 20 */
4644     { "pmovsxbw", { XM, EXq }, PREFIX_DATA },
4645     { "pmovsxbd", { XM, EXd }, PREFIX_DATA },
4646     { "pmovsxbq", { XM, EXw }, PREFIX_DATA },
4647     { "pmovsxwd", { XM, EXq }, PREFIX_DATA },
4648     { "pmovsxwq", { XM, EXd }, PREFIX_DATA },
4649     { "pmovsxdq", { XM, EXq }, PREFIX_DATA },
4650     { Bad_Opcode },
4651     { Bad_Opcode },
4652     /* 28 */
4653     { "pmuldq", { XM, EXx }, PREFIX_DATA },
4654     { "pcmpeqq", { XM, EXx }, PREFIX_DATA },
4655     { "movntdqa", { XM, Mx }, PREFIX_DATA },
4656     { "packusdw", { XM, EXx }, PREFIX_DATA },
4657     { Bad_Opcode },
4658     { Bad_Opcode },
4659     { Bad_Opcode },
4660     { Bad_Opcode },
4661     /* 30 */
4662     { "pmovzxbw", { XM, EXq }, PREFIX_DATA },
4663     { "pmovzxbd", { XM, EXd }, PREFIX_DATA },
4664     { "pmovzxbq", { XM, EXw }, PREFIX_DATA },
4665     { "pmovzxwd", { XM, EXq }, PREFIX_DATA },
4666     { "pmovzxwq", { XM, EXd }, PREFIX_DATA },
4667     { "pmovzxdq", { XM, EXq }, PREFIX_DATA },
4668     { Bad_Opcode },
4669     { "pcmpgtq", { XM, EXx }, PREFIX_DATA },
4670     /* 38 */
4671     { "pminsb", { XM, EXx }, PREFIX_DATA },
4672     { "pminsd", { XM, EXx }, PREFIX_DATA },
4673     { "pminuw", { XM, EXx }, PREFIX_DATA },
4674     { "pminud", { XM, EXx }, PREFIX_DATA },
4675     { "pmaxsb", { XM, EXx }, PREFIX_DATA },
4676     { "pmaxsd", { XM, EXx }, PREFIX_DATA },
4677     { "pmaxuw", { XM, EXx }, PREFIX_DATA },
4678     { "pmaxud", { XM, EXx }, PREFIX_DATA },
4679     /* 40 */
4680     { "pmulld", { XM, EXx }, PREFIX_DATA },
4681     { "phminposuw", { XM, EXx }, PREFIX_DATA },
4682     { Bad_Opcode },
4683     { Bad_Opcode },
4684     { Bad_Opcode },
4685     { Bad_Opcode },
4686     { Bad_Opcode },
4687     { Bad_Opcode },
4688     /* 48 */
4689     { Bad_Opcode },
4690     { Bad_Opcode },
4691     { Bad_Opcode },
4692     { Bad_Opcode },
4693     { Bad_Opcode },
4694     { Bad_Opcode },
4695     { Bad_Opcode },
4696     { Bad_Opcode },
4697     /* 50 */
4698     { Bad_Opcode },
4699     { Bad_Opcode },
4700     { Bad_Opcode },
4701     { Bad_Opcode },
4702     { Bad_Opcode },
4703     { Bad_Opcode },
4704     { Bad_Opcode },
4705     { Bad_Opcode },
4706     /* 58 */
4707     { Bad_Opcode },
4708     { Bad_Opcode },
4709     { Bad_Opcode },
4710     { Bad_Opcode },
4711     { Bad_Opcode },
4712     { Bad_Opcode },
4713     { Bad_Opcode },
4714     { Bad_Opcode },
4715     /* 60 */
4716     { Bad_Opcode },
4717     { Bad_Opcode },
4718     { Bad_Opcode },
4719     { Bad_Opcode },
4720     { Bad_Opcode },
4721     { Bad_Opcode },
4722     { Bad_Opcode },
4723     { Bad_Opcode },
4724     /* 68 */
4725     { Bad_Opcode },
4726     { Bad_Opcode },
4727     { Bad_Opcode },
4728     { Bad_Opcode },
4729     { Bad_Opcode },
4730     { Bad_Opcode },
4731     { Bad_Opcode },
4732     { Bad_Opcode },
4733     /* 70 */
4734     { Bad_Opcode },
4735     { Bad_Opcode },
4736     { Bad_Opcode },
4737     { Bad_Opcode },
4738     { Bad_Opcode },
4739     { Bad_Opcode },
4740     { Bad_Opcode },
4741     { Bad_Opcode },
4742     /* 78 */
4743     { Bad_Opcode },
4744     { Bad_Opcode },
4745     { Bad_Opcode },
4746     { Bad_Opcode },
4747     { Bad_Opcode },
4748     { Bad_Opcode },
4749     { Bad_Opcode },
4750     { Bad_Opcode },
4751     /* 80 */
4752     { "invept", { Gm, Mo }, PREFIX_DATA },
4753     { "invvpid", { Gm, Mo }, PREFIX_DATA },
4754     { "invpcid", { Gm, M }, PREFIX_DATA },
4755     { Bad_Opcode },
4756     { Bad_Opcode },
4757     { Bad_Opcode },
4758     { Bad_Opcode },
4759     { Bad_Opcode },
4760     /* 88 */
4761     { Bad_Opcode },
4762     { Bad_Opcode },
4763     { Bad_Opcode },
4764     { Bad_Opcode },
4765     { Bad_Opcode },
4766     { Bad_Opcode },
4767     { Bad_Opcode },
4768     { Bad_Opcode },
4769     /* 90 */
4770     { Bad_Opcode },
4771     { Bad_Opcode },
4772     { Bad_Opcode },
4773     { Bad_Opcode },
4774     { Bad_Opcode },
4775     { Bad_Opcode },
4776     { Bad_Opcode },
4777     { Bad_Opcode },
4778     /* 98 */
4779     { Bad_Opcode },
4780     { Bad_Opcode },
4781     { Bad_Opcode },
4782     { Bad_Opcode },
4783     { Bad_Opcode },
4784     { Bad_Opcode },
4785     { Bad_Opcode },
4786     { Bad_Opcode },
4787     /* a0 */
4788     { Bad_Opcode },
4789     { Bad_Opcode },
4790     { Bad_Opcode },
4791     { Bad_Opcode },
4792     { Bad_Opcode },
4793     { Bad_Opcode },
4794     { Bad_Opcode },
4795     { Bad_Opcode },
4796     /* a8 */
4797     { Bad_Opcode },
4798     { Bad_Opcode },
4799     { Bad_Opcode },
4800     { Bad_Opcode },
4801     { Bad_Opcode },
4802     { Bad_Opcode },
4803     { Bad_Opcode },
4804     { Bad_Opcode },
4805     /* b0 */
4806     { Bad_Opcode },
4807     { Bad_Opcode },
4808     { Bad_Opcode },
4809     { Bad_Opcode },
4810     { Bad_Opcode },
4811     { Bad_Opcode },
4812     { Bad_Opcode },
4813     { Bad_Opcode },
4814     /* b8 */
4815     { Bad_Opcode },
4816     { Bad_Opcode },
4817     { Bad_Opcode },
4818     { Bad_Opcode },
4819     { Bad_Opcode },
4820     { Bad_Opcode },
4821     { Bad_Opcode },
4822     { Bad_Opcode },
4823     /* c0 */
4824     { Bad_Opcode },
4825     { Bad_Opcode },
4826     { Bad_Opcode },
4827     { Bad_Opcode },
4828     { Bad_Opcode },
4829     { Bad_Opcode },
4830     { Bad_Opcode },
4831     { Bad_Opcode },
4832     /* c8 */
4833     { "sha1nexte", { XM, EXxmm }, PREFIX_OPCODE },
4834     { "sha1msg1", { XM, EXxmm }, PREFIX_OPCODE },
4835     { "sha1msg2", { XM, EXxmm }, PREFIX_OPCODE },
4836     { "sha256rnds2", { XM, EXxmm, XMM0 }, PREFIX_OPCODE },
4837     { "sha256msg1", { XM, EXxmm }, PREFIX_OPCODE },
4838     { "sha256msg2", { XM, EXxmm }, PREFIX_OPCODE },
4839     { Bad_Opcode },
4840     { "gf2p8mulb", { XM, EXxmm }, PREFIX_DATA },
4841     /* d0 */
4842     { Bad_Opcode },
4843     { Bad_Opcode },
4844     { Bad_Opcode },
4845     { Bad_Opcode },
4846     { Bad_Opcode },
4847     { Bad_Opcode },
4848     { Bad_Opcode },
4849     { Bad_Opcode },
4850     /* d8 */
4851     { PREFIX_TABLE (PREFIX_0F38D8) },
4852     { Bad_Opcode },
4853     { Bad_Opcode },
4854     { "aesimc", { XM, EXx }, PREFIX_DATA },
4855     { PREFIX_TABLE (PREFIX_0F38DC) },
4856     { PREFIX_TABLE (PREFIX_0F38DD) },
4857     { PREFIX_TABLE (PREFIX_0F38DE) },
4858     { PREFIX_TABLE (PREFIX_0F38DF) },
4859     /* e0 */
4860     { Bad_Opcode },
4861     { Bad_Opcode },
4862     { Bad_Opcode },
4863     { Bad_Opcode },
4864     { Bad_Opcode },
4865     { Bad_Opcode },
4866     { Bad_Opcode },
4867     { Bad_Opcode },
4868     /* e8 */
4869     { Bad_Opcode },
4870     { Bad_Opcode },
4871     { Bad_Opcode },
4872     { Bad_Opcode },
4873     { Bad_Opcode },
4874     { Bad_Opcode },
4875     { Bad_Opcode },
4876     { Bad_Opcode },
4877     /* f0 */
4878     { PREFIX_TABLE (PREFIX_0F38F0) },
4879     { PREFIX_TABLE (PREFIX_0F38F1) },
4880     { Bad_Opcode },
4881     { Bad_Opcode },
4882     { Bad_Opcode },
4883     { "wrussK",         { M, Gdq }, PREFIX_DATA },
4884     { PREFIX_TABLE (PREFIX_0F38F6) },
4885     { Bad_Opcode },
4886     /* f8 */
4887     { MOD_TABLE (MOD_0F38F8) },
4888     { "movdiri",        { Mdq, Gdq }, PREFIX_OPCODE },
4889     { PREFIX_TABLE (PREFIX_0F38FA) },
4890     { PREFIX_TABLE (PREFIX_0F38FB) },
4891     { PREFIX_TABLE (PREFIX_0F38FC) },
4892     { Bad_Opcode },
4893     { Bad_Opcode },
4894     { Bad_Opcode },
4895   },
4896   /* THREE_BYTE_0F3A */
4897   {
4898     /* 00 */
4899     { Bad_Opcode },
4900     { Bad_Opcode },
4901     { Bad_Opcode },
4902     { Bad_Opcode },
4903     { Bad_Opcode },
4904     { Bad_Opcode },
4905     { Bad_Opcode },
4906     { Bad_Opcode },
4907     /* 08 */
4908     { "roundps", { XM, EXx, Ib }, PREFIX_DATA },
4909     { "roundpd", { XM, EXx, Ib }, PREFIX_DATA },
4910     { "roundss", { XM, EXd, Ib }, PREFIX_DATA },
4911     { "roundsd", { XM, EXq, Ib }, PREFIX_DATA },
4912     { "blendps", { XM, EXx, Ib }, PREFIX_DATA },
4913     { "blendpd", { XM, EXx, Ib }, PREFIX_DATA },
4914     { "pblendw", { XM, EXx, Ib }, PREFIX_DATA },
4915     { "palignr",        { MX, EM, Ib }, PREFIX_OPCODE },
4916     /* 10 */
4917     { Bad_Opcode },
4918     { Bad_Opcode },
4919     { Bad_Opcode },
4920     { Bad_Opcode },
4921     { "pextrb", { Edb, XM, Ib }, PREFIX_DATA },
4922     { "pextrw", { Edw, XM, Ib }, PREFIX_DATA },
4923     { "pextrK", { Edq, XM, Ib }, PREFIX_DATA },
4924     { "extractps", { Ed, XM, Ib }, PREFIX_DATA },
4925     /* 18 */
4926     { Bad_Opcode },
4927     { Bad_Opcode },
4928     { Bad_Opcode },
4929     { Bad_Opcode },
4930     { Bad_Opcode },
4931     { Bad_Opcode },
4932     { Bad_Opcode },
4933     { Bad_Opcode },
4934     /* 20 */
4935     { "pinsrb", { XM, Edb, Ib }, PREFIX_DATA },
4936     { "insertps", { XM, EXd, Ib }, PREFIX_DATA },
4937     { "pinsrK", { XM, Edq, Ib }, PREFIX_DATA },
4938     { Bad_Opcode },
4939     { Bad_Opcode },
4940     { Bad_Opcode },
4941     { Bad_Opcode },
4942     { Bad_Opcode },
4943     /* 28 */
4944     { Bad_Opcode },
4945     { Bad_Opcode },
4946     { Bad_Opcode },
4947     { Bad_Opcode },
4948     { Bad_Opcode },
4949     { Bad_Opcode },
4950     { Bad_Opcode },
4951     { Bad_Opcode },
4952     /* 30 */
4953     { Bad_Opcode },
4954     { Bad_Opcode },
4955     { Bad_Opcode },
4956     { Bad_Opcode },
4957     { Bad_Opcode },
4958     { Bad_Opcode },
4959     { Bad_Opcode },
4960     { Bad_Opcode },
4961     /* 38 */
4962     { Bad_Opcode },
4963     { Bad_Opcode },
4964     { Bad_Opcode },
4965     { Bad_Opcode },
4966     { Bad_Opcode },
4967     { Bad_Opcode },
4968     { Bad_Opcode },
4969     { Bad_Opcode },
4970     /* 40 */
4971     { "dpps",   { XM, EXx, Ib }, PREFIX_DATA },
4972     { "dppd",   { XM, EXx, Ib }, PREFIX_DATA },
4973     { "mpsadbw", { XM, EXx, Ib }, PREFIX_DATA },
4974     { Bad_Opcode },
4975     { "pclmulqdq", { XM, EXx, PCLMUL }, PREFIX_DATA },
4976     { Bad_Opcode },
4977     { Bad_Opcode },
4978     { Bad_Opcode },
4979     /* 48 */
4980     { Bad_Opcode },
4981     { Bad_Opcode },
4982     { Bad_Opcode },
4983     { Bad_Opcode },
4984     { Bad_Opcode },
4985     { Bad_Opcode },
4986     { Bad_Opcode },
4987     { Bad_Opcode },
4988     /* 50 */
4989     { Bad_Opcode },
4990     { Bad_Opcode },
4991     { Bad_Opcode },
4992     { Bad_Opcode },
4993     { Bad_Opcode },
4994     { Bad_Opcode },
4995     { Bad_Opcode },
4996     { Bad_Opcode },
4997     /* 58 */
4998     { Bad_Opcode },
4999     { Bad_Opcode },
5000     { Bad_Opcode },
5001     { Bad_Opcode },
5002     { Bad_Opcode },
5003     { Bad_Opcode },
5004     { Bad_Opcode },
5005     { Bad_Opcode },
5006     /* 60 */
5007     { "pcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5008     { "pcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
5009     { "pcmpistrm", { XM, EXx, Ib }, PREFIX_DATA },
5010     { "pcmpistri", { XM, EXx, Ib }, PREFIX_DATA },
5011     { Bad_Opcode },
5012     { Bad_Opcode },
5013     { Bad_Opcode },
5014     { Bad_Opcode },
5015     /* 68 */
5016     { Bad_Opcode },
5017     { Bad_Opcode },
5018     { Bad_Opcode },
5019     { Bad_Opcode },
5020     { Bad_Opcode },
5021     { Bad_Opcode },
5022     { Bad_Opcode },
5023     { Bad_Opcode },
5024     /* 70 */
5025     { Bad_Opcode },
5026     { Bad_Opcode },
5027     { Bad_Opcode },
5028     { Bad_Opcode },
5029     { Bad_Opcode },
5030     { Bad_Opcode },
5031     { Bad_Opcode },
5032     { Bad_Opcode },
5033     /* 78 */
5034     { Bad_Opcode },
5035     { Bad_Opcode },
5036     { Bad_Opcode },
5037     { Bad_Opcode },
5038     { Bad_Opcode },
5039     { Bad_Opcode },
5040     { Bad_Opcode },
5041     { Bad_Opcode },
5042     /* 80 */
5043     { Bad_Opcode },
5044     { Bad_Opcode },
5045     { Bad_Opcode },
5046     { Bad_Opcode },
5047     { Bad_Opcode },
5048     { Bad_Opcode },
5049     { Bad_Opcode },
5050     { Bad_Opcode },
5051     /* 88 */
5052     { Bad_Opcode },
5053     { Bad_Opcode },
5054     { Bad_Opcode },
5055     { Bad_Opcode },
5056     { Bad_Opcode },
5057     { Bad_Opcode },
5058     { Bad_Opcode },
5059     { Bad_Opcode },
5060     /* 90 */
5061     { Bad_Opcode },
5062     { Bad_Opcode },
5063     { Bad_Opcode },
5064     { Bad_Opcode },
5065     { Bad_Opcode },
5066     { Bad_Opcode },
5067     { Bad_Opcode },
5068     { Bad_Opcode },
5069     /* 98 */
5070     { Bad_Opcode },
5071     { Bad_Opcode },
5072     { Bad_Opcode },
5073     { Bad_Opcode },
5074     { Bad_Opcode },
5075     { Bad_Opcode },
5076     { Bad_Opcode },
5077     { Bad_Opcode },
5078     /* a0 */
5079     { Bad_Opcode },
5080     { Bad_Opcode },
5081     { Bad_Opcode },
5082     { Bad_Opcode },
5083     { Bad_Opcode },
5084     { Bad_Opcode },
5085     { Bad_Opcode },
5086     { Bad_Opcode },
5087     /* a8 */
5088     { Bad_Opcode },
5089     { Bad_Opcode },
5090     { Bad_Opcode },
5091     { Bad_Opcode },
5092     { Bad_Opcode },
5093     { Bad_Opcode },
5094     { Bad_Opcode },
5095     { Bad_Opcode },
5096     /* b0 */
5097     { Bad_Opcode },
5098     { Bad_Opcode },
5099     { Bad_Opcode },
5100     { Bad_Opcode },
5101     { Bad_Opcode },
5102     { Bad_Opcode },
5103     { Bad_Opcode },
5104     { Bad_Opcode },
5105     /* b8 */
5106     { Bad_Opcode },
5107     { Bad_Opcode },
5108     { Bad_Opcode },
5109     { Bad_Opcode },
5110     { Bad_Opcode },
5111     { Bad_Opcode },
5112     { Bad_Opcode },
5113     { Bad_Opcode },
5114     /* c0 */
5115     { Bad_Opcode },
5116     { Bad_Opcode },
5117     { Bad_Opcode },
5118     { Bad_Opcode },
5119     { Bad_Opcode },
5120     { Bad_Opcode },
5121     { Bad_Opcode },
5122     { Bad_Opcode },
5123     /* c8 */
5124     { Bad_Opcode },
5125     { Bad_Opcode },
5126     { Bad_Opcode },
5127     { Bad_Opcode },
5128     { "sha1rnds4", { XM, EXxmm, Ib }, PREFIX_OPCODE },
5129     { Bad_Opcode },
5130     { "gf2p8affineqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5131     { "gf2p8affineinvqb", { XM, EXxmm, Ib }, PREFIX_DATA },
5132     /* d0 */
5133     { Bad_Opcode },
5134     { Bad_Opcode },
5135     { Bad_Opcode },
5136     { Bad_Opcode },
5137     { Bad_Opcode },
5138     { Bad_Opcode },
5139     { Bad_Opcode },
5140     { Bad_Opcode },
5141     /* d8 */
5142     { Bad_Opcode },
5143     { Bad_Opcode },
5144     { Bad_Opcode },
5145     { Bad_Opcode },
5146     { Bad_Opcode },
5147     { Bad_Opcode },
5148     { Bad_Opcode },
5149     { "aeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
5150     /* e0 */
5151     { Bad_Opcode },
5152     { Bad_Opcode },
5153     { Bad_Opcode },
5154     { Bad_Opcode },
5155     { Bad_Opcode },
5156     { Bad_Opcode },
5157     { Bad_Opcode },
5158     { Bad_Opcode },
5159     /* e8 */
5160     { Bad_Opcode },
5161     { Bad_Opcode },
5162     { Bad_Opcode },
5163     { Bad_Opcode },
5164     { Bad_Opcode },
5165     { Bad_Opcode },
5166     { Bad_Opcode },
5167     { Bad_Opcode },
5168     /* f0 */
5169     { PREFIX_TABLE (PREFIX_0F3A0F) },
5170     { Bad_Opcode },
5171     { Bad_Opcode },
5172     { Bad_Opcode },
5173     { Bad_Opcode },
5174     { Bad_Opcode },
5175     { Bad_Opcode },
5176     { Bad_Opcode },
5177     /* f8 */
5178     { Bad_Opcode },
5179     { Bad_Opcode },
5180     { Bad_Opcode },
5181     { Bad_Opcode },
5182     { Bad_Opcode },
5183     { Bad_Opcode },
5184     { Bad_Opcode },
5185     { Bad_Opcode },
5186   },
5187 };
5188
5189 static const struct dis386 xop_table[][256] = {
5190   /* XOP_08 */
5191   {
5192     /* 00 */
5193     { Bad_Opcode },
5194     { Bad_Opcode },
5195     { Bad_Opcode },
5196     { Bad_Opcode },
5197     { Bad_Opcode },
5198     { Bad_Opcode },
5199     { Bad_Opcode },
5200     { Bad_Opcode },
5201     /* 08 */
5202     { Bad_Opcode },
5203     { Bad_Opcode },
5204     { Bad_Opcode },
5205     { Bad_Opcode },
5206     { Bad_Opcode },
5207     { Bad_Opcode },
5208     { Bad_Opcode },
5209     { Bad_Opcode },
5210     /* 10 */
5211     { Bad_Opcode },
5212     { Bad_Opcode },
5213     { Bad_Opcode },
5214     { Bad_Opcode },
5215     { Bad_Opcode },
5216     { Bad_Opcode },
5217     { Bad_Opcode },
5218     { Bad_Opcode },
5219     /* 18 */
5220     { Bad_Opcode },
5221     { Bad_Opcode },
5222     { Bad_Opcode },
5223     { Bad_Opcode },
5224     { Bad_Opcode },
5225     { Bad_Opcode },
5226     { Bad_Opcode },
5227     { Bad_Opcode },
5228     /* 20 */
5229     { Bad_Opcode },
5230     { Bad_Opcode },
5231     { Bad_Opcode },
5232     { Bad_Opcode },
5233     { Bad_Opcode },
5234     { Bad_Opcode },
5235     { Bad_Opcode },
5236     { Bad_Opcode },
5237     /* 28 */
5238     { Bad_Opcode },
5239     { Bad_Opcode },
5240     { Bad_Opcode },
5241     { Bad_Opcode },
5242     { Bad_Opcode },
5243     { Bad_Opcode },
5244     { Bad_Opcode },
5245     { Bad_Opcode },
5246     /* 30 */
5247     { Bad_Opcode },
5248     { Bad_Opcode },
5249     { Bad_Opcode },
5250     { Bad_Opcode },
5251     { Bad_Opcode },
5252     { Bad_Opcode },
5253     { Bad_Opcode },
5254     { Bad_Opcode },
5255     /* 38 */
5256     { Bad_Opcode },
5257     { Bad_Opcode },
5258     { Bad_Opcode },
5259     { Bad_Opcode },
5260     { Bad_Opcode },
5261     { Bad_Opcode },
5262     { Bad_Opcode },
5263     { Bad_Opcode },
5264     /* 40 */
5265     { Bad_Opcode },
5266     { Bad_Opcode },
5267     { Bad_Opcode },
5268     { Bad_Opcode },
5269     { Bad_Opcode },
5270     { Bad_Opcode },
5271     { Bad_Opcode },
5272     { Bad_Opcode },
5273     /* 48 */
5274     { Bad_Opcode },
5275     { Bad_Opcode },
5276     { Bad_Opcode },
5277     { Bad_Opcode },
5278     { Bad_Opcode },
5279     { Bad_Opcode },
5280     { Bad_Opcode },
5281     { Bad_Opcode },
5282     /* 50 */
5283     { Bad_Opcode },
5284     { Bad_Opcode },
5285     { Bad_Opcode },
5286     { Bad_Opcode },
5287     { Bad_Opcode },
5288     { Bad_Opcode },
5289     { Bad_Opcode },
5290     { Bad_Opcode },
5291     /* 58 */
5292     { Bad_Opcode },
5293     { Bad_Opcode },
5294     { Bad_Opcode },
5295     { Bad_Opcode },
5296     { Bad_Opcode },
5297     { Bad_Opcode },
5298     { Bad_Opcode },
5299     { Bad_Opcode },
5300     /* 60 */
5301     { Bad_Opcode },
5302     { Bad_Opcode },
5303     { Bad_Opcode },
5304     { Bad_Opcode },
5305     { Bad_Opcode },
5306     { Bad_Opcode },
5307     { Bad_Opcode },
5308     { Bad_Opcode },
5309     /* 68 */
5310     { Bad_Opcode },
5311     { Bad_Opcode },
5312     { Bad_Opcode },
5313     { Bad_Opcode },
5314     { Bad_Opcode },
5315     { Bad_Opcode },
5316     { Bad_Opcode },
5317     { Bad_Opcode },
5318     /* 70 */
5319     { Bad_Opcode },
5320     { Bad_Opcode },
5321     { Bad_Opcode },
5322     { Bad_Opcode },
5323     { Bad_Opcode },
5324     { Bad_Opcode },
5325     { Bad_Opcode },
5326     { Bad_Opcode },
5327     /* 78 */
5328     { Bad_Opcode },
5329     { Bad_Opcode },
5330     { Bad_Opcode },
5331     { Bad_Opcode },
5332     { Bad_Opcode },
5333     { Bad_Opcode },
5334     { Bad_Opcode },
5335     { Bad_Opcode },
5336     /* 80 */
5337     { Bad_Opcode },
5338     { Bad_Opcode },
5339     { Bad_Opcode },
5340     { Bad_Opcode },
5341     { Bad_Opcode },
5342     { VEX_LEN_TABLE (VEX_LEN_XOP_08_85) },
5343     { VEX_LEN_TABLE (VEX_LEN_XOP_08_86) },
5344     { VEX_LEN_TABLE (VEX_LEN_XOP_08_87) },
5345     /* 88 */
5346     { Bad_Opcode },
5347     { Bad_Opcode },
5348     { Bad_Opcode },
5349     { Bad_Opcode },
5350     { Bad_Opcode },
5351     { Bad_Opcode },
5352     { VEX_LEN_TABLE (VEX_LEN_XOP_08_8E) },
5353     { VEX_LEN_TABLE (VEX_LEN_XOP_08_8F) },
5354     /* 90 */
5355     { Bad_Opcode },
5356     { Bad_Opcode },
5357     { Bad_Opcode },
5358     { Bad_Opcode },
5359     { Bad_Opcode },
5360     { VEX_LEN_TABLE (VEX_LEN_XOP_08_95) },
5361     { VEX_LEN_TABLE (VEX_LEN_XOP_08_96) },
5362     { VEX_LEN_TABLE (VEX_LEN_XOP_08_97) },
5363     /* 98 */
5364     { Bad_Opcode },
5365     { Bad_Opcode },
5366     { Bad_Opcode },
5367     { Bad_Opcode },
5368     { Bad_Opcode },
5369     { Bad_Opcode },
5370     { VEX_LEN_TABLE (VEX_LEN_XOP_08_9E) },
5371     { VEX_LEN_TABLE (VEX_LEN_XOP_08_9F) },
5372     /* a0 */
5373     { Bad_Opcode },
5374     { Bad_Opcode },
5375     { "vpcmov",         { XM, Vex, EXx, XMVexI4 }, 0 },
5376     { VEX_LEN_TABLE (VEX_LEN_XOP_08_A3) },
5377     { Bad_Opcode },
5378     { Bad_Opcode },
5379     { VEX_LEN_TABLE (VEX_LEN_XOP_08_A6) },
5380     { Bad_Opcode },
5381     /* a8 */
5382     { Bad_Opcode },
5383     { Bad_Opcode },
5384     { Bad_Opcode },
5385     { Bad_Opcode },
5386     { Bad_Opcode },
5387     { Bad_Opcode },
5388     { Bad_Opcode },
5389     { Bad_Opcode },
5390     /* b0 */
5391     { Bad_Opcode },
5392     { Bad_Opcode },
5393     { Bad_Opcode },
5394     { Bad_Opcode },
5395     { Bad_Opcode },
5396     { Bad_Opcode },
5397     { VEX_LEN_TABLE (VEX_LEN_XOP_08_B6) },
5398     { Bad_Opcode },
5399     /* b8 */
5400     { Bad_Opcode },
5401     { Bad_Opcode },
5402     { Bad_Opcode },
5403     { Bad_Opcode },
5404     { Bad_Opcode },
5405     { Bad_Opcode },
5406     { Bad_Opcode },
5407     { Bad_Opcode },
5408     /* c0 */
5409     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C0) },
5410     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C1) },
5411     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C2) },
5412     { VEX_LEN_TABLE (VEX_LEN_XOP_08_C3) },
5413     { Bad_Opcode },
5414     { Bad_Opcode },
5415     { Bad_Opcode },
5416     { Bad_Opcode },
5417     /* c8 */
5418     { Bad_Opcode },
5419     { Bad_Opcode },
5420     { Bad_Opcode },
5421     { Bad_Opcode },
5422     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CC) },
5423     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CD) },
5424     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CE) },
5425     { VEX_LEN_TABLE (VEX_LEN_XOP_08_CF) },
5426     /* d0 */
5427     { Bad_Opcode },
5428     { Bad_Opcode },
5429     { Bad_Opcode },
5430     { Bad_Opcode },
5431     { Bad_Opcode },
5432     { Bad_Opcode },
5433     { Bad_Opcode },
5434     { Bad_Opcode },
5435     /* d8 */
5436     { Bad_Opcode },
5437     { Bad_Opcode },
5438     { Bad_Opcode },
5439     { Bad_Opcode },
5440     { Bad_Opcode },
5441     { Bad_Opcode },
5442     { Bad_Opcode },
5443     { Bad_Opcode },
5444     /* e0 */
5445     { Bad_Opcode },
5446     { Bad_Opcode },
5447     { Bad_Opcode },
5448     { Bad_Opcode },
5449     { Bad_Opcode },
5450     { Bad_Opcode },
5451     { Bad_Opcode },
5452     { Bad_Opcode },
5453     /* e8 */
5454     { Bad_Opcode },
5455     { Bad_Opcode },
5456     { Bad_Opcode },
5457     { Bad_Opcode },
5458     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EC) },
5459     { VEX_LEN_TABLE (VEX_LEN_XOP_08_ED) },
5460     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EE) },
5461     { VEX_LEN_TABLE (VEX_LEN_XOP_08_EF) },
5462     /* f0 */
5463     { Bad_Opcode },
5464     { Bad_Opcode },
5465     { Bad_Opcode },
5466     { Bad_Opcode },
5467     { Bad_Opcode },
5468     { Bad_Opcode },
5469     { Bad_Opcode },
5470     { Bad_Opcode },
5471     /* f8 */
5472     { Bad_Opcode },
5473     { Bad_Opcode },
5474     { Bad_Opcode },
5475     { Bad_Opcode },
5476     { Bad_Opcode },
5477     { Bad_Opcode },
5478     { Bad_Opcode },
5479     { Bad_Opcode },
5480   },
5481   /* XOP_09 */
5482   {
5483     /* 00 */
5484     { Bad_Opcode },
5485     { VEX_LEN_TABLE (VEX_LEN_XOP_09_01) },
5486     { VEX_LEN_TABLE (VEX_LEN_XOP_09_02) },
5487     { Bad_Opcode },
5488     { Bad_Opcode },
5489     { Bad_Opcode },
5490     { Bad_Opcode },
5491     { Bad_Opcode },
5492     /* 08 */
5493     { Bad_Opcode },
5494     { Bad_Opcode },
5495     { Bad_Opcode },
5496     { Bad_Opcode },
5497     { Bad_Opcode },
5498     { Bad_Opcode },
5499     { Bad_Opcode },
5500     { Bad_Opcode },
5501     /* 10 */
5502     { Bad_Opcode },
5503     { Bad_Opcode },
5504     { VEX_LEN_TABLE (VEX_LEN_XOP_09_12) },
5505     { Bad_Opcode },
5506     { Bad_Opcode },
5507     { Bad_Opcode },
5508     { Bad_Opcode },
5509     { Bad_Opcode },
5510     /* 18 */
5511     { Bad_Opcode },
5512     { Bad_Opcode },
5513     { Bad_Opcode },
5514     { Bad_Opcode },
5515     { Bad_Opcode },
5516     { Bad_Opcode },
5517     { Bad_Opcode },
5518     { Bad_Opcode },
5519     /* 20 */
5520     { Bad_Opcode },
5521     { Bad_Opcode },
5522     { Bad_Opcode },
5523     { Bad_Opcode },
5524     { Bad_Opcode },
5525     { Bad_Opcode },
5526     { Bad_Opcode },
5527     { Bad_Opcode },
5528     /* 28 */
5529     { Bad_Opcode },
5530     { Bad_Opcode },
5531     { Bad_Opcode },
5532     { Bad_Opcode },
5533     { Bad_Opcode },
5534     { Bad_Opcode },
5535     { Bad_Opcode },
5536     { Bad_Opcode },
5537     /* 30 */
5538     { Bad_Opcode },
5539     { Bad_Opcode },
5540     { Bad_Opcode },
5541     { Bad_Opcode },
5542     { Bad_Opcode },
5543     { Bad_Opcode },
5544     { Bad_Opcode },
5545     { Bad_Opcode },
5546     /* 38 */
5547     { Bad_Opcode },
5548     { Bad_Opcode },
5549     { Bad_Opcode },
5550     { Bad_Opcode },
5551     { Bad_Opcode },
5552     { Bad_Opcode },
5553     { Bad_Opcode },
5554     { Bad_Opcode },
5555     /* 40 */
5556     { Bad_Opcode },
5557     { Bad_Opcode },
5558     { Bad_Opcode },
5559     { Bad_Opcode },
5560     { Bad_Opcode },
5561     { Bad_Opcode },
5562     { Bad_Opcode },
5563     { Bad_Opcode },
5564     /* 48 */
5565     { Bad_Opcode },
5566     { Bad_Opcode },
5567     { Bad_Opcode },
5568     { Bad_Opcode },
5569     { Bad_Opcode },
5570     { Bad_Opcode },
5571     { Bad_Opcode },
5572     { Bad_Opcode },
5573     /* 50 */
5574     { Bad_Opcode },
5575     { Bad_Opcode },
5576     { Bad_Opcode },
5577     { Bad_Opcode },
5578     { Bad_Opcode },
5579     { Bad_Opcode },
5580     { Bad_Opcode },
5581     { Bad_Opcode },
5582     /* 58 */
5583     { Bad_Opcode },
5584     { Bad_Opcode },
5585     { Bad_Opcode },
5586     { Bad_Opcode },
5587     { Bad_Opcode },
5588     { Bad_Opcode },
5589     { Bad_Opcode },
5590     { Bad_Opcode },
5591     /* 60 */
5592     { Bad_Opcode },
5593     { Bad_Opcode },
5594     { Bad_Opcode },
5595     { Bad_Opcode },
5596     { Bad_Opcode },
5597     { Bad_Opcode },
5598     { Bad_Opcode },
5599     { Bad_Opcode },
5600     /* 68 */
5601     { Bad_Opcode },
5602     { Bad_Opcode },
5603     { Bad_Opcode },
5604     { Bad_Opcode },
5605     { Bad_Opcode },
5606     { Bad_Opcode },
5607     { Bad_Opcode },
5608     { Bad_Opcode },
5609     /* 70 */
5610     { Bad_Opcode },
5611     { Bad_Opcode },
5612     { Bad_Opcode },
5613     { Bad_Opcode },
5614     { Bad_Opcode },
5615     { Bad_Opcode },
5616     { Bad_Opcode },
5617     { Bad_Opcode },
5618     /* 78 */
5619     { Bad_Opcode },
5620     { Bad_Opcode },
5621     { Bad_Opcode },
5622     { Bad_Opcode },
5623     { Bad_Opcode },
5624     { Bad_Opcode },
5625     { Bad_Opcode },
5626     { Bad_Opcode },
5627     /* 80 */
5628     { VEX_W_TABLE (VEX_W_XOP_09_80) },
5629     { VEX_W_TABLE (VEX_W_XOP_09_81) },
5630     { VEX_W_TABLE (VEX_W_XOP_09_82) },
5631     { VEX_W_TABLE (VEX_W_XOP_09_83) },
5632     { Bad_Opcode },
5633     { Bad_Opcode },
5634     { Bad_Opcode },
5635     { Bad_Opcode },
5636     /* 88 */
5637     { Bad_Opcode },
5638     { Bad_Opcode },
5639     { Bad_Opcode },
5640     { Bad_Opcode },
5641     { Bad_Opcode },
5642     { Bad_Opcode },
5643     { Bad_Opcode },
5644     { Bad_Opcode },
5645     /* 90 */
5646     { VEX_LEN_TABLE (VEX_LEN_XOP_09_90) },
5647     { VEX_LEN_TABLE (VEX_LEN_XOP_09_91) },
5648     { VEX_LEN_TABLE (VEX_LEN_XOP_09_92) },
5649     { VEX_LEN_TABLE (VEX_LEN_XOP_09_93) },
5650     { VEX_LEN_TABLE (VEX_LEN_XOP_09_94) },
5651     { VEX_LEN_TABLE (VEX_LEN_XOP_09_95) },
5652     { VEX_LEN_TABLE (VEX_LEN_XOP_09_96) },
5653     { VEX_LEN_TABLE (VEX_LEN_XOP_09_97) },
5654     /* 98 */
5655     { VEX_LEN_TABLE (VEX_LEN_XOP_09_98) },
5656     { VEX_LEN_TABLE (VEX_LEN_XOP_09_99) },
5657     { VEX_LEN_TABLE (VEX_LEN_XOP_09_9A) },
5658     { VEX_LEN_TABLE (VEX_LEN_XOP_09_9B) },
5659     { Bad_Opcode },
5660     { Bad_Opcode },
5661     { Bad_Opcode },
5662     { Bad_Opcode },
5663     /* a0 */
5664     { Bad_Opcode },
5665     { Bad_Opcode },
5666     { Bad_Opcode },
5667     { Bad_Opcode },
5668     { Bad_Opcode },
5669     { Bad_Opcode },
5670     { Bad_Opcode },
5671     { Bad_Opcode },
5672     /* a8 */
5673     { Bad_Opcode },
5674     { Bad_Opcode },
5675     { Bad_Opcode },
5676     { Bad_Opcode },
5677     { Bad_Opcode },
5678     { Bad_Opcode },
5679     { Bad_Opcode },
5680     { Bad_Opcode },
5681     /* b0 */
5682     { Bad_Opcode },
5683     { Bad_Opcode },
5684     { Bad_Opcode },
5685     { Bad_Opcode },
5686     { Bad_Opcode },
5687     { Bad_Opcode },
5688     { Bad_Opcode },
5689     { Bad_Opcode },
5690     /* b8 */
5691     { Bad_Opcode },
5692     { Bad_Opcode },
5693     { Bad_Opcode },
5694     { Bad_Opcode },
5695     { Bad_Opcode },
5696     { Bad_Opcode },
5697     { Bad_Opcode },
5698     { Bad_Opcode },
5699     /* c0 */
5700     { Bad_Opcode },
5701     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C1) },
5702     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C2) },
5703     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C3) },
5704     { Bad_Opcode },
5705     { Bad_Opcode },
5706     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C6) },
5707     { VEX_LEN_TABLE (VEX_LEN_XOP_09_C7) },
5708     /* c8 */
5709     { Bad_Opcode },
5710     { Bad_Opcode },
5711     { Bad_Opcode },
5712     { VEX_LEN_TABLE (VEX_LEN_XOP_09_CB) },
5713     { Bad_Opcode },
5714     { Bad_Opcode },
5715     { Bad_Opcode },
5716     { Bad_Opcode },
5717     /* d0 */
5718     { Bad_Opcode },
5719     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D1) },
5720     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D2) },
5721     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D3) },
5722     { Bad_Opcode },
5723     { Bad_Opcode },
5724     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D6) },
5725     { VEX_LEN_TABLE (VEX_LEN_XOP_09_D7) },
5726     /* d8 */
5727     { Bad_Opcode },
5728     { Bad_Opcode },
5729     { Bad_Opcode },
5730     { VEX_LEN_TABLE (VEX_LEN_XOP_09_DB) },
5731     { Bad_Opcode },
5732     { Bad_Opcode },
5733     { Bad_Opcode },
5734     { Bad_Opcode },
5735     /* e0 */
5736     { Bad_Opcode },
5737     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E1) },
5738     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E2) },
5739     { VEX_LEN_TABLE (VEX_LEN_XOP_09_E3) },
5740     { Bad_Opcode },
5741     { Bad_Opcode },
5742     { Bad_Opcode },
5743     { Bad_Opcode },
5744     /* e8 */
5745     { Bad_Opcode },
5746     { Bad_Opcode },
5747     { Bad_Opcode },
5748     { Bad_Opcode },
5749     { Bad_Opcode },
5750     { Bad_Opcode },
5751     { Bad_Opcode },
5752     { Bad_Opcode },
5753     /* f0 */
5754     { Bad_Opcode },
5755     { Bad_Opcode },
5756     { Bad_Opcode },
5757     { Bad_Opcode },
5758     { Bad_Opcode },
5759     { Bad_Opcode },
5760     { Bad_Opcode },
5761     { Bad_Opcode },
5762     /* f8 */
5763     { Bad_Opcode },
5764     { Bad_Opcode },
5765     { Bad_Opcode },
5766     { Bad_Opcode },
5767     { Bad_Opcode },
5768     { Bad_Opcode },
5769     { Bad_Opcode },
5770     { Bad_Opcode },
5771   },
5772   /* XOP_0A */
5773   {
5774     /* 00 */
5775     { Bad_Opcode },
5776     { Bad_Opcode },
5777     { Bad_Opcode },
5778     { Bad_Opcode },
5779     { Bad_Opcode },
5780     { Bad_Opcode },
5781     { Bad_Opcode },
5782     { Bad_Opcode },
5783     /* 08 */
5784     { Bad_Opcode },
5785     { Bad_Opcode },
5786     { Bad_Opcode },
5787     { Bad_Opcode },
5788     { Bad_Opcode },
5789     { Bad_Opcode },
5790     { Bad_Opcode },
5791     { Bad_Opcode },
5792     /* 10 */
5793     { "bextrS", { Gdq, Edq, Id }, 0 },
5794     { Bad_Opcode },
5795     { VEX_LEN_TABLE (VEX_LEN_XOP_0A_12) },
5796     { Bad_Opcode },
5797     { Bad_Opcode },
5798     { Bad_Opcode },
5799     { Bad_Opcode },
5800     { Bad_Opcode },
5801     /* 18 */
5802     { Bad_Opcode },
5803     { Bad_Opcode },
5804     { Bad_Opcode },
5805     { Bad_Opcode },
5806     { Bad_Opcode },
5807     { Bad_Opcode },
5808     { Bad_Opcode },
5809     { Bad_Opcode },
5810     /* 20 */
5811     { Bad_Opcode },
5812     { Bad_Opcode },
5813     { Bad_Opcode },
5814     { Bad_Opcode },
5815     { Bad_Opcode },
5816     { Bad_Opcode },
5817     { Bad_Opcode },
5818     { Bad_Opcode },
5819     /* 28 */
5820     { Bad_Opcode },
5821     { Bad_Opcode },
5822     { Bad_Opcode },
5823     { Bad_Opcode },
5824     { Bad_Opcode },
5825     { Bad_Opcode },
5826     { Bad_Opcode },
5827     { Bad_Opcode },
5828     /* 30 */
5829     { Bad_Opcode },
5830     { Bad_Opcode },
5831     { Bad_Opcode },
5832     { Bad_Opcode },
5833     { Bad_Opcode },
5834     { Bad_Opcode },
5835     { Bad_Opcode },
5836     { Bad_Opcode },
5837     /* 38 */
5838     { Bad_Opcode },
5839     { Bad_Opcode },
5840     { Bad_Opcode },
5841     { Bad_Opcode },
5842     { Bad_Opcode },
5843     { Bad_Opcode },
5844     { Bad_Opcode },
5845     { Bad_Opcode },
5846     /* 40 */
5847     { Bad_Opcode },
5848     { Bad_Opcode },
5849     { Bad_Opcode },
5850     { Bad_Opcode },
5851     { Bad_Opcode },
5852     { Bad_Opcode },
5853     { Bad_Opcode },
5854     { Bad_Opcode },
5855     /* 48 */
5856     { Bad_Opcode },
5857     { Bad_Opcode },
5858     { Bad_Opcode },
5859     { Bad_Opcode },
5860     { Bad_Opcode },
5861     { Bad_Opcode },
5862     { Bad_Opcode },
5863     { Bad_Opcode },
5864     /* 50 */
5865     { Bad_Opcode },
5866     { Bad_Opcode },
5867     { Bad_Opcode },
5868     { Bad_Opcode },
5869     { Bad_Opcode },
5870     { Bad_Opcode },
5871     { Bad_Opcode },
5872     { Bad_Opcode },
5873     /* 58 */
5874     { Bad_Opcode },
5875     { Bad_Opcode },
5876     { Bad_Opcode },
5877     { Bad_Opcode },
5878     { Bad_Opcode },
5879     { Bad_Opcode },
5880     { Bad_Opcode },
5881     { Bad_Opcode },
5882     /* 60 */
5883     { Bad_Opcode },
5884     { Bad_Opcode },
5885     { Bad_Opcode },
5886     { Bad_Opcode },
5887     { Bad_Opcode },
5888     { Bad_Opcode },
5889     { Bad_Opcode },
5890     { Bad_Opcode },
5891     /* 68 */
5892     { Bad_Opcode },
5893     { Bad_Opcode },
5894     { Bad_Opcode },
5895     { Bad_Opcode },
5896     { Bad_Opcode },
5897     { Bad_Opcode },
5898     { Bad_Opcode },
5899     { Bad_Opcode },
5900     /* 70 */
5901     { Bad_Opcode },
5902     { Bad_Opcode },
5903     { Bad_Opcode },
5904     { Bad_Opcode },
5905     { Bad_Opcode },
5906     { Bad_Opcode },
5907     { Bad_Opcode },
5908     { Bad_Opcode },
5909     /* 78 */
5910     { Bad_Opcode },
5911     { Bad_Opcode },
5912     { Bad_Opcode },
5913     { Bad_Opcode },
5914     { Bad_Opcode },
5915     { Bad_Opcode },
5916     { Bad_Opcode },
5917     { Bad_Opcode },
5918     /* 80 */
5919     { Bad_Opcode },
5920     { Bad_Opcode },
5921     { Bad_Opcode },
5922     { Bad_Opcode },
5923     { Bad_Opcode },
5924     { Bad_Opcode },
5925     { Bad_Opcode },
5926     { Bad_Opcode },
5927     /* 88 */
5928     { Bad_Opcode },
5929     { Bad_Opcode },
5930     { Bad_Opcode },
5931     { Bad_Opcode },
5932     { Bad_Opcode },
5933     { Bad_Opcode },
5934     { Bad_Opcode },
5935     { Bad_Opcode },
5936     /* 90 */
5937     { Bad_Opcode },
5938     { Bad_Opcode },
5939     { Bad_Opcode },
5940     { Bad_Opcode },
5941     { Bad_Opcode },
5942     { Bad_Opcode },
5943     { Bad_Opcode },
5944     { Bad_Opcode },
5945     /* 98 */
5946     { Bad_Opcode },
5947     { Bad_Opcode },
5948     { Bad_Opcode },
5949     { Bad_Opcode },
5950     { Bad_Opcode },
5951     { Bad_Opcode },
5952     { Bad_Opcode },
5953     { Bad_Opcode },
5954     /* a0 */
5955     { Bad_Opcode },
5956     { Bad_Opcode },
5957     { Bad_Opcode },
5958     { Bad_Opcode },
5959     { Bad_Opcode },
5960     { Bad_Opcode },
5961     { Bad_Opcode },
5962     { Bad_Opcode },
5963     /* a8 */
5964     { Bad_Opcode },
5965     { Bad_Opcode },
5966     { Bad_Opcode },
5967     { Bad_Opcode },
5968     { Bad_Opcode },
5969     { Bad_Opcode },
5970     { Bad_Opcode },
5971     { Bad_Opcode },
5972     /* b0 */
5973     { Bad_Opcode },
5974     { Bad_Opcode },
5975     { Bad_Opcode },
5976     { Bad_Opcode },
5977     { Bad_Opcode },
5978     { Bad_Opcode },
5979     { Bad_Opcode },
5980     { Bad_Opcode },
5981     /* b8 */
5982     { Bad_Opcode },
5983     { Bad_Opcode },
5984     { Bad_Opcode },
5985     { Bad_Opcode },
5986     { Bad_Opcode },
5987     { Bad_Opcode },
5988     { Bad_Opcode },
5989     { Bad_Opcode },
5990     /* c0 */
5991     { Bad_Opcode },
5992     { Bad_Opcode },
5993     { Bad_Opcode },
5994     { Bad_Opcode },
5995     { Bad_Opcode },
5996     { Bad_Opcode },
5997     { Bad_Opcode },
5998     { Bad_Opcode },
5999     /* c8 */
6000     { Bad_Opcode },
6001     { Bad_Opcode },
6002     { Bad_Opcode },
6003     { Bad_Opcode },
6004     { Bad_Opcode },
6005     { Bad_Opcode },
6006     { Bad_Opcode },
6007     { Bad_Opcode },
6008     /* d0 */
6009     { Bad_Opcode },
6010     { Bad_Opcode },
6011     { Bad_Opcode },
6012     { Bad_Opcode },
6013     { Bad_Opcode },
6014     { Bad_Opcode },
6015     { Bad_Opcode },
6016     { Bad_Opcode },
6017     /* d8 */
6018     { Bad_Opcode },
6019     { Bad_Opcode },
6020     { Bad_Opcode },
6021     { Bad_Opcode },
6022     { Bad_Opcode },
6023     { Bad_Opcode },
6024     { Bad_Opcode },
6025     { Bad_Opcode },
6026     /* e0 */
6027     { Bad_Opcode },
6028     { Bad_Opcode },
6029     { Bad_Opcode },
6030     { Bad_Opcode },
6031     { Bad_Opcode },
6032     { Bad_Opcode },
6033     { Bad_Opcode },
6034     { Bad_Opcode },
6035     /* e8 */
6036     { Bad_Opcode },
6037     { Bad_Opcode },
6038     { Bad_Opcode },
6039     { Bad_Opcode },
6040     { Bad_Opcode },
6041     { Bad_Opcode },
6042     { Bad_Opcode },
6043     { Bad_Opcode },
6044     /* f0 */
6045     { Bad_Opcode },
6046     { Bad_Opcode },
6047     { Bad_Opcode },
6048     { Bad_Opcode },
6049     { Bad_Opcode },
6050     { Bad_Opcode },
6051     { Bad_Opcode },
6052     { Bad_Opcode },
6053     /* f8 */
6054     { Bad_Opcode },
6055     { Bad_Opcode },
6056     { Bad_Opcode },
6057     { Bad_Opcode },
6058     { Bad_Opcode },
6059     { Bad_Opcode },
6060     { Bad_Opcode },
6061     { Bad_Opcode },
6062   },
6063 };
6064
6065 static const struct dis386 vex_table[][256] = {
6066   /* VEX_0F */
6067   {
6068     /* 00 */
6069     { Bad_Opcode },
6070     { Bad_Opcode },
6071     { Bad_Opcode },
6072     { Bad_Opcode },
6073     { Bad_Opcode },
6074     { Bad_Opcode },
6075     { Bad_Opcode },
6076     { Bad_Opcode },
6077     /* 08 */
6078     { Bad_Opcode },
6079     { Bad_Opcode },
6080     { Bad_Opcode },
6081     { Bad_Opcode },
6082     { Bad_Opcode },
6083     { Bad_Opcode },
6084     { Bad_Opcode },
6085     { Bad_Opcode },
6086     /* 10 */
6087     { PREFIX_TABLE (PREFIX_0F10) },
6088     { PREFIX_TABLE (PREFIX_0F11) },
6089     { PREFIX_TABLE (PREFIX_VEX_0F12) },
6090     { VEX_LEN_TABLE (VEX_LEN_0F13) },
6091     { "vunpcklpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6092     { "vunpckhpX",      { XM, Vex, EXx }, PREFIX_OPCODE },
6093     { PREFIX_TABLE (PREFIX_VEX_0F16) },
6094     { VEX_LEN_TABLE (VEX_LEN_0F17) },
6095     /* 18 */
6096     { Bad_Opcode },
6097     { Bad_Opcode },
6098     { Bad_Opcode },
6099     { Bad_Opcode },
6100     { Bad_Opcode },
6101     { Bad_Opcode },
6102     { Bad_Opcode },
6103     { Bad_Opcode },
6104     /* 20 */
6105     { Bad_Opcode },
6106     { Bad_Opcode },
6107     { Bad_Opcode },
6108     { Bad_Opcode },
6109     { Bad_Opcode },
6110     { Bad_Opcode },
6111     { Bad_Opcode },
6112     { Bad_Opcode },
6113     /* 28 */
6114     { "vmovapX",        { XM, EXx }, PREFIX_OPCODE },
6115     { "vmovapX",        { EXxS, XM }, PREFIX_OPCODE },
6116     { PREFIX_TABLE (PREFIX_VEX_0F2A) },
6117     { "vmovntpX",       { Mx, XM }, PREFIX_OPCODE },
6118     { PREFIX_TABLE (PREFIX_VEX_0F2C) },
6119     { PREFIX_TABLE (PREFIX_VEX_0F2D) },
6120     { PREFIX_TABLE (PREFIX_0F2E) },
6121     { PREFIX_TABLE (PREFIX_0F2F) },
6122     /* 30 */
6123     { Bad_Opcode },
6124     { Bad_Opcode },
6125     { Bad_Opcode },
6126     { Bad_Opcode },
6127     { Bad_Opcode },
6128     { Bad_Opcode },
6129     { Bad_Opcode },
6130     { Bad_Opcode },
6131     /* 38 */
6132     { Bad_Opcode },
6133     { Bad_Opcode },
6134     { Bad_Opcode },
6135     { Bad_Opcode },
6136     { Bad_Opcode },
6137     { Bad_Opcode },
6138     { Bad_Opcode },
6139     { Bad_Opcode },
6140     /* 40 */
6141     { Bad_Opcode },
6142     { VEX_LEN_TABLE (VEX_LEN_0F41) },
6143     { VEX_LEN_TABLE (VEX_LEN_0F42) },
6144     { Bad_Opcode },
6145     { VEX_LEN_TABLE (VEX_LEN_0F44) },
6146     { VEX_LEN_TABLE (VEX_LEN_0F45) },
6147     { VEX_LEN_TABLE (VEX_LEN_0F46) },
6148     { VEX_LEN_TABLE (VEX_LEN_0F47) },
6149     /* 48 */
6150     { Bad_Opcode },
6151     { Bad_Opcode },
6152     { VEX_LEN_TABLE (VEX_LEN_0F4A) },
6153     { VEX_LEN_TABLE (VEX_LEN_0F4B) },
6154     { Bad_Opcode },
6155     { Bad_Opcode },
6156     { Bad_Opcode },
6157     { Bad_Opcode },
6158     /* 50 */
6159     { "vmovmskpX",      { Gdq, Ux }, PREFIX_OPCODE },
6160     { PREFIX_TABLE (PREFIX_0F51) },
6161     { PREFIX_TABLE (PREFIX_0F52) },
6162     { PREFIX_TABLE (PREFIX_0F53) },
6163     { "vandpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6164     { "vandnpX",        { XM, Vex, EXx }, PREFIX_OPCODE },
6165     { "vorpX",          { XM, Vex, EXx }, PREFIX_OPCODE },
6166     { "vxorpX",         { XM, Vex, EXx }, PREFIX_OPCODE },
6167     /* 58 */
6168     { PREFIX_TABLE (PREFIX_0F58) },
6169     { PREFIX_TABLE (PREFIX_0F59) },
6170     { PREFIX_TABLE (PREFIX_0F5A) },
6171     { PREFIX_TABLE (PREFIX_0F5B) },
6172     { PREFIX_TABLE (PREFIX_0F5C) },
6173     { PREFIX_TABLE (PREFIX_0F5D) },
6174     { PREFIX_TABLE (PREFIX_0F5E) },
6175     { PREFIX_TABLE (PREFIX_0F5F) },
6176     /* 60 */
6177     { "vpunpcklbw",     { XM, Vex, EXx }, PREFIX_DATA },
6178     { "vpunpcklwd",     { XM, Vex, EXx }, PREFIX_DATA },
6179     { "vpunpckldq",     { XM, Vex, EXx }, PREFIX_DATA },
6180     { "vpacksswb",      { XM, Vex, EXx }, PREFIX_DATA },
6181     { "vpcmpgtb",       { XM, Vex, EXx }, PREFIX_DATA },
6182     { "vpcmpgtw",       { XM, Vex, EXx }, PREFIX_DATA },
6183     { "vpcmpgtd",       { XM, Vex, EXx }, PREFIX_DATA },
6184     { "vpackuswb",      { XM, Vex, EXx }, PREFIX_DATA },
6185     /* 68 */
6186     { "vpunpckhbw",     { XM, Vex, EXx }, PREFIX_DATA },
6187     { "vpunpckhwd",     { XM, Vex, EXx }, PREFIX_DATA },
6188     { "vpunpckhdq",     { XM, Vex, EXx }, PREFIX_DATA },
6189     { "vpackssdw",      { XM, Vex, EXx }, PREFIX_DATA },
6190     { "vpunpcklqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6191     { "vpunpckhqdq",    { XM, Vex, EXx }, PREFIX_DATA },
6192     { VEX_LEN_TABLE (VEX_LEN_0F6E) },
6193     { PREFIX_TABLE (PREFIX_VEX_0F6F) },
6194     /* 70 */
6195     { PREFIX_TABLE (PREFIX_VEX_0F70) },
6196     { REG_TABLE (REG_VEX_0F71) },
6197     { REG_TABLE (REG_VEX_0F72) },
6198     { REG_TABLE (REG_VEX_0F73) },
6199     { "vpcmpeqb",       { XM, Vex, EXx }, PREFIX_DATA },
6200     { "vpcmpeqw",       { XM, Vex, EXx }, PREFIX_DATA },
6201     { "vpcmpeqd",       { XM, Vex, EXx }, PREFIX_DATA },
6202     { VEX_LEN_TABLE (VEX_LEN_0F77) },
6203     /* 78 */
6204     { Bad_Opcode },
6205     { Bad_Opcode },
6206     { Bad_Opcode },
6207     { Bad_Opcode },
6208     { PREFIX_TABLE (PREFIX_0F7C) },
6209     { PREFIX_TABLE (PREFIX_0F7D) },
6210     { PREFIX_TABLE (PREFIX_VEX_0F7E) },
6211     { PREFIX_TABLE (PREFIX_VEX_0F7F) },
6212     /* 80 */
6213     { Bad_Opcode },
6214     { Bad_Opcode },
6215     { Bad_Opcode },
6216     { Bad_Opcode },
6217     { Bad_Opcode },
6218     { Bad_Opcode },
6219     { Bad_Opcode },
6220     { Bad_Opcode },
6221     /* 88 */
6222     { Bad_Opcode },
6223     { Bad_Opcode },
6224     { Bad_Opcode },
6225     { Bad_Opcode },
6226     { Bad_Opcode },
6227     { Bad_Opcode },
6228     { Bad_Opcode },
6229     { Bad_Opcode },
6230     /* 90 */
6231     { VEX_LEN_TABLE (VEX_LEN_0F90) },
6232     { VEX_LEN_TABLE (VEX_LEN_0F91) },
6233     { VEX_LEN_TABLE (VEX_LEN_0F92) },
6234     { VEX_LEN_TABLE (VEX_LEN_0F93) },
6235     { Bad_Opcode },
6236     { Bad_Opcode },
6237     { Bad_Opcode },
6238     { Bad_Opcode },
6239     /* 98 */
6240     { VEX_LEN_TABLE (VEX_LEN_0F98) },
6241     { VEX_LEN_TABLE (VEX_LEN_0F99) },
6242     { Bad_Opcode },
6243     { Bad_Opcode },
6244     { Bad_Opcode },
6245     { Bad_Opcode },
6246     { Bad_Opcode },
6247     { Bad_Opcode },
6248     /* a0 */
6249     { Bad_Opcode },
6250     { Bad_Opcode },
6251     { Bad_Opcode },
6252     { Bad_Opcode },
6253     { Bad_Opcode },
6254     { Bad_Opcode },
6255     { Bad_Opcode },
6256     { Bad_Opcode },
6257     /* a8 */
6258     { Bad_Opcode },
6259     { Bad_Opcode },
6260     { Bad_Opcode },
6261     { Bad_Opcode },
6262     { Bad_Opcode },
6263     { Bad_Opcode },
6264     { REG_TABLE (REG_VEX_0FAE) },
6265     { Bad_Opcode },
6266     /* b0 */
6267     { Bad_Opcode },
6268     { Bad_Opcode },
6269     { Bad_Opcode },
6270     { Bad_Opcode },
6271     { Bad_Opcode },
6272     { Bad_Opcode },
6273     { Bad_Opcode },
6274     { Bad_Opcode },
6275     /* b8 */
6276     { Bad_Opcode },
6277     { Bad_Opcode },
6278     { Bad_Opcode },
6279     { Bad_Opcode },
6280     { Bad_Opcode },
6281     { Bad_Opcode },
6282     { Bad_Opcode },
6283     { Bad_Opcode },
6284     /* c0 */
6285     { Bad_Opcode },
6286     { Bad_Opcode },
6287     { PREFIX_TABLE (PREFIX_0FC2) },
6288     { Bad_Opcode },
6289     { VEX_LEN_TABLE (VEX_LEN_0FC4) },
6290     { "vpextrw",        { Gd, Uxmm, Ib }, PREFIX_DATA },
6291     { "vshufpX",        { XM, Vex, EXx, Ib }, PREFIX_OPCODE },
6292     { Bad_Opcode },
6293     /* c8 */
6294     { Bad_Opcode },
6295     { Bad_Opcode },
6296     { Bad_Opcode },
6297     { Bad_Opcode },
6298     { Bad_Opcode },
6299     { Bad_Opcode },
6300     { Bad_Opcode },
6301     { Bad_Opcode },
6302     /* d0 */
6303     { PREFIX_TABLE (PREFIX_0FD0) },
6304     { "vpsrlw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6305     { "vpsrld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6306     { "vpsrlq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6307     { "vpaddq",         { XM, Vex, EXx }, PREFIX_DATA },
6308     { "vpmullw",        { XM, Vex, EXx }, PREFIX_DATA },
6309     { VEX_LEN_TABLE (VEX_LEN_0FD6) },
6310     { "vpmovmskb",      { Gdq, Ux }, PREFIX_DATA },
6311     /* d8 */
6312     { "vpsubusb",       { XM, Vex, EXx }, PREFIX_DATA },
6313     { "vpsubusw",       { XM, Vex, EXx }, PREFIX_DATA },
6314     { "vpminub",        { XM, Vex, EXx }, PREFIX_DATA },
6315     { "vpand",          { XM, Vex, EXx }, PREFIX_DATA },
6316     { "vpaddusb",       { XM, Vex, EXx }, PREFIX_DATA },
6317     { "vpaddusw",       { XM, Vex, EXx }, PREFIX_DATA },
6318     { "vpmaxub",        { XM, Vex, EXx }, PREFIX_DATA },
6319     { "vpandn",         { XM, Vex, EXx }, PREFIX_DATA },
6320     /* e0 */
6321     { "vpavgb",         { XM, Vex, EXx }, PREFIX_DATA },
6322     { "vpsraw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6323     { "vpsrad",         { XM, Vex, EXxmm }, PREFIX_DATA },
6324     { "vpavgw",         { XM, Vex, EXx }, PREFIX_DATA },
6325     { "vpmulhuw",       { XM, Vex, EXx }, PREFIX_DATA },
6326     { "vpmulhw",        { XM, Vex, EXx }, PREFIX_DATA },
6327     { PREFIX_TABLE (PREFIX_0FE6) },
6328     { "vmovntdq",       { Mx, XM }, PREFIX_DATA },
6329     /* e8 */
6330     { "vpsubsb",        { XM, Vex, EXx }, PREFIX_DATA },
6331     { "vpsubsw",        { XM, Vex, EXx }, PREFIX_DATA },
6332     { "vpminsw",        { XM, Vex, EXx }, PREFIX_DATA },
6333     { "vpor",           { XM, Vex, EXx }, PREFIX_DATA },
6334     { "vpaddsb",        { XM, Vex, EXx }, PREFIX_DATA },
6335     { "vpaddsw",        { XM, Vex, EXx }, PREFIX_DATA },
6336     { "vpmaxsw",        { XM, Vex, EXx }, PREFIX_DATA },
6337     { "vpxor",          { XM, Vex, EXx }, PREFIX_DATA },
6338     /* f0 */
6339     { PREFIX_TABLE (PREFIX_0FF0) },
6340     { "vpsllw",         { XM, Vex, EXxmm }, PREFIX_DATA },
6341     { "vpslld",         { XM, Vex, EXxmm }, PREFIX_DATA },
6342     { "vpsllq",         { XM, Vex, EXxmm }, PREFIX_DATA },
6343     { "vpmuludq",       { XM, Vex, EXx }, PREFIX_DATA },
6344     { "vpmaddwd",       { XM, Vex, EXx }, PREFIX_DATA },
6345     { "vpsadbw",        { XM, Vex, EXx }, PREFIX_DATA },
6346     { "vmaskmovdqu",    { XM, Uxmm }, PREFIX_DATA },
6347     /* f8 */
6348     { "vpsubb",         { XM, Vex, EXx }, PREFIX_DATA },
6349     { "vpsubw",         { XM, Vex, EXx }, PREFIX_DATA },
6350     { "vpsubd",         { XM, Vex, EXx }, PREFIX_DATA },
6351     { "vpsubq",         { XM, Vex, EXx }, PREFIX_DATA },
6352     { "vpaddb",         { XM, Vex, EXx }, PREFIX_DATA },
6353     { "vpaddw",         { XM, Vex, EXx }, PREFIX_DATA },
6354     { "vpaddd",         { XM, Vex, EXx }, PREFIX_DATA },
6355     { Bad_Opcode },
6356   },
6357   /* VEX_0F38 */
6358   {
6359     /* 00 */
6360     { "vpshufb",        { XM, Vex, EXx }, PREFIX_DATA },
6361     { "vphaddw",        { XM, Vex, EXx }, PREFIX_DATA },
6362     { "vphaddd",        { XM, Vex, EXx }, PREFIX_DATA },
6363     { "vphaddsw",       { XM, Vex, EXx }, PREFIX_DATA },
6364     { "vpmaddubsw",     { XM, Vex, EXx }, PREFIX_DATA },
6365     { "vphsubw",        { XM, Vex, EXx }, PREFIX_DATA },
6366     { "vphsubd",        { XM, Vex, EXx }, PREFIX_DATA },
6367     { "vphsubsw",       { XM, Vex, EXx }, PREFIX_DATA },
6368     /* 08 */
6369     { "vpsignb",        { XM, Vex, EXx }, PREFIX_DATA },
6370     { "vpsignw",        { XM, Vex, EXx }, PREFIX_DATA },
6371     { "vpsignd",        { XM, Vex, EXx }, PREFIX_DATA },
6372     { "vpmulhrsw",      { XM, Vex, EXx }, PREFIX_DATA },
6373     { VEX_W_TABLE (VEX_W_0F380C) },
6374     { VEX_W_TABLE (VEX_W_0F380D) },
6375     { VEX_W_TABLE (VEX_W_0F380E) },
6376     { VEX_W_TABLE (VEX_W_0F380F) },
6377     /* 10 */
6378     { Bad_Opcode },
6379     { Bad_Opcode },
6380     { Bad_Opcode },
6381     { VEX_W_TABLE (VEX_W_0F3813) },
6382     { Bad_Opcode },
6383     { Bad_Opcode },
6384     { VEX_LEN_TABLE (VEX_LEN_0F3816) },
6385     { "vptest",         { XM, EXx }, PREFIX_DATA },
6386     /* 18 */
6387     { VEX_W_TABLE (VEX_W_0F3818) },
6388     { VEX_LEN_TABLE (VEX_LEN_0F3819) },
6389     { VEX_LEN_TABLE (VEX_LEN_0F381A) },
6390     { Bad_Opcode },
6391     { "vpabsb",         { XM, EXx }, PREFIX_DATA },
6392     { "vpabsw",         { XM, EXx }, PREFIX_DATA },
6393     { "vpabsd",         { XM, EXx }, PREFIX_DATA },
6394     { Bad_Opcode },
6395     /* 20 */
6396     { "vpmovsxbw",      { XM, EXxmmq }, PREFIX_DATA },
6397     { "vpmovsxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6398     { "vpmovsxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6399     { "vpmovsxwd",      { XM, EXxmmq }, PREFIX_DATA },
6400     { "vpmovsxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6401     { "vpmovsxdq",      { XM, EXxmmq }, PREFIX_DATA },
6402     { Bad_Opcode },
6403     { Bad_Opcode },
6404     /* 28 */
6405     { "vpmuldq",        { XM, Vex, EXx }, PREFIX_DATA },
6406     { "vpcmpeqq",       { XM, Vex, EXx }, PREFIX_DATA },
6407     { "vmovntdqa",      { XM, Mx }, PREFIX_DATA },
6408     { "vpackusdw",      { XM, Vex, EXx }, PREFIX_DATA },
6409     { VEX_W_TABLE (VEX_W_0F382C) },
6410     { VEX_W_TABLE (VEX_W_0F382D) },
6411     { VEX_W_TABLE (VEX_W_0F382E) },
6412     { VEX_W_TABLE (VEX_W_0F382F) },
6413     /* 30 */
6414     { "vpmovzxbw",      { XM, EXxmmq }, PREFIX_DATA },
6415     { "vpmovzxbd",      { XM, EXxmmqd }, PREFIX_DATA },
6416     { "vpmovzxbq",      { XM, EXxmmdw }, PREFIX_DATA },
6417     { "vpmovzxwd",      { XM, EXxmmq }, PREFIX_DATA },
6418     { "vpmovzxwq",      { XM, EXxmmqd }, PREFIX_DATA },
6419     { "vpmovzxdq",      { XM, EXxmmq }, PREFIX_DATA },
6420     { VEX_LEN_TABLE (VEX_LEN_0F3836) },
6421     { "vpcmpgtq",       { XM, Vex, EXx }, PREFIX_DATA },
6422     /* 38 */
6423     { "vpminsb",        { XM, Vex, EXx }, PREFIX_DATA },
6424     { "vpminsd",        { XM, Vex, EXx }, PREFIX_DATA },
6425     { "vpminuw",        { XM, Vex, EXx }, PREFIX_DATA },
6426     { "vpminud",        { XM, Vex, EXx }, PREFIX_DATA },
6427     { "vpmaxsb",        { XM, Vex, EXx }, PREFIX_DATA },
6428     { "vpmaxsd",        { XM, Vex, EXx }, PREFIX_DATA },
6429     { "vpmaxuw",        { XM, Vex, EXx }, PREFIX_DATA },
6430     { "vpmaxud",        { XM, Vex, EXx }, PREFIX_DATA },
6431     /* 40 */
6432     { "vpmulld",        { XM, Vex, EXx }, PREFIX_DATA },
6433     { VEX_LEN_TABLE (VEX_LEN_0F3841) },
6434     { Bad_Opcode },
6435     { Bad_Opcode },
6436     { Bad_Opcode },
6437     { "vpsrlv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6438     { VEX_W_TABLE (VEX_W_0F3846) },
6439     { "vpsllv%DQ", { XM, Vex, EXx }, PREFIX_DATA },
6440     /* 48 */
6441     { Bad_Opcode },
6442     { X86_64_TABLE (X86_64_VEX_0F3849) },
6443     { Bad_Opcode },
6444     { X86_64_TABLE (X86_64_VEX_0F384B) },
6445     { Bad_Opcode },
6446     { Bad_Opcode },
6447     { Bad_Opcode },
6448     { Bad_Opcode },
6449     /* 50 */
6450     { VEX_W_TABLE (VEX_W_0F3850) },
6451     { VEX_W_TABLE (VEX_W_0F3851) },
6452     { VEX_W_TABLE (VEX_W_0F3852) },
6453     { VEX_W_TABLE (VEX_W_0F3853) },
6454     { Bad_Opcode },
6455     { Bad_Opcode },
6456     { Bad_Opcode },
6457     { Bad_Opcode },
6458     /* 58 */
6459     { VEX_W_TABLE (VEX_W_0F3858) },
6460     { VEX_W_TABLE (VEX_W_0F3859) },
6461     { VEX_LEN_TABLE (VEX_LEN_0F385A) },
6462     { Bad_Opcode },
6463     { X86_64_TABLE (X86_64_VEX_0F385C) },
6464     { Bad_Opcode },
6465     { X86_64_TABLE (X86_64_VEX_0F385E) },
6466     { Bad_Opcode },
6467     /* 60 */
6468     { Bad_Opcode },
6469     { Bad_Opcode },
6470     { Bad_Opcode },
6471     { Bad_Opcode },
6472     { Bad_Opcode },
6473     { Bad_Opcode },
6474     { Bad_Opcode },
6475     { Bad_Opcode },
6476     /* 68 */
6477     { Bad_Opcode },
6478     { Bad_Opcode },
6479     { Bad_Opcode },
6480     { Bad_Opcode },
6481     { X86_64_TABLE (X86_64_VEX_0F386C) },
6482     { Bad_Opcode },
6483     { Bad_Opcode },
6484     { Bad_Opcode },
6485     /* 70 */
6486     { Bad_Opcode },
6487     { Bad_Opcode },
6488     { PREFIX_TABLE (PREFIX_VEX_0F3872) },
6489     { Bad_Opcode },
6490     { Bad_Opcode },
6491     { Bad_Opcode },
6492     { Bad_Opcode },
6493     { Bad_Opcode },
6494     /* 78 */
6495     { VEX_W_TABLE (VEX_W_0F3878) },
6496     { VEX_W_TABLE (VEX_W_0F3879) },
6497     { Bad_Opcode },
6498     { Bad_Opcode },
6499     { Bad_Opcode },
6500     { Bad_Opcode },
6501     { Bad_Opcode },
6502     { Bad_Opcode },
6503     /* 80 */
6504     { Bad_Opcode },
6505     { Bad_Opcode },
6506     { Bad_Opcode },
6507     { Bad_Opcode },
6508     { Bad_Opcode },
6509     { Bad_Opcode },
6510     { Bad_Opcode },
6511     { Bad_Opcode },
6512     /* 88 */
6513     { Bad_Opcode },
6514     { Bad_Opcode },
6515     { Bad_Opcode },
6516     { Bad_Opcode },
6517     { "vpmaskmov%DQ",   { XM, Vex, Mx }, PREFIX_DATA },
6518     { Bad_Opcode },
6519     { "vpmaskmov%DQ",   { Mx, Vex, XM }, PREFIX_DATA },
6520     { Bad_Opcode },
6521     /* 90 */
6522     { "vpgatherd%DQ", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6523     { "vpgatherq%DQ", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6524     { "vgatherdp%XW", { XM, MVexVSIBDWpX, VexGatherD }, PREFIX_DATA },
6525     { "vgatherqp%XW", { XMGatherQ, MVexVSIBQWpX, VexGatherQ }, PREFIX_DATA },
6526     { Bad_Opcode },
6527     { Bad_Opcode },
6528     { "vfmaddsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6529     { "vfmsubadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6530     /* 98 */
6531     { "vfmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6532     { "vfmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6533     { "vfmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6534     { "vfmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6535     { "vfnmadd132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6536     { "vfnmadd132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6537     { "vfnmsub132p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6538     { "vfnmsub132s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6539     /* a0 */
6540     { Bad_Opcode },
6541     { Bad_Opcode },
6542     { Bad_Opcode },
6543     { Bad_Opcode },
6544     { Bad_Opcode },
6545     { Bad_Opcode },
6546     { "vfmaddsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6547     { "vfmsubadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6548     /* a8 */
6549     { "vfmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6550     { "vfmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6551     { "vfmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6552     { "vfmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6553     { "vfnmadd213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6554     { "vfnmadd213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6555     { "vfnmsub213p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6556     { "vfnmsub213s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6557     /* b0 */
6558     { VEX_W_TABLE (VEX_W_0F38B0) },
6559     { VEX_W_TABLE (VEX_W_0F38B1) },
6560     { Bad_Opcode },
6561     { Bad_Opcode },
6562     { VEX_W_TABLE (VEX_W_0F38B4) },
6563     { VEX_W_TABLE (VEX_W_0F38B5) },
6564     { "vfmaddsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6565     { "vfmsubadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6566     /* b8 */
6567     { "vfmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6568     { "vfmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6569     { "vfmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6570     { "vfmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6571     { "vfnmadd231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6572     { "vfnmadd231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6573     { "vfnmsub231p%XW", { XM, Vex, EXx }, PREFIX_DATA },
6574     { "vfnmsub231s%XW", { XMScalar, VexScalar, EXdq }, PREFIX_DATA },
6575     /* c0 */
6576     { Bad_Opcode },
6577     { Bad_Opcode },
6578     { Bad_Opcode },
6579     { Bad_Opcode },
6580     { Bad_Opcode },
6581     { Bad_Opcode },
6582     { Bad_Opcode },
6583     { Bad_Opcode },
6584     /* c8 */
6585     { Bad_Opcode },
6586     { Bad_Opcode },
6587     { Bad_Opcode },
6588     { PREFIX_TABLE (PREFIX_VEX_0F38CB) },
6589     { PREFIX_TABLE (PREFIX_VEX_0F38CC) },
6590     { PREFIX_TABLE (PREFIX_VEX_0F38CD) },
6591     { Bad_Opcode },
6592     { VEX_W_TABLE (VEX_W_0F38CF) },
6593     /* d0 */
6594     { Bad_Opcode },
6595     { Bad_Opcode },
6596     { VEX_W_TABLE (VEX_W_0F38D2) },
6597     { VEX_W_TABLE (VEX_W_0F38D3) },
6598     { Bad_Opcode },
6599     { Bad_Opcode },
6600     { Bad_Opcode },
6601     { Bad_Opcode },
6602     /* d8 */
6603     { Bad_Opcode },
6604     { Bad_Opcode },
6605     { VEX_W_TABLE (VEX_W_0F38DA) },
6606     { VEX_LEN_TABLE (VEX_LEN_0F38DB) },
6607     { "vaesenc",        { XM, Vex, EXx }, PREFIX_DATA },
6608     { "vaesenclast",    { XM, Vex, EXx }, PREFIX_DATA },
6609     { "vaesdec",        { XM, Vex, EXx }, PREFIX_DATA },
6610     { "vaesdeclast",    { XM, Vex, EXx }, PREFIX_DATA },
6611     /* e0 */
6612     { X86_64_TABLE (X86_64_VEX_0F38E0) },
6613     { X86_64_TABLE (X86_64_VEX_0F38E1) },
6614     { X86_64_TABLE (X86_64_VEX_0F38E2) },
6615     { X86_64_TABLE (X86_64_VEX_0F38E3) },
6616     { X86_64_TABLE (X86_64_VEX_0F38E4) },
6617     { X86_64_TABLE (X86_64_VEX_0F38E5) },
6618     { X86_64_TABLE (X86_64_VEX_0F38E6) },
6619     { X86_64_TABLE (X86_64_VEX_0F38E7) },
6620     /* e8 */
6621     { X86_64_TABLE (X86_64_VEX_0F38E8) },
6622     { X86_64_TABLE (X86_64_VEX_0F38E9) },
6623     { X86_64_TABLE (X86_64_VEX_0F38EA) },
6624     { X86_64_TABLE (X86_64_VEX_0F38EB) },
6625     { X86_64_TABLE (X86_64_VEX_0F38EC) },
6626     { X86_64_TABLE (X86_64_VEX_0F38ED) },
6627     { X86_64_TABLE (X86_64_VEX_0F38EE) },
6628     { X86_64_TABLE (X86_64_VEX_0F38EF) },
6629     /* f0 */
6630     { Bad_Opcode },
6631     { Bad_Opcode },
6632     { VEX_LEN_TABLE (VEX_LEN_0F38F2) },
6633     { VEX_LEN_TABLE (VEX_LEN_0F38F3) },
6634     { Bad_Opcode },
6635     { VEX_LEN_TABLE (VEX_LEN_0F38F5) },
6636     { VEX_LEN_TABLE (VEX_LEN_0F38F6) },
6637     { VEX_LEN_TABLE (VEX_LEN_0F38F7) },
6638     /* f8 */
6639     { Bad_Opcode },
6640     { Bad_Opcode },
6641     { Bad_Opcode },
6642     { Bad_Opcode },
6643     { Bad_Opcode },
6644     { Bad_Opcode },
6645     { Bad_Opcode },
6646     { Bad_Opcode },
6647   },
6648   /* VEX_0F3A */
6649   {
6650     /* 00 */
6651     { VEX_LEN_TABLE (VEX_LEN_0F3A00) },
6652     { VEX_LEN_TABLE (VEX_LEN_0F3A01) },
6653     { VEX_W_TABLE (VEX_W_0F3A02) },
6654     { Bad_Opcode },
6655     { VEX_W_TABLE (VEX_W_0F3A04) },
6656     { VEX_W_TABLE (VEX_W_0F3A05) },
6657     { VEX_LEN_TABLE (VEX_LEN_0F3A06) },
6658     { Bad_Opcode },
6659     /* 08 */
6660     { "vroundps",       { XM, EXx, Ib }, PREFIX_DATA },
6661     { "vroundpd",       { XM, EXx, Ib }, PREFIX_DATA },
6662     { "vroundss",       { XMScalar, VexScalar, EXd, Ib }, PREFIX_DATA },
6663     { "vroundsd",       { XMScalar, VexScalar, EXq, Ib }, PREFIX_DATA },
6664     { "vblendps",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6665     { "vblendpd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6666     { "vpblendw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6667     { "vpalignr",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6668     /* 10 */
6669     { Bad_Opcode },
6670     { Bad_Opcode },
6671     { Bad_Opcode },
6672     { Bad_Opcode },
6673     { VEX_LEN_TABLE (VEX_LEN_0F3A14) },
6674     { VEX_LEN_TABLE (VEX_LEN_0F3A15) },
6675     { VEX_LEN_TABLE (VEX_LEN_0F3A16) },
6676     { VEX_LEN_TABLE (VEX_LEN_0F3A17) },
6677     /* 18 */
6678     { VEX_LEN_TABLE (VEX_LEN_0F3A18) },
6679     { VEX_LEN_TABLE (VEX_LEN_0F3A19) },
6680     { Bad_Opcode },
6681     { Bad_Opcode },
6682     { Bad_Opcode },
6683     { VEX_W_TABLE (VEX_W_0F3A1D) },
6684     { Bad_Opcode },
6685     { Bad_Opcode },
6686     /* 20 */
6687     { VEX_LEN_TABLE (VEX_LEN_0F3A20) },
6688     { VEX_LEN_TABLE (VEX_LEN_0F3A21) },
6689     { VEX_LEN_TABLE (VEX_LEN_0F3A22) },
6690     { Bad_Opcode },
6691     { Bad_Opcode },
6692     { Bad_Opcode },
6693     { Bad_Opcode },
6694     { Bad_Opcode },
6695     /* 28 */
6696     { Bad_Opcode },
6697     { Bad_Opcode },
6698     { Bad_Opcode },
6699     { Bad_Opcode },
6700     { Bad_Opcode },
6701     { Bad_Opcode },
6702     { Bad_Opcode },
6703     { Bad_Opcode },
6704     /* 30 */
6705     { VEX_LEN_TABLE (VEX_LEN_0F3A30) },
6706     { VEX_LEN_TABLE (VEX_LEN_0F3A31) },
6707     { VEX_LEN_TABLE (VEX_LEN_0F3A32) },
6708     { VEX_LEN_TABLE (VEX_LEN_0F3A33) },
6709     { Bad_Opcode },
6710     { Bad_Opcode },
6711     { Bad_Opcode },
6712     { Bad_Opcode },
6713     /* 38 */
6714     { VEX_LEN_TABLE (VEX_LEN_0F3A38) },
6715     { VEX_LEN_TABLE (VEX_LEN_0F3A39) },
6716     { Bad_Opcode },
6717     { Bad_Opcode },
6718     { Bad_Opcode },
6719     { Bad_Opcode },
6720     { Bad_Opcode },
6721     { Bad_Opcode },
6722     /* 40 */
6723     { "vdpps",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
6724     { VEX_LEN_TABLE (VEX_LEN_0F3A41) },
6725     { "vmpsadbw",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
6726     { Bad_Opcode },
6727     { "vpclmulqdq",     { XM, Vex, EXx, PCLMUL }, PREFIX_DATA },
6728     { Bad_Opcode },
6729     { VEX_LEN_TABLE (VEX_LEN_0F3A46) },
6730     { Bad_Opcode },
6731     /* 48 */
6732     { "vpermil2ps",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6733     { "vpermil2pd",     { XM, Vex, EXx, XMVexI4, VexI4 }, PREFIX_DATA },
6734     { VEX_W_TABLE (VEX_W_0F3A4A) },
6735     { VEX_W_TABLE (VEX_W_0F3A4B) },
6736     { VEX_W_TABLE (VEX_W_0F3A4C) },
6737     { Bad_Opcode },
6738     { Bad_Opcode },
6739     { Bad_Opcode },
6740     /* 50 */
6741     { Bad_Opcode },
6742     { Bad_Opcode },
6743     { Bad_Opcode },
6744     { Bad_Opcode },
6745     { Bad_Opcode },
6746     { Bad_Opcode },
6747     { Bad_Opcode },
6748     { Bad_Opcode },
6749     /* 58 */
6750     { Bad_Opcode },
6751     { Bad_Opcode },
6752     { Bad_Opcode },
6753     { Bad_Opcode },
6754     { "vfmaddsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6755     { "vfmaddsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6756     { "vfmsubaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6757     { "vfmsubaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6758     /* 60 */
6759     { VEX_LEN_TABLE (VEX_LEN_0F3A60) },
6760     { VEX_LEN_TABLE (VEX_LEN_0F3A61) },
6761     { VEX_LEN_TABLE (VEX_LEN_0F3A62) },
6762     { VEX_LEN_TABLE (VEX_LEN_0F3A63) },
6763     { Bad_Opcode },
6764     { Bad_Opcode },
6765     { Bad_Opcode },
6766     { Bad_Opcode },
6767     /* 68 */
6768     { "vfmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6769     { "vfmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6770     { "vfmaddss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6771     { "vfmaddsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6772     { "vfmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6773     { "vfmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6774     { "vfmsubss",       { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6775     { "vfmsubsd",       { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6776     /* 70 */
6777     { Bad_Opcode },
6778     { Bad_Opcode },
6779     { Bad_Opcode },
6780     { Bad_Opcode },
6781     { Bad_Opcode },
6782     { Bad_Opcode },
6783     { Bad_Opcode },
6784     { Bad_Opcode },
6785     /* 78 */
6786     { "vfnmaddps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6787     { "vfnmaddpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6788     { "vfnmaddss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6789     { "vfnmaddsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6790     { "vfnmsubps", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6791     { "vfnmsubpd", { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
6792     { "vfnmsubss",      { XMScalar, VexScalar, EXd, XMVexScalarI4 }, PREFIX_DATA },
6793     { "vfnmsubsd",      { XMScalar, VexScalar, EXq, XMVexScalarI4 }, PREFIX_DATA },
6794     /* 80 */
6795     { Bad_Opcode },
6796     { Bad_Opcode },
6797     { Bad_Opcode },
6798     { Bad_Opcode },
6799     { Bad_Opcode },
6800     { Bad_Opcode },
6801     { Bad_Opcode },
6802     { Bad_Opcode },
6803     /* 88 */
6804     { Bad_Opcode },
6805     { Bad_Opcode },
6806     { Bad_Opcode },
6807     { Bad_Opcode },
6808     { Bad_Opcode },
6809     { Bad_Opcode },
6810     { Bad_Opcode },
6811     { Bad_Opcode },
6812     /* 90 */
6813     { Bad_Opcode },
6814     { Bad_Opcode },
6815     { Bad_Opcode },
6816     { Bad_Opcode },
6817     { Bad_Opcode },
6818     { Bad_Opcode },
6819     { Bad_Opcode },
6820     { Bad_Opcode },
6821     /* 98 */
6822     { Bad_Opcode },
6823     { Bad_Opcode },
6824     { Bad_Opcode },
6825     { Bad_Opcode },
6826     { Bad_Opcode },
6827     { Bad_Opcode },
6828     { Bad_Opcode },
6829     { Bad_Opcode },
6830     /* a0 */
6831     { Bad_Opcode },
6832     { Bad_Opcode },
6833     { Bad_Opcode },
6834     { Bad_Opcode },
6835     { Bad_Opcode },
6836     { Bad_Opcode },
6837     { Bad_Opcode },
6838     { Bad_Opcode },
6839     /* a8 */
6840     { Bad_Opcode },
6841     { Bad_Opcode },
6842     { Bad_Opcode },
6843     { Bad_Opcode },
6844     { Bad_Opcode },
6845     { Bad_Opcode },
6846     { Bad_Opcode },
6847     { Bad_Opcode },
6848     /* b0 */
6849     { Bad_Opcode },
6850     { Bad_Opcode },
6851     { Bad_Opcode },
6852     { Bad_Opcode },
6853     { Bad_Opcode },
6854     { Bad_Opcode },
6855     { Bad_Opcode },
6856     { Bad_Opcode },
6857     /* b8 */
6858     { Bad_Opcode },
6859     { Bad_Opcode },
6860     { Bad_Opcode },
6861     { Bad_Opcode },
6862     { Bad_Opcode },
6863     { Bad_Opcode },
6864     { Bad_Opcode },
6865     { Bad_Opcode },
6866     /* c0 */
6867     { Bad_Opcode },
6868     { Bad_Opcode },
6869     { Bad_Opcode },
6870     { Bad_Opcode },
6871     { Bad_Opcode },
6872     { Bad_Opcode },
6873     { Bad_Opcode },
6874     { Bad_Opcode },
6875     /* c8 */
6876     { Bad_Opcode },
6877     { Bad_Opcode },
6878     { Bad_Opcode },
6879     { Bad_Opcode },
6880     { Bad_Opcode },
6881     { Bad_Opcode },
6882     { VEX_W_TABLE (VEX_W_0F3ACE) },
6883     { VEX_W_TABLE (VEX_W_0F3ACF) },
6884     /* d0 */
6885     { Bad_Opcode },
6886     { Bad_Opcode },
6887     { Bad_Opcode },
6888     { Bad_Opcode },
6889     { Bad_Opcode },
6890     { Bad_Opcode },
6891     { Bad_Opcode },
6892     { Bad_Opcode },
6893     /* d8 */
6894     { Bad_Opcode },
6895     { Bad_Opcode },
6896     { Bad_Opcode },
6897     { Bad_Opcode },
6898     { Bad_Opcode },
6899     { Bad_Opcode },
6900     { VEX_W_TABLE (VEX_W_0F3ADE) },
6901     { VEX_LEN_TABLE (VEX_LEN_0F3ADF) },
6902     /* e0 */
6903     { Bad_Opcode },
6904     { Bad_Opcode },
6905     { Bad_Opcode },
6906     { Bad_Opcode },
6907     { Bad_Opcode },
6908     { Bad_Opcode },
6909     { Bad_Opcode },
6910     { Bad_Opcode },
6911     /* e8 */
6912     { Bad_Opcode },
6913     { Bad_Opcode },
6914     { Bad_Opcode },
6915     { Bad_Opcode },
6916     { Bad_Opcode },
6917     { Bad_Opcode },
6918     { Bad_Opcode },
6919     { Bad_Opcode },
6920     /* f0 */
6921     { VEX_LEN_TABLE (VEX_LEN_0F3AF0) },
6922     { Bad_Opcode },
6923     { Bad_Opcode },
6924     { Bad_Opcode },
6925     { Bad_Opcode },
6926     { Bad_Opcode },
6927     { Bad_Opcode },
6928     { Bad_Opcode },
6929     /* f8 */
6930     { Bad_Opcode },
6931     { Bad_Opcode },
6932     { Bad_Opcode },
6933     { Bad_Opcode },
6934     { Bad_Opcode },
6935     { Bad_Opcode },
6936     { Bad_Opcode },
6937     { Bad_Opcode },
6938   },
6939 };
6940
6941 #include "i386-dis-evex.h"
6942
6943 static const struct dis386 vex_len_table[][2] = {
6944   /* VEX_LEN_0F12_P_0 */
6945   {
6946     { MOD_TABLE (MOD_0F12_PREFIX_0) },
6947   },
6948
6949   /* VEX_LEN_0F12_P_2 */
6950   {
6951     { "%XEVmovlpYX",    { XM, Vex, Mq }, 0 },
6952   },
6953
6954   /* VEX_LEN_0F13 */
6955   {
6956     { "%XEVmovlpYX",    { Mq, XM }, PREFIX_OPCODE },
6957   },
6958
6959   /* VEX_LEN_0F16_P_0 */
6960   {
6961     { MOD_TABLE (MOD_0F16_PREFIX_0) },
6962   },
6963
6964   /* VEX_LEN_0F16_P_2 */
6965   {
6966     { "%XEVmovhpYX",    { XM, Vex, Mq }, 0 },
6967   },
6968
6969   /* VEX_LEN_0F17 */
6970   {
6971     { "%XEVmovhpYX",    { Mq, XM }, PREFIX_OPCODE },
6972   },
6973
6974   /* VEX_LEN_0F41 */
6975   {
6976     { Bad_Opcode },
6977     { VEX_W_TABLE (VEX_W_0F41_L_1) },
6978   },
6979
6980   /* VEX_LEN_0F42 */
6981   {
6982     { Bad_Opcode },
6983     { VEX_W_TABLE (VEX_W_0F42_L_1) },
6984   },
6985
6986   /* VEX_LEN_0F44 */
6987   {
6988     { VEX_W_TABLE (VEX_W_0F44_L_0) },
6989   },
6990
6991   /* VEX_LEN_0F45 */
6992   {
6993     { Bad_Opcode },
6994     { VEX_W_TABLE (VEX_W_0F45_L_1) },
6995   },
6996
6997   /* VEX_LEN_0F46 */
6998   {
6999     { Bad_Opcode },
7000     { VEX_W_TABLE (VEX_W_0F46_L_1) },
7001   },
7002
7003   /* VEX_LEN_0F47 */
7004   {
7005     { Bad_Opcode },
7006     { VEX_W_TABLE (VEX_W_0F47_L_1) },
7007   },
7008
7009   /* VEX_LEN_0F4A */
7010   {
7011     { Bad_Opcode },
7012     { VEX_W_TABLE (VEX_W_0F4A_L_1) },
7013   },
7014
7015   /* VEX_LEN_0F4B */
7016   {
7017     { Bad_Opcode },
7018     { VEX_W_TABLE (VEX_W_0F4B_L_1) },
7019   },
7020
7021   /* VEX_LEN_0F6E */
7022   {
7023     { "%XEvmovYK",      { XMScalar, Edq }, PREFIX_DATA },
7024   },
7025
7026   /* VEX_LEN_0F77 */
7027   {
7028     { "vzeroupper",     { XX }, 0 },
7029     { "vzeroall",       { XX }, 0 },
7030   },
7031
7032   /* VEX_LEN_0F7E_P_1 */
7033   {
7034     { "%XEvmovqY",      { XMScalar, EXq }, 0 },
7035   },
7036
7037   /* VEX_LEN_0F7E_P_2 */
7038   {
7039     { "%XEvmovK",       { Edq, XMScalar }, 0 },
7040   },
7041
7042   /* VEX_LEN_0F90 */
7043   {
7044     { VEX_W_TABLE (VEX_W_0F90_L_0) },
7045   },
7046
7047   /* VEX_LEN_0F91 */
7048   {
7049     { VEX_W_TABLE (VEX_W_0F91_L_0) },
7050   },
7051
7052   /* VEX_LEN_0F92 */
7053   {
7054     { VEX_W_TABLE (VEX_W_0F92_L_0) },
7055   },
7056
7057   /* VEX_LEN_0F93 */
7058   {
7059     { VEX_W_TABLE (VEX_W_0F93_L_0) },
7060   },
7061
7062   /* VEX_LEN_0F98 */
7063   {
7064     { VEX_W_TABLE (VEX_W_0F98_L_0) },
7065   },
7066
7067   /* VEX_LEN_0F99 */
7068   {
7069     { VEX_W_TABLE (VEX_W_0F99_L_0) },
7070   },
7071
7072   /* VEX_LEN_0FAE_R_2 */
7073   {
7074     { "vldmxcsr",       { Md }, 0 },
7075   },
7076
7077   /* VEX_LEN_0FAE_R_3 */
7078   {
7079     { "vstmxcsr",       { Md }, 0 },
7080   },
7081
7082   /* VEX_LEN_0FC4 */
7083   {
7084     { "%XEvpinsrwY",    { XM, Vex, Edw, Ib }, PREFIX_DATA },
7085   },
7086
7087   /* VEX_LEN_0FD6 */
7088   {
7089     { "%XEvmovqY",      { EXqS, XMScalar }, PREFIX_DATA },
7090   },
7091
7092   /* VEX_LEN_0F3816 */
7093   {
7094     { Bad_Opcode },
7095     { VEX_W_TABLE (VEX_W_0F3816_L_1) },
7096   },
7097
7098   /* VEX_LEN_0F3819 */
7099   {
7100     { Bad_Opcode },
7101     { VEX_W_TABLE (VEX_W_0F3819_L_1) },
7102   },
7103
7104   /* VEX_LEN_0F381A */
7105   {
7106     { Bad_Opcode },
7107     { VEX_W_TABLE (VEX_W_0F381A_L_1) },
7108   },
7109
7110   /* VEX_LEN_0F3836 */
7111   {
7112     { Bad_Opcode },
7113     { VEX_W_TABLE (VEX_W_0F3836) },
7114   },
7115
7116   /* VEX_LEN_0F3841 */
7117   {
7118     { "vphminposuw",    { XM, EXx }, PREFIX_DATA },
7119   },
7120
7121   /* VEX_LEN_0F3849_X86_64 */
7122   {
7123     { VEX_W_TABLE (VEX_W_0F3849_X86_64_L_0) },
7124   },
7125
7126   /* VEX_LEN_0F384B_X86_64 */
7127   {
7128     { VEX_W_TABLE (VEX_W_0F384B_X86_64_L_0) },
7129   },
7130
7131   /* VEX_LEN_0F385A */
7132   {
7133     { Bad_Opcode },
7134     { VEX_W_TABLE (VEX_W_0F385A_L_0) },
7135   },
7136
7137   /* VEX_LEN_0F385C_X86_64 */
7138   {
7139     { VEX_W_TABLE (VEX_W_0F385C_X86_64_L_0) },
7140   },
7141
7142   /* VEX_LEN_0F385E_X86_64 */
7143   {
7144     { VEX_W_TABLE (VEX_W_0F385E_X86_64_L_0) },
7145   },
7146
7147   /* VEX_LEN_0F386C_X86_64 */
7148   {
7149     { VEX_W_TABLE (VEX_W_0F386C_X86_64_L_0) },
7150   },
7151
7152   /* VEX_LEN_0F38CB_P_3_W_0 */
7153   {
7154     { Bad_Opcode },
7155     { "vsha512rnds2", { XM, Vex, Rxmmq }, 0 },
7156   },
7157
7158   /* VEX_LEN_0F38CC_P_3_W_0 */
7159   {
7160     { Bad_Opcode },
7161     { "vsha512msg1", { XM, Rxmmq }, 0 },
7162   },
7163
7164   /* VEX_LEN_0F38CD_P_3_W_0 */
7165   {
7166     { Bad_Opcode },
7167     { "vsha512msg2", { XM, Rymm }, 0 },
7168   },
7169
7170   /* VEX_LEN_0F38DA_W_0_P_0 */
7171   {
7172     { "vsm3msg1", { XM, Vex, EXxmm }, 0 },
7173   },
7174
7175   /* VEX_LEN_0F38DA_W_0_P_2 */
7176   {
7177     { "vsm3msg2", { XM, Vex, EXxmm }, 0 },
7178   },
7179
7180   /* VEX_LEN_0F38DB */
7181   {
7182     { "vaesimc",        { XM, EXx }, PREFIX_DATA },
7183   },
7184
7185   /* VEX_LEN_0F38F2 */
7186   {
7187     { PREFIX_TABLE (PREFIX_VEX_0F38F2_L_0) },
7188   },
7189
7190   /* VEX_LEN_0F38F3 */
7191   {
7192     { PREFIX_TABLE (PREFIX_VEX_0F38F3_L_0) },
7193   },
7194
7195   /* VEX_LEN_0F38F5 */
7196   {
7197     { PREFIX_TABLE(PREFIX_VEX_0F38F5_L_0) },
7198   },
7199
7200   /* VEX_LEN_0F38F6 */
7201   {
7202     { PREFIX_TABLE(PREFIX_VEX_0F38F6_L_0) },
7203   },
7204
7205   /* VEX_LEN_0F38F7 */
7206   {
7207     { PREFIX_TABLE(PREFIX_VEX_0F38F7_L_0) },
7208   },
7209
7210   /* VEX_LEN_0F3A00 */
7211   {
7212     { Bad_Opcode },
7213     { VEX_W_TABLE (VEX_W_0F3A00_L_1) },
7214   },
7215
7216   /* VEX_LEN_0F3A01 */
7217   {
7218     { Bad_Opcode },
7219     { VEX_W_TABLE (VEX_W_0F3A01_L_1) },
7220   },
7221
7222   /* VEX_LEN_0F3A06 */
7223   {
7224     { Bad_Opcode },
7225     { VEX_W_TABLE (VEX_W_0F3A06_L_1) },
7226   },
7227
7228   /* VEX_LEN_0F3A14 */
7229   {
7230     { "%XEvpextrb",     { Edb, XM, Ib }, PREFIX_DATA },
7231   },
7232
7233   /* VEX_LEN_0F3A15 */
7234   {
7235     { "%XEvpextrw",     { Edw, XM, Ib }, PREFIX_DATA },
7236   },
7237
7238   /* VEX_LEN_0F3A16  */
7239   {
7240     { "%XEvpextrK",     { Edq, XM, Ib }, PREFIX_DATA },
7241   },
7242
7243   /* VEX_LEN_0F3A17 */
7244   {
7245     { "%XEvextractps",  { Ed, XM, Ib }, PREFIX_DATA },
7246   },
7247
7248   /* VEX_LEN_0F3A18 */
7249   {
7250     { Bad_Opcode },
7251     { VEX_W_TABLE (VEX_W_0F3A18_L_1) },
7252   },
7253
7254   /* VEX_LEN_0F3A19 */
7255   {
7256     { Bad_Opcode },
7257     { VEX_W_TABLE (VEX_W_0F3A19_L_1) },
7258   },
7259
7260   /* VEX_LEN_0F3A20 */
7261   {
7262     { "%XEvpinsrbY",    { XM, Vex, Edb, Ib }, PREFIX_DATA },
7263   },
7264
7265   /* VEX_LEN_0F3A21 */
7266   {
7267     { "%XEvinsertpsY",  { XM, Vex, EXd, Ib }, PREFIX_DATA },
7268   },
7269
7270   /* VEX_LEN_0F3A22 */
7271   {
7272     { "%XEvpinsrYK",    { XM, Vex, Edq, Ib }, PREFIX_DATA },
7273   },
7274
7275   /* VEX_LEN_0F3A30 */
7276   {
7277     { "kshiftr%BW",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7278   },
7279
7280   /* VEX_LEN_0F3A31 */
7281   {
7282     { "kshiftr%DQ",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7283   },
7284
7285   /* VEX_LEN_0F3A32 */
7286   {
7287     { "kshiftl%BW",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7288   },
7289
7290   /* VEX_LEN_0F3A33 */
7291   {
7292     { "kshiftl%DQ",     { MaskG, MaskR, Ib }, PREFIX_DATA },
7293   },
7294
7295   /* VEX_LEN_0F3A38 */
7296   {
7297     { Bad_Opcode },
7298     { VEX_W_TABLE (VEX_W_0F3A38_L_1) },
7299   },
7300
7301   /* VEX_LEN_0F3A39 */
7302   {
7303     { Bad_Opcode },
7304     { VEX_W_TABLE (VEX_W_0F3A39_L_1) },
7305   },
7306
7307   /* VEX_LEN_0F3A41 */
7308   {
7309     { "vdppd",          { XM, Vex, EXx, Ib }, PREFIX_DATA },
7310   },
7311
7312   /* VEX_LEN_0F3A46 */
7313   {
7314     { Bad_Opcode },
7315     { VEX_W_TABLE (VEX_W_0F3A46_L_1) },
7316   },
7317
7318   /* VEX_LEN_0F3A60 */
7319   {
7320     { "vpcmpestrm!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7321   },
7322
7323   /* VEX_LEN_0F3A61 */
7324   {
7325     { "vpcmpestri!%LQ", { XM, EXx, Ib }, PREFIX_DATA },
7326   },
7327
7328   /* VEX_LEN_0F3A62 */
7329   {
7330     { "vpcmpistrm",     { XM, EXx, Ib }, PREFIX_DATA },
7331   },
7332
7333   /* VEX_LEN_0F3A63 */
7334   {
7335     { "vpcmpistri",     { XM, EXx, Ib }, PREFIX_DATA },
7336   },
7337
7338   /* VEX_LEN_0F3ADE_W_0 */
7339   {
7340     { "vsm3rnds2", { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7341   },
7342
7343   /* VEX_LEN_0F3ADF */
7344   {
7345     { "vaeskeygenassist", { XM, EXx, Ib }, PREFIX_DATA },
7346   },
7347
7348   /* VEX_LEN_0F3AF0 */
7349   {
7350     { PREFIX_TABLE (PREFIX_VEX_0F3AF0_L_0) },
7351   },
7352
7353   /* VEX_LEN_MAP7_F8 */
7354   {
7355     { VEX_W_TABLE (VEX_W_MAP7_F8_L_0) },
7356   },
7357
7358   /* VEX_LEN_XOP_08_85 */
7359   {
7360     { VEX_W_TABLE (VEX_W_XOP_08_85_L_0) },
7361   },
7362
7363   /* VEX_LEN_XOP_08_86 */
7364   {
7365     { VEX_W_TABLE (VEX_W_XOP_08_86_L_0) },
7366   },
7367
7368   /* VEX_LEN_XOP_08_87 */
7369   {
7370     { VEX_W_TABLE (VEX_W_XOP_08_87_L_0) },
7371   },
7372
7373   /* VEX_LEN_XOP_08_8E */
7374   {
7375     { VEX_W_TABLE (VEX_W_XOP_08_8E_L_0) },
7376   },
7377
7378   /* VEX_LEN_XOP_08_8F */
7379   {
7380     { VEX_W_TABLE (VEX_W_XOP_08_8F_L_0) },
7381   },
7382
7383   /* VEX_LEN_XOP_08_95 */
7384   {
7385     { VEX_W_TABLE (VEX_W_XOP_08_95_L_0) },
7386   },
7387
7388   /* VEX_LEN_XOP_08_96 */
7389   {
7390     { VEX_W_TABLE (VEX_W_XOP_08_96_L_0) },
7391   },
7392
7393   /* VEX_LEN_XOP_08_97 */
7394   {
7395     { VEX_W_TABLE (VEX_W_XOP_08_97_L_0) },
7396   },
7397
7398   /* VEX_LEN_XOP_08_9E */
7399   {
7400     { VEX_W_TABLE (VEX_W_XOP_08_9E_L_0) },
7401   },
7402
7403   /* VEX_LEN_XOP_08_9F */
7404   {
7405     { VEX_W_TABLE (VEX_W_XOP_08_9F_L_0) },
7406   },
7407
7408   /* VEX_LEN_XOP_08_A3 */
7409   {
7410     { "vpperm",         { XM, Vex, EXx, XMVexI4 }, 0 },
7411   },
7412
7413   /* VEX_LEN_XOP_08_A6 */
7414   {
7415     { VEX_W_TABLE (VEX_W_XOP_08_A6_L_0) },
7416   },
7417
7418   /* VEX_LEN_XOP_08_B6 */
7419   {
7420     { VEX_W_TABLE (VEX_W_XOP_08_B6_L_0) },
7421   },
7422
7423   /* VEX_LEN_XOP_08_C0 */
7424   {
7425     { VEX_W_TABLE (VEX_W_XOP_08_C0_L_0) },
7426   },
7427
7428   /* VEX_LEN_XOP_08_C1 */
7429   {
7430     { VEX_W_TABLE (VEX_W_XOP_08_C1_L_0) },
7431   },
7432
7433   /* VEX_LEN_XOP_08_C2 */
7434   {
7435     { VEX_W_TABLE (VEX_W_XOP_08_C2_L_0) },
7436   },
7437
7438   /* VEX_LEN_XOP_08_C3 */
7439   {
7440     { VEX_W_TABLE (VEX_W_XOP_08_C3_L_0) },
7441   },
7442
7443   /* VEX_LEN_XOP_08_CC */
7444   {
7445     { VEX_W_TABLE (VEX_W_XOP_08_CC_L_0) },
7446   },
7447
7448   /* VEX_LEN_XOP_08_CD */
7449   {
7450     { VEX_W_TABLE (VEX_W_XOP_08_CD_L_0) },
7451   },
7452
7453   /* VEX_LEN_XOP_08_CE */
7454   {
7455     { VEX_W_TABLE (VEX_W_XOP_08_CE_L_0) },
7456   },
7457
7458   /* VEX_LEN_XOP_08_CF */
7459   {
7460     { VEX_W_TABLE (VEX_W_XOP_08_CF_L_0) },
7461   },
7462
7463   /* VEX_LEN_XOP_08_EC */
7464   {
7465     { VEX_W_TABLE (VEX_W_XOP_08_EC_L_0) },
7466   },
7467
7468   /* VEX_LEN_XOP_08_ED */
7469   {
7470     { VEX_W_TABLE (VEX_W_XOP_08_ED_L_0) },
7471   },
7472
7473   /* VEX_LEN_XOP_08_EE */
7474   {
7475     { VEX_W_TABLE (VEX_W_XOP_08_EE_L_0) },
7476   },
7477
7478   /* VEX_LEN_XOP_08_EF */
7479   {
7480     { VEX_W_TABLE (VEX_W_XOP_08_EF_L_0) },
7481   },
7482
7483   /* VEX_LEN_XOP_09_01 */
7484   {
7485     { REG_TABLE (REG_XOP_09_01_L_0) },
7486   },
7487
7488   /* VEX_LEN_XOP_09_02 */
7489   {
7490     { REG_TABLE (REG_XOP_09_02_L_0) },
7491   },
7492
7493   /* VEX_LEN_XOP_09_12 */
7494   {
7495     { REG_TABLE (REG_XOP_09_12_L_0) },
7496   },
7497
7498   /* VEX_LEN_XOP_09_82_W_0 */
7499   {
7500     { "vfrczss",        { XM, EXd }, 0 },
7501   },
7502
7503   /* VEX_LEN_XOP_09_83_W_0 */
7504   {
7505     { "vfrczsd",        { XM, EXq }, 0 },
7506   },
7507
7508   /* VEX_LEN_XOP_09_90 */
7509   {
7510     { "vprotb",         { XM, EXx, VexW }, 0 },
7511   },
7512
7513   /* VEX_LEN_XOP_09_91 */
7514   {
7515     { "vprotw",         { XM, EXx, VexW }, 0 },
7516   },
7517
7518   /* VEX_LEN_XOP_09_92 */
7519   {
7520     { "vprotd",         { XM, EXx, VexW }, 0 },
7521   },
7522
7523   /* VEX_LEN_XOP_09_93 */
7524   {
7525     { "vprotq",         { XM, EXx, VexW }, 0 },
7526   },
7527
7528   /* VEX_LEN_XOP_09_94 */
7529   {
7530     { "vpshlb",         { XM, EXx, VexW }, 0 },
7531   },
7532
7533   /* VEX_LEN_XOP_09_95 */
7534   {
7535     { "vpshlw",         { XM, EXx, VexW }, 0 },
7536   },
7537
7538   /* VEX_LEN_XOP_09_96 */
7539   {
7540     { "vpshld",         { XM, EXx, VexW }, 0 },
7541   },
7542
7543   /* VEX_LEN_XOP_09_97 */
7544   {
7545     { "vpshlq",         { XM, EXx, VexW }, 0 },
7546   },
7547
7548   /* VEX_LEN_XOP_09_98 */
7549   {
7550     { "vpshab",         { XM, EXx, VexW }, 0 },
7551   },
7552
7553   /* VEX_LEN_XOP_09_99 */
7554   {
7555     { "vpshaw",         { XM, EXx, VexW }, 0 },
7556   },
7557
7558   /* VEX_LEN_XOP_09_9A */
7559   {
7560     { "vpshad",         { XM, EXx, VexW }, 0 },
7561   },
7562
7563   /* VEX_LEN_XOP_09_9B */
7564   {
7565     { "vpshaq",         { XM, EXx, VexW }, 0 },
7566   },
7567
7568   /* VEX_LEN_XOP_09_C1 */
7569   {
7570     { VEX_W_TABLE (VEX_W_XOP_09_C1_L_0) },
7571   },
7572
7573   /* VEX_LEN_XOP_09_C2 */
7574   {
7575     { VEX_W_TABLE (VEX_W_XOP_09_C2_L_0) },
7576   },
7577
7578   /* VEX_LEN_XOP_09_C3 */
7579   {
7580     { VEX_W_TABLE (VEX_W_XOP_09_C3_L_0) },
7581   },
7582
7583   /* VEX_LEN_XOP_09_C6 */
7584   {
7585     { VEX_W_TABLE (VEX_W_XOP_09_C6_L_0) },
7586   },
7587
7588   /* VEX_LEN_XOP_09_C7 */
7589   {
7590     { VEX_W_TABLE (VEX_W_XOP_09_C7_L_0) },
7591   },
7592
7593   /* VEX_LEN_XOP_09_CB */
7594   {
7595     { VEX_W_TABLE (VEX_W_XOP_09_CB_L_0) },
7596   },
7597
7598   /* VEX_LEN_XOP_09_D1 */
7599   {
7600     { VEX_W_TABLE (VEX_W_XOP_09_D1_L_0) },
7601   },
7602
7603   /* VEX_LEN_XOP_09_D2 */
7604   {
7605     { VEX_W_TABLE (VEX_W_XOP_09_D2_L_0) },
7606   },
7607
7608   /* VEX_LEN_XOP_09_D3 */
7609   {
7610     { VEX_W_TABLE (VEX_W_XOP_09_D3_L_0) },
7611   },
7612
7613   /* VEX_LEN_XOP_09_D6 */
7614   {
7615     { VEX_W_TABLE (VEX_W_XOP_09_D6_L_0) },
7616   },
7617
7618   /* VEX_LEN_XOP_09_D7 */
7619   {
7620     { VEX_W_TABLE (VEX_W_XOP_09_D7_L_0) },
7621   },
7622
7623   /* VEX_LEN_XOP_09_DB */
7624   {
7625     { VEX_W_TABLE (VEX_W_XOP_09_DB_L_0) },
7626   },
7627
7628   /* VEX_LEN_XOP_09_E1 */
7629   {
7630     { VEX_W_TABLE (VEX_W_XOP_09_E1_L_0) },
7631   },
7632
7633   /* VEX_LEN_XOP_09_E2 */
7634   {
7635     { VEX_W_TABLE (VEX_W_XOP_09_E2_L_0) },
7636   },
7637
7638   /* VEX_LEN_XOP_09_E3 */
7639   {
7640     { VEX_W_TABLE (VEX_W_XOP_09_E3_L_0) },
7641   },
7642
7643   /* VEX_LEN_XOP_0A_12 */
7644   {
7645     { REG_TABLE (REG_XOP_0A_12_L_0) },
7646   },
7647 };
7648
7649 #include "i386-dis-evex-len.h"
7650
7651 static const struct dis386 vex_w_table[][2] = {
7652   {
7653     /* VEX_W_0F41_L_1_M_1 */
7654     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_0) },
7655     { PREFIX_TABLE (PREFIX_VEX_0F41_L_1_W_1) },
7656   },
7657   {
7658     /* VEX_W_0F42_L_1_M_1 */
7659     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_0) },
7660     { PREFIX_TABLE (PREFIX_VEX_0F42_L_1_W_1) },
7661   },
7662   {
7663     /* VEX_W_0F44_L_0_M_1 */
7664     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_0) },
7665     { PREFIX_TABLE (PREFIX_VEX_0F44_L_0_W_1) },
7666   },
7667   {
7668     /* VEX_W_0F45_L_1_M_1 */
7669     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_0) },
7670     { PREFIX_TABLE (PREFIX_VEX_0F45_L_1_W_1) },
7671   },
7672   {
7673     /* VEX_W_0F46_L_1_M_1 */
7674     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_0) },
7675     { PREFIX_TABLE (PREFIX_VEX_0F46_L_1_W_1) },
7676   },
7677   {
7678     /* VEX_W_0F47_L_1_M_1 */
7679     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_0) },
7680     { PREFIX_TABLE (PREFIX_VEX_0F47_L_1_W_1) },
7681   },
7682   {
7683     /* VEX_W_0F4A_L_1_M_1 */
7684     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_0) },
7685     { PREFIX_TABLE (PREFIX_VEX_0F4A_L_1_W_1) },
7686   },
7687   {
7688     /* VEX_W_0F4B_L_1_M_1 */
7689     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_0) },
7690     { PREFIX_TABLE (PREFIX_VEX_0F4B_L_1_W_1) },
7691   },
7692   {
7693     /* VEX_W_0F90_L_0 */
7694     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_0) },
7695     { PREFIX_TABLE (PREFIX_VEX_0F90_L_0_W_1) },
7696   },
7697   {
7698     /* VEX_W_0F91_L_0_M_0 */
7699     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_0) },
7700     { PREFIX_TABLE (PREFIX_VEX_0F91_L_0_W_1) },
7701   },
7702   {
7703     /* VEX_W_0F92_L_0_M_1 */
7704     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_0) },
7705     { PREFIX_TABLE (PREFIX_VEX_0F92_L_0_W_1) },
7706   },
7707   {
7708     /* VEX_W_0F93_L_0_M_1 */
7709     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_0) },
7710     { PREFIX_TABLE (PREFIX_VEX_0F93_L_0_W_1) },
7711   },
7712   {
7713     /* VEX_W_0F98_L_0_M_1 */
7714     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_0) },
7715     { PREFIX_TABLE (PREFIX_VEX_0F98_L_0_W_1) },
7716   },
7717   {
7718     /* VEX_W_0F99_L_0_M_1 */
7719     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_0) },
7720     { PREFIX_TABLE (PREFIX_VEX_0F99_L_0_W_1) },
7721   },
7722   {
7723     /* VEX_W_0F380C  */
7724     { "%XEvpermilps",   { XM, Vex, EXx }, PREFIX_DATA },
7725   },
7726   {
7727     /* VEX_W_0F380D  */
7728     { "vpermilpd",      { XM, Vex, EXx }, PREFIX_DATA },
7729   },
7730   {
7731     /* VEX_W_0F380E  */
7732     { "vtestps",        { XM, EXx }, PREFIX_DATA },
7733   },
7734   {
7735     /* VEX_W_0F380F  */
7736     { "vtestpd",        { XM, EXx }, PREFIX_DATA },
7737   },
7738   {
7739     /* VEX_W_0F3813 */
7740     { "vcvtph2ps", { XM, EXxmmq }, PREFIX_DATA },
7741   },
7742   {
7743     /* VEX_W_0F3816_L_1  */
7744     { "vpermps",        { XM, Vex, EXx }, PREFIX_DATA },
7745   },
7746   {
7747     /* VEX_W_0F3818 */
7748     { "%XEvbroadcastss",        { XM, EXd }, PREFIX_DATA },
7749   },
7750   {
7751     /* VEX_W_0F3819_L_1 */
7752     { "vbroadcastsd",   { XM, EXq }, PREFIX_DATA },
7753   },
7754   {
7755     /* VEX_W_0F381A_L_1 */
7756     { "vbroadcastf128", { XM, Mxmm }, PREFIX_DATA },
7757   },
7758   {
7759     /* VEX_W_0F382C */
7760     { "vmaskmovps",     { XM, Vex, Mx }, PREFIX_DATA },
7761   },
7762   {
7763     /* VEX_W_0F382D */
7764     { "vmaskmovpd",     { XM, Vex, Mx }, PREFIX_DATA },
7765   },
7766   {
7767     /* VEX_W_0F382E */
7768     { "vmaskmovps",     { Mx, Vex, XM }, PREFIX_DATA },
7769   },
7770   {
7771     /* VEX_W_0F382F */
7772     { "vmaskmovpd",     { Mx, Vex, XM }, PREFIX_DATA },
7773   },
7774   {
7775     /* VEX_W_0F3836  */
7776     { "vpermd",         { XM, Vex, EXx }, PREFIX_DATA },
7777   },
7778   {
7779     /* VEX_W_0F3846 */
7780     { "vpsravd",        { XM, Vex, EXx }, PREFIX_DATA },
7781   },
7782   {
7783     /* VEX_W_0F3849_X86_64_L_0 */
7784     { MOD_TABLE (MOD_VEX_0F3849_X86_64_L_0_W_0) },
7785   },
7786   {
7787     /* VEX_W_0F384B_X86_64_L_0 */
7788     { PREFIX_TABLE (PREFIX_VEX_0F384B_X86_64_L_0_W_0) },
7789   },
7790   {
7791     /* VEX_W_0F3850 */
7792     { PREFIX_TABLE (PREFIX_VEX_0F3850_W_0) },
7793   },
7794   {
7795     /* VEX_W_0F3851 */
7796     { PREFIX_TABLE (PREFIX_VEX_0F3851_W_0) },
7797   },
7798   {
7799     /* VEX_W_0F3852 */
7800     { "%XVvpdpwssd",    { XM, Vex, EXx }, PREFIX_DATA },
7801   },
7802   {
7803     /* VEX_W_0F3853 */
7804     { "%XVvpdpwssds",   { XM, Vex, EXx }, PREFIX_DATA },
7805   },
7806   {
7807     /* VEX_W_0F3858 */
7808     { "%XEvpbroadcastd", { XM, EXd }, PREFIX_DATA },
7809   },
7810   {
7811     /* VEX_W_0F3859 */
7812     { "vpbroadcastq", { XM, EXq }, PREFIX_DATA },
7813   },
7814   {
7815     /* VEX_W_0F385A_L_0 */
7816     { "vbroadcasti128", { XM, Mxmm }, PREFIX_DATA },
7817   },
7818   {
7819     /* VEX_W_0F385C_X86_64_L_0 */
7820     { PREFIX_TABLE (PREFIX_VEX_0F385C_X86_64_L_0_W_0) },
7821   },
7822   {
7823     /* VEX_W_0F385E_X86_64_L_0 */
7824     { PREFIX_TABLE (PREFIX_VEX_0F385E_X86_64_L_0_W_0) },
7825   },
7826   {
7827     /* VEX_W_0F386C_X86_64_L_0 */
7828     { PREFIX_TABLE (PREFIX_VEX_0F386C_X86_64_L_0_W_0) },
7829   },
7830   {
7831     /* VEX_W_0F3872_P_1 */
7832     { "%XVvcvtneps2bf16%XY", { XMM, EXx }, 0 },
7833   },
7834   {
7835     /* VEX_W_0F3878 */
7836     { "%XEvpbroadcastb",        { XM, EXb }, PREFIX_DATA },
7837   },
7838   {
7839     /* VEX_W_0F3879 */
7840     { "%XEvpbroadcastw",        { XM, EXw }, PREFIX_DATA },
7841   },
7842   {
7843     /* VEX_W_0F38B0 */
7844     { PREFIX_TABLE (PREFIX_VEX_0F38B0_W_0) },
7845   },
7846   {
7847     /* VEX_W_0F38B1 */
7848     { PREFIX_TABLE (PREFIX_VEX_0F38B1_W_0) },
7849   },
7850   {
7851     /* VEX_W_0F38B4 */
7852     { Bad_Opcode },
7853     { "%XVvpmadd52luq", { XM, Vex, EXx }, PREFIX_DATA },
7854   },
7855   {
7856     /* VEX_W_0F38B5 */
7857     { Bad_Opcode },
7858     { "%XVvpmadd52huq", { XM, Vex, EXx }, PREFIX_DATA },
7859   },
7860   {
7861     /* VEX_W_0F38CB_P_3 */
7862     { VEX_LEN_TABLE (VEX_LEN_0F38CB_P_3_W_0) },
7863   },
7864   {
7865     /* VEX_W_0F38CC_P_3 */
7866     { VEX_LEN_TABLE (VEX_LEN_0F38CC_P_3_W_0) },
7867   },
7868   {
7869     /* VEX_W_0F38CD_P_3 */
7870     { VEX_LEN_TABLE (VEX_LEN_0F38CD_P_3_W_0) },
7871   },
7872   {
7873     /* VEX_W_0F38CF */
7874     { "%XEvgf2p8mulb", { XM, Vex, EXx }, PREFIX_DATA },
7875   },
7876   {
7877     /* VEX_W_0F38D2 */
7878     { PREFIX_TABLE (PREFIX_VEX_0F38D2_W_0) },
7879   },
7880   {
7881     /* VEX_W_0F38D3 */
7882     { PREFIX_TABLE (PREFIX_VEX_0F38D3_W_0) },
7883   },
7884   {
7885     /* VEX_W_0F38DA */
7886     { PREFIX_TABLE (PREFIX_VEX_0F38DA_W_0) },
7887   },
7888   {
7889     /* VEX_W_0F3A00_L_1 */
7890     { Bad_Opcode },
7891     { "%XEvpermq",              { XM, EXx, Ib }, PREFIX_DATA },
7892   },
7893   {
7894     /* VEX_W_0F3A01_L_1 */
7895     { Bad_Opcode },
7896     { "%XEvpermpd",     { XM, EXx, Ib }, PREFIX_DATA },
7897   },
7898   {
7899     /* VEX_W_0F3A02 */
7900     { "vpblendd",       { XM, Vex, EXx, Ib }, PREFIX_DATA },
7901   },
7902   {
7903     /* VEX_W_0F3A04 */
7904     { "%XEvpermilps",   { XM, EXx, Ib }, PREFIX_DATA },
7905   },
7906   {
7907     /* VEX_W_0F3A05 */
7908     { "vpermilpd",      { XM, EXx, Ib }, PREFIX_DATA },
7909   },
7910   {
7911     /* VEX_W_0F3A06_L_1 */
7912     { "vperm2f128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7913   },
7914   {
7915     /* VEX_W_0F3A18_L_1 */
7916     { "vinsertf128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7917   },
7918   {
7919     /* VEX_W_0F3A19_L_1 */
7920     { "vextractf128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7921   },
7922   {
7923     /* VEX_W_0F3A1D */
7924     { "%XEvcvtps2ph", { EXxmmq, XM, EXxEVexS, Ib }, PREFIX_DATA },
7925   },
7926   {
7927     /* VEX_W_0F3A38_L_1 */
7928     { "vinserti128",    { XM, Vex, EXxmm, Ib }, PREFIX_DATA },
7929   },
7930   {
7931     /* VEX_W_0F3A39_L_1 */
7932     { "vextracti128",   { EXxmm, XM, Ib }, PREFIX_DATA },
7933   },
7934   {
7935     /* VEX_W_0F3A46_L_1 */
7936     { "vperm2i128",     { XM, Vex, EXx, Ib }, PREFIX_DATA },
7937   },
7938   {
7939     /* VEX_W_0F3A4A */
7940     { "vblendvps",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7941   },
7942   {
7943     /* VEX_W_0F3A4B */
7944     { "vblendvpd",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7945   },
7946   {
7947     /* VEX_W_0F3A4C */
7948     { "vpblendvb",      { XM, Vex, EXx, XMVexI4 }, PREFIX_DATA },
7949   },
7950   {
7951     /* VEX_W_0F3ACE */
7952     { Bad_Opcode },
7953     { "%XEvgf2p8affineqb", { XM, Vex, EXx, Ib }, PREFIX_DATA },
7954   },
7955   {
7956     /* VEX_W_0F3ACF */
7957     { Bad_Opcode },
7958     { "%XEvgf2p8affineinvqb",  { XM, Vex, EXx, Ib }, PREFIX_DATA },
7959   },
7960   {
7961     /* VEX_W_0F3ADE */
7962     { VEX_LEN_TABLE (VEX_LEN_0F3ADE_W_0) },
7963   },
7964   {
7965     /* VEX_W_MAP7_F8_L_0 */
7966     { REG_TABLE (REG_VEX_MAP7_F8_L_0_W_0) },
7967   },
7968   /* VEX_W_XOP_08_85_L_0 */
7969   {
7970     { "vpmacssww",      { XM, Vex, EXx, XMVexI4 }, 0 },
7971   },
7972   /* VEX_W_XOP_08_86_L_0 */
7973   {
7974     { "vpmacsswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7975   },
7976   /* VEX_W_XOP_08_87_L_0 */
7977   {
7978     { "vpmacssdql",     { XM, Vex, EXx, XMVexI4 }, 0 },
7979   },
7980   /* VEX_W_XOP_08_8E_L_0 */
7981   {
7982     { "vpmacssdd",      { XM, Vex, EXx, XMVexI4 }, 0 },
7983   },
7984   /* VEX_W_XOP_08_8F_L_0 */
7985   {
7986     { "vpmacssdqh",     { XM, Vex, EXx, XMVexI4 }, 0 },
7987   },
7988   /* VEX_W_XOP_08_95_L_0 */
7989   {
7990     { "vpmacsww",       { XM, Vex, EXx, XMVexI4 }, 0 },
7991   },
7992   /* VEX_W_XOP_08_96_L_0 */
7993   {
7994     { "vpmacswd",       { XM, Vex, EXx, XMVexI4 }, 0 },
7995   },
7996   /* VEX_W_XOP_08_97_L_0 */
7997   {
7998     { "vpmacsdql",      { XM, Vex, EXx, XMVexI4 }, 0 },
7999   },
8000   /* VEX_W_XOP_08_9E_L_0 */
8001   {
8002     { "vpmacsdd",       { XM, Vex, EXx, XMVexI4 }, 0 },
8003   },
8004   /* VEX_W_XOP_08_9F_L_0 */
8005   {
8006     { "vpmacsdqh",      { XM, Vex, EXx, XMVexI4 }, 0 },
8007   },
8008   /* VEX_W_XOP_08_A6_L_0 */
8009   {
8010     { "vpmadcsswd",     { XM, Vex, EXx, XMVexI4 }, 0 },
8011   },
8012   /* VEX_W_XOP_08_B6_L_0 */
8013   {
8014     { "vpmadcswd",      { XM, Vex, EXx, XMVexI4 }, 0 },
8015   },
8016   /* VEX_W_XOP_08_C0_L_0 */
8017   {
8018     { "vprotb",         { XM, EXx, Ib }, 0 },
8019   },
8020   /* VEX_W_XOP_08_C1_L_0 */
8021   {
8022     { "vprotw",         { XM, EXx, Ib }, 0 },
8023   },
8024   /* VEX_W_XOP_08_C2_L_0 */
8025   {
8026     { "vprotd",         { XM, EXx, Ib }, 0 },
8027   },
8028   /* VEX_W_XOP_08_C3_L_0 */
8029   {
8030     { "vprotq",         { XM, EXx, Ib }, 0 },
8031   },
8032   /* VEX_W_XOP_08_CC_L_0 */
8033   {
8034      { "vpcomb",        { XM, Vex, EXx, VPCOM }, 0 },
8035   },
8036   /* VEX_W_XOP_08_CD_L_0 */
8037   {
8038      { "vpcomw",        { XM, Vex, EXx, VPCOM }, 0 },
8039   },
8040   /* VEX_W_XOP_08_CE_L_0 */
8041   {
8042      { "vpcomd",        { XM, Vex, EXx, VPCOM }, 0 },
8043   },
8044   /* VEX_W_XOP_08_CF_L_0 */
8045   {
8046      { "vpcomq",        { XM, Vex, EXx, VPCOM }, 0 },
8047   },
8048   /* VEX_W_XOP_08_EC_L_0 */
8049   {
8050      { "vpcomub",       { XM, Vex, EXx, VPCOM }, 0 },
8051   },
8052   /* VEX_W_XOP_08_ED_L_0 */
8053   {
8054      { "vpcomuw",       { XM, Vex, EXx, VPCOM }, 0 },
8055   },
8056   /* VEX_W_XOP_08_EE_L_0 */
8057   {
8058      { "vpcomud",       { XM, Vex, EXx, VPCOM }, 0 },
8059   },
8060   /* VEX_W_XOP_08_EF_L_0 */
8061   {
8062      { "vpcomuq",       { XM, Vex, EXx, VPCOM }, 0 },
8063   },
8064   /* VEX_W_XOP_09_80 */
8065   {
8066     { "vfrczps",        { XM, EXx }, 0 },
8067   },
8068   /* VEX_W_XOP_09_81 */
8069   {
8070     { "vfrczpd",        { XM, EXx }, 0 },
8071   },
8072   /* VEX_W_XOP_09_82 */
8073   {
8074     { VEX_LEN_TABLE (VEX_LEN_XOP_09_82_W_0) },
8075   },
8076   /* VEX_W_XOP_09_83 */
8077   {
8078     { VEX_LEN_TABLE (VEX_LEN_XOP_09_83_W_0) },
8079   },
8080   /* VEX_W_XOP_09_C1_L_0 */
8081   {
8082     { "vphaddbw",       { XM, EXxmm }, 0 },
8083   },
8084   /* VEX_W_XOP_09_C2_L_0 */
8085   {
8086     { "vphaddbd",       { XM, EXxmm }, 0 },
8087   },
8088   /* VEX_W_XOP_09_C3_L_0 */
8089   {
8090     { "vphaddbq",       { XM, EXxmm }, 0 },
8091   },
8092   /* VEX_W_XOP_09_C6_L_0 */
8093   {
8094     { "vphaddwd",       { XM, EXxmm }, 0 },
8095   },
8096   /* VEX_W_XOP_09_C7_L_0 */
8097   {
8098     { "vphaddwq",       { XM, EXxmm }, 0 },
8099   },
8100   /* VEX_W_XOP_09_CB_L_0 */
8101   {
8102     { "vphadddq",       { XM, EXxmm }, 0 },
8103   },
8104   /* VEX_W_XOP_09_D1_L_0 */
8105   {
8106     { "vphaddubw",      { XM, EXxmm }, 0 },
8107   },
8108   /* VEX_W_XOP_09_D2_L_0 */
8109   {
8110     { "vphaddubd",      { XM, EXxmm }, 0 },
8111   },
8112   /* VEX_W_XOP_09_D3_L_0 */
8113   {
8114     { "vphaddubq",      { XM, EXxmm }, 0 },
8115   },
8116   /* VEX_W_XOP_09_D6_L_0 */
8117   {
8118     { "vphadduwd",      { XM, EXxmm }, 0 },
8119   },
8120   /* VEX_W_XOP_09_D7_L_0 */
8121   {
8122     { "vphadduwq",      { XM, EXxmm }, 0 },
8123   },
8124   /* VEX_W_XOP_09_DB_L_0 */
8125   {
8126     { "vphaddudq",      { XM, EXxmm }, 0 },
8127   },
8128   /* VEX_W_XOP_09_E1_L_0 */
8129   {
8130     { "vphsubbw",       { XM, EXxmm }, 0 },
8131   },
8132   /* VEX_W_XOP_09_E2_L_0 */
8133   {
8134     { "vphsubwd",       { XM, EXxmm }, 0 },
8135   },
8136   /* VEX_W_XOP_09_E3_L_0 */
8137   {
8138     { "vphsubdq",       { XM, EXxmm }, 0 },
8139   },
8140
8141 #include "i386-dis-evex-w.h"
8142 };
8143
8144 static const struct dis386 mod_table[][2] = {
8145   {
8146     /* MOD_62_32BIT */
8147     { "bound{S|}",      { Gv, Ma }, 0 },
8148     { EVEX_TABLE () },
8149   },
8150   {
8151     /* MOD_C4_32BIT */
8152     { "lesS",           { Gv, Mp }, 0 },
8153     { VEX_C4_TABLE () },
8154   },
8155   {
8156     /* MOD_C5_32BIT */
8157     { "ldsS",           { Gv, Mp }, 0 },
8158     { VEX_C5_TABLE () },
8159   },
8160   {
8161     /* MOD_0F01_REG_0 */
8162     { X86_64_TABLE (X86_64_0F01_REG_0) },
8163     { RM_TABLE (RM_0F01_REG_0) },
8164   },
8165   {
8166     /* MOD_0F01_REG_1 */
8167     { X86_64_TABLE (X86_64_0F01_REG_1) },
8168     { RM_TABLE (RM_0F01_REG_1) },
8169   },
8170   {
8171     /* MOD_0F01_REG_2 */
8172     { X86_64_TABLE (X86_64_0F01_REG_2) },
8173     { RM_TABLE (RM_0F01_REG_2) },
8174   },
8175   {
8176     /* MOD_0F01_REG_3 */
8177     { X86_64_TABLE (X86_64_0F01_REG_3) },
8178     { RM_TABLE (RM_0F01_REG_3) },
8179   },
8180   {
8181     /* MOD_0F01_REG_5 */
8182     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_0) },
8183     { RM_TABLE (RM_0F01_REG_5_MOD_3) },
8184   },
8185   {
8186     /* MOD_0F01_REG_7 */
8187     { "invlpg",         { Mb }, 0 },
8188     { RM_TABLE (RM_0F01_REG_7_MOD_3) },
8189   },
8190   {
8191     /* MOD_0F12_PREFIX_0 */
8192     { "%XEVmovlpYX",    { XM, Vex, EXq }, 0 },
8193     { "%XEVmovhlpY%XS", { XM, Vex, EXq }, 0 },
8194   },
8195   {
8196     /* MOD_0F16_PREFIX_0 */
8197     { "%XEVmovhpYX",    { XM, Vex, EXq }, 0 },
8198     { "%XEVmovlhpY%XS", { XM, Vex, EXq }, 0 },
8199   },
8200   {
8201     /* MOD_0F18_REG_0 */
8202     { "prefetchnta",    { Mb }, 0 },
8203     { "nopQ",           { Ev }, 0 },
8204   },
8205   {
8206     /* MOD_0F18_REG_1 */
8207     { "prefetcht0",     { Mb }, 0 },
8208     { "nopQ",           { Ev }, 0 },
8209   },
8210   {
8211     /* MOD_0F18_REG_2 */
8212     { "prefetcht1",     { Mb }, 0 },
8213     { "nopQ",           { Ev }, 0 },
8214   },
8215   {
8216     /* MOD_0F18_REG_3 */
8217     { "prefetcht2",     { Mb }, 0 },
8218     { "nopQ",           { Ev }, 0 },
8219   },
8220   {
8221     /* MOD_0F18_REG_6 */
8222     { X86_64_TABLE (X86_64_0F18_REG_6_MOD_0) },
8223     { "nopQ",           { Ev }, 0 },
8224   },
8225   {
8226     /* MOD_0F18_REG_7 */
8227     { X86_64_TABLE (X86_64_0F18_REG_7_MOD_0) },
8228     { "nopQ",           { Ev }, 0 },
8229   },
8230   {
8231     /* MOD_0F1A_PREFIX_0 */
8232     { "bndldx",         { Gbnd, Mv_bnd }, 0 },
8233     { "nopQ",           { Ev }, 0 },
8234   },
8235   {
8236     /* MOD_0F1B_PREFIX_0 */
8237     { "bndstx",         { Mv_bnd, Gbnd }, 0 },
8238     { "nopQ",           { Ev }, 0 },
8239   },
8240   {
8241     /* MOD_0F1B_PREFIX_1 */
8242     { "bndmk",          { Gbnd, Mv_bnd }, 0 },
8243     { "nopQ",           { Ev }, PREFIX_IGNORED },
8244   },
8245   {
8246     /* MOD_0F1C_PREFIX_0 */
8247     { REG_TABLE (REG_0F1C_P_0_MOD_0) },
8248     { "nopQ",           { Ev }, 0 },
8249   },
8250   {
8251     /* MOD_0F1E_PREFIX_1 */
8252     { "nopQ",           { Ev }, PREFIX_IGNORED },
8253     { REG_TABLE (REG_0F1E_P_1_MOD_3) },
8254   },
8255   {
8256     /* MOD_0FAE_REG_0 */
8257     { "fxsave",         { FXSAVE }, 0 },
8258     { PREFIX_TABLE (PREFIX_0FAE_REG_0_MOD_3) },
8259   },
8260   {
8261     /* MOD_0FAE_REG_1 */
8262     { "fxrstor",        { FXSAVE }, 0 },
8263     { PREFIX_TABLE (PREFIX_0FAE_REG_1_MOD_3) },
8264   },
8265   {
8266     /* MOD_0FAE_REG_2 */
8267     { "ldmxcsr",        { Md }, 0 },
8268     { PREFIX_TABLE (PREFIX_0FAE_REG_2_MOD_3) },
8269   },
8270   {
8271     /* MOD_0FAE_REG_3 */
8272     { "stmxcsr",        { Md }, 0 },
8273     { PREFIX_TABLE (PREFIX_0FAE_REG_3_MOD_3) },
8274   },
8275   {
8276     /* MOD_0FAE_REG_4 */
8277     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_0) },
8278     { PREFIX_TABLE (PREFIX_0FAE_REG_4_MOD_3) },
8279   },
8280   {
8281     /* MOD_0FAE_REG_5 */
8282     { "xrstor",         { FXSAVE }, PREFIX_OPCODE | PREFIX_REX2_ILLEGAL },
8283     { PREFIX_TABLE (PREFIX_0FAE_REG_5_MOD_3) },
8284   },
8285   {
8286     /* MOD_0FAE_REG_6 */
8287     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_0) },
8288     { PREFIX_TABLE (PREFIX_0FAE_REG_6_MOD_3) },
8289   },
8290   {
8291     /* MOD_0FAE_REG_7 */
8292     { PREFIX_TABLE (PREFIX_0FAE_REG_7_MOD_0) },
8293     { RM_TABLE (RM_0FAE_REG_7_MOD_3) },
8294   },
8295   {
8296     /* MOD_0FC7_REG_6 */
8297     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_0) },
8298     { PREFIX_TABLE (PREFIX_0FC7_REG_6_MOD_3) }
8299   },
8300   {
8301     /* MOD_0FC7_REG_7 */
8302     { "vmptrst",        { Mq }, 0 },
8303     { PREFIX_TABLE (PREFIX_0FC7_REG_7_MOD_3) }
8304   },
8305   {
8306     /* MOD_0F38DC_PREFIX_1 */
8307     { "aesenc128kl",    { XM, M }, 0 },
8308     { "loadiwkey",      { XM, EXx }, 0 },
8309   },
8310   /* MOD_0F38F8 */
8311   {
8312     { PREFIX_TABLE (PREFIX_0F38F8_M_0) },
8313     { X86_64_TABLE (X86_64_0F38F8_M_1) },
8314   },
8315   {
8316     /* MOD_VEX_0F3849_X86_64_L_0_W_0 */
8317     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_0) },
8318     { PREFIX_TABLE (PREFIX_VEX_0F3849_X86_64_L_0_W_0_M_1) },
8319   },
8320
8321 #include "i386-dis-evex-mod.h"
8322 };
8323
8324 static const struct dis386 rm_table[][8] = {
8325   {
8326     /* RM_C6_REG_7 */
8327     { "xabort",         { Skip_MODRM, Ib }, 0 },
8328   },
8329   {
8330     /* RM_C7_REG_7 */
8331     { "xbeginT",        { Skip_MODRM, Jdqw }, 0 },
8332   },
8333   {
8334     /* RM_0F01_REG_0 */
8335     { "enclv",          { Skip_MODRM }, 0 },
8336     { "vmcall",         { Skip_MODRM }, 0 },
8337     { "vmlaunch",       { Skip_MODRM }, 0 },
8338     { "vmresume",       { Skip_MODRM }, 0 },
8339     { "vmxoff",         { Skip_MODRM }, 0 },
8340     { "pconfig",        { Skip_MODRM }, 0 },
8341     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_6) },
8342     { PREFIX_TABLE (PREFIX_0F01_REG_0_MOD_3_RM_7) },
8343   },
8344   {
8345     /* RM_0F01_REG_1 */
8346     { "monitor",        { { OP_Monitor, 0 } }, 0 },
8347     { "mwait",          { { OP_Mwait, 0 } }, 0 },
8348     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_2) },
8349     { "stac",           { Skip_MODRM }, 0 },
8350     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_4) },
8351     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_5) },
8352     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_6) },
8353     { PREFIX_TABLE (PREFIX_0F01_REG_1_RM_7) },
8354   },
8355   {
8356     /* RM_0F01_REG_2 */
8357     { "xgetbv",         { Skip_MODRM }, 0 },
8358     { "xsetbv",         { Skip_MODRM }, 0 },
8359     { Bad_Opcode },
8360     { Bad_Opcode },
8361     { "vmfunc",         { Skip_MODRM }, 0 },
8362     { "xend",           { Skip_MODRM }, 0 },
8363     { "xtest",          { Skip_MODRM }, 0 },
8364     { "enclu",          { Skip_MODRM }, 0 },
8365   },
8366   {
8367     /* RM_0F01_REG_3 */
8368     { "vmrun",          { Skip_MODRM }, 0 },
8369     { PREFIX_TABLE (PREFIX_0F01_REG_3_RM_1) },
8370     { "vmload",         { Skip_MODRM }, 0 },
8371     { "vmsave",         { Skip_MODRM }, 0 },
8372     { "stgi",           { Skip_MODRM }, 0 },
8373     { "clgi",           { Skip_MODRM }, 0 },
8374     { "skinit",         { Skip_MODRM }, 0 },
8375     { "invlpga",        { Skip_MODRM }, 0 },
8376   },
8377   {
8378     /* RM_0F01_REG_5_MOD_3 */
8379     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_0) },
8380     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_1) },
8381     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_2) },
8382     { Bad_Opcode },
8383     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_4) },
8384     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_5) },
8385     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_6) },
8386     { PREFIX_TABLE (PREFIX_0F01_REG_5_MOD_3_RM_7) },
8387   },
8388   {
8389     /* RM_0F01_REG_7_MOD_3 */
8390     { "swapgs",         { Skip_MODRM }, 0  },
8391     { "rdtscp",         { Skip_MODRM }, 0  },
8392     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_2) },
8393     { "mwaitx",         { { OP_Mwait, eBX_reg } }, PREFIX_OPCODE },
8394     { "clzero",         { Skip_MODRM }, 0  },
8395     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_5) },
8396     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_6) },
8397     { PREFIX_TABLE (PREFIX_0F01_REG_7_MOD_3_RM_7) },
8398   },
8399   {
8400     /* RM_0F1E_P_1_MOD_3_REG_7 */
8401     { "nopQ",           { Ev }, PREFIX_IGNORED },
8402     { "nopQ",           { Ev }, PREFIX_IGNORED },
8403     { "endbr64",        { Skip_MODRM }, 0 },
8404     { "endbr32",        { Skip_MODRM }, 0 },
8405     { "nopQ",           { Ev }, PREFIX_IGNORED },
8406     { "nopQ",           { Ev }, PREFIX_IGNORED },
8407     { "nopQ",           { Ev }, PREFIX_IGNORED },
8408     { "nopQ",           { Ev }, PREFIX_IGNORED },
8409   },
8410   {
8411     /* RM_0FAE_REG_6_MOD_3 */
8412     { "mfence",         { Skip_MODRM }, 0 },
8413   },
8414   {
8415     /* RM_0FAE_REG_7_MOD_3 */
8416     { "sfence",         { Skip_MODRM }, 0 },
8417   },
8418   {
8419     /* RM_0F3A0F_P_1_R_0 */
8420     { "hreset",         { Skip_MODRM, Ib }, 0 },
8421   },
8422   {
8423     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_0_R_0 */
8424     { "tilerelease",    { Skip_MODRM }, 0 },
8425   },
8426   {
8427     /* RM_VEX_0F3849_X86_64_L_0_W_0_M_1_P_3 */
8428     { "tilezero",       { TMM, Skip_MODRM }, 0 },
8429   },
8430 };
8431
8432 #define INTERNAL_DISASSEMBLER_ERROR _("<internal disassembler error>")
8433
8434 /* The values used here must be non-zero, fit in 'unsigned char', and not be
8435    in conflict with actual prefix opcodes.  */
8436 #define REP_PREFIX      0x01
8437 #define XACQUIRE_PREFIX 0x02
8438 #define XRELEASE_PREFIX 0x03
8439 #define BND_PREFIX      0x04
8440 #define NOTRACK_PREFIX  0x05
8441
8442 static enum {
8443   ckp_okay,
8444   ckp_bogus,
8445   ckp_fetch_error,
8446 }
8447 ckprefix (instr_info *ins)
8448 {
8449   int i, length;
8450   uint8_t newrex;
8451
8452   i = 0;
8453   length = 0;
8454   /* The maximum instruction length is 15bytes.  */
8455   while (length < MAX_CODE_LENGTH - 1)
8456     {
8457       if (!fetch_code (ins->info, ins->codep + 1))
8458         return ckp_fetch_error;
8459       newrex = 0;
8460       switch (*ins->codep)
8461         {
8462         /* REX prefixes family.  */
8463         case 0x40:
8464         case 0x41:
8465         case 0x42:
8466         case 0x43:
8467         case 0x44:
8468         case 0x45:
8469         case 0x46:
8470         case 0x47:
8471         case 0x48:
8472         case 0x49:
8473         case 0x4a:
8474         case 0x4b:
8475         case 0x4c:
8476         case 0x4d:
8477         case 0x4e:
8478         case 0x4f:
8479           if (ins->address_mode == mode_64bit)
8480             newrex = *ins->codep;
8481           else
8482             return ckp_okay;
8483           ins->last_rex_prefix = i;
8484           break;
8485         /* REX2 must be the last prefix. */
8486         case REX2_OPCODE:
8487           if (ins->address_mode == mode_64bit)
8488             {
8489               if (ins->last_rex_prefix >= 0)
8490                 return ckp_bogus;
8491
8492               ins->codep++;
8493               if (!fetch_code (ins->info, ins->codep + 1))
8494                 return ckp_fetch_error;
8495               ins->rex2_payload = *ins->codep;
8496               ins->rex2 = ins->rex2_payload >> 4;
8497               ins->rex = (ins->rex2_payload & 0xf) | REX_OPCODE;
8498               ins->codep++;
8499               ins->last_rex2_prefix = i;
8500               ins->all_prefixes[i] = REX2_OPCODE;
8501             }
8502           return ckp_okay;
8503         case 0xf3:
8504           ins->prefixes |= PREFIX_REPZ;
8505           ins->last_repz_prefix = i;
8506           break;
8507         case 0xf2:
8508           ins->prefixes |= PREFIX_REPNZ;
8509           ins->last_repnz_prefix = i;
8510           break;
8511         case 0xf0:
8512           ins->prefixes |= PREFIX_LOCK;
8513           ins->last_lock_prefix = i;
8514           break;
8515         case 0x2e:
8516           ins->prefixes |= PREFIX_CS;
8517           ins->last_seg_prefix = i;
8518           if (ins->address_mode != mode_64bit)
8519             ins->active_seg_prefix = PREFIX_CS;
8520           break;
8521         case 0x36:
8522           ins->prefixes |= PREFIX_SS;
8523           ins->last_seg_prefix = i;
8524           if (ins->address_mode != mode_64bit)
8525             ins->active_seg_prefix = PREFIX_SS;
8526           break;
8527         case 0x3e:
8528           ins->prefixes |= PREFIX_DS;
8529           ins->last_seg_prefix = i;
8530           if (ins->address_mode != mode_64bit)
8531             ins->active_seg_prefix = PREFIX_DS;
8532           break;
8533         case 0x26:
8534           ins->prefixes |= PREFIX_ES;
8535           ins->last_seg_prefix = i;
8536           if (ins->address_mode != mode_64bit)
8537             ins->active_seg_prefix = PREFIX_ES;
8538           break;
8539         case 0x64:
8540           ins->prefixes |= PREFIX_FS;
8541           ins->last_seg_prefix = i;
8542           ins->active_seg_prefix = PREFIX_FS;
8543           break;
8544         case 0x65:
8545           ins->prefixes |= PREFIX_GS;
8546           ins->last_seg_prefix = i;
8547           ins->active_seg_prefix = PREFIX_GS;
8548           break;
8549         case 0x66:
8550           ins->prefixes |= PREFIX_DATA;
8551           ins->last_data_prefix = i;
8552           break;
8553         case 0x67:
8554           ins->prefixes |= PREFIX_ADDR;
8555           ins->last_addr_prefix = i;
8556           break;
8557         case FWAIT_OPCODE:
8558           /* fwait is really an instruction.  If there are prefixes
8559              before the fwait, they belong to the fwait, *not* to the
8560              following instruction.  */
8561           ins->fwait_prefix = i;
8562           if (ins->prefixes || ins->rex)
8563             {
8564               ins->prefixes |= PREFIX_FWAIT;
8565               ins->codep++;
8566               /* This ensures that the previous REX prefixes are noticed
8567                  as unused prefixes, as in the return case below.  */
8568               return ins->rex ? ckp_bogus : ckp_okay;
8569             }
8570           ins->prefixes = PREFIX_FWAIT;
8571           break;
8572         default:
8573           return ckp_okay;
8574         }
8575       /* Rex is ignored when followed by another prefix.  */
8576       if (ins->rex)
8577         return ckp_bogus;
8578       if (*ins->codep != FWAIT_OPCODE)
8579         ins->all_prefixes[i++] = *ins->codep;
8580       ins->rex = newrex;
8581       ins->codep++;
8582       length++;
8583     }
8584   return ckp_bogus;
8585 }
8586
8587 /* Return the name of the prefix byte PREF, or NULL if PREF is not a
8588    prefix byte.  */
8589
8590 static const char *
8591 prefix_name (enum address_mode mode, uint8_t pref, int sizeflag)
8592 {
8593   static const char *rexes [16] =
8594     {
8595       "rex",            /* 0x40 */
8596       "rex.B",          /* 0x41 */
8597       "rex.X",          /* 0x42 */
8598       "rex.XB",         /* 0x43 */
8599       "rex.R",          /* 0x44 */
8600       "rex.RB",         /* 0x45 */
8601       "rex.RX",         /* 0x46 */
8602       "rex.RXB",        /* 0x47 */
8603       "rex.W",          /* 0x48 */
8604       "rex.WB",         /* 0x49 */
8605       "rex.WX",         /* 0x4a */
8606       "rex.WXB",        /* 0x4b */
8607       "rex.WR",         /* 0x4c */
8608       "rex.WRB",        /* 0x4d */
8609       "rex.WRX",        /* 0x4e */
8610       "rex.WRXB",       /* 0x4f */
8611     };
8612
8613   switch (pref)
8614     {
8615     /* REX prefixes family.  */
8616     case 0x40:
8617     case 0x41:
8618     case 0x42:
8619     case 0x43:
8620     case 0x44:
8621     case 0x45:
8622     case 0x46:
8623     case 0x47:
8624     case 0x48:
8625     case 0x49:
8626     case 0x4a:
8627     case 0x4b:
8628     case 0x4c:
8629     case 0x4d:
8630     case 0x4e:
8631     case 0x4f:
8632       return rexes [pref - 0x40];
8633     case 0xf3:
8634       return "repz";
8635     case 0xf2:
8636       return "repnz";
8637     case 0xf0:
8638       return "lock";
8639     case 0x2e:
8640       return "cs";
8641     case 0x36:
8642       return "ss";
8643     case 0x3e:
8644       return "ds";
8645     case 0x26:
8646       return "es";
8647     case 0x64:
8648       return "fs";
8649     case 0x65:
8650       return "gs";
8651     case 0x66:
8652       return (sizeflag & DFLAG) ? "data16" : "data32";
8653     case 0x67:
8654       if (mode == mode_64bit)
8655         return (sizeflag & AFLAG) ? "addr32" : "addr64";
8656       else
8657         return (sizeflag & AFLAG) ? "addr16" : "addr32";
8658     case FWAIT_OPCODE:
8659       return "fwait";
8660     case REP_PREFIX:
8661       return "rep";
8662     case XACQUIRE_PREFIX:
8663       return "xacquire";
8664     case XRELEASE_PREFIX:
8665       return "xrelease";
8666     case BND_PREFIX:
8667       return "bnd";
8668     case NOTRACK_PREFIX:
8669       return "notrack";
8670     case REX2_OPCODE:
8671       return "rex2";
8672     default:
8673       return NULL;
8674     }
8675 }
8676
8677 void
8678 print_i386_disassembler_options (FILE *stream)
8679 {
8680   fprintf (stream, _("\n\
8681 The following i386/x86-64 specific disassembler options are supported for use\n\
8682 with the -M switch (multiple options should be separated by commas):\n"));
8683
8684   fprintf (stream, _("  x86-64      Disassemble in 64bit mode\n"));
8685   fprintf (stream, _("  i386        Disassemble in 32bit mode\n"));
8686   fprintf (stream, _("  i8086       Disassemble in 16bit mode\n"));
8687   fprintf (stream, _("  att         Display instruction in AT&T syntax\n"));
8688   fprintf (stream, _("  intel       Display instruction in Intel syntax\n"));
8689   fprintf (stream, _("  att-mnemonic  (AT&T syntax only)\n"
8690                      "              Display instruction with AT&T mnemonic\n"));
8691   fprintf (stream, _("  intel-mnemonic  (AT&T syntax only)\n"
8692                      "              Display instruction with Intel mnemonic\n"));
8693   fprintf (stream, _("  addr64      Assume 64bit address size\n"));
8694   fprintf (stream, _("  addr32      Assume 32bit address size\n"));
8695   fprintf (stream, _("  addr16      Assume 16bit address size\n"));
8696   fprintf (stream, _("  data32      Assume 32bit data size\n"));
8697   fprintf (stream, _("  data16      Assume 16bit data size\n"));
8698   fprintf (stream, _("  suffix      Always display instruction suffix in AT&T syntax\n"));
8699   fprintf (stream, _("  amd64       Display instruction in AMD64 ISA\n"));
8700   fprintf (stream, _("  intel64     Display instruction in Intel64 ISA\n"));
8701 }
8702
8703 /* Bad opcode.  */
8704 static const struct dis386 bad_opcode = { "(bad)", { XX }, 0 };
8705
8706 /* Fetch error indicator.  */
8707 static const struct dis386 err_opcode = { NULL, { XX }, 0 };
8708
8709 static const struct dis386 map7_f8_opcode = { VEX_LEN_TABLE (VEX_LEN_MAP7_F8) };
8710
8711 /* Get a pointer to struct dis386 with a valid name.  */
8712
8713 static const struct dis386 *
8714 get_valid_dis386 (const struct dis386 *dp, instr_info *ins)
8715 {
8716   int vindex, vex_table_index;
8717
8718   if (dp->name != NULL)
8719     return dp;
8720
8721   switch (dp->op[0].bytemode)
8722     {
8723     case USE_REG_TABLE:
8724       dp = &reg_table[dp->op[1].bytemode][ins->modrm.reg];
8725       break;
8726
8727     case USE_MOD_TABLE:
8728       vindex = ins->modrm.mod == 0x3 ? 1 : 0;
8729       dp = &mod_table[dp->op[1].bytemode][vindex];
8730       break;
8731
8732     case USE_RM_TABLE:
8733       dp = &rm_table[dp->op[1].bytemode][ins->modrm.rm];
8734       break;
8735
8736     case USE_PREFIX_TABLE:
8737       if (ins->need_vex)
8738         {
8739           /* The prefix in VEX is implicit.  */
8740           switch (ins->vex.prefix)
8741             {
8742             case 0:
8743               vindex = 0;
8744               break;
8745             case REPE_PREFIX_OPCODE:
8746               vindex = 1;
8747               break;
8748             case DATA_PREFIX_OPCODE:
8749               vindex = 2;
8750               break;
8751             case REPNE_PREFIX_OPCODE:
8752               vindex = 3;
8753               break;
8754             default:
8755               abort ();
8756               break;
8757             }
8758         }
8759       else
8760         {
8761           int last_prefix = -1;
8762           int prefix = 0;
8763           vindex = 0;
8764           /* We check PREFIX_REPNZ and PREFIX_REPZ before PREFIX_DATA.
8765              When there are multiple PREFIX_REPNZ and PREFIX_REPZ, the
8766              last one wins.  */
8767           if ((ins->prefixes & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
8768             {
8769               if (ins->last_repz_prefix > ins->last_repnz_prefix)
8770                 {
8771                   vindex = 1;
8772                   prefix = PREFIX_REPZ;
8773                   last_prefix = ins->last_repz_prefix;
8774                 }
8775               else
8776                 {
8777                   vindex = 3;
8778                   prefix = PREFIX_REPNZ;
8779                   last_prefix = ins->last_repnz_prefix;
8780                 }
8781
8782               /* Check if prefix should be ignored.  */
8783               if ((((prefix_table[dp->op[1].bytemode][vindex].prefix_requirement
8784                      & PREFIX_IGNORED) >> PREFIX_IGNORED_SHIFT)
8785                    & prefix) != 0
8786                   && !prefix_table[dp->op[1].bytemode][vindex].name)
8787                 vindex = 0;
8788             }
8789
8790           if (vindex == 0 && (ins->prefixes & PREFIX_DATA) != 0)
8791             {
8792               vindex = 2;
8793               prefix = PREFIX_DATA;
8794               last_prefix = ins->last_data_prefix;
8795             }
8796
8797           if (vindex != 0)
8798             {
8799               ins->used_prefixes |= prefix;
8800               ins->all_prefixes[last_prefix] = 0;
8801             }
8802         }
8803       dp = &prefix_table[dp->op[1].bytemode][vindex];
8804       break;
8805
8806     case USE_X86_64_EVEX_FROM_VEX_TABLE:
8807       ins->evex_type = evex_from_vex;
8808       /* EVEX from VEX instrucions require that EVEX.z, EVEX.L’L, EVEX.b and
8809          the lower 2 bits of EVEX.aaa must be 0.  */
8810       if ((ins->vex.mask_register_specifier & 0x3) != 0
8811           || ins->vex.ll != 0
8812           || ins->vex.zeroing != 0
8813           || ins->vex.b)
8814         return &bad_opcode;
8815
8816       /* Fall through.  */
8817     case USE_X86_64_TABLE:
8818       vindex = ins->address_mode == mode_64bit ? 1 : 0;
8819       dp = &x86_64_table[dp->op[1].bytemode][vindex];
8820       break;
8821
8822     case USE_3BYTE_TABLE:
8823       if (!fetch_code (ins->info, ins->codep + 2))
8824         return &err_opcode;
8825       vindex = *ins->codep++;
8826       dp = &three_byte_table[dp->op[1].bytemode][vindex];
8827       ins->end_codep = ins->codep;
8828       if (!fetch_modrm (ins))
8829         return &err_opcode;
8830       break;
8831
8832     case USE_VEX_LEN_TABLE:
8833       if (!ins->need_vex)
8834         abort ();
8835
8836       switch (ins->vex.length)
8837         {
8838         case 128:
8839           vindex = 0;
8840           break;
8841         case 512:
8842           /* This allows re-using in particular table entries where only
8843              128-bit operand size (VEX.L=0 / EVEX.L'L=0) are valid.  */
8844           if (ins->vex.evex)
8845             {
8846         case 256:
8847               vindex = 1;
8848               break;
8849             }
8850         /* Fall through.  */
8851         default:
8852           abort ();
8853           break;
8854         }
8855
8856       dp = &vex_len_table[dp->op[1].bytemode][vindex];
8857       break;
8858
8859     case USE_EVEX_LEN_TABLE:
8860       if (!ins->vex.evex)
8861         abort ();
8862
8863       switch (ins->vex.length)
8864         {
8865         case 128:
8866           vindex = 0;
8867           break;
8868         case 256:
8869           vindex = 1;
8870           break;
8871         case 512:
8872           vindex = 2;
8873           break;
8874         default:
8875           abort ();
8876           break;
8877         }
8878
8879       dp = &evex_len_table[dp->op[1].bytemode][vindex];
8880       break;
8881
8882     case USE_XOP_8F_TABLE:
8883       if (!fetch_code (ins->info, ins->codep + 3))
8884         return &err_opcode;
8885       ins->rex = ~(*ins->codep >> 5) & 0x7;
8886
8887       /* VEX_TABLE_INDEX is the mmmmm part of the XOP byte 1 "RCB.mmmmm".  */
8888       switch ((*ins->codep & 0x1f))
8889         {
8890         default:
8891           dp = &bad_opcode;
8892           return dp;
8893         case 0x8:
8894           vex_table_index = XOP_08;
8895           break;
8896         case 0x9:
8897           vex_table_index = XOP_09;
8898           break;
8899         case 0xa:
8900           vex_table_index = XOP_0A;
8901           break;
8902         }
8903       ins->codep++;
8904       ins->vex.w = *ins->codep & 0x80;
8905       if (ins->vex.w && ins->address_mode == mode_64bit)
8906         ins->rex |= REX_W;
8907
8908       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8909       if (ins->address_mode != mode_64bit)
8910         {
8911           /* In 16/32-bit mode REX_B is silently ignored.  */
8912           ins->rex &= ~REX_B;
8913         }
8914
8915       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8916       switch ((*ins->codep & 0x3))
8917         {
8918         case 0:
8919           break;
8920         case 1:
8921           ins->vex.prefix = DATA_PREFIX_OPCODE;
8922           break;
8923         case 2:
8924           ins->vex.prefix = REPE_PREFIX_OPCODE;
8925           break;
8926         case 3:
8927           ins->vex.prefix = REPNE_PREFIX_OPCODE;
8928           break;
8929         }
8930       ins->need_vex = 3;
8931       ins->codep++;
8932       vindex = *ins->codep++;
8933       dp = &xop_table[vex_table_index][vindex];
8934
8935       ins->end_codep = ins->codep;
8936       if (!fetch_modrm (ins))
8937         return &err_opcode;
8938
8939       /* No XOP encoding so far allows for a non-zero embedded prefix. Avoid
8940          having to decode the bits for every otherwise valid encoding.  */
8941       if (ins->vex.prefix)
8942         return &bad_opcode;
8943       break;
8944
8945     case USE_VEX_C4_TABLE:
8946       /* VEX prefix.  */
8947       if (!fetch_code (ins->info, ins->codep + 3))
8948         return &err_opcode;
8949       ins->rex = ~(*ins->codep >> 5) & 0x7;
8950       switch ((*ins->codep & 0x1f))
8951         {
8952         default:
8953           dp = &bad_opcode;
8954           return dp;
8955         case 0x1:
8956           vex_table_index = VEX_0F;
8957           break;
8958         case 0x2:
8959           vex_table_index = VEX_0F38;
8960           break;
8961         case 0x3:
8962           vex_table_index = VEX_0F3A;
8963           break;
8964         case 0x7:
8965           vex_table_index = VEX_MAP7;
8966           break;
8967         }
8968       ins->codep++;
8969       ins->vex.w = *ins->codep & 0x80;
8970       if (ins->address_mode == mode_64bit)
8971         {
8972           if (ins->vex.w)
8973             ins->rex |= REX_W;
8974         }
8975       else
8976         {
8977           /* For the 3-byte VEX prefix in 32-bit mode, the REX_B bit
8978              is ignored, other REX bits are 0 and the highest bit in
8979              VEX.vvvv is also ignored (but we mustn't clear it here).  */
8980           ins->rex = 0;
8981         }
8982       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
8983       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
8984       switch ((*ins->codep & 0x3))
8985         {
8986         case 0:
8987           break;
8988         case 1:
8989           ins->vex.prefix = DATA_PREFIX_OPCODE;
8990           break;
8991         case 2:
8992           ins->vex.prefix = REPE_PREFIX_OPCODE;
8993           break;
8994         case 3:
8995           ins->vex.prefix = REPNE_PREFIX_OPCODE;
8996           break;
8997         }
8998       ins->need_vex = 3;
8999       ins->codep++;
9000       vindex = *ins->codep++;
9001       if (vex_table_index != VEX_MAP7)
9002         dp = &vex_table[vex_table_index][vindex];
9003       else if (vindex == 0xf8)
9004         dp = &map7_f8_opcode;
9005       else
9006         dp = &bad_opcode;
9007       ins->end_codep = ins->codep;
9008       /* There is no MODRM byte for VEX0F 77.  */
9009       if ((vex_table_index != VEX_0F || vindex != 0x77)
9010           && !fetch_modrm (ins))
9011         return &err_opcode;
9012       break;
9013
9014     case USE_VEX_C5_TABLE:
9015       /* VEX prefix.  */
9016       if (!fetch_code (ins->info, ins->codep + 2))
9017         return &err_opcode;
9018       ins->rex = (*ins->codep & 0x80) ? 0 : REX_R;
9019
9020       /* For the 2-byte VEX prefix in 32-bit mode, the highest bit in
9021          VEX.vvvv is 1.  */
9022       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9023       ins->vex.length = (*ins->codep & 0x4) ? 256 : 128;
9024       switch ((*ins->codep & 0x3))
9025         {
9026         case 0:
9027           break;
9028         case 1:
9029           ins->vex.prefix = DATA_PREFIX_OPCODE;
9030           break;
9031         case 2:
9032           ins->vex.prefix = REPE_PREFIX_OPCODE;
9033           break;
9034         case 3:
9035           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9036           break;
9037         }
9038       ins->need_vex = 2;
9039       ins->codep++;
9040       vindex = *ins->codep++;
9041       dp = &vex_table[VEX_0F][vindex];
9042       ins->end_codep = ins->codep;
9043       /* There is no MODRM byte for VEX 77.  */
9044       if (vindex != 0x77 && !fetch_modrm (ins))
9045         return &err_opcode;
9046       break;
9047
9048     case USE_VEX_W_TABLE:
9049       if (!ins->need_vex)
9050         abort ();
9051
9052       dp = &vex_w_table[dp->op[1].bytemode][ins->vex.w];
9053       break;
9054
9055     case USE_EVEX_TABLE:
9056       ins->two_source_ops = false;
9057       /* EVEX prefix.  */
9058       ins->vex.evex = true;
9059       if (!fetch_code (ins->info, ins->codep + 4))
9060         return &err_opcode;
9061       /* The first byte after 0x62.  */
9062       if (*ins->codep & 0x8)
9063         ins->rex2 |= REX_B;
9064       if (!(*ins->codep & 0x10))
9065         ins->rex2 |= REX_R;
9066
9067       ins->rex = ~(*ins->codep >> 5) & 0x7;
9068       switch (*ins->codep & 0x7)
9069         {
9070         default:
9071           return &bad_opcode;
9072         case 0x1:
9073           vex_table_index = EVEX_0F;
9074           break;
9075         case 0x2:
9076           vex_table_index = EVEX_0F38;
9077           break;
9078         case 0x3:
9079           vex_table_index = EVEX_0F3A;
9080           break;
9081         case 0x4:
9082           vex_table_index = EVEX_MAP4;
9083           ins->evex_type = evex_from_legacy;
9084           if (ins->address_mode != mode_64bit)
9085             return &bad_opcode;
9086           break;
9087         case 0x5:
9088           vex_table_index = EVEX_MAP5;
9089           break;
9090         case 0x6:
9091           vex_table_index = EVEX_MAP6;
9092           break;
9093         }
9094
9095       /* The second byte after 0x62.  */
9096       ins->codep++;
9097       ins->vex.w = *ins->codep & 0x80;
9098       if (ins->vex.w && ins->address_mode == mode_64bit)
9099         ins->rex |= REX_W;
9100
9101       ins->vex.register_specifier = (~(*ins->codep >> 3)) & 0xf;
9102
9103       if (!(*ins->codep & 0x4))
9104         ins->rex2 |= REX_X;
9105
9106       switch ((*ins->codep & 0x3))
9107         {
9108         case 0:
9109           break;
9110         case 1:
9111           ins->vex.prefix = DATA_PREFIX_OPCODE;
9112           break;
9113         case 2:
9114           ins->vex.prefix = REPE_PREFIX_OPCODE;
9115           break;
9116         case 3:
9117           ins->vex.prefix = REPNE_PREFIX_OPCODE;
9118           break;
9119         }
9120
9121       /* The third byte after 0x62.  */
9122       ins->codep++;
9123
9124       /* Remember the static rounding bits.  */
9125       ins->vex.ll = (*ins->codep >> 5) & 3;
9126       ins->vex.b = *ins->codep & 0x10;
9127
9128       ins->vex.v = *ins->codep & 0x8;
9129       ins->vex.mask_register_specifier = *ins->codep & 0x7;
9130       ins->vex.zeroing = *ins->codep & 0x80;
9131
9132       if (ins->address_mode != mode_64bit)
9133         {
9134           /* Report bad for !evex_default and when two fixed values of evex
9135              change..  */
9136           if (ins->evex_type != evex_default
9137               || (ins->rex2 & (REX_B | REX_X)))
9138             return &bad_opcode;
9139           /* In 16/32-bit mode silently ignore following bits.  */
9140           ins->rex &= ~REX_B;
9141           ins->rex2 &= ~REX_R;
9142         }
9143
9144       /* EVEX from legacy instructions, when the EVEX.ND bit is 0,
9145          all bits of EVEX.vvvv and EVEX.V' must be 1.  */
9146       if (ins->evex_type == evex_from_legacy && !ins->vex.nd
9147           && (ins->vex.register_specifier || !ins->vex.v))
9148         return &bad_opcode;
9149
9150       ins->need_vex = 4;
9151
9152       /* EVEX from legacy instructions require that EVEX.z, EVEX.L’L and the
9153          lower 2 bits of EVEX.aaa must be 0.  */
9154       if (ins->evex_type == evex_from_legacy
9155           && ((ins->vex.mask_register_specifier & 0x3) != 0
9156               || ins->vex.ll != 0
9157               || ins->vex.zeroing != 0))
9158         return &bad_opcode;
9159
9160       ins->codep++;
9161       vindex = *ins->codep++;
9162       dp = &evex_table[vex_table_index][vindex];
9163       ins->end_codep = ins->codep;
9164       if (!fetch_modrm (ins))
9165         return &err_opcode;
9166
9167       /* Set vector length. For EVEX-promoted instructions, evex.ll == 0b00,
9168          which has the same encoding as vex.length == 128 and they can share
9169          the same processing with vex.length in OP_VEX.  */
9170       if (ins->modrm.mod == 3 && ins->vex.b && ins->evex_type != evex_from_legacy)
9171         ins->vex.length = 512;
9172       else
9173         {
9174           switch (ins->vex.ll)
9175             {
9176             case 0x0:
9177               ins->vex.length = 128;
9178               break;
9179             case 0x1:
9180               ins->vex.length = 256;
9181               break;
9182             case 0x2:
9183               ins->vex.length = 512;
9184               break;
9185             default:
9186               return &bad_opcode;
9187             }
9188         }
9189       break;
9190
9191     case 0:
9192       dp = &bad_opcode;
9193       break;
9194
9195     default:
9196       abort ();
9197     }
9198
9199   if (dp->name != NULL)
9200     return dp;
9201   else
9202     return get_valid_dis386 (dp, ins);
9203 }
9204
9205 static bool
9206 get_sib (instr_info *ins, int sizeflag)
9207 {
9208   /* If modrm.mod == 3, operand must be register.  */
9209   if (ins->need_modrm
9210       && ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
9211       && ins->modrm.mod != 3
9212       && ins->modrm.rm == 4)
9213     {
9214       if (!fetch_code (ins->info, ins->codep + 2))
9215         return false;
9216       ins->sib.index = (ins->codep[1] >> 3) & 7;
9217       ins->sib.scale = (ins->codep[1] >> 6) & 3;
9218       ins->sib.base = ins->codep[1] & 7;
9219       ins->has_sib = true;
9220     }
9221   else
9222     ins->has_sib = false;
9223
9224   return true;
9225 }
9226
9227 /* Like oappend_with_style (below) but always with text style.  */
9228
9229 static void
9230 oappend (instr_info *ins, const char *s)
9231 {
9232   oappend_with_style (ins, s, dis_style_text);
9233 }
9234
9235 /* Like oappend (above), but S is a string starting with '%'.  In
9236    Intel syntax, the '%' is elided.  */
9237
9238 static void
9239 oappend_register (instr_info *ins, const char *s)
9240 {
9241   oappend_with_style (ins, s + ins->intel_syntax, dis_style_register);
9242 }
9243
9244 /* Wrap around a call to INS->info->fprintf_styled_func, printing FMT.
9245    STYLE is the default style to use in the fprintf_styled_func calls,
9246    however, FMT might include embedded style markers (see oappend_style),
9247    these embedded markers are not printed, but instead change the style
9248    used in the next fprintf_styled_func call.  */
9249
9250 static void ATTRIBUTE_PRINTF_3
9251 i386_dis_printf (const disassemble_info *info, enum disassembler_style style,
9252                  const char *fmt, ...)
9253 {
9254   va_list ap;
9255   enum disassembler_style curr_style = style;
9256   const char *start, *curr;
9257   char staging_area[40];
9258
9259   va_start (ap, fmt);
9260   /* In particular print_insn()'s processing of op_txt[] can hand rather long
9261      strings here.  Bypass vsnprintf() in such cases to avoid capacity issues
9262      with the staging area.  */
9263   if (strcmp (fmt, "%s"))
9264     {
9265       int res = vsnprintf (staging_area, sizeof (staging_area), fmt, ap);
9266
9267       va_end (ap);
9268
9269       if (res < 0)
9270         return;
9271
9272       if ((size_t) res >= sizeof (staging_area))
9273         abort ();
9274
9275       start = curr = staging_area;
9276     }
9277   else
9278     {
9279       start = curr = va_arg (ap, const char *);
9280       va_end (ap);
9281     }
9282
9283   do
9284     {
9285       if (*curr == '\0'
9286           || (*curr == STYLE_MARKER_CHAR
9287               && ISXDIGIT (*(curr + 1))
9288               && *(curr + 2) == STYLE_MARKER_CHAR))
9289         {
9290           /* Output content between our START position and CURR.  */
9291           int len = curr - start;
9292           int n = (*info->fprintf_styled_func) (info->stream, curr_style,
9293                                                 "%.*s", len, start);
9294           if (n < 0)
9295             break;
9296
9297           if (*curr == '\0')
9298             break;
9299
9300           /* Skip over the initial STYLE_MARKER_CHAR.  */
9301           ++curr;
9302
9303           /* Update the CURR_STYLE.  As there are less than 16 styles, it
9304              is possible, that if the input is corrupted in some way, that
9305              we might set CURR_STYLE to an invalid value.  Don't worry
9306              though, we check for this situation.  */
9307           if (*curr >= '0' && *curr <= '9')
9308             curr_style = (enum disassembler_style) (*curr - '0');
9309           else if (*curr >= 'a' && *curr <= 'f')
9310             curr_style = (enum disassembler_style) (*curr - 'a' + 10);
9311           else
9312             curr_style = dis_style_text;
9313
9314           /* Check for an invalid style having been selected.  This should
9315              never happen, but it doesn't hurt to be a little paranoid.  */
9316           if (curr_style > dis_style_comment_start)
9317             curr_style = dis_style_text;
9318
9319           /* Skip the hex character, and the closing STYLE_MARKER_CHAR.  */
9320           curr += 2;
9321
9322           /* Reset the START to after the style marker.  */
9323           start = curr;
9324         }
9325       else
9326         ++curr;
9327     }
9328   while (true);
9329 }
9330
9331 static int
9332 print_insn (bfd_vma pc, disassemble_info *info, int intel_syntax)
9333 {
9334   const struct dis386 *dp;
9335   int i;
9336   int ret;
9337   char *op_txt[MAX_OPERANDS];
9338   int needcomma;
9339   bool intel_swap_2_3;
9340   int sizeflag, orig_sizeflag;
9341   const char *p;
9342   struct dis_private priv;
9343   int prefix_length;
9344   int op_count;
9345   instr_info ins = {
9346     .info = info,
9347     .intel_syntax = intel_syntax >= 0
9348                     ? intel_syntax
9349                     : (info->mach & bfd_mach_i386_intel_syntax) != 0,
9350     .intel_mnemonic = !SYSV386_COMPAT,
9351     .op_index[0 ... MAX_OPERANDS - 1] = -1,
9352     .start_pc = pc,
9353     .start_codep = priv.the_buffer,
9354     .codep = priv.the_buffer,
9355     .obufp = ins.obuf,
9356     .last_lock_prefix = -1,
9357     .last_repz_prefix = -1,
9358     .last_repnz_prefix = -1,
9359     .last_data_prefix = -1,
9360     .last_addr_prefix = -1,
9361     .last_rex_prefix = -1,
9362     .last_rex2_prefix = -1,
9363     .last_seg_prefix = -1,
9364     .fwait_prefix = -1,
9365   };
9366   char op_out[MAX_OPERANDS][MAX_OPERAND_BUFFER_SIZE];
9367
9368   priv.orig_sizeflag = AFLAG | DFLAG;
9369   if ((info->mach & bfd_mach_i386_i386) != 0)
9370     ins.address_mode = mode_32bit;
9371   else if (info->mach == bfd_mach_i386_i8086)
9372     {
9373       ins.address_mode = mode_16bit;
9374       priv.orig_sizeflag = 0;
9375     }
9376   else
9377     ins.address_mode = mode_64bit;
9378
9379   for (p = info->disassembler_options; p != NULL;)
9380     {
9381       if (startswith (p, "amd64"))
9382         ins.isa64 = amd64;
9383       else if (startswith (p, "intel64"))
9384         ins.isa64 = intel64;
9385       else if (startswith (p, "x86-64"))
9386         {
9387           ins.address_mode = mode_64bit;
9388           priv.orig_sizeflag |= AFLAG | DFLAG;
9389         }
9390       else if (startswith (p, "i386"))
9391         {
9392           ins.address_mode = mode_32bit;
9393           priv.orig_sizeflag |= AFLAG | DFLAG;
9394         }
9395       else if (startswith (p, "i8086"))
9396         {
9397           ins.address_mode = mode_16bit;
9398           priv.orig_sizeflag &= ~(AFLAG | DFLAG);
9399         }
9400       else if (startswith (p, "intel"))
9401         {
9402           if (startswith (p + 5, "-mnemonic"))
9403             ins.intel_mnemonic = true;
9404           else
9405             ins.intel_syntax = 1;
9406         }
9407       else if (startswith (p, "att"))
9408         {
9409           ins.intel_syntax = 0;
9410           if (startswith (p + 3, "-mnemonic"))
9411             ins.intel_mnemonic = false;
9412         }
9413       else if (startswith (p, "addr"))
9414         {
9415           if (ins.address_mode == mode_64bit)
9416             {
9417               if (p[4] == '3' && p[5] == '2')
9418                 priv.orig_sizeflag &= ~AFLAG;
9419               else if (p[4] == '6' && p[5] == '4')
9420                 priv.orig_sizeflag |= AFLAG;
9421             }
9422           else
9423             {
9424               if (p[4] == '1' && p[5] == '6')
9425                 priv.orig_sizeflag &= ~AFLAG;
9426               else if (p[4] == '3' && p[5] == '2')
9427                 priv.orig_sizeflag |= AFLAG;
9428             }
9429         }
9430       else if (startswith (p, "data"))
9431         {
9432           if (p[4] == '1' && p[5] == '6')
9433             priv.orig_sizeflag &= ~DFLAG;
9434           else if (p[4] == '3' && p[5] == '2')
9435             priv.orig_sizeflag |= DFLAG;
9436         }
9437       else if (startswith (p, "suffix"))
9438         priv.orig_sizeflag |= SUFFIX_ALWAYS;
9439
9440       p = strchr (p, ',');
9441       if (p != NULL)
9442         p++;
9443     }
9444
9445   if (ins.address_mode == mode_64bit && sizeof (bfd_vma) < 8)
9446     {
9447       i386_dis_printf (info, dis_style_text, _("64-bit address is disabled"));
9448       return -1;
9449     }
9450
9451   if (ins.intel_syntax)
9452     {
9453       ins.open_char = '[';
9454       ins.close_char = ']';
9455       ins.separator_char = '+';
9456       ins.scale_char = '*';
9457     }
9458   else
9459     {
9460       ins.open_char = '(';
9461       ins.close_char =  ')';
9462       ins.separator_char = ',';
9463       ins.scale_char = ',';
9464     }
9465
9466   /* The output looks better if we put 7 bytes on a line, since that
9467      puts most long word instructions on a single line.  */
9468   info->bytes_per_line = 7;
9469
9470   info->private_data = &priv;
9471   priv.fetched = 0;
9472   priv.insn_start = pc;
9473
9474   for (i = 0; i < MAX_OPERANDS; ++i)
9475     {
9476       op_out[i][0] = 0;
9477       ins.op_out[i] = op_out[i];
9478     }
9479
9480   sizeflag = priv.orig_sizeflag;
9481
9482   switch (ckprefix (&ins))
9483     {
9484     case ckp_okay:
9485       break;
9486
9487     case ckp_bogus:
9488       /* Too many prefixes or unused REX prefixes.  */
9489       for (i = 0;
9490            i < (int) ARRAY_SIZE (ins.all_prefixes) && ins.all_prefixes[i];
9491            i++)
9492         i386_dis_printf (info, dis_style_mnemonic, "%s%s",
9493                          (i == 0 ? "" : " "),
9494                          prefix_name (ins.address_mode, ins.all_prefixes[i],
9495                                       sizeflag));
9496       ret = i;
9497       goto out;
9498
9499     case ckp_fetch_error:
9500       goto fetch_error_out;
9501     }
9502
9503   ins.nr_prefixes = ins.codep - ins.start_codep;
9504
9505   if (!fetch_code (info, ins.codep + 1))
9506     {
9507     fetch_error_out:
9508       ret = fetch_error (&ins);
9509       goto out;
9510     }
9511
9512   ins.two_source_ops = (*ins.codep == 0x62 || *ins.codep == 0xc8);
9513
9514   if ((ins.prefixes & PREFIX_FWAIT)
9515       && (*ins.codep < 0xd8 || *ins.codep > 0xdf))
9516     {
9517       /* Handle ins.prefixes before fwait.  */
9518       for (i = 0; i < ins.fwait_prefix && ins.all_prefixes[i];
9519            i++)
9520         i386_dis_printf (info, dis_style_mnemonic, "%s ",
9521                          prefix_name (ins.address_mode, ins.all_prefixes[i],
9522                                       sizeflag));
9523       i386_dis_printf (info, dis_style_mnemonic, "fwait");
9524       ret = i + 1;
9525       goto out;
9526     }
9527
9528   /* REX2.M in rex2 prefix represents map0 or map1.  */
9529   if (ins.last_rex2_prefix < 0 ? *ins.codep == 0x0f : (ins.rex2 & REX2_M))
9530     {
9531       unsigned char threebyte;
9532
9533       if (!ins.rex2)
9534         {
9535           ins.codep++;
9536           if (!fetch_code (info, ins.codep + 1))
9537             goto fetch_error_out;
9538         }
9539
9540       threebyte = *ins.codep;
9541       dp = &dis386_twobyte[threebyte];
9542       ins.need_modrm = twobyte_has_modrm[threebyte];
9543       ins.codep++;
9544     }
9545   else
9546     {
9547       dp = &dis386[*ins.codep];
9548       ins.need_modrm = onebyte_has_modrm[*ins.codep];
9549       ins.codep++;
9550     }
9551
9552   /* Save sizeflag for printing the extra ins.prefixes later before updating
9553      it for mnemonic and operand processing.  The prefix names depend
9554      only on the address mode.  */
9555   orig_sizeflag = sizeflag;
9556   if (ins.prefixes & PREFIX_ADDR)
9557     sizeflag ^= AFLAG;
9558   if ((ins.prefixes & PREFIX_DATA))
9559     sizeflag ^= DFLAG;
9560
9561   ins.end_codep = ins.codep;
9562   if (ins.need_modrm && !fetch_modrm (&ins))
9563     goto fetch_error_out;
9564
9565   if (dp->name == NULL && dp->op[0].bytemode == FLOATCODE)
9566     {
9567       if (!get_sib (&ins, sizeflag)
9568           || !dofloat (&ins, sizeflag))
9569         goto fetch_error_out;
9570     }
9571   else
9572     {
9573       dp = get_valid_dis386 (dp, &ins);
9574       if (dp == &err_opcode)
9575         goto fetch_error_out;
9576
9577       /* For APX instructions promoted from legacy maps 0/1, embedded prefix
9578          is interpreted as the operand size override.  */
9579       if (ins.evex_type == evex_from_legacy
9580           && ins.vex.prefix == DATA_PREFIX_OPCODE)
9581         sizeflag ^= DFLAG;
9582
9583       if (dp != NULL && putop (&ins, dp->name, sizeflag) == 0)
9584         {
9585           if (!get_sib (&ins, sizeflag))
9586             goto fetch_error_out;
9587           for (i = 0; i < MAX_OPERANDS; ++i)
9588             {
9589               ins.obufp = ins.op_out[i];
9590               ins.op_ad = MAX_OPERANDS - 1 - i;
9591               if (dp->op[i].rtn
9592                   && !dp->op[i].rtn (&ins, dp->op[i].bytemode, sizeflag))
9593                 goto fetch_error_out;
9594               /* For EVEX instruction after the last operand masking
9595                  should be printed.  */
9596               if (i == 0 && ins.vex.evex)
9597                 {
9598                   /* Don't print {%k0}.  */
9599                   if (ins.vex.mask_register_specifier)
9600                     {
9601                       const char *reg_name
9602                         = att_names_mask[ins.vex.mask_register_specifier];
9603
9604                       oappend (&ins, "{");
9605                       oappend_register (&ins, reg_name);
9606                       oappend (&ins, "}");
9607
9608                       if (ins.vex.zeroing)
9609                         oappend (&ins, "{z}");
9610                     }
9611                   else if (ins.vex.zeroing)
9612                     {
9613                       oappend (&ins, "{bad}");
9614                       continue;
9615                     }
9616
9617                   /* Instructions with a mask register destination allow for
9618                      zeroing-masking only (if any masking at all), which is
9619                      _not_ expressed by EVEX.z.  */
9620                   if (ins.vex.zeroing && dp->op[0].bytemode == mask_mode)
9621                     ins.illegal_masking = true;
9622
9623                   /* S/G insns require a mask and don't allow
9624                      zeroing-masking.  */
9625                   if ((dp->op[0].bytemode == vex_vsib_d_w_dq_mode
9626                        || dp->op[0].bytemode == vex_vsib_q_w_dq_mode)
9627                       && (ins.vex.mask_register_specifier == 0
9628                           || ins.vex.zeroing))
9629                     ins.illegal_masking = true;
9630
9631                   if (ins.illegal_masking)
9632                     oappend (&ins, "/(bad)");
9633                 }
9634             }
9635
9636           /* Check whether rounding control was enabled for an insn not
9637              supporting it, when evex.b is not treated as evex.nd.  */
9638           if (ins.modrm.mod == 3 && ins.vex.b && ins.evex_type == evex_default
9639               && !(ins.evex_used & EVEX_b_used))
9640             {
9641               for (i = 0; i < MAX_OPERANDS; ++i)
9642                 {
9643                   ins.obufp = ins.op_out[i];
9644                   if (*ins.obufp)
9645                     continue;
9646                   oappend (&ins, names_rounding[ins.vex.ll]);
9647                   oappend (&ins, "bad}");
9648                   break;
9649                 }
9650             }
9651         }
9652     }
9653
9654   /* Clear instruction information.  */
9655   info->insn_info_valid = 0;
9656   info->branch_delay_insns = 0;
9657   info->data_size = 0;
9658   info->insn_type = dis_noninsn;
9659   info->target = 0;
9660   info->target2 = 0;
9661
9662   /* Reset jump operation indicator.  */
9663   ins.op_is_jump = false;
9664   {
9665     int jump_detection = 0;
9666
9667     /* Extract flags.  */
9668     for (i = 0; i < MAX_OPERANDS; ++i)
9669       {
9670         if ((dp->op[i].rtn == OP_J)
9671             || (dp->op[i].rtn == OP_indirE))
9672           jump_detection |= 1;
9673         else if ((dp->op[i].rtn == BND_Fixup)
9674                  || (!dp->op[i].rtn && !dp->op[i].bytemode))
9675           jump_detection |= 2;
9676         else if ((dp->op[i].bytemode == cond_jump_mode)
9677                  || (dp->op[i].bytemode == loop_jcxz_mode))
9678           jump_detection |= 4;
9679       }
9680
9681     /* Determine if this is a jump or branch.  */
9682     if ((jump_detection & 0x3) == 0x3)
9683       {
9684         ins.op_is_jump = true;
9685         if (jump_detection & 0x4)
9686           info->insn_type = dis_condbranch;
9687         else
9688           info->insn_type = (dp->name && !strncmp (dp->name, "call", 4))
9689             ? dis_jsr : dis_branch;
9690       }
9691   }
9692
9693   /* If VEX.vvvv and EVEX.vvvv are unused, they must be all 1s, which
9694      are all 0s in inverted form.  */
9695   if (ins.need_vex && ins.vex.register_specifier != 0)
9696     {
9697       i386_dis_printf (info, dis_style_text, "(bad)");
9698       ret = ins.end_codep - priv.the_buffer;
9699       goto out;
9700     }
9701
9702   if ((dp->prefix_requirement & PREFIX_REX2_ILLEGAL)
9703       && ins.last_rex2_prefix >= 0 && (ins.rex2 & REX2_SPECIAL) == 0)
9704     {
9705       i386_dis_printf (info, dis_style_text, "(bad)");
9706       ret = ins.end_codep - priv.the_buffer;
9707       goto out;
9708     }
9709
9710   switch (dp->prefix_requirement & ~PREFIX_REX2_ILLEGAL)
9711     {
9712     case PREFIX_DATA:
9713       /* If only the data prefix is marked as mandatory, its absence renders
9714          the encoding invalid.  Most other PREFIX_OPCODE rules still apply.  */
9715       if (ins.need_vex ? !ins.vex.prefix : !(ins.prefixes & PREFIX_DATA))
9716         {
9717           i386_dis_printf (info, dis_style_text, "(bad)");
9718           ret = ins.end_codep - priv.the_buffer;
9719           goto out;
9720         }
9721       ins.used_prefixes |= PREFIX_DATA;
9722       /* Fall through.  */
9723     case PREFIX_OPCODE:
9724       /* If the mandatory PREFIX_REPZ/PREFIX_REPNZ/PREFIX_DATA prefix is
9725          unused, opcode is invalid.  Since the PREFIX_DATA prefix may be
9726          used by putop and MMX/SSE operand and may be overridden by the
9727          PREFIX_REPZ/PREFIX_REPNZ fix, we check the PREFIX_DATA prefix
9728          separately.  */
9729       if (((ins.need_vex
9730             ? ins.vex.prefix == REPE_PREFIX_OPCODE
9731               || ins.vex.prefix == REPNE_PREFIX_OPCODE
9732             : (ins.prefixes
9733                & (PREFIX_REPZ | PREFIX_REPNZ)) != 0)
9734            && (ins.used_prefixes
9735                & (PREFIX_REPZ | PREFIX_REPNZ)) == 0)
9736           || (((ins.need_vex
9737                 ? ins.vex.prefix == DATA_PREFIX_OPCODE
9738                 : ((ins.prefixes
9739                     & (PREFIX_REPZ | PREFIX_REPNZ | PREFIX_DATA))
9740                    == PREFIX_DATA))
9741                && (ins.used_prefixes & PREFIX_DATA) == 0))
9742           || (ins.vex.evex && dp->prefix_requirement != PREFIX_DATA
9743               && !ins.vex.w != !(ins.used_prefixes & PREFIX_DATA)))
9744         {
9745           i386_dis_printf (info, dis_style_text, "(bad)");
9746           ret = ins.end_codep - priv.the_buffer;
9747           goto out;
9748         }
9749       break;
9750
9751     case PREFIX_IGNORED:
9752       /* Zap data size and rep prefixes from used_prefixes and reinstate their
9753          origins in all_prefixes.  */
9754       ins.used_prefixes &= ~PREFIX_OPCODE;
9755       if (ins.last_data_prefix >= 0)
9756         ins.all_prefixes[ins.last_data_prefix] = 0x66;
9757       if (ins.last_repz_prefix >= 0)
9758         ins.all_prefixes[ins.last_repz_prefix] = 0xf3;
9759       if (ins.last_repnz_prefix >= 0)
9760         ins.all_prefixes[ins.last_repnz_prefix] = 0xf2;
9761       break;
9762
9763     case PREFIX_NP_OR_DATA:
9764       if (ins.vex.prefix == REPE_PREFIX_OPCODE
9765           || ins.vex.prefix == REPNE_PREFIX_OPCODE)
9766         {
9767           i386_dis_printf (info, dis_style_text, "(bad)");
9768           ret = ins.end_codep - priv.the_buffer;
9769           goto out;
9770         }
9771       break;
9772
9773     case NO_PREFIX:
9774       if (ins.vex.prefix)
9775         {
9776           i386_dis_printf (info, dis_style_text, "(bad)");
9777           ret = ins.end_codep - priv.the_buffer;
9778           goto out;
9779         }
9780       break;
9781     }
9782
9783   /* Check if the REX prefix is used.  */
9784   if ((ins.rex ^ ins.rex_used) == 0
9785       && !ins.need_vex && ins.last_rex_prefix >= 0)
9786     ins.all_prefixes[ins.last_rex_prefix] = 0;
9787
9788   /* Check if the REX2 prefix is used.  */
9789   if (ins.last_rex2_prefix >= 0
9790       && ((ins.rex2 & REX2_SPECIAL)
9791           || (((ins.rex2 & 7) ^ (ins.rex2_used & 7)) == 0
9792               && (ins.rex ^ ins.rex_used) == 0
9793               && (ins.rex2 & 7))))
9794     ins.all_prefixes[ins.last_rex2_prefix] = 0;
9795
9796   /* Check if the SEG prefix is used.  */
9797   if ((ins.prefixes & (PREFIX_CS | PREFIX_SS | PREFIX_DS | PREFIX_ES
9798                        | PREFIX_FS | PREFIX_GS)) != 0
9799       && (ins.used_prefixes & ins.active_seg_prefix) != 0)
9800     ins.all_prefixes[ins.last_seg_prefix] = 0;
9801
9802   /* Check if the ADDR prefix is used.  */
9803   if ((ins.prefixes & PREFIX_ADDR) != 0
9804       && (ins.used_prefixes & PREFIX_ADDR) != 0)
9805     ins.all_prefixes[ins.last_addr_prefix] = 0;
9806
9807   /* Check if the DATA prefix is used.  */
9808   if ((ins.prefixes & PREFIX_DATA) != 0
9809       && (ins.used_prefixes & PREFIX_DATA) != 0
9810       && !ins.need_vex)
9811     ins.all_prefixes[ins.last_data_prefix] = 0;
9812
9813   /* Print the extra ins.prefixes.  */
9814   prefix_length = 0;
9815   for (i = 0; i < (int) ARRAY_SIZE (ins.all_prefixes); i++)
9816     if (ins.all_prefixes[i])
9817       {
9818         const char *name = prefix_name (ins.address_mode, ins.all_prefixes[i],
9819                                         orig_sizeflag);
9820
9821         if (name == NULL)
9822           abort ();
9823         prefix_length += strlen (name) + 1;
9824         if (ins.all_prefixes[i] == REX2_OPCODE)
9825           i386_dis_printf (info, dis_style_mnemonic, "{%s 0x%x} ", name,
9826                            (unsigned int) ins.rex2_payload);
9827         else
9828           i386_dis_printf (info, dis_style_mnemonic, "%s ", name);
9829       }
9830
9831   /* Check maximum code length.  */
9832   if ((ins.codep - ins.start_codep) > MAX_CODE_LENGTH)
9833     {
9834       i386_dis_printf (info, dis_style_text, "(bad)");
9835       ret = MAX_CODE_LENGTH;
9836       goto out;
9837     }
9838
9839   /* Calculate the number of operands this instruction has.  */
9840   op_count = 0;
9841   for (i = 0; i < MAX_OPERANDS; ++i)
9842     if (*ins.op_out[i] != '\0')
9843       ++op_count;
9844
9845   /* Calculate the number of spaces to print after the mnemonic.  */
9846   ins.obufp = ins.mnemonicendp;
9847   if (op_count > 0)
9848     {
9849       i = strlen (ins.obuf) + prefix_length;
9850       if (i < 7)
9851         i = 7 - i;
9852       else
9853         i = 1;
9854     }
9855   else
9856     i = 0;
9857
9858   /* Print the instruction mnemonic along with any trailing whitespace.  */
9859   i386_dis_printf (info, dis_style_mnemonic, "%s%*s", ins.obuf, i, "");
9860
9861   /* The enter and bound instructions are printed with operands in the same
9862      order as the intel book; everything else is printed in reverse order.  */
9863   intel_swap_2_3 = false;
9864   if (ins.intel_syntax || ins.two_source_ops)
9865     {
9866       for (i = 0; i < MAX_OPERANDS; ++i)
9867         op_txt[i] = ins.op_out[i];
9868
9869       if (ins.intel_syntax && dp && dp->op[2].rtn == OP_Rounding
9870           && dp->op[3].rtn == OP_E && dp->op[4].rtn == NULL)
9871         {
9872           op_txt[2] = ins.op_out[3];
9873           op_txt[3] = ins.op_out[2];
9874           intel_swap_2_3 = true;
9875         }
9876
9877       for (i = 0; i < (MAX_OPERANDS >> 1); ++i)
9878         {
9879           bool riprel;
9880
9881           ins.op_ad = ins.op_index[i];
9882           ins.op_index[i] = ins.op_index[MAX_OPERANDS - 1 - i];
9883           ins.op_index[MAX_OPERANDS - 1 - i] = ins.op_ad;
9884           riprel = ins.op_riprel[i];
9885           ins.op_riprel[i] = ins.op_riprel[MAX_OPERANDS - 1 - i];
9886           ins.op_riprel[MAX_OPERANDS - 1 - i] = riprel;
9887         }
9888     }
9889   else
9890     {
9891       for (i = 0; i < MAX_OPERANDS; ++i)
9892         op_txt[MAX_OPERANDS - 1 - i] = ins.op_out[i];
9893     }
9894
9895   needcomma = 0;
9896   for (i = 0; i < MAX_OPERANDS; ++i)
9897     if (*op_txt[i])
9898       {
9899         /* In Intel syntax embedded rounding / SAE are not separate operands.
9900            Instead they're attached to the prior register operand.  Simply
9901            suppress emission of the comma to achieve that effect.  */
9902         switch (i & -(ins.intel_syntax && dp))
9903           {
9904           case 2:
9905             if (dp->op[2].rtn == OP_Rounding && !intel_swap_2_3)
9906               needcomma = 0;
9907             break;
9908           case 3:
9909             if (dp->op[3].rtn == OP_Rounding || intel_swap_2_3)
9910               needcomma = 0;
9911             break;
9912           }
9913         if (needcomma)
9914           i386_dis_printf (info, dis_style_text, ",");
9915         if (ins.op_index[i] != -1 && !ins.op_riprel[i])
9916           {
9917             bfd_vma target = (bfd_vma) ins.op_address[ins.op_index[i]];
9918
9919             if (ins.op_is_jump)
9920               {
9921                 info->insn_info_valid = 1;
9922                 info->branch_delay_insns = 0;
9923                 info->data_size = 0;
9924                 info->target = target;
9925                 info->target2 = 0;
9926               }
9927             (*info->print_address_func) (target, info);
9928           }
9929         else
9930           i386_dis_printf (info, dis_style_text, "%s", op_txt[i]);
9931         needcomma = 1;
9932       }
9933
9934   for (i = 0; i < MAX_OPERANDS; i++)
9935     if (ins.op_index[i] != -1 && ins.op_riprel[i])
9936       {
9937         i386_dis_printf (info, dis_style_comment_start, "        # ");
9938         (*info->print_address_func)
9939           ((bfd_vma)(ins.start_pc + (ins.codep - ins.start_codep)
9940                      + ins.op_address[ins.op_index[i]]),
9941           info);
9942         break;
9943       }
9944   ret = ins.codep - priv.the_buffer;
9945  out:
9946   info->private_data = NULL;
9947   return ret;
9948 }
9949
9950 /* Here for backwards compatibility.  When gdb stops using
9951    print_insn_i386_att and print_insn_i386_intel these functions can
9952    disappear, and print_insn_i386 be merged into print_insn.  */
9953 int
9954 print_insn_i386_att (bfd_vma pc, disassemble_info *info)
9955 {
9956   return print_insn (pc, info, 0);
9957 }
9958
9959 int
9960 print_insn_i386_intel (bfd_vma pc, disassemble_info *info)
9961 {
9962   return print_insn (pc, info, 1);
9963 }
9964
9965 int
9966 print_insn_i386 (bfd_vma pc, disassemble_info *info)
9967 {
9968   return print_insn (pc, info, -1);
9969 }
9970
9971 static const char *float_mem[] = {
9972   /* d8 */
9973   "fadd{s|}",
9974   "fmul{s|}",
9975   "fcom{s|}",
9976   "fcomp{s|}",
9977   "fsub{s|}",
9978   "fsubr{s|}",
9979   "fdiv{s|}",
9980   "fdivr{s|}",
9981   /* d9 */
9982   "fld{s|}",
9983   "(bad)",
9984   "fst{s|}",
9985   "fstp{s|}",
9986   "fldenv{C|C}",
9987   "fldcw",
9988   "fNstenv{C|C}",
9989   "fNstcw",
9990   /* da */
9991   "fiadd{l|}",
9992   "fimul{l|}",
9993   "ficom{l|}",
9994   "ficomp{l|}",
9995   "fisub{l|}",
9996   "fisubr{l|}",
9997   "fidiv{l|}",
9998   "fidivr{l|}",
9999   /* db */
10000   "fild{l|}",
10001   "fisttp{l|}",
10002   "fist{l|}",
10003   "fistp{l|}",
10004   "(bad)",
10005   "fld{t|}",
10006   "(bad)",
10007   "fstp{t|}",
10008   /* dc */
10009   "fadd{l|}",
10010   "fmul{l|}",
10011   "fcom{l|}",
10012   "fcomp{l|}",
10013   "fsub{l|}",
10014   "fsubr{l|}",
10015   "fdiv{l|}",
10016   "fdivr{l|}",
10017   /* dd */
10018   "fld{l|}",
10019   "fisttp{ll|}",
10020   "fst{l||}",
10021   "fstp{l|}",
10022   "frstor{C|C}",
10023   "(bad)",
10024   "fNsave{C|C}",
10025   "fNstsw",
10026   /* de */
10027   "fiadd{s|}",
10028   "fimul{s|}",
10029   "ficom{s|}",
10030   "ficomp{s|}",
10031   "fisub{s|}",
10032   "fisubr{s|}",
10033   "fidiv{s|}",
10034   "fidivr{s|}",
10035   /* df */
10036   "fild{s|}",
10037   "fisttp{s|}",
10038   "fist{s|}",
10039   "fistp{s|}",
10040   "fbld",
10041   "fild{ll|}",
10042   "fbstp",
10043   "fistp{ll|}",
10044 };
10045
10046 static const unsigned char float_mem_mode[] = {
10047   /* d8 */
10048   d_mode,
10049   d_mode,
10050   d_mode,
10051   d_mode,
10052   d_mode,
10053   d_mode,
10054   d_mode,
10055   d_mode,
10056   /* d9 */
10057   d_mode,
10058   0,
10059   d_mode,
10060   d_mode,
10061   0,
10062   w_mode,
10063   0,
10064   w_mode,
10065   /* da */
10066   d_mode,
10067   d_mode,
10068   d_mode,
10069   d_mode,
10070   d_mode,
10071   d_mode,
10072   d_mode,
10073   d_mode,
10074   /* db */
10075   d_mode,
10076   d_mode,
10077   d_mode,
10078   d_mode,
10079   0,
10080   t_mode,
10081   0,
10082   t_mode,
10083   /* dc */
10084   q_mode,
10085   q_mode,
10086   q_mode,
10087   q_mode,
10088   q_mode,
10089   q_mode,
10090   q_mode,
10091   q_mode,
10092   /* dd */
10093   q_mode,
10094   q_mode,
10095   q_mode,
10096   q_mode,
10097   0,
10098   0,
10099   0,
10100   w_mode,
10101   /* de */
10102   w_mode,
10103   w_mode,
10104   w_mode,
10105   w_mode,
10106   w_mode,
10107   w_mode,
10108   w_mode,
10109   w_mode,
10110   /* df */
10111   w_mode,
10112   w_mode,
10113   w_mode,
10114   w_mode,
10115   t_mode,
10116   q_mode,
10117   t_mode,
10118   q_mode
10119 };
10120
10121 #define ST { OP_ST, 0 }
10122 #define STi { OP_STi, 0 }
10123
10124 #define FGRPd9_2 NULL, { { NULL, 1 } }, 0
10125 #define FGRPd9_4 NULL, { { NULL, 2 } }, 0
10126 #define FGRPd9_5 NULL, { { NULL, 3 } }, 0
10127 #define FGRPd9_6 NULL, { { NULL, 4 } }, 0
10128 #define FGRPd9_7 NULL, { { NULL, 5 } }, 0
10129 #define FGRPda_5 NULL, { { NULL, 6 } }, 0
10130 #define FGRPdb_4 NULL, { { NULL, 7 } }, 0
10131 #define FGRPde_3 NULL, { { NULL, 8 } }, 0
10132 #define FGRPdf_4 NULL, { { NULL, 9 } }, 0
10133
10134 static const struct dis386 float_reg[][8] = {
10135   /* d8 */
10136   {
10137     { "fadd",   { ST, STi }, 0 },
10138     { "fmul",   { ST, STi }, 0 },
10139     { "fcom",   { STi }, 0 },
10140     { "fcomp",  { STi }, 0 },
10141     { "fsub",   { ST, STi }, 0 },
10142     { "fsubr",  { ST, STi }, 0 },
10143     { "fdiv",   { ST, STi }, 0 },
10144     { "fdivr",  { ST, STi }, 0 },
10145   },
10146   /* d9 */
10147   {
10148     { "fld",    { STi }, 0 },
10149     { "fxch",   { STi }, 0 },
10150     { FGRPd9_2 },
10151     { Bad_Opcode },
10152     { FGRPd9_4 },
10153     { FGRPd9_5 },
10154     { FGRPd9_6 },
10155     { FGRPd9_7 },
10156   },
10157   /* da */
10158   {
10159     { "fcmovb", { ST, STi }, 0 },
10160     { "fcmove", { ST, STi }, 0 },
10161     { "fcmovbe",{ ST, STi }, 0 },
10162     { "fcmovu", { ST, STi }, 0 },
10163     { Bad_Opcode },
10164     { FGRPda_5 },
10165     { Bad_Opcode },
10166     { Bad_Opcode },
10167   },
10168   /* db */
10169   {
10170     { "fcmovnb",{ ST, STi }, 0 },
10171     { "fcmovne",{ ST, STi }, 0 },
10172     { "fcmovnbe",{ ST, STi }, 0 },
10173     { "fcmovnu",{ ST, STi }, 0 },
10174     { FGRPdb_4 },
10175     { "fucomi", { ST, STi }, 0 },
10176     { "fcomi",  { ST, STi }, 0 },
10177     { Bad_Opcode },
10178   },
10179   /* dc */
10180   {
10181     { "fadd",   { STi, ST }, 0 },
10182     { "fmul",   { STi, ST }, 0 },
10183     { Bad_Opcode },
10184     { Bad_Opcode },
10185     { "fsub{!M|r}",     { STi, ST }, 0 },
10186     { "fsub{M|}",       { STi, ST }, 0 },
10187     { "fdiv{!M|r}",     { STi, ST }, 0 },
10188     { "fdiv{M|}",       { STi, ST }, 0 },
10189   },
10190   /* dd */
10191   {
10192     { "ffree",  { STi }, 0 },
10193     { Bad_Opcode },
10194     { "fst",    { STi }, 0 },
10195     { "fstp",   { STi }, 0 },
10196     { "fucom",  { STi }, 0 },
10197     { "fucomp", { STi }, 0 },
10198     { Bad_Opcode },
10199     { Bad_Opcode },
10200   },
10201   /* de */
10202   {
10203     { "faddp",  { STi, ST }, 0 },
10204     { "fmulp",  { STi, ST }, 0 },
10205     { Bad_Opcode },
10206     { FGRPde_3 },
10207     { "fsub{!M|r}p",    { STi, ST }, 0 },
10208     { "fsub{M|}p",      { STi, ST }, 0 },
10209     { "fdiv{!M|r}p",    { STi, ST }, 0 },
10210     { "fdiv{M|}p",      { STi, ST }, 0 },
10211   },
10212   /* df */
10213   {
10214     { "ffreep", { STi }, 0 },
10215     { Bad_Opcode },
10216     { Bad_Opcode },
10217     { Bad_Opcode },
10218     { FGRPdf_4 },
10219     { "fucomip", { ST, STi }, 0 },
10220     { "fcomip", { ST, STi }, 0 },
10221     { Bad_Opcode },
10222   },
10223 };
10224
10225 static const char *const fgrps[][8] = {
10226   /* Bad opcode 0 */
10227   {
10228     "(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10229   },
10230
10231   /* d9_2  1 */
10232   {
10233     "fnop","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10234   },
10235
10236   /* d9_4  2 */
10237   {
10238     "fchs","fabs","(bad)","(bad)","ftst","fxam","(bad)","(bad)",
10239   },
10240
10241   /* d9_5  3 */
10242   {
10243     "fld1","fldl2t","fldl2e","fldpi","fldlg2","fldln2","fldz","(bad)",
10244   },
10245
10246   /* d9_6  4 */
10247   {
10248     "f2xm1","fyl2x","fptan","fpatan","fxtract","fprem1","fdecstp","fincstp",
10249   },
10250
10251   /* d9_7  5 */
10252   {
10253     "fprem","fyl2xp1","fsqrt","fsincos","frndint","fscale","fsin","fcos",
10254   },
10255
10256   /* da_5  6 */
10257   {
10258     "(bad)","fucompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10259   },
10260
10261   /* db_4  7 */
10262   {
10263     "fNeni(8087 only)","fNdisi(8087 only)","fNclex","fNinit",
10264     "fNsetpm(287 only)","frstpm(287 only)","(bad)","(bad)",
10265   },
10266
10267   /* de_3  8 */
10268   {
10269     "(bad)","fcompp","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10270   },
10271
10272   /* df_4  9 */
10273   {
10274     "fNstsw","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)","(bad)",
10275   },
10276 };
10277
10278 static void
10279 swap_operand (instr_info *ins)
10280 {
10281   ins->mnemonicendp[0] = '.';
10282   ins->mnemonicendp[1] = 's';
10283   ins->mnemonicendp[2] = '\0';
10284   ins->mnemonicendp += 2;
10285 }
10286
10287 static bool
10288 dofloat (instr_info *ins, int sizeflag)
10289 {
10290   const struct dis386 *dp;
10291   unsigned char floatop = ins->codep[-1];
10292
10293   if (ins->modrm.mod != 3)
10294     {
10295       int fp_indx = (floatop - 0xd8) * 8 + ins->modrm.reg;
10296
10297       putop (ins, float_mem[fp_indx], sizeflag);
10298       ins->obufp = ins->op_out[0];
10299       ins->op_ad = 2;
10300       return OP_E (ins, float_mem_mode[fp_indx], sizeflag);
10301     }
10302   /* Skip mod/rm byte.  */
10303   MODRM_CHECK;
10304   ins->codep++;
10305
10306   dp = &float_reg[floatop - 0xd8][ins->modrm.reg];
10307   if (dp->name == NULL)
10308     {
10309       putop (ins, fgrps[dp->op[0].bytemode][ins->modrm.rm], sizeflag);
10310
10311       /* Instruction fnstsw is only one with strange arg.  */
10312       if (floatop == 0xdf && ins->codep[-1] == 0xe0)
10313         strcpy (ins->op_out[0], att_names16[0] + ins->intel_syntax);
10314     }
10315   else
10316     {
10317       putop (ins, dp->name, sizeflag);
10318
10319       ins->obufp = ins->op_out[0];
10320       ins->op_ad = 2;
10321       if (dp->op[0].rtn
10322           && !dp->op[0].rtn (ins, dp->op[0].bytemode, sizeflag))
10323         return false;
10324
10325       ins->obufp = ins->op_out[1];
10326       ins->op_ad = 1;
10327       if (dp->op[1].rtn
10328           && !dp->op[1].rtn (ins, dp->op[1].bytemode, sizeflag))
10329         return false;
10330     }
10331   return true;
10332 }
10333
10334 static bool
10335 OP_ST (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10336        int sizeflag ATTRIBUTE_UNUSED)
10337 {
10338   oappend_register (ins, "%st");
10339   return true;
10340 }
10341
10342 static bool
10343 OP_STi (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
10344         int sizeflag ATTRIBUTE_UNUSED)
10345 {
10346   char scratch[8];
10347   int res = snprintf (scratch, ARRAY_SIZE (scratch), "%%st(%d)", ins->modrm.rm);
10348
10349   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
10350     abort ();
10351   oappend_register (ins, scratch);
10352   return true;
10353 }
10354
10355 /* Capital letters in template are macros.  */
10356 static int
10357 putop (instr_info *ins, const char *in_template, int sizeflag)
10358 {
10359   const char *p;
10360   int alt = 0;
10361   int cond = 1;
10362   unsigned int l = 0, len = 0;
10363   char last[4];
10364
10365   for (p = in_template; *p; p++)
10366     {
10367       if (len > l)
10368         {
10369           if (l >= sizeof (last) || !ISUPPER (*p))
10370             abort ();
10371           last[l++] = *p;
10372           continue;
10373         }
10374       switch (*p)
10375         {
10376         default:
10377           *ins->obufp++ = *p;
10378           break;
10379         case '%':
10380           len++;
10381           break;
10382         case '!':
10383           cond = 0;
10384           break;
10385         case '{':
10386           if (ins->intel_syntax)
10387             {
10388               while (*++p != '|')
10389                 if (*p == '}' || *p == '\0')
10390                   abort ();
10391               alt = 1;
10392             }
10393           break;
10394         case '|':
10395           while (*++p != '}')
10396             {
10397               if (*p == '\0')
10398                 abort ();
10399             }
10400           break;
10401         case '}':
10402           alt = 0;
10403           break;
10404         case 'A':
10405           if (ins->intel_syntax)
10406             break;
10407           if ((ins->need_modrm && ins->modrm.mod != 3)
10408               || (sizeflag & SUFFIX_ALWAYS))
10409             *ins->obufp++ = 'b';
10410           break;
10411         case 'B':
10412           if (l == 0)
10413             {
10414             case_B:
10415               if (ins->intel_syntax)
10416                 break;
10417               if (sizeflag & SUFFIX_ALWAYS)
10418                 *ins->obufp++ = 'b';
10419             }
10420           else if (l == 1 && last[0] == 'L')
10421             {
10422               if (ins->address_mode == mode_64bit
10423                   && !(ins->prefixes & PREFIX_ADDR))
10424                 {
10425                   *ins->obufp++ = 'a';
10426                   *ins->obufp++ = 'b';
10427                   *ins->obufp++ = 's';
10428                 }
10429
10430               goto case_B;
10431             }
10432           else
10433             abort ();
10434           break;
10435         case 'C':
10436           if (ins->intel_syntax && !alt)
10437             break;
10438           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10439             {
10440               if (sizeflag & DFLAG)
10441                 *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10442               else
10443                 *ins->obufp++ = ins->intel_syntax ? 'w' : 's';
10444               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10445             }
10446           break;
10447         case 'D':
10448           if (l == 1)
10449             {
10450               switch (last[0])
10451               {
10452               case 'X':
10453                 if (!ins->vex.evex || ins->vex.w)
10454                   *ins->obufp++ = 'd';
10455                 else
10456                   oappend (ins, "{bad}");
10457                 break;
10458               default:
10459                 abort ();
10460               }
10461               break;
10462             }
10463           if (l)
10464             abort ();
10465           if (ins->intel_syntax || !(sizeflag & SUFFIX_ALWAYS))
10466             break;
10467           USED_REX (REX_W);
10468           if (ins->modrm.mod == 3)
10469             {
10470               if (ins->rex & REX_W)
10471                 *ins->obufp++ = 'q';
10472               else
10473                 {
10474                   if (sizeflag & DFLAG)
10475                     *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10476                   else
10477                     *ins->obufp++ = 'w';
10478                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10479                 }
10480             }
10481           else
10482             *ins->obufp++ = 'w';
10483           break;
10484         case 'E':
10485           if (l == 1)
10486             {
10487               switch (last[0])
10488                 {
10489                 case 'X':
10490                   if (!ins->vex.evex || ins->vex.b || ins->vex.ll >= 2
10491                       || (ins->rex2 & 7)
10492                       || (ins->modrm.mod == 3 && (ins->rex & REX_X))
10493                       || !ins->vex.v || ins->vex.mask_register_specifier)
10494                     break;
10495                   /* AVX512 extends a number of V*D insns to also have V*Q variants,
10496                      merely distinguished by EVEX.W.  Look for a use of the
10497                      respective macro.  */
10498                   if (ins->vex.w)
10499                     {
10500                       const char *pct = strchr (p + 1, '%');
10501
10502                       if (pct != NULL && pct[1] == 'D' && pct[2] == 'Q')
10503                         break;
10504                     }
10505                   *ins->obufp++ = '{';
10506                   *ins->obufp++ = 'e';
10507                   *ins->obufp++ = 'v';
10508                   *ins->obufp++ = 'e';
10509                   *ins->obufp++ = 'x';
10510                   *ins->obufp++ = '}';
10511                   *ins->obufp++ = ' ';
10512                   break;
10513                 default:
10514                   abort ();
10515                 }
10516                 break;
10517             }
10518           /* For jcxz/jecxz */
10519           if (ins->address_mode == mode_64bit)
10520             {
10521               if (sizeflag & AFLAG)
10522                 *ins->obufp++ = 'r';
10523               else
10524                 *ins->obufp++ = 'e';
10525             }
10526           else
10527             if (sizeflag & AFLAG)
10528               *ins->obufp++ = 'e';
10529           ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10530           break;
10531         case 'F':
10532           if (l == 0)
10533             {
10534               if (ins->intel_syntax)
10535                 break;
10536               if ((ins->prefixes & PREFIX_ADDR) || (sizeflag & SUFFIX_ALWAYS))
10537                 {
10538                   if (sizeflag & AFLAG)
10539                     *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10540                   else
10541                     *ins->obufp++ = ins->address_mode == mode_64bit ? 'l' : 'w';
10542                   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
10543                 }
10544             }
10545           else if (l == 1 && last[0] == 'C')
10546             break;
10547           else
10548             abort ();
10549           break;
10550         case 'G':
10551           if (ins->intel_syntax || (ins->obufp[-1] != 's'
10552                                     && !(sizeflag & SUFFIX_ALWAYS)))
10553             break;
10554           if ((ins->rex & REX_W) || (sizeflag & DFLAG))
10555             *ins->obufp++ = 'l';
10556           else
10557             *ins->obufp++ = 'w';
10558           if (!(ins->rex & REX_W))
10559             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10560           break;
10561         case 'H':
10562           if (l == 0)
10563             {
10564               if (ins->intel_syntax)
10565                 break;
10566               if ((ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_CS
10567                   || (ins->prefixes & (PREFIX_CS | PREFIX_DS)) == PREFIX_DS)
10568                 {
10569                   ins->used_prefixes |= ins->prefixes & (PREFIX_CS | PREFIX_DS);
10570                   *ins->obufp++ = ',';
10571                   *ins->obufp++ = 'p';
10572
10573                   /* Set active_seg_prefix even if not set in 64-bit mode
10574                      because here it is a valid branch hint. */
10575                   if (ins->prefixes & PREFIX_DS)
10576                     {
10577                       ins->active_seg_prefix = PREFIX_DS;
10578                       *ins->obufp++ = 't';
10579                     }
10580                   else
10581                     {
10582                       ins->active_seg_prefix = PREFIX_CS;
10583                       *ins->obufp++ = 'n';
10584                     }
10585                 }
10586             }
10587           else if (l == 1 && last[0] == 'X')
10588             {
10589               if (!ins->vex.w)
10590                 *ins->obufp++ = 'h';
10591               else
10592                 oappend (ins, "{bad}");
10593             }
10594           else
10595             abort ();
10596           break;
10597         case 'K':
10598           USED_REX (REX_W);
10599           if (ins->rex & REX_W)
10600             *ins->obufp++ = 'q';
10601           else
10602             *ins->obufp++ = 'd';
10603           break;
10604         case 'L':
10605           if (ins->intel_syntax)
10606             break;
10607           if (sizeflag & SUFFIX_ALWAYS)
10608             {
10609               if (ins->rex & REX_W)
10610                 *ins->obufp++ = 'q';
10611               else
10612                 *ins->obufp++ = 'l';
10613             }
10614           break;
10615         case 'M':
10616           if (ins->intel_mnemonic != cond)
10617             *ins->obufp++ = 'r';
10618           break;
10619         case 'N':
10620           if ((ins->prefixes & PREFIX_FWAIT) == 0)
10621             *ins->obufp++ = 'n';
10622           else
10623             ins->used_prefixes |= PREFIX_FWAIT;
10624           break;
10625         case 'O':
10626           USED_REX (REX_W);
10627           if (ins->rex & REX_W)
10628             *ins->obufp++ = 'o';
10629           else if (ins->intel_syntax && (sizeflag & DFLAG))
10630             *ins->obufp++ = 'q';
10631           else
10632             *ins->obufp++ = 'd';
10633           if (!(ins->rex & REX_W))
10634             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10635           break;
10636         case '@':
10637           if (ins->address_mode == mode_64bit
10638               && (ins->isa64 == intel64 || (ins->rex & REX_W)
10639                   || !(ins->prefixes & PREFIX_DATA)))
10640             {
10641               if (sizeflag & SUFFIX_ALWAYS)
10642                 *ins->obufp++ = 'q';
10643               break;
10644             }
10645           /* Fall through.  */
10646         case 'P':
10647           if (l == 0)
10648             {
10649               if (!cond && ins->last_rex2_prefix >= 0 && (ins->rex & REX_W))
10650                 {
10651                   /* For pushp and popp, p is printed and do not print {rex2}
10652                      for them.  */
10653                   *ins->obufp++ = 'p';
10654                   ins->rex2 |= REX2_SPECIAL;
10655                   break;
10656                 }
10657
10658               /* For "!P" print nothing else in Intel syntax.  */
10659               if (!cond && ins->intel_syntax)
10660                 break;
10661
10662               if ((ins->modrm.mod == 3 || !cond)
10663                   && !(sizeflag & SUFFIX_ALWAYS))
10664                 break;
10665           /* Fall through.  */
10666         case 'T':
10667               if ((!(ins->rex & REX_W) && (ins->prefixes & PREFIX_DATA))
10668                   || ((sizeflag & SUFFIX_ALWAYS)
10669                       && ins->address_mode != mode_64bit))
10670                 {
10671                   *ins->obufp++ = (sizeflag & DFLAG)
10672                                   ? ins->intel_syntax ? 'd' : 'l' : 'w';
10673                   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10674                 }
10675               else if (sizeflag & SUFFIX_ALWAYS)
10676                 *ins->obufp++ = 'q';
10677             }
10678           else if (l == 1 && last[0] == 'L')
10679             {
10680               if ((ins->prefixes & PREFIX_DATA)
10681                   || (ins->rex & REX_W)
10682                   || (sizeflag & SUFFIX_ALWAYS))
10683                 {
10684                   USED_REX (REX_W);
10685                   if (ins->rex & REX_W)
10686                     *ins->obufp++ = 'q';
10687                   else
10688                     {
10689                       if (sizeflag & DFLAG)
10690                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10691                       else
10692                         *ins->obufp++ = 'w';
10693                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10694                     }
10695                 }
10696             }
10697           else
10698             abort ();
10699           break;
10700         case 'Q':
10701           if (l == 0)
10702             {
10703               if (ins->intel_syntax && !alt)
10704                 break;
10705               USED_REX (REX_W);
10706               if ((ins->need_modrm && ins->modrm.mod != 3)
10707                   || (sizeflag & SUFFIX_ALWAYS))
10708                 {
10709                   if (ins->rex & REX_W)
10710                     *ins->obufp++ = 'q';
10711                   else
10712                     {
10713                       if (sizeflag & DFLAG)
10714                         *ins->obufp++ = ins->intel_syntax ? 'd' : 'l';
10715                       else
10716                         *ins->obufp++ = 'w';
10717                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10718                     }
10719                 }
10720             }
10721           else if (l == 1 && last[0] == 'D')
10722             *ins->obufp++ = ins->vex.w ? 'q' : 'd';
10723           else if (l == 1 && last[0] == 'L')
10724             {
10725               if (cond ? ins->modrm.mod == 3 && !(sizeflag & SUFFIX_ALWAYS)
10726                        : ins->address_mode != mode_64bit)
10727                 break;
10728               if ((ins->rex & REX_W))
10729                 {
10730                   USED_REX (REX_W);
10731                   *ins->obufp++ = 'q';
10732                 }
10733               else if ((ins->address_mode == mode_64bit && cond)
10734                       || (sizeflag & SUFFIX_ALWAYS))
10735                 *ins->obufp++ = ins->intel_syntax? 'd' : 'l';
10736             }
10737           else
10738             abort ();
10739           break;
10740         case 'R':
10741           USED_REX (REX_W);
10742           if (ins->rex & REX_W)
10743             *ins->obufp++ = 'q';
10744           else if (sizeflag & DFLAG)
10745             {
10746               if (ins->intel_syntax)
10747                   *ins->obufp++ = 'd';
10748               else
10749                   *ins->obufp++ = 'l';
10750             }
10751           else
10752             *ins->obufp++ = 'w';
10753           if (ins->intel_syntax && !p[1]
10754               && ((ins->rex & REX_W) || (sizeflag & DFLAG)))
10755             *ins->obufp++ = 'e';
10756           if (!(ins->rex & REX_W))
10757             ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10758           break;
10759         case 'S':
10760           if (l == 0)
10761             {
10762             case_S:
10763               if (ins->intel_syntax)
10764                 break;
10765               if (sizeflag & SUFFIX_ALWAYS)
10766                 {
10767                   if (ins->rex & REX_W)
10768                     *ins->obufp++ = 'q';
10769                   else
10770                     {
10771                       if (sizeflag & DFLAG)
10772                         *ins->obufp++ = 'l';
10773                       else
10774                         *ins->obufp++ = 'w';
10775                       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10776                     }
10777                 }
10778               break;
10779             }
10780           if (l != 1)
10781             abort ();
10782           switch (last[0])
10783             {
10784             case 'L':
10785               if (ins->address_mode == mode_64bit
10786                   && !(ins->prefixes & PREFIX_ADDR))
10787                 {
10788                   *ins->obufp++ = 'a';
10789                   *ins->obufp++ = 'b';
10790                   *ins->obufp++ = 's';
10791                 }
10792
10793               goto case_S;
10794             case 'X':
10795               if (!ins->vex.evex || !ins->vex.w)
10796                 *ins->obufp++ = 's';
10797               else
10798                 oappend (ins, "{bad}");
10799               break;
10800             default:
10801               abort ();
10802             }
10803           break;
10804         case 'V':
10805           if (l == 0)
10806             {
10807               if (ins->need_vex)
10808                 *ins->obufp++ = 'v';
10809             }
10810           else if (l == 1)
10811             {
10812               switch (last[0])
10813                 {
10814                 case 'X':
10815                   if (ins->vex.evex)
10816                     break;
10817                   *ins->obufp++ = '{';
10818                   *ins->obufp++ = 'v';
10819                   *ins->obufp++ = 'e';
10820                   *ins->obufp++ = 'x';
10821                   *ins->obufp++ = '}';
10822                   *ins->obufp++ = ' ';
10823                   break;
10824                 case 'L':
10825                   if (ins->rex & REX_W)
10826                     {
10827                       *ins->obufp++ = 'a';
10828                       *ins->obufp++ = 'b';
10829                       *ins->obufp++ = 's';
10830                     }
10831                   goto case_S;
10832                 default:
10833                   abort ();
10834                 }
10835             }
10836           else
10837             abort ();
10838           break;
10839         case 'W':
10840           if (l == 0)
10841             {
10842               /* operand size flag for cwtl, cbtw */
10843               USED_REX (REX_W);
10844               if (ins->rex & REX_W)
10845                 {
10846                   if (ins->intel_syntax)
10847                     *ins->obufp++ = 'd';
10848                   else
10849                     *ins->obufp++ = 'l';
10850                 }
10851               else if (sizeflag & DFLAG)
10852                 *ins->obufp++ = 'w';
10853               else
10854                 *ins->obufp++ = 'b';
10855               if (!(ins->rex & REX_W))
10856                 ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10857             }
10858           else if (l == 1)
10859             {
10860               if (!ins->need_vex)
10861                 abort ();
10862               if (last[0] == 'X')
10863                 *ins->obufp++ = ins->vex.w ? 'd': 's';
10864               else if (last[0] == 'B')
10865                 *ins->obufp++ = ins->vex.w ? 'w': 'b';
10866               else
10867                 abort ();
10868             }
10869           else
10870             abort ();
10871           break;
10872         case 'X':
10873           if (l != 0)
10874             abort ();
10875           if (ins->need_vex
10876               ? ins->vex.prefix == DATA_PREFIX_OPCODE
10877               : ins->prefixes & PREFIX_DATA)
10878             {
10879               *ins->obufp++ = 'd';
10880               ins->used_prefixes |= PREFIX_DATA;
10881             }
10882           else
10883             *ins->obufp++ = 's';
10884           break;
10885         case 'Y':
10886           if (l == 0)
10887             {
10888               if (ins->vex.mask_register_specifier)
10889                 ins->illegal_masking = true;
10890             }
10891           else if (l == 1 && last[0] == 'X')
10892             {
10893               if (!ins->need_vex)
10894                 break;
10895               if (ins->intel_syntax
10896                   || ((ins->modrm.mod == 3 || ins->vex.b)
10897                       && !(sizeflag & SUFFIX_ALWAYS)))
10898                 break;
10899               switch (ins->vex.length)
10900                 {
10901                 case 128:
10902                   *ins->obufp++ = 'x';
10903                   break;
10904                 case 256:
10905                   *ins->obufp++ = 'y';
10906                   break;
10907                 case 512:
10908                   if (!ins->vex.evex)
10909                 default:
10910                     abort ();
10911                 }
10912             }
10913           else
10914             abort ();
10915           break;
10916         case 'Z':
10917           if (l == 0)
10918             {
10919               /* These insns ignore ModR/M.mod: Force it to 3 for OP_E().  */
10920               ins->modrm.mod = 3;
10921               if (!ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
10922                 *ins->obufp++ = ins->address_mode == mode_64bit ? 'q' : 'l';
10923             }
10924           else if (l == 1 && last[0] == 'X')
10925             {
10926               if (!ins->vex.evex)
10927                 abort ();
10928               if (ins->intel_syntax
10929                   || ((ins->modrm.mod == 3 || ins->vex.b)
10930                       && !(sizeflag & SUFFIX_ALWAYS)))
10931                 break;
10932               switch (ins->vex.length)
10933                 {
10934                 case 128:
10935                   *ins->obufp++ = 'x';
10936                   break;
10937                 case 256:
10938                   *ins->obufp++ = 'y';
10939                   break;
10940                 case 512:
10941                   *ins->obufp++ = 'z';
10942                   break;
10943                 default:
10944                   abort ();
10945                 }
10946             }
10947           else
10948             abort ();
10949           break;
10950         case '^':
10951           if (ins->intel_syntax)
10952             break;
10953           if (ins->isa64 == intel64 && (ins->rex & REX_W))
10954             {
10955               USED_REX (REX_W);
10956               *ins->obufp++ = 'q';
10957               break;
10958             }
10959           if ((ins->prefixes & PREFIX_DATA) || (sizeflag & SUFFIX_ALWAYS))
10960             {
10961               if (sizeflag & DFLAG)
10962                 *ins->obufp++ = 'l';
10963               else
10964                 *ins->obufp++ = 'w';
10965               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
10966             }
10967           break;
10968         }
10969
10970       if (len == l)
10971         len = l = 0;
10972     }
10973   *ins->obufp = 0;
10974   ins->mnemonicendp = ins->obufp;
10975   return 0;
10976 }
10977
10978 /* Add a style marker to *INS->obufp that encodes STYLE.  This assumes that
10979    the buffer pointed to by INS->obufp has space.  A style marker is made
10980    from the STYLE_MARKER_CHAR followed by STYLE converted to a single hex
10981    digit, followed by another STYLE_MARKER_CHAR.  This function assumes
10982    that the number of styles is not greater than 16.  */
10983
10984 static void
10985 oappend_insert_style (instr_info *ins, enum disassembler_style style)
10986 {
10987   unsigned num = (unsigned) style;
10988
10989   /* We currently assume that STYLE can be encoded as a single hex
10990      character.  If more styles are added then this might start to fail,
10991      and we'll need to expand this code.  */
10992   if (num > 0xf)
10993     abort ();
10994
10995   *ins->obufp++ = STYLE_MARKER_CHAR;
10996   *ins->obufp++ = (num < 10 ? ('0' + num)
10997                    : ((num < 16) ? ('a' + (num - 10)) : '0'));
10998   *ins->obufp++ = STYLE_MARKER_CHAR;
10999
11000   /* This final null character is not strictly necessary, after inserting a
11001      style marker we should always be inserting some additional content.
11002      However, having the buffer null terminated doesn't cost much, and make
11003      it easier to debug what's going on.  Also, if we do ever forget to add
11004      any additional content after this style marker, then the buffer will
11005      still be well formed.  */
11006   *ins->obufp = '\0';
11007 }
11008
11009 static void
11010 oappend_with_style (instr_info *ins, const char *s,
11011                     enum disassembler_style style)
11012 {
11013   oappend_insert_style (ins, style);
11014   ins->obufp = stpcpy (ins->obufp, s);
11015 }
11016
11017 /* Add a single character C to the buffer pointer to by INS->obufp, marking
11018    the style for the character as STYLE.  */
11019
11020 static void
11021 oappend_char_with_style (instr_info *ins, const char c,
11022                          enum disassembler_style style)
11023 {
11024   oappend_insert_style (ins, style);
11025   *ins->obufp++ = c;
11026   *ins->obufp = '\0';
11027 }
11028
11029 /* Like oappend_char_with_style, but always uses dis_style_text.  */
11030
11031 static void
11032 oappend_char (instr_info *ins, const char c)
11033 {
11034   oappend_char_with_style (ins, c, dis_style_text);
11035 }
11036
11037 static void
11038 append_seg (instr_info *ins)
11039 {
11040   /* Only print the active segment register.  */
11041   if (!ins->active_seg_prefix)
11042     return;
11043
11044   ins->used_prefixes |= ins->active_seg_prefix;
11045   switch (ins->active_seg_prefix)
11046     {
11047     case PREFIX_CS:
11048       oappend_register (ins, att_names_seg[1]);
11049       break;
11050     case PREFIX_DS:
11051       oappend_register (ins, att_names_seg[3]);
11052       break;
11053     case PREFIX_SS:
11054       oappend_register (ins, att_names_seg[2]);
11055       break;
11056     case PREFIX_ES:
11057       oappend_register (ins, att_names_seg[0]);
11058       break;
11059     case PREFIX_FS:
11060       oappend_register (ins, att_names_seg[4]);
11061       break;
11062     case PREFIX_GS:
11063       oappend_register (ins, att_names_seg[5]);
11064       break;
11065     default:
11066       break;
11067     }
11068   oappend_char (ins, ':');
11069 }
11070
11071 static void
11072 print_operand_value (instr_info *ins, bfd_vma disp,
11073                      enum disassembler_style style)
11074 {
11075   char tmp[30];
11076
11077   if (ins->address_mode != mode_64bit)
11078     disp &= 0xffffffff;
11079   sprintf (tmp, "0x%" PRIx64, (uint64_t) disp);
11080   oappend_with_style (ins, tmp, style);
11081 }
11082
11083 /* Like oappend, but called for immediate operands.  */
11084
11085 static void
11086 oappend_immediate (instr_info *ins, bfd_vma imm)
11087 {
11088   if (!ins->intel_syntax)
11089     oappend_char_with_style (ins, '$', dis_style_immediate);
11090   print_operand_value (ins, imm, dis_style_immediate);
11091 }
11092
11093 /* Put DISP in BUF as signed hex number.  */
11094
11095 static void
11096 print_displacement (instr_info *ins, bfd_signed_vma val)
11097 {
11098   char tmp[30];
11099
11100   if (val < 0)
11101     {
11102       oappend_char_with_style (ins, '-', dis_style_address_offset);
11103       val = (bfd_vma) 0 - val;
11104
11105       /* Check for possible overflow.  */
11106       if (val < 0)
11107         {
11108           switch (ins->address_mode)
11109             {
11110             case mode_64bit:
11111               oappend_with_style (ins, "0x8000000000000000",
11112                                   dis_style_address_offset);
11113               break;
11114             case mode_32bit:
11115               oappend_with_style (ins, "0x80000000",
11116                                   dis_style_address_offset);
11117               break;
11118             case mode_16bit:
11119               oappend_with_style (ins, "0x8000",
11120                                   dis_style_address_offset);
11121               break;
11122             }
11123           return;
11124         }
11125     }
11126
11127   sprintf (tmp, "0x%" PRIx64, (int64_t) val);
11128   oappend_with_style (ins, tmp, dis_style_address_offset);
11129 }
11130
11131 static void
11132 intel_operand_size (instr_info *ins, int bytemode, int sizeflag)
11133 {
11134   /* Check if there is a broadcast, when evex.b is not treated as evex.nd.  */
11135   if (ins->vex.b && ins->evex_type == evex_default)
11136     {
11137       if (!ins->vex.no_broadcast)
11138         switch (bytemode)
11139           {
11140           case x_mode:
11141           case evex_half_bcst_xmmq_mode:
11142             if (ins->vex.w)
11143               oappend (ins, "QWORD BCST ");
11144             else
11145               oappend (ins, "DWORD BCST ");
11146             break;
11147           case xh_mode:
11148           case evex_half_bcst_xmmqh_mode:
11149           case evex_half_bcst_xmmqdh_mode:
11150             oappend (ins, "WORD BCST ");
11151             break;
11152           default:
11153             ins->vex.no_broadcast = true;
11154             break;
11155           }
11156       return;
11157     }
11158   switch (bytemode)
11159     {
11160     case b_mode:
11161     case b_swap_mode:
11162     case db_mode:
11163       oappend (ins, "BYTE PTR ");
11164       break;
11165     case w_mode:
11166     case w_swap_mode:
11167     case dw_mode:
11168       oappend (ins, "WORD PTR ");
11169       break;
11170     case indir_v_mode:
11171       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11172         {
11173           oappend (ins, "QWORD PTR ");
11174           break;
11175         }
11176       /* Fall through.  */
11177     case stack_v_mode:
11178       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11179                                               || (ins->rex & REX_W)))
11180         {
11181           oappend (ins, "QWORD PTR ");
11182           break;
11183         }
11184       /* Fall through.  */
11185     case v_mode:
11186     case v_swap_mode:
11187     case dq_mode:
11188       USED_REX (REX_W);
11189       if (ins->rex & REX_W)
11190         oappend (ins, "QWORD PTR ");
11191       else if (bytemode == dq_mode)
11192         oappend (ins, "DWORD PTR ");
11193       else
11194         {
11195           if (sizeflag & DFLAG)
11196             oappend (ins, "DWORD PTR ");
11197           else
11198             oappend (ins, "WORD PTR ");
11199           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11200         }
11201       break;
11202     case z_mode:
11203       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
11204         *ins->obufp++ = 'D';
11205       oappend (ins, "WORD PTR ");
11206       if (!(ins->rex & REX_W))
11207         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11208       break;
11209     case a_mode:
11210       if (sizeflag & DFLAG)
11211         oappend (ins, "QWORD PTR ");
11212       else
11213         oappend (ins, "DWORD PTR ");
11214       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11215       break;
11216     case movsxd_mode:
11217       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11218         oappend (ins, "WORD PTR ");
11219       else
11220         oappend (ins, "DWORD PTR ");
11221       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11222       break;
11223     case d_mode:
11224     case d_swap_mode:
11225       oappend (ins, "DWORD PTR ");
11226       break;
11227     case q_mode:
11228     case q_swap_mode:
11229       oappend (ins, "QWORD PTR ");
11230       break;
11231     case m_mode:
11232       if (ins->address_mode == mode_64bit)
11233         oappend (ins, "QWORD PTR ");
11234       else
11235         oappend (ins, "DWORD PTR ");
11236       break;
11237     case f_mode:
11238       if (sizeflag & DFLAG)
11239         oappend (ins, "FWORD PTR ");
11240       else
11241         oappend (ins, "DWORD PTR ");
11242       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11243       break;
11244     case t_mode:
11245       oappend (ins, "TBYTE PTR ");
11246       break;
11247     case x_mode:
11248     case xh_mode:
11249     case x_swap_mode:
11250     case evex_x_gscat_mode:
11251     case evex_x_nobcst_mode:
11252     case bw_unit_mode:
11253       if (ins->need_vex)
11254         {
11255           switch (ins->vex.length)
11256             {
11257             case 128:
11258               oappend (ins, "XMMWORD PTR ");
11259               break;
11260             case 256:
11261               oappend (ins, "YMMWORD PTR ");
11262               break;
11263             case 512:
11264               oappend (ins, "ZMMWORD PTR ");
11265               break;
11266             default:
11267               abort ();
11268             }
11269         }
11270       else
11271         oappend (ins, "XMMWORD PTR ");
11272       break;
11273     case xmm_mode:
11274       oappend (ins, "XMMWORD PTR ");
11275       break;
11276     case ymm_mode:
11277       oappend (ins, "YMMWORD PTR ");
11278       break;
11279     case xmmq_mode:
11280     case evex_half_bcst_xmmqh_mode:
11281     case evex_half_bcst_xmmq_mode:
11282       switch (ins->vex.length)
11283         {
11284         case 0:
11285         case 128:
11286           oappend (ins, "QWORD PTR ");
11287           break;
11288         case 256:
11289           oappend (ins, "XMMWORD PTR ");
11290           break;
11291         case 512:
11292           oappend (ins, "YMMWORD PTR ");
11293           break;
11294         default:
11295           abort ();
11296         }
11297       break;
11298     case xmmdw_mode:
11299       if (!ins->need_vex)
11300         abort ();
11301
11302       switch (ins->vex.length)
11303         {
11304         case 128:
11305           oappend (ins, "WORD PTR ");
11306           break;
11307         case 256:
11308           oappend (ins, "DWORD PTR ");
11309           break;
11310         case 512:
11311           oappend (ins, "QWORD PTR ");
11312           break;
11313         default:
11314           abort ();
11315         }
11316       break;
11317     case xmmqd_mode:
11318     case evex_half_bcst_xmmqdh_mode:
11319       if (!ins->need_vex)
11320         abort ();
11321
11322       switch (ins->vex.length)
11323         {
11324         case 128:
11325           oappend (ins, "DWORD PTR ");
11326           break;
11327         case 256:
11328           oappend (ins, "QWORD PTR ");
11329           break;
11330         case 512:
11331           oappend (ins, "XMMWORD PTR ");
11332           break;
11333         default:
11334           abort ();
11335         }
11336       break;
11337     case ymmq_mode:
11338       if (!ins->need_vex)
11339         abort ();
11340
11341       switch (ins->vex.length)
11342         {
11343         case 128:
11344           oappend (ins, "QWORD PTR ");
11345           break;
11346         case 256:
11347           oappend (ins, "YMMWORD PTR ");
11348           break;
11349         case 512:
11350           oappend (ins, "ZMMWORD PTR ");
11351           break;
11352         default:
11353           abort ();
11354         }
11355       break;
11356     case o_mode:
11357       oappend (ins, "OWORD PTR ");
11358       break;
11359     case vex_vsib_d_w_dq_mode:
11360     case vex_vsib_q_w_dq_mode:
11361       if (!ins->need_vex)
11362         abort ();
11363       if (ins->vex.w)
11364         oappend (ins, "QWORD PTR ");
11365       else
11366         oappend (ins, "DWORD PTR ");
11367       break;
11368     case mask_bd_mode:
11369       if (!ins->need_vex || ins->vex.length != 128)
11370         abort ();
11371       if (ins->vex.w)
11372         oappend (ins, "DWORD PTR ");
11373       else
11374         oappend (ins, "BYTE PTR ");
11375       break;
11376     case mask_mode:
11377       if (!ins->need_vex)
11378         abort ();
11379       if (ins->vex.w)
11380         oappend (ins, "QWORD PTR ");
11381       else
11382         oappend (ins, "WORD PTR ");
11383       break;
11384     case v_bnd_mode:
11385     case v_bndmk_mode:
11386     default:
11387       break;
11388     }
11389 }
11390
11391 static void
11392 print_register (instr_info *ins, unsigned int reg, unsigned int rexmask,
11393                 int bytemode, int sizeflag)
11394 {
11395   const char (*names)[8];
11396
11397   /* Masking is invalid for insns with GPR destination. Set the flag uniformly,
11398      as the consumer will inspect it only for the destination operand.  */
11399   if (bytemode != mask_mode && ins->vex.mask_register_specifier)
11400     ins->illegal_masking = true;
11401
11402   USED_REX (rexmask);
11403   if (ins->rex & rexmask)
11404     reg += 8;
11405   if (ins->rex2 & rexmask)
11406     reg += 16;
11407
11408   switch (bytemode)
11409     {
11410     case b_mode:
11411     case b_swap_mode:
11412       if (reg & 4)
11413         USED_REX (0);
11414       if (ins->rex || ins->rex2)
11415         names = att_names8rex;
11416       else
11417         names = att_names8;
11418       break;
11419     case w_mode:
11420       names = att_names16;
11421       break;
11422     case d_mode:
11423     case dw_mode:
11424     case db_mode:
11425       names = att_names32;
11426       break;
11427     case q_mode:
11428       names = att_names64;
11429       break;
11430     case m_mode:
11431     case v_bnd_mode:
11432       names = ins->address_mode == mode_64bit ? att_names64 : att_names32;
11433       break;
11434     case bnd_mode:
11435     case bnd_swap_mode:
11436       if (reg > 0x3)
11437         {
11438           oappend (ins, "(bad)");
11439           return;
11440         }
11441       names = att_names_bnd;
11442       break;
11443     case indir_v_mode:
11444       if (ins->address_mode == mode_64bit && ins->isa64 == intel64)
11445         {
11446           names = att_names64;
11447           break;
11448         }
11449       /* Fall through.  */
11450     case stack_v_mode:
11451       if (ins->address_mode == mode_64bit && ((sizeflag & DFLAG)
11452                                               || (ins->rex & REX_W)))
11453         {
11454           names = att_names64;
11455           break;
11456         }
11457       bytemode = v_mode;
11458       /* Fall through.  */
11459     case v_mode:
11460     case v_swap_mode:
11461     case dq_mode:
11462       USED_REX (REX_W);
11463       if (ins->rex & REX_W)
11464         names = att_names64;
11465       else if (bytemode != v_mode && bytemode != v_swap_mode)
11466         names = att_names32;
11467       else
11468         {
11469           if (sizeflag & DFLAG)
11470             names = att_names32;
11471           else
11472             names = att_names16;
11473           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11474         }
11475       break;
11476     case movsxd_mode:
11477       if (!(sizeflag & DFLAG) && ins->isa64 == intel64)
11478         names = att_names16;
11479       else
11480         names = att_names32;
11481       ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
11482       break;
11483     case va_mode:
11484       names = (ins->address_mode == mode_64bit
11485                ? att_names64 : att_names32);
11486       if (!(ins->prefixes & PREFIX_ADDR))
11487         names = (ins->address_mode == mode_16bit
11488                      ? att_names16 : names);
11489       else
11490         {
11491           /* Remove "addr16/addr32".  */
11492           ins->all_prefixes[ins->last_addr_prefix] = 0;
11493           names = (ins->address_mode != mode_32bit
11494                        ? att_names32 : att_names16);
11495           ins->used_prefixes |= PREFIX_ADDR;
11496         }
11497       break;
11498     case mask_bd_mode:
11499     case mask_mode:
11500       if (reg > 0x7)
11501         {
11502           oappend (ins, "(bad)");
11503           return;
11504         }
11505       names = att_names_mask;
11506       break;
11507     case 0:
11508       return;
11509     default:
11510       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
11511       return;
11512     }
11513   oappend_register (ins, names[reg]);
11514 }
11515
11516 static bool
11517 get8s (instr_info *ins, bfd_vma *res)
11518 {
11519   if (!fetch_code (ins->info, ins->codep + 1))
11520     return false;
11521   *res = ((bfd_vma) *ins->codep++ ^ 0x80) - 0x80;
11522   return true;
11523 }
11524
11525 static bool
11526 get16 (instr_info *ins, bfd_vma *res)
11527 {
11528   if (!fetch_code (ins->info, ins->codep + 2))
11529     return false;
11530   *res = *ins->codep++;
11531   *res |= (bfd_vma) *ins->codep++ << 8;
11532   return true;
11533 }
11534
11535 static bool
11536 get16s (instr_info *ins, bfd_vma *res)
11537 {
11538   if (!get16 (ins, res))
11539     return false;
11540   *res = (*res ^ 0x8000) - 0x8000;
11541   return true;
11542 }
11543
11544 static bool
11545 get32 (instr_info *ins, bfd_vma *res)
11546 {
11547   if (!fetch_code (ins->info, ins->codep + 4))
11548     return false;
11549   *res = *ins->codep++;
11550   *res |= (bfd_vma) *ins->codep++ << 8;
11551   *res |= (bfd_vma) *ins->codep++ << 16;
11552   *res |= (bfd_vma) *ins->codep++ << 24;
11553   return true;
11554 }
11555
11556 static bool
11557 get32s (instr_info *ins, bfd_vma *res)
11558 {
11559   if (!get32 (ins, res))
11560     return false;
11561
11562   *res = (*res ^ ((bfd_vma) 1 << 31)) - ((bfd_vma) 1 << 31);
11563
11564   return true;
11565 }
11566
11567 static bool
11568 get64 (instr_info *ins, uint64_t *res)
11569 {
11570   unsigned int a;
11571   unsigned int b;
11572
11573   if (!fetch_code (ins->info, ins->codep + 8))
11574     return false;
11575   a = *ins->codep++;
11576   a |= (unsigned int) *ins->codep++ << 8;
11577   a |= (unsigned int) *ins->codep++ << 16;
11578   a |= (unsigned int) *ins->codep++ << 24;
11579   b = *ins->codep++;
11580   b |= (unsigned int) *ins->codep++ << 8;
11581   b |= (unsigned int) *ins->codep++ << 16;
11582   b |= (unsigned int) *ins->codep++ << 24;
11583   *res = a + ((uint64_t) b << 32);
11584   return true;
11585 }
11586
11587 static void
11588 set_op (instr_info *ins, bfd_vma op, bool riprel)
11589 {
11590   ins->op_index[ins->op_ad] = ins->op_ad;
11591   if (ins->address_mode == mode_64bit)
11592     ins->op_address[ins->op_ad] = op;
11593   else /* Mask to get a 32-bit address.  */
11594     ins->op_address[ins->op_ad] = op & 0xffffffff;
11595   ins->op_riprel[ins->op_ad] = riprel;
11596 }
11597
11598 static bool
11599 BadOp (instr_info *ins)
11600 {
11601   /* Throw away prefixes and 1st. opcode byte.  */
11602   struct dis_private *priv = ins->info->private_data;
11603
11604   ins->codep = priv->the_buffer + ins->nr_prefixes + ins->need_vex + 1;
11605   ins->obufp = stpcpy (ins->obufp, "(bad)");
11606   return true;
11607 }
11608
11609 static bool
11610 OP_Skip_MODRM (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
11611                int sizeflag ATTRIBUTE_UNUSED)
11612 {
11613   if (ins->modrm.mod != 3)
11614     return BadOp (ins);
11615
11616   /* Skip mod/rm byte.  */
11617   MODRM_CHECK;
11618   ins->codep++;
11619   ins->has_skipped_modrm = true;
11620   return true;
11621 }
11622
11623 static bool
11624 OP_E_memory (instr_info *ins, int bytemode, int sizeflag)
11625 {
11626   int add = (ins->rex & REX_B) ? 8 : 0;
11627   int riprel = 0;
11628   int shift;
11629
11630   add += (ins->rex2 & REX_B) ? 16 : 0;
11631
11632   /* Handles EVEX other than APX EVEX-promoted instructions.  */
11633   if (ins->vex.evex && ins->evex_type == evex_default)
11634     {
11635
11636       /* Zeroing-masking is invalid for memory destinations. Set the flag
11637          uniformly, as the consumer will inspect it only for the destination
11638          operand.  */
11639       if (ins->vex.zeroing)
11640         ins->illegal_masking = true;
11641
11642       switch (bytemode)
11643         {
11644         case dw_mode:
11645         case w_mode:
11646         case w_swap_mode:
11647           shift = 1;
11648           break;
11649         case db_mode:
11650         case b_mode:
11651           shift = 0;
11652           break;
11653         case dq_mode:
11654           if (ins->address_mode != mode_64bit)
11655             {
11656         case d_mode:
11657         case d_swap_mode:
11658               shift = 2;
11659               break;
11660             }
11661             /* fall through */
11662         case vex_vsib_d_w_dq_mode:
11663         case vex_vsib_q_w_dq_mode:
11664         case evex_x_gscat_mode:
11665           shift = ins->vex.w ? 3 : 2;
11666           break;
11667         case xh_mode:
11668         case evex_half_bcst_xmmqh_mode:
11669         case evex_half_bcst_xmmqdh_mode:
11670           if (ins->vex.b)
11671             {
11672               shift = ins->vex.w ? 2 : 1;
11673               break;
11674             }
11675           /* Fall through.  */
11676         case x_mode:
11677         case evex_half_bcst_xmmq_mode:
11678           if (ins->vex.b)
11679             {
11680               shift = ins->vex.w ? 3 : 2;
11681               break;
11682             }
11683           /* Fall through.  */
11684         case xmmqd_mode:
11685         case xmmdw_mode:
11686         case xmmq_mode:
11687         case ymmq_mode:
11688         case evex_x_nobcst_mode:
11689         case x_swap_mode:
11690           switch (ins->vex.length)
11691             {
11692             case 128:
11693               shift = 4;
11694               break;
11695             case 256:
11696               shift = 5;
11697               break;
11698             case 512:
11699               shift = 6;
11700               break;
11701             default:
11702               abort ();
11703             }
11704           /* Make necessary corrections to shift for modes that need it.  */
11705           if (bytemode == xmmq_mode
11706               || bytemode == evex_half_bcst_xmmqh_mode
11707               || bytemode == evex_half_bcst_xmmq_mode
11708               || (bytemode == ymmq_mode && ins->vex.length == 128))
11709             shift -= 1;
11710           else if (bytemode == xmmqd_mode
11711                    || bytemode == evex_half_bcst_xmmqdh_mode)
11712             shift -= 2;
11713           else if (bytemode == xmmdw_mode)
11714             shift -= 3;
11715           break;
11716         case ymm_mode:
11717           shift = 5;
11718           break;
11719         case xmm_mode:
11720           shift = 4;
11721           break;
11722         case q_mode:
11723         case q_swap_mode:
11724           shift = 3;
11725           break;
11726         case bw_unit_mode:
11727           shift = ins->vex.w ? 1 : 0;
11728           break;
11729         default:
11730           abort ();
11731         }
11732     }
11733   else
11734     shift = 0;
11735
11736   USED_REX (REX_B);
11737   if (ins->intel_syntax)
11738     intel_operand_size (ins, bytemode, sizeflag);
11739   append_seg (ins);
11740
11741   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
11742     {
11743       /* 32/64 bit address mode */
11744       bfd_vma disp = 0;
11745       int havedisp;
11746       int havebase;
11747       int needindex;
11748       int needaddr32;
11749       int base, rbase;
11750       int vindex = 0;
11751       int scale = 0;
11752       int addr32flag = !((sizeflag & AFLAG)
11753                          || bytemode == v_bnd_mode
11754                          || bytemode == v_bndmk_mode
11755                          || bytemode == bnd_mode
11756                          || bytemode == bnd_swap_mode);
11757       bool check_gather = false;
11758       const char (*indexes)[8] = NULL;
11759
11760       havebase = 1;
11761       base = ins->modrm.rm;
11762
11763       if (base == 4)
11764         {
11765           vindex = ins->sib.index;
11766           USED_REX (REX_X);
11767           if (ins->rex & REX_X)
11768             vindex += 8;
11769           switch (bytemode)
11770             {
11771             case vex_vsib_d_w_dq_mode:
11772             case vex_vsib_q_w_dq_mode:
11773               if (!ins->need_vex)
11774                 abort ();
11775               if (ins->vex.evex)
11776                 {
11777                   /* S/G EVEX insns require EVEX.X4 not to be set.  */
11778                   if (ins->rex2 & REX_X)
11779                     {
11780                       oappend (ins, "(bad)");
11781                       return true;
11782                     }
11783
11784                   if (!ins->vex.v)
11785                     vindex += 16;
11786                   check_gather = ins->obufp == ins->op_out[1];
11787                 }
11788
11789               switch (ins->vex.length)
11790                 {
11791                 case 128:
11792                   indexes = att_names_xmm;
11793                   break;
11794                 case 256:
11795                   if (!ins->vex.w
11796                       || bytemode == vex_vsib_q_w_dq_mode)
11797                     indexes = att_names_ymm;
11798                   else
11799                     indexes = att_names_xmm;
11800                   break;
11801                 case 512:
11802                   if (!ins->vex.w
11803                       || bytemode == vex_vsib_q_w_dq_mode)
11804                     indexes = att_names_zmm;
11805                   else
11806                     indexes = att_names_ymm;
11807                   break;
11808                 default:
11809                   abort ();
11810                 }
11811               break;
11812             default:
11813               if (ins->rex2 & REX_X)
11814                 vindex += 16;
11815
11816               if (vindex != 4)
11817                 indexes = ins->address_mode == mode_64bit && !addr32flag
11818                           ? att_names64 : att_names32;
11819               break;
11820             }
11821           scale = ins->sib.scale;
11822           base = ins->sib.base;
11823           ins->codep++;
11824         }
11825       else
11826         {
11827           /* Check for mandatory SIB.  */
11828           if (bytemode == vex_vsib_d_w_dq_mode
11829               || bytemode == vex_vsib_q_w_dq_mode
11830               || bytemode == vex_sibmem_mode)
11831             {
11832               oappend (ins, "(bad)");
11833               return true;
11834             }
11835         }
11836       rbase = base + add;
11837
11838       switch (ins->modrm.mod)
11839         {
11840         case 0:
11841           if (base == 5)
11842             {
11843               havebase = 0;
11844               if (ins->address_mode == mode_64bit && !ins->has_sib)
11845                 riprel = 1;
11846               if (!get32s (ins, &disp))
11847                 return false;
11848               if (riprel && bytemode == v_bndmk_mode)
11849                 {
11850                   oappend (ins, "(bad)");
11851                   return true;
11852                 }
11853             }
11854           break;
11855         case 1:
11856           if (!get8s (ins, &disp))
11857             return false;
11858           if (ins->vex.evex && shift > 0)
11859             disp <<= shift;
11860           break;
11861         case 2:
11862           if (!get32s (ins, &disp))
11863             return false;
11864           break;
11865         }
11866
11867       needindex = 0;
11868       needaddr32 = 0;
11869       if (ins->has_sib
11870           && !havebase
11871           && !indexes
11872           && ins->address_mode != mode_16bit)
11873         {
11874           if (ins->address_mode == mode_64bit)
11875             {
11876               if (addr32flag)
11877                 {
11878                   /* Without base nor index registers, zero-extend the
11879                      lower 32-bit displacement to 64 bits.  */
11880                   disp &= 0xffffffff;
11881                   needindex = 1;
11882                 }
11883               needaddr32 = 1;
11884             }
11885           else
11886             {
11887               /* In 32-bit mode, we need index register to tell [offset]
11888                  from [eiz*1 + offset].  */
11889               needindex = 1;
11890             }
11891         }
11892
11893       havedisp = (havebase
11894                   || needindex
11895                   || (ins->has_sib && (indexes || scale != 0)));
11896
11897       if (!ins->intel_syntax)
11898         if (ins->modrm.mod != 0 || base == 5)
11899           {
11900             if (havedisp || riprel)
11901               print_displacement (ins, disp);
11902             else
11903               print_operand_value (ins, disp, dis_style_address_offset);
11904             if (riprel)
11905               {
11906                 set_op (ins, disp, true);
11907                 oappend_char (ins, '(');
11908                 oappend_with_style (ins, !addr32flag ? "%rip" : "%eip",
11909                                     dis_style_register);
11910                 oappend_char (ins, ')');
11911               }
11912           }
11913
11914       if ((havebase || indexes || needindex || needaddr32 || riprel)
11915           && (ins->address_mode != mode_64bit
11916               || ((bytemode != v_bnd_mode)
11917                   && (bytemode != v_bndmk_mode)
11918                   && (bytemode != bnd_mode)
11919                   && (bytemode != bnd_swap_mode))))
11920         ins->used_prefixes |= PREFIX_ADDR;
11921
11922       if (havedisp || (ins->intel_syntax && riprel))
11923         {
11924           oappend_char (ins, ins->open_char);
11925           if (ins->intel_syntax && riprel)
11926             {
11927               set_op (ins, disp, true);
11928               oappend_with_style (ins, !addr32flag ? "rip" : "eip",
11929                                   dis_style_register);
11930             }
11931           if (havebase)
11932             oappend_register
11933               (ins,
11934                (ins->address_mode == mode_64bit && !addr32flag
11935                 ? att_names64 : att_names32)[rbase]);
11936           if (ins->has_sib)
11937             {
11938               /* ESP/RSP won't allow index.  If base isn't ESP/RSP,
11939                  print index to tell base + index from base.  */
11940               if (scale != 0
11941                   || needindex
11942                   || indexes
11943                   || (havebase && base != ESP_REG_NUM))
11944                 {
11945                   if (!ins->intel_syntax || havebase)
11946                     oappend_char (ins, ins->separator_char);
11947                   if (indexes)
11948                     {
11949                       if (ins->address_mode == mode_64bit || vindex < 16)
11950                         oappend_register (ins, indexes[vindex]);
11951                       else
11952                         oappend (ins, "(bad)");
11953                     }
11954                   else
11955                     oappend_register (ins,
11956                                       ins->address_mode == mode_64bit
11957                                       && !addr32flag
11958                                       ? att_index64
11959                                       : att_index32);
11960
11961                   oappend_char (ins, ins->scale_char);
11962                   oappend_char_with_style (ins, '0' + (1 << scale),
11963                                            dis_style_immediate);
11964                 }
11965             }
11966           if (ins->intel_syntax
11967               && (disp || ins->modrm.mod != 0 || base == 5))
11968             {
11969               if (!havedisp || (bfd_signed_vma) disp >= 0)
11970                   oappend_char (ins, '+');
11971               if (havedisp)
11972                 print_displacement (ins, disp);
11973               else
11974                 print_operand_value (ins, disp, dis_style_address_offset);
11975             }
11976
11977           oappend_char (ins, ins->close_char);
11978
11979           if (check_gather)
11980             {
11981               /* Both XMM/YMM/ZMM registers must be distinct.  */
11982               int modrm_reg = ins->modrm.reg;
11983
11984               if (ins->rex & REX_R)
11985                 modrm_reg += 8;
11986               if (ins->rex2 & REX_R)
11987                 modrm_reg += 16;
11988               if (vindex == modrm_reg)
11989                 oappend (ins, "/(bad)");
11990             }
11991         }
11992       else if (ins->intel_syntax)
11993         {
11994           if (ins->modrm.mod != 0 || base == 5)
11995             {
11996               if (!ins->active_seg_prefix)
11997                 {
11998                   oappend_register (ins, att_names_seg[ds_reg - es_reg]);
11999                   oappend (ins, ":");
12000                 }
12001               print_operand_value (ins, disp, dis_style_text);
12002             }
12003         }
12004     }
12005   else if (bytemode == v_bnd_mode
12006            || bytemode == v_bndmk_mode
12007            || bytemode == bnd_mode
12008            || bytemode == bnd_swap_mode
12009            || bytemode == vex_vsib_d_w_dq_mode
12010            || bytemode == vex_vsib_q_w_dq_mode)
12011     {
12012       oappend (ins, "(bad)");
12013       return true;
12014     }
12015   else
12016     {
12017       /* 16 bit address mode */
12018       bfd_vma disp = 0;
12019
12020       ins->used_prefixes |= ins->prefixes & PREFIX_ADDR;
12021       switch (ins->modrm.mod)
12022         {
12023         case 0:
12024           if (ins->modrm.rm == 6)
12025             {
12026         case 2:
12027               if (!get16s (ins, &disp))
12028                 return false;
12029             }
12030           break;
12031         case 1:
12032           if (!get8s (ins, &disp))
12033             return false;
12034           if (ins->vex.evex && shift > 0)
12035             disp <<= shift;
12036           break;
12037         }
12038
12039       if (!ins->intel_syntax)
12040         if (ins->modrm.mod != 0 || ins->modrm.rm == 6)
12041           print_displacement (ins, disp);
12042
12043       if (ins->modrm.mod != 0 || ins->modrm.rm != 6)
12044         {
12045           oappend_char (ins, ins->open_char);
12046           oappend (ins, ins->intel_syntax ? intel_index16[ins->modrm.rm]
12047                                           : att_index16[ins->modrm.rm]);
12048           if (ins->intel_syntax
12049               && (disp || ins->modrm.mod != 0 || ins->modrm.rm == 6))
12050             {
12051               if ((bfd_signed_vma) disp >= 0)
12052                 oappend_char (ins, '+');
12053               print_displacement (ins, disp);
12054             }
12055
12056           oappend_char (ins, ins->close_char);
12057         }
12058       else if (ins->intel_syntax)
12059         {
12060           if (!ins->active_seg_prefix)
12061             {
12062               oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12063               oappend (ins, ":");
12064             }
12065           print_operand_value (ins, disp & 0xffff, dis_style_text);
12066         }
12067     }
12068   if (ins->vex.b && ins->evex_type == evex_default)
12069     {
12070       ins->evex_used |= EVEX_b_used;
12071
12072       /* Broadcast can only ever be valid for memory sources.  */
12073       if (ins->obufp == ins->op_out[0])
12074         ins->vex.no_broadcast = true;
12075
12076       if (!ins->vex.no_broadcast
12077           && (!ins->intel_syntax || !(ins->evex_used & EVEX_len_used)))
12078         {
12079           if (bytemode == xh_mode)
12080             {
12081               switch (ins->vex.length)
12082                 {
12083                 case 128:
12084                   oappend (ins, "{1to8}");
12085                   break;
12086                 case 256:
12087                   oappend (ins, "{1to16}");
12088                   break;
12089                 case 512:
12090                   oappend (ins, "{1to32}");
12091                   break;
12092                 default:
12093                   abort ();
12094                 }
12095             }
12096           else if (bytemode == q_mode
12097                    || bytemode == ymmq_mode)
12098             ins->vex.no_broadcast = true;
12099           else if (ins->vex.w
12100                    || bytemode == evex_half_bcst_xmmqdh_mode
12101                    || bytemode == evex_half_bcst_xmmq_mode)
12102             {
12103               switch (ins->vex.length)
12104                 {
12105                 case 128:
12106                   oappend (ins, "{1to2}");
12107                   break;
12108                 case 256:
12109                   oappend (ins, "{1to4}");
12110                   break;
12111                 case 512:
12112                   oappend (ins, "{1to8}");
12113                   break;
12114                 default:
12115                   abort ();
12116                 }
12117             }
12118           else if (bytemode == x_mode
12119                    || bytemode == evex_half_bcst_xmmqh_mode)
12120             {
12121               switch (ins->vex.length)
12122                 {
12123                 case 128:
12124                   oappend (ins, "{1to4}");
12125                   break;
12126                 case 256:
12127                   oappend (ins, "{1to8}");
12128                   break;
12129                 case 512:
12130                   oappend (ins, "{1to16}");
12131                   break;
12132                 default:
12133                   abort ();
12134                 }
12135             }
12136           else
12137             ins->vex.no_broadcast = true;
12138         }
12139       if (ins->vex.no_broadcast)
12140         oappend (ins, "{bad}");
12141     }
12142
12143   return true;
12144 }
12145
12146 static bool
12147 OP_E (instr_info *ins, int bytemode, int sizeflag)
12148 {
12149   /* Skip mod/rm byte.  */
12150   MODRM_CHECK;
12151   if (!ins->has_skipped_modrm)
12152     {
12153       ins->codep++;
12154       ins->has_skipped_modrm = true;
12155     }
12156
12157   if (ins->modrm.mod == 3)
12158     {
12159       if ((sizeflag & SUFFIX_ALWAYS)
12160           && (bytemode == b_swap_mode
12161               || bytemode == bnd_swap_mode
12162               || bytemode == v_swap_mode))
12163         swap_operand (ins);
12164
12165       print_register (ins, ins->modrm.rm, REX_B, bytemode, sizeflag);
12166       return true;
12167     }
12168
12169   /* Masking is invalid for insns with GPR-like memory destination. Set the
12170      flag uniformly, as the consumer will inspect it only for the destination
12171      operand.  */
12172   if (ins->vex.mask_register_specifier)
12173     ins->illegal_masking = true;
12174
12175   return OP_E_memory (ins, bytemode, sizeflag);
12176 }
12177
12178 static bool
12179 OP_indirE (instr_info *ins, int bytemode, int sizeflag)
12180 {
12181   if (ins->modrm.mod == 3 && bytemode == f_mode)
12182     /* bad lcall/ljmp */
12183     return BadOp (ins);
12184   if (!ins->intel_syntax)
12185     oappend (ins, "*");
12186   return OP_E (ins, bytemode, sizeflag);
12187 }
12188
12189 static bool
12190 OP_G (instr_info *ins, int bytemode, int sizeflag)
12191 {
12192   print_register (ins, ins->modrm.reg, REX_R, bytemode, sizeflag);
12193   return true;
12194 }
12195
12196 static bool
12197 OP_REG (instr_info *ins, int code, int sizeflag)
12198 {
12199   const char *s;
12200   int add = 0;
12201
12202   switch (code)
12203     {
12204     case es_reg: case ss_reg: case cs_reg:
12205     case ds_reg: case fs_reg: case gs_reg:
12206       oappend_register (ins, att_names_seg[code - es_reg]);
12207       return true;
12208     }
12209
12210   USED_REX (REX_B);
12211   if (ins->rex & REX_B)
12212     add = 8;
12213   if (ins->rex2 & REX_B)
12214     add += 16;
12215
12216   switch (code)
12217     {
12218     case ax_reg: case cx_reg: case dx_reg: case bx_reg:
12219     case sp_reg: case bp_reg: case si_reg: case di_reg:
12220       s = att_names16[code - ax_reg + add];
12221       break;
12222     case ah_reg: case ch_reg: case dh_reg: case bh_reg:
12223       USED_REX (0);
12224       /* Fall through.  */
12225     case al_reg: case cl_reg: case dl_reg: case bl_reg:
12226       if (ins->rex)
12227         s = att_names8rex[code - al_reg + add];
12228       else
12229         s = att_names8[code - al_reg];
12230       break;
12231     case rAX_reg: case rCX_reg: case rDX_reg: case rBX_reg:
12232     case rSP_reg: case rBP_reg: case rSI_reg: case rDI_reg:
12233       if (ins->address_mode == mode_64bit
12234           && ((sizeflag & DFLAG) || (ins->rex & REX_W)))
12235         {
12236           s = att_names64[code - rAX_reg + add];
12237           break;
12238         }
12239       code += eAX_reg - rAX_reg;
12240       /* Fall through.  */
12241     case eAX_reg: case eCX_reg: case eDX_reg: case eBX_reg:
12242     case eSP_reg: case eBP_reg: case eSI_reg: case eDI_reg:
12243       USED_REX (REX_W);
12244       if (ins->rex & REX_W)
12245         s = att_names64[code - eAX_reg + add];
12246       else
12247         {
12248           if (sizeflag & DFLAG)
12249             s = att_names32[code - eAX_reg + add];
12250           else
12251             s = att_names16[code - eAX_reg + add];
12252           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12253         }
12254       break;
12255     default:
12256       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12257       return true;
12258     }
12259   oappend_register (ins, s);
12260   return true;
12261 }
12262
12263 static bool
12264 OP_IMREG (instr_info *ins, int code, int sizeflag)
12265 {
12266   const char *s;
12267
12268   switch (code)
12269     {
12270     case indir_dx_reg:
12271       if (!ins->intel_syntax)
12272         {
12273           oappend (ins, "(%dx)");
12274           return true;
12275         }
12276       s = att_names16[dx_reg - ax_reg];
12277       break;
12278     case al_reg: case cl_reg:
12279       s = att_names8[code - al_reg];
12280       break;
12281     case eAX_reg:
12282       USED_REX (REX_W);
12283       if (ins->rex & REX_W)
12284         {
12285           s = *att_names64;
12286           break;
12287         }
12288       /* Fall through.  */
12289     case z_mode_ax_reg:
12290       if ((ins->rex & REX_W) || (sizeflag & DFLAG))
12291         s = *att_names32;
12292       else
12293         s = *att_names16;
12294       if (!(ins->rex & REX_W))
12295         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12296       break;
12297     default:
12298       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12299       return true;
12300     }
12301   oappend_register (ins, s);
12302   return true;
12303 }
12304
12305 static bool
12306 OP_I (instr_info *ins, int bytemode, int sizeflag)
12307 {
12308   bfd_vma op;
12309
12310   switch (bytemode)
12311     {
12312     case b_mode:
12313       if (!fetch_code (ins->info, ins->codep + 1))
12314         return false;
12315       op = *ins->codep++;
12316       break;
12317     case v_mode:
12318       USED_REX (REX_W);
12319       if (ins->rex & REX_W)
12320         {
12321           if (!get32s (ins, &op))
12322             return false;
12323         }
12324       else
12325         {
12326           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12327           if (sizeflag & DFLAG)
12328             {
12329     case d_mode:
12330               if (!get32 (ins, &op))
12331                 return false;
12332             }
12333           else
12334             {
12335               /* Fall through.  */
12336     case w_mode:
12337               if (!get16 (ins, &op))
12338                 return false;
12339             }
12340         }
12341       break;
12342     case const_1_mode:
12343       if (ins->intel_syntax)
12344         oappend (ins, "1");
12345       else
12346         oappend (ins, "$1");
12347       return true;
12348     default:
12349       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12350       return true;
12351     }
12352
12353   oappend_immediate (ins, op);
12354   return true;
12355 }
12356
12357 static bool
12358 OP_I64 (instr_info *ins, int bytemode, int sizeflag)
12359 {
12360   uint64_t op;
12361
12362   if (bytemode != v_mode || ins->address_mode != mode_64bit
12363       || !(ins->rex & REX_W))
12364     return OP_I (ins, bytemode, sizeflag);
12365
12366   USED_REX (REX_W);
12367
12368   if (!get64 (ins, &op))
12369     return false;
12370
12371   oappend_immediate (ins, op);
12372   return true;
12373 }
12374
12375 static bool
12376 OP_sI (instr_info *ins, int bytemode, int sizeflag)
12377 {
12378   bfd_vma op;
12379
12380   switch (bytemode)
12381     {
12382     case b_mode:
12383     case b_T_mode:
12384       if (!get8s (ins, &op))
12385         return false;
12386       if (bytemode == b_T_mode)
12387         {
12388           if (ins->address_mode != mode_64bit
12389               || !((sizeflag & DFLAG) || (ins->rex & REX_W)))
12390             {
12391               /* The operand-size prefix is overridden by a REX prefix.  */
12392               if ((sizeflag & DFLAG) || (ins->rex & REX_W))
12393                 op &= 0xffffffff;
12394               else
12395                 op &= 0xffff;
12396           }
12397         }
12398       else
12399         {
12400           if (!(ins->rex & REX_W))
12401             {
12402               if (sizeflag & DFLAG)
12403                 op &= 0xffffffff;
12404               else
12405                 op &= 0xffff;
12406             }
12407         }
12408       break;
12409     case v_mode:
12410       /* The operand-size prefix is overridden by a REX prefix.  */
12411       if (!(sizeflag & DFLAG) && !(ins->rex & REX_W))
12412         {
12413           if (!get16 (ins, &op))
12414             return false;
12415         }
12416       else if (!get32s (ins, &op))
12417         return false;
12418       break;
12419     default:
12420       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12421       return true;
12422     }
12423
12424   oappend_immediate (ins, op);
12425   return true;
12426 }
12427
12428 static bool
12429 OP_J (instr_info *ins, int bytemode, int sizeflag)
12430 {
12431   bfd_vma disp;
12432   bfd_vma mask = -1;
12433   bfd_vma segment = 0;
12434
12435   switch (bytemode)
12436     {
12437     case b_mode:
12438       if (!get8s (ins, &disp))
12439         return false;
12440       break;
12441     case v_mode:
12442     case dqw_mode:
12443       if ((sizeflag & DFLAG)
12444           || (ins->address_mode == mode_64bit
12445               && ((ins->isa64 == intel64 && bytemode != dqw_mode)
12446                   || (ins->rex & REX_W))))
12447         {
12448           if (!get32s (ins, &disp))
12449             return false;
12450         }
12451       else
12452         {
12453           if (!get16s (ins, &disp))
12454             return false;
12455           /* In 16bit mode, address is wrapped around at 64k within
12456              the same segment.  Otherwise, a data16 prefix on a jump
12457              instruction means that the pc is masked to 16 bits after
12458              the displacement is added!  */
12459           mask = 0xffff;
12460           if ((ins->prefixes & PREFIX_DATA) == 0)
12461             segment = ((ins->start_pc + (ins->codep - ins->start_codep))
12462                        & ~((bfd_vma) 0xffff));
12463         }
12464       if (ins->address_mode != mode_64bit
12465           || (ins->isa64 != intel64 && !(ins->rex & REX_W)))
12466         ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12467       break;
12468     default:
12469       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
12470       return true;
12471     }
12472   disp = ((ins->start_pc + (ins->codep - ins->start_codep) + disp) & mask)
12473          | segment;
12474   set_op (ins, disp, false);
12475   print_operand_value (ins, disp, dis_style_text);
12476   return true;
12477 }
12478
12479 static bool
12480 OP_SEG (instr_info *ins, int bytemode, int sizeflag)
12481 {
12482   if (bytemode == w_mode)
12483     {
12484       oappend_register (ins, att_names_seg[ins->modrm.reg]);
12485       return true;
12486     }
12487   return OP_E (ins, ins->modrm.mod == 3 ? bytemode : w_mode, sizeflag);
12488 }
12489
12490 static bool
12491 OP_DIR (instr_info *ins, int dummy ATTRIBUTE_UNUSED, int sizeflag)
12492 {
12493   bfd_vma seg, offset;
12494   int res;
12495   char scratch[24];
12496
12497   if (sizeflag & DFLAG)
12498     {
12499       if (!get32 (ins, &offset))
12500         return false;;
12501     }
12502   else if (!get16 (ins, &offset))
12503     return false;
12504   if (!get16 (ins, &seg))
12505     return false;;
12506   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12507
12508   res = snprintf (scratch, ARRAY_SIZE (scratch),
12509                   ins->intel_syntax ? "0x%x:0x%x" : "$0x%x,$0x%x",
12510                   (unsigned) seg, (unsigned) offset);
12511   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12512     abort ();
12513   oappend (ins, scratch);
12514   return true;
12515 }
12516
12517 static bool
12518 OP_OFF (instr_info *ins, int bytemode, int sizeflag)
12519 {
12520   bfd_vma off;
12521
12522   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12523     intel_operand_size (ins, bytemode, sizeflag);
12524   append_seg (ins);
12525
12526   if ((sizeflag & AFLAG) || ins->address_mode == mode_64bit)
12527     {
12528       if (!get32 (ins, &off))
12529         return false;
12530     }
12531   else
12532     {
12533       if (!get16 (ins, &off))
12534         return false;
12535     }
12536
12537   if (ins->intel_syntax)
12538     {
12539       if (!ins->active_seg_prefix)
12540         {
12541           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12542           oappend (ins, ":");
12543         }
12544     }
12545   print_operand_value (ins, off, dis_style_address_offset);
12546   return true;
12547 }
12548
12549 static bool
12550 OP_OFF64 (instr_info *ins, int bytemode, int sizeflag)
12551 {
12552   uint64_t off;
12553
12554   if (ins->address_mode != mode_64bit
12555       || (ins->prefixes & PREFIX_ADDR))
12556     return OP_OFF (ins, bytemode, sizeflag);
12557
12558   if (ins->intel_syntax && (sizeflag & SUFFIX_ALWAYS))
12559     intel_operand_size (ins, bytemode, sizeflag);
12560   append_seg (ins);
12561
12562   if (!get64 (ins, &off))
12563     return false;
12564
12565   if (ins->intel_syntax)
12566     {
12567       if (!ins->active_seg_prefix)
12568         {
12569           oappend_register (ins, att_names_seg[ds_reg - es_reg]);
12570           oappend (ins, ":");
12571         }
12572     }
12573   print_operand_value (ins, off, dis_style_address_offset);
12574   return true;
12575 }
12576
12577 static void
12578 ptr_reg (instr_info *ins, int code, int sizeflag)
12579 {
12580   const char *s;
12581
12582   *ins->obufp++ = ins->open_char;
12583   ins->used_prefixes |= (ins->prefixes & PREFIX_ADDR);
12584   if (ins->address_mode == mode_64bit)
12585     {
12586       if (!(sizeflag & AFLAG))
12587         s = att_names32[code - eAX_reg];
12588       else
12589         s = att_names64[code - eAX_reg];
12590     }
12591   else if (sizeflag & AFLAG)
12592     s = att_names32[code - eAX_reg];
12593   else
12594     s = att_names16[code - eAX_reg];
12595   oappend_register (ins, s);
12596   oappend_char (ins, ins->close_char);
12597 }
12598
12599 static bool
12600 OP_ESreg (instr_info *ins, int code, int sizeflag)
12601 {
12602   if (ins->intel_syntax)
12603     {
12604       switch (ins->codep[-1])
12605         {
12606         case 0x6d:      /* insw/insl */
12607           intel_operand_size (ins, z_mode, sizeflag);
12608           break;
12609         case 0xa5:      /* movsw/movsl/movsq */
12610         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12611         case 0xab:      /* stosw/stosl */
12612         case 0xaf:      /* scasw/scasl */
12613           intel_operand_size (ins, v_mode, sizeflag);
12614           break;
12615         default:
12616           intel_operand_size (ins, b_mode, sizeflag);
12617         }
12618     }
12619   oappend_register (ins, att_names_seg[0]);
12620   oappend_char (ins, ':');
12621   ptr_reg (ins, code, sizeflag);
12622   return true;
12623 }
12624
12625 static bool
12626 OP_DSreg (instr_info *ins, int code, int sizeflag)
12627 {
12628   if (ins->intel_syntax)
12629     {
12630       switch (ins->codep[-1])
12631         {
12632         case 0x6f:      /* outsw/outsl */
12633           intel_operand_size (ins, z_mode, sizeflag);
12634           break;
12635         case 0xa5:      /* movsw/movsl/movsq */
12636         case 0xa7:      /* cmpsw/cmpsl/cmpsq */
12637         case 0xad:      /* lodsw/lodsl/lodsq */
12638           intel_operand_size (ins, v_mode, sizeflag);
12639           break;
12640         default:
12641           intel_operand_size (ins, b_mode, sizeflag);
12642         }
12643     }
12644   /* Set ins->active_seg_prefix to PREFIX_DS if it is unset so that the
12645      default segment register DS is printed.  */
12646   if (!ins->active_seg_prefix)
12647     ins->active_seg_prefix = PREFIX_DS;
12648   append_seg (ins);
12649   ptr_reg (ins, code, sizeflag);
12650   return true;
12651 }
12652
12653 static bool
12654 OP_C (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12655       int sizeflag ATTRIBUTE_UNUSED)
12656 {
12657   int add, res;
12658   char scratch[8];
12659
12660   if (ins->rex & REX_R)
12661     {
12662       USED_REX (REX_R);
12663       add = 8;
12664     }
12665   else if (ins->address_mode != mode_64bit && (ins->prefixes & PREFIX_LOCK))
12666     {
12667       ins->all_prefixes[ins->last_lock_prefix] = 0;
12668       ins->used_prefixes |= PREFIX_LOCK;
12669       add = 8;
12670     }
12671   else
12672     add = 0;
12673   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%cr%d",
12674                   ins->modrm.reg + add);
12675   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12676     abort ();
12677   oappend_register (ins, scratch);
12678   return true;
12679 }
12680
12681 static bool
12682 OP_D (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12683       int sizeflag ATTRIBUTE_UNUSED)
12684 {
12685   int add, res;
12686   char scratch[8];
12687
12688   USED_REX (REX_R);
12689   if (ins->rex & REX_R)
12690     add = 8;
12691   else
12692     add = 0;
12693   res = snprintf (scratch, ARRAY_SIZE (scratch),
12694                   ins->intel_syntax ? "dr%d" : "%%db%d",
12695                   ins->modrm.reg + add);
12696   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12697     abort ();
12698   oappend (ins, scratch);
12699   return true;
12700 }
12701
12702 static bool
12703 OP_T (instr_info *ins, int dummy ATTRIBUTE_UNUSED,
12704       int sizeflag ATTRIBUTE_UNUSED)
12705 {
12706   int res;
12707   char scratch[8];
12708
12709   res = snprintf (scratch, ARRAY_SIZE (scratch), "%%tr%d", ins->modrm.reg);
12710   if (res < 0 || (size_t) res >= ARRAY_SIZE (scratch))
12711     abort ();
12712   oappend_register (ins, scratch);
12713   return true;
12714 }
12715
12716 static bool
12717 OP_MMX (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12718         int sizeflag ATTRIBUTE_UNUSED)
12719 {
12720   int reg = ins->modrm.reg;
12721   const char (*names)[8];
12722
12723   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12724   if (ins->prefixes & PREFIX_DATA)
12725     {
12726       names = att_names_xmm;
12727       USED_REX (REX_R);
12728       if (ins->rex & REX_R)
12729         reg += 8;
12730     }
12731   else
12732     names = att_names_mm;
12733   oappend_register (ins, names[reg]);
12734   return true;
12735 }
12736
12737 static void
12738 print_vector_reg (instr_info *ins, unsigned int reg, int bytemode)
12739 {
12740   const char (*names)[8];
12741
12742   if (bytemode == xmmq_mode
12743       || bytemode == evex_half_bcst_xmmqh_mode
12744       || bytemode == evex_half_bcst_xmmq_mode)
12745     {
12746       switch (ins->vex.length)
12747         {
12748         case 0:
12749         case 128:
12750         case 256:
12751           names = att_names_xmm;
12752           break;
12753         case 512:
12754           names = att_names_ymm;
12755           ins->evex_used |= EVEX_len_used;
12756           break;
12757         default:
12758           abort ();
12759         }
12760     }
12761   else if (bytemode == ymm_mode)
12762     names = att_names_ymm;
12763   else if (bytemode == tmm_mode)
12764     {
12765       if (reg >= 8)
12766         {
12767           oappend (ins, "(bad)");
12768           return;
12769         }
12770       names = att_names_tmm;
12771     }
12772   else if (ins->need_vex
12773            && bytemode != xmm_mode
12774            && bytemode != scalar_mode
12775            && bytemode != xmmdw_mode
12776            && bytemode != xmmqd_mode
12777            && bytemode != evex_half_bcst_xmmqdh_mode
12778            && bytemode != w_swap_mode
12779            && bytemode != b_mode
12780            && bytemode != w_mode
12781            && bytemode != d_mode
12782            && bytemode != q_mode)
12783     {
12784       ins->evex_used |= EVEX_len_used;
12785       switch (ins->vex.length)
12786         {
12787         case 128:
12788           names = att_names_xmm;
12789           break;
12790         case 256:
12791           if (ins->vex.w
12792               || bytemode != vex_vsib_q_w_dq_mode)
12793             names = att_names_ymm;
12794           else
12795             names = att_names_xmm;
12796           break;
12797         case 512:
12798           if (ins->vex.w
12799               || bytemode != vex_vsib_q_w_dq_mode)
12800             names = att_names_zmm;
12801           else
12802             names = att_names_ymm;
12803           break;
12804         default:
12805           abort ();
12806         }
12807     }
12808   else
12809     names = att_names_xmm;
12810   oappend_register (ins, names[reg]);
12811 }
12812
12813 static bool
12814 OP_XMM (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
12815 {
12816   unsigned int reg = ins->modrm.reg;
12817
12818   USED_REX (REX_R);
12819   if (ins->rex & REX_R)
12820     reg += 8;
12821   if (ins->vex.evex)
12822     {
12823       if (ins->rex2 & REX_R)
12824         reg += 16;
12825     }
12826
12827   if (bytemode == tmm_mode)
12828     ins->modrm.reg = reg;
12829   else if (bytemode == scalar_mode)
12830     ins->vex.no_broadcast = true;
12831
12832   print_vector_reg (ins, reg, bytemode);
12833   return true;
12834 }
12835
12836 static bool
12837 OP_EM (instr_info *ins, int bytemode, int sizeflag)
12838 {
12839   int reg;
12840   const char (*names)[8];
12841
12842   if (ins->modrm.mod != 3)
12843     {
12844       if (ins->intel_syntax
12845           && (bytemode == v_mode || bytemode == v_swap_mode))
12846         {
12847           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12848           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12849         }
12850       return OP_E (ins, bytemode, sizeflag);
12851     }
12852
12853   if ((sizeflag & SUFFIX_ALWAYS) && bytemode == v_swap_mode)
12854     swap_operand (ins);
12855
12856   /* Skip mod/rm byte.  */
12857   MODRM_CHECK;
12858   ins->codep++;
12859   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12860   reg = ins->modrm.rm;
12861   if (ins->prefixes & PREFIX_DATA)
12862     {
12863       names = att_names_xmm;
12864       USED_REX (REX_B);
12865       if (ins->rex & REX_B)
12866         reg += 8;
12867     }
12868   else
12869     names = att_names_mm;
12870   oappend_register (ins, names[reg]);
12871   return true;
12872 }
12873
12874 /* cvt* are the only instructions in sse2 which have
12875    both SSE and MMX operands and also have 0x66 prefix
12876    in their opcode. 0x66 was originally used to differentiate
12877    between SSE and MMX instruction(operands). So we have to handle the
12878    cvt* separately using OP_EMC and OP_MXC */
12879 static bool
12880 OP_EMC (instr_info *ins, int bytemode, int sizeflag)
12881 {
12882   if (ins->modrm.mod != 3)
12883     {
12884       if (ins->intel_syntax && bytemode == v_mode)
12885         {
12886           bytemode = (ins->prefixes & PREFIX_DATA) ? x_mode : q_mode;
12887           ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12888         }
12889       return OP_E (ins, bytemode, sizeflag);
12890     }
12891
12892   /* Skip mod/rm byte.  */
12893   MODRM_CHECK;
12894   ins->codep++;
12895   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12896   oappend_register (ins, att_names_mm[ins->modrm.rm]);
12897   return true;
12898 }
12899
12900 static bool
12901 OP_MXC (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
12902         int sizeflag ATTRIBUTE_UNUSED)
12903 {
12904   ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
12905   oappend_register (ins, att_names_mm[ins->modrm.reg]);
12906   return true;
12907 }
12908
12909 static bool
12910 OP_EX (instr_info *ins, int bytemode, int sizeflag)
12911 {
12912   int reg;
12913
12914   /* Skip mod/rm byte.  */
12915   MODRM_CHECK;
12916   ins->codep++;
12917
12918   if (bytemode == dq_mode)
12919     bytemode = ins->vex.w ? q_mode : d_mode;
12920
12921   if (ins->modrm.mod != 3)
12922     return OP_E_memory (ins, bytemode, sizeflag);
12923
12924   reg = ins->modrm.rm;
12925   USED_REX (REX_B);
12926   if (ins->rex & REX_B)
12927     reg += 8;
12928   if (ins->rex2 & REX_B)
12929     reg += 16;
12930   if (ins->vex.evex)
12931     {
12932       USED_REX (REX_X);
12933       if ((ins->rex & REX_X))
12934         reg += 16;
12935     }
12936
12937   if ((sizeflag & SUFFIX_ALWAYS)
12938       && (bytemode == x_swap_mode
12939           || bytemode == w_swap_mode
12940           || bytemode == d_swap_mode
12941           || bytemode == q_swap_mode))
12942     swap_operand (ins);
12943
12944   if (bytemode == tmm_mode)
12945     ins->modrm.rm = reg;
12946
12947   print_vector_reg (ins, reg, bytemode);
12948   return true;
12949 }
12950
12951 static bool
12952 OP_R (instr_info *ins, int bytemode, int sizeflag)
12953 {
12954   if (ins->modrm.mod != 3)
12955     return BadOp (ins);
12956
12957   switch (bytemode)
12958     {
12959     case d_mode:
12960     case dq_mode:
12961     case q_mode:
12962     case mask_mode:
12963       return OP_E (ins, bytemode, sizeflag);
12964     case q_mm_mode:
12965       return OP_EM (ins, x_mode, sizeflag);
12966     case xmm_mode:
12967       if (ins->vex.length <= 128)
12968         break;
12969       return BadOp (ins);
12970     }
12971
12972   return OP_EX (ins, bytemode, sizeflag);
12973 }
12974
12975 static bool
12976 OP_M (instr_info *ins, int bytemode, int sizeflag)
12977 {
12978   /* Skip mod/rm byte.  */
12979   MODRM_CHECK;
12980   ins->codep++;
12981
12982   if (ins->modrm.mod == 3)
12983     /* bad bound,lea,lds,les,lfs,lgs,lss,cmpxchg8b,vmptrst modrm */
12984     return BadOp (ins);
12985
12986   if (bytemode == x_mode)
12987     ins->vex.no_broadcast = true;
12988
12989   return OP_E_memory (ins, bytemode, sizeflag);
12990 }
12991
12992 static bool
12993 OP_0f07 (instr_info *ins, int bytemode, int sizeflag)
12994 {
12995   if (ins->modrm.mod != 3 || ins->modrm.rm != 0)
12996     return BadOp (ins);
12997   return OP_E (ins, bytemode, sizeflag);
12998 }
12999
13000 /* NOP is an alias of "xchg %ax,%ax" in 16bit mode, "xchg %eax,%eax" in
13001    32bit mode and "xchg %rax,%rax" in 64bit mode.  */
13002
13003 static bool
13004 NOP_Fixup (instr_info *ins, int opnd, int sizeflag)
13005 {
13006   if ((ins->prefixes & PREFIX_DATA) == 0 && (ins->rex & REX_B) == 0)
13007     {
13008       ins->mnemonicendp = stpcpy (ins->obuf, "nop");
13009       return true;
13010     }
13011   if (opnd == 0)
13012     return OP_REG (ins, eAX_reg, sizeflag);
13013   return OP_IMREG (ins, eAX_reg, sizeflag);
13014 }
13015
13016 static const char *const Suffix3DNow[] = {
13017 /* 00 */        NULL,           NULL,           NULL,           NULL,
13018 /* 04 */        NULL,           NULL,           NULL,           NULL,
13019 /* 08 */        NULL,           NULL,           NULL,           NULL,
13020 /* 0C */        "pi2fw",        "pi2fd",        NULL,           NULL,
13021 /* 10 */        NULL,           NULL,           NULL,           NULL,
13022 /* 14 */        NULL,           NULL,           NULL,           NULL,
13023 /* 18 */        NULL,           NULL,           NULL,           NULL,
13024 /* 1C */        "pf2iw",        "pf2id",        NULL,           NULL,
13025 /* 20 */        NULL,           NULL,           NULL,           NULL,
13026 /* 24 */        NULL,           NULL,           NULL,           NULL,
13027 /* 28 */        NULL,           NULL,           NULL,           NULL,
13028 /* 2C */        NULL,           NULL,           NULL,           NULL,
13029 /* 30 */        NULL,           NULL,           NULL,           NULL,
13030 /* 34 */        NULL,           NULL,           NULL,           NULL,
13031 /* 38 */        NULL,           NULL,           NULL,           NULL,
13032 /* 3C */        NULL,           NULL,           NULL,           NULL,
13033 /* 40 */        NULL,           NULL,           NULL,           NULL,
13034 /* 44 */        NULL,           NULL,           NULL,           NULL,
13035 /* 48 */        NULL,           NULL,           NULL,           NULL,
13036 /* 4C */        NULL,           NULL,           NULL,           NULL,
13037 /* 50 */        NULL,           NULL,           NULL,           NULL,
13038 /* 54 */        NULL,           NULL,           NULL,           NULL,
13039 /* 58 */        NULL,           NULL,           NULL,           NULL,
13040 /* 5C */        NULL,           NULL,           NULL,           NULL,
13041 /* 60 */        NULL,           NULL,           NULL,           NULL,
13042 /* 64 */        NULL,           NULL,           NULL,           NULL,
13043 /* 68 */        NULL,           NULL,           NULL,           NULL,
13044 /* 6C */        NULL,           NULL,           NULL,           NULL,
13045 /* 70 */        NULL,           NULL,           NULL,           NULL,
13046 /* 74 */        NULL,           NULL,           NULL,           NULL,
13047 /* 78 */        NULL,           NULL,           NULL,           NULL,
13048 /* 7C */        NULL,           NULL,           NULL,           NULL,
13049 /* 80 */        NULL,           NULL,           NULL,           NULL,
13050 /* 84 */        NULL,           NULL,           NULL,           NULL,
13051 /* 88 */        NULL,           NULL,           "pfnacc",       NULL,
13052 /* 8C */        NULL,           NULL,           "pfpnacc",      NULL,
13053 /* 90 */        "pfcmpge",      NULL,           NULL,           NULL,
13054 /* 94 */        "pfmin",        NULL,           "pfrcp",        "pfrsqrt",
13055 /* 98 */        NULL,           NULL,           "pfsub",        NULL,
13056 /* 9C */        NULL,           NULL,           "pfadd",        NULL,
13057 /* A0 */        "pfcmpgt",      NULL,           NULL,           NULL,
13058 /* A4 */        "pfmax",        NULL,           "pfrcpit1",     "pfrsqit1",
13059 /* A8 */        NULL,           NULL,           "pfsubr",       NULL,
13060 /* AC */        NULL,           NULL,           "pfacc",        NULL,
13061 /* B0 */        "pfcmpeq",      NULL,           NULL,           NULL,
13062 /* B4 */        "pfmul",        NULL,           "pfrcpit2",     "pmulhrw",
13063 /* B8 */        NULL,           NULL,           NULL,           "pswapd",
13064 /* BC */        NULL,           NULL,           NULL,           "pavgusb",
13065 /* C0 */        NULL,           NULL,           NULL,           NULL,
13066 /* C4 */        NULL,           NULL,           NULL,           NULL,
13067 /* C8 */        NULL,           NULL,           NULL,           NULL,
13068 /* CC */        NULL,           NULL,           NULL,           NULL,
13069 /* D0 */        NULL,           NULL,           NULL,           NULL,
13070 /* D4 */        NULL,           NULL,           NULL,           NULL,
13071 /* D8 */        NULL,           NULL,           NULL,           NULL,
13072 /* DC */        NULL,           NULL,           NULL,           NULL,
13073 /* E0 */        NULL,           NULL,           NULL,           NULL,
13074 /* E4 */        NULL,           NULL,           NULL,           NULL,
13075 /* E8 */        NULL,           NULL,           NULL,           NULL,
13076 /* EC */        NULL,           NULL,           NULL,           NULL,
13077 /* F0 */        NULL,           NULL,           NULL,           NULL,
13078 /* F4 */        NULL,           NULL,           NULL,           NULL,
13079 /* F8 */        NULL,           NULL,           NULL,           NULL,
13080 /* FC */        NULL,           NULL,           NULL,           NULL,
13081 };
13082
13083 static bool
13084 OP_3DNowSuffix (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13085                 int sizeflag ATTRIBUTE_UNUSED)
13086 {
13087   const char *mnemonic;
13088
13089   if (!fetch_code (ins->info, ins->codep + 1))
13090     return false;
13091   /* AMD 3DNow! instructions are specified by an opcode suffix in the
13092      place where an 8-bit immediate would normally go.  ie. the last
13093      byte of the instruction.  */
13094   ins->obufp = ins->mnemonicendp;
13095   mnemonic = Suffix3DNow[*ins->codep++];
13096   if (mnemonic)
13097     ins->obufp = stpcpy (ins->obufp, mnemonic);
13098   else
13099     {
13100       /* Since a variable sized ins->modrm/ins->sib chunk is between the start
13101          of the opcode (0x0f0f) and the opcode suffix, we need to do
13102          all the ins->modrm processing first, and don't know until now that
13103          we have a bad opcode.  This necessitates some cleaning up.  */
13104       ins->op_out[0][0] = '\0';
13105       ins->op_out[1][0] = '\0';
13106       BadOp (ins);
13107     }
13108   ins->mnemonicendp = ins->obufp;
13109   return true;
13110 }
13111
13112 static const struct op simd_cmp_op[] =
13113 {
13114   { STRING_COMMA_LEN ("eq") },
13115   { STRING_COMMA_LEN ("lt") },
13116   { STRING_COMMA_LEN ("le") },
13117   { STRING_COMMA_LEN ("unord") },
13118   { STRING_COMMA_LEN ("neq") },
13119   { STRING_COMMA_LEN ("nlt") },
13120   { STRING_COMMA_LEN ("nle") },
13121   { STRING_COMMA_LEN ("ord") }
13122 };
13123
13124 static const struct op vex_cmp_op[] =
13125 {
13126   { STRING_COMMA_LEN ("eq_uq") },
13127   { STRING_COMMA_LEN ("nge") },
13128   { STRING_COMMA_LEN ("ngt") },
13129   { STRING_COMMA_LEN ("false") },
13130   { STRING_COMMA_LEN ("neq_oq") },
13131   { STRING_COMMA_LEN ("ge") },
13132   { STRING_COMMA_LEN ("gt") },
13133   { STRING_COMMA_LEN ("true") },
13134   { STRING_COMMA_LEN ("eq_os") },
13135   { STRING_COMMA_LEN ("lt_oq") },
13136   { STRING_COMMA_LEN ("le_oq") },
13137   { STRING_COMMA_LEN ("unord_s") },
13138   { STRING_COMMA_LEN ("neq_us") },
13139   { STRING_COMMA_LEN ("nlt_uq") },
13140   { STRING_COMMA_LEN ("nle_uq") },
13141   { STRING_COMMA_LEN ("ord_s") },
13142   { STRING_COMMA_LEN ("eq_us") },
13143   { STRING_COMMA_LEN ("nge_uq") },
13144   { STRING_COMMA_LEN ("ngt_uq") },
13145   { STRING_COMMA_LEN ("false_os") },
13146   { STRING_COMMA_LEN ("neq_os") },
13147   { STRING_COMMA_LEN ("ge_oq") },
13148   { STRING_COMMA_LEN ("gt_oq") },
13149   { STRING_COMMA_LEN ("true_us") },
13150 };
13151
13152 static bool
13153 CMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13154            int sizeflag ATTRIBUTE_UNUSED)
13155 {
13156   unsigned int cmp_type;
13157
13158   if (!fetch_code (ins->info, ins->codep + 1))
13159     return false;
13160   cmp_type = *ins->codep++;
13161   if (cmp_type < ARRAY_SIZE (simd_cmp_op))
13162     {
13163       char suffix[3];
13164       char *p = ins->mnemonicendp - 2;
13165       suffix[0] = p[0];
13166       suffix[1] = p[1];
13167       suffix[2] = '\0';
13168       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13169       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13170     }
13171   else if (ins->need_vex
13172            && cmp_type < ARRAY_SIZE (simd_cmp_op) + ARRAY_SIZE (vex_cmp_op))
13173     {
13174       char suffix[3];
13175       char *p = ins->mnemonicendp - 2;
13176       suffix[0] = p[0];
13177       suffix[1] = p[1];
13178       suffix[2] = '\0';
13179       cmp_type -= ARRAY_SIZE (simd_cmp_op);
13180       sprintf (p, "%s%s", vex_cmp_op[cmp_type].name, suffix);
13181       ins->mnemonicendp += vex_cmp_op[cmp_type].len;
13182     }
13183   else
13184     {
13185       /* We have a reserved extension byte.  Output it directly.  */
13186       oappend_immediate (ins, cmp_type);
13187     }
13188   return true;
13189 }
13190
13191 static bool
13192 OP_Mwait (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13193 {
13194   /* mwait %eax,%ecx / mwaitx %eax,%ecx,%ebx  */
13195   if (!ins->intel_syntax)
13196     {
13197       strcpy (ins->op_out[0], att_names32[0] + ins->intel_syntax);
13198       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13199       if (bytemode == eBX_reg)
13200         strcpy (ins->op_out[2], att_names32[3] + ins->intel_syntax);
13201       ins->two_source_ops = true;
13202     }
13203   /* Skip mod/rm byte.  */
13204   MODRM_CHECK;
13205   ins->codep++;
13206   return true;
13207 }
13208
13209 static bool
13210 OP_Monitor (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13211             int sizeflag ATTRIBUTE_UNUSED)
13212 {
13213   /* monitor %{e,r,}ax,%ecx,%edx"  */
13214   if (!ins->intel_syntax)
13215     {
13216       const char (*names)[8] = (ins->address_mode == mode_64bit
13217                                 ? att_names64 : att_names32);
13218
13219       if (ins->prefixes & PREFIX_ADDR)
13220         {
13221           /* Remove "addr16/addr32".  */
13222           ins->all_prefixes[ins->last_addr_prefix] = 0;
13223           names = (ins->address_mode != mode_32bit
13224                    ? att_names32 : att_names16);
13225           ins->used_prefixes |= PREFIX_ADDR;
13226         }
13227       else if (ins->address_mode == mode_16bit)
13228         names = att_names16;
13229       strcpy (ins->op_out[0], names[0] + ins->intel_syntax);
13230       strcpy (ins->op_out[1], att_names32[1] + ins->intel_syntax);
13231       strcpy (ins->op_out[2], att_names32[2] + ins->intel_syntax);
13232       ins->two_source_ops = true;
13233     }
13234   /* Skip mod/rm byte.  */
13235   MODRM_CHECK;
13236   ins->codep++;
13237   return true;
13238 }
13239
13240 static bool
13241 REP_Fixup (instr_info *ins, int bytemode, int sizeflag)
13242 {
13243   /* The 0xf3 prefix should be displayed as "rep" for ins, outs, movs,
13244      lods and stos.  */
13245   if (ins->prefixes & PREFIX_REPZ)
13246     ins->all_prefixes[ins->last_repz_prefix] = REP_PREFIX;
13247
13248   switch (bytemode)
13249     {
13250     case al_reg:
13251     case eAX_reg:
13252     case indir_dx_reg:
13253       return OP_IMREG (ins, bytemode, sizeflag);
13254     case eDI_reg:
13255       return OP_ESreg (ins, bytemode, sizeflag);
13256     case eSI_reg:
13257       return OP_DSreg (ins, bytemode, sizeflag);
13258     default:
13259       abort ();
13260       break;
13261     }
13262   return true;
13263 }
13264
13265 static bool
13266 SEP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13267            int sizeflag ATTRIBUTE_UNUSED)
13268 {
13269   if (ins->isa64 != amd64)
13270     return true;
13271
13272   ins->obufp = ins->obuf;
13273   BadOp (ins);
13274   ins->mnemonicendp = ins->obufp;
13275   ++ins->codep;
13276   return true;
13277 }
13278
13279 /* For BND-prefixed instructions 0xF2 prefix should be displayed as
13280    "bnd".  */
13281
13282 static bool
13283 BND_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13284            int sizeflag ATTRIBUTE_UNUSED)
13285 {
13286   if (ins->prefixes & PREFIX_REPNZ)
13287     ins->all_prefixes[ins->last_repnz_prefix] = BND_PREFIX;
13288   return true;
13289 }
13290
13291 /* For NOTRACK-prefixed instructions, 0x3E prefix should be displayed as
13292    "notrack".  */
13293
13294 static bool
13295 NOTRACK_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13296                int sizeflag ATTRIBUTE_UNUSED)
13297 {
13298   /* Since active_seg_prefix is not set in 64-bit mode, check whether
13299      we've seen a PREFIX_DS.  */
13300   if ((ins->prefixes & PREFIX_DS) != 0
13301       && (ins->address_mode != mode_64bit || ins->last_data_prefix < 0))
13302     {
13303       /* NOTRACK prefix is only valid on indirect branch instructions.
13304          NB: DATA prefix is unsupported for Intel64.  */
13305       ins->active_seg_prefix = 0;
13306       ins->all_prefixes[ins->last_seg_prefix] = NOTRACK_PREFIX;
13307     }
13308   return true;
13309 }
13310
13311 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13312    "xacquire"/"xrelease" for memory operand if there is a LOCK prefix.
13313  */
13314
13315 static bool
13316 HLE_Fixup1 (instr_info *ins, int bytemode, int sizeflag)
13317 {
13318   if (ins->modrm.mod != 3
13319       && (ins->prefixes & PREFIX_LOCK) != 0)
13320     {
13321       if (ins->prefixes & PREFIX_REPZ)
13322         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13323       if (ins->prefixes & PREFIX_REPNZ)
13324         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13325     }
13326
13327   return OP_E (ins, bytemode, sizeflag);
13328 }
13329
13330 /* Similar to OP_E.  But the 0xf2/0xf3 ins->prefixes should be displayed as
13331    "xacquire"/"xrelease" for memory operand.  No check for LOCK prefix.
13332  */
13333
13334 static bool
13335 HLE_Fixup2 (instr_info *ins, int bytemode, int sizeflag)
13336 {
13337   if (ins->modrm.mod != 3)
13338     {
13339       if (ins->prefixes & PREFIX_REPZ)
13340         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13341       if (ins->prefixes & PREFIX_REPNZ)
13342         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13343     }
13344
13345   return OP_E (ins, bytemode, sizeflag);
13346 }
13347
13348 /* Similar to OP_E.  But the 0xf3 prefixes should be displayed as
13349    "xrelease" for memory operand.  No check for LOCK prefix.   */
13350
13351 static bool
13352 HLE_Fixup3 (instr_info *ins, int bytemode, int sizeflag)
13353 {
13354   if (ins->modrm.mod != 3
13355       && ins->last_repz_prefix > ins->last_repnz_prefix
13356       && (ins->prefixes & PREFIX_REPZ) != 0)
13357     ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13358
13359   return OP_E (ins, bytemode, sizeflag);
13360 }
13361
13362 static bool
13363 CMPXCHG8B_Fixup (instr_info *ins, int bytemode, int sizeflag)
13364 {
13365   USED_REX (REX_W);
13366   if (ins->rex & REX_W)
13367     {
13368       /* Change cmpxchg8b to cmpxchg16b.  */
13369       char *p = ins->mnemonicendp - 2;
13370       ins->mnemonicendp = stpcpy (p, "16b");
13371       bytemode = o_mode;
13372     }
13373   else if ((ins->prefixes & PREFIX_LOCK) != 0)
13374     {
13375       if (ins->prefixes & PREFIX_REPZ)
13376         ins->all_prefixes[ins->last_repz_prefix] = XRELEASE_PREFIX;
13377       if (ins->prefixes & PREFIX_REPNZ)
13378         ins->all_prefixes[ins->last_repnz_prefix] = XACQUIRE_PREFIX;
13379     }
13380
13381   return OP_M (ins, bytemode, sizeflag);
13382 }
13383
13384 static bool
13385 XMM_Fixup (instr_info *ins, int reg, int sizeflag ATTRIBUTE_UNUSED)
13386 {
13387   const char (*names)[8] = att_names_xmm;
13388
13389   if (ins->need_vex)
13390     {
13391       switch (ins->vex.length)
13392         {
13393         case 128:
13394           break;
13395         case 256:
13396           names = att_names_ymm;
13397           break;
13398         default:
13399           abort ();
13400         }
13401     }
13402   oappend_register (ins, names[reg]);
13403   return true;
13404 }
13405
13406 static bool
13407 FXSAVE_Fixup (instr_info *ins, int bytemode, int sizeflag)
13408 {
13409   /* Add proper suffix to "fxsave" and "fxrstor".  */
13410   USED_REX (REX_W);
13411   if (ins->rex & REX_W)
13412     {
13413       char *p = ins->mnemonicendp;
13414       *p++ = '6';
13415       *p++ = '4';
13416       *p = '\0';
13417       ins->mnemonicendp = p;
13418     }
13419   return OP_M (ins, bytemode, sizeflag);
13420 }
13421
13422 /* Display the destination register operand for instructions with
13423    VEX. */
13424
13425 static bool
13426 OP_VEX (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13427 {
13428   int reg, modrm_reg, sib_index = -1;
13429   const char (*names)[8];
13430
13431   if (!ins->need_vex)
13432     return true;
13433
13434   if (ins->evex_type == evex_from_legacy)
13435     {
13436       ins->evex_used |= EVEX_b_used;
13437       if (!ins->vex.nd)
13438         return true;
13439     }
13440
13441   reg = ins->vex.register_specifier;
13442   ins->vex.register_specifier = 0;
13443   if (ins->address_mode != mode_64bit)
13444     {
13445       if (ins->vex.evex && !ins->vex.v)
13446         {
13447           oappend (ins, "(bad)");
13448           return true;
13449         }
13450
13451       reg &= 7;
13452     }
13453   else if (ins->vex.evex && !ins->vex.v)
13454     reg += 16;
13455
13456   switch (bytemode)
13457     {
13458     case scalar_mode:
13459       oappend_register (ins, att_names_xmm[reg]);
13460       return true;
13461
13462     case vex_vsib_d_w_dq_mode:
13463     case vex_vsib_q_w_dq_mode:
13464       /* This must be the 3rd operand.  */
13465       if (ins->obufp != ins->op_out[2])
13466         abort ();
13467       if (ins->vex.length == 128
13468           || (bytemode != vex_vsib_d_w_dq_mode
13469               && !ins->vex.w))
13470         oappend_register (ins, att_names_xmm[reg]);
13471       else
13472         oappend_register (ins, att_names_ymm[reg]);
13473
13474       /* All 3 XMM/YMM registers must be distinct.  */
13475       modrm_reg = ins->modrm.reg;
13476       if (ins->rex & REX_R)
13477         modrm_reg += 8;
13478
13479       if (ins->has_sib && ins->modrm.rm == 4)
13480         {
13481           sib_index = ins->sib.index;
13482           if (ins->rex & REX_X)
13483             sib_index += 8;
13484         }
13485
13486       if (reg == modrm_reg || reg == sib_index)
13487         strcpy (ins->obufp, "/(bad)");
13488       if (modrm_reg == sib_index || modrm_reg == reg)
13489         strcat (ins->op_out[0], "/(bad)");
13490       if (sib_index == modrm_reg || sib_index == reg)
13491         strcat (ins->op_out[1], "/(bad)");
13492
13493       return true;
13494
13495     case tmm_mode:
13496       /* All 3 TMM registers must be distinct.  */
13497       if (reg >= 8)
13498         oappend (ins, "(bad)");
13499       else
13500         {
13501           /* This must be the 3rd operand.  */
13502           if (ins->obufp != ins->op_out[2])
13503             abort ();
13504           oappend_register (ins, att_names_tmm[reg]);
13505           if (reg == ins->modrm.reg || reg == ins->modrm.rm)
13506             strcpy (ins->obufp, "/(bad)");
13507         }
13508
13509       if (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg
13510           || ins->modrm.rm == reg)
13511         {
13512           if (ins->modrm.reg <= 8
13513               && (ins->modrm.reg == ins->modrm.rm || ins->modrm.reg == reg))
13514             strcat (ins->op_out[0], "/(bad)");
13515           if (ins->modrm.rm <= 8
13516               && (ins->modrm.rm == ins->modrm.reg || ins->modrm.rm == reg))
13517             strcat (ins->op_out[1], "/(bad)");
13518         }
13519
13520       return true;
13521     }
13522
13523   switch (ins->vex.length)
13524     {
13525     case 128:
13526       switch (bytemode)
13527         {
13528         case x_mode:
13529           names = att_names_xmm;
13530           ins->evex_used |= EVEX_len_used;
13531           break;
13532         case v_mode:
13533         case dq_mode:
13534           if (ins->rex & REX_W)
13535             names = att_names64;
13536           else if (bytemode == v_mode
13537                    && !(sizeflag & DFLAG))
13538             names = att_names16;
13539           else
13540             names = att_names32;
13541           break;
13542         case b_mode:
13543           names = att_names8rex;
13544           break;
13545         case q_mode:
13546           names = att_names64;
13547           break;
13548         case mask_bd_mode:
13549         case mask_mode:
13550           if (reg > 0x7)
13551             {
13552               oappend (ins, "(bad)");
13553               return true;
13554             }
13555           names = att_names_mask;
13556           break;
13557         default:
13558           abort ();
13559           return true;
13560         }
13561       break;
13562     case 256:
13563       switch (bytemode)
13564         {
13565         case x_mode:
13566           names = att_names_ymm;
13567           ins->evex_used |= EVEX_len_used;
13568           break;
13569         case mask_bd_mode:
13570         case mask_mode:
13571           if (reg <= 0x7)
13572             {
13573               names = att_names_mask;
13574               break;
13575             }
13576           /* Fall through.  */
13577         default:
13578           /* See PR binutils/20893 for a reproducer.  */
13579           oappend (ins, "(bad)");
13580           return true;
13581         }
13582       break;
13583     case 512:
13584       names = att_names_zmm;
13585       ins->evex_used |= EVEX_len_used;
13586       break;
13587     default:
13588       abort ();
13589       break;
13590     }
13591   oappend_register (ins, names[reg]);
13592   return true;
13593 }
13594
13595 static bool
13596 OP_VexR (instr_info *ins, int bytemode, int sizeflag)
13597 {
13598   if (ins->modrm.mod == 3)
13599     return OP_VEX (ins, bytemode, sizeflag);
13600   return true;
13601 }
13602
13603 static bool
13604 OP_VexW (instr_info *ins, int bytemode, int sizeflag)
13605 {
13606   OP_VEX (ins, bytemode, sizeflag);
13607
13608   if (ins->vex.w)
13609     {
13610       /* Swap 2nd and 3rd operands.  */
13611       char *tmp = ins->op_out[2];
13612
13613       ins->op_out[2] = ins->op_out[1];
13614       ins->op_out[1] = tmp;
13615     }
13616   return true;
13617 }
13618
13619 static bool
13620 OP_REG_VexI4 (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13621 {
13622   int reg;
13623   const char (*names)[8] = att_names_xmm;
13624
13625   if (!fetch_code (ins->info, ins->codep + 1))
13626     return false;
13627   reg = *ins->codep++;
13628
13629   if (bytemode != x_mode && bytemode != scalar_mode)
13630     abort ();
13631
13632   reg >>= 4;
13633   if (ins->address_mode != mode_64bit)
13634     reg &= 7;
13635
13636   if (bytemode == x_mode && ins->vex.length == 256)
13637     names = att_names_ymm;
13638
13639   oappend_register (ins, names[reg]);
13640
13641   if (ins->vex.w)
13642     {
13643       /* Swap 3rd and 4th operands.  */
13644       char *tmp = ins->op_out[3];
13645
13646       ins->op_out[3] = ins->op_out[2];
13647       ins->op_out[2] = tmp;
13648     }
13649   return true;
13650 }
13651
13652 static bool
13653 OP_VexI4 (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13654           int sizeflag ATTRIBUTE_UNUSED)
13655 {
13656   oappend_immediate (ins, ins->codep[-1] & 0xf);
13657   return true;
13658 }
13659
13660 static bool
13661 VPCMP_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13662              int sizeflag ATTRIBUTE_UNUSED)
13663 {
13664   unsigned int cmp_type;
13665
13666   if (!ins->vex.evex)
13667     abort ();
13668
13669   if (!fetch_code (ins->info, ins->codep + 1))
13670     return false;
13671   cmp_type = *ins->codep++;
13672   /* There are aliases for immediates 0, 1, 2, 4, 5, 6.
13673      If it's the case, print suffix, otherwise - print the immediate.  */
13674   if (cmp_type < ARRAY_SIZE (simd_cmp_op)
13675       && cmp_type != 3
13676       && cmp_type != 7)
13677     {
13678       char suffix[3];
13679       char *p = ins->mnemonicendp - 2;
13680
13681       /* vpcmp* can have both one- and two-lettered suffix.  */
13682       if (p[0] == 'p')
13683         {
13684           p++;
13685           suffix[0] = p[0];
13686           suffix[1] = '\0';
13687         }
13688       else
13689         {
13690           suffix[0] = p[0];
13691           suffix[1] = p[1];
13692           suffix[2] = '\0';
13693         }
13694
13695       sprintf (p, "%s%s", simd_cmp_op[cmp_type].name, suffix);
13696       ins->mnemonicendp += simd_cmp_op[cmp_type].len;
13697     }
13698   else
13699     {
13700       /* We have a reserved extension byte.  Output it directly.  */
13701       oappend_immediate (ins, cmp_type);
13702     }
13703   return true;
13704 }
13705
13706 static const struct op xop_cmp_op[] =
13707 {
13708   { STRING_COMMA_LEN ("lt") },
13709   { STRING_COMMA_LEN ("le") },
13710   { STRING_COMMA_LEN ("gt") },
13711   { STRING_COMMA_LEN ("ge") },
13712   { STRING_COMMA_LEN ("eq") },
13713   { STRING_COMMA_LEN ("neq") },
13714   { STRING_COMMA_LEN ("false") },
13715   { STRING_COMMA_LEN ("true") }
13716 };
13717
13718 static bool
13719 VPCOM_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13720              int sizeflag ATTRIBUTE_UNUSED)
13721 {
13722   unsigned int cmp_type;
13723
13724   if (!fetch_code (ins->info, ins->codep + 1))
13725     return false;
13726   cmp_type = *ins->codep++;
13727   if (cmp_type < ARRAY_SIZE (xop_cmp_op))
13728     {
13729       char suffix[3];
13730       char *p = ins->mnemonicendp - 2;
13731
13732       /* vpcom* can have both one- and two-lettered suffix.  */
13733       if (p[0] == 'm')
13734         {
13735           p++;
13736           suffix[0] = p[0];
13737           suffix[1] = '\0';
13738         }
13739       else
13740         {
13741           suffix[0] = p[0];
13742           suffix[1] = p[1];
13743           suffix[2] = '\0';
13744         }
13745
13746       sprintf (p, "%s%s", xop_cmp_op[cmp_type].name, suffix);
13747       ins->mnemonicendp += xop_cmp_op[cmp_type].len;
13748     }
13749   else
13750     {
13751       /* We have a reserved extension byte.  Output it directly.  */
13752       oappend_immediate (ins, cmp_type);
13753     }
13754   return true;
13755 }
13756
13757 static const struct op pclmul_op[] =
13758 {
13759   { STRING_COMMA_LEN ("lql") },
13760   { STRING_COMMA_LEN ("hql") },
13761   { STRING_COMMA_LEN ("lqh") },
13762   { STRING_COMMA_LEN ("hqh") }
13763 };
13764
13765 static bool
13766 PCLMUL_Fixup (instr_info *ins, int bytemode ATTRIBUTE_UNUSED,
13767               int sizeflag ATTRIBUTE_UNUSED)
13768 {
13769   unsigned int pclmul_type;
13770
13771   if (!fetch_code (ins->info, ins->codep + 1))
13772     return false;
13773   pclmul_type = *ins->codep++;
13774   switch (pclmul_type)
13775     {
13776     case 0x10:
13777       pclmul_type = 2;
13778       break;
13779     case 0x11:
13780       pclmul_type = 3;
13781       break;
13782     default:
13783       break;
13784     }
13785   if (pclmul_type < ARRAY_SIZE (pclmul_op))
13786     {
13787       char suffix[4];
13788       char *p = ins->mnemonicendp - 3;
13789       suffix[0] = p[0];
13790       suffix[1] = p[1];
13791       suffix[2] = p[2];
13792       suffix[3] = '\0';
13793       sprintf (p, "%s%s", pclmul_op[pclmul_type].name, suffix);
13794       ins->mnemonicendp += pclmul_op[pclmul_type].len;
13795     }
13796   else
13797     {
13798       /* We have a reserved extension byte.  Output it directly.  */
13799       oappend_immediate (ins, pclmul_type);
13800     }
13801   return true;
13802 }
13803
13804 static bool
13805 MOVSXD_Fixup (instr_info *ins, int bytemode, int sizeflag)
13806 {
13807   /* Add proper suffix to "movsxd".  */
13808   char *p = ins->mnemonicendp;
13809
13810   switch (bytemode)
13811     {
13812     case movsxd_mode:
13813       if (!ins->intel_syntax)
13814         {
13815           USED_REX (REX_W);
13816           if (ins->rex & REX_W)
13817             {
13818               *p++ = 'l';
13819               *p++ = 'q';
13820               break;
13821             }
13822         }
13823
13824       *p++ = 'x';
13825       *p++ = 'd';
13826       break;
13827     default:
13828       oappend (ins, INTERNAL_DISASSEMBLER_ERROR);
13829       break;
13830     }
13831
13832   ins->mnemonicendp = p;
13833   *p = '\0';
13834   return OP_E (ins, bytemode, sizeflag);
13835 }
13836
13837 static bool
13838 DistinctDest_Fixup (instr_info *ins, int bytemode, int sizeflag)
13839 {
13840   unsigned int reg = ins->vex.register_specifier;
13841   unsigned int modrm_reg = ins->modrm.reg;
13842   unsigned int modrm_rm = ins->modrm.rm;
13843
13844   /* Calc destination register number.  */
13845   if (ins->rex & REX_R)
13846     modrm_reg += 8;
13847   if (ins->rex2 & REX_R)
13848     modrm_reg += 16;
13849
13850   /* Calc src1 register number.  */
13851   if (ins->address_mode != mode_64bit)
13852     reg &= 7;
13853   else if (ins->vex.evex && !ins->vex.v)
13854     reg += 16;
13855
13856   /* Calc src2 register number.  */
13857   if (ins->modrm.mod == 3)
13858     {
13859       if (ins->rex & REX_B)
13860         modrm_rm += 8;
13861       if (ins->rex & REX_X)
13862         modrm_rm += 16;
13863     }
13864
13865   /* Destination and source registers must be distinct, output bad if
13866      dest == src1 or dest == src2.  */
13867   if (modrm_reg == reg
13868       || (ins->modrm.mod == 3
13869           && modrm_reg == modrm_rm))
13870     {
13871       oappend (ins, "(bad)");
13872       return true;
13873     }
13874   return OP_XMM (ins, bytemode, sizeflag);
13875 }
13876
13877 static bool
13878 OP_Rounding (instr_info *ins, int bytemode, int sizeflag ATTRIBUTE_UNUSED)
13879 {
13880   if (ins->modrm.mod != 3 || !ins->vex.b)
13881     return true;
13882
13883   switch (bytemode)
13884     {
13885     case evex_rounding_64_mode:
13886       if (ins->address_mode != mode_64bit || !ins->vex.w)
13887         return true;
13888       /* Fall through.  */
13889     case evex_rounding_mode:
13890       ins->evex_used |= EVEX_b_used;
13891       oappend (ins, names_rounding[ins->vex.ll]);
13892       break;
13893     case evex_sae_mode:
13894       ins->evex_used |= EVEX_b_used;
13895       oappend (ins, "{");
13896       break;
13897     default:
13898       abort ();
13899     }
13900   oappend (ins, "sae}");
13901   return true;
13902 }
13903
13904 static bool
13905 PREFETCHI_Fixup (instr_info *ins, int bytemode, int sizeflag)
13906 {
13907   if (ins->modrm.mod != 0 || ins->modrm.rm != 5)
13908     {
13909       if (ins->intel_syntax)
13910         {
13911           ins->mnemonicendp = stpcpy (ins->obuf, "nop   ");
13912         }
13913       else
13914         {
13915           USED_REX (REX_W);
13916           if (ins->rex & REX_W)
13917             ins->mnemonicendp = stpcpy (ins->obuf, "nopq  ");
13918           else
13919             {
13920               if (sizeflag & DFLAG)
13921                 ins->mnemonicendp = stpcpy (ins->obuf, "nopl  ");
13922               else
13923                 ins->mnemonicendp = stpcpy (ins->obuf, "nopw  ");
13924               ins->used_prefixes |= (ins->prefixes & PREFIX_DATA);
13925             }
13926         }
13927       bytemode = v_mode;
13928     }
13929
13930   return OP_M (ins, bytemode, sizeflag);
13931 }
13932
13933 static bool
13934 PUSH2_POP2_Fixup (instr_info *ins, int bytemode, int sizeflag)
13935 {
13936   if (ins->modrm.mod != 3)
13937     return true;
13938
13939   unsigned int vvvv_reg = ins->vex.register_specifier
13940     | (!ins->vex.v << 4);
13941   unsigned int rm_reg = ins->modrm.rm + (ins->rex & REX_B ? 8 : 0)
13942     + (ins->rex2 & REX_B ? 16 : 0);
13943
13944   /* Push2/Pop2 cannot use RSP and Pop2 cannot pop two same registers.  */
13945   if (!ins->vex.nd || vvvv_reg == 0x4 || rm_reg == 0x4
13946       || (!ins->modrm.reg
13947           && vvvv_reg == rm_reg))
13948     {
13949       oappend (ins, "(bad)");
13950       return true;
13951     }
13952
13953   return OP_VEX (ins, bytemode, sizeflag);
13954 }
13955
13956 static bool
13957 JMPABS_Fixup (instr_info *ins, int bytemode, int sizeflag)
13958 {
13959   if (ins->last_rex2_prefix >= 0)
13960     {
13961       uint64_t op;
13962
13963       if ((ins->prefixes & (PREFIX_OPCODE | PREFIX_ADDR | PREFIX_LOCK)) != 0x0
13964           || (ins->rex & REX_W) != 0x0)
13965         {
13966           oappend (ins, "(bad)");
13967           return true;
13968         }
13969
13970       if (bytemode == eAX_reg)
13971         return true;
13972
13973       if (!get64 (ins, &op))
13974         return false;
13975
13976       ins->mnemonicendp = stpcpy (ins->obuf, "jmpabs");
13977       ins->rex2 |= REX2_SPECIAL;
13978       oappend_immediate (ins, op);
13979
13980       return true;
13981     }
13982
13983   if (bytemode == eAX_reg)
13984     return OP_IMREG (ins, bytemode, sizeflag);
13985   return OP_OFF64 (ins, bytemode, sizeflag);
13986 }