gprofng/common/opteron_pcbe.c

   1 /* Copyright (C) 2021-2024 Free Software Foundation, Inc.
   2    Contributed by Oracle.
   3
   4    This file is part of GNU Binutils.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 /*
  22  * This file contains preset event names from the Performance Application
  23  * Programming Interface v3.5 which included the following notice:
  24  *
  25  *                             Copyright (c) 2005,6
  26  *                           Innovative Computing Labs
  27  *                         Computer Science Department,
  28  *                            University of Tennessee,
  29  *                                 Knoxville, TN.
  30  *                              All Rights Reserved.
  31  *
  32  *
  33  * Redistribution and use in source and binary forms, with or without
  34  * modification, are permitted provided that the following conditions are met:
  35  *
  36  *    * Redistributions of source code must retain the above copyright notice,
  37  *      this list of conditions and the following disclaimer.
  38  *    * Redistributions in binary form must reproduce the above copyright
  39  *      notice, this list of conditions and the following disclaimer in the
  40  *      documentation and/or other materials provided with the distribution.
  41  *    * Neither the name of the University of Tennessee nor the names of its
  42  *      contributors may be used to endorse or promote products derived from
  43  *      this software without specific prior written permission.
  44  *
  45  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  46  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  47  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
  48  * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
  49  * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
  50  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
  51  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
  52  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
  53  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
  54  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  55  * POSSIBILITY OF SUCH DAMAGE.
  56  *
  57  *
  58  * This open source software license conforms to the BSD License template.
  59  */
  60
  61 /*
  62  * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors.
  63  */
  64
  65 #include <sys/types.h>
  66 #include "hwcdrv.h"
  67
  68 #define CPU /* used by cpuid_get*() functions */
  69
  70 typedef struct _amd_event
  71 {
  72   char *name;
  73   uint16_t emask;       /* Event mask setting */
  74   uint8_t umask_valid;  /* Mask of unreserved UNIT_MASK bits */
  75 } amd_event_t;
  76
  77 typedef struct _amd_generic_event
  78 {
  79   char *name;
  80   char *event;
  81   uint8_t umask;
  82 } amd_generic_event_t;
  83
  84 #define EV_END      { NULL, 0, 0 }
  85 #define GEN_EV_END  { NULL, NULL, 0 }
  86
  87 #define AMD_cmn_events       \
  88   { "FP_dispatched_fpu_ops",                            0x00, 0x3F }, \
  89   { "FP_cycles_no_fpu_ops_retired",                     0x01, 0x0 }, \
  90   { "FP_dispatched_fpu_ops_ff",                         0x02, 0x0 }, \
  91   { "LS_seg_reg_load",                                  0x20, 0x7F }, \
  92   { "LS_uarch_resync_self_modify",                      0x21, 0x0 }, \
  93   { "LS_uarch_resync_snoop",                            0x22, 0x0 }, \
  94   { "LS_buffer_2_full",                                 0x23, 0x0 }, \
  95   { "LS_retired_cflush",                                0x26, 0x0 }, \
  96   { "LS_retired_cpuid",                                 0x27, 0x0 }, \
  97   { "DC_access",                                        0x40, 0x0 }, \
  98   { "DC_miss",                                          0x41, 0x0 }, \
  99   { "DC_refill_from_L2",                                0x42, 0x1F }, \
 100   { "DC_refill_from_system",                            0x43, 0x1F }, \
 101   { "DC_misaligned_data_ref",                           0x47, 0x0 }, \
 102   { "DC_uarch_late_cancel_access",                      0x48, 0x0 }, \
 103   { "DC_uarch_early_cancel_access",                     0x49, 0x0 }, \
 104   { "DC_dispatched_prefetch_instr",                     0x4B, 0x7 }, \
 105   { "DC_dcache_accesses_by_locks",                      0x4C, 0x2 }, \
 106   { "BU_memory_requests",                               0x65, 0x83}, \
 107   { "BU_data_prefetch",                                 0x67, 0x3 }, \
 108   { "BU_cpu_clk_unhalted",                              0x76, 0x0 }, \
 109   { "IC_fetch",                                         0x80, 0x0 }, \
 110   { "IC_miss",                                          0x81, 0x0 }, \
 111   { "IC_refill_from_L2",                                0x82, 0x0 }, \
 112   { "IC_refill_from_system",                            0x83, 0x0 }, \
 113   { "IC_itlb_L1_miss_L2_hit",                           0x84, 0x0 }, \
 114   { "IC_uarch_resync_snoop",                            0x86, 0x0 }, \
 115   { "IC_instr_fetch_stall",                             0x87, 0x0 }, \
 116   { "IC_return_stack_hit",                              0x88, 0x0 }, \
 117   { "IC_return_stack_overflow",                         0x89, 0x0 }, \
 118   { "FR_retired_x86_instr_w_excp_intr",                 0xC0, 0x0 }, \
 119   { "FR_retired_uops",                                  0xC1, 0x0 }, \
 120   { "FR_retired_branches_w_excp_intr",                  0xC2, 0x0 }, \
 121   { "FR_retired_branches_mispred",                      0xC3, 0x0 }, \
 122   { "FR_retired_taken_branches",                        0xC4, 0x0 }, \
 123   { "FR_retired_taken_branches_mispred",                0xC5, 0x0 }, \
 124   { "FR_retired_far_ctl_transfer",                      0xC6, 0x0 }, \
 125   { "FR_retired_resyncs",                               0xC7, 0x0 }, \
 126   { "FR_retired_near_rets",                             0xC8, 0x0 }, \
 127   { "FR_retired_near_rets_mispred",                     0xC9, 0x0 }, \
 128   { "FR_retired_taken_branches_mispred_addr_miscomp",   0xCA, 0x0 }, \
 129   { "FR_retired_fastpath_double_op_instr",              0xCC, 0x7 }, \
 130   { "FR_intr_masked_cycles",                            0xCD, 0x0 }, \
 131   { "FR_intr_masked_while_pending_cycles",              0xCE, 0x0 }, \
 132   { "FR_taken_hardware_intrs",                          0xCF, 0x0 }, \
 133   { "FR_nothing_to_dispatch",                           0xD0, 0x0 }, \
 134   { "FR_dispatch_stalls",                               0xD1, 0x0 }, \
 135   { "FR_dispatch_stall_branch_abort_to_retire",         0xD2, 0x0 }, \
 136   { "FR_dispatch_stall_serialization",                  0xD3, 0x0 }, \
 137   { "FR_dispatch_stall_segment_load",                   0xD4, 0x0 }, \
 138   { "FR_dispatch_stall_reorder_buffer_full",            0xD5, 0x0 }, \
 139   { "FR_dispatch_stall_resv_stations_full",             0xD6, 0x0 }, \
 140   { "FR_dispatch_stall_fpu_full",                       0xD7, 0x0 }, \
 141   { "FR_dispatch_stall_ls_full",                        0xD8, 0x0 }, \
 142   { "FR_dispatch_stall_waiting_all_quiet",              0xD9, 0x0 }, \
 143   { "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend", 0xDA, 0x0 },\
 144   { "FR_fpu_exception",                                 0xDB, 0xF }, \
 145   { "FR_num_brkpts_dr0",                                0xDC, 0x0 }, \
 146   { "FR_num_brkpts_dr1",                                0xDD, 0x0 }, \
 147   { "FR_num_brkpts_dr2",                                0xDE, 0x0 }, \
 148   { "FR_num_brkpts_dr3",                                0xDF, 0x0 }, \
 149   { "NB_mem_ctrlr_bypass_counter_saturation",           0xE4, 0xF }
 150
 151 #define OPT_events \
 152   { "LS_locked_operation",                              0x24, 0x7 }, \
 153   { "DC_copyback",                                      0x44, 0x1F }, \
 154   { "DC_dtlb_L1_miss_L2_hit",                           0x45, 0x0 }, \
 155   { "DC_dtlb_L1_miss_L2_miss",                          0x46, 0x0 }, \
 156   { "DC_1bit_ecc_error_found",                          0x4A, 0x3 }, \
 157   { "BU_system_read_responses",                         0x6C, 0x7 }, \
 158   { "BU_quadwords_written_to_system",                   0x6D, 0x1 }, \
 159   { "BU_internal_L2_req",                               0x7D, 0x1F }, \
 160   { "BU_fill_req_missed_L2",                            0x7E, 0x7 }, \
 161   { "BU_fill_into_L2",                                  0x7F, 0x1 }, \
 162   { "IC_itlb_L1_miss_L2_miss",                          0x85, 0x0 }, \
 163   { "FR_retired_fpu_instr",                             0xCB, 0xF }, \
 164   { "NB_mem_ctrlr_page_access",                         0xE0, 0x7 }, \
 165   { "NB_mem_ctrlr_page_table_overflow",                 0xE1, 0x0 }, \
 166   { "NB_mem_ctrlr_turnaround",                          0xE3, 0x7 }, \
 167   { "NB_ECC_errors",                                    0xE8, 0x80}, \
 168   { "NB_sized_commands",                                0xEB, 0x7F }, \
 169   { "NB_probe_result",                                  0xEC, 0x7F}, \
 170   { "NB_gart_events",                                   0xEE, 0x7 }, \
 171   { "NB_ht_bus0_bandwidth",                             0xF6, 0xF }, \
 172   { "NB_ht_bus1_bandwidth",                             0xF7, 0xF }, \
 173   { "NB_ht_bus2_bandwidth",                             0xF8, 0xF }
 174
 175 #define OPT_RevD_events \
 176   { "NB_sized_blocks",                                  0xE5, 0x3C }
 177
 178 #define OPT_RevE_events \
 179   { "NB_cpu_io_to_mem_io",                              0xE9, 0xFF}, \
 180   { "NB_cache_block_commands",                          0xEA, 0x3D}
 181
 182 #define AMD_FAMILY_10h_cmn_events \
 183   { "FP_retired_sse_ops",                               0x3,   0x7F}, \
 184   { "FP_retired_move_ops",                              0x4,   0xF}, \
 185   { "FP_retired_serialize_ops",                         0x5,   0xF}, \
 186   { "FP_serialize_ops_cycles",                          0x6,   0x3}, \
 187   { "DC_copyback",                                      0x44,  0x7F }, \
 188   { "DC_dtlb_L1_miss_L2_hit",                           0x45,  0x3 }, \
 189   { "DC_dtlb_L1_miss_L2_miss",                          0x46,  0x7 }, \
 190   { "DC_1bit_ecc_error_found",                          0x4A,  0xF }, \
 191   { "DC_dtlb_L1_hit",                                   0x4D,  0x7 }, \
 192   { "BU_system_read_responses",                         0x6C,  0x17 }, \
 193   { "BU_octwords_written_to_system",                    0x6D,  0x1 }, \
 194   { "BU_internal_L2_req",                               0x7D,  0x3F }, \
 195   { "BU_fill_req_missed_L2",                            0x7E,  0xF }, \
 196   { "BU_fill_into_L2",                                  0x7F,  0x3 }, \
 197   { "IC_itlb_L1_miss_L2_miss",                          0x85,  0x3 }, \
 198   { "IC_eviction",                                      0x8B,  0x0 }, \
 199   { "IC_cache_lines_invalidate",                        0x8C,  0xF }, \
 200   { "IC_itlb_reload",                                   0x99,  0x0 }, \
 201   { "IC_itlb_reload_aborted",                           0x9A,  0x0 }, \
 202   { "FR_retired_mmx_sse_fp_instr",                      0xCB,  0x7 }, \
 203   { "NB_mem_ctrlr_page_access",                         0xE0,  0xFF }, \
 204   { "NB_mem_ctrlr_page_table_overflow",                 0xE1,  0x3 }, \
 205   { "NB_mem_ctrlr_turnaround",                          0xE3,  0x3F }, \
 206   { "NB_thermal_status",                                0xE8,  0x7C}, \
 207   { "NB_sized_commands",                                0xEB,  0x3F }, \
 208   { "NB_probe_results_upstream_req",                    0xEC,  0xFF}, \
 209   { "NB_gart_events",                                   0xEE,  0xFF }, \
 210   { "NB_ht_bus0_bandwidth",                             0xF6,  0xBF }, \
 211   { "NB_ht_bus1_bandwidth",                             0xF7,  0xBF }, \
 212   { "NB_ht_bus2_bandwidth",                             0xF8,  0xBF }, \
 213   { "NB_ht_bus3_bandwidth",                             0x1F9, 0xBF }, \
 214   { "LS_locked_operation",                              0x24,  0xF }, \
 215   { "LS_cancelled_store_to_load_fwd_ops",               0x2A,  0x7 }, \
 216   { "LS_smi_received",                                  0x2B,  0x0 }, \
 217   { "LS_ineffective_prefetch",                          0x52,  0x9 }, \
 218   { "LS_global_tlb_flush",                              0x54,  0x0 }, \
 219   { "NB_mem_ctrlr_dram_cmd_slots_missed",               0xE2,  0x3 }, \
 220   { "NB_mem_ctrlr_req",                                 0x1F0, 0xFF }, \
 221   { "CB_cpu_to_dram_req_to_target",                     0x1E0, 0xFF }, \
 222   { "CB_io_to_dram_req_to_target",                      0x1E1, 0xFF }, \
 223   { "CB_cpu_read_cmd_latency_to_target_0_to_3",         0x1E2, 0xFF }, \
 224   { "CB_cpu_read_cmd_req_to_target_0_to_3",             0x1E3, 0xFF }, \
 225   { "CB_cpu_read_cmd_latency_to_target_4_to_7",         0x1E4, 0xFF }, \
 226   { "CB_cpu_read_cmd_req_to_target_4_to_7",             0x1E5, 0xFF }, \
 227   { "CB_cpu_cmd_latency_to_target_0_to_7",              0x1E6, 0xFF }, \
 228   { "CB_cpu_req_to_target_0_to_7",                      0x1E7, 0xFF }, \
 229   { "L3_read_req",                                      0x4E0, 0xF7 }, \
 230   { "L3_miss",                                          0x4E1, 0xF7 }, \
 231   { "L3_l2_eviction_l3_fill",                           0x4E2, 0xFF }, \
 232   { "L3_eviction",                                      0x4E3, 0xF  }
 233
 234 #define AMD_cmn_generic_events \
 235   { "PAPI_br_ins", "FR_retired_branches_w_excp_intr",   0x0 },\
 236   { "PAPI_br_msp", "FR_retired_branches_mispred",       0x0 }, \
 237   { "PAPI_br_tkn", "FR_retired_taken_branches",         0x0 }, \
 238   { "PAPI_fp_ops", "FP_dispatched_fpu_ops",             0x3 }, \
 239   { "PAPI_fad_ins", "FP_dispatched_fpu_ops",            0x1 }, \
 240   { "PAPI_fml_ins", "FP_dispatched_fpu_ops",            0x2 }, \
 241   { "PAPI_fpu_idl", "FP_cycles_no_fpu_ops_retired",     0x0 }, \
 242   { "PAPI_tot_cyc", "BU_cpu_clk_unhalted",              0x0 }, \
 243   { "PAPI_tot_ins", "FR_retired_x86_instr_w_excp_intr", 0x0 }, \
 244   { "PAPI_l1_dca", "DC_access",                         0x0 }, \
 245   { "PAPI_l1_dcm", "DC_miss",                           0x0 }, \
 246   { "PAPI_l1_ldm", "DC_refill_from_L2",                 0xe }, \
 247   { "PAPI_l1_stm", "DC_refill_from_L2",                 0x10 }, \
 248   { "PAPI_l1_ica", "IC_fetch",                          0x0 }, \
 249   { "PAPI_l1_icm", "IC_miss",                           0x0 }, \
 250   { "PAPI_l1_icr", "IC_fetch",                          0x0 }, \
 251   { "PAPI_l2_dch", "DC_refill_from_L2",                 0x1e }, \
 252   { "PAPI_l2_dcm", "DC_refill_from_system",             0x1e }, \
 253   { "PAPI_l2_dcr", "DC_refill_from_L2",                 0xe }, \
 254   { "PAPI_l2_dcw", "DC_refill_from_L2",                 0x10 }, \
 255   { "PAPI_l2_ich", "IC_refill_from_L2",                 0x0 }, \
 256   { "PAPI_l2_icm", "IC_refill_from_system",             0x0 }, \
 257   { "PAPI_l2_ldm", "DC_refill_from_system",             0xe }, \
 258   { "PAPI_l2_stm", "DC_refill_from_system",             0x10 }, \
 259   { "PAPI_res_stl", "FR_dispatch_stalls",               0x0 }, \
 260   { "PAPI_stl_icy", "FR_nothing_to_dispatch",           0x0 }, \
 261   { "PAPI_hw_int", "FR_taken_hardware_intrs",           0x0 }
 262
 263 #define OPT_cmn_generic_events \
 264   { "PAPI_tlb_dm", "DC_dtlb_L1_miss_L2_miss",           0x0 }, \
 265   { "PAPI_tlb_im", "IC_itlb_L1_miss_L2_miss",           0x0 }, \
 266   { "PAPI_fp_ins", "FR_retired_fpu_instr",              0xd }, \
 267   { "PAPI_vec_ins", "FR_retired_fpu_instr",             0x4 }
 268
 269 #define AMD_FAMILY_10h_generic_events \
 270   { "PAPI_tlb_dm", "DC_dtlb_L1_miss_L2_miss",           0x7 }, \
 271   { "PAPI_tlb_im", "IC_itlb_L1_miss_L2_miss",           0x3 }, \
 272   { "PAPI_l3_dcr", "L3_read_req",                       0xf1 }, \
 273   { "PAPI_l3_icr", "L3_read_req",                       0xf2 }, \
 274   { "PAPI_l3_tcr", "L3_read_req",                       0xf7 }, \
 275   { "PAPI_l3_stm", "L3_miss",                           0xf4 }, \
 276   { "PAPI_l3_ldm", "L3_miss",                           0xf3 }, \
 277   { "PAPI_l3_tcm", "L3_miss",                           0xf7 }
 278
 279 static amd_event_t opt_events_rev_E[] = {
 280   AMD_cmn_events,
 281   OPT_events,
 282   OPT_RevD_events,
 283   OPT_RevE_events,
 284   EV_END
 285 };
 286
 287 static amd_event_t family_10h_events[] = {
 288   AMD_cmn_events,
 289   OPT_RevE_events,
 290   AMD_FAMILY_10h_cmn_events,
 291   EV_END
 292 };
 293
 294 static amd_generic_event_t opt_generic_events[] = {
 295   AMD_cmn_generic_events,
 296   OPT_cmn_generic_events,
 297   GEN_EV_END
 298 };
 299
 300 static amd_generic_event_t family_10h_generic_events[] = {
 301   AMD_cmn_generic_events,
 302   AMD_FAMILY_10h_generic_events,
 303   GEN_EV_END
 304 };
 305
 306 static amd_event_t *amd_events = NULL;
 307 static uint_t amd_family;
 308 static amd_generic_event_t *amd_generic_events = NULL;
 309
 310 #define BITS(v, u, l)       (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1))
 311 #define OPTERON_FAMILY      0x0f
 312 #define AMD_FAMILY_10H      0x10
 313
 314 static int
 315 opt_pcbe_init (void)
 316 {
 317   amd_family = cpuid_getfamily ();
 318   if (cpuid_getvendor () != X86_VENDOR_AMD)
 319     return -1;
 320
 321   /*
 322    * Figure out processor revision here and assign appropriate
 323    * event configuration.
 324    */
 325   switch (amd_family)
 326     {
 327     case OPTERON_FAMILY:
 328       amd_events = opt_events_rev_E;
 329       amd_generic_events = opt_generic_events;
 330       break;
 331     case AMD_FAMILY_10H:
 332       amd_events = family_10h_events;
 333       amd_generic_events = family_10h_generic_events;
 334       break;
 335     }
 336   return 0;
 337 }
 338
 339 static uint_t
 340 opt_pcbe_ncounters (void)
 341 {
 342   return (4);
 343 }
 344
 345 static const char *
 346 opt_pcbe_impl_name (void)
 347 {
 348   if (amd_family == OPTERON_FAMILY)
 349     return ("AMD Opteron & Athlon64");
 350   else if (amd_family == AMD_FAMILY_10H)
 351     return ("AMD Family 10h");
 352   else
 353     return ("Unknown AMD processor");
 354 }
 355
 356 static const char *
 357 opt_pcbe_cpuref (void)
 358 {
 359   if (amd_family == OPTERON_FAMILY)
 360     return GTXT ("See Chapter 10 of the \"BIOS and Kernel Developer's Guide for the AMD Athlon 64 and AMD Opteron Processors,\"\nAMD publication #26094");
 361   else if (amd_family == AMD_FAMILY_10H)
 362     return GTXT ("See section 3.15 of the \"BIOS and Kernel Developer's Guide (BKDG) For AMD Family 10h Processors,\"\nAMD publication #31116");
 363   else
 364     return GTXT ("Unknown AMD processor");
 365 }
 366
 367 static int
 368 opt_pcbe_get_events (hwcf_hwc_cb_t *hwc_cb)
 369 {
 370   int count = 0;
 371   for (uint_t kk = 0; amd_events && amd_events[kk].name; kk++)
 372     for (uint_t jj = 0; jj < opt_pcbe_ncounters (); jj++)
 373       {
 374         hwc_cb (jj, amd_events[kk].name);
 375         count++;
 376       }
 377   for (uint_t kk = 0; amd_generic_events && amd_generic_events[kk].name; kk++)
 378     for (uint_t jj = 0; jj < opt_pcbe_ncounters (); jj++)
 379       {
 380         hwc_cb (jj, amd_generic_events[kk].name);
 381         count++;
 382       }
 383   return count;
 384 }
 385
 386 static int
 387 opt_pcbe_get_eventnum (const char *eventname, uint_t pmc, eventsel_t *eventsel,
 388                        eventsel_t *event_valid_umask, uint_t *pmc_sel)
 389 {
 390   uint_t kk;
 391   *pmc_sel = pmc; /* for AMD, pmc doesn't need to be adjusted */
 392   *eventsel = (eventsel_t) - 1;
 393   *event_valid_umask = 0x0;
 394
 395   /* search table */
 396   for (kk = 0; amd_events && amd_events[kk].name; kk++)
 397     {
 398       if (strcmp (eventname, amd_events[kk].name) == 0)
 399         {
 400           *eventsel = EXTENDED_EVNUM_2_EVSEL (amd_events[kk].emask);
 401           *event_valid_umask = amd_events[kk].umask_valid;
 402           return 0;
 403         }
 404     }
 405
 406   /* search generic */
 407   int generic = 0;
 408   eventsel_t tmp_umask = 0;
 409   for (kk = 0; amd_generic_events && amd_generic_events[kk].name; kk++)
 410     {
 411       if (strcmp (eventname, amd_generic_events[kk].name) == 0)
 412         {
 413           generic = 1;
 414           eventname = amd_generic_events[kk].event;
 415           tmp_umask = amd_generic_events[kk].umask;
 416           break;
 417         }
 418     }
 419   if (!generic)
 420     return -1;
 421
 422   /* find real event # for generic event */
 423   for (kk = 0; amd_events && amd_events[kk].name; kk++)
 424     {
 425       if (strcmp (eventname, amd_events[kk].name) == 0)
 426         {
 427           *eventsel = EXTENDED_EVNUM_2_EVSEL (amd_events[kk].emask);
 428           *eventsel |= (tmp_umask << PERFCTR_UMASK_SHIFT);
 429           *event_valid_umask = 0; /* user umask not allowed w/generic events */
 430           return 0;
 431         }
 432     }
 433   return -1;
 434 }
 435
 436 static hdrv_pcbe_api_t hdrv_pcbe_opteron_api = {
 437   opt_pcbe_init,
 438   opt_pcbe_ncounters,
 439   opt_pcbe_impl_name,
 440   opt_pcbe_cpuref,
 441   opt_pcbe_get_events,
 442   opt_pcbe_get_eventnum
 443 };