include/opcode/riscv.h

   1 /* riscv.h.  RISC-V opcode list for GDB, the GNU debugger.
   2    Copyright (C) 2011-2024 Free Software Foundation, Inc.
   3    Contributed by Andrew Waterman
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version
  10    3, or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef _RISCV_H_
  22 #define _RISCV_H_
  23
  24 #include "riscv-opc.h"
  25 #include <stdlib.h>
  26 #include <stdint.h>
  27
  28 typedef uint64_t insn_t;
  29
  30 static inline unsigned int riscv_insn_length (insn_t insn)
  31 {
  32   if ((insn & 0x3) != 0x3) /* RVC instructions.  */
  33     return 2;
  34   if ((insn & 0x1f) != 0x1f) /* 32-bit instructions.  */
  35     return 4;
  36   if ((insn & 0x3f) == 0x1f) /* 48-bit instructions.  */
  37     return 6;
  38   if ((insn & 0x7f) == 0x3f) /* 64-bit instructions.  */
  39     return 8;
  40   /* 80- ... 176-bit instructions.  */
  41   if ((insn & 0x7f) == 0x7f && (insn & 0x7000) != 0x7000)
  42     return 10 + ((insn >> 11) & 0xe);
  43   /* Maximum value returned by this function.  */
  44 #define RISCV_MAX_INSN_LEN 22
  45   /* Longer instructions not supported at the moment.  */
  46   return 2;
  47 }
  48
  49 #define RVC_JUMP_BITS 11
  50 #define RVC_JUMP_REACH ((1ULL << RVC_JUMP_BITS) * RISCV_JUMP_ALIGN)
  51
  52 #define RVC_BRANCH_BITS 8
  53 #define RVC_BRANCH_REACH ((1ULL << RVC_BRANCH_BITS) * RISCV_BRANCH_ALIGN)
  54
  55 #define RV_X(x, s, n)  (((x) >> (s)) & ((1 << (n)) - 1))
  56 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
  57 #define RV_X_SIGNED(x, s, n) (RV_X(x, s, n) | ((-(RV_X(x, (s + n - 1), 1))) << (n)))
  58
  59 #define EXTRACT_ITYPE_IMM(x) \
  60   (RV_X(x, 20, 12) | (RV_IMM_SIGN(x) << 12))
  61 #define EXTRACT_STYPE_IMM(x) \
  62   (RV_X(x, 7, 5) | (RV_X(x, 25, 7) << 5) | (RV_IMM_SIGN(x) << 12))
  63 #define EXTRACT_BTYPE_IMM(x) \
  64   ((RV_X(x, 8, 4) << 1) | (RV_X(x, 25, 6) << 5) | (RV_X(x, 7, 1) << 11) | (RV_IMM_SIGN(x) << 12))
  65 #define EXTRACT_UTYPE_IMM(x) \
  66   ((RV_X(x, 12, 20) << 12) | (RV_IMM_SIGN(x) << 32))
  67 #define EXTRACT_JTYPE_IMM(x) \
  68   ((RV_X(x, 21, 10) << 1) | (RV_X(x, 20, 1) << 11) | (RV_X(x, 12, 8) << 12) | (RV_IMM_SIGN(x) << 20))
  69 #define EXTRACT_CITYPE_IMM(x) \
  70   (RV_X(x, 2, 5) | (-RV_X(x, 12, 1) << 5))
  71 #define EXTRACT_CITYPE_LUI_IMM(x) \
  72   (EXTRACT_CITYPE_IMM (x) << RISCV_IMM_BITS)
  73 #define EXTRACT_CITYPE_ADDI16SP_IMM(x) \
  74   ((RV_X(x, 6, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 1) << 6) | (RV_X(x, 3, 2) << 7) | (-RV_X(x, 12, 1) << 9))
  75 #define EXTRACT_CITYPE_LWSP_IMM(x) \
  76   ((RV_X(x, 4, 3) << 2) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 2) << 6))
  77 #define EXTRACT_CITYPE_LDSP_IMM(x) \
  78   ((RV_X(x, 5, 2) << 3) | (RV_X(x, 12, 1) << 5) | (RV_X(x, 2, 3) << 6))
  79 #define EXTRACT_CSSTYPE_IMM(x) \
  80   (RV_X(x, 7, 6) << 0)
  81 #define EXTRACT_CSSTYPE_SWSP_IMM(x) \
  82   ((RV_X(x, 9, 4) << 2) | (RV_X(x, 7, 2) << 6))
  83 #define EXTRACT_CSSTYPE_SDSP_IMM(x) \
  84   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 7, 3) << 6))
  85 #define EXTRACT_CIWTYPE_IMM(x) \
  86   (RV_X(x, 5, 8))
  87 #define EXTRACT_CIWTYPE_ADDI4SPN_IMM(x) \
  88   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 5, 1) << 3) | (RV_X(x, 11, 2) << 4) | (RV_X(x, 7, 4) << 6))
  89 #define EXTRACT_CLTYPE_IMM(x) \
  90   ((RV_X(x, 5, 2) << 0) | (RV_X(x, 10, 3) << 2))
  91 #define EXTRACT_CLTYPE_LW_IMM(x) \
  92   ((RV_X(x, 6, 1) << 2) | (RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 1) << 6))
  93 #define EXTRACT_CLTYPE_LD_IMM(x) \
  94   ((RV_X(x, 10, 3) << 3) | (RV_X(x, 5, 2) << 6))
  95 #define EXTRACT_CBTYPE_IMM(x) \
  96   ((RV_X(x, 3, 2) << 1) | (RV_X(x, 10, 2) << 3) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 5, 2) << 6) | (-RV_X(x, 12, 1) << 8))
  97 #define EXTRACT_CJTYPE_IMM(x) \
  98   ((RV_X(x, 3, 3) << 1) | (RV_X(x, 11, 1) << 4) | (RV_X(x, 2, 1) << 5) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 9, 2) << 8) | (RV_X(x, 8, 1) << 10) | (-RV_X(x, 12, 1) << 11))
  99 #define EXTRACT_RVV_VI_IMM(x) \
 100   (RV_X(x, 15, 5) | (-RV_X(x, 19, 1) << 5))
 101 #define EXTRACT_RVV_VI_UIMM(x) \
 102   (RV_X(x, 15, 5))
 103 #define EXTRACT_RVV_VI_UIMM6(x) \
 104   (RV_X(x, 15, 5) | (RV_X(x, 26, 1) << 5))
 105 #define EXTRACT_RVV_OFFSET(x) \
 106   (RV_X(x, 29, 3))
 107 #define EXTRACT_RVV_VB_IMM(x) \
 108   (RV_X(x, 20, 10))
 109 #define EXTRACT_RVV_VC_IMM(x) \
 110   (RV_X(x, 20, 11))
 111 #define EXTRACT_ZCB_BYTE_UIMM(x) \
 112   (RV_X(x, 6, 1) | (RV_X(x, 5, 1) << 1))
 113 #define EXTRACT_ZCB_HALFWORD_UIMM(x) \
 114   (RV_X(x, 5, 1) << 1)
 115 /* Vendor-specific (CORE-V) extract macros.  */
 116 #define EXTRACT_CV_IS2_UIMM5(x) \
 117   (RV_X(x, 20, 5))
 118 #define EXTRACT_CV_IS3_UIMM5(x) \
 119   (RV_X(x, 25, 5))
 120
 121 #define ENCODE_ITYPE_IMM(x) \
 122   (RV_X(x, 0, 12) << 20)
 123 #define ENCODE_STYPE_IMM(x) \
 124   ((RV_X(x, 0, 5) << 7) | (RV_X(x, 5, 7) << 25))
 125 #define ENCODE_BTYPE_IMM(x) \
 126   ((RV_X(x, 1, 4) << 8) | (RV_X(x, 5, 6) << 25) | (RV_X(x, 11, 1) << 7) | (RV_X(x, 12, 1) << 31))
 127 #define ENCODE_UTYPE_IMM(x) \
 128   (RV_X(x, 12, 20) << 12)
 129 #define ENCODE_JTYPE_IMM(x) \
 130   ((RV_X(x, 1, 10) << 21) | (RV_X(x, 11, 1) << 20) | (RV_X(x, 12, 8) << 12) | (RV_X(x, 20, 1) << 31))
 131 #define ENCODE_CITYPE_IMM(x) \
 132   ((RV_X(x, 0, 5) << 2) | (RV_X(x, 5, 1) << 12))
 133 #define ENCODE_CITYPE_LUI_IMM(x) \
 134   ENCODE_CITYPE_IMM ((x) >> RISCV_IMM_BITS)
 135 #define ENCODE_CITYPE_ADDI16SP_IMM(x) \
 136   ((RV_X(x, 4, 1) << 6) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 5) | (RV_X(x, 7, 2) << 3) | (RV_X(x, 9, 1) << 12))
 137 #define ENCODE_CITYPE_LWSP_IMM(x) \
 138   ((RV_X(x, 2, 3) << 4) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 2) << 2))
 139 #define ENCODE_CITYPE_LDSP_IMM(x) \
 140   ((RV_X(x, 3, 2) << 5) | (RV_X(x, 5, 1) << 12) | (RV_X(x, 6, 3) << 2))
 141 #define ENCODE_CSSTYPE_IMM(x) \
 142   (RV_X(x, 0, 6) << 7)
 143 #define ENCODE_CSSTYPE_SWSP_IMM(x) \
 144   ((RV_X(x, 2, 4) << 9) | (RV_X(x, 6, 2) << 7))
 145 #define ENCODE_CSSTYPE_SDSP_IMM(x) \
 146   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 3) << 7))
 147 #define ENCODE_CIWTYPE_IMM(x) \
 148   (RV_X(x, 0, 8) << 5)
 149 #define ENCODE_CIWTYPE_ADDI4SPN_IMM(x) \
 150   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 1) << 5) | (RV_X(x, 4, 2) << 11) | (RV_X(x, 6, 4) << 7))
 151 #define ENCODE_CLTYPE_IMM(x) \
 152   ((RV_X(x, 0, 2) << 5) | (RV_X(x, 2, 3) << 10))
 153 #define ENCODE_CLTYPE_LW_IMM(x) \
 154   ((RV_X(x, 2, 1) << 6) | (RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 1) << 5))
 155 #define ENCODE_CLTYPE_LD_IMM(x) \
 156   ((RV_X(x, 3, 3) << 10) | (RV_X(x, 6, 2) << 5))
 157 #define ENCODE_CBTYPE_IMM(x) \
 158   ((RV_X(x, 1, 2) << 3) | (RV_X(x, 3, 2) << 10) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 2) << 5) | (RV_X(x, 8, 1) << 12))
 159 #define ENCODE_CJTYPE_IMM(x) \
 160   ((RV_X(x, 1, 3) << 3) | (RV_X(x, 4, 1) << 11) | (RV_X(x, 5, 1) << 2) | (RV_X(x, 6, 1) << 7) | (RV_X(x, 7, 1) << 6) | (RV_X(x, 8, 2) << 9) | (RV_X(x, 10, 1) << 8) | (RV_X(x, 11, 1) << 12))
 161 #define ENCODE_RVV_VB_IMM(x) \
 162   (RV_X(x, 0, 10) << 20)
 163 #define ENCODE_RVV_VC_IMM(x) \
 164   (RV_X(x, 0, 11) << 20)
 165 #define ENCODE_RVV_VI_UIMM6(x) \
 166   (RV_X(x, 0, 5) << 15 | RV_X(x, 5, 1) << 26)
 167 #define ENCODE_ZCB_BYTE_UIMM(x) \
 168   ((RV_X(x, 0, 1) << 6) | (RV_X(x, 1, 1) << 5))
 169 #define ENCODE_ZCB_HALFWORD_UIMM(x) \
 170   (RV_X(x, 1, 1) << 5)
 171 /* Vendor-specific (CORE-V) encode macros.  */
 172 #define ENCODE_CV_IS2_UIMM5(x) \
 173   (RV_X(x, 0, 5) << 20)
 174 #define ENCODE_CV_IS3_UIMM5(x) \
 175   (RV_X(x, 0, 5) << 25)
 176
 177 #define VALID_ITYPE_IMM(x) (EXTRACT_ITYPE_IMM(ENCODE_ITYPE_IMM(x)) == (x))
 178 #define VALID_STYPE_IMM(x) (EXTRACT_STYPE_IMM(ENCODE_STYPE_IMM(x)) == (x))
 179 #define VALID_BTYPE_IMM(x) (EXTRACT_BTYPE_IMM(ENCODE_BTYPE_IMM(x)) == (x))
 180 #define VALID_UTYPE_IMM(x) (EXTRACT_UTYPE_IMM(ENCODE_UTYPE_IMM(x)) == (x))
 181 #define VALID_JTYPE_IMM(x) (EXTRACT_JTYPE_IMM(ENCODE_JTYPE_IMM(x)) == (x))
 182 #define VALID_CITYPE_IMM(x) (EXTRACT_CITYPE_IMM(ENCODE_CITYPE_IMM(x)) == (x))
 183 #define VALID_CITYPE_LUI_IMM(x) (ENCODE_CITYPE_LUI_IMM(x) != 0 \
 184                                  && EXTRACT_CITYPE_LUI_IMM(ENCODE_CITYPE_LUI_IMM(x)) == (x))
 185 #define VALID_CITYPE_ADDI16SP_IMM(x) (ENCODE_CITYPE_ADDI16SP_IMM(x) != 0 \
 186                                       && EXTRACT_CITYPE_ADDI16SP_IMM(ENCODE_CITYPE_ADDI16SP_IMM(x)) == (x))
 187 #define VALID_CITYPE_LWSP_IMM(x) (EXTRACT_CITYPE_LWSP_IMM(ENCODE_CITYPE_LWSP_IMM(x)) == (x))
 188 #define VALID_CITYPE_LDSP_IMM(x) (EXTRACT_CITYPE_LDSP_IMM(ENCODE_CITYPE_LDSP_IMM(x)) == (x))
 189 #define VALID_CSSTYPE_IMM(x) (EXTRACT_CSSTYPE_IMM(ENCODE_CSSTYPE_IMM(x)) == (x))
 190 #define VALID_CSSTYPE_SWSP_IMM(x) (EXTRACT_CSSTYPE_SWSP_IMM(ENCODE_CSSTYPE_SWSP_IMM(x)) == (x))
 191 #define VALID_CSSTYPE_SDSP_IMM(x) (EXTRACT_CSSTYPE_SDSP_IMM(ENCODE_CSSTYPE_SDSP_IMM(x)) == (x))
 192 #define VALID_CIWTYPE_IMM(x) (EXTRACT_CIWTYPE_IMM(ENCODE_CIWTYPE_IMM(x)) == (x))
 193 #define VALID_CIWTYPE_ADDI4SPN_IMM(x) (EXTRACT_CIWTYPE_ADDI4SPN_IMM(ENCODE_CIWTYPE_ADDI4SPN_IMM(x)) == (x))
 194 #define VALID_CLTYPE_IMM(x) (EXTRACT_CLTYPE_IMM(ENCODE_CLTYPE_IMM(x)) == (x))
 195 #define VALID_CLTYPE_LW_IMM(x) (EXTRACT_CLTYPE_LW_IMM(ENCODE_CLTYPE_LW_IMM(x)) == (x))
 196 #define VALID_CLTYPE_LD_IMM(x) (EXTRACT_CLTYPE_LD_IMM(ENCODE_CLTYPE_LD_IMM(x)) == (x))
 197 #define VALID_CBTYPE_IMM(x) (EXTRACT_CBTYPE_IMM(ENCODE_CBTYPE_IMM(x)) == (x))
 198 #define VALID_CJTYPE_IMM(x) (EXTRACT_CJTYPE_IMM(ENCODE_CJTYPE_IMM(x)) == (x))
 199 #define VALID_RVV_VB_IMM(x) (EXTRACT_RVV_VB_IMM(ENCODE_RVV_VB_IMM(x)) == (x))
 200 #define VALID_RVV_VC_IMM(x) (EXTRACT_RVV_VC_IMM(ENCODE_RVV_VC_IMM(x)) == (x))
 201 #define VALID_ZCB_BYTE_UIMM(x) (EXTRACT_ZCB_BYTE_UIMM(ENCODE_ZCB_BYTE_UIMM(x)) == (x))
 202 #define VALID_ZCB_HALFWORD_UIMM(x) (EXTRACT_ZCB_HALFWORD_UIMM(ENCODE_ZCB_HALFWORD_UIMM(x)) == (x))
 203
 204 #define RISCV_RTYPE(insn, rd, rs1, rs2) \
 205   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2))
 206 #define RISCV_ITYPE(insn, rd, rs1, imm) \
 207   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ((rs1) << OP_SH_RS1) | ENCODE_ITYPE_IMM(imm))
 208 #define RISCV_STYPE(insn, rs1, rs2, imm) \
 209   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_STYPE_IMM(imm))
 210 #define RISCV_BTYPE(insn, rs1, rs2, target) \
 211   ((MATCH_ ## insn) | ((rs1) << OP_SH_RS1) | ((rs2) << OP_SH_RS2) | ENCODE_BTYPE_IMM(target))
 212 #define RISCV_UTYPE(insn, rd, bigimm) \
 213   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_UTYPE_IMM(bigimm))
 214 #define RISCV_JTYPE(insn, rd, target) \
 215   ((MATCH_ ## insn) | ((rd) << OP_SH_RD) | ENCODE_JTYPE_IMM(target))
 216
 217 #define RISCV_NOP RISCV_ITYPE(ADDI, 0, 0, 0)
 218 #define RVC_NOP MATCH_C_ADDI
 219
 220 #define RISCV_CONST_HIGH_PART(VALUE) \
 221   (((VALUE) + (RISCV_IMM_REACH/2)) & ~(RISCV_IMM_REACH-1))
 222 #define RISCV_CONST_LOW_PART(VALUE) ((VALUE) - RISCV_CONST_HIGH_PART (VALUE))
 223 #define RISCV_PCREL_HIGH_PART(VALUE, PC) RISCV_CONST_HIGH_PART((VALUE) - (PC))
 224 #define RISCV_PCREL_LOW_PART(VALUE, PC) RISCV_CONST_LOW_PART((VALUE) - (PC))
 225
 226 #define RISCV_JUMP_BITS RISCV_BIGIMM_BITS
 227 #define RISCV_JUMP_ALIGN_BITS 1
 228 #define RISCV_JUMP_ALIGN (1 << RISCV_JUMP_ALIGN_BITS)
 229 #define RISCV_JUMP_REACH ((1ULL << RISCV_JUMP_BITS) * RISCV_JUMP_ALIGN)
 230
 231 #define RISCV_IMM_BITS 12
 232 #define RISCV_BIGIMM_BITS (32 - RISCV_IMM_BITS)
 233 #define RISCV_IMM_REACH (1LL << RISCV_IMM_BITS)
 234 #define RISCV_BIGIMM_REACH (1LL << RISCV_BIGIMM_BITS)
 235 #define RISCV_RVC_IMM_REACH (1LL << 6)
 236 #define RISCV_BRANCH_BITS RISCV_IMM_BITS
 237 #define RISCV_BRANCH_ALIGN_BITS RISCV_JUMP_ALIGN_BITS
 238 #define RISCV_BRANCH_ALIGN (1 << RISCV_BRANCH_ALIGN_BITS)
 239 #define RISCV_BRANCH_REACH (RISCV_IMM_REACH * RISCV_BRANCH_ALIGN)
 240
 241 /* RV fields.  */
 242
 243 #define OP_MASK_OP              0x7f
 244 #define OP_SH_OP                0
 245 #define OP_MASK_RS2             0x1f
 246 #define OP_SH_RS2               20
 247 #define OP_MASK_RS1             0x1f
 248 #define OP_SH_RS1               15
 249 #define OP_MASK_RS3             0x1fU
 250 #define OP_SH_RS3               27
 251 #define OP_MASK_RD              0x1f
 252 #define OP_SH_RD                7
 253 #define OP_MASK_SHAMT           0x3f
 254 #define OP_SH_SHAMT             20
 255 #define OP_MASK_SHAMTW          0x1f
 256 #define OP_SH_SHAMTW            20
 257 #define OP_MASK_RM              0x7
 258 #define OP_SH_RM                12
 259 #define OP_MASK_PRED            0xf
 260 #define OP_SH_PRED              24
 261 #define OP_MASK_SUCC            0xf
 262 #define OP_SH_SUCC              20
 263 #define OP_MASK_AQ              0x1
 264 #define OP_SH_AQ                26
 265 #define OP_MASK_RL              0x1
 266 #define OP_SH_RL                25
 267
 268 #define OP_MASK_CSR             0xfffU
 269 #define OP_SH_CSR               20
 270
 271 #define OP_MASK_FUNCT3          0x7
 272 #define OP_SH_FUNCT3            12
 273 #define OP_MASK_FUNCT7          0x7fU
 274 #define OP_SH_FUNCT7            25
 275 #define OP_MASK_FUNCT2          0x3
 276 #define OP_SH_FUNCT2            25
 277
 278 /* RVC fields.  */
 279
 280 #define OP_MASK_OP2             0x3
 281 #define OP_SH_OP2               0
 282
 283 #define OP_MASK_CRS2            0x1f
 284 #define OP_SH_CRS2              2
 285 #define OP_MASK_CRS1S           0x7
 286 #define OP_SH_CRS1S             7
 287 #define OP_MASK_CRS2S           0x7
 288 #define OP_SH_CRS2S             2
 289
 290 #define OP_MASK_CFUNCT6         0x3f
 291 #define OP_SH_CFUNCT6           10
 292 #define OP_MASK_CFUNCT4         0xf
 293 #define OP_SH_CFUNCT4           12
 294 #define OP_MASK_CFUNCT3         0x7
 295 #define OP_SH_CFUNCT3           13
 296 #define OP_MASK_CFUNCT2         0x3
 297 #define OP_SH_CFUNCT2           5
 298
 299 /* Scalar crypto fields. */
 300
 301 #define OP_SH_BS        30
 302 #define OP_MASK_BS      3
 303 #define OP_SH_RNUM      20
 304 #define OP_MASK_RNUM    0xf
 305
 306 /* RVV fields.  */
 307
 308 #define OP_MASK_VD              0x1f
 309 #define OP_SH_VD                7
 310 #define OP_MASK_VS1             0x1f
 311 #define OP_SH_VS1               15
 312 #define OP_MASK_VS2             0x1f
 313 #define OP_SH_VS2               20
 314 #define OP_MASK_VIMM            0x1f
 315 #define OP_SH_VIMM              15
 316 #define OP_MASK_VMASK           0x1
 317 #define OP_SH_VMASK             25
 318 #define OP_MASK_VFUNCT6         0x3f
 319 #define OP_SH_VFUNCT6           26
 320 #define OP_MASK_VLMUL           0x7
 321 #define OP_SH_VLMUL             0
 322 #define OP_MASK_VSEW            0x7
 323 #define OP_SH_VSEW              3
 324 #define OP_MASK_VTA             0x1
 325 #define OP_SH_VTA               6
 326 #define OP_MASK_VMA             0x1
 327 #define OP_SH_VMA               7
 328 #define OP_MASK_VWD             0x1
 329 #define OP_SH_VWD               26
 330
 331 #define OP_MASK_XTHEADVLMUL     0x3
 332 #define OP_SH_XTHEADVLMUL       0
 333 #define OP_MASK_XTHEADVSEW      0x7
 334 #define OP_SH_XTHEADVSEW        2
 335 #define OP_MASK_XTHEADVEDIV     0x3
 336 #define OP_SH_XTHEADVEDIV       5
 337 #define OP_MASK_XTHEADVTYPE_RES 0xf
 338 #define OP_SH_XTHEADVTYPE_RES   7
 339
 340 #define NVECR 32
 341 #define NVECM 1
 342
 343 /* SiFive fields.  */
 344 #define OP_MASK_XSO2            0x3
 345 #define OP_SH_XSO2              26
 346 #define OP_MASK_XSO1            0x1
 347 #define OP_SH_XSO1              26
 348
 349 /* ABI names for selected x-registers.  */
 350
 351 #define X_RA 1
 352 #define X_SP 2
 353 #define X_GP 3
 354 #define X_TP 4
 355 #define X_T0 5
 356 #define X_T1 6
 357 #define X_T2 7
 358 #define X_T3 28
 359
 360 #define NGPR 32
 361 #define NFPR 32
 362
 363 /* These fake label defines are use by both the assembler, and
 364    libopcodes.  The assembler uses this when it needs to generate a fake
 365    label, and libopcodes uses it to hide the fake labels in its output.  */
 366 #define RISCV_FAKE_LABEL_NAME ".L0 "
 367 #define RISCV_FAKE_LABEL_CHAR ' '
 368
 369 /* Replace bits MASK << SHIFT of STRUCT with the equivalent bits in
 370    VALUE << SHIFT.  VALUE is evaluated exactly once.  */
 371 #define INSERT_BITS(STRUCT, VALUE, MASK, SHIFT) \
 372   (STRUCT) = (((STRUCT) & ~((insn_t)(MASK) << (SHIFT))) \
 373               | ((insn_t)((VALUE) & (MASK)) << (SHIFT)))
 374
 375 /* Extract bits MASK << SHIFT from STRUCT and shift them right
 376    SHIFT places.  */
 377 #define EXTRACT_BITS(STRUCT, MASK, SHIFT) \
 378   (((STRUCT) >> (SHIFT)) & (MASK))
 379
 380 /* Extract the operand given by FIELD from integer INSN.  */
 381 #define EXTRACT_OPERAND(FIELD, INSN) \
 382   ((unsigned int) EXTRACT_BITS ((INSN), OP_MASK_##FIELD, OP_SH_##FIELD))
 383
 384 /* Extract an unsigned immediate operand on position s with n bits.  */
 385 #define EXTRACT_U_IMM(n, s, l) \
 386   RV_X (l, s, n)
 387
 388 /* Extract an signed immediate operand on position s with n bits.  */
 389 #define EXTRACT_S_IMM(n, s, l) \
 390   RV_X_SIGNED (l, s, n)
 391
 392 /* Validate that unsigned n-bit immediate is within bounds.  */
 393 #define VALIDATE_U_IMM(v, n) \
 394   ((unsigned long) v < (1UL << n))
 395
 396 /* Validate that signed n-bit immediate is within bounds.  */
 397 #define VALIDATE_S_IMM(v, n) \
 398   (v < (long) (1UL << (n-1)) && v >= -(offsetT) (1UL << (n-1)))
 399
 400 /* The maximal number of subset can be required.  */
 401 #define MAX_SUBSET_NUM 4
 402
 403 /* All RISC-V instructions belong to at least one of these classes.  */
 404 enum riscv_insn_class
 405 {
 406   INSN_CLASS_NONE,
 407
 408   INSN_CLASS_I,
 409   INSN_CLASS_C,
 410   INSN_CLASS_A,
 411   INSN_CLASS_M,
 412   INSN_CLASS_F,
 413   INSN_CLASS_D,
 414   INSN_CLASS_Q,
 415   INSN_CLASS_F_AND_C,
 416   INSN_CLASS_D_AND_C,
 417   INSN_CLASS_ZICOND,
 418   INSN_CLASS_ZICSR,
 419   INSN_CLASS_ZIFENCEI,
 420   INSN_CLASS_ZIHINTNTL,
 421   INSN_CLASS_ZIHINTNTL_AND_C,
 422   INSN_CLASS_ZIHINTPAUSE,
 423   INSN_CLASS_ZMMUL,
 424   INSN_CLASS_ZAWRS,
 425   INSN_CLASS_F_INX,
 426   INSN_CLASS_D_INX,
 427   INSN_CLASS_Q_INX,
 428   INSN_CLASS_ZFH_INX,
 429   INSN_CLASS_ZFHMIN,
 430   INSN_CLASS_ZFHMIN_INX,
 431   INSN_CLASS_ZFHMIN_AND_D_INX,
 432   INSN_CLASS_ZFHMIN_AND_Q_INX,
 433   INSN_CLASS_ZFA,
 434   INSN_CLASS_D_AND_ZFA,
 435   INSN_CLASS_Q_AND_ZFA,
 436   INSN_CLASS_ZFH_AND_ZFA,
 437   INSN_CLASS_ZFH_OR_ZVFH_AND_ZFA,
 438   INSN_CLASS_ZBA,
 439   INSN_CLASS_ZBB,
 440   INSN_CLASS_ZBC,
 441   INSN_CLASS_ZBS,
 442   INSN_CLASS_ZBKB,
 443   INSN_CLASS_ZBKC,
 444   INSN_CLASS_ZBKX,
 445   INSN_CLASS_ZKND,
 446   INSN_CLASS_ZKNE,
 447   INSN_CLASS_ZKNH,
 448   INSN_CLASS_ZKSED,
 449   INSN_CLASS_ZKSH,
 450   INSN_CLASS_ZBB_OR_ZBKB,
 451   INSN_CLASS_ZBC_OR_ZBKC,
 452   INSN_CLASS_ZKND_OR_ZKNE,
 453   INSN_CLASS_V,
 454   INSN_CLASS_ZVEF,
 455   INSN_CLASS_ZVBB,
 456   INSN_CLASS_ZVBC,
 457   INSN_CLASS_ZVKB,
 458   INSN_CLASS_ZVKG,
 459   INSN_CLASS_ZVKNED,
 460   INSN_CLASS_ZVKNHA_OR_ZVKNHB,
 461   INSN_CLASS_ZVKSED,
 462   INSN_CLASS_ZVKSH,
 463   INSN_CLASS_ZCB,
 464   INSN_CLASS_ZCB_AND_ZBA,
 465   INSN_CLASS_ZCB_AND_ZBB,
 466   INSN_CLASS_ZCB_AND_ZMMUL,
 467   INSN_CLASS_SVINVAL,
 468   INSN_CLASS_ZICBOM,
 469   INSN_CLASS_ZICBOP,
 470   INSN_CLASS_ZICBOZ,
 471   INSN_CLASS_ZABHA,
 472   INSN_CLASS_H,
 473   INSN_CLASS_XCVMAC,
 474   INSN_CLASS_XCVALU,
 475   INSN_CLASS_XTHEADBA,
 476   INSN_CLASS_XTHEADBB,
 477   INSN_CLASS_XTHEADBS,
 478   INSN_CLASS_XTHEADCMO,
 479   INSN_CLASS_XTHEADCONDMOV,
 480   INSN_CLASS_XTHEADFMEMIDX,
 481   INSN_CLASS_XTHEADFMV,
 482   INSN_CLASS_XTHEADINT,
 483   INSN_CLASS_XTHEADMAC,
 484   INSN_CLASS_XTHEADMEMIDX,
 485   INSN_CLASS_XTHEADMEMPAIR,
 486   INSN_CLASS_XTHEADSYNC,
 487   INSN_CLASS_XTHEADVECTOR,
 488   INSN_CLASS_XTHEADZVAMO,
 489   INSN_CLASS_XVENTANACONDOPS,
 490   INSN_CLASS_XSFVCP,
 491 };
 492
 493 /* This structure holds information for a particular instruction.  */
 494 struct riscv_opcode
 495 {
 496   /* The name of the instruction.  */
 497   const char *name;
 498
 499   /* The requirement of xlen for the instruction, 0 if no requirement.  */
 500   unsigned xlen_requirement;
 501
 502   /* Class to which this instruction belongs.  Used to decide whether or
 503      not this instruction is legal in the current -march context.  */
 504   enum riscv_insn_class insn_class;
 505
 506   /* A string describing the arguments for this instruction.  */
 507   const char *args;
 508
 509   /* The basic opcode for the instruction.  When assembling, this
 510      opcode is modified by the arguments to produce the actual opcode
 511      that is used.  If pinfo is INSN_MACRO, then this is 0.  */
 512   insn_t match;
 513
 514   /* If pinfo is not INSN_MACRO, then this is a bit mask for the
 515      relevant portions of the opcode when disassembling.  If the
 516      actual opcode anded with the match field equals the opcode field,
 517      then we have found the correct instruction.  If pinfo is
 518      INSN_MACRO, then this field is the macro identifier.  */
 519   insn_t mask;
 520
 521   /* A function to determine if a word corresponds to this instruction.
 522      Usually, this computes ((word & mask) == match).  */
 523   int (*match_func) (const struct riscv_opcode *op, insn_t word);
 524
 525   /* For a macro, this is INSN_MACRO.  Otherwise, it is a collection
 526      of bits describing the instruction, notably any relevant hazard
 527      information.  */
 528   unsigned long pinfo;
 529 };
 530
 531 /* Instruction is a simple alias (e.g. "mv" for "addi").  */
 532 #define INSN_ALIAS              0x00000001
 533
 534 /* These are for setting insn_info fields.
 535
 536    Nonbranch is the default.  Noninsn is used only if there is no match.
 537    There are no condjsr or dref2 instructions.  So that leaves condbranch,
 538    branch, jsr, and dref that we need to handle here, encoded in 3 bits.  */
 539 #define INSN_TYPE               0x0000000e
 540
 541 /* Instruction is an unconditional branch.  */
 542 #define INSN_BRANCH             0x00000002
 543 /* Instruction is a conditional branch.  */
 544 #define INSN_CONDBRANCH         0x00000004
 545 /* Instruction is a jump to subroutine.  */
 546 #define INSN_JSR                0x00000006
 547 /* Instruction is a data reference.  */
 548 #define INSN_DREF               0x00000008
 549 /* Instruction is allowed when eew >= 64.  */
 550 #define INSN_V_EEW64            0x10000000
 551
 552 /* We have 5 data reference sizes, which we can encode in 3 bits.  */
 553 #define INSN_DATA_SIZE          0x00000070
 554 #define INSN_DATA_SIZE_SHIFT    4
 555 #define INSN_1_BYTE             0x00000010
 556 #define INSN_2_BYTE             0x00000020
 557 #define INSN_4_BYTE             0x00000030
 558 #define INSN_8_BYTE             0x00000040
 559 #define INSN_16_BYTE            0x00000050
 560
 561 /* Instruction is actually a macro.  It should be ignored by the
 562    disassembler, and requires special treatment by the assembler.  */
 563 #define INSN_MACRO              0xffffffff
 564
 565 /* This is a list of macro expanded instructions.  */
 566 enum
 567 {
 568   M_LA,
 569   M_LLA,
 570   M_LGA,
 571   M_LA_TLS_GD,
 572   M_LA_TLS_IE,
 573   M_Lx,
 574   M_FLx,
 575   M_Sx_FSx,
 576   M_CALL,
 577   M_J,
 578   M_LI,
 579   M_EXTH,
 580   M_ZEXTW,
 581   M_SEXTB,
 582   M_VMSGE,
 583   M_NUM_MACROS
 584 };
 585
 586 /* The mapping symbol states.  */
 587 enum riscv_seg_mstate
 588 {
 589   MAP_NONE = 0,         /* Must be zero, for seginfo in new sections.  */
 590   MAP_DATA,             /* Data.  */
 591   MAP_INSN,             /* Instructions.  */
 592 };
 593
 594 #define NRC (4 + 1)     /* Max characters in register names, incl nul.  */
 595
 596 extern const char riscv_gpr_names_numeric[NGPR][NRC];
 597 extern const char riscv_gpr_names_abi[NGPR][NRC];
 598 extern const char riscv_fpr_names_numeric[NFPR][NRC];
 599 extern const char riscv_fpr_names_abi[NFPR][NRC];
 600 extern const char * const riscv_rm[8];
 601 extern const char * const riscv_pred_succ[16];
 602 extern const char riscv_vecr_names_numeric[NVECR][NRC];
 603 extern const char riscv_vecm_names_numeric[NVECM][NRC];
 604 extern const char * const riscv_vsew[8];
 605 extern const char * const riscv_vlmul[8];
 606 extern const char * const riscv_vta[2];
 607 extern const char * const riscv_vma[2];
 608 extern const char * const riscv_th_vlen[4];
 609 extern const char * const riscv_th_vediv[4];
 610 extern const char * const riscv_fli_symval[32];
 611 extern const float riscv_fli_numval[32];
 612
 613 extern const struct riscv_opcode riscv_opcodes[];
 614 extern const struct riscv_opcode riscv_insn_types[];
 615
 616 #endif /* _RISCV_H_ */