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Fix whitespace snafu in tc-riscv.c
[binutils-gdb.git] / sim / erc32 / erc32.c
blob32c45bddb6804fc5868d68676937e11713f7f41a
1 /* This file is part of SIS (SPARC instruction simulator)
2
3 Copyright (C) 1995-2023 Free Software Foundation, Inc.
4 Contributed by Jiri Gaisler, European Space Agency
5
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
10
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
15
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
18
19 /* The control space devices */
20
21 /* This must come before any other includes. */
22 #include "defs.h"
23
24 #include <sys/types.h>
25 #include <stdio.h>
26 #include <string.h>
27 #ifdef HAVE_TERMIOS_H
28 #include <termios.h>
29 #endif
30 #include <sys/fcntl.h>
31 #include <sys/file.h>
32 #include <unistd.h>
33 #include "sis.h"
34 #include "sim-config.h"
35
36 extern int ctrl_c;
37 extern int32_t sis_verbose;
38 extern int32_t sparclite, sparclite_board;
39 extern int rom8,wrp,uben;
40 extern char uart_dev1[], uart_dev2[];
41
42 int dumbio = 0; /* normal, smart, terminal oriented IO by default */
43
44 /* MEC registers */
45 #define MEC_START 0x01f80000
46 #define MEC_END 0x01f80100
47
48 /* Memory exception waitstates */
49 #define MEM_EX_WS 1
50
51 /* ERC32 always adds one waitstate during RAM std */
52 #define STD_WS 1
53
54 #ifdef ERRINJ
55 extern int errmec;
56 #endif
57
58 #define MEC_WS 0 /* Waitstates per MEC access (0 ws) */
59 #define MOK 0
60
61 /* MEC register addresses */
62
63 #define MEC_MCR 0x000
64 #define MEC_SFR 0x004
65 #define MEC_PWDR 0x008
66 #define MEC_MEMCFG 0x010
67 #define MEC_IOCR 0x014
68 #define MEC_WCR 0x018
69
70 #define MEC_MAR0 0x020
71 #define MEC_MAR1 0x024
72
73 #define MEC_SSA1 0x020
74 #define MEC_SEA1 0x024
75 #define MEC_SSA2 0x028
76 #define MEC_SEA2 0x02C
77 #define MEC_ISR 0x044
78 #define MEC_IPR 0x048
79 #define MEC_IMR 0x04C
80 #define MEC_ICR 0x050
81 #define MEC_IFR 0x054
82 #define MEC_WDOG 0x060
83 #define MEC_TRAPD 0x064
84 #define MEC_RTC_COUNTER 0x080
85 #define MEC_RTC_RELOAD 0x080
86 #define MEC_RTC_SCALER 0x084
87 #define MEC_GPT_COUNTER 0x088
88 #define MEC_GPT_RELOAD 0x088
89 #define MEC_GPT_SCALER 0x08C
90 #define MEC_TIMER_CTRL 0x098
91 #define MEC_SFSR 0x0A0
92 #define MEC_FFAR 0x0A4
93 #define MEC_ERSR 0x0B0
94 #define MEC_DBG 0x0C0
95 #define MEC_TCR 0x0D0
96
97 #define MEC_BRK 0x0C4
98 #define MEC_WPR 0x0C8
99
100 #define MEC_UARTA 0x0E0
101 #define MEC_UARTB 0x0E4
102 #define MEC_UART_CTRL 0x0E8
103 #define SIM_LOAD 0x0F0
104
105 /* Memory exception causes */
106 #define PROT_EXC 0x3
107 #define UIMP_ACC 0x4
108 #define MEC_ACC 0x6
109 #define WATCH_EXC 0xa
110 #define BREAK_EXC 0xb
111
112 /* Size of UART buffers (bytes) */
113 #define UARTBUF 1024
114
115 /* Number of simulator ticks between flushing the UARTS. */
116 /* For good performance, keep above 1000 */
117 #define UART_FLUSH_TIME 3000
118
119 /* MEC timer control register bits */
120 #define TCR_GACR 1
121 #define TCR_GACL 2
122 #define TCR_GASE 4
123 #define TCR_GASL 8
124 #define TCR_TCRCR 0x100
125 #define TCR_TCRCL 0x200
126 #define TCR_TCRSE 0x400
127 #define TCR_TCRSL 0x800
128
129 /* New uart defines */
130 #define UART_TX_TIME 1000
131 #define UART_RX_TIME 1000
132 #define UARTA_DR 0x1
133 #define UARTA_SRE 0x2
134 #define UARTA_HRE 0x4
135 #define UARTA_OR 0x40
136 #define UARTA_CLR 0x80
137 #define UARTB_DR 0x10000
138 #define UARTB_SRE 0x20000
139 #define UARTB_HRE 0x40000
140 #define UARTB_OR 0x400000
141 #define UARTB_CLR 0x800000
142
143 #define UART_DR 0x100
144 #define UART_TSE 0x200
145 #define UART_THE 0x400
146
147 /* MEC registers */
148
149 static char fname[256];
150 static int32_t find = 0;
151 static uint32_t mec_ssa[2]; /* Write protection start address */
152 static uint32_t mec_sea[2]; /* Write protection end address */
153 static uint32_t mec_wpr[2]; /* Write protection control fields */
154 static uint32_t mec_sfsr;
155 static uint32_t mec_ffar;
156 static uint32_t mec_ipr;
157 static uint32_t mec_imr;
158 static uint32_t mec_isr;
159 static uint32_t mec_icr;
160 static uint32_t mec_ifr;
161 static uint32_t mec_mcr; /* MEC control register */
162 static uint32_t mec_memcfg; /* Memory control register */
163 static uint32_t mec_wcr; /* MEC waitstate register */
164 static uint32_t mec_iocr; /* MEC IO control register */
165 static uint32_t posted_irq;
166 static uint32_t mec_ersr; /* MEC error and status register */
167 static uint32_t mec_tcr; /* MEC test comtrol register */
168
169 static uint32_t rtc_counter;
170 static uint32_t rtc_reload;
171 static uint32_t rtc_scaler;
172 static uint32_t rtc_scaler_start;
173 static uint32_t rtc_enabled;
174 static uint32_t rtc_cr;
175 static uint32_t rtc_se;
176
177 static uint32_t gpt_counter;
178 static uint32_t gpt_reload;
179 static uint32_t gpt_scaler;
180 static uint32_t gpt_scaler_start;
181 static uint32_t gpt_enabled;
182 static uint32_t gpt_cr;
183 static uint32_t gpt_se;
184
185 static uint32_t wdog_scaler;
186 static uint32_t wdog_counter;
187 static uint32_t wdog_rst_delay;
188 static uint32_t wdog_rston;
189
190 enum wdog_type {
191 init, disabled, enabled, stopped
192 };
193
194 static enum wdog_type wdog_status;
195
196
197 /* ROM size 1024 Kbyte */
198 #define ROM_SZ 0x100000
199 #define ROM_MASK 0x0fffff
200
201 /* RAM size 4 Mbyte */
202 #define RAM_START 0x02000000
203 #define RAM_END 0x02400000
204 #define RAM_MASK 0x003fffff
205
206 /* SPARClite boards all seem to have RAM at the same place. */
207 #define RAM_START_SLITE 0x40000000
208 #define RAM_END_SLITE 0x40400000
209 #define RAM_MASK_SLITE 0x003fffff
210
211 /* Memory support variables */
212
213 static uint32_t mem_ramr_ws; /* RAM read waitstates */
214 static uint32_t mem_ramw_ws; /* RAM write waitstates */
215 static uint32_t mem_romr_ws; /* ROM read waitstates */
216 static uint32_t mem_romw_ws; /* ROM write waitstates */
217 static uint32_t mem_ramstart; /* RAM start */
218 static uint32_t mem_ramend; /* RAM end */
219 static uint32_t mem_rammask; /* RAM address mask */
220 static uint32_t mem_ramsz; /* RAM size */
221 static uint32_t mem_romsz; /* ROM size */
222 static uint32_t mem_accprot; /* RAM write protection enabled */
223 static uint32_t mem_blockprot; /* RAM block write protection enabled */
224
225 static unsigned char romb[ROM_SZ];
226 static unsigned char ramb[RAM_END - RAM_START];
227
228
229 /* UART support variables */
230
231 static int32_t fd1, fd2; /* file descriptor for input file */
232 static int32_t Ucontrol; /* UART status register */
233 static unsigned char aq[UARTBUF], bq[UARTBUF];
234 static int32_t anum, aind = 0;
235 static int32_t bnum, bind = 0;
236 static char wbufa[UARTBUF], wbufb[UARTBUF];
237 static unsigned wnuma;
238 static unsigned wnumb;
239 static FILE *f1in, *f1out, *f2in, *f2out;
240 #ifdef HAVE_TERMIOS_H
241 static struct termios ioc1, ioc2, iocold1, iocold2;
242 #endif
243 static int f1open = 0, f2open = 0;
244
245 static char uarta_sreg, uarta_hreg, uartb_sreg, uartb_hreg;
246 static uint32_t uart_stat_reg;
247 static uint32_t uarta_data, uartb_data;
248
249 #ifdef ERA
250 int era = 0;
251 int erareg;
252 #endif
253
254 /* Forward declarations */
255
256 static void decode_ersr (void);
257 #ifdef ERRINJ
258 static void iucomperr (void);
259 #endif
260 static void mecparerror (void);
261 static void decode_memcfg (void);
262 static void decode_wcr (void);
263 static void decode_mcr (void);
264 static void close_port (void);
265 static void mec_reset (void);
266 static void mec_intack (int32_t level);
267 static void chk_irq (void);
268 static void mec_irq (int32_t level);
269 static void set_sfsr (uint32_t fault, uint32_t addr,
270 uint32_t asi, uint32_t read);
271 static int32_t mec_read (uint32_t addr, uint32_t asi, uint32_t *data);
272 static int mec_write (uint32_t addr, uint32_t data);
273 static void port_init (void);
274 static uint32_t read_uart (uint32_t addr);
275 static void write_uart (uint32_t addr, uint32_t data);
276 static void flush_uart (void);
277 static void uarta_tx (int32_t);
278 static void uartb_tx (int32_t);
279 static void uart_rx (int32_t);
280 static void uart_intr (int32_t);
281 static void uart_irq_start (void);
282 static void wdog_intr (int32_t);
283 static void wdog_start (void);
284 static void rtc_intr (int32_t);
285 static void rtc_start (void);
286 static uint32_t rtc_counter_read (void);
287 static void rtc_scaler_set (uint32_t val);
288 static void rtc_reload_set (uint32_t val);
289 static void gpt_intr (int32_t);
290 static void gpt_start (void);
291 static uint32_t gpt_counter_read (void);
292 static void gpt_scaler_set (uint32_t val);
293 static void gpt_reload_set (uint32_t val);
294 static void timer_ctrl (uint32_t val);
295 static void * get_mem_ptr (uint32_t addr, uint32_t size);
296 static void store_bytes (unsigned char *mem, uint32_t waddr,
297 uint32_t *data, int sz, int32_t *ws);
298
299 extern int ext_irl;
300
301
302 /* One-time init */
303
304 void
305 init_sim(void)
306 {
307 port_init();
308 }
309
310 /* Power-on reset init */
311
312 void
313 reset(void)
314 {
315 mec_reset();
316 uart_irq_start();
317 wdog_start();
318 }
319
320 static void
321 decode_ersr(void)
322 {
323 if (mec_ersr & 0x01) {
324 if (!(mec_mcr & 0x20)) {
325 if (mec_mcr & 0x40) {
326 sys_reset();
327 mec_ersr = 0x8000;
328 if (sis_verbose)
329 printf("Error manager reset - IU in error mode\n");
330 } else {
331 sys_halt();
332 mec_ersr |= 0x2000;
333 if (sis_verbose)
334 printf("Error manager halt - IU in error mode\n");
335 }
336 } else
337 mec_irq(1);
338 }
339 if (mec_ersr & 0x04) {
340 if (!(mec_mcr & 0x200)) {
341 if (mec_mcr & 0x400) {
342 sys_reset();
343 mec_ersr = 0x8000;
344 if (sis_verbose)
345 printf("Error manager reset - IU comparison error\n");
346 } else {
347 sys_halt();
348 mec_ersr |= 0x2000;
349 if (sis_verbose)
350 printf("Error manager halt - IU comparison error\n");
351 }
352 } else
353 mec_irq(1);
354 }
355 if (mec_ersr & 0x20) {
356 if (!(mec_mcr & 0x2000)) {
357 if (mec_mcr & 0x4000) {
358 sys_reset();
359 mec_ersr = 0x8000;
360 if (sis_verbose)
361 printf("Error manager reset - MEC hardware error\n");
362 } else {
363 sys_halt();
364 mec_ersr |= 0x2000;
365 if (sis_verbose)
366 printf("Error manager halt - MEC hardware error\n");
367 }
368 } else
369 mec_irq(1);
370 }
371 }
372
373 #ifdef ERRINJ
374 static void
375 iucomperr()
376 {
377 mec_ersr |= 0x04;
378 decode_ersr();
379 }
380 #endif
381
382 static void
383 mecparerror(void)
384 {
385 mec_ersr |= 0x20;
386 decode_ersr();
387 }
388
389
390 /* IU error mode manager */
391
392 void
393 error_mode(uint32_t pc)
394 {
395
396 mec_ersr |= 0x1;
397 decode_ersr();
398 }
399
400
401 /* Check memory settings */
402
403 static void
404 decode_memcfg(void)
405 {
406 if (rom8) mec_memcfg &= ~0x20000;
407 else mec_memcfg |= 0x20000;
408
409 mem_ramsz = (256 * 1024) << ((mec_memcfg >> 10) & 7);
410 mem_romsz = (128 * 1024) << ((mec_memcfg >> 18) & 7);
411
412 if (sparclite_board) {
413 mem_ramstart = RAM_START_SLITE;
414 mem_ramend = RAM_END_SLITE;
415 mem_rammask = RAM_MASK_SLITE;
416 }
417 else {
418 mem_ramstart = RAM_START;
419 mem_ramend = RAM_END;
420 mem_rammask = RAM_MASK;
421 }
422 if (sis_verbose)
423 printf("RAM start: 0x%x, RAM size: %d K, ROM size: %d K\n",
424 mem_ramstart, mem_ramsz >> 10, mem_romsz >> 10);
425 }
426
427 static void
428 decode_wcr(void)
429 {
430 mem_ramr_ws = mec_wcr & 3;
431 mem_ramw_ws = (mec_wcr >> 2) & 3;
432 mem_romr_ws = (mec_wcr >> 4) & 0x0f;
433 if (rom8) {
434 if (mem_romr_ws > 0 ) mem_romr_ws--;
435 mem_romr_ws = 5 + (4*mem_romr_ws);
436 }
437 mem_romw_ws = (mec_wcr >> 8) & 0x0f;
438 if (sis_verbose)
439 printf("Waitstates = RAM read: %d, RAM write: %d, ROM read: %d, ROM write: %d\n",
440 mem_ramr_ws, mem_ramw_ws, mem_romr_ws, mem_romw_ws);
441 }
442
443 static void
444 decode_mcr(void)
445 {
446 mem_accprot = (mec_wpr[0] | mec_wpr[1]);
447 mem_blockprot = (mec_mcr >> 3) & 1;
448 if (sis_verbose && mem_accprot)
449 printf("Memory block write protection enabled\n");
450 if (mec_mcr & 0x08000) {
451 mec_ersr |= 0x20;
452 decode_ersr();
453 }
454 if (sis_verbose && (mec_mcr & 2))
455 printf("Software reset enabled\n");
456 if (sis_verbose && (mec_mcr & 1))
457 printf("Power-down mode enabled\n");
458 }
459
460 /* Flush ports when simulator stops */
461
462 void
463 sim_halt(void)
464 {
465 #ifdef FAST_UART
466 flush_uart();
467 #endif
468 }
469
470 int
471 sim_stop(SIM_DESC sd)
472 {
473 ctrl_c = 1;
474 return 1;
475 }
476
477 static void
478 close_port(void)
479 {
480 if (f1open && f1in != stdin)
481 fclose(f1in);
482 if (f2open && f2in != stdin)
483 fclose(f2in);
484 }
485
486 void
487 exit_sim(void)
488 {
489 close_port();
490 }
491
492 static void
493 mec_reset(void)
494 {
495 int i;
496
497 find = 0;
498 for (i = 0; i < 2; i++)
499 mec_ssa[i] = mec_sea[i] = mec_wpr[i] = 0;
500 mec_mcr = 0x01350014;
501 mec_iocr = 0;
502 mec_sfsr = 0x078;
503 mec_ffar = 0;
504 mec_ipr = 0;
505 mec_imr = 0x7ffe;
506 mec_isr = 0;
507 mec_icr = 0;
508 mec_ifr = 0;
509 mec_memcfg = 0x10000;
510 mec_wcr = -1;
511 mec_ersr = 0; /* MEC error and status register */
512 mec_tcr = 0; /* MEC test comtrol register */
513
514 decode_memcfg();
515 decode_wcr();
516 decode_mcr();
517
518 posted_irq = 0;
519 wnuma = wnumb = 0;
520 anum = aind = bnum = bind = 0;
521
522 uart_stat_reg = UARTA_SRE | UARTA_HRE | UARTB_SRE | UARTB_HRE;
523 uarta_data = uartb_data = UART_THE | UART_TSE;
524
525 rtc_counter = 0xffffffff;
526 rtc_reload = 0xffffffff;
527 rtc_scaler = 0xff;
528 rtc_enabled = 0;
529 rtc_cr = 0;
530 rtc_se = 0;
531
532 gpt_counter = 0xffffffff;
533 gpt_reload = 0xffffffff;
534 gpt_scaler = 0xffff;
535 gpt_enabled = 0;
536 gpt_cr = 0;
537 gpt_se = 0;
538
539 wdog_scaler = 255;
540 wdog_rst_delay = 255;
541 wdog_counter = 0xffff;
542 wdog_rston = 0;
543 wdog_status = init;
544
545 #ifdef ERA
546 erareg = 0;
547 #endif
548
549 }
550
551
552
553 static void
554 mec_intack(int32_t level)
555 {
556 int irq_test;
557
558 if (sis_verbose)
559 printf("interrupt %d acknowledged\n", level);
560 irq_test = mec_tcr & 0x80000;
561 if ((irq_test) && (mec_ifr & (1 << level)))
562 mec_ifr &= ~(1 << level);
563 else
564 mec_ipr &= ~(1 << level);
565 chk_irq();
566 }
567
568 static void
569 chk_irq(void)
570 {
571 int32_t i;
572 uint32_t itmp;
573 int old_irl;
574
575 old_irl = ext_irl;
576 if (mec_tcr & 0x80000) itmp = mec_ifr;
577 else itmp = 0;
578 itmp = ((mec_ipr | itmp) & ~mec_imr) & 0x0fffe;
579 ext_irl = 0;
580 if (itmp != 0) {
581 for (i = 15; i > 0; i--) {
582 if (((itmp >> i) & 1) != 0) {
583 if ((sis_verbose) && (i > old_irl))
584 printf("IU irl: %d\n", i);
585 ext_irl = i;
586 set_int(i, mec_intack, i);
587 break;
588 }
589 }
590 }
591 }
592
593 static void
594 mec_irq(int32_t level)
595 {
596 mec_ipr |= (1 << level);
597 chk_irq();
598 }
599
600 static void
601 set_sfsr(uint32_t fault, uint32_t addr, uint32_t asi, uint32_t read)
602 {
603 if ((asi == 0xa) || (asi == 0xb)) {
604 mec_ffar = addr;
605 mec_sfsr = (fault << 3) | (!read << 15);
606 mec_sfsr |= ((mec_sfsr & 1) ^ 1) | (mec_sfsr & 1);
607 switch (asi) {
608 case 0xa:
609 mec_sfsr |= 0x0004;
610 break;
611 case 0xb:
612 mec_sfsr |= 0x1004;
613 break;
614 }
615 }
616 }
617
618 static int32_t
619 mec_read(uint32_t addr, uint32_t asi, uint32_t *data)
620 {
621
622 switch (addr & 0x0ff) {
623
624 case MEC_MCR: /* 0x00 */
625 *data = mec_mcr;
626 break;
627
628 case MEC_MEMCFG: /* 0x10 */
629 *data = mec_memcfg;
630 break;
631
632 case MEC_IOCR:
633 *data = mec_iocr; /* 0x14 */
634 break;
635
636 case MEC_SSA1: /* 0x20 */
637 *data = mec_ssa[0] | (mec_wpr[0] << 23);
638 break;
639 case MEC_SEA1: /* 0x24 */
640 *data = mec_sea[0];
641 break;
642 case MEC_SSA2: /* 0x28 */
643 *data = mec_ssa[1] | (mec_wpr[1] << 23);
644 break;
645 case MEC_SEA2: /* 0x2c */
646 *data = mec_sea[1];
647 break;
648
649 case MEC_ISR: /* 0x44 */
650 *data = mec_isr;
651 break;
652
653 case MEC_IPR: /* 0x48 */
654 *data = mec_ipr;
655 break;
656
657 case MEC_IMR: /* 0x4c */
658 *data = mec_imr;
659 break;
660
661 case MEC_IFR: /* 0x54 */
662 *data = mec_ifr;
663 break;
664
665 case MEC_RTC_COUNTER: /* 0x80 */
666 *data = rtc_counter_read();
667 break;
668 case MEC_RTC_SCALER: /* 0x84 */
669 if (rtc_enabled)
670 *data = rtc_scaler - (now() - rtc_scaler_start);
671 else
672 *data = rtc_scaler;
673 break;
674
675 case MEC_GPT_COUNTER: /* 0x88 */
676 *data = gpt_counter_read();
677 break;
678
679 case MEC_GPT_SCALER: /* 0x8c */
680 if (rtc_enabled)
681 *data = gpt_scaler - (now() - gpt_scaler_start);
682 else
683 *data = gpt_scaler;
684 break;
685
686
687 case MEC_SFSR: /* 0xA0 */
688 *data = mec_sfsr;
689 break;
690
691 case MEC_FFAR: /* 0xA4 */
692 *data = mec_ffar;
693 break;
694
695 case SIM_LOAD:
696 fname[find] = 0;
697 if (find == 0)
698 strcpy(fname, "simload");
699 find = bfd_load(fname);
700 if (find == -1)
701 *data = 0;
702 else
703 *data = 1;
704 find = 0;
705 break;
706
707 case MEC_ERSR: /* 0xB0 */
708 *data = mec_ersr;
709 break;
710
711 case MEC_TCR: /* 0xD0 */
712 *data = mec_tcr;
713 break;
714
715 case MEC_UARTA: /* 0xE0 */
716 case MEC_UARTB: /* 0xE4 */
717 if (asi != 0xb) {
718 set_sfsr(MEC_ACC, addr, asi, 1);
719 return 1;
720 }
721 *data = read_uart(addr);
722 break;
723
724 case MEC_UART_CTRL: /* 0xE8 */
725
726 *data = read_uart(addr);
727 break;
728
729 case 0xF4: /* simulator RAM size in bytes */
730 *data = 4096*1024;
731 break;
732
733 case 0xF8: /* simulator ROM size in bytes */
734 *data = 1024*1024;
735 break;
736
737 default:
738 set_sfsr(MEC_ACC, addr, asi, 1);
739 return 1;
740 break;
741 }
742 return MOK;
743 }
744
745 static int
746 mec_write(uint32_t addr, uint32_t data)
747 {
748 if (sis_verbose > 1)
749 printf("MEC write a: %08x, d: %08x\n",addr,data);
750 switch (addr & 0x0ff) {
751
752 case MEC_MCR:
753 mec_mcr = data;
754 decode_mcr();
755 if (mec_mcr & 0x08000) mecparerror();
756 break;
757
758 case MEC_SFR:
759 if (mec_mcr & 0x2) {
760 sys_reset();
761 mec_ersr = 0x4000;
762 if (sis_verbose)
763 printf(" Software reset issued\n");
764 }
765 break;
766
767 case MEC_IOCR:
768 mec_iocr = data;
769 if (mec_iocr & 0xC0C0C0C0) mecparerror();
770 break;
771
772 case MEC_SSA1: /* 0x20 */
773 if (data & 0xFE000000) mecparerror();
774 mec_ssa[0] = data & 0x7fffff;
775 mec_wpr[0] = (data >> 23) & 0x03;
776 mem_accprot = mec_wpr[0] || mec_wpr[1];
777 if (sis_verbose && mec_wpr[0])
778 printf("Segment 1 memory protection enabled (0x02%06x - 0x02%06x)\n",
779 mec_ssa[0] << 2, mec_sea[0] << 2);
780 break;
781 case MEC_SEA1: /* 0x24 */
782 if (data & 0xFF800000) mecparerror();
783 mec_sea[0] = data & 0x7fffff;
784 break;
785 case MEC_SSA2: /* 0x28 */
786 if (data & 0xFE000000) mecparerror();
787 mec_ssa[1] = data & 0x7fffff;
788 mec_wpr[1] = (data >> 23) & 0x03;
789 mem_accprot = mec_wpr[0] || mec_wpr[1];
790 if (sis_verbose && mec_wpr[1])
791 printf("Segment 2 memory protection enabled (0x02%06x - 0x02%06x)\n",
792 mec_ssa[1] << 2, mec_sea[1] << 2);
793 break;
794 case MEC_SEA2: /* 0x2c */
795 if (data & 0xFF800000) mecparerror();
796 mec_sea[1] = data & 0x7fffff;
797 break;
798
799 case MEC_UARTA:
800 case MEC_UARTB:
801 if (data & 0xFFFFFF00) mecparerror();
802 case MEC_UART_CTRL:
803 if (data & 0xFF00FF00) mecparerror();
804 write_uart(addr, data);
805 break;
806
807 case MEC_GPT_RELOAD:
808 gpt_reload_set(data);
809 break;
810
811 case MEC_GPT_SCALER:
812 if (data & 0xFFFF0000) mecparerror();
813 gpt_scaler_set(data);
814 break;
815
816 case MEC_TIMER_CTRL:
817 if (data & 0xFFFFF0F0) mecparerror();
818 timer_ctrl(data);
819 break;
820
821 case MEC_RTC_RELOAD:
822 rtc_reload_set(data);
823 break;
824
825 case MEC_RTC_SCALER:
826 if (data & 0xFFFFFF00) mecparerror();
827 rtc_scaler_set(data);
828 break;
829
830 case MEC_SFSR: /* 0xA0 */
831 if (data & 0xFFFF0880) mecparerror();
832 mec_sfsr = 0x78;
833 break;
834
835 case MEC_ISR:
836 if (data & 0xFFFFE000) mecparerror();
837 mec_isr = data;
838 break;
839
840 case MEC_IMR: /* 0x4c */
841
842 if (data & 0xFFFF8001) mecparerror();
843 mec_imr = data & 0x7ffe;
844 chk_irq();
845 break;
846
847 case MEC_ICR: /* 0x50 */
848
849 if (data & 0xFFFF0001) mecparerror();
850 mec_ipr &= ~data & 0x0fffe;
851 chk_irq();
852 break;
853
854 case MEC_IFR: /* 0x54 */
855
856 if (mec_tcr & 0x080000) {
857 if (data & 0xFFFF0001) mecparerror();
858 mec_ifr = data & 0xfffe;
859 chk_irq();
860 }
861 break;
862 case SIM_LOAD:
863 fname[find++] = (char) data;
864 break;
865
866
867 case MEC_MEMCFG: /* 0x10 */
868 if (data & 0xC0E08000) mecparerror();
869 mec_memcfg = data;
870 decode_memcfg();
871 if (mec_memcfg & 0xc0e08000)
872 mecparerror();
873 break;
874
875 case MEC_WCR: /* 0x18 */
876 mec_wcr = data;
877 decode_wcr();
878 break;
879
880 case MEC_ERSR: /* 0xB0 */
881 if (mec_tcr & 0x100000)
882 if (data & 0xFFFFEFC0) mecparerror();
883 mec_ersr = data & 0x103f;
884 break;
885
886 case MEC_TCR: /* 0xD0 */
887 if (data & 0xFFE1FFC0) mecparerror();
888 mec_tcr = data & 0x1e003f;
889 break;
890
891 case MEC_WDOG: /* 0x60 */
892 wdog_scaler = (data >> 16) & 0x0ff;
893 wdog_counter = data & 0x0ffff;
894 wdog_rst_delay = data >> 24;
895 wdog_rston = 0;
896 if (wdog_status == stopped)
897 wdog_start();
898 wdog_status = enabled;
899 break;
900
901 case MEC_TRAPD: /* 0x64 */
902 if (wdog_status == init) {
903 wdog_status = disabled;
904 if (sis_verbose)
905 printf("Watchdog disabled\n");
906 }
907 break;
908
909 case MEC_PWDR:
910 if (mec_mcr & 1)
911 wait_for_irq();
912 break;
913
914 default:
915 set_sfsr(MEC_ACC, addr, 0xb, 0);
916 return 1;
917 break;
918 }
919 return MOK;
920 }
921
922
923 /* MEC UARTS */
924
925 static int ifd1 = -1, ifd2 = -1, ofd1 = -1, ofd2 = -1;
926
927 void
928 init_stdio(void)
929 {
930 if (dumbio)
931 return; /* do nothing */
932 #ifdef HAVE_TERMIOS_H
933 if (!ifd1)
934 tcsetattr(0, TCSANOW, &ioc1);
935 if (!ifd2)
936 tcsetattr(0, TCSANOW, &ioc2);
937 #endif
938 }
939
940 void
941 restore_stdio(void)
942 {
943 if (dumbio)
944 return; /* do nothing */
945 #ifdef HAVE_TERMIOS_H
946 if (!ifd1)
947 tcsetattr(0, TCSANOW, &iocold1);
948 if (!ifd2)
949 tcsetattr(0, TCSANOW, &iocold2);
950 #endif
951 }
952
953 #define DO_STDIO_READ( _fd_, _buf_, _len_ ) \
954 ( dumbio \
955 ? (0) /* no bytes read, no delay */ \
956 : read( _fd_, _buf_, _len_ ) )
957
958
959 static void
960 port_init(void)
961 {
962
963 if (uben) {
964 f2in = stdin;
965 f1in = NULL;
966 f2out = stdout;
967 f1out = NULL;
968 } else {
969 f1in = stdin;
970 f2in = NULL;
971 f1out = stdout;
972 f2out = NULL;
973 }
974 if (uart_dev1[0] != 0) {
975 if ((fd1 = open(uart_dev1, O_RDWR | O_NONBLOCK)) < 0) {
976 printf("Warning, couldn't open output device %s\n", uart_dev1);
977 } else {
978 if (sis_verbose)
979 printf("serial port A on %s\n", uart_dev1);
980 f1in = f1out = fdopen(fd1, "r+");
981 setbuf(f1out, NULL);
982 f1open = 1;
983 }
984 }
985 if (f1in) ifd1 = fileno(f1in);
986 if (ifd1 == 0) {
987 if (sis_verbose)
988 printf("serial port A on stdin/stdout\n");
989 if (!dumbio) {
990 #ifdef HAVE_TERMIOS_H
991 tcgetattr(ifd1, &ioc1);
992 iocold1 = ioc1;
993 ioc1.c_lflag &= ~(ICANON | ECHO);
994 ioc1.c_cc[VMIN] = 0;
995 ioc1.c_cc[VTIME] = 0;
996 #endif
997 }
998 f1open = 1;
999 }
1000
1001 if (f1out) {
1002 ofd1 = fileno(f1out);
1003 if (!dumbio && ofd1 == 1) setbuf(f1out, NULL);
1004 }
1005
1006 if (uart_dev2[0] != 0) {
1007 if ((fd2 = open(uart_dev2, O_RDWR | O_NONBLOCK)) < 0) {
1008 printf("Warning, couldn't open output device %s\n", uart_dev2);
1009 } else {
1010 if (sis_verbose)
1011 printf("serial port B on %s\n", uart_dev2);
1012 f2in = f2out = fdopen(fd2, "r+");
1013 setbuf(f2out, NULL);
1014 f2open = 1;
1015 }
1016 }
1017 if (f2in) ifd2 = fileno(f2in);
1018 if (ifd2 == 0) {
1019 if (sis_verbose)
1020 printf("serial port B on stdin/stdout\n");
1021 if (!dumbio) {
1022 #ifdef HAVE_TERMIOS_H
1023 tcgetattr(ifd2, &ioc2);
1024 iocold2 = ioc2;
1025 ioc2.c_lflag &= ~(ICANON | ECHO);
1026 ioc2.c_cc[VMIN] = 0;
1027 ioc2.c_cc[VTIME] = 0;
1028 #endif
1029 }
1030 f2open = 1;
1031 }
1032
1033 if (f2out) {
1034 ofd2 = fileno(f2out);
1035 if (!dumbio && ofd2 == 1) setbuf(f2out, NULL);
1036 }
1037
1038 wnuma = wnumb = 0;
1039
1040 }
1041
1042 static uint32_t
1043 read_uart(uint32_t addr)
1044 {
1045 switch (addr & 0xff) {
1046
1047 case 0xE0: /* UART 1 */
1048 #ifndef _WIN32
1049 #ifdef FAST_UART
1050
1051 if (aind < anum) {
1052 if ((aind + 1) < anum)
1053 mec_irq(4);
1054 return (0x700 | (uint32_t) aq[aind++]);
1055 } else {
1056 if (f1open) {
1057 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1058 }
1059 if (anum > 0) {
1060 aind = 0;
1061 if ((aind + 1) < anum)
1062 mec_irq(4);
1063 return (0x700 | (uint32_t) aq[aind++]);
1064 } else {
1065 return (0x600 | (uint32_t) aq[aind]);
1066 }
1067
1068 }
1069 #else
1070 unsigned tmp = uarta_data;
1071 uarta_data &= ~UART_DR;
1072 uart_stat_reg &= ~UARTA_DR;
1073 return tmp;
1074 #endif
1075 #else
1076 return 0;
1077 #endif
1078 break;
1079
1080 case 0xE4: /* UART 2 */
1081 #ifndef _WIN32
1082 #ifdef FAST_UART
1083 if (bind < bnum) {
1084 if ((bind + 1) < bnum)
1085 mec_irq(5);
1086 return (0x700 | (uint32_t) bq[bind++]);
1087 } else {
1088 if (f2open) {
1089 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1090 }
1091 if (bnum > 0) {
1092 bind = 0;
1093 if ((bind + 1) < bnum)
1094 mec_irq(5);
1095 return (0x700 | (uint32_t) bq[bind++]);
1096 } else {
1097 return (0x600 | (uint32_t) bq[bind]);
1098 }
1099
1100 }
1101 #else
1102 unsigned tmp = uartb_data;
1103 uartb_data &= ~UART_DR;
1104 uart_stat_reg &= ~UARTB_DR;
1105 return tmp;
1106 #endif
1107 #else
1108 return 0;
1109 #endif
1110 break;
1111
1112 case 0xE8: /* UART status register */
1113 #ifndef _WIN32
1114 #ifdef FAST_UART
1115
1116 Ucontrol = 0;
1117 if (aind < anum) {
1118 Ucontrol |= 0x00000001;
1119 } else {
1120 if (f1open) {
1121 anum = DO_STDIO_READ(ifd1, aq, UARTBUF);
1122 }
1123 if (anum > 0) {
1124 Ucontrol |= 0x00000001;
1125 aind = 0;
1126 mec_irq(4);
1127 }
1128 }
1129 if (bind < bnum) {
1130 Ucontrol |= 0x00010000;
1131 } else {
1132 if (f2open) {
1133 bnum = DO_STDIO_READ(ifd2, bq, UARTBUF);
1134 }
1135 if (bnum > 0) {
1136 Ucontrol |= 0x00010000;
1137 bind = 0;
1138 mec_irq(5);
1139 }
1140 }
1141
1142 Ucontrol |= 0x00060006;
1143 return Ucontrol;
1144 #else
1145 return uart_stat_reg;
1146 #endif
1147 #else
1148 return 0x00060006;
1149 #endif
1150 break;
1151 default:
1152 if (sis_verbose)
1153 printf("Read from unimplemented MEC register (%x)\n", addr);
1154
1155 }
1156 return 0;
1157 }
1158
1159 static void
1160 write_uart(uint32_t addr, uint32_t data)
1161 {
1162 unsigned char c;
1163
1164 c = (unsigned char) data;
1165 switch (addr & 0xff) {
1166
1167 case 0xE0: /* UART A */
1168 #ifdef FAST_UART
1169 if (f1open) {
1170 if (wnuma < UARTBUF)
1171 wbufa[wnuma++] = c;
1172 else {
1173 while (wnuma)
1174 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1175 wbufa[wnuma++] = c;
1176 }
1177 }
1178 mec_irq(4);
1179 #else
1180 if (uart_stat_reg & UARTA_SRE) {
1181 uarta_sreg = c;
1182 uart_stat_reg &= ~UARTA_SRE;
1183 event(uarta_tx, 0, UART_TX_TIME);
1184 } else {
1185 uarta_hreg = c;
1186 uart_stat_reg &= ~UARTA_HRE;
1187 }
1188 #endif
1189 break;
1190
1191 case 0xE4: /* UART B */
1192 #ifdef FAST_UART
1193 if (f2open) {
1194 if (wnumb < UARTBUF)
1195 wbufb[wnumb++] = c;
1196 else {
1197 while (wnumb)
1198 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1199 wbufb[wnumb++] = c;
1200 }
1201 }
1202 mec_irq(5);
1203 #else
1204 if (uart_stat_reg & UARTB_SRE) {
1205 uartb_sreg = c;
1206 uart_stat_reg &= ~UARTB_SRE;
1207 event(uartb_tx, 0, UART_TX_TIME);
1208 } else {
1209 uartb_hreg = c;
1210 uart_stat_reg &= ~UARTB_HRE;
1211 }
1212 #endif
1213 break;
1214 case 0xE8: /* UART status register */
1215 #ifndef FAST_UART
1216 if (data & UARTA_CLR) {
1217 uart_stat_reg &= 0xFFFF0000;
1218 uart_stat_reg |= UARTA_SRE | UARTA_HRE;
1219 }
1220 if (data & UARTB_CLR) {
1221 uart_stat_reg &= 0x0000FFFF;
1222 uart_stat_reg |= UARTB_SRE | UARTB_HRE;
1223 }
1224 #endif
1225 break;
1226 default:
1227 if (sis_verbose)
1228 printf("Write to unimplemented MEC register (%x)\n", addr);
1229
1230 }
1231 }
1232
1233 static void
1234 flush_uart(void)
1235 {
1236 while (wnuma && f1open)
1237 wnuma -= fwrite(wbufa, 1, wnuma, f1out);
1238 while (wnumb && f2open)
1239 wnumb -= fwrite(wbufb, 1, wnumb, f2out);
1240 }
1241
1242 ATTRIBUTE_UNUSED
1243 static void
1244 uarta_tx(int32_t arg ATTRIBUTE_UNUSED)
1245 {
1246
1247 while (f1open && fwrite(&uarta_sreg, 1, 1, f1out) != 1);
1248 if (uart_stat_reg & UARTA_HRE) {
1249 uart_stat_reg |= UARTA_SRE;
1250 } else {
1251 uarta_sreg = uarta_hreg;
1252 uart_stat_reg |= UARTA_HRE;
1253 event(uarta_tx, 0, UART_TX_TIME);
1254 }
1255 mec_irq(4);
1256 }
1257
1258 ATTRIBUTE_UNUSED
1259 static void
1260 uartb_tx(int32_t arg ATTRIBUTE_UNUSED)
1261 {
1262 while (f2open && fwrite(&uartb_sreg, 1, 1, f2out) != 1);
1263 if (uart_stat_reg & UARTB_HRE) {
1264 uart_stat_reg |= UARTB_SRE;
1265 } else {
1266 uartb_sreg = uartb_hreg;
1267 uart_stat_reg |= UARTB_HRE;
1268 event(uartb_tx, 0, UART_TX_TIME);
1269 }
1270 mec_irq(5);
1271 }
1272
1273 ATTRIBUTE_UNUSED
1274 static void
1275 uart_rx(int32_t arg ATTRIBUTE_UNUSED)
1276 {
1277 int32_t rsize;
1278 char rxd;
1279
1280
1281 rsize = 0;
1282 if (f1open)
1283 rsize = DO_STDIO_READ(ifd1, &rxd, 1);
1284 if (rsize > 0) {
1285 uarta_data = UART_DR | rxd;
1286 if (uart_stat_reg & UARTA_HRE)
1287 uarta_data |= UART_THE;
1288 if (uart_stat_reg & UARTA_SRE)
1289 uarta_data |= UART_TSE;
1290 if (uart_stat_reg & UARTA_DR) {
1291 uart_stat_reg |= UARTA_OR;
1292 mec_irq(7); /* UART error interrupt */
1293 }
1294 uart_stat_reg |= UARTA_DR;
1295 mec_irq(4);
1296 }
1297 rsize = 0;
1298 if (f2open)
1299 rsize = DO_STDIO_READ(ifd2, &rxd, 1);
1300 if (rsize) {
1301 uartb_data = UART_DR | rxd;
1302 if (uart_stat_reg & UARTB_HRE)
1303 uartb_data |= UART_THE;
1304 if (uart_stat_reg & UARTB_SRE)
1305 uartb_data |= UART_TSE;
1306 if (uart_stat_reg & UARTB_DR) {
1307 uart_stat_reg |= UARTB_OR;
1308 mec_irq(7); /* UART error interrupt */
1309 }
1310 uart_stat_reg |= UARTB_DR;
1311 mec_irq(5);
1312 }
1313 event(uart_rx, 0, UART_RX_TIME);
1314 }
1315
1316 static void
1317 uart_intr(int32_t arg ATTRIBUTE_UNUSED)
1318 {
1319 read_uart(0xE8); /* Check for UART interrupts every 1000 clk */
1320 flush_uart(); /* Flush UART ports */
1321 event(uart_intr, 0, UART_FLUSH_TIME);
1322 }
1323
1324
1325 static void
1326 uart_irq_start(void)
1327 {
1328 #ifdef FAST_UART
1329 event(uart_intr, 0, UART_FLUSH_TIME);
1330 #else
1331 #ifndef _WIN32
1332 event(uart_rx, 0, UART_RX_TIME);
1333 #endif
1334 #endif
1335 }
1336
1337 /* Watch-dog */
1338
1339 static void
1340 wdog_intr(int32_t arg ATTRIBUTE_UNUSED)
1341 {
1342 if (wdog_status == disabled) {
1343 wdog_status = stopped;
1344 } else {
1345
1346 if (wdog_counter) {
1347 wdog_counter--;
1348 event(wdog_intr, 0, wdog_scaler + 1);
1349 } else {
1350 if (wdog_rston) {
1351 printf("Watchdog reset!\n");
1352 sys_reset();
1353 mec_ersr = 0xC000;
1354 } else {
1355 mec_irq(15);
1356 wdog_rston = 1;
1357 wdog_counter = wdog_rst_delay;
1358 event(wdog_intr, 0, wdog_scaler + 1);
1359 }
1360 }
1361 }
1362 }
1363
1364 static void
1365 wdog_start(void)
1366 {
1367 event(wdog_intr, 0, wdog_scaler + 1);
1368 if (sis_verbose)
1369 printf("Watchdog started, scaler = %d, counter = %d\n",
1370 wdog_scaler, wdog_counter);
1371 }
1372
1373
1374 /* MEC timers */
1375
1376
1377 static void
1378 rtc_intr(int32_t arg ATTRIBUTE_UNUSED)
1379 {
1380 if (rtc_counter == 0) {
1381
1382 mec_irq(13);
1383 if (rtc_cr)
1384 rtc_counter = rtc_reload;
1385 else
1386 rtc_se = 0;
1387 } else
1388 rtc_counter -= 1;
1389 if (rtc_se) {
1390 event(rtc_intr, 0, rtc_scaler + 1);
1391 rtc_scaler_start = now();
1392 rtc_enabled = 1;
1393 } else {
1394 if (sis_verbose)
1395 printf("RTC stopped\n\r");
1396 rtc_enabled = 0;
1397 }
1398 }
1399
1400 static void
1401 rtc_start(void)
1402 {
1403 if (sis_verbose)
1404 printf("RTC started (period %d)\n\r", rtc_scaler + 1);
1405 event(rtc_intr, 0, rtc_scaler + 1);
1406 rtc_scaler_start = now();
1407 rtc_enabled = 1;
1408 }
1409
1410 static uint32_t
1411 rtc_counter_read(void)
1412 {
1413 return rtc_counter;
1414 }
1415
1416 static void
1417 rtc_scaler_set(uint32_t val)
1418 {
1419 rtc_scaler = val & 0x0ff; /* eight-bit scaler only */
1420 }
1421
1422 static void
1423 rtc_reload_set(uint32_t val)
1424 {
1425 rtc_reload = val;
1426 }
1427
1428 static void
1429 gpt_intr(int32_t arg ATTRIBUTE_UNUSED)
1430 {
1431 if (gpt_counter == 0) {
1432 mec_irq(12);
1433 if (gpt_cr)
1434 gpt_counter = gpt_reload;
1435 else
1436 gpt_se = 0;
1437 } else
1438 gpt_counter -= 1;
1439 if (gpt_se) {
1440 event(gpt_intr, 0, gpt_scaler + 1);
1441 gpt_scaler_start = now();
1442 gpt_enabled = 1;
1443 } else {
1444 if (sis_verbose)
1445 printf("GPT stopped\n\r");
1446 gpt_enabled = 0;
1447 }
1448 }
1449
1450 static void
1451 gpt_start(void)
1452 {
1453 if (sis_verbose)
1454 printf("GPT started (period %d)\n\r", gpt_scaler + 1);
1455 event(gpt_intr, 0, gpt_scaler + 1);
1456 gpt_scaler_start = now();
1457 gpt_enabled = 1;
1458 }
1459
1460 static uint32_t
1461 gpt_counter_read(void)
1462 {
1463 return gpt_counter;
1464 }
1465
1466 static void
1467 gpt_scaler_set(uint32_t val)
1468 {
1469 gpt_scaler = val & 0x0ffff; /* 16-bit scaler */
1470 }
1471
1472 static void
1473 gpt_reload_set(uint32_t val)
1474 {
1475 gpt_reload = val;
1476 }
1477
1478 static void
1479 timer_ctrl(uint32_t val)
1480 {
1481
1482 rtc_cr = ((val & TCR_TCRCR) != 0);
1483 if (val & TCR_TCRCL) {
1484 rtc_counter = rtc_reload;
1485 }
1486 if (val & TCR_TCRSL) {
1487 }
1488 rtc_se = ((val & TCR_TCRSE) != 0);
1489 if (rtc_se && (rtc_enabled == 0))
1490 rtc_start();
1491
1492 gpt_cr = (val & TCR_GACR);
1493 if (val & TCR_GACL) {
1494 gpt_counter = gpt_reload;
1495 }
1496 if (val & TCR_GACL) {
1497 }
1498 gpt_se = (val & TCR_GASE) >> 2;
1499 if (gpt_se && (gpt_enabled == 0))
1500 gpt_start();
1501 }
1502
1503 /* Store data in host byte order. MEM points to the beginning of the
1504 emulated memory; WADDR contains the index the emulated memory,
1505 DATA points to words in host byte order to be stored. SZ contains log(2)
1506 of the number of bytes to retrieve, and can be 0 (1 byte), 1 (one half-word),
1507 2 (one word), or 3 (two words); WS should return the number of
1508 wait-states. */
1509
1510 static void
1511 store_bytes (unsigned char *mem, uint32_t waddr, uint32_t *data, int32_t sz,
1512 int32_t *ws)
1513 {
1514 switch (sz) {
1515 case 0:
1516 waddr ^= EBT;
1517 mem[waddr] = *data & 0x0ff;
1518 *ws = mem_ramw_ws + 3;
1519 break;
1520 case 1:
1521 #ifdef HOST_LITTLE_ENDIAN
1522 waddr ^= 2;
1523 #endif
1524 memcpy (&mem[waddr], data, 2);
1525 *ws = mem_ramw_ws + 3;
1526 break;
1527 case 2:
1528 memcpy (&mem[waddr], data, 4);
1529 *ws = mem_ramw_ws;
1530 break;
1531 case 3:
1532 memcpy (&mem[waddr], data, 8);
1533 *ws = 2 * mem_ramw_ws + STD_WS;
1534 break;
1535 }
1536 }
1537
1538
1539 /* Memory emulation */
1540
1541 int
1542 memory_iread (uint32_t addr, uint32_t *data, uint32_t *ws)
1543 {
1544 uint32_t asi;
1545 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1546 memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
1547 *ws = mem_ramr_ws;
1548 return 0;
1549 } else if (addr < mem_romsz) {
1550 memcpy (data, &romb[addr & ~3], 4);
1551 *ws = mem_romr_ws;
1552 return 0;
1553 }
1554
1555 if (sis_verbose)
1556 printf ("Memory exception at %x (illegal address)\n", addr);
1557 if (sregs.psr & 0x080)
1558 asi = 9;
1559 else
1560 asi = 8;
1561 set_sfsr (UIMP_ACC, addr, asi, 1);
1562 *ws = MEM_EX_WS;
1563 return 1;
1564 }
1565
1566 int
1567 memory_read(int32_t asi, uint32_t addr, void *data, int32_t sz, int32_t *ws)
1568 {
1569 int32_t mexc;
1570
1571 #ifdef ERRINJ
1572 if (errmec) {
1573 if (sis_verbose)
1574 printf("Inserted MEC error %d\n",errmec);
1575 set_sfsr(errmec, addr, asi, 1);
1576 if (errmec == 5) mecparerror();
1577 if (errmec == 6) iucomperr();
1578 errmec = 0;
1579 return 1;
1580 }
1581 #endif
1582
1583 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1584 memcpy (data, &ramb[addr & mem_rammask & ~3], 4);
1585 *ws = mem_ramr_ws;
1586 return 0;
1587 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1588 mexc = mec_read(addr, asi, data);
1589 if (mexc) {
1590 set_sfsr(MEC_ACC, addr, asi, 1);
1591 *ws = MEM_EX_WS;
1592 } else {
1593 *ws = 0;
1594 }
1595 return mexc;
1596
1597 #ifdef ERA
1598
1599 } else if (era) {
1600 if ((addr < 0x100000) ||
1601 ((addr>= 0x80000000) && (addr < 0x80100000))) {
1602 memcpy (data, &romb[addr & ROM_MASK & ~3], 4);
1603 *ws = 4;
1604 return 0;
1605 } else if ((addr >= 0x10000000) &&
1606 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1607 (mec_iocr & 0x10)) {
1608 memcpy (data, &erareg, 4);
1609 return 0;
1610 }
1611
1612 } else if (addr < mem_romsz) {
1613 memcpy (data, &romb[addr & ~3], 4);
1614 *ws = mem_romr_ws;
1615 return 0;
1616 #else
1617 } else if (addr < mem_romsz) {
1618 memcpy (data, &romb[addr & ~3], 4);
1619 *ws = mem_romr_ws;
1620 return 0;
1621 #endif
1622
1623 }
1624
1625 if (sis_verbose)
1626 printf ("Memory exception at %x (illegal address)\n", addr);
1627 set_sfsr(UIMP_ACC, addr, asi, 1);
1628 *ws = MEM_EX_WS;
1629 return 1;
1630 }
1631
1632 int
1633 memory_write(int32_t asi, uint32_t addr, uint32_t *data, int32_t sz, int32_t *ws)
1634 {
1635 uint32_t byte_addr;
1636 uint32_t byte_mask;
1637 uint32_t waddr;
1638 uint32_t *ram;
1639 int32_t mexc;
1640 int i;
1641 int wphit[2];
1642
1643 #ifdef ERRINJ
1644 if (errmec) {
1645 if (sis_verbose)
1646 printf("Inserted MEC error %d\n",errmec);
1647 set_sfsr(errmec, addr, asi, 0);
1648 if (errmec == 5) mecparerror();
1649 if (errmec == 6) iucomperr();
1650 errmec = 0;
1651 return 1;
1652 }
1653 #endif
1654
1655 if ((addr >= mem_ramstart) && (addr < (mem_ramstart + mem_ramsz))) {
1656 if (mem_accprot) {
1657
1658 waddr = (addr & 0x7fffff) >> 2;
1659 for (i = 0; i < 2; i++)
1660 wphit[i] =
1661 (((asi == 0xa) && (mec_wpr[i] & 1)) ||
1662 ((asi == 0xb) && (mec_wpr[i] & 2))) &&
1663 ((waddr >= mec_ssa[i]) && ((waddr | (sz == 3)) < mec_sea[i]));
1664
1665 if (((mem_blockprot) && (wphit[0] || wphit[1])) ||
1666 ((!mem_blockprot) &&
1667 !((mec_wpr[0] && wphit[0]) || (mec_wpr[1] && wphit[1]))
1668 )) {
1669 if (sis_verbose)
1670 printf("Memory access protection error at 0x%08x\n", addr);
1671 set_sfsr(PROT_EXC, addr, asi, 0);
1672 *ws = MEM_EX_WS;
1673 return 1;
1674 }
1675 }
1676 waddr = addr & mem_rammask;
1677 store_bytes (ramb, waddr, data, sz, ws);
1678 return 0;
1679 } else if ((addr >= MEC_START) && (addr < MEC_END)) {
1680 if ((sz != 2) || (asi != 0xb)) {
1681 set_sfsr(MEC_ACC, addr, asi, 0);
1682 *ws = MEM_EX_WS;
1683 return 1;
1684 }
1685 mexc = mec_write(addr, *data);
1686 if (mexc) {
1687 set_sfsr(MEC_ACC, addr, asi, 0);
1688 *ws = MEM_EX_WS;
1689 } else {
1690 *ws = 0;
1691 }
1692 return mexc;
1693
1694 #ifdef ERA
1695
1696 } else if (era) {
1697 if ((erareg & 2) &&
1698 ((addr < 0x100000) || ((addr >= 0x80000000) && (addr < 0x80100000)))) {
1699 addr &= ROM_MASK;
1700 *ws = sz == 3 ? 8 : 4;
1701 store_bytes (romb, addr, data, sz, ws);
1702 return 0;
1703 } else if ((addr >= 0x10000000) &&
1704 (addr < (0x10000000 + (512 << (mec_iocr & 0x0f)))) &&
1705 (mec_iocr & 0x10)) {
1706 erareg = *data & 0x0e;
1707 return 0;
1708 }
1709
1710 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1711 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1712 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1713
1714 *ws = mem_romw_ws + 1;
1715 if (sz == 3)
1716 *ws += mem_romw_ws + STD_WS;
1717 store_bytes (romb, addr, data, sz, ws);
1718 return 0;
1719
1720 #else
1721 } else if ((addr < mem_romsz) && (mec_memcfg & 0x10000) && (wrp) &&
1722 (((mec_memcfg & 0x20000) && (sz > 1)) ||
1723 (!(mec_memcfg & 0x20000) && (sz == 0)))) {
1724
1725 *ws = mem_romw_ws + 1;
1726 if (sz == 3)
1727 *ws += mem_romw_ws + STD_WS;
1728 store_bytes (romb, addr, data, sz, ws);
1729 return 0;
1730
1731 #endif
1732
1733 }
1734
1735 *ws = MEM_EX_WS;
1736 set_sfsr(UIMP_ACC, addr, asi, 0);
1737 return 1;
1738 }
1739
1740 static void *
1741 get_mem_ptr(uint32_t addr, uint32_t size)
1742 {
1743 if ((addr + size) < ROM_SZ) {
1744 return &romb[addr];
1745 } else if ((addr >= mem_ramstart) && ((addr + size) < mem_ramend)) {
1746 return &ramb[addr & mem_rammask];
1747 }
1748
1749 #ifdef ERA
1750 else if ((era) && ((addr <0x100000) ||
1751 ((addr >= (unsigned) 0x80000000) && ((addr + size) < (unsigned) 0x80100000)))) {
1752 return &romb[addr & ROM_MASK];
1753 }
1754 #endif
1755
1756 return (void *) -1;
1757 }
1758
1759 int
1760 sis_memory_write(uint32_t addr, const void *data, uint32_t length)
1761 {
1762 void *mem;
1763
1764 if ((mem = get_mem_ptr(addr, length)) == ((void *) -1))
1765 return 0;
1766
1767 memcpy(mem, data, length);
1768 return length;
1769 }
1770
1771 int
1772 sis_memory_read(uint32_t addr, void *data, uint32_t length)
1773 {
1774 char *mem;
1775
1776 if ((mem = get_mem_ptr(addr, length)) == ((void *) -1))
1777 return 0;
1778
1779 memcpy(data, mem, length);
1780 return length;
1781 }
1782
1783 extern struct pstate sregs;
1784
1785 void
1786 boot_init (void)
1787 {
1788 mec_write(MEC_WCR, 0); /* zero waitstates */
1789 mec_write(MEC_TRAPD, 0); /* turn off watch-dog */
1790 mec_write(MEC_RTC_SCALER, sregs.freq - 1); /* generate 1 MHz RTC tick */
1791 mec_write(MEC_MEMCFG, (3 << 18) | (4 << 10)); /* 1 MB ROM, 4 MB RAM */
1792 sregs.wim = 2;
1793 sregs.psr = 0x110010e0;
1794 sregs.r[30] = RAM_END;
1795 sregs.r[14] = sregs.r[30] - 96 * 4;
1796 mec_mcr |= 1; /* power-down enabled */
1797 }
The GNU Binutils are a collection of binary tools.