1 /* Intel 386 target-dependent stuff.
3 Copyright (C) 1988-2023 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 #include "opcode/i386.h"
22 #include "arch-utils.h"
24 #include "dummy-frame.h"
25 #include "dwarf2/frame.h"
27 #include "frame-base.h"
28 #include "frame-unwind.h"
37 #include "reggroups.h"
42 #include "target-float.h"
47 #include "i386-tdep.h"
48 #include "i387-tdep.h"
49 #include "gdbsupport/x86-xstate.h"
54 #include "record-full.h"
55 #include "target-descriptions.h"
56 #include "arch/i386.h"
61 #include "stap-probe.h"
62 #include "user-regs.h"
63 #include "cli/cli-utils.h"
64 #include "expression.h"
65 #include "parser-defs.h"
68 #include <unordered_set>
75 static const char * const i386_register_names
[] =
77 "eax", "ecx", "edx", "ebx",
78 "esp", "ebp", "esi", "edi",
79 "eip", "eflags", "cs", "ss",
80 "ds", "es", "fs", "gs",
81 "st0", "st1", "st2", "st3",
82 "st4", "st5", "st6", "st7",
83 "fctrl", "fstat", "ftag", "fiseg",
84 "fioff", "foseg", "fooff", "fop",
85 "xmm0", "xmm1", "xmm2", "xmm3",
86 "xmm4", "xmm5", "xmm6", "xmm7",
90 static const char * const i386_zmm_names
[] =
92 "zmm0", "zmm1", "zmm2", "zmm3",
93 "zmm4", "zmm5", "zmm6", "zmm7"
96 static const char * const i386_zmmh_names
[] =
98 "zmm0h", "zmm1h", "zmm2h", "zmm3h",
99 "zmm4h", "zmm5h", "zmm6h", "zmm7h"
102 static const char * const i386_k_names
[] =
104 "k0", "k1", "k2", "k3",
105 "k4", "k5", "k6", "k7"
108 static const char * const i386_ymm_names
[] =
110 "ymm0", "ymm1", "ymm2", "ymm3",
111 "ymm4", "ymm5", "ymm6", "ymm7",
114 static const char * const i386_ymmh_names
[] =
116 "ymm0h", "ymm1h", "ymm2h", "ymm3h",
117 "ymm4h", "ymm5h", "ymm6h", "ymm7h",
120 static const char * const i386_mpx_names
[] =
122 "bnd0raw", "bnd1raw", "bnd2raw", "bnd3raw", "bndcfgu", "bndstatus"
125 static const char * const i386_pkeys_names
[] =
130 /* Register names for MPX pseudo-registers. */
132 static const char * const i386_bnd_names
[] =
134 "bnd0", "bnd1", "bnd2", "bnd3"
137 /* Register names for MMX pseudo-registers. */
139 static const char * const i386_mmx_names
[] =
141 "mm0", "mm1", "mm2", "mm3",
142 "mm4", "mm5", "mm6", "mm7"
145 /* Register names for byte pseudo-registers. */
147 static const char * const i386_byte_names
[] =
149 "al", "cl", "dl", "bl",
150 "ah", "ch", "dh", "bh"
153 /* Register names for word pseudo-registers. */
155 static const char * const i386_word_names
[] =
157 "ax", "cx", "dx", "bx",
161 /* Constant used for reading/writing pseudo registers. In 64-bit mode, we have
162 16 lower ZMM regs that extend corresponding xmm/ymm registers. In addition,
163 we have 16 upper ZMM regs that have to be handled differently. */
165 const int num_lower_zmm_regs
= 16;
170 i386_mmx_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
172 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
173 int mm0_regnum
= tdep
->mm0_regnum
;
178 regnum
-= mm0_regnum
;
179 return regnum
>= 0 && regnum
< tdep
->num_mmx_regs
;
185 i386_byte_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
187 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
189 regnum
-= tdep
->al_regnum
;
190 return regnum
>= 0 && regnum
< tdep
->num_byte_regs
;
196 i386_word_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
198 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
200 regnum
-= tdep
->ax_regnum
;
201 return regnum
>= 0 && regnum
< tdep
->num_word_regs
;
204 /* Dword register? */
207 i386_dword_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
209 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
210 int eax_regnum
= tdep
->eax_regnum
;
215 regnum
-= eax_regnum
;
216 return regnum
>= 0 && regnum
< tdep
->num_dword_regs
;
219 /* AVX512 register? */
222 i386_zmmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
224 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
225 int zmm0h_regnum
= tdep
->zmm0h_regnum
;
227 if (zmm0h_regnum
< 0)
230 regnum
-= zmm0h_regnum
;
231 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
235 i386_zmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
237 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
238 int zmm0_regnum
= tdep
->zmm0_regnum
;
243 regnum
-= zmm0_regnum
;
244 return regnum
>= 0 && regnum
< tdep
->num_zmm_regs
;
248 i386_k_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
250 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
251 int k0_regnum
= tdep
->k0_regnum
;
257 return regnum
>= 0 && regnum
< I387_NUM_K_REGS
;
261 i386_ymmh_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
263 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
264 int ymm0h_regnum
= tdep
->ymm0h_regnum
;
266 if (ymm0h_regnum
< 0)
269 regnum
-= ymm0h_regnum
;
270 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
276 i386_ymm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
278 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
279 int ymm0_regnum
= tdep
->ymm0_regnum
;
284 regnum
-= ymm0_regnum
;
285 return regnum
>= 0 && regnum
< tdep
->num_ymm_regs
;
289 i386_ymmh_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
291 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
292 int ymm16h_regnum
= tdep
->ymm16h_regnum
;
294 if (ymm16h_regnum
< 0)
297 regnum
-= ymm16h_regnum
;
298 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
302 i386_ymm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
304 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
305 int ymm16_regnum
= tdep
->ymm16_regnum
;
307 if (ymm16_regnum
< 0)
310 regnum
-= ymm16_regnum
;
311 return regnum
>= 0 && regnum
< tdep
->num_ymm_avx512_regs
;
317 i386_bnd_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
319 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
320 int bnd0_regnum
= tdep
->bnd0_regnum
;
325 regnum
-= bnd0_regnum
;
326 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
332 i386_xmm_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
334 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
335 int num_xmm_regs
= I387_NUM_XMM_REGS (tdep
);
337 if (num_xmm_regs
== 0)
340 regnum
-= I387_XMM0_REGNUM (tdep
);
341 return regnum
>= 0 && regnum
< num_xmm_regs
;
344 /* XMM_512 register? */
347 i386_xmm_avx512_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
349 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
350 int num_xmm_avx512_regs
= I387_NUM_XMM_AVX512_REGS (tdep
);
352 if (num_xmm_avx512_regs
== 0)
355 regnum
-= I387_XMM16_REGNUM (tdep
);
356 return regnum
>= 0 && regnum
< num_xmm_avx512_regs
;
360 i386_mxcsr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
362 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
364 if (I387_NUM_XMM_REGS (tdep
) == 0)
367 return (regnum
== I387_MXCSR_REGNUM (tdep
));
373 i386_fp_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
375 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
377 if (I387_ST0_REGNUM (tdep
) < 0)
380 return (I387_ST0_REGNUM (tdep
) <= regnum
381 && regnum
< I387_FCTRL_REGNUM (tdep
));
385 i386_fpc_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
387 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
389 if (I387_ST0_REGNUM (tdep
) < 0)
392 return (I387_FCTRL_REGNUM (tdep
) <= regnum
393 && regnum
< I387_XMM0_REGNUM (tdep
));
396 /* BNDr (raw) register? */
399 i386_bndr_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
401 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
403 if (I387_BND0R_REGNUM (tdep
) < 0)
406 regnum
-= tdep
->bnd0r_regnum
;
407 return regnum
>= 0 && regnum
< I387_NUM_BND_REGS
;
410 /* BND control register? */
413 i386_mpx_ctrl_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
415 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
417 if (I387_BNDCFGU_REGNUM (tdep
) < 0)
420 regnum
-= I387_BNDCFGU_REGNUM (tdep
);
421 return regnum
>= 0 && regnum
< I387_NUM_MPX_CTRL_REGS
;
427 i386_pkru_regnum_p (struct gdbarch
*gdbarch
, int regnum
)
429 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
430 int pkru_regnum
= tdep
->pkru_regnum
;
435 regnum
-= pkru_regnum
;
436 return regnum
>= 0 && regnum
< I387_NUM_PKEYS_REGS
;
439 /* Return the name of register REGNUM, or the empty string if it is
440 an anonymous register. */
443 i386_register_name (struct gdbarch
*gdbarch
, int regnum
)
445 /* Hide the upper YMM registers. */
446 if (i386_ymmh_regnum_p (gdbarch
, regnum
))
449 /* Hide the upper YMM16-31 registers. */
450 if (i386_ymmh_avx512_regnum_p (gdbarch
, regnum
))
453 /* Hide the upper ZMM registers. */
454 if (i386_zmmh_regnum_p (gdbarch
, regnum
))
457 return tdesc_register_name (gdbarch
, regnum
);
460 /* Return the name of register REGNUM. */
463 i386_pseudo_register_name (struct gdbarch
*gdbarch
, int regnum
)
465 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
466 if (i386_bnd_regnum_p (gdbarch
, regnum
))
467 return i386_bnd_names
[regnum
- tdep
->bnd0_regnum
];
468 if (i386_mmx_regnum_p (gdbarch
, regnum
))
469 return i386_mmx_names
[regnum
- I387_MM0_REGNUM (tdep
)];
470 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
471 return i386_ymm_names
[regnum
- tdep
->ymm0_regnum
];
472 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
473 return i386_zmm_names
[regnum
- tdep
->zmm0_regnum
];
474 else if (i386_byte_regnum_p (gdbarch
, regnum
))
475 return i386_byte_names
[regnum
- tdep
->al_regnum
];
476 else if (i386_word_regnum_p (gdbarch
, regnum
))
477 return i386_word_names
[regnum
- tdep
->ax_regnum
];
479 internal_error (_("invalid regnum"));
482 /* Convert a dbx register number REG to the appropriate register
483 number used by GDB. */
486 i386_dbx_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
488 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
490 /* This implements what GCC calls the "default" register map
491 (dbx_register_map[]). */
493 if (reg
>= 0 && reg
<= 7)
495 /* General-purpose registers. The debug info calls %ebp
496 register 4, and %esp register 5. */
503 else if (reg
>= 12 && reg
<= 19)
505 /* Floating-point registers. */
506 return reg
- 12 + I387_ST0_REGNUM (tdep
);
508 else if (reg
>= 21 && reg
<= 28)
511 int ymm0_regnum
= tdep
->ymm0_regnum
;
514 && i386_xmm_regnum_p (gdbarch
, reg
))
515 return reg
- 21 + ymm0_regnum
;
517 return reg
- 21 + I387_XMM0_REGNUM (tdep
);
519 else if (reg
>= 29 && reg
<= 36)
522 return reg
- 29 + I387_MM0_REGNUM (tdep
);
525 /* This will hopefully provoke a warning. */
526 return gdbarch_num_cooked_regs (gdbarch
);
529 /* Convert SVR4 DWARF register number REG to the appropriate register number
533 i386_svr4_dwarf_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
535 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
537 /* This implements the GCC register map that tries to be compatible
538 with the SVR4 C compiler for DWARF (svr4_dbx_register_map[]). */
540 /* The SVR4 register numbering includes %eip and %eflags, and
541 numbers the floating point registers differently. */
542 if (reg
>= 0 && reg
<= 9)
544 /* General-purpose registers. */
547 else if (reg
>= 11 && reg
<= 18)
549 /* Floating-point registers. */
550 return reg
- 11 + I387_ST0_REGNUM (tdep
);
552 else if (reg
>= 21 && reg
<= 36)
554 /* The SSE and MMX registers have the same numbers as with dbx. */
555 return i386_dbx_reg_to_regnum (gdbarch
, reg
);
560 case 37: return I387_FCTRL_REGNUM (tdep
);
561 case 38: return I387_FSTAT_REGNUM (tdep
);
562 case 39: return I387_MXCSR_REGNUM (tdep
);
563 case 40: return I386_ES_REGNUM
;
564 case 41: return I386_CS_REGNUM
;
565 case 42: return I386_SS_REGNUM
;
566 case 43: return I386_DS_REGNUM
;
567 case 44: return I386_FS_REGNUM
;
568 case 45: return I386_GS_REGNUM
;
574 /* Wrapper on i386_svr4_dwarf_reg_to_regnum to return
575 num_regs + num_pseudo_regs for other debug formats. */
578 i386_svr4_reg_to_regnum (struct gdbarch
*gdbarch
, int reg
)
580 int regnum
= i386_svr4_dwarf_reg_to_regnum (gdbarch
, reg
);
583 return gdbarch_num_cooked_regs (gdbarch
);
589 /* This is the variable that is set with "set disassembly-flavor", and
590 its legitimate values. */
591 static const char att_flavor
[] = "att";
592 static const char intel_flavor
[] = "intel";
593 static const char *const valid_flavors
[] =
599 static const char *disassembly_flavor
= att_flavor
;
602 /* Use the program counter to determine the contents and size of a
603 breakpoint instruction. Return a pointer to a string of bytes that
604 encode a breakpoint instruction, store the length of the string in
605 *LEN and optionally adjust *PC to point to the correct memory
606 location for inserting the breakpoint.
608 On the i386 we have a single breakpoint that fits in a single byte
609 and can be inserted anywhere.
611 This function is 64-bit safe. */
613 constexpr gdb_byte i386_break_insn
[] = { 0xcc }; /* int 3 */
615 typedef BP_MANIPULATION (i386_break_insn
) i386_breakpoint
;
618 /* Displaced instruction handling. */
620 /* Skip the legacy instruction prefixes in INSN.
621 Not all prefixes are valid for any particular insn
622 but we needn't care, the insn will fault if it's invalid.
623 The result is a pointer to the first opcode byte,
624 or NULL if we run off the end of the buffer. */
627 i386_skip_prefixes (gdb_byte
*insn
, size_t max_len
)
629 gdb_byte
*end
= insn
+ max_len
;
635 case DATA_PREFIX_OPCODE
:
636 case ADDR_PREFIX_OPCODE
:
637 case CS_PREFIX_OPCODE
:
638 case DS_PREFIX_OPCODE
:
639 case ES_PREFIX_OPCODE
:
640 case FS_PREFIX_OPCODE
:
641 case GS_PREFIX_OPCODE
:
642 case SS_PREFIX_OPCODE
:
643 case LOCK_PREFIX_OPCODE
:
644 case REPE_PREFIX_OPCODE
:
645 case REPNE_PREFIX_OPCODE
:
657 i386_absolute_jmp_p (const gdb_byte
*insn
)
659 /* jmp far (absolute address in operand). */
665 /* jump near, absolute indirect (/4). */
666 if ((insn
[1] & 0x38) == 0x20)
669 /* jump far, absolute indirect (/5). */
670 if ((insn
[1] & 0x38) == 0x28)
677 /* Return non-zero if INSN is a jump, zero otherwise. */
680 i386_jmp_p (const gdb_byte
*insn
)
682 /* jump short, relative. */
686 /* jump near, relative. */
690 return i386_absolute_jmp_p (insn
);
694 i386_absolute_call_p (const gdb_byte
*insn
)
696 /* call far, absolute. */
702 /* Call near, absolute indirect (/2). */
703 if ((insn
[1] & 0x38) == 0x10)
706 /* Call far, absolute indirect (/3). */
707 if ((insn
[1] & 0x38) == 0x18)
715 i386_ret_p (const gdb_byte
*insn
)
719 case 0xc2: /* ret near, pop N bytes. */
720 case 0xc3: /* ret near */
721 case 0xca: /* ret far, pop N bytes. */
722 case 0xcb: /* ret far */
723 case 0xcf: /* iret */
732 i386_call_p (const gdb_byte
*insn
)
734 if (i386_absolute_call_p (insn
))
737 /* call near, relative. */
744 /* Return non-zero if INSN is a system call, and set *LENGTHP to its
745 length in bytes. Otherwise, return zero. */
748 i386_syscall_p (const gdb_byte
*insn
, int *lengthp
)
750 /* Is it 'int $0x80'? */
751 if ((insn
[0] == 0xcd && insn
[1] == 0x80)
752 /* Or is it 'sysenter'? */
753 || (insn
[0] == 0x0f && insn
[1] == 0x34)
754 /* Or is it 'syscall'? */
755 || (insn
[0] == 0x0f && insn
[1] == 0x05))
764 /* The gdbarch insn_is_call method. */
767 i386_insn_is_call (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
769 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
771 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
772 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
774 return i386_call_p (insn
);
777 /* The gdbarch insn_is_ret method. */
780 i386_insn_is_ret (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
782 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
784 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
785 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
787 return i386_ret_p (insn
);
790 /* The gdbarch insn_is_jump method. */
793 i386_insn_is_jump (struct gdbarch
*gdbarch
, CORE_ADDR addr
)
795 gdb_byte buf
[I386_MAX_INSN_LEN
], *insn
;
797 read_code (addr
, buf
, I386_MAX_INSN_LEN
);
798 insn
= i386_skip_prefixes (buf
, I386_MAX_INSN_LEN
);
800 return i386_jmp_p (insn
);
803 /* Some kernels may run one past a syscall insn, so we have to cope. */
805 displaced_step_copy_insn_closure_up
806 i386_displaced_step_copy_insn (struct gdbarch
*gdbarch
,
807 CORE_ADDR from
, CORE_ADDR to
,
808 struct regcache
*regs
)
810 size_t len
= gdbarch_max_insn_length (gdbarch
);
811 std::unique_ptr
<i386_displaced_step_copy_insn_closure
> closure
812 (new i386_displaced_step_copy_insn_closure (len
));
813 gdb_byte
*buf
= closure
->buf
.data ();
815 read_memory (from
, buf
, len
);
817 /* GDB may get control back after the insn after the syscall.
818 Presumably this is a kernel bug.
819 If this is a syscall, make sure there's a nop afterwards. */
824 insn
= i386_skip_prefixes (buf
, len
);
825 if (insn
!= NULL
&& i386_syscall_p (insn
, &syscall_length
))
826 insn
[syscall_length
] = NOP_OPCODE
;
829 write_memory (to
, buf
, len
);
831 displaced_debug_printf ("%s->%s: %s",
832 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
833 bytes_to_string (buf
, len
).c_str ());
835 /* This is a work around for a problem with g++ 4.8. */
836 return displaced_step_copy_insn_closure_up (closure
.release ());
839 /* Fix up the state of registers and memory after having single-stepped
840 a displaced instruction. */
843 i386_displaced_step_fixup (struct gdbarch
*gdbarch
,
844 struct displaced_step_copy_insn_closure
*closure_
,
845 CORE_ADDR from
, CORE_ADDR to
,
846 struct regcache
*regs
, bool completed_p
)
848 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
850 /* The offset we applied to the instruction's address.
851 This could well be negative (when viewed as a signed 32-bit
852 value), but ULONGEST won't reflect that, so take care when
854 ULONGEST insn_offset
= to
- from
;
856 i386_displaced_step_copy_insn_closure
*closure
857 = (i386_displaced_step_copy_insn_closure
*) closure_
;
858 gdb_byte
*insn
= closure
->buf
.data ();
859 /* The start of the insn, needed in case we see some prefixes. */
860 gdb_byte
*insn_start
= insn
;
862 displaced_debug_printf ("fixup (%s, %s), insn = 0x%02x 0x%02x ...",
863 paddress (gdbarch
, from
), paddress (gdbarch
, to
),
866 /* The list of issues to contend with here is taken from
867 resume_execution in arch/i386/kernel/kprobes.c, Linux 2.6.20.
868 Yay for Free Software! */
870 /* Relocate the %eip, if necessary. */
872 /* The instruction recognizers we use assume any leading prefixes
873 have been skipped. */
875 /* This is the size of the buffer in closure. */
876 size_t max_insn_len
= gdbarch_max_insn_length (gdbarch
);
877 gdb_byte
*opcode
= i386_skip_prefixes (insn
, max_insn_len
);
878 /* If there are too many prefixes, just ignore the insn.
879 It will fault when run. */
884 /* Except in the case of absolute or indirect jump or call
885 instructions, or a return instruction, the new eip is relative to
886 the displaced instruction; make it relative. Well, signal
887 handler returns don't need relocation either, but we use the
888 value of %eip to recognize those; see below. */
890 || (!i386_absolute_jmp_p (insn
)
891 && !i386_absolute_call_p (insn
)
892 && !i386_ret_p (insn
)))
896 CORE_ADDR pc
= regcache_read_pc (regs
);
898 /* A signal trampoline system call changes the %eip, resuming
899 execution of the main program after the signal handler has
900 returned. That makes them like 'return' instructions; we
901 shouldn't relocate %eip.
903 But most system calls don't, and we do need to relocate %eip.
905 Our heuristic for distinguishing these cases: if stepping
906 over the system call instruction left control directly after
907 the instruction, the we relocate --- control almost certainly
908 doesn't belong in the displaced copy. Otherwise, we assume
909 the instruction has put control where it belongs, and leave
910 it unrelocated. Goodness help us if there are PC-relative
912 if (i386_syscall_p (insn
, &insn_len
)
913 && pc
!= to
+ (insn
- insn_start
) + insn_len
914 /* GDB can get control back after the insn after the syscall.
915 Presumably this is a kernel bug.
916 i386_displaced_step_copy_insn ensures it's a nop,
917 we add one to the length for it. */
918 && pc
!= to
+ (insn
- insn_start
) + insn_len
+ 1)
919 displaced_debug_printf ("syscall changed %%eip; not relocating");
922 ULONGEST eip
= (pc
- insn_offset
) & 0xffffffffUL
;
924 /* If we just stepped over a breakpoint insn, we don't backup
925 the pc on purpose; this is to match behaviour without
928 regcache_write_pc (regs
, eip
);
930 displaced_debug_printf ("relocated %%eip from %s to %s",
931 paddress (gdbarch
, pc
),
932 paddress (gdbarch
, eip
));
936 /* If the instruction was PUSHFL, then the TF bit will be set in the
937 pushed value, and should be cleared. We'll leave this for later,
938 since GDB already messes up the TF flag when stepping over a
941 /* If the instruction was a call, the return address now atop the
942 stack is the address following the copied instruction. We need
943 to make it the address following the original instruction. */
944 if (completed_p
&& i386_call_p (insn
))
948 const ULONGEST retaddr_len
= 4;
950 regcache_cooked_read_unsigned (regs
, I386_ESP_REGNUM
, &esp
);
951 retaddr
= read_memory_unsigned_integer (esp
, retaddr_len
, byte_order
);
952 retaddr
= (retaddr
- insn_offset
) & 0xffffffffUL
;
953 write_memory_unsigned_integer (esp
, retaddr_len
, byte_order
, retaddr
);
955 displaced_debug_printf ("relocated return addr at %s to %s",
956 paddress (gdbarch
, esp
),
957 paddress (gdbarch
, retaddr
));
962 append_insns (CORE_ADDR
*to
, ULONGEST len
, const gdb_byte
*buf
)
964 target_write_memory (*to
, buf
, len
);
969 i386_relocate_instruction (struct gdbarch
*gdbarch
,
970 CORE_ADDR
*to
, CORE_ADDR oldloc
)
972 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
973 gdb_byte buf
[I386_MAX_INSN_LEN
];
974 int offset
= 0, rel32
, newrel
;
976 gdb_byte
*insn
= buf
;
978 read_memory (oldloc
, buf
, I386_MAX_INSN_LEN
);
980 insn_length
= gdb_buffered_insn_length (gdbarch
, insn
,
981 I386_MAX_INSN_LEN
, oldloc
);
983 /* Get past the prefixes. */
984 insn
= i386_skip_prefixes (insn
, I386_MAX_INSN_LEN
);
986 /* Adjust calls with 32-bit relative addresses as push/jump, with
987 the address pushed being the location where the original call in
988 the user program would return to. */
991 gdb_byte push_buf
[16];
992 unsigned int ret_addr
;
994 /* Where "ret" in the original code will return to. */
995 ret_addr
= oldloc
+ insn_length
;
996 push_buf
[0] = 0x68; /* pushq $... */
997 store_unsigned_integer (&push_buf
[1], 4, byte_order
, ret_addr
);
999 append_insns (to
, 5, push_buf
);
1001 /* Convert the relative call to a relative jump. */
1004 /* Adjust the destination offset. */
1005 rel32
= extract_signed_integer (insn
+ 1, 4, byte_order
);
1006 newrel
= (oldloc
- *to
) + rel32
;
1007 store_signed_integer (insn
+ 1, 4, byte_order
, newrel
);
1009 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1010 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1011 hex_string (newrel
), paddress (gdbarch
, *to
));
1013 /* Write the adjusted jump into its displaced location. */
1014 append_insns (to
, 5, insn
);
1018 /* Adjust jumps with 32-bit relative addresses. Calls are already
1020 if (insn
[0] == 0xe9)
1022 /* Adjust conditional jumps. */
1023 else if (insn
[0] == 0x0f && (insn
[1] & 0xf0) == 0x80)
1028 rel32
= extract_signed_integer (insn
+ offset
, 4, byte_order
);
1029 newrel
= (oldloc
- *to
) + rel32
;
1030 store_signed_integer (insn
+ offset
, 4, byte_order
, newrel
);
1031 displaced_debug_printf ("adjusted insn rel32=%s at %s to rel32=%s at %s",
1032 hex_string (rel32
), paddress (gdbarch
, oldloc
),
1033 hex_string (newrel
), paddress (gdbarch
, *to
));
1036 /* Write the adjusted instructions into their displaced
1038 append_insns (to
, insn_length
, buf
);
1042 #ifdef I386_REGNO_TO_SYMMETRY
1043 #error "The Sequent Symmetry is no longer supported."
1046 /* According to the System V ABI, the registers %ebp, %ebx, %edi, %esi
1047 and %esp "belong" to the calling function. Therefore these
1048 registers should be saved if they're going to be modified. */
1050 /* The maximum number of saved registers. This should include all
1051 registers mentioned above, and %eip. */
1052 #define I386_NUM_SAVED_REGS I386_NUM_GREGS
1054 struct i386_frame_cache
1062 /* Saved registers. */
1063 CORE_ADDR saved_regs
[I386_NUM_SAVED_REGS
];
1068 /* Stack space reserved for local variables. */
1072 /* Allocate and initialize a frame cache. */
1074 static struct i386_frame_cache
*
1075 i386_alloc_frame_cache (void)
1077 struct i386_frame_cache
*cache
;
1080 cache
= FRAME_OBSTACK_ZALLOC (struct i386_frame_cache
);
1085 cache
->sp_offset
= -4;
1088 /* Saved registers. We initialize these to -1 since zero is a valid
1089 offset (that's where %ebp is supposed to be stored). */
1090 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
1091 cache
->saved_regs
[i
] = -1;
1092 cache
->saved_sp
= 0;
1093 cache
->saved_sp_reg
= -1;
1094 cache
->pc_in_eax
= 0;
1096 /* Frameless until proven otherwise. */
1102 /* If the instruction at PC is a jump, return the address of its
1103 target. Otherwise, return PC. */
1106 i386_follow_jump (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1108 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1113 if (target_read_code (pc
, &op
, 1))
1120 op
= read_code_unsigned_integer (pc
+ 1, 1, byte_order
);
1126 /* Relative jump: if data16 == 0, disp32, else disp16. */
1129 delta
= read_memory_integer (pc
+ 2, 2, byte_order
);
1131 /* Include the size of the jmp instruction (including the
1137 delta
= read_memory_integer (pc
+ 1, 4, byte_order
);
1139 /* Include the size of the jmp instruction. */
1144 /* Relative jump, disp8 (ignore data16). */
1145 delta
= read_memory_integer (pc
+ data16
+ 1, 1, byte_order
);
1147 delta
+= data16
+ 2;
1154 /* Check whether PC points at a prologue for a function returning a
1155 structure or union. If so, it updates CACHE and returns the
1156 address of the first instruction after the code sequence that
1157 removes the "hidden" argument from the stack or CURRENT_PC,
1158 whichever is smaller. Otherwise, return PC. */
1161 i386_analyze_struct_return (CORE_ADDR pc
, CORE_ADDR current_pc
,
1162 struct i386_frame_cache
*cache
)
1164 /* Functions that return a structure or union start with:
1167 xchgl %eax, (%esp) 0x87 0x04 0x24
1168 or xchgl %eax, 0(%esp) 0x87 0x44 0x24 0x00
1170 (the System V compiler puts out the second `xchg' instruction,
1171 and the assembler doesn't try to optimize it, so the 'sib' form
1172 gets generated). This sequence is used to get the address of the
1173 return buffer for a function that returns a structure. */
1174 static gdb_byte proto1
[3] = { 0x87, 0x04, 0x24 };
1175 static gdb_byte proto2
[4] = { 0x87, 0x44, 0x24, 0x00 };
1179 if (current_pc
<= pc
)
1182 if (target_read_code (pc
, &op
, 1))
1185 if (op
!= 0x58) /* popl %eax */
1188 if (target_read_code (pc
+ 1, buf
, 4))
1191 if (memcmp (buf
, proto1
, 3) != 0 && memcmp (buf
, proto2
, 4) != 0)
1194 if (current_pc
== pc
)
1196 cache
->sp_offset
+= 4;
1200 if (current_pc
== pc
+ 1)
1202 cache
->pc_in_eax
= 1;
1206 if (buf
[1] == proto1
[1])
1213 i386_skip_probe (CORE_ADDR pc
)
1215 /* A function may start with
1229 if (target_read_code (pc
, &op
, 1))
1232 if (op
== 0x68 || op
== 0x6a)
1236 /* Skip past the `pushl' instruction; it has either a one-byte or a
1237 four-byte operand, depending on the opcode. */
1243 /* Read the following 8 bytes, which should be `call _probe' (6
1244 bytes) followed by `addl $4,%esp' (2 bytes). */
1245 read_memory (pc
+ delta
, buf
, sizeof (buf
));
1246 if (buf
[0] == 0xe8 && buf
[6] == 0xc4 && buf
[7] == 0x4)
1247 pc
+= delta
+ sizeof (buf
);
1253 /* GCC 4.1 and later, can put code in the prologue to realign the
1254 stack pointer. Check whether PC points to such code, and update
1255 CACHE accordingly. Return the first instruction after the code
1256 sequence or CURRENT_PC, whichever is smaller. If we don't
1257 recognize the code, return PC. */
1260 i386_analyze_stack_align (CORE_ADDR pc
, CORE_ADDR current_pc
,
1261 struct i386_frame_cache
*cache
)
1263 /* There are 2 code sequences to re-align stack before the frame
1266 1. Use a caller-saved saved register:
1272 2. Use a callee-saved saved register:
1279 "andl $-XXX, %esp" can be either 3 bytes or 6 bytes:
1281 0x83 0xe4 0xf0 andl $-16, %esp
1282 0x81 0xe4 0x00 0xff 0xff 0xff andl $-256, %esp
1287 int offset
, offset_and
;
1288 static int regnums
[8] = {
1289 I386_EAX_REGNUM
, /* %eax */
1290 I386_ECX_REGNUM
, /* %ecx */
1291 I386_EDX_REGNUM
, /* %edx */
1292 I386_EBX_REGNUM
, /* %ebx */
1293 I386_ESP_REGNUM
, /* %esp */
1294 I386_EBP_REGNUM
, /* %ebp */
1295 I386_ESI_REGNUM
, /* %esi */
1296 I386_EDI_REGNUM
/* %edi */
1299 if (target_read_code (pc
, buf
, sizeof buf
))
1302 /* Check caller-saved saved register. The first instruction has
1303 to be "leal 4(%esp), %reg". */
1304 if (buf
[0] == 0x8d && buf
[2] == 0x24 && buf
[3] == 0x4)
1306 /* MOD must be binary 10 and R/M must be binary 100. */
1307 if ((buf
[1] & 0xc7) != 0x44)
1310 /* REG has register number. */
1311 reg
= (buf
[1] >> 3) & 7;
1316 /* Check callee-saved saved register. The first instruction
1317 has to be "pushl %reg". */
1318 if ((buf
[0] & 0xf8) != 0x50)
1324 /* The next instruction has to be "leal 8(%esp), %reg". */
1325 if (buf
[1] != 0x8d || buf
[3] != 0x24 || buf
[4] != 0x8)
1328 /* MOD must be binary 10 and R/M must be binary 100. */
1329 if ((buf
[2] & 0xc7) != 0x44)
1332 /* REG has register number. Registers in pushl and leal have to
1334 if (reg
!= ((buf
[2] >> 3) & 7))
1340 /* Rigister can't be %esp nor %ebp. */
1341 if (reg
== 4 || reg
== 5)
1344 /* The next instruction has to be "andl $-XXX, %esp". */
1345 if (buf
[offset
+ 1] != 0xe4
1346 || (buf
[offset
] != 0x81 && buf
[offset
] != 0x83))
1349 offset_and
= offset
;
1350 offset
+= buf
[offset
] == 0x81 ? 6 : 3;
1352 /* The next instruction has to be "pushl -4(%reg)". 8bit -4 is
1353 0xfc. REG must be binary 110 and MOD must be binary 01. */
1354 if (buf
[offset
] != 0xff
1355 || buf
[offset
+ 2] != 0xfc
1356 || (buf
[offset
+ 1] & 0xf8) != 0x70)
1359 /* R/M has register. Registers in leal and pushl have to be the
1361 if (reg
!= (buf
[offset
+ 1] & 7))
1364 if (current_pc
> pc
+ offset_and
)
1365 cache
->saved_sp_reg
= regnums
[reg
];
1367 return std::min (pc
+ offset
+ 3, current_pc
);
1370 /* Maximum instruction length we need to handle. */
1371 #define I386_MAX_MATCHED_INSN_LEN 6
1373 /* Instruction description. */
1377 gdb_byte insn
[I386_MAX_MATCHED_INSN_LEN
];
1378 gdb_byte mask
[I386_MAX_MATCHED_INSN_LEN
];
1381 /* Return whether instruction at PC matches PATTERN. */
1384 i386_match_pattern (CORE_ADDR pc
, struct i386_insn pattern
)
1388 if (target_read_code (pc
, &op
, 1))
1391 if ((op
& pattern
.mask
[0]) == pattern
.insn
[0])
1393 gdb_byte buf
[I386_MAX_MATCHED_INSN_LEN
- 1];
1394 int insn_matched
= 1;
1397 gdb_assert (pattern
.len
> 1);
1398 gdb_assert (pattern
.len
<= I386_MAX_MATCHED_INSN_LEN
);
1400 if (target_read_code (pc
+ 1, buf
, pattern
.len
- 1))
1403 for (i
= 1; i
< pattern
.len
; i
++)
1405 if ((buf
[i
- 1] & pattern
.mask
[i
]) != pattern
.insn
[i
])
1408 return insn_matched
;
1413 /* Search for the instruction at PC in the list INSN_PATTERNS. Return
1414 the first instruction description that matches. Otherwise, return
1417 static struct i386_insn
*
1418 i386_match_insn (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1420 struct i386_insn
*pattern
;
1422 for (pattern
= insn_patterns
; pattern
->len
> 0; pattern
++)
1424 if (i386_match_pattern (pc
, *pattern
))
1431 /* Return whether PC points inside a sequence of instructions that
1432 matches INSN_PATTERNS. */
1435 i386_match_insn_block (CORE_ADDR pc
, struct i386_insn
*insn_patterns
)
1437 CORE_ADDR current_pc
;
1439 struct i386_insn
*insn
;
1441 insn
= i386_match_insn (pc
, insn_patterns
);
1446 ix
= insn
- insn_patterns
;
1447 for (i
= ix
- 1; i
>= 0; i
--)
1449 current_pc
-= insn_patterns
[i
].len
;
1451 if (!i386_match_pattern (current_pc
, insn_patterns
[i
]))
1455 current_pc
= pc
+ insn
->len
;
1456 for (insn
= insn_patterns
+ ix
+ 1; insn
->len
> 0; insn
++)
1458 if (!i386_match_pattern (current_pc
, *insn
))
1461 current_pc
+= insn
->len
;
1467 /* Some special instructions that might be migrated by GCC into the
1468 part of the prologue that sets up the new stack frame. Because the
1469 stack frame hasn't been setup yet, no registers have been saved
1470 yet, and only the scratch registers %eax, %ecx and %edx can be
1473 static i386_insn i386_frame_setup_skip_insns
[] =
1475 /* Check for `movb imm8, r' and `movl imm32, r'.
1477 ??? Should we handle 16-bit operand-sizes here? */
1479 /* `movb imm8, %al' and `movb imm8, %ah' */
1480 /* `movb imm8, %cl' and `movb imm8, %ch' */
1481 { 2, { 0xb0, 0x00 }, { 0xfa, 0x00 } },
1482 /* `movb imm8, %dl' and `movb imm8, %dh' */
1483 { 2, { 0xb2, 0x00 }, { 0xfb, 0x00 } },
1484 /* `movl imm32, %eax' and `movl imm32, %ecx' */
1485 { 5, { 0xb8 }, { 0xfe } },
1486 /* `movl imm32, %edx' */
1487 { 5, { 0xba }, { 0xff } },
1489 /* Check for `mov imm32, r32'. Note that there is an alternative
1490 encoding for `mov m32, %eax'.
1492 ??? Should we handle SIB addressing here?
1493 ??? Should we handle 16-bit operand-sizes here? */
1495 /* `movl m32, %eax' */
1496 { 5, { 0xa1 }, { 0xff } },
1497 /* `movl m32, %eax' and `mov; m32, %ecx' */
1498 { 6, { 0x89, 0x05 }, {0xff, 0xf7 } },
1499 /* `movl m32, %edx' */
1500 { 6, { 0x89, 0x15 }, {0xff, 0xff } },
1502 /* Check for `xorl r32, r32' and the equivalent `subl r32, r32'.
1503 Because of the symmetry, there are actually two ways to encode
1504 these instructions; opcode bytes 0x29 and 0x2b for `subl' and
1505 opcode bytes 0x31 and 0x33 for `xorl'. */
1507 /* `subl %eax, %eax' */
1508 { 2, { 0x29, 0xc0 }, { 0xfd, 0xff } },
1509 /* `subl %ecx, %ecx' */
1510 { 2, { 0x29, 0xc9 }, { 0xfd, 0xff } },
1511 /* `subl %edx, %edx' */
1512 { 2, { 0x29, 0xd2 }, { 0xfd, 0xff } },
1513 /* `xorl %eax, %eax' */
1514 { 2, { 0x31, 0xc0 }, { 0xfd, 0xff } },
1515 /* `xorl %ecx, %ecx' */
1516 { 2, { 0x31, 0xc9 }, { 0xfd, 0xff } },
1517 /* `xorl %edx, %edx' */
1518 { 2, { 0x31, 0xd2 }, { 0xfd, 0xff } },
1522 /* Check whether PC points to an endbr32 instruction. */
1524 i386_skip_endbr (CORE_ADDR pc
)
1526 static const gdb_byte endbr32
[] = { 0xf3, 0x0f, 0x1e, 0xfb };
1528 gdb_byte buf
[sizeof (endbr32
)];
1530 /* Stop there if we can't read the code */
1531 if (target_read_code (pc
, buf
, sizeof (endbr32
)))
1534 /* If the instruction isn't an endbr32, stop */
1535 if (memcmp (buf
, endbr32
, sizeof (endbr32
)) != 0)
1538 return pc
+ sizeof (endbr32
);
1541 /* Check whether PC points to a no-op instruction. */
1543 i386_skip_noop (CORE_ADDR pc
)
1548 if (target_read_code (pc
, &op
, 1))
1554 /* Ignore `nop' instruction. */
1558 if (target_read_code (pc
, &op
, 1))
1562 /* Ignore no-op instruction `mov %edi, %edi'.
1563 Microsoft system dlls often start with
1564 a `mov %edi,%edi' instruction.
1565 The 5 bytes before the function start are
1566 filled with `nop' instructions.
1567 This pattern can be used for hot-patching:
1568 The `mov %edi, %edi' instruction can be replaced by a
1569 near jump to the location of the 5 `nop' instructions
1570 which can be replaced by a 32-bit jump to anywhere
1571 in the 32-bit address space. */
1573 else if (op
== 0x8b)
1575 if (target_read_code (pc
+ 1, &op
, 1))
1581 if (target_read_code (pc
, &op
, 1))
1591 /* Check whether PC points at a code that sets up a new stack frame.
1592 If so, it updates CACHE and returns the address of the first
1593 instruction after the sequence that sets up the frame or LIMIT,
1594 whichever is smaller. If we don't recognize the code, return PC. */
1597 i386_analyze_frame_setup (struct gdbarch
*gdbarch
,
1598 CORE_ADDR pc
, CORE_ADDR limit
,
1599 struct i386_frame_cache
*cache
)
1601 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1602 struct i386_insn
*insn
;
1609 if (target_read_code (pc
, &op
, 1))
1612 if (op
== 0x55) /* pushl %ebp */
1614 /* Take into account that we've executed the `pushl %ebp' that
1615 starts this instruction sequence. */
1616 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
1617 cache
->sp_offset
+= 4;
1620 /* If that's all, return now. */
1624 /* Check for some special instructions that might be migrated by
1625 GCC into the prologue and skip them. At this point in the
1626 prologue, code should only touch the scratch registers %eax,
1627 %ecx and %edx, so while the number of possibilities is sheer,
1630 Make sure we only skip these instructions if we later see the
1631 `movl %esp, %ebp' that actually sets up the frame. */
1632 while (pc
+ skip
< limit
)
1634 insn
= i386_match_insn (pc
+ skip
, i386_frame_setup_skip_insns
);
1641 /* If that's all, return now. */
1642 if (limit
<= pc
+ skip
)
1645 if (target_read_code (pc
+ skip
, &op
, 1))
1648 /* The i386 prologue looks like
1654 and a different prologue can be generated for atom.
1658 lea -0x10(%esp),%esp
1660 We handle both of them here. */
1664 /* Check for `movl %esp, %ebp' -- can be written in two ways. */
1666 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1672 if (read_code_unsigned_integer (pc
+ skip
+ 1, 1, byte_order
)
1677 case 0x8d: /* Check for 'lea (%ebp), %ebp'. */
1678 if (read_code_unsigned_integer (pc
+ skip
+ 1, 2, byte_order
)
1687 /* OK, we actually have a frame. We just don't know how large
1688 it is yet. Set its size to zero. We'll adjust it if
1689 necessary. We also now commit to skipping the special
1690 instructions mentioned before. */
1693 /* If that's all, return now. */
1697 /* Check for stack adjustment
1703 NOTE: You can't subtract a 16-bit immediate from a 32-bit
1704 reg, so we don't have to worry about a data16 prefix. */
1705 if (target_read_code (pc
, &op
, 1))
1709 /* `subl' with 8-bit immediate. */
1710 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1711 /* Some instruction starting with 0x83 other than `subl'. */
1714 /* `subl' with signed 8-bit immediate (though it wouldn't
1715 make sense to be negative). */
1716 cache
->locals
= read_code_integer (pc
+ 2, 1, byte_order
);
1719 else if (op
== 0x81)
1721 /* Maybe it is `subl' with a 32-bit immediate. */
1722 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0xec)
1723 /* Some instruction starting with 0x81 other than `subl'. */
1726 /* It is `subl' with a 32-bit immediate. */
1727 cache
->locals
= read_code_integer (pc
+ 2, 4, byte_order
);
1730 else if (op
== 0x8d)
1732 /* The ModR/M byte is 0x64. */
1733 if (read_code_unsigned_integer (pc
+ 1, 1, byte_order
) != 0x64)
1735 /* 'lea' with 8-bit displacement. */
1736 cache
->locals
= -1 * read_code_integer (pc
+ 3, 1, byte_order
);
1741 /* Some instruction other than `subl' nor 'lea'. */
1745 else if (op
== 0xc8) /* enter */
1747 cache
->locals
= read_code_unsigned_integer (pc
+ 1, 2, byte_order
);
1754 /* Check whether PC points at code that saves registers on the stack.
1755 If so, it updates CACHE and returns the address of the first
1756 instruction after the register saves or CURRENT_PC, whichever is
1757 smaller. Otherwise, return PC. */
1760 i386_analyze_register_saves (CORE_ADDR pc
, CORE_ADDR current_pc
,
1761 struct i386_frame_cache
*cache
)
1763 CORE_ADDR offset
= 0;
1767 if (cache
->locals
> 0)
1768 offset
-= cache
->locals
;
1769 for (i
= 0; i
< 8 && pc
< current_pc
; i
++)
1771 if (target_read_code (pc
, &op
, 1))
1773 if (op
< 0x50 || op
> 0x57)
1777 cache
->saved_regs
[op
- 0x50] = offset
;
1778 cache
->sp_offset
+= 4;
1785 /* Do a full analysis of the prologue at PC and update CACHE
1786 accordingly. Bail out early if CURRENT_PC is reached. Return the
1787 address where the analysis stopped.
1789 We handle these cases:
1791 The startup sequence can be at the start of the function, or the
1792 function can start with a branch to startup code at the end.
1794 %ebp can be set up with either the 'enter' instruction, or "pushl
1795 %ebp, movl %esp, %ebp" (`enter' is too slow to be useful, but was
1796 once used in the System V compiler).
1798 Local space is allocated just below the saved %ebp by either the
1799 'enter' instruction, or by "subl $<size>, %esp". 'enter' has a
1800 16-bit unsigned argument for space to allocate, and the 'addl'
1801 instruction could have either a signed byte, or 32-bit immediate.
1803 Next, the registers used by this function are pushed. With the
1804 System V compiler they will always be in the order: %edi, %esi,
1805 %ebx (and sometimes a harmless bug causes it to also save but not
1806 restore %eax); however, the code below is willing to see the pushes
1807 in any order, and will handle up to 8 of them.
1809 If the setup sequence is at the end of the function, then the next
1810 instruction will be a branch back to the start. */
1813 i386_analyze_prologue (struct gdbarch
*gdbarch
,
1814 CORE_ADDR pc
, CORE_ADDR current_pc
,
1815 struct i386_frame_cache
*cache
)
1817 pc
= i386_skip_endbr (pc
);
1818 pc
= i386_skip_noop (pc
);
1819 pc
= i386_follow_jump (gdbarch
, pc
);
1820 pc
= i386_analyze_struct_return (pc
, current_pc
, cache
);
1821 pc
= i386_skip_probe (pc
);
1822 pc
= i386_analyze_stack_align (pc
, current_pc
, cache
);
1823 pc
= i386_analyze_frame_setup (gdbarch
, pc
, current_pc
, cache
);
1824 return i386_analyze_register_saves (pc
, current_pc
, cache
);
1827 /* Return PC of first real instruction. */
1830 i386_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR start_pc
)
1832 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1834 static gdb_byte pic_pat
[6] =
1836 0xe8, 0, 0, 0, 0, /* call 0x0 */
1837 0x5b, /* popl %ebx */
1839 struct i386_frame_cache cache
;
1843 CORE_ADDR func_addr
;
1845 if (find_pc_partial_function (start_pc
, NULL
, &func_addr
, NULL
))
1847 CORE_ADDR post_prologue_pc
1848 = skip_prologue_using_sal (gdbarch
, func_addr
);
1849 struct compunit_symtab
*cust
= find_pc_compunit_symtab (func_addr
);
1851 /* LLVM backend (Clang/Flang) always emits a line note before the
1852 prologue and another one after. We trust clang and newer Intel
1853 compilers to emit usable line notes. */
1854 if (post_prologue_pc
1856 && cust
->producer () != NULL
1857 && (producer_is_llvm (cust
->producer ())
1858 || producer_is_icc_ge_19 (cust
->producer ()))))
1859 return std::max (start_pc
, post_prologue_pc
);
1863 pc
= i386_analyze_prologue (gdbarch
, start_pc
, 0xffffffff, &cache
);
1864 if (cache
.locals
< 0)
1867 /* Found valid frame setup. */
1869 /* The native cc on SVR4 in -K PIC mode inserts the following code
1870 to get the address of the global offset table (GOT) into register
1875 movl %ebx,x(%ebp) (optional)
1878 This code is with the rest of the prologue (at the end of the
1879 function), so we have to skip it to get to the first real
1880 instruction at the start of the function. */
1882 for (i
= 0; i
< 6; i
++)
1884 if (target_read_code (pc
+ i
, &op
, 1))
1887 if (pic_pat
[i
] != op
)
1894 if (target_read_code (pc
+ delta
, &op
, 1))
1897 if (op
== 0x89) /* movl %ebx, x(%ebp) */
1899 op
= read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
);
1901 if (op
== 0x5d) /* One byte offset from %ebp. */
1903 else if (op
== 0x9d) /* Four byte offset from %ebp. */
1905 else /* Unexpected instruction. */
1908 if (target_read_code (pc
+ delta
, &op
, 1))
1913 if (delta
> 0 && op
== 0x81
1914 && read_code_unsigned_integer (pc
+ delta
+ 1, 1, byte_order
)
1921 /* If the function starts with a branch (to startup code at the end)
1922 the last instruction should bring us back to the first
1923 instruction of the real code. */
1924 if (i386_follow_jump (gdbarch
, start_pc
) != start_pc
)
1925 pc
= i386_follow_jump (gdbarch
, pc
);
1930 /* Check that the code pointed to by PC corresponds to a call to
1931 __main, skip it if so. Return PC otherwise. */
1934 i386_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1936 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1939 if (target_read_code (pc
, &op
, 1))
1945 if (target_read_code (pc
+ 1, buf
, sizeof buf
) == 0)
1947 /* Make sure address is computed correctly as a 32bit
1948 integer even if CORE_ADDR is 64 bit wide. */
1949 struct bound_minimal_symbol s
;
1950 CORE_ADDR call_dest
;
1952 call_dest
= pc
+ 5 + extract_signed_integer (buf
, 4, byte_order
);
1953 call_dest
= call_dest
& 0xffffffffU
;
1954 s
= lookup_minimal_symbol_by_pc (call_dest
);
1955 if (s
.minsym
!= NULL
1956 && s
.minsym
->linkage_name () != NULL
1957 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1965 /* This function is 64-bit safe. */
1968 i386_unwind_pc (struct gdbarch
*gdbarch
, frame_info_ptr next_frame
)
1972 frame_unwind_register (next_frame
, gdbarch_pc_regnum (gdbarch
), buf
);
1973 return extract_typed_address (buf
, builtin_type (gdbarch
)->builtin_func_ptr
);
1977 /* Normal frames. */
1980 i386_frame_cache_1 (frame_info_ptr this_frame
,
1981 struct i386_frame_cache
*cache
)
1983 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1984 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1988 cache
->pc
= get_frame_func (this_frame
);
1990 /* In principle, for normal frames, %ebp holds the frame pointer,
1991 which holds the base address for the current stack frame.
1992 However, for functions that don't need it, the frame pointer is
1993 optional. For these "frameless" functions the frame pointer is
1994 actually the frame pointer of the calling frame. Signal
1995 trampolines are just a special case of a "frameless" function.
1996 They (usually) share their frame pointer with the frame that was
1997 in progress when the signal occurred. */
1999 get_frame_register (this_frame
, I386_EBP_REGNUM
, buf
);
2000 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
);
2001 if (cache
->base
== 0)
2007 /* For normal frames, %eip is stored at 4(%ebp). */
2008 cache
->saved_regs
[I386_EIP_REGNUM
] = 4;
2011 i386_analyze_prologue (gdbarch
, cache
->pc
, get_frame_pc (this_frame
),
2014 if (cache
->locals
< 0)
2016 /* We didn't find a valid frame, which means that CACHE->base
2017 currently holds the frame pointer for our calling frame. If
2018 we're at the start of a function, or somewhere half-way its
2019 prologue, the function's frame probably hasn't been fully
2020 setup yet. Try to reconstruct the base address for the stack
2021 frame by looking at the stack pointer. For truly "frameless"
2022 functions this might work too. */
2024 if (cache
->saved_sp_reg
!= -1)
2026 /* Saved stack pointer has been saved. */
2027 get_frame_register (this_frame
, cache
->saved_sp_reg
, buf
);
2028 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2030 /* We're halfway aligning the stack. */
2031 cache
->base
= ((cache
->saved_sp
- 4) & 0xfffffff0) - 4;
2032 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->saved_sp
- 4;
2034 /* This will be added back below. */
2035 cache
->saved_regs
[I386_EIP_REGNUM
] -= cache
->base
;
2037 else if (cache
->pc
!= 0
2038 || target_read_code (get_frame_pc (this_frame
), buf
, 1))
2040 /* We're in a known function, but did not find a frame
2041 setup. Assume that the function does not use %ebp.
2042 Alternatively, we may have jumped to an invalid
2043 address; in that case there is definitely no new
2045 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2046 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
)
2050 /* We're in an unknown function. We could not find the start
2051 of the function to analyze the prologue; our best option is
2052 to assume a typical frame layout with the caller's %ebp
2054 cache
->saved_regs
[I386_EBP_REGNUM
] = 0;
2057 if (cache
->saved_sp_reg
!= -1)
2059 /* Saved stack pointer has been saved (but the SAVED_SP_REG
2060 register may be unavailable). */
2061 if (cache
->saved_sp
== 0
2062 && deprecated_frame_register_read (this_frame
,
2063 cache
->saved_sp_reg
, buf
))
2064 cache
->saved_sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2066 /* Now that we have the base address for the stack frame we can
2067 calculate the value of %esp in the calling frame. */
2068 else if (cache
->saved_sp
== 0)
2069 cache
->saved_sp
= cache
->base
+ 8;
2071 /* Adjust all the saved registers such that they contain addresses
2072 instead of offsets. */
2073 for (i
= 0; i
< I386_NUM_SAVED_REGS
; i
++)
2074 if (cache
->saved_regs
[i
] != -1)
2075 cache
->saved_regs
[i
] += cache
->base
;
2080 static struct i386_frame_cache
*
2081 i386_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
2083 struct i386_frame_cache
*cache
;
2086 return (struct i386_frame_cache
*) *this_cache
;
2088 cache
= i386_alloc_frame_cache ();
2089 *this_cache
= cache
;
2093 i386_frame_cache_1 (this_frame
, cache
);
2095 catch (const gdb_exception_error
&ex
)
2097 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2105 i386_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
2106 struct frame_id
*this_id
)
2108 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2111 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2112 else if (cache
->base
== 0)
2114 /* This marks the outermost frame. */
2118 /* See the end of i386_push_dummy_call. */
2119 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2123 static enum unwind_stop_reason
2124 i386_frame_unwind_stop_reason (frame_info_ptr this_frame
,
2127 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2130 return UNWIND_UNAVAILABLE
;
2132 /* This marks the outermost frame. */
2133 if (cache
->base
== 0)
2134 return UNWIND_OUTERMOST
;
2136 return UNWIND_NO_REASON
;
2139 static struct value
*
2140 i386_frame_prev_register (frame_info_ptr this_frame
, void **this_cache
,
2143 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2145 gdb_assert (regnum
>= 0);
2147 /* The System V ABI says that:
2149 "The flags register contains the system flags, such as the
2150 direction flag and the carry flag. The direction flag must be
2151 set to the forward (that is, zero) direction before entry and
2152 upon exit from a function. Other user flags have no specified
2153 role in the standard calling sequence and are not preserved."
2155 To guarantee the "upon exit" part of that statement we fake a
2156 saved flags register that has its direction flag cleared.
2158 Note that GCC doesn't seem to rely on the fact that the direction
2159 flag is cleared after a function return; it always explicitly
2160 clears the flag before operations where it matters.
2162 FIXME: kettenis/20030316: I'm not quite sure whether this is the
2163 right thing to do. The way we fake the flags register here makes
2164 it impossible to change it. */
2166 if (regnum
== I386_EFLAGS_REGNUM
)
2170 val
= get_frame_register_unsigned (this_frame
, regnum
);
2172 return frame_unwind_got_constant (this_frame
, regnum
, val
);
2175 if (regnum
== I386_EIP_REGNUM
&& cache
->pc_in_eax
)
2176 return frame_unwind_got_register (this_frame
, regnum
, I386_EAX_REGNUM
);
2178 if (regnum
== I386_ESP_REGNUM
2179 && (cache
->saved_sp
!= 0 || cache
->saved_sp_reg
!= -1))
2181 /* If the SP has been saved, but we don't know where, then this
2182 means that SAVED_SP_REG register was found unavailable back
2183 when we built the cache. */
2184 if (cache
->saved_sp
== 0)
2185 return frame_unwind_got_register (this_frame
, regnum
,
2186 cache
->saved_sp_reg
);
2188 return frame_unwind_got_constant (this_frame
, regnum
,
2192 if (regnum
< I386_NUM_SAVED_REGS
&& cache
->saved_regs
[regnum
] != -1)
2193 return frame_unwind_got_memory (this_frame
, regnum
,
2194 cache
->saved_regs
[regnum
]);
2196 return frame_unwind_got_register (this_frame
, regnum
, regnum
);
2199 static const struct frame_unwind i386_frame_unwind
=
2203 i386_frame_unwind_stop_reason
,
2205 i386_frame_prev_register
,
2207 default_frame_sniffer
2210 /* Normal frames, but in a function epilogue. */
2212 /* Implement the stack_frame_destroyed_p gdbarch method.
2214 The epilogue is defined here as the 'ret' instruction, which will
2215 follow any instruction such as 'leave' or 'pop %ebp' that destroys
2216 the function's stack frame. */
2219 i386_stack_frame_destroyed_p (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
2222 if (target_read_memory (pc
, &insn
, 1))
2223 return 0; /* Can't read memory at pc. */
2225 if (insn
!= 0xc3) /* 'ret' instruction. */
2232 i386_epilogue_frame_sniffer_1 (const struct frame_unwind
*self
,
2233 frame_info_ptr this_frame
,
2234 void **this_prologue_cache
, bool override_p
)
2236 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2237 CORE_ADDR pc
= get_frame_pc (this_frame
);
2239 if (frame_relative_level (this_frame
) != 0)
2240 /* We're not in the inner frame, so assume we're not in an epilogue. */
2244 = compunit_epilogue_unwind_valid (find_pc_compunit_symtab (pc
));
2248 /* Don't override the symtab unwinders, skip
2249 "i386 epilogue override". */
2254 if (!unwind_valid_p
)
2255 /* "i386 epilogue override" unwinder already ran, skip
2260 /* Check whether we're in an epilogue. */
2261 return i386_stack_frame_destroyed_p (gdbarch
, pc
);
2265 i386_epilogue_override_frame_sniffer (const struct frame_unwind
*self
,
2266 frame_info_ptr this_frame
,
2267 void **this_prologue_cache
)
2269 return i386_epilogue_frame_sniffer_1 (self
, this_frame
, this_prologue_cache
,
2274 i386_epilogue_frame_sniffer (const struct frame_unwind
*self
,
2275 frame_info_ptr this_frame
,
2276 void **this_prologue_cache
)
2278 return i386_epilogue_frame_sniffer_1 (self
, this_frame
, this_prologue_cache
,
2282 static struct i386_frame_cache
*
2283 i386_epilogue_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
2285 struct i386_frame_cache
*cache
;
2289 return (struct i386_frame_cache
*) *this_cache
;
2291 cache
= i386_alloc_frame_cache ();
2292 *this_cache
= cache
;
2296 cache
->pc
= get_frame_func (this_frame
);
2298 /* At this point the stack looks as if we just entered the
2299 function, with the return address at the top of the
2301 sp
= get_frame_register_unsigned (this_frame
, I386_ESP_REGNUM
);
2302 cache
->base
= sp
+ cache
->sp_offset
;
2303 cache
->saved_sp
= cache
->base
+ 8;
2304 cache
->saved_regs
[I386_EIP_REGNUM
] = cache
->base
+ 4;
2308 catch (const gdb_exception_error
&ex
)
2310 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2317 static enum unwind_stop_reason
2318 i386_epilogue_frame_unwind_stop_reason (frame_info_ptr this_frame
,
2321 struct i386_frame_cache
*cache
=
2322 i386_epilogue_frame_cache (this_frame
, this_cache
);
2325 return UNWIND_UNAVAILABLE
;
2327 return UNWIND_NO_REASON
;
2331 i386_epilogue_frame_this_id (frame_info_ptr this_frame
,
2333 struct frame_id
*this_id
)
2335 struct i386_frame_cache
*cache
=
2336 i386_epilogue_frame_cache (this_frame
, this_cache
);
2339 (*this_id
) = frame_id_build_unavailable_stack (cache
->pc
);
2341 (*this_id
) = frame_id_build (cache
->base
+ 8, cache
->pc
);
2344 static struct value
*
2345 i386_epilogue_frame_prev_register (frame_info_ptr this_frame
,
2346 void **this_cache
, int regnum
)
2348 /* Make sure we've initialized the cache. */
2349 i386_epilogue_frame_cache (this_frame
, this_cache
);
2351 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2354 static const struct frame_unwind i386_epilogue_override_frame_unwind
=
2356 "i386 epilogue override",
2358 i386_epilogue_frame_unwind_stop_reason
,
2359 i386_epilogue_frame_this_id
,
2360 i386_epilogue_frame_prev_register
,
2362 i386_epilogue_override_frame_sniffer
2365 static const struct frame_unwind i386_epilogue_frame_unwind
=
2369 i386_epilogue_frame_unwind_stop_reason
,
2370 i386_epilogue_frame_this_id
,
2371 i386_epilogue_frame_prev_register
,
2373 i386_epilogue_frame_sniffer
2377 /* Stack-based trampolines. */
2379 /* These trampolines are used on cross x86 targets, when taking the
2380 address of a nested function. When executing these trampolines,
2381 no stack frame is set up, so we are in a similar situation as in
2382 epilogues and i386_epilogue_frame_this_id can be re-used. */
2384 /* Static chain passed in register. */
2386 static i386_insn i386_tramp_chain_in_reg_insns
[] =
2388 /* `movl imm32, %eax' and `movl imm32, %ecx' */
2389 { 5, { 0xb8 }, { 0xfe } },
2392 { 5, { 0xe9 }, { 0xff } },
2397 /* Static chain passed on stack (when regparm=3). */
2399 static i386_insn i386_tramp_chain_on_stack_insns
[] =
2402 { 5, { 0x68 }, { 0xff } },
2405 { 5, { 0xe9 }, { 0xff } },
2410 /* Return whether PC points inside a stack trampoline. */
2413 i386_in_stack_tramp_p (CORE_ADDR pc
)
2418 /* A stack trampoline is detected if no name is associated
2419 to the current pc and if it points inside a trampoline
2422 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
2426 if (target_read_memory (pc
, &insn
, 1))
2429 if (!i386_match_insn_block (pc
, i386_tramp_chain_in_reg_insns
)
2430 && !i386_match_insn_block (pc
, i386_tramp_chain_on_stack_insns
))
2437 i386_stack_tramp_frame_sniffer (const struct frame_unwind
*self
,
2438 frame_info_ptr this_frame
,
2441 if (frame_relative_level (this_frame
) == 0)
2442 return i386_in_stack_tramp_p (get_frame_pc (this_frame
));
2447 static const struct frame_unwind i386_stack_tramp_frame_unwind
=
2451 i386_epilogue_frame_unwind_stop_reason
,
2452 i386_epilogue_frame_this_id
,
2453 i386_epilogue_frame_prev_register
,
2455 i386_stack_tramp_frame_sniffer
2458 /* Generate a bytecode expression to get the value of the saved PC. */
2461 i386_gen_return_address (struct gdbarch
*gdbarch
,
2462 struct agent_expr
*ax
, struct axs_value
*value
,
2465 /* The following sequence assumes the traditional use of the base
2467 ax_reg (ax
, I386_EBP_REGNUM
);
2469 ax_simple (ax
, aop_add
);
2470 value
->type
= register_type (gdbarch
, I386_EIP_REGNUM
);
2471 value
->kind
= axs_lvalue_memory
;
2475 /* Signal trampolines. */
2477 static struct i386_frame_cache
*
2478 i386_sigtramp_frame_cache (frame_info_ptr this_frame
, void **this_cache
)
2480 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
2481 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
2482 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2483 struct i386_frame_cache
*cache
;
2488 return (struct i386_frame_cache
*) *this_cache
;
2490 cache
= i386_alloc_frame_cache ();
2494 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
2495 cache
->base
= extract_unsigned_integer (buf
, 4, byte_order
) - 4;
2497 addr
= tdep
->sigcontext_addr (this_frame
);
2498 if (tdep
->sc_reg_offset
)
2502 gdb_assert (tdep
->sc_num_regs
<= I386_NUM_SAVED_REGS
);
2504 for (i
= 0; i
< tdep
->sc_num_regs
; i
++)
2505 if (tdep
->sc_reg_offset
[i
] != -1)
2506 cache
->saved_regs
[i
] = addr
+ tdep
->sc_reg_offset
[i
];
2510 cache
->saved_regs
[I386_EIP_REGNUM
] = addr
+ tdep
->sc_pc_offset
;
2511 cache
->saved_regs
[I386_ESP_REGNUM
] = addr
+ tdep
->sc_sp_offset
;
2516 catch (const gdb_exception_error
&ex
)
2518 if (ex
.error
!= NOT_AVAILABLE_ERROR
)
2522 *this_cache
= cache
;
2526 static enum unwind_stop_reason
2527 i386_sigtramp_frame_unwind_stop_reason (frame_info_ptr this_frame
,
2530 struct i386_frame_cache
*cache
=
2531 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2534 return UNWIND_UNAVAILABLE
;
2536 return UNWIND_NO_REASON
;
2540 i386_sigtramp_frame_this_id (frame_info_ptr this_frame
, void **this_cache
,
2541 struct frame_id
*this_id
)
2543 struct i386_frame_cache
*cache
=
2544 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2547 (*this_id
) = frame_id_build_unavailable_stack (get_frame_pc (this_frame
));
2550 /* See the end of i386_push_dummy_call. */
2551 (*this_id
) = frame_id_build (cache
->base
+ 8, get_frame_pc (this_frame
));
2555 static struct value
*
2556 i386_sigtramp_frame_prev_register (frame_info_ptr this_frame
,
2557 void **this_cache
, int regnum
)
2559 /* Make sure we've initialized the cache. */
2560 i386_sigtramp_frame_cache (this_frame
, this_cache
);
2562 return i386_frame_prev_register (this_frame
, this_cache
, regnum
);
2566 i386_sigtramp_frame_sniffer (const struct frame_unwind
*self
,
2567 frame_info_ptr this_frame
,
2568 void **this_prologue_cache
)
2570 gdbarch
*arch
= get_frame_arch (this_frame
);
2571 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (arch
);
2573 /* We shouldn't even bother if we don't have a sigcontext_addr
2575 if (tdep
->sigcontext_addr
== NULL
)
2578 if (tdep
->sigtramp_p
!= NULL
)
2580 if (tdep
->sigtramp_p (this_frame
))
2584 if (tdep
->sigtramp_start
!= 0)
2586 CORE_ADDR pc
= get_frame_pc (this_frame
);
2588 gdb_assert (tdep
->sigtramp_end
!= 0);
2589 if (pc
>= tdep
->sigtramp_start
&& pc
< tdep
->sigtramp_end
)
2596 static const struct frame_unwind i386_sigtramp_frame_unwind
=
2600 i386_sigtramp_frame_unwind_stop_reason
,
2601 i386_sigtramp_frame_this_id
,
2602 i386_sigtramp_frame_prev_register
,
2604 i386_sigtramp_frame_sniffer
2609 i386_frame_base_address (frame_info_ptr this_frame
, void **this_cache
)
2611 struct i386_frame_cache
*cache
= i386_frame_cache (this_frame
, this_cache
);
2616 static const struct frame_base i386_frame_base
=
2619 i386_frame_base_address
,
2620 i386_frame_base_address
,
2621 i386_frame_base_address
2624 static struct frame_id
2625 i386_dummy_id (struct gdbarch
*gdbarch
, frame_info_ptr this_frame
)
2629 fp
= get_frame_register_unsigned (this_frame
, I386_EBP_REGNUM
);
2631 /* See the end of i386_push_dummy_call. */
2632 return frame_id_build (fp
+ 8, get_frame_pc (this_frame
));
2635 /* _Decimal128 function return values need 16-byte alignment on the
2639 i386_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
2641 return sp
& -(CORE_ADDR
)16;
2645 /* Figure out where the longjmp will land. Slurp the args out of the
2646 stack. We expect the first arg to be a pointer to the jmp_buf
2647 structure from which we extract the address that we will land at.
2648 This address is copied into PC. This routine returns non-zero on
2652 i386_get_longjmp_target (frame_info_ptr frame
, CORE_ADDR
*pc
)
2655 CORE_ADDR sp
, jb_addr
;
2656 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
2657 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2658 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
2659 int jb_pc_offset
= tdep
->jb_pc_offset
;
2661 /* If JB_PC_OFFSET is -1, we have no way to find out where the
2662 longjmp will land. */
2663 if (jb_pc_offset
== -1)
2666 get_frame_register (frame
, I386_ESP_REGNUM
, buf
);
2667 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
2668 if (target_read_memory (sp
+ 4, buf
, 4))
2671 jb_addr
= extract_unsigned_integer (buf
, 4, byte_order
);
2672 if (target_read_memory (jb_addr
+ jb_pc_offset
, buf
, 4))
2675 *pc
= extract_unsigned_integer (buf
, 4, byte_order
);
2680 /* Check whether TYPE must be 16-byte-aligned when passed as a
2681 function argument. 16-byte vectors, _Decimal128 and structures or
2682 unions containing such types must be 16-byte-aligned; other
2683 arguments are 4-byte-aligned. */
2686 i386_16_byte_align_p (struct type
*type
)
2688 type
= check_typedef (type
);
2689 if ((type
->code () == TYPE_CODE_DECFLOAT
2690 || (type
->code () == TYPE_CODE_ARRAY
&& type
->is_vector ()))
2691 && type
->length () == 16)
2693 if (type
->code () == TYPE_CODE_ARRAY
)
2694 return i386_16_byte_align_p (type
->target_type ());
2695 if (type
->code () == TYPE_CODE_STRUCT
2696 || type
->code () == TYPE_CODE_UNION
)
2699 for (i
= 0; i
< type
->num_fields (); i
++)
2701 if (type
->field (i
).is_static ())
2703 if (i386_16_byte_align_p (type
->field (i
).type ()))
2710 /* Implementation for set_gdbarch_push_dummy_code. */
2713 i386_push_dummy_code (struct gdbarch
*gdbarch
, CORE_ADDR sp
, CORE_ADDR funaddr
,
2714 struct value
**args
, int nargs
, struct type
*value_type
,
2715 CORE_ADDR
*real_pc
, CORE_ADDR
*bp_addr
,
2716 struct regcache
*regcache
)
2718 /* Use 0xcc breakpoint - 1 byte. */
2722 /* Keep the stack aligned. */
2726 /* The "push_dummy_call" gdbarch method, optionally with the thiscall
2727 calling convention. */
2730 i386_thiscall_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2731 struct regcache
*regcache
, CORE_ADDR bp_addr
,
2732 int nargs
, struct value
**args
, CORE_ADDR sp
,
2733 function_call_return_method return_method
,
2734 CORE_ADDR struct_addr
, bool thiscall
)
2736 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
2742 /* BND registers can be in arbitrary values at the moment of the
2743 inferior call. This can cause boundary violations that are not
2744 due to a real bug or even desired by the user. The best to be done
2745 is set the BND registers to allow access to the whole memory, INIT
2746 state, before pushing the inferior call. */
2747 i387_reset_bnd_regs (gdbarch
, regcache
);
2749 /* Determine the total space required for arguments and struct
2750 return address in a first pass (allowing for 16-byte-aligned
2751 arguments), then push arguments in a second pass. */
2753 for (write_pass
= 0; write_pass
< 2; write_pass
++)
2755 int args_space_used
= 0;
2757 if (return_method
== return_method_struct
)
2761 /* Push value address. */
2762 store_unsigned_integer (buf
, 4, byte_order
, struct_addr
);
2763 write_memory (sp
, buf
, 4);
2764 args_space_used
+= 4;
2770 for (i
= thiscall
? 1 : 0; i
< nargs
; i
++)
2772 int len
= args
[i
]->enclosing_type ()->length ();
2776 if (i386_16_byte_align_p (args
[i
]->enclosing_type ()))
2777 args_space_used
= align_up (args_space_used
, 16);
2779 write_memory (sp
+ args_space_used
,
2780 args
[i
]->contents_all ().data (), len
);
2781 /* The System V ABI says that:
2783 "An argument's size is increased, if necessary, to make it a
2784 multiple of [32-bit] words. This may require tail padding,
2785 depending on the size of the argument."
2787 This makes sure the stack stays word-aligned. */
2788 args_space_used
+= align_up (len
, 4);
2792 if (i386_16_byte_align_p (args
[i
]->enclosing_type ()))
2793 args_space
= align_up (args_space
, 16);
2794 args_space
+= align_up (len
, 4);
2802 /* The original System V ABI only requires word alignment,
2803 but modern incarnations need 16-byte alignment in order
2804 to support SSE. Since wasting a few bytes here isn't
2805 harmful we unconditionally enforce 16-byte alignment. */
2810 /* Store return address. */
2812 store_unsigned_integer (buf
, 4, byte_order
, bp_addr
);
2813 write_memory (sp
, buf
, 4);
2815 /* Finally, update the stack pointer... */
2816 store_unsigned_integer (buf
, 4, byte_order
, sp
);
2817 regcache
->cooked_write (I386_ESP_REGNUM
, buf
);
2819 /* ...and fake a frame pointer. */
2820 regcache
->cooked_write (I386_EBP_REGNUM
, buf
);
2822 /* The 'this' pointer needs to be in ECX. */
2824 regcache
->cooked_write (I386_ECX_REGNUM
,
2825 args
[0]->contents_all ().data ());
2827 /* If the PLT is position-independent, the SYSTEM V ABI requires %ebx to be
2828 set to the address of the GOT when doing a call to a PLT address.
2829 Note that we do not try to determine whether the PLT is
2830 position-independent, we just set the register regardless. */
2831 CORE_ADDR func_addr
= find_function_addr (function
, nullptr, nullptr);
2832 if (in_plt_section (func_addr
))
2834 struct objfile
*objf
= nullptr;
2835 asection
*asect
= nullptr;
2836 obj_section
*osect
= nullptr;
2838 /* Get object file containing func_addr. */
2839 obj_section
*func_section
= find_pc_section (func_addr
);
2840 if (func_section
!= nullptr)
2841 objf
= func_section
->objfile
;
2843 if (objf
!= nullptr)
2845 /* Get corresponding .got.plt or .got section. */
2846 asect
= bfd_get_section_by_name (objf
->obfd
.get (), ".got.plt");
2847 if (asect
== nullptr)
2848 asect
= bfd_get_section_by_name (objf
->obfd
.get (), ".got");
2851 if (asect
!= nullptr)
2852 /* Translate asection to obj_section. */
2853 osect
= maint_obj_section_from_bfd_section (objf
->obfd
.get (),
2856 if (osect
!= nullptr)
2858 /* Store the section address in %ebx. */
2859 store_unsigned_integer (buf
, 4, byte_order
, osect
->addr ());
2860 regcache
->cooked_write (I386_EBX_REGNUM
, buf
);
2864 /* If we would only do this for a position-independent PLT, it would
2865 make sense to issue a warning here. */
2869 /* MarkK wrote: This "+ 8" is all over the place:
2870 (i386_frame_this_id, i386_sigtramp_frame_this_id,
2871 i386_dummy_id). It's there, since all frame unwinders for
2872 a given target have to agree (within a certain margin) on the
2873 definition of the stack address of a frame. Otherwise frame id
2874 comparison might not work correctly. Since DWARF2/GCC uses the
2875 stack address *before* the function call as a frame's CFA. On
2876 the i386, when %ebp is used as a frame pointer, the offset
2877 between the contents %ebp and the CFA as defined by GCC. */
2881 /* Implement the "push_dummy_call" gdbarch method. */
2884 i386_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
2885 struct regcache
*regcache
, CORE_ADDR bp_addr
, int nargs
,
2886 struct value
**args
, CORE_ADDR sp
,
2887 function_call_return_method return_method
,
2888 CORE_ADDR struct_addr
)
2890 return i386_thiscall_push_dummy_call (gdbarch
, function
, regcache
, bp_addr
,
2891 nargs
, args
, sp
, return_method
,
2892 struct_addr
, false);
2895 /* These registers are used for returning integers (and on some
2896 targets also for returning `struct' and `union' values when their
2897 size and alignment match an integer type). */
2898 #define LOW_RETURN_REGNUM I386_EAX_REGNUM /* %eax */
2899 #define HIGH_RETURN_REGNUM I386_EDX_REGNUM /* %edx */
2901 /* Read, for architecture GDBARCH, a function return value of TYPE
2902 from REGCACHE, and copy that into VALBUF. */
2905 i386_extract_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2906 struct regcache
*regcache
, gdb_byte
*valbuf
)
2908 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
2909 int len
= type
->length ();
2910 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2912 /* _Float16 and _Float16 _Complex values are returned via xmm0. */
2913 if (((type
->code () == TYPE_CODE_FLT
) && len
== 2)
2914 || ((type
->code () == TYPE_CODE_COMPLEX
) && len
== 4))
2916 regcache
->raw_read (I387_XMM0_REGNUM (tdep
), valbuf
);
2919 else if (type
->code () == TYPE_CODE_FLT
)
2921 if (tdep
->st0_regnum
< 0)
2923 warning (_("Cannot find floating-point return value."));
2924 memset (valbuf
, 0, len
);
2928 /* Floating-point return values can be found in %st(0). Convert
2929 its contents to the desired type. This is probably not
2930 exactly how it would happen on the target itself, but it is
2931 the best we can do. */
2932 regcache
->raw_read (I386_ST0_REGNUM
, buf
);
2933 target_float_convert (buf
, i387_ext_type (gdbarch
), valbuf
, type
);
2937 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
2938 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
2940 if (len
<= low_size
)
2942 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2943 memcpy (valbuf
, buf
, len
);
2945 else if (len
<= (low_size
+ high_size
))
2947 regcache
->raw_read (LOW_RETURN_REGNUM
, buf
);
2948 memcpy (valbuf
, buf
, low_size
);
2949 regcache
->raw_read (HIGH_RETURN_REGNUM
, buf
);
2950 memcpy (valbuf
+ low_size
, buf
, len
- low_size
);
2953 internal_error (_("Cannot extract return value of %d bytes long."),
2958 /* Write, for architecture GDBARCH, a function return value of TYPE
2959 from VALBUF into REGCACHE. */
2962 i386_store_return_value (struct gdbarch
*gdbarch
, struct type
*type
,
2963 struct regcache
*regcache
, const gdb_byte
*valbuf
)
2965 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
2966 int len
= type
->length ();
2968 if (type
->code () == TYPE_CODE_FLT
)
2971 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
2973 if (tdep
->st0_regnum
< 0)
2975 warning (_("Cannot set floating-point return value."));
2979 /* Returning floating-point values is a bit tricky. Apart from
2980 storing the return value in %st(0), we have to simulate the
2981 state of the FPU at function return point. */
2983 /* Convert the value found in VALBUF to the extended
2984 floating-point format used by the FPU. This is probably
2985 not exactly how it would happen on the target itself, but
2986 it is the best we can do. */
2987 target_float_convert (valbuf
, type
, buf
, i387_ext_type (gdbarch
));
2988 regcache
->raw_write (I386_ST0_REGNUM
, buf
);
2990 /* Set the top of the floating-point register stack to 7. The
2991 actual value doesn't really matter, but 7 is what a normal
2992 function return would end up with if the program started out
2993 with a freshly initialized FPU. */
2994 regcache_raw_read_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), &fstat
);
2996 regcache_raw_write_unsigned (regcache
, I387_FSTAT_REGNUM (tdep
), fstat
);
2998 /* Mark %st(1) through %st(7) as empty. Since we set the top of
2999 the floating-point register stack to 7, the appropriate value
3000 for the tag word is 0x3fff. */
3001 regcache_raw_write_unsigned (regcache
, I387_FTAG_REGNUM (tdep
), 0x3fff);
3005 int low_size
= register_size (gdbarch
, LOW_RETURN_REGNUM
);
3006 int high_size
= register_size (gdbarch
, HIGH_RETURN_REGNUM
);
3008 if (len
<= low_size
)
3009 regcache
->raw_write_part (LOW_RETURN_REGNUM
, 0, len
, valbuf
);
3010 else if (len
<= (low_size
+ high_size
))
3012 regcache
->raw_write (LOW_RETURN_REGNUM
, valbuf
);
3013 regcache
->raw_write_part (HIGH_RETURN_REGNUM
, 0, len
- low_size
,
3017 internal_error (_("Cannot store return value of %d bytes long."), len
);
3022 /* This is the variable that is set with "set struct-convention", and
3023 its legitimate values. */
3024 static const char default_struct_convention
[] = "default";
3025 static const char pcc_struct_convention
[] = "pcc";
3026 static const char reg_struct_convention
[] = "reg";
3027 static const char *const valid_conventions
[] =
3029 default_struct_convention
,
3030 pcc_struct_convention
,
3031 reg_struct_convention
,
3034 static const char *struct_convention
= default_struct_convention
;
3036 /* Return non-zero if TYPE, which is assumed to be a structure,
3037 a union type, or an array type, should be returned in registers
3038 for architecture GDBARCH. */
3041 i386_reg_struct_return_p (struct gdbarch
*gdbarch
, struct type
*type
)
3043 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3044 enum type_code code
= type
->code ();
3045 int len
= type
->length ();
3047 gdb_assert (code
== TYPE_CODE_STRUCT
3048 || code
== TYPE_CODE_UNION
3049 || code
== TYPE_CODE_ARRAY
);
3051 if (struct_convention
== pcc_struct_convention
3052 || (struct_convention
== default_struct_convention
3053 && tdep
->struct_return
== pcc_struct_return
)
3054 || TYPE_HAS_DYNAMIC_LENGTH (type
))
3057 /* Structures consisting of a single `float', `double' or 'long
3058 double' member are returned in %st(0). */
3059 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
3061 type
= check_typedef (type
->field (0).type ());
3062 if (type
->code () == TYPE_CODE_FLT
)
3063 return (len
== 4 || len
== 8 || len
== 12);
3066 return (len
== 1 || len
== 2 || len
== 4 || len
== 8);
3069 /* Determine, for architecture GDBARCH, how a return value of TYPE
3070 should be returned. If it is supposed to be returned in registers,
3071 and READBUF is non-zero, read the appropriate value from REGCACHE,
3072 and copy it into READBUF. If WRITEBUF is non-zero, write the value
3073 from WRITEBUF into REGCACHE. */
3075 static enum return_value_convention
3076 i386_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
3077 struct type
*type
, struct regcache
*regcache
,
3078 struct value
**read_value
, const gdb_byte
*writebuf
)
3080 enum type_code code
= type
->code ();
3082 if (((code
== TYPE_CODE_STRUCT
3083 || code
== TYPE_CODE_UNION
3084 || code
== TYPE_CODE_ARRAY
)
3085 && !i386_reg_struct_return_p (gdbarch
, type
))
3086 /* Complex double and long double uses the struct return convention. */
3087 || (code
== TYPE_CODE_COMPLEX
&& type
->length () == 16)
3088 || (code
== TYPE_CODE_COMPLEX
&& type
->length () == 24)
3089 /* 128-bit decimal float uses the struct return convention. */
3090 || (code
== TYPE_CODE_DECFLOAT
&& type
->length () == 16))
3092 /* The System V ABI says that:
3094 "A function that returns a structure or union also sets %eax
3095 to the value of the original address of the caller's area
3096 before it returns. Thus when the caller receives control
3097 again, the address of the returned object resides in register
3098 %eax and can be used to access the object."
3100 So the ABI guarantees that we can always find the return
3101 value just after the function has returned. */
3103 /* Note that the ABI doesn't mention functions returning arrays,
3104 which is something possible in certain languages such as Ada.
3105 In this case, the value is returned as if it was wrapped in
3106 a record, so the convention applied to records also applies
3109 if (read_value
!= nullptr)
3113 regcache_raw_read_unsigned (regcache
, I386_EAX_REGNUM
, &addr
);
3114 *read_value
= value_at_non_lval (type
, addr
);
3117 return RETURN_VALUE_ABI_RETURNS_ADDRESS
;
3120 /* This special case is for structures consisting of a single
3121 `float', `double' or 'long double' member. These structures are
3122 returned in %st(0). For these structures, we call ourselves
3123 recursively, changing TYPE into the type of the first member of
3124 the structure. Since that should work for all structures that
3125 have only one member, we don't bother to check the member's type
3127 if (code
== TYPE_CODE_STRUCT
&& type
->num_fields () == 1)
3129 struct type
*inner_type
= check_typedef (type
->field (0).type ());
3130 enum return_value_convention result
3131 = i386_return_value (gdbarch
, function
, inner_type
, regcache
,
3132 read_value
, writebuf
);
3133 if (read_value
!= nullptr)
3134 (*read_value
)->deprecated_set_type (type
);
3138 if (read_value
!= nullptr)
3140 *read_value
= value::allocate (type
);
3141 i386_extract_return_value (gdbarch
, type
, regcache
,
3142 (*read_value
)->contents_raw ().data ());
3145 i386_store_return_value (gdbarch
, type
, regcache
, writebuf
);
3147 return RETURN_VALUE_REGISTER_CONVENTION
;
3152 i387_ext_type (struct gdbarch
*gdbarch
)
3154 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3156 if (!tdep
->i387_ext_type
)
3158 tdep
->i387_ext_type
= tdesc_find_type (gdbarch
, "i387_ext");
3159 gdb_assert (tdep
->i387_ext_type
!= NULL
);
3162 return tdep
->i387_ext_type
;
3165 /* Construct type for pseudo BND registers. We can't use
3166 tdesc_find_type since a complement of one value has to be used
3167 to describe the upper bound. */
3169 static struct type
*
3170 i386_bnd_type (struct gdbarch
*gdbarch
)
3172 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3175 if (!tdep
->i386_bnd_type
)
3178 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3180 /* The type we're building is described bellow: */
3185 void *ubound
; /* One complement of raw ubound field. */
3189 t
= arch_composite_type (gdbarch
,
3190 "__gdb_builtin_type_bound128", TYPE_CODE_STRUCT
);
3192 append_composite_type_field (t
, "lbound", bt
->builtin_data_ptr
);
3193 append_composite_type_field (t
, "ubound", bt
->builtin_data_ptr
);
3195 t
->set_name ("builtin_type_bound128");
3196 tdep
->i386_bnd_type
= t
;
3199 return tdep
->i386_bnd_type
;
3202 /* Construct vector type for pseudo ZMM registers. We can't use
3203 tdesc_find_type since ZMM isn't described in target description. */
3205 static struct type
*
3206 i386_zmm_type (struct gdbarch
*gdbarch
)
3208 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3210 if (!tdep
->i386_zmm_type
)
3212 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3214 /* The type we're building is this: */
3216 union __gdb_builtin_type_vec512i
3218 int128_t v4_int128
[4];
3219 int64_t v8_int64
[8];
3220 int32_t v16_int32
[16];
3221 int16_t v32_int16
[32];
3222 int8_t v64_int8
[64];
3223 double v8_double
[8];
3224 float v16_float
[16];
3225 float16_t v32_half
[32];
3226 bfloat16_t v32_bfloat16
[32];
3232 t
= arch_composite_type (gdbarch
,
3233 "__gdb_builtin_type_vec512i", TYPE_CODE_UNION
);
3234 append_composite_type_field (t
, "v32_bfloat16",
3235 init_vector_type (bt
->builtin_bfloat16
, 32));
3236 append_composite_type_field (t
, "v32_half",
3237 init_vector_type (bt
->builtin_half
, 32));
3238 append_composite_type_field (t
, "v16_float",
3239 init_vector_type (bt
->builtin_float
, 16));
3240 append_composite_type_field (t
, "v8_double",
3241 init_vector_type (bt
->builtin_double
, 8));
3242 append_composite_type_field (t
, "v64_int8",
3243 init_vector_type (bt
->builtin_int8
, 64));
3244 append_composite_type_field (t
, "v32_int16",
3245 init_vector_type (bt
->builtin_int16
, 32));
3246 append_composite_type_field (t
, "v16_int32",
3247 init_vector_type (bt
->builtin_int32
, 16));
3248 append_composite_type_field (t
, "v8_int64",
3249 init_vector_type (bt
->builtin_int64
, 8));
3250 append_composite_type_field (t
, "v4_int128",
3251 init_vector_type (bt
->builtin_int128
, 4));
3253 t
->set_is_vector (true);
3254 t
->set_name ("builtin_type_vec512i");
3255 tdep
->i386_zmm_type
= t
;
3258 return tdep
->i386_zmm_type
;
3261 /* Construct vector type for pseudo YMM registers. We can't use
3262 tdesc_find_type since YMM isn't described in target description. */
3264 static struct type
*
3265 i386_ymm_type (struct gdbarch
*gdbarch
)
3267 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3269 if (!tdep
->i386_ymm_type
)
3271 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3273 /* The type we're building is this: */
3275 union __gdb_builtin_type_vec256i
3277 int128_t v2_int128
[2];
3278 int64_t v4_int64
[4];
3279 int32_t v8_int32
[8];
3280 int16_t v16_int16
[16];
3281 int8_t v32_int8
[32];
3282 double v4_double
[4];
3284 float16_t v16_half
[16];
3285 bfloat16_t v16_bfloat16
[16];
3291 t
= arch_composite_type (gdbarch
,
3292 "__gdb_builtin_type_vec256i", TYPE_CODE_UNION
);
3293 append_composite_type_field (t
, "v16_bfloat16",
3294 init_vector_type (bt
->builtin_bfloat16
, 16));
3295 append_composite_type_field (t
, "v16_half",
3296 init_vector_type (bt
->builtin_half
, 16));
3297 append_composite_type_field (t
, "v8_float",
3298 init_vector_type (bt
->builtin_float
, 8));
3299 append_composite_type_field (t
, "v4_double",
3300 init_vector_type (bt
->builtin_double
, 4));
3301 append_composite_type_field (t
, "v32_int8",
3302 init_vector_type (bt
->builtin_int8
, 32));
3303 append_composite_type_field (t
, "v16_int16",
3304 init_vector_type (bt
->builtin_int16
, 16));
3305 append_composite_type_field (t
, "v8_int32",
3306 init_vector_type (bt
->builtin_int32
, 8));
3307 append_composite_type_field (t
, "v4_int64",
3308 init_vector_type (bt
->builtin_int64
, 4));
3309 append_composite_type_field (t
, "v2_int128",
3310 init_vector_type (bt
->builtin_int128
, 2));
3312 t
->set_is_vector (true);
3313 t
->set_name ("builtin_type_vec256i");
3314 tdep
->i386_ymm_type
= t
;
3317 return tdep
->i386_ymm_type
;
3320 /* Construct vector type for MMX registers. */
3321 static struct type
*
3322 i386_mmx_type (struct gdbarch
*gdbarch
)
3324 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3326 if (!tdep
->i386_mmx_type
)
3328 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3330 /* The type we're building is this: */
3332 union __gdb_builtin_type_vec64i
3335 int32_t v2_int32
[2];
3336 int16_t v4_int16
[4];
3343 t
= arch_composite_type (gdbarch
,
3344 "__gdb_builtin_type_vec64i", TYPE_CODE_UNION
);
3346 append_composite_type_field (t
, "uint64", bt
->builtin_int64
);
3347 append_composite_type_field (t
, "v2_int32",
3348 init_vector_type (bt
->builtin_int32
, 2));
3349 append_composite_type_field (t
, "v4_int16",
3350 init_vector_type (bt
->builtin_int16
, 4));
3351 append_composite_type_field (t
, "v8_int8",
3352 init_vector_type (bt
->builtin_int8
, 8));
3354 t
->set_is_vector (true);
3355 t
->set_name ("builtin_type_vec64i");
3356 tdep
->i386_mmx_type
= t
;
3359 return tdep
->i386_mmx_type
;
3362 /* Return the GDB type object for the "standard" data type of data in
3366 i386_pseudo_register_type (struct gdbarch
*gdbarch
, int regnum
)
3368 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3369 return i386_bnd_type (gdbarch
);
3370 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3371 return i386_mmx_type (gdbarch
);
3372 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3373 return i386_ymm_type (gdbarch
);
3374 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3375 return i386_ymm_type (gdbarch
);
3376 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3377 return i386_zmm_type (gdbarch
);
3380 const struct builtin_type
*bt
= builtin_type (gdbarch
);
3381 if (i386_byte_regnum_p (gdbarch
, regnum
))
3382 return bt
->builtin_int8
;
3383 else if (i386_word_regnum_p (gdbarch
, regnum
))
3384 return bt
->builtin_int16
;
3385 else if (i386_dword_regnum_p (gdbarch
, regnum
))
3386 return bt
->builtin_int32
;
3387 else if (i386_k_regnum_p (gdbarch
, regnum
))
3388 return bt
->builtin_int64
;
3391 internal_error (_("invalid regnum"));
3394 /* Map a cooked register onto a raw register or memory. For the i386,
3395 the MMX registers need to be mapped onto floating point registers. */
3398 i386_mmx_regnum_to_fp_regnum (readable_regcache
*regcache
, int regnum
)
3400 gdbarch
*arch
= regcache
->arch ();
3401 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (arch
);
3406 mmxreg
= regnum
- tdep
->mm0_regnum
;
3407 regcache
->raw_read (I387_FSTAT_REGNUM (tdep
), &fstat
);
3408 tos
= (fstat
>> 11) & 0x7;
3409 fpreg
= (mmxreg
+ tos
) % 8;
3411 return (I387_ST0_REGNUM (tdep
) + fpreg
);
3414 /* A helper function for us by i386_pseudo_register_read_value and
3415 amd64_pseudo_register_read_value. It does all the work but reads
3416 the data into an already-allocated value. */
3419 i386_pseudo_register_read_into_value (struct gdbarch
*gdbarch
,
3420 readable_regcache
*regcache
,
3422 struct value
*result_value
)
3424 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3425 enum register_status status
;
3426 gdb_byte
*buf
= result_value
->contents_raw ().data ();
3428 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3430 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3432 /* Extract (always little endian). */
3433 status
= regcache
->raw_read (fpnum
, raw_buf
);
3434 if (status
!= REG_VALID
)
3435 result_value
->mark_bytes_unavailable (0,
3436 result_value
->type ()->length ());
3438 memcpy (buf
, raw_buf
, register_size (gdbarch
, regnum
));
3442 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3443 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3445 regnum
-= tdep
->bnd0_regnum
;
3447 /* Extract (always little endian). Read lower 128bits. */
3448 status
= regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3450 if (status
!= REG_VALID
)
3451 result_value
->mark_bytes_unavailable (0, 16);
3454 bfd_endian byte_order
3455 = gdbarch_byte_order (current_inferior ()->arch ());
3456 LONGEST upper
, lower
;
3457 int size
= builtin_type (gdbarch
)->builtin_data_ptr
->length ();
3459 lower
= extract_unsigned_integer (raw_buf
, 8, byte_order
);
3460 upper
= extract_unsigned_integer (raw_buf
+ 8, 8, byte_order
);
3463 memcpy (buf
, &lower
, size
);
3464 memcpy (buf
+ size
, &upper
, size
);
3467 else if (i386_k_regnum_p (gdbarch
, regnum
))
3469 regnum
-= tdep
->k0_regnum
;
3471 /* Extract (always little endian). */
3472 status
= regcache
->raw_read (tdep
->k0_regnum
+ regnum
, raw_buf
);
3473 if (status
!= REG_VALID
)
3474 result_value
->mark_bytes_unavailable (0, 8);
3476 memcpy (buf
, raw_buf
, 8);
3478 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3480 regnum
-= tdep
->zmm0_regnum
;
3482 if (regnum
< num_lower_zmm_regs
)
3484 /* Extract (always little endian). Read lower 128bits. */
3485 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3487 if (status
!= REG_VALID
)
3488 result_value
->mark_bytes_unavailable (0, 16);
3490 memcpy (buf
, raw_buf
, 16);
3492 /* Extract (always little endian). Read upper 128bits. */
3493 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3495 if (status
!= REG_VALID
)
3496 result_value
->mark_bytes_unavailable (16, 16);
3498 memcpy (buf
+ 16, raw_buf
, 16);
3502 /* Extract (always little endian). Read lower 128bits. */
3503 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
3504 - num_lower_zmm_regs
,
3506 if (status
!= REG_VALID
)
3507 result_value
->mark_bytes_unavailable (0, 16);
3509 memcpy (buf
, raw_buf
, 16);
3511 /* Extract (always little endian). Read upper 128bits. */
3512 status
= regcache
->raw_read (I387_YMM16H_REGNUM (tdep
) + regnum
3513 - num_lower_zmm_regs
,
3515 if (status
!= REG_VALID
)
3516 result_value
->mark_bytes_unavailable (16, 16);
3518 memcpy (buf
+ 16, raw_buf
, 16);
3521 /* Read upper 256bits. */
3522 status
= regcache
->raw_read (tdep
->zmm0h_regnum
+ regnum
,
3524 if (status
!= REG_VALID
)
3525 result_value
->mark_bytes_unavailable (32, 32);
3527 memcpy (buf
+ 32, raw_buf
, 32);
3529 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3531 regnum
-= tdep
->ymm0_regnum
;
3533 /* Extract (always little endian). Read lower 128bits. */
3534 status
= regcache
->raw_read (I387_XMM0_REGNUM (tdep
) + regnum
,
3536 if (status
!= REG_VALID
)
3537 result_value
->mark_bytes_unavailable (0, 16);
3539 memcpy (buf
, raw_buf
, 16);
3540 /* Read upper 128bits. */
3541 status
= regcache
->raw_read (tdep
->ymm0h_regnum
+ regnum
,
3543 if (status
!= REG_VALID
)
3544 result_value
->mark_bytes_unavailable (16, 32);
3546 memcpy (buf
+ 16, raw_buf
, 16);
3548 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3550 regnum
-= tdep
->ymm16_regnum
;
3551 /* Extract (always little endian). Read lower 128bits. */
3552 status
= regcache
->raw_read (I387_XMM16_REGNUM (tdep
) + regnum
,
3554 if (status
!= REG_VALID
)
3555 result_value
->mark_bytes_unavailable (0, 16);
3557 memcpy (buf
, raw_buf
, 16);
3558 /* Read upper 128bits. */
3559 status
= regcache
->raw_read (tdep
->ymm16h_regnum
+ regnum
,
3561 if (status
!= REG_VALID
)
3562 result_value
->mark_bytes_unavailable (16, 16);
3564 memcpy (buf
+ 16, raw_buf
, 16);
3566 else if (i386_word_regnum_p (gdbarch
, regnum
))
3568 int gpnum
= regnum
- tdep
->ax_regnum
;
3570 /* Extract (always little endian). */
3571 status
= regcache
->raw_read (gpnum
, raw_buf
);
3572 if (status
!= REG_VALID
)
3573 result_value
->mark_bytes_unavailable (0,
3574 result_value
->type ()->length ());
3576 memcpy (buf
, raw_buf
, 2);
3578 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3580 int gpnum
= regnum
- tdep
->al_regnum
;
3582 /* Extract (always little endian). We read both lower and
3584 status
= regcache
->raw_read (gpnum
% 4, raw_buf
);
3585 if (status
!= REG_VALID
)
3586 result_value
->mark_bytes_unavailable (0,
3587 result_value
->type ()->length ());
3588 else if (gpnum
>= 4)
3589 memcpy (buf
, raw_buf
+ 1, 1);
3591 memcpy (buf
, raw_buf
, 1);
3594 internal_error (_("invalid regnum"));
3598 static struct value
*
3599 i386_pseudo_register_read_value (struct gdbarch
*gdbarch
,
3600 readable_regcache
*regcache
,
3603 struct value
*result
;
3605 result
= value::allocate (register_type (gdbarch
, regnum
));
3606 result
->set_lval (lval_register
);
3607 VALUE_REGNUM (result
) = regnum
;
3609 i386_pseudo_register_read_into_value (gdbarch
, regcache
, regnum
, result
);
3615 i386_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
3616 int regnum
, const gdb_byte
*buf
)
3618 gdb_byte raw_buf
[I386_MAX_REGISTER_SIZE
];
3620 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3622 int fpnum
= i386_mmx_regnum_to_fp_regnum (regcache
, regnum
);
3625 regcache
->raw_read (fpnum
, raw_buf
);
3626 /* ... Modify ... (always little endian). */
3627 memcpy (raw_buf
, buf
, register_size (gdbarch
, regnum
));
3629 regcache
->raw_write (fpnum
, raw_buf
);
3633 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3635 if (i386_bnd_regnum_p (gdbarch
, regnum
))
3637 ULONGEST upper
, lower
;
3638 int size
= builtin_type (gdbarch
)->builtin_data_ptr
->length ();
3639 bfd_endian byte_order
3640 = gdbarch_byte_order (current_inferior ()->arch ());
3642 /* New values from input value. */
3643 regnum
-= tdep
->bnd0_regnum
;
3644 lower
= extract_unsigned_integer (buf
, size
, byte_order
);
3645 upper
= extract_unsigned_integer (buf
+ size
, size
, byte_order
);
3647 /* Fetching register buffer. */
3648 regcache
->raw_read (I387_BND0R_REGNUM (tdep
) + regnum
,
3653 /* Set register bits. */
3654 memcpy (raw_buf
, &lower
, 8);
3655 memcpy (raw_buf
+ 8, &upper
, 8);
3657 regcache
->raw_write (I387_BND0R_REGNUM (tdep
) + regnum
, raw_buf
);
3659 else if (i386_k_regnum_p (gdbarch
, regnum
))
3661 regnum
-= tdep
->k0_regnum
;
3663 regcache
->raw_write (tdep
->k0_regnum
+ regnum
, buf
);
3665 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3667 regnum
-= tdep
->zmm0_regnum
;
3669 if (regnum
< num_lower_zmm_regs
)
3671 /* Write lower 128bits. */
3672 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3673 /* Write upper 128bits. */
3674 regcache
->raw_write (I387_YMM0_REGNUM (tdep
) + regnum
, buf
+ 16);
3678 /* Write lower 128bits. */
3679 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
3680 - num_lower_zmm_regs
, buf
);
3681 /* Write upper 128bits. */
3682 regcache
->raw_write (I387_YMM16H_REGNUM (tdep
) + regnum
3683 - num_lower_zmm_regs
, buf
+ 16);
3685 /* Write upper 256bits. */
3686 regcache
->raw_write (tdep
->zmm0h_regnum
+ regnum
, buf
+ 32);
3688 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3690 regnum
-= tdep
->ymm0_regnum
;
3692 /* ... Write lower 128bits. */
3693 regcache
->raw_write (I387_XMM0_REGNUM (tdep
) + regnum
, buf
);
3694 /* ... Write upper 128bits. */
3695 regcache
->raw_write (tdep
->ymm0h_regnum
+ regnum
, buf
+ 16);
3697 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3699 regnum
-= tdep
->ymm16_regnum
;
3701 /* ... Write lower 128bits. */
3702 regcache
->raw_write (I387_XMM16_REGNUM (tdep
) + regnum
, buf
);
3703 /* ... Write upper 128bits. */
3704 regcache
->raw_write (tdep
->ymm16h_regnum
+ regnum
, buf
+ 16);
3706 else if (i386_word_regnum_p (gdbarch
, regnum
))
3708 int gpnum
= regnum
- tdep
->ax_regnum
;
3711 regcache
->raw_read (gpnum
, raw_buf
);
3712 /* ... Modify ... (always little endian). */
3713 memcpy (raw_buf
, buf
, 2);
3715 regcache
->raw_write (gpnum
, raw_buf
);
3717 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3719 int gpnum
= regnum
- tdep
->al_regnum
;
3721 /* Read ... We read both lower and upper registers. */
3722 regcache
->raw_read (gpnum
% 4, raw_buf
);
3723 /* ... Modify ... (always little endian). */
3725 memcpy (raw_buf
+ 1, buf
, 1);
3727 memcpy (raw_buf
, buf
, 1);
3729 regcache
->raw_write (gpnum
% 4, raw_buf
);
3732 internal_error (_("invalid regnum"));
3736 /* Implement the 'ax_pseudo_register_collect' gdbarch method. */
3739 i386_ax_pseudo_register_collect (struct gdbarch
*gdbarch
,
3740 struct agent_expr
*ax
, int regnum
)
3742 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3744 if (i386_mmx_regnum_p (gdbarch
, regnum
))
3746 /* MMX to FPU register mapping depends on current TOS. Let's just
3747 not care and collect everything... */
3750 ax_reg_mask (ax
, I387_FSTAT_REGNUM (tdep
));
3751 for (i
= 0; i
< 8; i
++)
3752 ax_reg_mask (ax
, I387_ST0_REGNUM (tdep
) + i
);
3755 else if (i386_bnd_regnum_p (gdbarch
, regnum
))
3757 regnum
-= tdep
->bnd0_regnum
;
3758 ax_reg_mask (ax
, I387_BND0R_REGNUM (tdep
) + regnum
);
3761 else if (i386_k_regnum_p (gdbarch
, regnum
))
3763 regnum
-= tdep
->k0_regnum
;
3764 ax_reg_mask (ax
, tdep
->k0_regnum
+ regnum
);
3767 else if (i386_zmm_regnum_p (gdbarch
, regnum
))
3769 regnum
-= tdep
->zmm0_regnum
;
3770 if (regnum
< num_lower_zmm_regs
)
3772 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3773 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3777 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
3778 - num_lower_zmm_regs
);
3779 ax_reg_mask (ax
, I387_YMM16H_REGNUM (tdep
) + regnum
3780 - num_lower_zmm_regs
);
3782 ax_reg_mask (ax
, tdep
->zmm0h_regnum
+ regnum
);
3785 else if (i386_ymm_regnum_p (gdbarch
, regnum
))
3787 regnum
-= tdep
->ymm0_regnum
;
3788 ax_reg_mask (ax
, I387_XMM0_REGNUM (tdep
) + regnum
);
3789 ax_reg_mask (ax
, tdep
->ymm0h_regnum
+ regnum
);
3792 else if (i386_ymm_avx512_regnum_p (gdbarch
, regnum
))
3794 regnum
-= tdep
->ymm16_regnum
;
3795 ax_reg_mask (ax
, I387_XMM16_REGNUM (tdep
) + regnum
);
3796 ax_reg_mask (ax
, tdep
->ymm16h_regnum
+ regnum
);
3799 else if (i386_word_regnum_p (gdbarch
, regnum
))
3801 int gpnum
= regnum
- tdep
->ax_regnum
;
3803 ax_reg_mask (ax
, gpnum
);
3806 else if (i386_byte_regnum_p (gdbarch
, regnum
))
3808 int gpnum
= regnum
- tdep
->al_regnum
;
3810 ax_reg_mask (ax
, gpnum
% 4);
3814 internal_error (_("invalid regnum"));
3819 /* Return the register number of the register allocated by GCC after
3820 REGNUM, or -1 if there is no such register. */
3823 i386_next_regnum (int regnum
)
3825 /* GCC allocates the registers in the order:
3827 %eax, %edx, %ecx, %ebx, %esi, %edi, %ebp, %esp, ...
3829 Since storing a variable in %esp doesn't make any sense we return
3830 -1 for %ebp and for %esp itself. */
3831 static int next_regnum
[] =
3833 I386_EDX_REGNUM
, /* Slot for %eax. */
3834 I386_EBX_REGNUM
, /* Slot for %ecx. */
3835 I386_ECX_REGNUM
, /* Slot for %edx. */
3836 I386_ESI_REGNUM
, /* Slot for %ebx. */
3837 -1, -1, /* Slots for %esp and %ebp. */
3838 I386_EDI_REGNUM
, /* Slot for %esi. */
3839 I386_EBP_REGNUM
/* Slot for %edi. */
3842 if (regnum
>= 0 && regnum
< sizeof (next_regnum
) / sizeof (next_regnum
[0]))
3843 return next_regnum
[regnum
];
3848 /* Return nonzero if a value of type TYPE stored in register REGNUM
3849 needs any special handling. */
3852 i386_convert_register_p (struct gdbarch
*gdbarch
,
3853 int regnum
, struct type
*type
)
3855 int len
= type
->length ();
3857 /* Values may be spread across multiple registers. Most debugging
3858 formats aren't expressive enough to specify the locations, so
3859 some heuristics is involved. Right now we only handle types that
3860 have a length that is a multiple of the word size, since GCC
3861 doesn't seem to put any other types into registers. */
3862 if (len
> 4 && len
% 4 == 0)
3864 int last_regnum
= regnum
;
3868 last_regnum
= i386_next_regnum (last_regnum
);
3872 if (last_regnum
!= -1)
3876 return i387_convert_register_p (gdbarch
, regnum
, type
);
3879 /* Read a value of type TYPE from register REGNUM in frame FRAME, and
3880 return its contents in TO. */
3883 i386_register_to_value (frame_info_ptr frame
, int regnum
,
3884 struct type
*type
, gdb_byte
*to
,
3885 int *optimizedp
, int *unavailablep
)
3887 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
3888 int len
= type
->length ();
3890 if (i386_fp_regnum_p (gdbarch
, regnum
))
3891 return i387_register_to_value (frame
, regnum
, type
, to
,
3892 optimizedp
, unavailablep
);
3894 /* Read a value spread across multiple registers. */
3896 gdb_assert (len
> 4 && len
% 4 == 0);
3900 gdb_assert (regnum
!= -1);
3901 gdb_assert (register_size (gdbarch
, regnum
) == 4);
3903 if (!get_frame_register_bytes (frame
, regnum
, 0,
3904 gdb::make_array_view (to
,
3905 register_size (gdbarch
,
3907 optimizedp
, unavailablep
))
3910 regnum
= i386_next_regnum (regnum
);
3915 *optimizedp
= *unavailablep
= 0;
3919 /* Write the contents FROM of a value of type TYPE into register
3920 REGNUM in frame FRAME. */
3923 i386_value_to_register (frame_info_ptr frame
, int regnum
,
3924 struct type
*type
, const gdb_byte
*from
)
3926 int len
= type
->length ();
3928 if (i386_fp_regnum_p (get_frame_arch (frame
), regnum
))
3930 i387_value_to_register (frame
, regnum
, type
, from
);
3934 /* Write a value spread across multiple registers. */
3936 gdb_assert (len
> 4 && len
% 4 == 0);
3940 gdb_assert (regnum
!= -1);
3941 gdb_assert (register_size (get_frame_arch (frame
), regnum
) == 4);
3943 put_frame_register (frame
, regnum
, from
);
3944 regnum
= i386_next_regnum (regnum
);
3950 /* Supply register REGNUM from the buffer specified by GREGS and LEN
3951 in the general-purpose register set REGSET to register cache
3952 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
3955 i386_supply_gregset (const struct regset
*regset
, struct regcache
*regcache
,
3956 int regnum
, const void *gregs
, size_t len
)
3958 struct gdbarch
*gdbarch
= regcache
->arch ();
3959 const i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3960 const gdb_byte
*regs
= (const gdb_byte
*) gregs
;
3963 gdb_assert (len
>= tdep
->sizeof_gregset
);
3965 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3967 if ((regnum
== i
|| regnum
== -1)
3968 && tdep
->gregset_reg_offset
[i
] != -1)
3969 regcache
->raw_supply (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3973 /* Collect register REGNUM from the register cache REGCACHE and store
3974 it in the buffer specified by GREGS and LEN as described by the
3975 general-purpose register set REGSET. If REGNUM is -1, do this for
3976 all registers in REGSET. */
3979 i386_collect_gregset (const struct regset
*regset
,
3980 const struct regcache
*regcache
,
3981 int regnum
, void *gregs
, size_t len
)
3983 struct gdbarch
*gdbarch
= regcache
->arch ();
3984 const i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
3985 gdb_byte
*regs
= (gdb_byte
*) gregs
;
3988 gdb_assert (len
>= tdep
->sizeof_gregset
);
3990 for (i
= 0; i
< tdep
->gregset_num_regs
; i
++)
3992 if ((regnum
== i
|| regnum
== -1)
3993 && tdep
->gregset_reg_offset
[i
] != -1)
3994 regcache
->raw_collect (i
, regs
+ tdep
->gregset_reg_offset
[i
]);
3998 /* Supply register REGNUM from the buffer specified by FPREGS and LEN
3999 in the floating-point register set REGSET to register cache
4000 REGCACHE. If REGNUM is -1, do this for all registers in REGSET. */
4003 i386_supply_fpregset (const struct regset
*regset
, struct regcache
*regcache
,
4004 int regnum
, const void *fpregs
, size_t len
)
4006 struct gdbarch
*gdbarch
= regcache
->arch ();
4007 const i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
4009 if (len
== I387_SIZEOF_FXSAVE
)
4011 i387_supply_fxsave (regcache
, regnum
, fpregs
);
4015 gdb_assert (len
>= tdep
->sizeof_fpregset
);
4016 i387_supply_fsave (regcache
, regnum
, fpregs
);
4019 /* Collect register REGNUM from the register cache REGCACHE and store
4020 it in the buffer specified by FPREGS and LEN as described by the
4021 floating-point register set REGSET. If REGNUM is -1, do this for
4022 all registers in REGSET. */
4025 i386_collect_fpregset (const struct regset
*regset
,
4026 const struct regcache
*regcache
,
4027 int regnum
, void *fpregs
, size_t len
)
4029 struct gdbarch
*gdbarch
= regcache
->arch ();
4030 const i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
4032 if (len
== I387_SIZEOF_FXSAVE
)
4034 i387_collect_fxsave (regcache
, regnum
, fpregs
);
4038 gdb_assert (len
>= tdep
->sizeof_fpregset
);
4039 i387_collect_fsave (regcache
, regnum
, fpregs
);
4042 /* Register set definitions. */
4044 const struct regset i386_gregset
=
4046 NULL
, i386_supply_gregset
, i386_collect_gregset
4049 const struct regset i386_fpregset
=
4051 NULL
, i386_supply_fpregset
, i386_collect_fpregset
4054 /* Default iterator over core file register note sections. */
4057 i386_iterate_over_regset_sections (struct gdbarch
*gdbarch
,
4058 iterate_over_regset_sections_cb
*cb
,
4060 const struct regcache
*regcache
)
4062 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
4064 cb (".reg", tdep
->sizeof_gregset
, tdep
->sizeof_gregset
, &i386_gregset
, NULL
,
4066 if (tdep
->sizeof_fpregset
)
4067 cb (".reg2", tdep
->sizeof_fpregset
, tdep
->sizeof_fpregset
, tdep
->fpregset
,
4072 /* Stuff for WIN32 PE style DLL's but is pretty generic really. */
4075 i386_pe_skip_trampoline_code (frame_info_ptr frame
,
4076 CORE_ADDR pc
, char *name
)
4078 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4079 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4082 if (pc
&& read_memory_unsigned_integer (pc
, 2, byte_order
) == 0x25ff)
4084 unsigned long indirect
=
4085 read_memory_unsigned_integer (pc
+ 2, 4, byte_order
);
4086 struct minimal_symbol
*indsym
=
4087 indirect
? lookup_minimal_symbol_by_pc (indirect
).minsym
: 0;
4088 const char *symname
= indsym
? indsym
->linkage_name () : 0;
4092 if (startswith (symname
, "__imp_")
4093 || startswith (symname
, "_imp_"))
4095 read_memory_unsigned_integer (indirect
, 4, byte_order
);
4098 return 0; /* Not a trampoline. */
4102 /* Return whether the THIS_FRAME corresponds to a sigtramp
4106 i386_sigtramp_p (frame_info_ptr this_frame
)
4108 CORE_ADDR pc
= get_frame_pc (this_frame
);
4111 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4112 return (name
&& strcmp ("_sigtramp", name
) == 0);
4116 /* We have two flavours of disassembly. The machinery on this page
4117 deals with switching between those. */
4120 i386_print_insn (bfd_vma pc
, struct disassemble_info
*info
)
4122 gdb_assert (disassembly_flavor
== att_flavor
4123 || disassembly_flavor
== intel_flavor
);
4125 info
->disassembler_options
= disassembly_flavor
;
4127 return default_print_insn (pc
, info
);
4131 /* There are a few i386 architecture variants that differ only
4132 slightly from the generic i386 target. For now, we don't give them
4133 their own source file, but include them here. As a consequence,
4134 they'll always be included. */
4136 /* System V Release 4 (SVR4). */
4138 /* Return whether THIS_FRAME corresponds to a SVR4 sigtramp
4142 i386_svr4_sigtramp_p (frame_info_ptr this_frame
)
4144 CORE_ADDR pc
= get_frame_pc (this_frame
);
4147 /* The origin of these symbols is currently unknown. */
4148 find_pc_partial_function (pc
, &name
, NULL
, NULL
);
4149 return (name
&& (strcmp ("_sigreturn", name
) == 0
4150 || strcmp ("sigvechandler", name
) == 0));
4153 /* Assuming THIS_FRAME is for a SVR4 sigtramp routine, return the
4154 address of the associated sigcontext (ucontext) structure. */
4157 i386_svr4_sigcontext_addr (frame_info_ptr this_frame
)
4159 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
4160 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4164 get_frame_register (this_frame
, I386_ESP_REGNUM
, buf
);
4165 sp
= extract_unsigned_integer (buf
, 4, byte_order
);
4167 return read_memory_unsigned_integer (sp
+ 8, 4, byte_order
);
4172 /* Implementation of `gdbarch_stap_is_single_operand', as defined in
4176 i386_stap_is_single_operand (struct gdbarch
*gdbarch
, const char *s
)
4178 return (*s
== '$' /* Literal number. */
4179 || (isdigit (*s
) && s
[1] == '(' && s
[2] == '%') /* Displacement. */
4180 || (*s
== '(' && s
[1] == '%') /* Register indirection. */
4181 || (*s
== '%' && isalpha (s
[1]))); /* Register access. */
4184 /* Helper function for i386_stap_parse_special_token.
4186 This function parses operands of the form `-8+3+1(%rbp)', which
4187 must be interpreted as `*(-8 + 3 - 1 + (void *) $eax)'.
4189 Return true if the operand was parsed successfully, false
4192 static expr::operation_up
4193 i386_stap_parse_special_token_triplet (struct gdbarch
*gdbarch
,
4194 struct stap_parse_info
*p
)
4196 const char *s
= p
->arg
;
4198 if (isdigit (*s
) || *s
== '-' || *s
== '+')
4202 long displacements
[3];
4207 got_minus
[0] = false;
4213 got_minus
[0] = true;
4216 if (!isdigit ((unsigned char) *s
))
4219 displacements
[0] = strtol (s
, &endp
, 10);
4222 if (*s
!= '+' && *s
!= '-')
4224 /* We are not dealing with a triplet. */
4228 got_minus
[1] = false;
4234 got_minus
[1] = true;
4237 if (!isdigit ((unsigned char) *s
))
4240 displacements
[1] = strtol (s
, &endp
, 10);
4243 if (*s
!= '+' && *s
!= '-')
4245 /* We are not dealing with a triplet. */
4249 got_minus
[2] = false;
4255 got_minus
[2] = true;
4258 if (!isdigit ((unsigned char) *s
))
4261 displacements
[2] = strtol (s
, &endp
, 10);
4264 if (*s
!= '(' || s
[1] != '%')
4270 while (isalnum (*s
))
4276 len
= s
- start
- 1;
4277 std::string
regname (start
, len
);
4279 if (user_reg_map_name_to_regnum (gdbarch
, regname
.c_str (), len
) == -1)
4280 error (_("Invalid register name `%s' on expression `%s'."),
4281 regname
.c_str (), p
->saved_arg
);
4284 for (i
= 0; i
< 3; i
++)
4286 LONGEST this_val
= displacements
[i
];
4288 this_val
= -this_val
;
4294 using namespace expr
;
4296 struct type
*long_type
= builtin_type (gdbarch
)->builtin_long
;
4298 = make_operation
<long_const_operation
> (long_type
, value
);
4301 = make_operation
<register_operation
> (std::move (regname
));
4302 struct type
*void_ptr
= builtin_type (gdbarch
)->builtin_data_ptr
;
4303 reg
= make_operation
<unop_cast_operation
> (std::move (reg
), void_ptr
);
4306 = make_operation
<add_operation
> (std::move (reg
), std::move (offset
));
4307 struct type
*arg_ptr_type
= lookup_pointer_type (p
->arg_type
);
4308 sum
= make_operation
<unop_cast_operation
> (std::move (sum
),
4310 return make_operation
<unop_ind_operation
> (std::move (sum
));
4316 /* Helper function for i386_stap_parse_special_token.
4318 This function parses operands of the form `register base +
4319 (register index * size) + offset', as represented in
4320 `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4322 Return true if the operand was parsed successfully, false
4325 static expr::operation_up
4326 i386_stap_parse_special_token_three_arg_disp (struct gdbarch
*gdbarch
,
4327 struct stap_parse_info
*p
)
4329 const char *s
= p
->arg
;
4331 if (isdigit (*s
) || *s
== '(' || *s
== '-' || *s
== '+')
4333 bool offset_minus
= false;
4335 bool size_minus
= false;
4346 offset_minus
= true;
4349 if (offset_minus
&& !isdigit (*s
))
4356 offset
= strtol (s
, &endp
, 10);
4360 if (*s
!= '(' || s
[1] != '%')
4366 while (isalnum (*s
))
4369 if (*s
!= ',' || s
[1] != '%')
4372 len_base
= s
- start
;
4373 std::string
base (start
, len_base
);
4375 if (user_reg_map_name_to_regnum (gdbarch
, base
.c_str (), len_base
) == -1)
4376 error (_("Invalid register name `%s' on expression `%s'."),
4377 base
.c_str (), p
->saved_arg
);
4382 while (isalnum (*s
))
4385 len_index
= s
- start
;
4386 std::string
index (start
, len_index
);
4388 if (user_reg_map_name_to_regnum (gdbarch
, index
.c_str (),
4390 error (_("Invalid register name `%s' on expression `%s'."),
4391 index
.c_str (), p
->saved_arg
);
4393 if (*s
!= ',' && *s
!= ')')
4409 size
= strtol (s
, &endp
, 10);
4419 using namespace expr
;
4421 struct type
*long_type
= builtin_type (gdbarch
)->builtin_long
;
4422 operation_up reg
= make_operation
<register_operation
> (std::move (base
));
4429 = make_operation
<long_const_operation
> (long_type
, offset
);
4430 reg
= make_operation
<add_operation
> (std::move (reg
),
4434 operation_up ind_reg
4435 = make_operation
<register_operation
> (std::move (index
));
4442 = make_operation
<long_const_operation
> (long_type
, size
);
4443 ind_reg
= make_operation
<mul_operation
> (std::move (ind_reg
),
4448 = make_operation
<add_operation
> (std::move (reg
),
4449 std::move (ind_reg
));
4451 struct type
*arg_ptr_type
= lookup_pointer_type (p
->arg_type
);
4452 sum
= make_operation
<unop_cast_operation
> (std::move (sum
),
4454 return make_operation
<unop_ind_operation
> (std::move (sum
));
4460 /* Implementation of `gdbarch_stap_parse_special_token', as defined in
4464 i386_stap_parse_special_token (struct gdbarch
*gdbarch
,
4465 struct stap_parse_info
*p
)
4467 /* The special tokens to be parsed here are:
4469 - `register base + (register index * size) + offset', as represented
4470 in `(%rcx,%rax,8)', or `[OFFSET](BASE_REG,INDEX_REG[,SIZE])'.
4472 - Operands of the form `-8+3+1(%rbp)', which must be interpreted as
4473 `*(-8 + 3 - 1 + (void *) $eax)'. */
4475 expr::operation_up result
4476 = i386_stap_parse_special_token_triplet (gdbarch
, p
);
4478 if (result
== nullptr)
4479 result
= i386_stap_parse_special_token_three_arg_disp (gdbarch
, p
);
4484 /* Implementation of 'gdbarch_stap_adjust_register', as defined in
4488 i386_stap_adjust_register (struct gdbarch
*gdbarch
, struct stap_parse_info
*p
,
4489 const std::string
®name
, int regnum
)
4491 static const std::unordered_set
<std::string
> reg_assoc
4492 = { "ax", "bx", "cx", "dx",
4493 "si", "di", "bp", "sp" };
4495 /* If we are dealing with a register whose size is less than the size
4496 specified by the "[-]N@" prefix, and it is one of the registers that
4497 we know has an extended variant available, then use the extended
4498 version of the register instead. */
4499 if (register_size (gdbarch
, regnum
) < p
->arg_type
->length ()
4500 && reg_assoc
.find (regname
) != reg_assoc
.end ())
4501 return "e" + regname
;
4503 /* Otherwise, just use the requested register. */
4509 /* gdbarch gnu_triplet_regexp method. Both arches are acceptable as GDB always
4510 also supplies -m64 or -m32 by gdbarch_gcc_target_options. */
4513 i386_gnu_triplet_regexp (struct gdbarch
*gdbarch
)
4515 return "(x86_64|i.86)";
4520 /* Implement the "in_indirect_branch_thunk" gdbarch function. */
4523 i386_in_indirect_branch_thunk (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
4525 return x86_in_indirect_branch_thunk (pc
, i386_register_names
,
4526 I386_EAX_REGNUM
, I386_EIP_REGNUM
);
4532 i386_elf_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4534 static const char *const stap_integer_prefixes
[] = { "$", NULL
};
4535 static const char *const stap_register_prefixes
[] = { "%", NULL
};
4536 static const char *const stap_register_indirection_prefixes
[] = { "(",
4538 static const char *const stap_register_indirection_suffixes
[] = { ")",
4541 /* We typically use stabs-in-ELF with the SVR4 register numbering. */
4542 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_svr4_reg_to_regnum
);
4544 /* Registering SystemTap handlers. */
4545 set_gdbarch_stap_integer_prefixes (gdbarch
, stap_integer_prefixes
);
4546 set_gdbarch_stap_register_prefixes (gdbarch
, stap_register_prefixes
);
4547 set_gdbarch_stap_register_indirection_prefixes (gdbarch
,
4548 stap_register_indirection_prefixes
);
4549 set_gdbarch_stap_register_indirection_suffixes (gdbarch
,
4550 stap_register_indirection_suffixes
);
4551 set_gdbarch_stap_is_single_operand (gdbarch
,
4552 i386_stap_is_single_operand
);
4553 set_gdbarch_stap_parse_special_token (gdbarch
,
4554 i386_stap_parse_special_token
);
4555 set_gdbarch_stap_adjust_register (gdbarch
,
4556 i386_stap_adjust_register
);
4558 set_gdbarch_in_indirect_branch_thunk (gdbarch
,
4559 i386_in_indirect_branch_thunk
);
4562 /* System V Release 4 (SVR4). */
4565 i386_svr4_init_abi (struct gdbarch_info info
, struct gdbarch
*gdbarch
)
4567 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
4569 /* System V Release 4 uses ELF. */
4570 i386_elf_init_abi (info
, gdbarch
);
4572 /* System V Release 4 has shared libraries. */
4573 set_gdbarch_skip_trampoline_code (gdbarch
, find_solib_trampoline_target
);
4575 tdep
->sigtramp_p
= i386_svr4_sigtramp_p
;
4576 tdep
->sigcontext_addr
= i386_svr4_sigcontext_addr
;
4577 tdep
->sc_pc_offset
= 36 + 14 * 4;
4578 tdep
->sc_sp_offset
= 36 + 17 * 4;
4580 tdep
->jb_pc_offset
= 20;
4585 /* i386 register groups. In addition to the normal groups, add "mmx"
4588 static const reggroup
*i386_sse_reggroup
;
4589 static const reggroup
*i386_mmx_reggroup
;
4592 i386_init_reggroups (void)
4594 i386_sse_reggroup
= reggroup_new ("sse", USER_REGGROUP
);
4595 i386_mmx_reggroup
= reggroup_new ("mmx", USER_REGGROUP
);
4599 i386_add_reggroups (struct gdbarch
*gdbarch
)
4601 reggroup_add (gdbarch
, i386_sse_reggroup
);
4602 reggroup_add (gdbarch
, i386_mmx_reggroup
);
4606 i386_register_reggroup_p (struct gdbarch
*gdbarch
, int regnum
,
4607 const struct reggroup
*group
)
4609 const i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
4610 int fp_regnum_p
, mmx_regnum_p
, xmm_regnum_p
, mxcsr_regnum_p
,
4611 ymm_regnum_p
, ymmh_regnum_p
, ymm_avx512_regnum_p
, ymmh_avx512_regnum_p
,
4612 bndr_regnum_p
, bnd_regnum_p
, zmm_regnum_p
, zmmh_regnum_p
,
4613 mpx_ctrl_regnum_p
, xmm_avx512_regnum_p
,
4614 avx512_p
, avx_p
, sse_p
, pkru_regnum_p
;
4616 /* Don't include pseudo registers, except for MMX, in any register
4618 if (i386_byte_regnum_p (gdbarch
, regnum
))
4621 if (i386_word_regnum_p (gdbarch
, regnum
))
4624 if (i386_dword_regnum_p (gdbarch
, regnum
))
4627 mmx_regnum_p
= i386_mmx_regnum_p (gdbarch
, regnum
);
4628 if (group
== i386_mmx_reggroup
)
4629 return mmx_regnum_p
;
4631 pkru_regnum_p
= i386_pkru_regnum_p(gdbarch
, regnum
);
4632 xmm_regnum_p
= i386_xmm_regnum_p (gdbarch
, regnum
);
4633 xmm_avx512_regnum_p
= i386_xmm_avx512_regnum_p (gdbarch
, regnum
);
4634 mxcsr_regnum_p
= i386_mxcsr_regnum_p (gdbarch
, regnum
);
4635 if (group
== i386_sse_reggroup
)
4636 return xmm_regnum_p
|| xmm_avx512_regnum_p
|| mxcsr_regnum_p
;
4638 ymm_regnum_p
= i386_ymm_regnum_p (gdbarch
, regnum
);
4639 ymm_avx512_regnum_p
= i386_ymm_avx512_regnum_p (gdbarch
, regnum
);
4640 zmm_regnum_p
= i386_zmm_regnum_p (gdbarch
, regnum
);
4642 avx512_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4643 == X86_XSTATE_AVX_AVX512_MASK
);
4644 avx_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4645 == X86_XSTATE_AVX_MASK
) && !avx512_p
;
4646 sse_p
= ((tdep
->xcr0
& X86_XSTATE_AVX_AVX512_MASK
)
4647 == X86_XSTATE_SSE_MASK
) && !avx512_p
&& ! avx_p
;
4649 if (group
== vector_reggroup
)
4650 return (mmx_regnum_p
4651 || (zmm_regnum_p
&& avx512_p
)
4652 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && avx_p
)
4653 || ((xmm_regnum_p
|| xmm_avx512_regnum_p
) && sse_p
)
4656 fp_regnum_p
= (i386_fp_regnum_p (gdbarch
, regnum
)
4657 || i386_fpc_regnum_p (gdbarch
, regnum
));
4658 if (group
== float_reggroup
)
4661 /* For "info reg all", don't include upper YMM registers nor XMM
4662 registers when AVX is supported. */
4663 ymmh_regnum_p
= i386_ymmh_regnum_p (gdbarch
, regnum
);
4664 ymmh_avx512_regnum_p
= i386_ymmh_avx512_regnum_p (gdbarch
, regnum
);
4665 zmmh_regnum_p
= i386_zmmh_regnum_p (gdbarch
, regnum
);
4666 if (group
== all_reggroup
4667 && (((xmm_regnum_p
|| xmm_avx512_regnum_p
) && !sse_p
)
4668 || ((ymm_regnum_p
|| ymm_avx512_regnum_p
) && !avx_p
)
4670 || ymmh_avx512_regnum_p
4674 bnd_regnum_p
= i386_bnd_regnum_p (gdbarch
, regnum
);
4675 if (group
== all_reggroup
4676 && ((bnd_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4677 return bnd_regnum_p
;
4679 bndr_regnum_p
= i386_bndr_regnum_p (gdbarch
, regnum
);
4680 if (group
== all_reggroup
4681 && ((bndr_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4684 mpx_ctrl_regnum_p
= i386_mpx_ctrl_regnum_p (gdbarch
, regnum
);
4685 if (group
== all_reggroup
4686 && ((mpx_ctrl_regnum_p
&& (tdep
->xcr0
& X86_XSTATE_MPX_MASK
))))
4687 return mpx_ctrl_regnum_p
;
4689 if (group
== general_reggroup
)
4690 return (!fp_regnum_p
4694 && !xmm_avx512_regnum_p
4697 && !ymm_avx512_regnum_p
4698 && !ymmh_avx512_regnum_p
4701 && !mpx_ctrl_regnum_p
4706 return default_register_reggroup_p (gdbarch
, regnum
, group
);
4710 /* Get the ARGIth function argument for the current function. */
4713 i386_fetch_pointer_argument (frame_info_ptr frame
, int argi
,
4716 struct gdbarch
*gdbarch
= get_frame_arch (frame
);
4717 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4718 CORE_ADDR sp
= get_frame_register_unsigned (frame
, I386_ESP_REGNUM
);
4719 return read_memory_unsigned_integer (sp
+ (4 * (argi
+ 1)), 4, byte_order
);
4722 #define PREFIX_REPZ 0x01
4723 #define PREFIX_REPNZ 0x02
4724 #define PREFIX_LOCK 0x04
4725 #define PREFIX_DATA 0x08
4726 #define PREFIX_ADDR 0x10
4738 /* i386 arith/logic operations */
4751 struct i386_record_s
4753 struct gdbarch
*gdbarch
;
4754 struct regcache
*regcache
;
4755 CORE_ADDR orig_addr
;
4761 uint8_t mod
, reg
, rm
;
4770 /* Parse the "modrm" part of the memory address irp->addr points at.
4771 Returns -1 if something goes wrong, 0 otherwise. */
4774 i386_record_modrm (struct i386_record_s
*irp
)
4776 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4778 if (record_read_memory (gdbarch
, irp
->addr
, &irp
->modrm
, 1))
4782 irp
->mod
= (irp
->modrm
>> 6) & 3;
4783 irp
->reg
= (irp
->modrm
>> 3) & 7;
4784 irp
->rm
= irp
->modrm
& 7;
4789 /* Extract the memory address that the current instruction writes to,
4790 and return it in *ADDR. Return -1 if something goes wrong. */
4793 i386_record_lea_modrm_addr (struct i386_record_s
*irp
, uint64_t *addr
)
4795 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4796 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
4801 if (irp
->aflag
|| irp
->regmap
[X86_RECORD_R8_REGNUM
])
4808 uint8_t base
= irp
->rm
;
4813 if (record_read_memory (gdbarch
, irp
->addr
, &byte
, 1))
4816 scale
= (byte
>> 6) & 3;
4817 index
= ((byte
>> 3) & 7) | irp
->rex_x
;
4825 if ((base
& 7) == 5)
4828 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4831 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4832 if (irp
->regmap
[X86_RECORD_R8_REGNUM
] && !havesib
)
4833 *addr
+= irp
->addr
+ irp
->rip_offset
;
4837 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4840 *addr
= (int8_t) buf
[0];
4843 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 4))
4845 *addr
= extract_signed_integer (buf
, 4, byte_order
);
4853 if (base
== 4 && irp
->popl_esp_hack
)
4854 *addr
+= irp
->popl_esp_hack
;
4855 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[base
],
4858 if (irp
->aflag
== 2)
4863 *addr
= (uint32_t) (offset64
+ *addr
);
4865 if (havesib
&& (index
!= 4 || scale
!= 0))
4867 regcache_raw_read_unsigned (irp
->regcache
, irp
->regmap
[index
],
4869 if (irp
->aflag
== 2)
4870 *addr
+= offset64
<< scale
;
4872 *addr
= (uint32_t) (*addr
+ (offset64
<< scale
));
4877 /* Since we are in 64-bit mode with ADDR32 prefix, zero-extend
4878 address from 32-bit to 64-bit. */
4879 *addr
= (uint32_t) *addr
;
4890 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4893 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4899 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 1))
4902 *addr
= (int8_t) buf
[0];
4905 if (record_read_memory (gdbarch
, irp
->addr
, buf
, 2))
4908 *addr
= extract_signed_integer (buf
, 2, byte_order
);
4915 regcache_raw_read_unsigned (irp
->regcache
,
4916 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4918 *addr
= (uint32_t) (*addr
+ offset64
);
4919 regcache_raw_read_unsigned (irp
->regcache
,
4920 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4922 *addr
= (uint32_t) (*addr
+ offset64
);
4925 regcache_raw_read_unsigned (irp
->regcache
,
4926 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4928 *addr
= (uint32_t) (*addr
+ offset64
);
4929 regcache_raw_read_unsigned (irp
->regcache
,
4930 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4932 *addr
= (uint32_t) (*addr
+ offset64
);
4935 regcache_raw_read_unsigned (irp
->regcache
,
4936 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4938 *addr
= (uint32_t) (*addr
+ offset64
);
4939 regcache_raw_read_unsigned (irp
->regcache
,
4940 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4942 *addr
= (uint32_t) (*addr
+ offset64
);
4945 regcache_raw_read_unsigned (irp
->regcache
,
4946 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4948 *addr
= (uint32_t) (*addr
+ offset64
);
4949 regcache_raw_read_unsigned (irp
->regcache
,
4950 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4952 *addr
= (uint32_t) (*addr
+ offset64
);
4955 regcache_raw_read_unsigned (irp
->regcache
,
4956 irp
->regmap
[X86_RECORD_RESI_REGNUM
],
4958 *addr
= (uint32_t) (*addr
+ offset64
);
4961 regcache_raw_read_unsigned (irp
->regcache
,
4962 irp
->regmap
[X86_RECORD_REDI_REGNUM
],
4964 *addr
= (uint32_t) (*addr
+ offset64
);
4967 regcache_raw_read_unsigned (irp
->regcache
,
4968 irp
->regmap
[X86_RECORD_REBP_REGNUM
],
4970 *addr
= (uint32_t) (*addr
+ offset64
);
4973 regcache_raw_read_unsigned (irp
->regcache
,
4974 irp
->regmap
[X86_RECORD_REBX_REGNUM
],
4976 *addr
= (uint32_t) (*addr
+ offset64
);
4986 /* Record the address and contents of the memory that will be changed
4987 by the current instruction. Return -1 if something goes wrong, 0
4991 i386_record_lea_modrm (struct i386_record_s
*irp
)
4993 struct gdbarch
*gdbarch
= irp
->gdbarch
;
4996 if (irp
->override
>= 0)
4998 if (record_full_memory_query
)
5001 Process record ignores the memory change of instruction at address %s\n\
5002 because it can't get the value of the segment register.\n\
5003 Do you want to stop the program?"),
5004 paddress (gdbarch
, irp
->orig_addr
)))
5011 if (i386_record_lea_modrm_addr (irp
, &addr
))
5014 if (record_full_arch_list_add_mem (addr
, 1 << irp
->ot
))
5020 /* Record the effects of a push operation. Return -1 if something
5021 goes wrong, 0 otherwise. */
5024 i386_record_push (struct i386_record_s
*irp
, int size
)
5028 if (record_full_arch_list_add_reg (irp
->regcache
,
5029 irp
->regmap
[X86_RECORD_RESP_REGNUM
]))
5031 regcache_raw_read_unsigned (irp
->regcache
,
5032 irp
->regmap
[X86_RECORD_RESP_REGNUM
],
5034 if (record_full_arch_list_add_mem ((CORE_ADDR
) addr
- size
, size
))
5041 /* Defines contents to record. */
5042 #define I386_SAVE_FPU_REGS 0xfffd
5043 #define I386_SAVE_FPU_ENV 0xfffe
5044 #define I386_SAVE_FPU_ENV_REG_STACK 0xffff
5046 /* Record the values of the floating point registers which will be
5047 changed by the current instruction. Returns -1 if something is
5048 wrong, 0 otherwise. */
5050 static int i386_record_floats (struct gdbarch
*gdbarch
,
5051 struct i386_record_s
*ir
,
5054 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
5057 /* Oza: Because of floating point insn push/pop of fpu stack is going to
5058 happen. Currently we store st0-st7 registers, but we need not store all
5059 registers all the time, in future we use ftag register and record only
5060 those who are not marked as an empty. */
5062 if (I386_SAVE_FPU_REGS
== iregnum
)
5064 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_ST0_REGNUM (tdep
) + 7; i
++)
5066 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5070 else if (I386_SAVE_FPU_ENV
== iregnum
)
5072 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5074 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5078 else if (I386_SAVE_FPU_ENV_REG_STACK
== iregnum
)
5080 for (i
= I387_ST0_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5081 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5084 else if ((iregnum
>= I387_ST0_REGNUM (tdep
)) &&
5085 (iregnum
<= I387_FOP_REGNUM (tdep
)))
5087 if (record_full_arch_list_add_reg (ir
->regcache
,iregnum
))
5092 /* Parameter error. */
5095 if(I386_SAVE_FPU_ENV
!= iregnum
)
5097 for (i
= I387_FCTRL_REGNUM (tdep
); i
<= I387_FOP_REGNUM (tdep
); i
++)
5099 if (record_full_arch_list_add_reg (ir
->regcache
, i
))
5106 /* Parse the current instruction, and record the values of the
5107 registers and memory that will be changed by the current
5108 instruction. Returns -1 if something goes wrong, 0 otherwise. */
5110 #define I386_RECORD_FULL_ARCH_LIST_ADD_REG(regnum) \
5111 record_full_arch_list_add_reg (ir.regcache, ir.regmap[(regnum)])
5114 i386_process_record (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
5115 CORE_ADDR input_addr
)
5117 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
5123 gdb_byte buf
[I386_MAX_REGISTER_SIZE
];
5124 struct i386_record_s ir
;
5125 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
5129 memset (&ir
, 0, sizeof (struct i386_record_s
));
5130 ir
.regcache
= regcache
;
5131 ir
.addr
= input_addr
;
5132 ir
.orig_addr
= input_addr
;
5136 ir
.popl_esp_hack
= 0;
5137 ir
.regmap
= tdep
->record_regmap
;
5138 ir
.gdbarch
= gdbarch
;
5140 if (record_debug
> 1)
5141 gdb_printf (gdb_stdlog
, "Process record: i386_process_record "
5143 paddress (gdbarch
, ir
.addr
));
5148 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5151 switch (opcode8
) /* Instruction prefixes */
5153 case REPE_PREFIX_OPCODE
:
5154 prefixes
|= PREFIX_REPZ
;
5156 case REPNE_PREFIX_OPCODE
:
5157 prefixes
|= PREFIX_REPNZ
;
5159 case LOCK_PREFIX_OPCODE
:
5160 prefixes
|= PREFIX_LOCK
;
5162 case CS_PREFIX_OPCODE
:
5163 ir
.override
= X86_RECORD_CS_REGNUM
;
5165 case SS_PREFIX_OPCODE
:
5166 ir
.override
= X86_RECORD_SS_REGNUM
;
5168 case DS_PREFIX_OPCODE
:
5169 ir
.override
= X86_RECORD_DS_REGNUM
;
5171 case ES_PREFIX_OPCODE
:
5172 ir
.override
= X86_RECORD_ES_REGNUM
;
5174 case FS_PREFIX_OPCODE
:
5175 ir
.override
= X86_RECORD_FS_REGNUM
;
5177 case GS_PREFIX_OPCODE
:
5178 ir
.override
= X86_RECORD_GS_REGNUM
;
5180 case DATA_PREFIX_OPCODE
:
5181 prefixes
|= PREFIX_DATA
;
5183 case ADDR_PREFIX_OPCODE
:
5184 prefixes
|= PREFIX_ADDR
;
5186 case 0x40: /* i386 inc %eax */
5187 case 0x41: /* i386 inc %ecx */
5188 case 0x42: /* i386 inc %edx */
5189 case 0x43: /* i386 inc %ebx */
5190 case 0x44: /* i386 inc %esp */
5191 case 0x45: /* i386 inc %ebp */
5192 case 0x46: /* i386 inc %esi */
5193 case 0x47: /* i386 inc %edi */
5194 case 0x48: /* i386 dec %eax */
5195 case 0x49: /* i386 dec %ecx */
5196 case 0x4a: /* i386 dec %edx */
5197 case 0x4b: /* i386 dec %ebx */
5198 case 0x4c: /* i386 dec %esp */
5199 case 0x4d: /* i386 dec %ebp */
5200 case 0x4e: /* i386 dec %esi */
5201 case 0x4f: /* i386 dec %edi */
5202 if (ir
.regmap
[X86_RECORD_R8_REGNUM
]) /* 64 bit target */
5205 rex_w
= (opcode8
>> 3) & 1;
5206 rex_r
= (opcode8
& 0x4) << 1;
5207 ir
.rex_x
= (opcode8
& 0x2) << 2;
5208 ir
.rex_b
= (opcode8
& 0x1) << 3;
5210 else /* 32 bit target */
5219 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && rex_w
== 1)
5225 if (prefixes
& PREFIX_DATA
)
5228 if (prefixes
& PREFIX_ADDR
)
5230 else if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5233 /* Now check op code. */
5234 opcode
= (uint32_t) opcode8
;
5239 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
5242 opcode
= (uint32_t) opcode8
| 0x0f00;
5246 case 0x00: /* arith & logic */
5294 if (((opcode
>> 3) & 7) != OP_CMPL
)
5296 if ((opcode
& 1) == 0)
5299 ir
.ot
= ir
.dflag
+ OT_WORD
;
5301 switch ((opcode
>> 1) & 3)
5303 case 0: /* OP Ev, Gv */
5304 if (i386_record_modrm (&ir
))
5308 if (i386_record_lea_modrm (&ir
))
5314 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5316 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5319 case 1: /* OP Gv, Ev */
5320 if (i386_record_modrm (&ir
))
5323 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5325 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5327 case 2: /* OP A, Iv */
5328 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5332 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5335 case 0x80: /* GRP1 */
5339 if (i386_record_modrm (&ir
))
5342 if (ir
.reg
!= OP_CMPL
)
5344 if ((opcode
& 1) == 0)
5347 ir
.ot
= ir
.dflag
+ OT_WORD
;
5354 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5355 if (i386_record_lea_modrm (&ir
))
5359 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5361 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5364 case 0x40: /* inc */
5373 case 0x48: /* dec */
5382 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 7);
5383 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5386 case 0xf6: /* GRP3 */
5388 if ((opcode
& 1) == 0)
5391 ir
.ot
= ir
.dflag
+ OT_WORD
;
5392 if (i386_record_modrm (&ir
))
5395 if (ir
.mod
!= 3 && ir
.reg
== 0)
5396 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5401 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5407 if (i386_record_lea_modrm (&ir
))
5413 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5415 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5417 if (ir
.reg
== 3) /* neg */
5418 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5424 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5425 if (ir
.ot
!= OT_BYTE
)
5426 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5427 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5431 opcode
= opcode
<< 8 | ir
.modrm
;
5437 case 0xfe: /* GRP4 */
5438 case 0xff: /* GRP5 */
5439 if (i386_record_modrm (&ir
))
5441 if (ir
.reg
>= 2 && opcode
== 0xfe)
5444 opcode
= opcode
<< 8 | ir
.modrm
;
5451 if ((opcode
& 1) == 0)
5454 ir
.ot
= ir
.dflag
+ OT_WORD
;
5457 if (i386_record_lea_modrm (&ir
))
5463 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5465 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5467 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5470 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5472 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5474 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5477 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
5478 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5480 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5484 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5487 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5489 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5494 opcode
= opcode
<< 8 | ir
.modrm
;
5500 case 0x84: /* test */
5504 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5507 case 0x98: /* CWDE/CBW */
5508 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5511 case 0x99: /* CDQ/CWD */
5512 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5513 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5516 case 0x0faf: /* imul */
5519 ir
.ot
= ir
.dflag
+ OT_WORD
;
5520 if (i386_record_modrm (&ir
))
5523 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5524 else if (opcode
== 0x6b)
5527 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5529 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5530 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5533 case 0x0fc0: /* xadd */
5535 if ((opcode
& 1) == 0)
5538 ir
.ot
= ir
.dflag
+ OT_WORD
;
5539 if (i386_record_modrm (&ir
))
5544 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5546 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5547 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5549 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5553 if (i386_record_lea_modrm (&ir
))
5555 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5557 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5559 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5562 case 0x0fb0: /* cmpxchg */
5564 if ((opcode
& 1) == 0)
5567 ir
.ot
= ir
.dflag
+ OT_WORD
;
5568 if (i386_record_modrm (&ir
))
5573 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5574 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5576 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5580 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5581 if (i386_record_lea_modrm (&ir
))
5584 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5587 case 0x0fc7: /* cmpxchg8b / rdrand / rdseed */
5588 if (i386_record_modrm (&ir
))
5592 /* rdrand and rdseed use the 3 bits of the REG field of ModR/M as
5593 an extended opcode. rdrand has bits 110 (/6) and rdseed
5594 has bits 111 (/7). */
5595 if (ir
.reg
== 6 || ir
.reg
== 7)
5597 /* The storage register is described by the 3 R/M bits, but the
5598 REX.B prefix may be used to give access to registers
5599 R8~R15. In this case ir.rex_b + R/M will give us the register
5600 in the range R8~R15.
5602 REX.W may also be used to access 64-bit registers, but we
5603 already record entire registers and not just partial bits
5605 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
+ ir
.rm
);
5606 /* These instructions also set conditional bits. */
5607 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5612 /* We don't handle this particular instruction yet. */
5614 opcode
= opcode
<< 8 | ir
.modrm
;
5618 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5619 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
5620 if (i386_record_lea_modrm (&ir
))
5622 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5625 case 0x50: /* push */
5635 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5637 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5641 case 0x06: /* push es */
5642 case 0x0e: /* push cs */
5643 case 0x16: /* push ss */
5644 case 0x1e: /* push ds */
5645 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5650 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5654 case 0x0fa0: /* push fs */
5655 case 0x0fa8: /* push gs */
5656 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5661 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5665 case 0x60: /* pusha */
5666 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5671 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 4)))
5675 case 0x58: /* pop */
5683 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5684 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5687 case 0x61: /* popa */
5688 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5693 for (regnum
= X86_RECORD_REAX_REGNUM
;
5694 regnum
<= X86_RECORD_REDI_REGNUM
;
5696 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5699 case 0x8f: /* pop */
5700 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5701 ir
.ot
= ir
.dflag
? OT_QUAD
: OT_WORD
;
5703 ir
.ot
= ir
.dflag
+ OT_WORD
;
5704 if (i386_record_modrm (&ir
))
5707 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
5710 ir
.popl_esp_hack
= 1 << ir
.ot
;
5711 if (i386_record_lea_modrm (&ir
))
5714 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5717 case 0xc8: /* enter */
5718 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5719 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
5721 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
5725 case 0xc9: /* leave */
5726 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5727 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
5730 case 0x07: /* pop es */
5731 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5736 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5737 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_ES_REGNUM
);
5738 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5741 case 0x17: /* pop ss */
5742 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5747 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5748 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_SS_REGNUM
);
5749 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5752 case 0x1f: /* pop ds */
5753 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
5758 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5759 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_DS_REGNUM
);
5760 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5763 case 0x0fa1: /* pop fs */
5764 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5765 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_FS_REGNUM
);
5766 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5769 case 0x0fa9: /* pop gs */
5770 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
5771 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
5772 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5775 case 0x88: /* mov */
5779 if ((opcode
& 1) == 0)
5782 ir
.ot
= ir
.dflag
+ OT_WORD
;
5784 if (i386_record_modrm (&ir
))
5789 if (opcode
== 0xc6 || opcode
== 0xc7)
5790 ir
.rip_offset
= (ir
.ot
> OT_LONG
) ? 4 : (1 << ir
.ot
);
5791 if (i386_record_lea_modrm (&ir
))
5796 if (opcode
== 0xc6 || opcode
== 0xc7)
5798 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5800 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5804 case 0x8a: /* mov */
5806 if ((opcode
& 1) == 0)
5809 ir
.ot
= ir
.dflag
+ OT_WORD
;
5810 if (i386_record_modrm (&ir
))
5813 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5815 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5818 case 0x8c: /* mov seg */
5819 if (i386_record_modrm (&ir
))
5824 opcode
= opcode
<< 8 | ir
.modrm
;
5829 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5833 if (i386_record_lea_modrm (&ir
))
5838 case 0x8e: /* mov seg */
5839 if (i386_record_modrm (&ir
))
5844 regnum
= X86_RECORD_ES_REGNUM
;
5847 regnum
= X86_RECORD_SS_REGNUM
;
5850 regnum
= X86_RECORD_DS_REGNUM
;
5853 regnum
= X86_RECORD_FS_REGNUM
;
5856 regnum
= X86_RECORD_GS_REGNUM
;
5860 opcode
= opcode
<< 8 | ir
.modrm
;
5864 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
5865 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
5868 case 0x0fb6: /* movzbS */
5869 case 0x0fb7: /* movzwS */
5870 case 0x0fbe: /* movsbS */
5871 case 0x0fbf: /* movswS */
5872 if (i386_record_modrm (&ir
))
5874 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
5877 case 0x8d: /* lea */
5878 if (i386_record_modrm (&ir
))
5883 opcode
= opcode
<< 8 | ir
.modrm
;
5888 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5890 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
5893 case 0xa0: /* mov EAX */
5896 case 0xd7: /* xlat */
5897 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5900 case 0xa2: /* mov EAX */
5902 if (ir
.override
>= 0)
5904 if (record_full_memory_query
)
5907 Process record ignores the memory change of instruction at address %s\n\
5908 because it can't get the value of the segment register.\n\
5909 Do you want to stop the program?"),
5910 paddress (gdbarch
, ir
.orig_addr
)))
5916 if ((opcode
& 1) == 0)
5919 ir
.ot
= ir
.dflag
+ OT_WORD
;
5922 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 8))
5925 addr
= extract_unsigned_integer (buf
, 8, byte_order
);
5929 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 4))
5932 addr
= extract_unsigned_integer (buf
, 4, byte_order
);
5936 if (record_read_memory (gdbarch
, ir
.addr
, buf
, 2))
5939 addr
= extract_unsigned_integer (buf
, 2, byte_order
);
5941 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
5946 case 0xb0: /* mov R, Ib */
5954 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((ir
.regmap
[X86_RECORD_R8_REGNUM
])
5955 ? ((opcode
& 0x7) | ir
.rex_b
)
5956 : ((opcode
& 0x7) & 0x3));
5959 case 0xb8: /* mov R, Iv */
5967 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 0x7) | ir
.rex_b
);
5970 case 0x91: /* xchg R, EAX */
5977 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
5978 I386_RECORD_FULL_ARCH_LIST_ADD_REG (opcode
& 0x7);
5981 case 0x86: /* xchg Ev, Gv */
5983 if ((opcode
& 1) == 0)
5986 ir
.ot
= ir
.dflag
+ OT_WORD
;
5987 if (i386_record_modrm (&ir
))
5992 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
5994 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
5998 if (i386_record_lea_modrm (&ir
))
6002 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
6004 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6007 case 0xc4: /* les Gv */
6008 case 0xc5: /* lds Gv */
6009 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6015 case 0x0fb2: /* lss Gv */
6016 case 0x0fb4: /* lfs Gv */
6017 case 0x0fb5: /* lgs Gv */
6018 if (i386_record_modrm (&ir
))
6026 opcode
= opcode
<< 8 | ir
.modrm
;
6031 case 0xc4: /* les Gv */
6032 regnum
= X86_RECORD_ES_REGNUM
;
6034 case 0xc5: /* lds Gv */
6035 regnum
= X86_RECORD_DS_REGNUM
;
6037 case 0x0fb2: /* lss Gv */
6038 regnum
= X86_RECORD_SS_REGNUM
;
6040 case 0x0fb4: /* lfs Gv */
6041 regnum
= X86_RECORD_FS_REGNUM
;
6043 case 0x0fb5: /* lgs Gv */
6044 regnum
= X86_RECORD_GS_REGNUM
;
6047 I386_RECORD_FULL_ARCH_LIST_ADD_REG (regnum
);
6048 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6049 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6052 case 0xc0: /* shifts */
6058 if ((opcode
& 1) == 0)
6061 ir
.ot
= ir
.dflag
+ OT_WORD
;
6062 if (i386_record_modrm (&ir
))
6064 if (ir
.mod
!= 3 && (opcode
== 0xd2 || opcode
== 0xd3))
6066 if (i386_record_lea_modrm (&ir
))
6072 if (ir
.ot
== OT_BYTE
&& !ir
.regmap
[X86_RECORD_R8_REGNUM
])
6074 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
);
6076 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6083 if (i386_record_modrm (&ir
))
6087 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
))
6092 if (i386_record_lea_modrm (&ir
))
6097 case 0xd8: /* Floats. */
6105 if (i386_record_modrm (&ir
))
6107 ir
.reg
|= ((opcode
& 7) << 3);
6113 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6121 /* For fcom, ficom nothing to do. */
6127 /* For fcomp, ficomp pop FPU stack, store all. */
6128 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6155 /* For fadd, fmul, fsub, fsubr, fdiv, fdivr, fiadd, fimul,
6156 fisub, fisubr, fidiv, fidivr, modR/M.reg is an extension
6157 of code, always affects st(0) register. */
6158 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6182 /* Handling fld, fild. */
6183 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6187 switch (ir
.reg
>> 4)
6190 if (record_full_arch_list_add_mem (addr64
, 4))
6194 if (record_full_arch_list_add_mem (addr64
, 8))
6200 if (record_full_arch_list_add_mem (addr64
, 2))
6206 switch (ir
.reg
>> 4)
6209 if (record_full_arch_list_add_mem (addr64
, 4))
6211 if (3 == (ir
.reg
& 7))
6213 /* For fstp m32fp. */
6214 if (i386_record_floats (gdbarch
, &ir
,
6215 I386_SAVE_FPU_REGS
))
6220 if (record_full_arch_list_add_mem (addr64
, 4))
6222 if ((3 == (ir
.reg
& 7))
6223 || (5 == (ir
.reg
& 7))
6224 || (7 == (ir
.reg
& 7)))
6226 /* For fstp insn. */
6227 if (i386_record_floats (gdbarch
, &ir
,
6228 I386_SAVE_FPU_REGS
))
6233 if (record_full_arch_list_add_mem (addr64
, 8))
6235 if (3 == (ir
.reg
& 7))
6237 /* For fstp m64fp. */
6238 if (i386_record_floats (gdbarch
, &ir
,
6239 I386_SAVE_FPU_REGS
))
6244 if ((3 <= (ir
.reg
& 7)) && (6 <= (ir
.reg
& 7)))
6246 /* For fistp, fbld, fild, fbstp. */
6247 if (i386_record_floats (gdbarch
, &ir
,
6248 I386_SAVE_FPU_REGS
))
6253 if (record_full_arch_list_add_mem (addr64
, 2))
6262 if (i386_record_floats (gdbarch
, &ir
,
6263 I386_SAVE_FPU_ENV_REG_STACK
))
6268 if (i386_record_floats (gdbarch
, &ir
, I387_FCTRL_REGNUM (tdep
)))
6273 if (i386_record_floats (gdbarch
, &ir
,
6274 I386_SAVE_FPU_ENV_REG_STACK
))
6280 if (record_full_arch_list_add_mem (addr64
, 28))
6285 if (record_full_arch_list_add_mem (addr64
, 14))
6291 if (record_full_arch_list_add_mem (addr64
, 2))
6293 /* Insn fstp, fbstp. */
6294 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6299 if (record_full_arch_list_add_mem (addr64
, 10))
6305 if (record_full_arch_list_add_mem (addr64
, 28))
6311 if (record_full_arch_list_add_mem (addr64
, 14))
6315 if (record_full_arch_list_add_mem (addr64
, 80))
6318 if (i386_record_floats (gdbarch
, &ir
,
6319 I386_SAVE_FPU_ENV_REG_STACK
))
6323 if (record_full_arch_list_add_mem (addr64
, 8))
6326 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6331 opcode
= opcode
<< 8 | ir
.modrm
;
6336 /* Opcode is an extension of modR/M byte. */
6342 if (i386_record_floats (gdbarch
, &ir
, I387_ST0_REGNUM (tdep
)))
6346 if (0x0c == (ir
.modrm
>> 4))
6348 if ((ir
.modrm
& 0x0f) <= 7)
6350 if (i386_record_floats (gdbarch
, &ir
,
6351 I386_SAVE_FPU_REGS
))
6356 if (i386_record_floats (gdbarch
, &ir
,
6357 I387_ST0_REGNUM (tdep
)))
6359 /* If only st(0) is changing, then we have already
6361 if ((ir
.modrm
& 0x0f) - 0x08)
6363 if (i386_record_floats (gdbarch
, &ir
,
6364 I387_ST0_REGNUM (tdep
) +
6365 ((ir
.modrm
& 0x0f) - 0x08)))
6383 if (i386_record_floats (gdbarch
, &ir
,
6384 I387_ST0_REGNUM (tdep
)))
6402 if (i386_record_floats (gdbarch
, &ir
,
6403 I386_SAVE_FPU_REGS
))
6407 if (i386_record_floats (gdbarch
, &ir
,
6408 I387_ST0_REGNUM (tdep
)))
6410 if (i386_record_floats (gdbarch
, &ir
,
6411 I387_ST0_REGNUM (tdep
) + 1))
6418 if (0xe9 == ir
.modrm
)
6420 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6423 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6425 if (i386_record_floats (gdbarch
, &ir
,
6426 I387_ST0_REGNUM (tdep
)))
6428 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6430 if (i386_record_floats (gdbarch
, &ir
,
6431 I387_ST0_REGNUM (tdep
) +
6435 else if ((ir
.modrm
& 0x0f) - 0x08)
6437 if (i386_record_floats (gdbarch
, &ir
,
6438 I387_ST0_REGNUM (tdep
) +
6439 ((ir
.modrm
& 0x0f) - 0x08)))
6445 if (0xe3 == ir
.modrm
)
6447 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_ENV
))
6450 else if ((0x0c == ir
.modrm
>> 4) || (0x0d == ir
.modrm
>> 4))
6452 if (i386_record_floats (gdbarch
, &ir
,
6453 I387_ST0_REGNUM (tdep
)))
6455 if (((ir
.modrm
& 0x0f) > 0) && ((ir
.modrm
& 0x0f) <= 7))
6457 if (i386_record_floats (gdbarch
, &ir
,
6458 I387_ST0_REGNUM (tdep
) +
6462 else if ((ir
.modrm
& 0x0f) - 0x08)
6464 if (i386_record_floats (gdbarch
, &ir
,
6465 I387_ST0_REGNUM (tdep
) +
6466 ((ir
.modrm
& 0x0f) - 0x08)))
6472 if ((0x0c == ir
.modrm
>> 4)
6473 || (0x0d == ir
.modrm
>> 4)
6474 || (0x0f == ir
.modrm
>> 4))
6476 if ((ir
.modrm
& 0x0f) <= 7)
6478 if (i386_record_floats (gdbarch
, &ir
,
6479 I387_ST0_REGNUM (tdep
) +
6485 if (i386_record_floats (gdbarch
, &ir
,
6486 I387_ST0_REGNUM (tdep
) +
6487 ((ir
.modrm
& 0x0f) - 0x08)))
6493 if (0x0c == ir
.modrm
>> 4)
6495 if (i386_record_floats (gdbarch
, &ir
,
6496 I387_FTAG_REGNUM (tdep
)))
6499 else if ((0x0d == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6501 if ((ir
.modrm
& 0x0f) <= 7)
6503 if (i386_record_floats (gdbarch
, &ir
,
6504 I387_ST0_REGNUM (tdep
) +
6510 if (i386_record_floats (gdbarch
, &ir
,
6511 I386_SAVE_FPU_REGS
))
6517 if ((0x0c == ir
.modrm
>> 4)
6518 || (0x0e == ir
.modrm
>> 4)
6519 || (0x0f == ir
.modrm
>> 4)
6520 || (0xd9 == ir
.modrm
))
6522 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6527 if (0xe0 == ir
.modrm
)
6529 if (record_full_arch_list_add_reg (ir
.regcache
,
6533 else if ((0x0f == ir
.modrm
>> 4) || (0x0e == ir
.modrm
>> 4))
6535 if (i386_record_floats (gdbarch
, &ir
, I386_SAVE_FPU_REGS
))
6543 case 0xa4: /* movsS */
6545 case 0xaa: /* stosS */
6547 case 0x6c: /* insS */
6549 regcache_raw_read_unsigned (ir
.regcache
,
6550 ir
.regmap
[X86_RECORD_RECX_REGNUM
],
6556 if ((opcode
& 1) == 0)
6559 ir
.ot
= ir
.dflag
+ OT_WORD
;
6560 regcache_raw_read_unsigned (ir
.regcache
,
6561 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
6564 regcache_raw_read_unsigned (ir
.regcache
,
6565 ir
.regmap
[X86_RECORD_ES_REGNUM
],
6567 regcache_raw_read_unsigned (ir
.regcache
,
6568 ir
.regmap
[X86_RECORD_DS_REGNUM
],
6570 if (ir
.aflag
&& (es
!= ds
))
6572 /* addr += ((uint32_t) read_register (I386_ES_REGNUM)) << 4; */
6573 if (record_full_memory_query
)
6576 Process record ignores the memory change of instruction at address %s\n\
6577 because it can't get the value of the segment register.\n\
6578 Do you want to stop the program?"),
6579 paddress (gdbarch
, ir
.orig_addr
)))
6585 if (record_full_arch_list_add_mem (addr
, 1 << ir
.ot
))
6589 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6590 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6591 if (opcode
== 0xa4 || opcode
== 0xa5)
6592 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6593 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6594 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6598 case 0xa6: /* cmpsS */
6600 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6601 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6602 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6603 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6604 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6607 case 0xac: /* lodsS */
6609 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6610 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6611 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6612 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6613 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6616 case 0xae: /* scasS */
6618 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
6619 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6620 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6621 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6624 case 0x6e: /* outsS */
6626 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
6627 if (prefixes
& (PREFIX_REPZ
| PREFIX_REPNZ
))
6628 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6629 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6632 case 0xe4: /* port I/O */
6636 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6637 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6647 case 0xc2: /* ret im */
6648 case 0xc3: /* ret */
6649 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6650 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6653 case 0xca: /* lret im */
6654 case 0xcb: /* lret */
6655 case 0xcf: /* iret */
6656 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6657 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6658 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6661 case 0xe8: /* call im */
6662 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6664 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6668 case 0x9a: /* lcall im */
6669 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6674 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_CS_REGNUM
);
6675 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6679 case 0xe9: /* jmp im */
6680 case 0xea: /* ljmp im */
6681 case 0xeb: /* jmp Jb */
6682 case 0x70: /* jcc Jb */
6698 case 0x0f80: /* jcc Jv */
6716 case 0x0f90: /* setcc Gv */
6732 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6734 if (i386_record_modrm (&ir
))
6737 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rex_b
? (ir
.rm
| ir
.rex_b
)
6741 if (i386_record_lea_modrm (&ir
))
6746 case 0x0f40: /* cmov Gv, Ev */
6762 if (i386_record_modrm (&ir
))
6765 if (ir
.dflag
== OT_BYTE
)
6767 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
6771 case 0x9c: /* pushf */
6772 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6773 if (ir
.regmap
[X86_RECORD_R8_REGNUM
] && ir
.dflag
)
6775 if (i386_record_push (&ir
, 1 << (ir
.dflag
+ 1)))
6779 case 0x9d: /* popf */
6780 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
6781 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6784 case 0x9e: /* sahf */
6785 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6791 case 0xf5: /* cmc */
6792 case 0xf8: /* clc */
6793 case 0xf9: /* stc */
6794 case 0xfc: /* cld */
6795 case 0xfd: /* std */
6796 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6799 case 0x9f: /* lahf */
6800 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6805 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6806 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6809 /* bit operations */
6810 case 0x0fba: /* bt/bts/btr/btc Gv, im */
6811 ir
.ot
= ir
.dflag
+ OT_WORD
;
6812 if (i386_record_modrm (&ir
))
6817 opcode
= opcode
<< 8 | ir
.modrm
;
6823 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6826 if (i386_record_lea_modrm (&ir
))
6830 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6833 case 0x0fa3: /* bt Gv, Ev */
6834 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6837 case 0x0fab: /* bts */
6838 case 0x0fb3: /* btr */
6839 case 0x0fbb: /* btc */
6840 ir
.ot
= ir
.dflag
+ OT_WORD
;
6841 if (i386_record_modrm (&ir
))
6844 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
6848 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
6850 regcache_raw_read_unsigned (ir
.regcache
,
6851 ir
.regmap
[ir
.reg
| rex_r
],
6856 addr64
+= ((int16_t) addr
>> 4) << 4;
6859 addr64
+= ((int32_t) addr
>> 5) << 5;
6862 addr64
+= ((int64_t) addr
>> 6) << 6;
6865 if (record_full_arch_list_add_mem (addr64
, 1 << ir
.ot
))
6867 if (i386_record_lea_modrm (&ir
))
6870 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6873 case 0x0fbc: /* bsf */
6874 case 0x0fbd: /* bsr */
6875 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
6876 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6880 case 0x27: /* daa */
6881 case 0x2f: /* das */
6882 case 0x37: /* aaa */
6883 case 0x3f: /* aas */
6884 case 0xd4: /* aam */
6885 case 0xd5: /* aad */
6886 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6891 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6892 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6896 case 0x90: /* nop */
6897 if (prefixes
& PREFIX_LOCK
)
6904 case 0x9b: /* fwait */
6905 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
6907 opcode
= (uint32_t) opcode8
;
6913 case 0xcc: /* int3 */
6914 gdb_printf (gdb_stderr
,
6915 _("Process record does not support instruction "
6922 case 0xcd: /* int */
6926 if (record_read_memory (gdbarch
, ir
.addr
, &interrupt
, 1))
6929 if (interrupt
!= 0x80
6930 || tdep
->i386_intx80_record
== NULL
)
6932 gdb_printf (gdb_stderr
,
6933 _("Process record does not support "
6934 "instruction int 0x%02x.\n"),
6939 ret
= tdep
->i386_intx80_record (ir
.regcache
);
6946 case 0xce: /* into */
6947 gdb_printf (gdb_stderr
,
6948 _("Process record does not support "
6949 "instruction into.\n"));
6954 case 0xfa: /* cli */
6955 case 0xfb: /* sti */
6958 case 0x62: /* bound */
6959 gdb_printf (gdb_stderr
,
6960 _("Process record does not support "
6961 "instruction bound.\n"));
6966 case 0x0fc8: /* bswap reg */
6974 I386_RECORD_FULL_ARCH_LIST_ADD_REG ((opcode
& 7) | ir
.rex_b
);
6977 case 0xd6: /* salc */
6978 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
6983 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
6984 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6987 case 0xe0: /* loopnz */
6988 case 0xe1: /* loopz */
6989 case 0xe2: /* loop */
6990 case 0xe3: /* jecxz */
6991 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
6992 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
6995 case 0x0f30: /* wrmsr */
6996 gdb_printf (gdb_stderr
,
6997 _("Process record does not support "
6998 "instruction wrmsr.\n"));
7003 case 0x0f32: /* rdmsr */
7004 gdb_printf (gdb_stderr
,
7005 _("Process record does not support "
7006 "instruction rdmsr.\n"));
7011 case 0x0f01f9: /* rdtscp */
7012 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7014 case 0x0f31: /* rdtsc */
7015 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7016 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7019 case 0x0f34: /* sysenter */
7022 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7027 if (tdep
->i386_sysenter_record
== NULL
)
7029 gdb_printf (gdb_stderr
,
7030 _("Process record does not support "
7031 "instruction sysenter.\n"));
7035 ret
= tdep
->i386_sysenter_record (ir
.regcache
);
7041 case 0x0f35: /* sysexit */
7042 gdb_printf (gdb_stderr
,
7043 _("Process record does not support "
7044 "instruction sysexit.\n"));
7049 case 0x0f05: /* syscall */
7052 if (tdep
->i386_syscall_record
== NULL
)
7054 gdb_printf (gdb_stderr
,
7055 _("Process record does not support "
7056 "instruction syscall.\n"));
7060 ret
= tdep
->i386_syscall_record (ir
.regcache
);
7066 case 0x0f07: /* sysret */
7067 gdb_printf (gdb_stderr
,
7068 _("Process record does not support "
7069 "instruction sysret.\n"));
7074 case 0x0fa2: /* cpuid */
7075 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7076 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7077 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7078 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7081 case 0xf4: /* hlt */
7082 gdb_printf (gdb_stderr
,
7083 _("Process record does not support "
7084 "instruction hlt.\n"));
7090 if (i386_record_modrm (&ir
))
7097 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7101 if (i386_record_lea_modrm (&ir
))
7110 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7114 opcode
= opcode
<< 8 | ir
.modrm
;
7121 if (i386_record_modrm (&ir
))
7123 if (ir
.modrm
== 0xf9)
7125 opcode
= (opcode
<< 8) | 0xf9;
7137 opcode
= opcode
<< 8 | ir
.modrm
;
7140 if (ir
.override
>= 0)
7142 if (record_full_memory_query
)
7145 Process record ignores the memory change of instruction at address %s\n\
7146 because it can't get the value of the segment register.\n\
7147 Do you want to stop the program?"),
7148 paddress (gdbarch
, ir
.orig_addr
)))
7154 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7156 if (record_full_arch_list_add_mem (addr64
, 2))
7159 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7161 if (record_full_arch_list_add_mem (addr64
, 8))
7166 if (record_full_arch_list_add_mem (addr64
, 4))
7177 case 0: /* monitor */
7180 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7184 opcode
= opcode
<< 8 | ir
.modrm
;
7192 if (ir
.override
>= 0)
7194 if (record_full_memory_query
)
7197 Process record ignores the memory change of instruction at address %s\n\
7198 because it can't get the value of the segment register.\n\
7199 Do you want to stop the program?"),
7200 paddress (gdbarch
, ir
.orig_addr
)))
7208 if (i386_record_lea_modrm_addr (&ir
, &addr64
))
7210 if (record_full_arch_list_add_mem (addr64
, 2))
7213 if (ir
.regmap
[X86_RECORD_R8_REGNUM
])
7215 if (record_full_arch_list_add_mem (addr64
, 8))
7220 if (record_full_arch_list_add_mem (addr64
, 4))
7232 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7233 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7237 else if (ir
.rm
== 1)
7245 opcode
= opcode
<< 8 | ir
.modrm
;
7252 if (record_full_arch_list_add_reg (ir
.regcache
, ir
.rm
| ir
.rex_b
))
7258 if (i386_record_lea_modrm (&ir
))
7261 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7264 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7266 case 7: /* invlpg */
7269 if (ir
.rm
== 0 && ir
.regmap
[X86_RECORD_R8_REGNUM
])
7270 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_GS_REGNUM
);
7274 opcode
= opcode
<< 8 | ir
.modrm
;
7279 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7283 opcode
= opcode
<< 8 | ir
.modrm
;
7289 case 0x0f08: /* invd */
7290 case 0x0f09: /* wbinvd */
7293 case 0x63: /* arpl */
7294 if (i386_record_modrm (&ir
))
7296 if (ir
.mod
== 3 || ir
.regmap
[X86_RECORD_R8_REGNUM
])
7298 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.regmap
[X86_RECORD_R8_REGNUM
]
7299 ? (ir
.reg
| rex_r
) : ir
.rm
);
7303 ir
.ot
= ir
.dflag
? OT_LONG
: OT_WORD
;
7304 if (i386_record_lea_modrm (&ir
))
7307 if (!ir
.regmap
[X86_RECORD_R8_REGNUM
])
7308 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7311 case 0x0f02: /* lar */
7312 case 0x0f03: /* lsl */
7313 if (i386_record_modrm (&ir
))
7315 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7316 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7320 if (i386_record_modrm (&ir
))
7322 if (ir
.mod
== 3 && ir
.reg
== 3)
7325 opcode
= opcode
<< 8 | ir
.modrm
;
7337 /* nop (multi byte) */
7340 case 0x0f20: /* mov reg, crN */
7341 case 0x0f22: /* mov crN, reg */
7342 if (i386_record_modrm (&ir
))
7344 if ((ir
.modrm
& 0xc0) != 0xc0)
7347 opcode
= opcode
<< 8 | ir
.modrm
;
7358 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7360 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7364 opcode
= opcode
<< 8 | ir
.modrm
;
7370 case 0x0f21: /* mov reg, drN */
7371 case 0x0f23: /* mov drN, reg */
7372 if (i386_record_modrm (&ir
))
7374 if ((ir
.modrm
& 0xc0) != 0xc0 || ir
.reg
== 4
7375 || ir
.reg
== 5 || ir
.reg
>= 8)
7378 opcode
= opcode
<< 8 | ir
.modrm
;
7382 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7384 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
7387 case 0x0f06: /* clts */
7388 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7391 /* MMX 3DNow! SSE SSE2 SSE3 SSSE3 SSE4 */
7393 case 0x0f0d: /* 3DNow! prefetch */
7396 case 0x0f0e: /* 3DNow! femms */
7397 case 0x0f77: /* emms */
7398 if (i386_fpc_regnum_p (gdbarch
, I387_FTAG_REGNUM(tdep
)))
7400 record_full_arch_list_add_reg (ir
.regcache
, I387_FTAG_REGNUM(tdep
));
7403 case 0x0f0f: /* 3DNow! data */
7404 if (i386_record_modrm (&ir
))
7406 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7411 case 0x0c: /* 3DNow! pi2fw */
7412 case 0x0d: /* 3DNow! pi2fd */
7413 case 0x1c: /* 3DNow! pf2iw */
7414 case 0x1d: /* 3DNow! pf2id */
7415 case 0x8a: /* 3DNow! pfnacc */
7416 case 0x8e: /* 3DNow! pfpnacc */
7417 case 0x90: /* 3DNow! pfcmpge */
7418 case 0x94: /* 3DNow! pfmin */
7419 case 0x96: /* 3DNow! pfrcp */
7420 case 0x97: /* 3DNow! pfrsqrt */
7421 case 0x9a: /* 3DNow! pfsub */
7422 case 0x9e: /* 3DNow! pfadd */
7423 case 0xa0: /* 3DNow! pfcmpgt */
7424 case 0xa4: /* 3DNow! pfmax */
7425 case 0xa6: /* 3DNow! pfrcpit1 */
7426 case 0xa7: /* 3DNow! pfrsqit1 */
7427 case 0xaa: /* 3DNow! pfsubr */
7428 case 0xae: /* 3DNow! pfacc */
7429 case 0xb0: /* 3DNow! pfcmpeq */
7430 case 0xb4: /* 3DNow! pfmul */
7431 case 0xb6: /* 3DNow! pfrcpit2 */
7432 case 0xb7: /* 3DNow! pmulhrw */
7433 case 0xbb: /* 3DNow! pswapd */
7434 case 0xbf: /* 3DNow! pavgusb */
7435 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
7436 goto no_support_3dnow_data
;
7437 record_full_arch_list_add_reg (ir
.regcache
, ir
.reg
);
7441 no_support_3dnow_data
:
7442 opcode
= (opcode
<< 8) | opcode8
;
7448 case 0x0faa: /* rsm */
7449 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7450 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REAX_REGNUM
);
7451 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RECX_REGNUM
);
7452 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDX_REGNUM
);
7453 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBX_REGNUM
);
7454 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESP_REGNUM
);
7455 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REBP_REGNUM
);
7456 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_RESI_REGNUM
);
7457 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REDI_REGNUM
);
7461 if (i386_record_modrm (&ir
))
7465 case 0: /* fxsave */
7469 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7470 if (i386_record_lea_modrm_addr (&ir
, &tmpu64
))
7472 if (record_full_arch_list_add_mem (tmpu64
, 512))
7477 case 1: /* fxrstor */
7481 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7483 for (i
= I387_MM0_REGNUM (tdep
);
7484 i386_mmx_regnum_p (gdbarch
, i
); i
++)
7485 record_full_arch_list_add_reg (ir
.regcache
, i
);
7487 for (i
= I387_XMM0_REGNUM (tdep
);
7488 i386_xmm_regnum_p (gdbarch
, i
); i
++)
7489 record_full_arch_list_add_reg (ir
.regcache
, i
);
7491 if (i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7492 record_full_arch_list_add_reg (ir
.regcache
,
7493 I387_MXCSR_REGNUM(tdep
));
7495 for (i
= I387_ST0_REGNUM (tdep
);
7496 i386_fp_regnum_p (gdbarch
, i
); i
++)
7497 record_full_arch_list_add_reg (ir
.regcache
, i
);
7499 for (i
= I387_FCTRL_REGNUM (tdep
);
7500 i386_fpc_regnum_p (gdbarch
, i
); i
++)
7501 record_full_arch_list_add_reg (ir
.regcache
, i
);
7505 case 2: /* ldmxcsr */
7506 if (!i386_mxcsr_regnum_p (gdbarch
, I387_MXCSR_REGNUM(tdep
)))
7508 record_full_arch_list_add_reg (ir
.regcache
, I387_MXCSR_REGNUM(tdep
));
7511 case 3: /* stmxcsr */
7513 if (i386_record_lea_modrm (&ir
))
7517 case 5: /* lfence */
7518 case 6: /* mfence */
7519 case 7: /* sfence clflush */
7523 opcode
= (opcode
<< 8) | ir
.modrm
;
7529 case 0x0fc3: /* movnti */
7530 ir
.ot
= (ir
.dflag
== 2) ? OT_QUAD
: OT_LONG
;
7531 if (i386_record_modrm (&ir
))
7536 if (i386_record_lea_modrm (&ir
))
7540 /* Add prefix to opcode. */
7655 /* Mask out PREFIX_ADDR. */
7656 switch ((prefixes
& ~PREFIX_ADDR
))
7668 reswitch_prefix_add
:
7676 if (record_read_memory (gdbarch
, ir
.addr
, &opcode8
, 1))
7679 opcode
= (uint32_t) opcode8
| opcode
<< 8;
7680 goto reswitch_prefix_add
;
7683 case 0x0f10: /* movups */
7684 case 0x660f10: /* movupd */
7685 case 0xf30f10: /* movss */
7686 case 0xf20f10: /* movsd */
7687 case 0x0f12: /* movlps */
7688 case 0x660f12: /* movlpd */
7689 case 0xf30f12: /* movsldup */
7690 case 0xf20f12: /* movddup */
7691 case 0x0f14: /* unpcklps */
7692 case 0x660f14: /* unpcklpd */
7693 case 0x0f15: /* unpckhps */
7694 case 0x660f15: /* unpckhpd */
7695 case 0x0f16: /* movhps */
7696 case 0x660f16: /* movhpd */
7697 case 0xf30f16: /* movshdup */
7698 case 0x0f28: /* movaps */
7699 case 0x660f28: /* movapd */
7700 case 0x0f2a: /* cvtpi2ps */
7701 case 0x660f2a: /* cvtpi2pd */
7702 case 0xf30f2a: /* cvtsi2ss */
7703 case 0xf20f2a: /* cvtsi2sd */
7704 case 0x0f2c: /* cvttps2pi */
7705 case 0x660f2c: /* cvttpd2pi */
7706 case 0x0f2d: /* cvtps2pi */
7707 case 0x660f2d: /* cvtpd2pi */
7708 case 0x660f3800: /* pshufb */
7709 case 0x660f3801: /* phaddw */
7710 case 0x660f3802: /* phaddd */
7711 case 0x660f3803: /* phaddsw */
7712 case 0x660f3804: /* pmaddubsw */
7713 case 0x660f3805: /* phsubw */
7714 case 0x660f3806: /* phsubd */
7715 case 0x660f3807: /* phsubsw */
7716 case 0x660f3808: /* psignb */
7717 case 0x660f3809: /* psignw */
7718 case 0x660f380a: /* psignd */
7719 case 0x660f380b: /* pmulhrsw */
7720 case 0x660f3810: /* pblendvb */
7721 case 0x660f3814: /* blendvps */
7722 case 0x660f3815: /* blendvpd */
7723 case 0x660f381c: /* pabsb */
7724 case 0x660f381d: /* pabsw */
7725 case 0x660f381e: /* pabsd */
7726 case 0x660f3820: /* pmovsxbw */
7727 case 0x660f3821: /* pmovsxbd */
7728 case 0x660f3822: /* pmovsxbq */
7729 case 0x660f3823: /* pmovsxwd */
7730 case 0x660f3824: /* pmovsxwq */
7731 case 0x660f3825: /* pmovsxdq */
7732 case 0x660f3828: /* pmuldq */
7733 case 0x660f3829: /* pcmpeqq */
7734 case 0x660f382a: /* movntdqa */
7735 case 0x660f3a08: /* roundps */
7736 case 0x660f3a09: /* roundpd */
7737 case 0x660f3a0a: /* roundss */
7738 case 0x660f3a0b: /* roundsd */
7739 case 0x660f3a0c: /* blendps */
7740 case 0x660f3a0d: /* blendpd */
7741 case 0x660f3a0e: /* pblendw */
7742 case 0x660f3a0f: /* palignr */
7743 case 0x660f3a20: /* pinsrb */
7744 case 0x660f3a21: /* insertps */
7745 case 0x660f3a22: /* pinsrd pinsrq */
7746 case 0x660f3a40: /* dpps */
7747 case 0x660f3a41: /* dppd */
7748 case 0x660f3a42: /* mpsadbw */
7749 case 0x660f3a60: /* pcmpestrm */
7750 case 0x660f3a61: /* pcmpestri */
7751 case 0x660f3a62: /* pcmpistrm */
7752 case 0x660f3a63: /* pcmpistri */
7753 case 0x0f51: /* sqrtps */
7754 case 0x660f51: /* sqrtpd */
7755 case 0xf20f51: /* sqrtsd */
7756 case 0xf30f51: /* sqrtss */
7757 case 0x0f52: /* rsqrtps */
7758 case 0xf30f52: /* rsqrtss */
7759 case 0x0f53: /* rcpps */
7760 case 0xf30f53: /* rcpss */
7761 case 0x0f54: /* andps */
7762 case 0x660f54: /* andpd */
7763 case 0x0f55: /* andnps */
7764 case 0x660f55: /* andnpd */
7765 case 0x0f56: /* orps */
7766 case 0x660f56: /* orpd */
7767 case 0x0f57: /* xorps */
7768 case 0x660f57: /* xorpd */
7769 case 0x0f58: /* addps */
7770 case 0x660f58: /* addpd */
7771 case 0xf20f58: /* addsd */
7772 case 0xf30f58: /* addss */
7773 case 0x0f59: /* mulps */
7774 case 0x660f59: /* mulpd */
7775 case 0xf20f59: /* mulsd */
7776 case 0xf30f59: /* mulss */
7777 case 0x0f5a: /* cvtps2pd */
7778 case 0x660f5a: /* cvtpd2ps */
7779 case 0xf20f5a: /* cvtsd2ss */
7780 case 0xf30f5a: /* cvtss2sd */
7781 case 0x0f5b: /* cvtdq2ps */
7782 case 0x660f5b: /* cvtps2dq */
7783 case 0xf30f5b: /* cvttps2dq */
7784 case 0x0f5c: /* subps */
7785 case 0x660f5c: /* subpd */
7786 case 0xf20f5c: /* subsd */
7787 case 0xf30f5c: /* subss */
7788 case 0x0f5d: /* minps */
7789 case 0x660f5d: /* minpd */
7790 case 0xf20f5d: /* minsd */
7791 case 0xf30f5d: /* minss */
7792 case 0x0f5e: /* divps */
7793 case 0x660f5e: /* divpd */
7794 case 0xf20f5e: /* divsd */
7795 case 0xf30f5e: /* divss */
7796 case 0x0f5f: /* maxps */
7797 case 0x660f5f: /* maxpd */
7798 case 0xf20f5f: /* maxsd */
7799 case 0xf30f5f: /* maxss */
7800 case 0x660f60: /* punpcklbw */
7801 case 0x660f61: /* punpcklwd */
7802 case 0x660f62: /* punpckldq */
7803 case 0x660f63: /* packsswb */
7804 case 0x660f64: /* pcmpgtb */
7805 case 0x660f65: /* pcmpgtw */
7806 case 0x660f66: /* pcmpgtd */
7807 case 0x660f67: /* packuswb */
7808 case 0x660f68: /* punpckhbw */
7809 case 0x660f69: /* punpckhwd */
7810 case 0x660f6a: /* punpckhdq */
7811 case 0x660f6b: /* packssdw */
7812 case 0x660f6c: /* punpcklqdq */
7813 case 0x660f6d: /* punpckhqdq */
7814 case 0x660f6e: /* movd */
7815 case 0x660f6f: /* movdqa */
7816 case 0xf30f6f: /* movdqu */
7817 case 0x660f70: /* pshufd */
7818 case 0xf20f70: /* pshuflw */
7819 case 0xf30f70: /* pshufhw */
7820 case 0x660f74: /* pcmpeqb */
7821 case 0x660f75: /* pcmpeqw */
7822 case 0x660f76: /* pcmpeqd */
7823 case 0x660f7c: /* haddpd */
7824 case 0xf20f7c: /* haddps */
7825 case 0x660f7d: /* hsubpd */
7826 case 0xf20f7d: /* hsubps */
7827 case 0xf30f7e: /* movq */
7828 case 0x0fc2: /* cmpps */
7829 case 0x660fc2: /* cmppd */
7830 case 0xf20fc2: /* cmpsd */
7831 case 0xf30fc2: /* cmpss */
7832 case 0x660fc4: /* pinsrw */
7833 case 0x0fc6: /* shufps */
7834 case 0x660fc6: /* shufpd */
7835 case 0x660fd0: /* addsubpd */
7836 case 0xf20fd0: /* addsubps */
7837 case 0x660fd1: /* psrlw */
7838 case 0x660fd2: /* psrld */
7839 case 0x660fd3: /* psrlq */
7840 case 0x660fd4: /* paddq */
7841 case 0x660fd5: /* pmullw */
7842 case 0xf30fd6: /* movq2dq */
7843 case 0x660fd8: /* psubusb */
7844 case 0x660fd9: /* psubusw */
7845 case 0x660fda: /* pminub */
7846 case 0x660fdb: /* pand */
7847 case 0x660fdc: /* paddusb */
7848 case 0x660fdd: /* paddusw */
7849 case 0x660fde: /* pmaxub */
7850 case 0x660fdf: /* pandn */
7851 case 0x660fe0: /* pavgb */
7852 case 0x660fe1: /* psraw */
7853 case 0x660fe2: /* psrad */
7854 case 0x660fe3: /* pavgw */
7855 case 0x660fe4: /* pmulhuw */
7856 case 0x660fe5: /* pmulhw */
7857 case 0x660fe6: /* cvttpd2dq */
7858 case 0xf20fe6: /* cvtpd2dq */
7859 case 0xf30fe6: /* cvtdq2pd */
7860 case 0x660fe8: /* psubsb */
7861 case 0x660fe9: /* psubsw */
7862 case 0x660fea: /* pminsw */
7863 case 0x660feb: /* por */
7864 case 0x660fec: /* paddsb */
7865 case 0x660fed: /* paddsw */
7866 case 0x660fee: /* pmaxsw */
7867 case 0x660fef: /* pxor */
7868 case 0xf20ff0: /* lddqu */
7869 case 0x660ff1: /* psllw */
7870 case 0x660ff2: /* pslld */
7871 case 0x660ff3: /* psllq */
7872 case 0x660ff4: /* pmuludq */
7873 case 0x660ff5: /* pmaddwd */
7874 case 0x660ff6: /* psadbw */
7875 case 0x660ff8: /* psubb */
7876 case 0x660ff9: /* psubw */
7877 case 0x660ffa: /* psubd */
7878 case 0x660ffb: /* psubq */
7879 case 0x660ffc: /* paddb */
7880 case 0x660ffd: /* paddw */
7881 case 0x660ffe: /* paddd */
7882 if (i386_record_modrm (&ir
))
7885 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.reg
))
7887 record_full_arch_list_add_reg (ir
.regcache
,
7888 I387_XMM0_REGNUM (tdep
) + ir
.reg
);
7889 if ((opcode
& 0xfffffffc) == 0x660f3a60)
7890 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
7893 case 0x0f11: /* movups */
7894 case 0x660f11: /* movupd */
7895 case 0xf30f11: /* movss */
7896 case 0xf20f11: /* movsd */
7897 case 0x0f13: /* movlps */
7898 case 0x660f13: /* movlpd */
7899 case 0x0f17: /* movhps */
7900 case 0x660f17: /* movhpd */
7901 case 0x0f29: /* movaps */
7902 case 0x660f29: /* movapd */
7903 case 0x660f3a14: /* pextrb */
7904 case 0x660f3a15: /* pextrw */
7905 case 0x660f3a16: /* pextrd pextrq */
7906 case 0x660f3a17: /* extractps */
7907 case 0x660f7f: /* movdqa */
7908 case 0xf30f7f: /* movdqu */
7909 if (i386_record_modrm (&ir
))
7913 if (opcode
== 0x0f13 || opcode
== 0x660f13
7914 || opcode
== 0x0f17 || opcode
== 0x660f17)
7917 if (!i386_xmm_regnum_p (gdbarch
,
7918 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
7920 record_full_arch_list_add_reg (ir
.regcache
,
7921 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
7943 if (i386_record_lea_modrm (&ir
))
7948 case 0x0f2b: /* movntps */
7949 case 0x660f2b: /* movntpd */
7950 case 0x0fe7: /* movntq */
7951 case 0x660fe7: /* movntdq */
7954 if (opcode
== 0x0fe7)
7958 if (i386_record_lea_modrm (&ir
))
7962 case 0xf30f2c: /* cvttss2si */
7963 case 0xf20f2c: /* cvttsd2si */
7964 case 0xf30f2d: /* cvtss2si */
7965 case 0xf20f2d: /* cvtsd2si */
7966 case 0xf20f38f0: /* crc32 */
7967 case 0xf20f38f1: /* crc32 */
7968 case 0x0f50: /* movmskps */
7969 case 0x660f50: /* movmskpd */
7970 case 0x0fc5: /* pextrw */
7971 case 0x660fc5: /* pextrw */
7972 case 0x0fd7: /* pmovmskb */
7973 case 0x660fd7: /* pmovmskb */
7974 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
| rex_r
);
7977 case 0x0f3800: /* pshufb */
7978 case 0x0f3801: /* phaddw */
7979 case 0x0f3802: /* phaddd */
7980 case 0x0f3803: /* phaddsw */
7981 case 0x0f3804: /* pmaddubsw */
7982 case 0x0f3805: /* phsubw */
7983 case 0x0f3806: /* phsubd */
7984 case 0x0f3807: /* phsubsw */
7985 case 0x0f3808: /* psignb */
7986 case 0x0f3809: /* psignw */
7987 case 0x0f380a: /* psignd */
7988 case 0x0f380b: /* pmulhrsw */
7989 case 0x0f381c: /* pabsb */
7990 case 0x0f381d: /* pabsw */
7991 case 0x0f381e: /* pabsd */
7992 case 0x0f382b: /* packusdw */
7993 case 0x0f3830: /* pmovzxbw */
7994 case 0x0f3831: /* pmovzxbd */
7995 case 0x0f3832: /* pmovzxbq */
7996 case 0x0f3833: /* pmovzxwd */
7997 case 0x0f3834: /* pmovzxwq */
7998 case 0x0f3835: /* pmovzxdq */
7999 case 0x0f3837: /* pcmpgtq */
8000 case 0x0f3838: /* pminsb */
8001 case 0x0f3839: /* pminsd */
8002 case 0x0f383a: /* pminuw */
8003 case 0x0f383b: /* pminud */
8004 case 0x0f383c: /* pmaxsb */
8005 case 0x0f383d: /* pmaxsd */
8006 case 0x0f383e: /* pmaxuw */
8007 case 0x0f383f: /* pmaxud */
8008 case 0x0f3840: /* pmulld */
8009 case 0x0f3841: /* phminposuw */
8010 case 0x0f3a0f: /* palignr */
8011 case 0x0f60: /* punpcklbw */
8012 case 0x0f61: /* punpcklwd */
8013 case 0x0f62: /* punpckldq */
8014 case 0x0f63: /* packsswb */
8015 case 0x0f64: /* pcmpgtb */
8016 case 0x0f65: /* pcmpgtw */
8017 case 0x0f66: /* pcmpgtd */
8018 case 0x0f67: /* packuswb */
8019 case 0x0f68: /* punpckhbw */
8020 case 0x0f69: /* punpckhwd */
8021 case 0x0f6a: /* punpckhdq */
8022 case 0x0f6b: /* packssdw */
8023 case 0x0f6e: /* movd */
8024 case 0x0f6f: /* movq */
8025 case 0x0f70: /* pshufw */
8026 case 0x0f74: /* pcmpeqb */
8027 case 0x0f75: /* pcmpeqw */
8028 case 0x0f76: /* pcmpeqd */
8029 case 0x0fc4: /* pinsrw */
8030 case 0x0fd1: /* psrlw */
8031 case 0x0fd2: /* psrld */
8032 case 0x0fd3: /* psrlq */
8033 case 0x0fd4: /* paddq */
8034 case 0x0fd5: /* pmullw */
8035 case 0xf20fd6: /* movdq2q */
8036 case 0x0fd8: /* psubusb */
8037 case 0x0fd9: /* psubusw */
8038 case 0x0fda: /* pminub */
8039 case 0x0fdb: /* pand */
8040 case 0x0fdc: /* paddusb */
8041 case 0x0fdd: /* paddusw */
8042 case 0x0fde: /* pmaxub */
8043 case 0x0fdf: /* pandn */
8044 case 0x0fe0: /* pavgb */
8045 case 0x0fe1: /* psraw */
8046 case 0x0fe2: /* psrad */
8047 case 0x0fe3: /* pavgw */
8048 case 0x0fe4: /* pmulhuw */
8049 case 0x0fe5: /* pmulhw */
8050 case 0x0fe8: /* psubsb */
8051 case 0x0fe9: /* psubsw */
8052 case 0x0fea: /* pminsw */
8053 case 0x0feb: /* por */
8054 case 0x0fec: /* paddsb */
8055 case 0x0fed: /* paddsw */
8056 case 0x0fee: /* pmaxsw */
8057 case 0x0fef: /* pxor */
8058 case 0x0ff1: /* psllw */
8059 case 0x0ff2: /* pslld */
8060 case 0x0ff3: /* psllq */
8061 case 0x0ff4: /* pmuludq */
8062 case 0x0ff5: /* pmaddwd */
8063 case 0x0ff6: /* psadbw */
8064 case 0x0ff8: /* psubb */
8065 case 0x0ff9: /* psubw */
8066 case 0x0ffa: /* psubd */
8067 case 0x0ffb: /* psubq */
8068 case 0x0ffc: /* paddb */
8069 case 0x0ffd: /* paddw */
8070 case 0x0ffe: /* paddd */
8071 if (i386_record_modrm (&ir
))
8073 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.reg
))
8075 record_full_arch_list_add_reg (ir
.regcache
,
8076 I387_MM0_REGNUM (tdep
) + ir
.reg
);
8079 case 0x0f71: /* psllw */
8080 case 0x0f72: /* pslld */
8081 case 0x0f73: /* psllq */
8082 if (i386_record_modrm (&ir
))
8084 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8086 record_full_arch_list_add_reg (ir
.regcache
,
8087 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8090 case 0x660f71: /* psllw */
8091 case 0x660f72: /* pslld */
8092 case 0x660f73: /* psllq */
8093 if (i386_record_modrm (&ir
))
8096 if (!i386_xmm_regnum_p (gdbarch
, I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8098 record_full_arch_list_add_reg (ir
.regcache
,
8099 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8102 case 0x0f7e: /* movd */
8103 case 0x660f7e: /* movd */
8104 if (i386_record_modrm (&ir
))
8107 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.rm
| ir
.rex_b
);
8114 if (i386_record_lea_modrm (&ir
))
8119 case 0x0f7f: /* movq */
8120 if (i386_record_modrm (&ir
))
8124 if (!i386_mmx_regnum_p (gdbarch
, I387_MM0_REGNUM (tdep
) + ir
.rm
))
8126 record_full_arch_list_add_reg (ir
.regcache
,
8127 I387_MM0_REGNUM (tdep
) + ir
.rm
);
8132 if (i386_record_lea_modrm (&ir
))
8137 case 0xf30fb8: /* popcnt */
8138 if (i386_record_modrm (&ir
))
8140 I386_RECORD_FULL_ARCH_LIST_ADD_REG (ir
.reg
);
8141 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8144 case 0x660fd6: /* movq */
8145 if (i386_record_modrm (&ir
))
8150 if (!i386_xmm_regnum_p (gdbarch
,
8151 I387_XMM0_REGNUM (tdep
) + ir
.rm
))
8153 record_full_arch_list_add_reg (ir
.regcache
,
8154 I387_XMM0_REGNUM (tdep
) + ir
.rm
);
8159 if (i386_record_lea_modrm (&ir
))
8164 case 0x660f3817: /* ptest */
8165 case 0x0f2e: /* ucomiss */
8166 case 0x660f2e: /* ucomisd */
8167 case 0x0f2f: /* comiss */
8168 case 0x660f2f: /* comisd */
8169 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_EFLAGS_REGNUM
);
8172 case 0x0ff7: /* maskmovq */
8173 regcache_raw_read_unsigned (ir
.regcache
,
8174 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8176 if (record_full_arch_list_add_mem (addr
, 64))
8180 case 0x660ff7: /* maskmovdqu */
8181 regcache_raw_read_unsigned (ir
.regcache
,
8182 ir
.regmap
[X86_RECORD_REDI_REGNUM
],
8184 if (record_full_arch_list_add_mem (addr
, 128))
8199 /* In the future, maybe still need to deal with need_dasm. */
8200 I386_RECORD_FULL_ARCH_LIST_ADD_REG (X86_RECORD_REIP_REGNUM
);
8201 if (record_full_arch_list_add_end ())
8207 gdb_printf (gdb_stderr
,
8208 _("Process record does not support instruction 0x%02x "
8209 "at address %s.\n"),
8210 (unsigned int) (opcode
),
8211 paddress (gdbarch
, ir
.orig_addr
));
8215 static const int i386_record_regmap
[] =
8217 I386_EAX_REGNUM
, I386_ECX_REGNUM
, I386_EDX_REGNUM
, I386_EBX_REGNUM
,
8218 I386_ESP_REGNUM
, I386_EBP_REGNUM
, I386_ESI_REGNUM
, I386_EDI_REGNUM
,
8219 0, 0, 0, 0, 0, 0, 0, 0,
8220 I386_EIP_REGNUM
, I386_EFLAGS_REGNUM
, I386_CS_REGNUM
, I386_SS_REGNUM
,
8221 I386_DS_REGNUM
, I386_ES_REGNUM
, I386_FS_REGNUM
, I386_GS_REGNUM
8224 /* Check that the given address appears suitable for a fast
8225 tracepoint, which on x86-64 means that we need an instruction of at
8226 least 5 bytes, so that we can overwrite it with a 4-byte-offset
8227 jump and not have to worry about program jumps to an address in the
8228 middle of the tracepoint jump. On x86, it may be possible to use
8229 4-byte jumps with a 2-byte offset to a trampoline located in the
8230 bottom 64 KiB of memory. Returns 1 if OK, and writes a size
8231 of instruction to replace, and 0 if not, plus an explanatory
8235 i386_fast_tracepoint_valid_at (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
8240 /* Ask the target for the minimum instruction length supported. */
8241 jumplen
= target_get_min_fast_tracepoint_insn_len ();
8245 /* If the target does not support the get_min_fast_tracepoint_insn_len
8246 operation, assume that fast tracepoints will always be implemented
8247 using 4-byte relative jumps on both x86 and x86-64. */
8250 else if (jumplen
== 0)
8252 /* If the target does support get_min_fast_tracepoint_insn_len but
8253 returns zero, then the IPA has not loaded yet. In this case,
8254 we optimistically assume that truncated 2-byte relative jumps
8255 will be available on x86, and compensate later if this assumption
8256 turns out to be incorrect. On x86-64 architectures, 4-byte relative
8257 jumps will always be used. */
8258 jumplen
= (register_size (gdbarch
, 0) == 8) ? 5 : 4;
8261 /* Check for fit. */
8262 len
= gdb_insn_length (gdbarch
, addr
);
8266 /* Return a bit of target-specific detail to add to the caller's
8267 generic failure message. */
8269 *msg
= string_printf (_("; instruction is only %d bytes long, "
8270 "need at least %d bytes for the jump"),
8282 /* Return a floating-point format for a floating-point variable of
8283 length LEN in bits. If non-NULL, NAME is the name of its type.
8284 If no suitable type is found, return NULL. */
8286 static const struct floatformat
**
8287 i386_floatformat_for_type (struct gdbarch
*gdbarch
,
8288 const char *name
, int len
)
8290 if (len
== 128 && name
)
8291 if (strcmp (name
, "__float128") == 0
8292 || strcmp (name
, "_Float128") == 0
8293 || strcmp (name
, "complex _Float128") == 0
8294 || strcmp (name
, "complex(kind=16)") == 0
8295 || strcmp (name
, "COMPLEX(16)") == 0
8296 || strcmp (name
, "complex*32") == 0
8297 || strcmp (name
, "COMPLEX*32") == 0
8298 || strcmp (name
, "quad complex") == 0
8299 || strcmp (name
, "real(kind=16)") == 0
8300 || strcmp (name
, "real*16") == 0
8301 || strcmp (name
, "REAL*16") == 0
8302 || strcmp (name
, "REAL(16)") == 0)
8303 return floatformats_ieee_quad
;
8305 return default_floatformat_for_type (gdbarch
, name
, len
);
8308 /* Compute an XCR0 mask based on a target description. */
8311 i386_xcr0_from_tdesc (const struct target_desc
*tdesc
)
8313 if (! tdesc_has_registers (tdesc
))
8316 const struct tdesc_feature
*feature_core
;
8318 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8319 *feature_avx512
, *feature_pkeys
;
8321 /* Get core registers. */
8322 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8323 if (feature_core
== NULL
)
8326 /* Get SSE registers. */
8327 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8329 /* Try AVX registers. */
8330 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8332 /* Try MPX registers. */
8333 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8335 /* Try AVX512 registers. */
8336 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8339 feature_pkeys
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys");
8341 /* The XCR0 bits. */
8342 uint64_t xcr0
= X86_XSTATE_X87
;
8345 xcr0
|= X86_XSTATE_SSE
;
8349 /* AVX register description requires SSE register description. */
8353 xcr0
|= X86_XSTATE_AVX
;
8357 xcr0
|= X86_XSTATE_MPX_MASK
;
8361 /* AVX512 register description requires AVX register description. */
8365 xcr0
|= X86_XSTATE_AVX512
;
8369 xcr0
|= X86_XSTATE_PKRU
;
8375 i386_validate_tdesc_p (i386_gdbarch_tdep
*tdep
,
8376 struct tdesc_arch_data
*tdesc_data
)
8378 const struct target_desc
*tdesc
= tdep
->tdesc
;
8379 const struct tdesc_feature
*feature_core
;
8381 const struct tdesc_feature
*feature_sse
, *feature_avx
, *feature_mpx
,
8382 *feature_avx512
, *feature_pkeys
, *feature_segments
;
8383 int i
, num_regs
, valid_p
;
8385 if (! tdesc_has_registers (tdesc
))
8388 /* Get core registers. */
8389 feature_core
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.core");
8390 if (feature_core
== NULL
)
8393 /* Get SSE registers. */
8394 feature_sse
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.sse");
8396 /* Try AVX registers. */
8397 feature_avx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx");
8399 /* Try MPX registers. */
8400 feature_mpx
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx");
8402 /* Try AVX512 registers. */
8403 feature_avx512
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.avx512");
8405 /* Try segment base registers. */
8406 feature_segments
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.segments");
8409 feature_pkeys
= tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.pkeys");
8413 /* The XCR0 bits. */
8416 /* AVX512 register description requires AVX register description. */
8420 tdep
->xcr0
= X86_XSTATE_AVX_AVX512_MASK
;
8422 /* It may have been set by OSABI initialization function. */
8423 if (tdep
->k0_regnum
< 0)
8425 tdep
->k_register_names
= i386_k_names
;
8426 tdep
->k0_regnum
= I386_K0_REGNUM
;
8429 for (i
= 0; i
< I387_NUM_K_REGS
; i
++)
8430 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8431 tdep
->k0_regnum
+ i
,
8434 if (tdep
->num_zmm_regs
== 0)
8436 tdep
->zmmh_register_names
= i386_zmmh_names
;
8437 tdep
->num_zmm_regs
= 8;
8438 tdep
->zmm0h_regnum
= I386_ZMM0H_REGNUM
;
8441 for (i
= 0; i
< tdep
->num_zmm_regs
; i
++)
8442 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8443 tdep
->zmm0h_regnum
+ i
,
8444 tdep
->zmmh_register_names
[i
]);
8446 for (i
= 0; i
< tdep
->num_xmm_avx512_regs
; i
++)
8447 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8448 tdep
->xmm16_regnum
+ i
,
8449 tdep
->xmm_avx512_register_names
[i
]);
8451 for (i
= 0; i
< tdep
->num_ymm_avx512_regs
; i
++)
8452 valid_p
&= tdesc_numbered_register (feature_avx512
, tdesc_data
,
8453 tdep
->ymm16h_regnum
+ i
,
8454 tdep
->ymm16h_register_names
[i
]);
8458 /* AVX register description requires SSE register description. */
8462 if (!feature_avx512
)
8463 tdep
->xcr0
= X86_XSTATE_AVX_MASK
;
8465 /* It may have been set by OSABI initialization function. */
8466 if (tdep
->num_ymm_regs
== 0)
8468 tdep
->ymmh_register_names
= i386_ymmh_names
;
8469 tdep
->num_ymm_regs
= 8;
8470 tdep
->ymm0h_regnum
= I386_YMM0H_REGNUM
;
8473 for (i
= 0; i
< tdep
->num_ymm_regs
; i
++)
8474 valid_p
&= tdesc_numbered_register (feature_avx
, tdesc_data
,
8475 tdep
->ymm0h_regnum
+ i
,
8476 tdep
->ymmh_register_names
[i
]);
8478 else if (feature_sse
)
8479 tdep
->xcr0
= X86_XSTATE_SSE_MASK
;
8482 tdep
->xcr0
= X86_XSTATE_X87_MASK
;
8483 tdep
->num_xmm_regs
= 0;
8486 num_regs
= tdep
->num_core_regs
;
8487 for (i
= 0; i
< num_regs
; i
++)
8488 valid_p
&= tdesc_numbered_register (feature_core
, tdesc_data
, i
,
8489 tdep
->register_names
[i
]);
8493 /* Need to include %mxcsr, so add one. */
8494 num_regs
+= tdep
->num_xmm_regs
+ 1;
8495 for (; i
< num_regs
; i
++)
8496 valid_p
&= tdesc_numbered_register (feature_sse
, tdesc_data
, i
,
8497 tdep
->register_names
[i
]);
8502 tdep
->xcr0
|= X86_XSTATE_MPX_MASK
;
8504 if (tdep
->bnd0r_regnum
< 0)
8506 tdep
->mpx_register_names
= i386_mpx_names
;
8507 tdep
->bnd0r_regnum
= I386_BND0R_REGNUM
;
8508 tdep
->bndcfgu_regnum
= I386_BNDCFGU_REGNUM
;
8511 for (i
= 0; i
< I387_NUM_MPX_REGS
; i
++)
8512 valid_p
&= tdesc_numbered_register (feature_mpx
, tdesc_data
,
8513 I387_BND0R_REGNUM (tdep
) + i
,
8514 tdep
->mpx_register_names
[i
]);
8517 if (feature_segments
)
8519 if (tdep
->fsbase_regnum
< 0)
8520 tdep
->fsbase_regnum
= I386_FSBASE_REGNUM
;
8521 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8522 tdep
->fsbase_regnum
, "fs_base");
8523 valid_p
&= tdesc_numbered_register (feature_segments
, tdesc_data
,
8524 tdep
->fsbase_regnum
+ 1, "gs_base");
8529 tdep
->xcr0
|= X86_XSTATE_PKRU
;
8530 if (tdep
->pkru_regnum
< 0)
8532 tdep
->pkeys_register_names
= i386_pkeys_names
;
8533 tdep
->pkru_regnum
= I386_PKRU_REGNUM
;
8534 tdep
->num_pkeys_regs
= 1;
8537 for (i
= 0; i
< I387_NUM_PKEYS_REGS
; i
++)
8538 valid_p
&= tdesc_numbered_register (feature_pkeys
, tdesc_data
,
8539 I387_PKRU_REGNUM (tdep
) + i
,
8540 tdep
->pkeys_register_names
[i
]);
8548 /* Implement the type_align gdbarch function. */
8551 i386_type_align (struct gdbarch
*gdbarch
, struct type
*type
)
8553 type
= check_typedef (type
);
8555 if (gdbarch_ptr_bit (gdbarch
) == 32)
8557 if ((type
->code () == TYPE_CODE_INT
8558 || type
->code () == TYPE_CODE_FLT
)
8559 && type
->length () > 4)
8562 /* Handle x86's funny long double. */
8563 if (type
->code () == TYPE_CODE_FLT
8564 && gdbarch_long_double_bit (gdbarch
) == type
->length () * 8)
8572 /* Note: This is called for both i386 and amd64. */
8574 static struct gdbarch
*
8575 i386_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
8577 const struct target_desc
*tdesc
;
8583 x86_xsave_layout xsave_layout
= target_fetch_x86_xsave_layout ();
8585 /* If the target did not provide an XSAVE layout but the target
8586 description includes registers from the XSAVE extended region,
8587 use a fallback XSAVE layout. Specifically, this fallback layout
8588 is used when writing out a local core dump for a remote
8590 if (xsave_layout
.sizeof_xsave
== 0)
8592 = i387_fallback_xsave_layout (i386_xcr0_from_tdesc (info
.target_desc
));
8594 /* If there is already a candidate, use it. */
8595 for (arches
= gdbarch_list_lookup_by_info (arches
, &info
);
8597 arches
= gdbarch_list_lookup_by_info (arches
->next
, &info
))
8599 /* Check that the XSAVE layout of ARCHES matches the layout for
8600 the current target. */
8601 i386_gdbarch_tdep
*other_tdep
8602 = gdbarch_tdep
<i386_gdbarch_tdep
> (arches
->gdbarch
);
8604 if (other_tdep
->xsave_layout
== xsave_layout
)
8605 return arches
->gdbarch
;
8608 /* Allocate space for the new architecture. Assume i386 for now. */
8610 = gdbarch_alloc (&info
, gdbarch_tdep_up (new i386_gdbarch_tdep
));
8611 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (gdbarch
);
8613 /* General-purpose registers. */
8614 tdep
->gregset_reg_offset
= NULL
;
8615 tdep
->gregset_num_regs
= I386_NUM_GREGS
;
8616 tdep
->sizeof_gregset
= 0;
8618 /* Floating-point registers. */
8619 tdep
->sizeof_fpregset
= I387_SIZEOF_FSAVE
;
8620 tdep
->fpregset
= &i386_fpregset
;
8622 /* The default settings include the FPU registers, the MMX registers
8623 and the SSE registers. This can be overridden for a specific ABI
8624 by adjusting the members `st0_regnum', `mm0_regnum' and
8625 `num_xmm_regs' of `struct gdbarch_tdep', otherwise the registers
8626 will show up in the output of "info all-registers". */
8628 tdep
->st0_regnum
= I386_ST0_REGNUM
;
8630 /* I386_NUM_XREGS includes %mxcsr, so substract one. */
8631 tdep
->num_xmm_regs
= I386_NUM_XREGS
- 1;
8633 tdep
->jb_pc_offset
= -1;
8634 tdep
->struct_return
= pcc_struct_return
;
8635 tdep
->sigtramp_start
= 0;
8636 tdep
->sigtramp_end
= 0;
8637 tdep
->sigtramp_p
= i386_sigtramp_p
;
8638 tdep
->sigcontext_addr
= NULL
;
8639 tdep
->sc_reg_offset
= NULL
;
8640 tdep
->sc_pc_offset
= -1;
8641 tdep
->sc_sp_offset
= -1;
8643 tdep
->xsave_xcr0_offset
= -1;
8645 tdep
->record_regmap
= i386_record_regmap
;
8647 set_gdbarch_type_align (gdbarch
, i386_type_align
);
8649 /* The format used for `long double' on almost all i386 targets is
8650 the i387 extended floating-point format. In fact, of all targets
8651 in the GCC 2.95 tree, only OSF/1 does it different, and insists
8652 on having a `long double' that's not `long' at all. */
8653 set_gdbarch_long_double_format (gdbarch
, floatformats_i387_ext
);
8655 /* Although the i387 extended floating-point has only 80 significant
8656 bits, a `long double' actually takes up 96, probably to enforce
8658 set_gdbarch_long_double_bit (gdbarch
, 96);
8660 /* Support of bfloat16 format. */
8661 set_gdbarch_bfloat16_format (gdbarch
, floatformats_bfloat16
);
8663 /* Support for floating-point data type variants. */
8664 set_gdbarch_floatformat_for_type (gdbarch
, i386_floatformat_for_type
);
8666 /* Register numbers of various important registers. */
8667 set_gdbarch_sp_regnum (gdbarch
, I386_ESP_REGNUM
); /* %esp */
8668 set_gdbarch_pc_regnum (gdbarch
, I386_EIP_REGNUM
); /* %eip */
8669 set_gdbarch_ps_regnum (gdbarch
, I386_EFLAGS_REGNUM
); /* %eflags */
8670 set_gdbarch_fp0_regnum (gdbarch
, I386_ST0_REGNUM
); /* %st(0) */
8672 /* NOTE: kettenis/20040418: GCC does have two possible register
8673 numbering schemes on the i386: dbx and SVR4. These schemes
8674 differ in how they number %ebp, %esp, %eflags, and the
8675 floating-point registers, and are implemented by the arrays
8676 dbx_register_map[] and svr4_dbx_register_map in
8677 gcc/config/i386.c. GCC also defines a third numbering scheme in
8678 gcc/config/i386.c, which it designates as the "default" register
8679 map used in 64bit mode. This last register numbering scheme is
8680 implemented in dbx64_register_map, and is used for AMD64; see
8683 Currently, each GCC i386 target always uses the same register
8684 numbering scheme across all its supported debugging formats
8685 i.e. SDB (COFF), stabs and DWARF 2. This is because
8686 gcc/sdbout.c, gcc/dbxout.c and gcc/dwarf2out.c all use the
8687 DBX_REGISTER_NUMBER macro which is defined by each target's
8688 respective config header in a manner independent of the requested
8689 output debugging format.
8691 This does not match the arrangement below, which presumes that
8692 the SDB and stabs numbering schemes differ from the DWARF and
8693 DWARF 2 ones. The reason for this arrangement is that it is
8694 likely to get the numbering scheme for the target's
8695 default/native debug format right. For targets where GCC is the
8696 native compiler (FreeBSD, NetBSD, OpenBSD, GNU/Linux) or for
8697 targets where the native toolchain uses a different numbering
8698 scheme for a particular debug format (stabs-in-ELF on Solaris)
8699 the defaults below will have to be overridden, like
8700 i386_elf_init_abi() does. */
8702 /* Use the dbx register numbering scheme for stabs and COFF. */
8703 set_gdbarch_stab_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8704 set_gdbarch_sdb_reg_to_regnum (gdbarch
, i386_dbx_reg_to_regnum
);
8706 /* Use the SVR4 register numbering scheme for DWARF 2. */
8707 set_gdbarch_dwarf2_reg_to_regnum (gdbarch
, i386_svr4_dwarf_reg_to_regnum
);
8709 /* We don't set gdbarch_stab_reg_to_regnum, since ECOFF doesn't seem to
8710 be in use on any of the supported i386 targets. */
8712 set_gdbarch_print_float_info (gdbarch
, i387_print_float_info
);
8714 set_gdbarch_get_longjmp_target (gdbarch
, i386_get_longjmp_target
);
8716 /* Call dummy code. */
8717 set_gdbarch_call_dummy_location (gdbarch
, ON_STACK
);
8718 set_gdbarch_push_dummy_code (gdbarch
, i386_push_dummy_code
);
8719 set_gdbarch_push_dummy_call (gdbarch
, i386_push_dummy_call
);
8720 set_gdbarch_frame_align (gdbarch
, i386_frame_align
);
8722 set_gdbarch_convert_register_p (gdbarch
, i386_convert_register_p
);
8723 set_gdbarch_register_to_value (gdbarch
, i386_register_to_value
);
8724 set_gdbarch_value_to_register (gdbarch
, i386_value_to_register
);
8726 set_gdbarch_return_value_as_value (gdbarch
, i386_return_value
);
8728 set_gdbarch_skip_prologue (gdbarch
, i386_skip_prologue
);
8730 /* Stack grows downward. */
8731 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
8733 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, i386_breakpoint::kind_from_pc
);
8734 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, i386_breakpoint::bp_from_kind
);
8736 set_gdbarch_decr_pc_after_break (gdbarch
, 1);
8737 set_gdbarch_max_insn_length (gdbarch
, I386_MAX_INSN_LEN
);
8739 set_gdbarch_frame_args_skip (gdbarch
, 8);
8741 set_gdbarch_print_insn (gdbarch
, i386_print_insn
);
8743 set_gdbarch_dummy_id (gdbarch
, i386_dummy_id
);
8745 set_gdbarch_unwind_pc (gdbarch
, i386_unwind_pc
);
8747 /* Add the i386 register groups. */
8748 i386_add_reggroups (gdbarch
);
8749 tdep
->register_reggroup_p
= i386_register_reggroup_p
;
8751 /* Helper for function argument information. */
8752 set_gdbarch_fetch_pointer_argument (gdbarch
, i386_fetch_pointer_argument
);
8754 /* Hook the function epilogue frame unwinder. This unwinder is
8755 appended to the list first, so that it supersedes the DWARF
8756 unwinder in function epilogues (where the DWARF unwinder
8757 currently fails). */
8758 if (info
.bfd_arch_info
->bits_per_word
== 32)
8759 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_override_frame_unwind
);
8761 /* Hook in the DWARF CFI frame unwinder. This unwinder is appended
8762 to the list before the prologue-based unwinders, so that DWARF
8763 CFI info will be used if it is available. */
8764 dwarf2_append_unwinders (gdbarch
);
8766 if (info
.bfd_arch_info
->bits_per_word
== 32)
8767 frame_unwind_append_unwinder (gdbarch
, &i386_epilogue_frame_unwind
);
8769 frame_base_set_default (gdbarch
, &i386_frame_base
);
8771 /* Pseudo registers may be changed by amd64_init_abi. */
8772 set_gdbarch_pseudo_register_read_value (gdbarch
,
8773 i386_pseudo_register_read_value
);
8774 set_gdbarch_pseudo_register_write (gdbarch
, i386_pseudo_register_write
);
8775 set_gdbarch_ax_pseudo_register_collect (gdbarch
,
8776 i386_ax_pseudo_register_collect
);
8778 set_tdesc_pseudo_register_type (gdbarch
, i386_pseudo_register_type
);
8779 set_tdesc_pseudo_register_name (gdbarch
, i386_pseudo_register_name
);
8781 /* Override the normal target description method to make the AVX
8782 upper halves anonymous. */
8783 set_gdbarch_register_name (gdbarch
, i386_register_name
);
8785 /* Even though the default ABI only includes general-purpose registers,
8786 floating-point registers and the SSE registers, we have to leave a
8787 gap for the upper AVX, MPX and AVX512 registers. */
8788 set_gdbarch_num_regs (gdbarch
, I386_NUM_REGS
);
8790 set_gdbarch_gnu_triplet_regexp (gdbarch
, i386_gnu_triplet_regexp
);
8792 /* Get the x86 target description from INFO. */
8793 tdesc
= info
.target_desc
;
8794 if (! tdesc_has_registers (tdesc
))
8795 tdesc
= i386_target_description (X86_XSTATE_SSE_MASK
, false);
8796 tdep
->tdesc
= tdesc
;
8798 tdep
->num_core_regs
= I386_NUM_GREGS
+ I387_NUM_REGS
;
8799 tdep
->register_names
= i386_register_names
;
8801 /* No upper YMM registers. */
8802 tdep
->ymmh_register_names
= NULL
;
8803 tdep
->ymm0h_regnum
= -1;
8805 /* No upper ZMM registers. */
8806 tdep
->zmmh_register_names
= NULL
;
8807 tdep
->zmm0h_regnum
= -1;
8809 /* No high XMM registers. */
8810 tdep
->xmm_avx512_register_names
= NULL
;
8811 tdep
->xmm16_regnum
= -1;
8813 /* No upper YMM16-31 registers. */
8814 tdep
->ymm16h_register_names
= NULL
;
8815 tdep
->ymm16h_regnum
= -1;
8817 tdep
->num_byte_regs
= 8;
8818 tdep
->num_word_regs
= 8;
8819 tdep
->num_dword_regs
= 0;
8820 tdep
->num_mmx_regs
= 8;
8821 tdep
->num_ymm_regs
= 0;
8823 /* No MPX registers. */
8824 tdep
->bnd0r_regnum
= -1;
8825 tdep
->bndcfgu_regnum
= -1;
8827 /* No AVX512 registers. */
8828 tdep
->k0_regnum
= -1;
8829 tdep
->num_zmm_regs
= 0;
8830 tdep
->num_ymm_avx512_regs
= 0;
8831 tdep
->num_xmm_avx512_regs
= 0;
8833 /* No PKEYS registers */
8834 tdep
->pkru_regnum
= -1;
8835 tdep
->num_pkeys_regs
= 0;
8837 /* No segment base registers. */
8838 tdep
->fsbase_regnum
= -1;
8840 tdesc_arch_data_up tdesc_data
= tdesc_data_alloc ();
8842 set_gdbarch_relocate_instruction (gdbarch
, i386_relocate_instruction
);
8844 set_gdbarch_gen_return_address (gdbarch
, i386_gen_return_address
);
8846 set_gdbarch_insn_is_call (gdbarch
, i386_insn_is_call
);
8847 set_gdbarch_insn_is_ret (gdbarch
, i386_insn_is_ret
);
8848 set_gdbarch_insn_is_jump (gdbarch
, i386_insn_is_jump
);
8850 /* Hook in ABI-specific overrides, if they have been registered.
8851 Note: If INFO specifies a 64 bit arch, this is where we turn
8852 a 32-bit i386 into a 64-bit amd64. */
8853 info
.tdesc_data
= tdesc_data
.get ();
8854 gdbarch_init_osabi (info
, gdbarch
);
8856 if (!i386_validate_tdesc_p (tdep
, tdesc_data
.get ()))
8858 gdbarch_free (gdbarch
);
8861 tdep
->xsave_layout
= xsave_layout
;
8863 num_bnd_cooked
= (tdep
->bnd0r_regnum
> 0 ? I387_NUM_BND_REGS
: 0);
8865 /* Wire in pseudo registers. Number of pseudo registers may be
8867 set_gdbarch_num_pseudo_regs (gdbarch
, (tdep
->num_byte_regs
8868 + tdep
->num_word_regs
8869 + tdep
->num_dword_regs
8870 + tdep
->num_mmx_regs
8871 + tdep
->num_ymm_regs
8873 + tdep
->num_ymm_avx512_regs
8874 + tdep
->num_zmm_regs
));
8876 /* Target description may be changed. */
8877 tdesc
= tdep
->tdesc
;
8879 tdesc_use_registers (gdbarch
, tdesc
, std::move (tdesc_data
));
8881 /* Override gdbarch_register_reggroup_p set in tdesc_use_registers. */
8882 set_gdbarch_register_reggroup_p (gdbarch
, tdep
->register_reggroup_p
);
8884 /* Make %al the first pseudo-register. */
8885 tdep
->al_regnum
= gdbarch_num_regs (gdbarch
);
8886 tdep
->ax_regnum
= tdep
->al_regnum
+ tdep
->num_byte_regs
;
8888 ymm0_regnum
= tdep
->ax_regnum
+ tdep
->num_word_regs
;
8889 if (tdep
->num_dword_regs
)
8891 /* Support dword pseudo-register if it hasn't been disabled. */
8892 tdep
->eax_regnum
= ymm0_regnum
;
8893 ymm0_regnum
+= tdep
->num_dword_regs
;
8896 tdep
->eax_regnum
= -1;
8898 mm0_regnum
= ymm0_regnum
;
8899 if (tdep
->num_ymm_regs
)
8901 /* Support YMM pseudo-register if it is available. */
8902 tdep
->ymm0_regnum
= ymm0_regnum
;
8903 mm0_regnum
+= tdep
->num_ymm_regs
;
8906 tdep
->ymm0_regnum
= -1;
8908 if (tdep
->num_ymm_avx512_regs
)
8910 /* Support YMM16-31 pseudo registers if available. */
8911 tdep
->ymm16_regnum
= mm0_regnum
;
8912 mm0_regnum
+= tdep
->num_ymm_avx512_regs
;
8915 tdep
->ymm16_regnum
= -1;
8917 if (tdep
->num_zmm_regs
)
8919 /* Support ZMM pseudo-register if it is available. */
8920 tdep
->zmm0_regnum
= mm0_regnum
;
8921 mm0_regnum
+= tdep
->num_zmm_regs
;
8924 tdep
->zmm0_regnum
= -1;
8926 bnd0_regnum
= mm0_regnum
;
8927 if (tdep
->num_mmx_regs
!= 0)
8929 /* Support MMX pseudo-register if MMX hasn't been disabled. */
8930 tdep
->mm0_regnum
= mm0_regnum
;
8931 bnd0_regnum
+= tdep
->num_mmx_regs
;
8934 tdep
->mm0_regnum
= -1;
8936 if (tdep
->bnd0r_regnum
> 0)
8937 tdep
->bnd0_regnum
= bnd0_regnum
;
8939 tdep
-> bnd0_regnum
= -1;
8941 /* Hook in the legacy prologue-based unwinders last (fallback). */
8942 if (info
.bfd_arch_info
->bits_per_word
== 32)
8944 frame_unwind_append_unwinder (gdbarch
, &i386_stack_tramp_frame_unwind
);
8945 frame_unwind_append_unwinder (gdbarch
, &i386_sigtramp_frame_unwind
);
8946 frame_unwind_append_unwinder (gdbarch
, &i386_frame_unwind
);
8949 /* If we have a register mapping, enable the generic core file
8950 support, unless it has already been enabled. */
8951 if (tdep
->gregset_reg_offset
8952 && !gdbarch_iterate_over_regset_sections_p (gdbarch
))
8953 set_gdbarch_iterate_over_regset_sections
8954 (gdbarch
, i386_iterate_over_regset_sections
);
8956 set_gdbarch_fast_tracepoint_valid_at (gdbarch
,
8957 i386_fast_tracepoint_valid_at
);
8964 /* Return the target description for a specified XSAVE feature mask. */
8966 const struct target_desc
*
8967 i386_target_description (uint64_t xcr0
, bool segments
)
8969 static target_desc
*i386_tdescs \
8970 [2/*SSE*/][2/*AVX*/][2/*MPX*/][2/*AVX512*/][2/*PKRU*/][2/*segments*/] = {};
8971 target_desc
**tdesc
;
8973 tdesc
= &i386_tdescs
[(xcr0
& X86_XSTATE_SSE
) ? 1 : 0]
8974 [(xcr0
& X86_XSTATE_AVX
) ? 1 : 0]
8975 [(xcr0
& X86_XSTATE_MPX
) ? 1 : 0]
8976 [(xcr0
& X86_XSTATE_AVX512
) ? 1 : 0]
8977 [(xcr0
& X86_XSTATE_PKRU
) ? 1 : 0]
8981 *tdesc
= i386_create_target_description (xcr0
, false, segments
);
8986 #define MPX_BASE_MASK (~(ULONGEST) 0xfff)
8988 /* Find the bound directory base address. */
8990 static unsigned long
8991 i386_mpx_bd_base (void)
8994 enum register_status regstatus
;
8996 regcache
*rcache
= get_thread_regcache (inferior_thread ());
8997 gdbarch
*arch
= rcache
->arch ();
8998 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (arch
);
9000 regstatus
= regcache_raw_read_unsigned (rcache
, tdep
->bndcfgu_regnum
, &ret
);
9002 if (regstatus
!= REG_VALID
)
9003 error (_("BNDCFGU register invalid, read status %d."), regstatus
);
9005 return ret
& MPX_BASE_MASK
;
9009 i386_mpx_enabled (void)
9011 gdbarch
*arch
= get_current_arch ();
9012 i386_gdbarch_tdep
*tdep
= gdbarch_tdep
<i386_gdbarch_tdep
> (arch
);
9013 const struct target_desc
*tdesc
= tdep
->tdesc
;
9015 return (tdesc_find_feature (tdesc
, "org.gnu.gdb.i386.mpx") != NULL
);
9018 #define MPX_BD_MASK 0xfffffff00000ULL /* select bits [47:20] */
9019 #define MPX_BT_MASK 0x0000000ffff8 /* select bits [19:3] */
9020 #define MPX_BD_MASK_32 0xfffff000 /* select bits [31:12] */
9021 #define MPX_BT_MASK_32 0x00000ffc /* select bits [11:2] */
9023 /* Find the bound table entry given the pointer location and the base
9024 address of the table. */
9027 i386_mpx_get_bt_entry (CORE_ADDR ptr
, CORE_ADDR bd_base
)
9031 CORE_ADDR mpx_bd_mask
, bd_ptr_r_shift
, bd_ptr_l_shift
;
9032 CORE_ADDR bt_mask
, bt_select_r_shift
, bt_select_l_shift
;
9033 CORE_ADDR bd_entry_addr
;
9036 struct gdbarch
*gdbarch
= get_current_arch ();
9037 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
9040 if (gdbarch_ptr_bit (gdbarch
) == 64)
9042 mpx_bd_mask
= (CORE_ADDR
) MPX_BD_MASK
;
9043 bd_ptr_r_shift
= 20;
9045 bt_select_r_shift
= 3;
9046 bt_select_l_shift
= 5;
9047 bt_mask
= (CORE_ADDR
) MPX_BT_MASK
;
9049 if ( sizeof (CORE_ADDR
) == 4)
9050 error (_("bound table examination not supported\
9051 for 64-bit process with 32-bit GDB"));
9055 mpx_bd_mask
= MPX_BD_MASK_32
;
9056 bd_ptr_r_shift
= 12;
9058 bt_select_r_shift
= 2;
9059 bt_select_l_shift
= 4;
9060 bt_mask
= MPX_BT_MASK_32
;
9063 offset1
= ((ptr
& mpx_bd_mask
) >> bd_ptr_r_shift
) << bd_ptr_l_shift
;
9064 bd_entry_addr
= bd_base
+ offset1
;
9065 bd_entry
= read_memory_typed_address (bd_entry_addr
, data_ptr_type
);
9067 if ((bd_entry
& 0x1) == 0)
9068 error (_("Invalid bounds directory entry at %s."),
9069 paddress (get_current_arch (), bd_entry_addr
));
9071 /* Clearing status bit. */
9073 bt_addr
= bd_entry
& ~bt_select_r_shift
;
9074 offset2
= ((ptr
& bt_mask
) >> bt_select_r_shift
) << bt_select_l_shift
;
9076 return bt_addr
+ offset2
;
9079 /* Print routine for the mpx bounds. */
9082 i386_mpx_print_bounds (const CORE_ADDR bt_entry
[4])
9084 struct ui_out
*uiout
= current_uiout
;
9086 struct gdbarch
*gdbarch
= get_current_arch ();
9087 CORE_ADDR onecompl
= ~((CORE_ADDR
) 0);
9088 int bounds_in_map
= ((~bt_entry
[1] == 0 && bt_entry
[0] == onecompl
) ? 1 : 0);
9090 if (bounds_in_map
== 1)
9092 uiout
->text ("Null bounds on map:");
9093 uiout
->text (" pointer value = ");
9094 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
9100 uiout
->text ("{lbound = ");
9101 uiout
->field_core_addr ("lower-bound", gdbarch
, bt_entry
[0]);
9102 uiout
->text (", ubound = ");
9104 /* The upper bound is stored in 1's complement. */
9105 uiout
->field_core_addr ("upper-bound", gdbarch
, ~bt_entry
[1]);
9106 uiout
->text ("}: pointer value = ");
9107 uiout
->field_core_addr ("pointer-value", gdbarch
, bt_entry
[2]);
9109 if (gdbarch_ptr_bit (gdbarch
) == 64)
9110 size
= ( (~(int64_t) bt_entry
[1]) - (int64_t) bt_entry
[0]);
9112 size
= ( ~((int32_t) bt_entry
[1]) - (int32_t) bt_entry
[0]);
9114 /* In case the bounds are 0x0 and 0xffff... the difference will be -1.
9115 -1 represents in this sense full memory access, and there is no need
9118 size
= (size
> -1 ? size
+ 1 : size
);
9119 uiout
->text (", size = ");
9120 uiout
->field_string ("size", plongest (size
));
9122 uiout
->text (", metadata = ");
9123 uiout
->field_core_addr ("metadata", gdbarch
, bt_entry
[3]);
9128 /* Implement the command "show mpx bound". */
9131 i386_mpx_info_bounds (const char *args
, int from_tty
)
9133 CORE_ADDR bd_base
= 0;
9135 CORE_ADDR bt_entry_addr
= 0;
9136 CORE_ADDR bt_entry
[4];
9138 struct gdbarch
*gdbarch
= get_current_arch ();
9139 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
9141 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
9142 || !i386_mpx_enabled ())
9144 gdb_printf (_("Intel Memory Protection Extensions not "
9145 "supported on this target.\n"));
9151 gdb_printf (_("Address of pointer variable expected.\n"));
9155 addr
= parse_and_eval_address (args
);
9157 bd_base
= i386_mpx_bd_base ();
9158 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
9160 memset (bt_entry
, 0, sizeof (bt_entry
));
9162 for (i
= 0; i
< 4; i
++)
9163 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
9164 + i
* data_ptr_type
->length (),
9167 i386_mpx_print_bounds (bt_entry
);
9170 /* Implement the command "set mpx bound". */
9173 i386_mpx_set_bounds (const char *args
, int from_tty
)
9175 CORE_ADDR bd_base
= 0;
9176 CORE_ADDR addr
, lower
, upper
;
9177 CORE_ADDR bt_entry_addr
= 0;
9178 CORE_ADDR bt_entry
[2];
9179 const char *input
= args
;
9181 struct gdbarch
*gdbarch
= get_current_arch ();
9182 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
9183 struct type
*data_ptr_type
= builtin_type (gdbarch
)->builtin_data_ptr
;
9185 if (gdbarch_bfd_arch_info (gdbarch
)->arch
!= bfd_arch_i386
9186 || !i386_mpx_enabled ())
9187 error (_("Intel Memory Protection Extensions not supported\
9191 error (_("Pointer value expected."));
9193 addr
= value_as_address (parse_to_comma_and_eval (&input
));
9195 if (input
[0] == ',')
9197 if (input
[0] == '\0')
9198 error (_("wrong number of arguments: missing lower and upper bound."));
9199 lower
= value_as_address (parse_to_comma_and_eval (&input
));
9201 if (input
[0] == ',')
9203 if (input
[0] == '\0')
9204 error (_("Wrong number of arguments; Missing upper bound."));
9205 upper
= value_as_address (parse_to_comma_and_eval (&input
));
9207 bd_base
= i386_mpx_bd_base ();
9208 bt_entry_addr
= i386_mpx_get_bt_entry (addr
, bd_base
);
9209 for (i
= 0; i
< 2; i
++)
9210 bt_entry
[i
] = read_memory_typed_address (bt_entry_addr
9211 + i
* data_ptr_type
->length (),
9213 bt_entry
[0] = (uint64_t) lower
;
9214 bt_entry
[1] = ~(uint64_t) upper
;
9216 for (i
= 0; i
< 2; i
++)
9217 write_memory_unsigned_integer (bt_entry_addr
9218 + i
* data_ptr_type
->length (),
9219 data_ptr_type
->length (), byte_order
,
9223 static struct cmd_list_element
*mpx_set_cmdlist
, *mpx_show_cmdlist
;
9225 void _initialize_i386_tdep ();
9227 _initialize_i386_tdep ()
9229 gdbarch_register (bfd_arch_i386
, i386_gdbarch_init
);
9231 /* Add the variable that controls the disassembly flavor. */
9232 add_setshow_enum_cmd ("disassembly-flavor", no_class
, valid_flavors
,
9233 &disassembly_flavor
, _("\
9234 Set the disassembly flavor."), _("\
9235 Show the disassembly flavor."), _("\
9236 The valid values are \"att\" and \"intel\", and the default value is \"att\"."),
9238 NULL
, /* FIXME: i18n: */
9239 &setlist
, &showlist
);
9241 /* Add the variable that controls the convention for returning
9243 add_setshow_enum_cmd ("struct-convention", no_class
, valid_conventions
,
9244 &struct_convention
, _("\
9245 Set the convention for returning small structs."), _("\
9246 Show the convention for returning small structs."), _("\
9247 Valid values are \"default\", \"pcc\" and \"reg\", and the default value\n\
9250 NULL
, /* FIXME: i18n: */
9251 &setlist
, &showlist
);
9253 /* Add "mpx" prefix for the set and show commands. */
9255 add_setshow_prefix_cmd
9256 ("mpx", class_support
,
9257 _("Set Intel Memory Protection Extensions specific variables."),
9258 _("Show Intel Memory Protection Extensions specific variables."),
9259 &mpx_set_cmdlist
, &mpx_show_cmdlist
, &setlist
, &showlist
);
9261 /* Add "bound" command for the show mpx commands list. */
9263 add_cmd ("bound", no_class
, i386_mpx_info_bounds
,
9264 "Show the memory bounds for a given array/pointer storage\
9265 in the bound table.",
9268 /* Add "bound" command for the set mpx commands list. */
9270 add_cmd ("bound", no_class
, i386_mpx_set_bounds
,
9271 "Set the memory bounds for a given array/pointer storage\
9272 in the bound table.",
9275 gdbarch_register_osabi (bfd_arch_i386
, 0, GDB_OSABI_SVR4
,
9276 i386_svr4_init_abi
);
9278 /* Initialize the i386-specific register groups. */
9279 i386_init_reggroups ();
9281 /* Tell remote stub that we support XML target description. */
9282 register_remote_support_xml ("i386");