opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2023 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep this sorted alphanumerically and synced with the fields array
  29    in aarch64-opc.c.  */
  30 enum aarch64_field_kind
  31 {
  32   FLD_NIL,
  33   FLD_CRm,
  34   FLD_CRm_dsb_nxs,
  35   FLD_CRn,
  36   FLD_CSSC_imm8,
  37   FLD_H,
  38   FLD_L,
  39   FLD_M,
  40   FLD_N,
  41   FLD_Q,
  42   FLD_Ra,
  43   FLD_Rd,
  44   FLD_Rm,
  45   FLD_Rn,
  46   FLD_Rs,
  47   FLD_Rt,
  48   FLD_Rt2,
  49   FLD_S,
  50   FLD_SM3_imm2,
  51   FLD_SME_Pdx2,
  52   FLD_SME_Pm,
  53   FLD_SME_PNd3,
  54   FLD_SME_PNn3,
  55   FLD_SME_Q,
  56   FLD_SME_Rm,
  57   FLD_SME_Rv,
  58   FLD_SME_V,
  59   FLD_SME_VL_10,
  60   FLD_SME_VL_13,
  61   FLD_SME_ZAda_2b,
  62   FLD_SME_ZAda_3b,
  63   FLD_SME_Zdn2,
  64   FLD_SME_Zdn4,
  65   FLD_SME_Zm,
  66   FLD_SME_Zm2,
  67   FLD_SME_Zm4,
  68   FLD_SME_Zn2,
  69   FLD_SME_Zn4,
  70   FLD_SME_ZtT,
  71   FLD_SME_Zt3,
  72   FLD_SME_Zt2,
  73   FLD_SME_i1,
  74   FLD_SME_size_12,
  75   FLD_SME_size_22,
  76   FLD_SME_sz_23,
  77   FLD_SME_tszh,
  78   FLD_SME_tszl,
  79   FLD_SME_zero_mask,
  80   FLD_SVE_M_4,
  81   FLD_SVE_M_14,
  82   FLD_SVE_M_16,
  83   FLD_SVE_N,
  84   FLD_SVE_Pd,
  85   FLD_SVE_Pg3,
  86   FLD_SVE_Pg4_5,
  87   FLD_SVE_Pg4_10,
  88   FLD_SVE_Pg4_16,
  89   FLD_SVE_Pm,
  90   FLD_SVE_Pn,
  91   FLD_SVE_Pt,
  92   FLD_SVE_Rm,
  93   FLD_SVE_Rn,
  94   FLD_SVE_Vd,
  95   FLD_SVE_Vm,
  96   FLD_SVE_Vn,
  97   FLD_SVE_Za_5,
  98   FLD_SVE_Za_16,
  99   FLD_SVE_Zd,
 100   FLD_SVE_Zm_5,
 101   FLD_SVE_Zm_16,
 102   FLD_SVE_Zn,
 103   FLD_SVE_Zt,
 104   FLD_SVE_i1,
 105   FLD_SVE_i2h,
 106   FLD_SVE_i3h,
 107   FLD_SVE_i3h2,
 108   FLD_SVE_i3l,
 109   FLD_SVE_imm3,
 110   FLD_SVE_imm4,
 111   FLD_SVE_imm5,
 112   FLD_SVE_imm5b,
 113   FLD_SVE_imm6,
 114   FLD_SVE_imm7,
 115   FLD_SVE_imm8,
 116   FLD_SVE_imm9,
 117   FLD_SVE_immr,
 118   FLD_SVE_imms,
 119   FLD_SVE_msz,
 120   FLD_SVE_pattern,
 121   FLD_SVE_prfop,
 122   FLD_SVE_rot1,
 123   FLD_SVE_rot2,
 124   FLD_SVE_rot3,
 125   FLD_SVE_size,
 126   FLD_SVE_sz,
 127   FLD_SVE_sz2,
 128   FLD_SVE_tsz,
 129   FLD_SVE_tszh,
 130   FLD_SVE_tszl_8,
 131   FLD_SVE_tszl_19,
 132   FLD_SVE_xs_14,
 133   FLD_SVE_xs_22,
 134   FLD_S_imm10,
 135   FLD_abc,
 136   FLD_asisdlso_opcode,
 137   FLD_b40,
 138   FLD_b5,
 139   FLD_cmode,
 140   FLD_cond,
 141   FLD_cond2,
 142   FLD_defgh,
 143   FLD_hw,
 144   FLD_imm1_0,
 145   FLD_imm1_2,
 146   FLD_imm1_8,
 147   FLD_imm1_10,
 148   FLD_imm1_15,
 149   FLD_imm1_16,
 150   FLD_imm2_0,
 151   FLD_imm2_1,
 152   FLD_imm2_8,
 153   FLD_imm2_10,
 154   FLD_imm2_12,
 155   FLD_imm2_15,
 156   FLD_imm2_16,
 157   FLD_imm2_19,
 158   FLD_imm3_0,
 159   FLD_imm3_5,
 160   FLD_imm3_10,
 161   FLD_imm3_12,
 162   FLD_imm3_14,
 163   FLD_imm3_15,
 164   FLD_imm4_0,
 165   FLD_imm4_5,
 166   FLD_imm4_10,
 167   FLD_imm4_11,
 168   FLD_imm4_14,
 169   FLD_imm5,
 170   FLD_imm6_10,
 171   FLD_imm6_15,
 172   FLD_imm7,
 173   FLD_imm8,
 174   FLD_imm9,
 175   FLD_imm12,
 176   FLD_imm14,
 177   FLD_imm16_0,
 178   FLD_imm16_5,
 179   FLD_imm19,
 180   FLD_imm26,
 181   FLD_immb,
 182   FLD_immh,
 183   FLD_immhi,
 184   FLD_immlo,
 185   FLD_immr,
 186   FLD_imms,
 187   FLD_index,
 188   FLD_index2,
 189   FLD_ldst_size,
 190   FLD_len,
 191   FLD_lse_sz,
 192   FLD_nzcv,
 193   FLD_op,
 194   FLD_op0,
 195   FLD_op1,
 196   FLD_op2,
 197   FLD_opc,
 198   FLD_opc1,
 199   FLD_opcode,
 200   FLD_option,
 201   FLD_rotate1,
 202   FLD_rotate2,
 203   FLD_rotate3,
 204   FLD_scale,
 205   FLD_sf,
 206   FLD_shift,
 207   FLD_size,
 208   FLD_sz,
 209   FLD_type,
 210   FLD_vldst_size,
 211 };
 212
 213 /* Field description.  */
 214 struct aarch64_field
 215 {
 216   int lsb;
 217   int width;
 218 };
 219
 220 typedef struct aarch64_field aarch64_field;
 221
 222 extern const aarch64_field fields[];
 223 \f
 224 /* Operand description.  */
 225
 226 struct aarch64_operand
 227 {
 228   enum aarch64_operand_class op_class;
 229
 230   /* Name of the operand code; used mainly for the purpose of internal
 231      debugging.  */
 232   const char *name;
 233
 234   unsigned int flags;
 235
 236   /* The associated instruction bit-fields; no operand has more than 4
 237      bit-fields */
 238   enum aarch64_field_kind fields[5];
 239
 240   /* Brief description */
 241   const char *desc;
 242 };
 243
 244 typedef struct aarch64_operand aarch64_operand;
 245
 246 extern const aarch64_operand aarch64_operands[];
 247
 248 enum err_type
 249 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 250                     bool, aarch64_operand_error *, aarch64_instr_sequence*);
 251
 252 /* Operand flags.  */
 253
 254 #define OPD_F_HAS_INSERTER      0x00000001
 255 #define OPD_F_HAS_EXTRACTOR     0x00000002
 256 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 257 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 258                                                    value by 2 to get the value
 259                                                    of an immediate operand.  */
 260 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 261 #define OPD_F_OD_MASK           0x000001e0      /* Operand-dependent data.  */
 262 #define OPD_F_OD_LSB            5
 263 #define OPD_F_NO_ZR             0x00000200      /* ZR index not allowed.  */
 264 #define OPD_F_SHIFT_BY_3        0x00000400      /* Need to left shift the field
 265                                                    value by 3 to get the value
 266                                                    of an immediate operand.  */
 267 #define OPD_F_SHIFT_BY_4        0x00000800      /* Need to left shift the field
 268                                                    value by 4 to get the value
 269                                                    of an immediate operand.  */
 270
 271
 272 /* Register flags.  */
 273
 274 #undef F_DEPRECATED
 275 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 276
 277 #undef F_ARCHEXT
 278 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 279
 280 #undef F_HASXT
 281 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 282                                      operand.  */
 283
 284 #undef F_REG_READ
 285 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 286                                      out of.  */
 287
 288 #undef F_REG_WRITE
 289 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 290                                      read from.  */
 291
 292 #undef F_REG_IN_CRM
 293 #define F_REG_IN_CRM    (1 << 5)  /* Register extra encoding in CRm.  */
 294
 295 #undef F_REG_ALIAS
 296 #define F_REG_ALIAS     (1 << 6)  /* Register name aliases another.  */
 297
 298 /* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
 299    Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
 300    In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below
 301    macros to encode and decode CRm encoding.
 302 */
 303 #define PSTATE_ENCODE_CRM(val) (val << 6)
 304 #define PSTATE_DECODE_CRM(flags) ((flags >> 6) & 0x0f)
 305
 306 #undef F_IMM_IN_CRM
 307 #define F_IMM_IN_CRM    (1 << 10)  /* Immediate extra encoding in CRm.  */
 308
 309 /* Also CRm may contain, in addition to <pstatefield> immediate.
 310    E.g. CRm[0] <imm1> at bit 0 for SME. Use below macros to encode and decode
 311    immediate mask.
 312 */
 313 #define PSTATE_ENCODE_CRM_IMM(mask) (mask << 11)
 314 #define PSTATE_DECODE_CRM_IMM(mask) ((mask >> 11) & 0x0f)
 315
 316 /* Helper macro to ENCODE CRm and its immediate.  */
 317 #define PSTATE_ENCODE_CRM_AND_IMM(CVAL,IMASK) \
 318         (F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \
 319          | F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK))
 320
 321 /* Bits [15, 18] contain the maximum value for an immediate MSR.  */
 322 #define F_REG_MAX_VALUE(X) ((X) << 15)
 323 #define F_GET_REG_MAX_VALUE(X) (((X) >> 15) & 0x0f)
 324
 325 /* HINT operand flags.  */
 326 #define HINT_OPD_F_NOPRINT      (1 << 0)  /* Should not be printed.  */
 327
 328 /* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
 329 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
 330 #define HINT_FLAG(val) (val >> 8)
 331 #define HINT_VAL(val) (val & 0xff)
 332
 333 static inline bool
 334 operand_has_inserter (const aarch64_operand *operand)
 335 {
 336   return (operand->flags & OPD_F_HAS_INSERTER) != 0;
 337 }
 338
 339 static inline bool
 340 operand_has_extractor (const aarch64_operand *operand)
 341 {
 342   return (operand->flags & OPD_F_HAS_EXTRACTOR) != 0;
 343 }
 344
 345 static inline bool
 346 operand_need_sign_extension (const aarch64_operand *operand)
 347 {
 348   return (operand->flags & OPD_F_SEXT) != 0;
 349 }
 350
 351 static inline bool
 352 operand_need_shift_by_two (const aarch64_operand *operand)
 353 {
 354   return (operand->flags & OPD_F_SHIFT_BY_2) != 0;
 355 }
 356
 357 static inline bool
 358 operand_need_shift_by_three (const aarch64_operand *operand)
 359 {
 360   return (operand->flags & OPD_F_SHIFT_BY_3) != 0;
 361 }
 362
 363 static inline bool
 364 operand_need_shift_by_four (const aarch64_operand *operand)
 365 {
 366   return (operand->flags & OPD_F_SHIFT_BY_4) != 0;
 367 }
 368
 369 static inline bool
 370 operand_maybe_stack_pointer (const aarch64_operand *operand)
 371 {
 372   return (operand->flags & OPD_F_MAYBE_SP) != 0;
 373 }
 374
 375 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 376 static inline unsigned int
 377 get_operand_specific_data (const aarch64_operand *operand)
 378 {
 379   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 380 }
 381
 382 /* Return the width of field number N of operand *OPERAND.  */
 383 static inline unsigned
 384 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 385 {
 386   assert (operand->fields[n] != FLD_NIL);
 387   return fields[operand->fields[n]].width;
 388 }
 389
 390 /* Return the total width of the operand *OPERAND.  */
 391 static inline unsigned
 392 get_operand_fields_width (const aarch64_operand *operand)
 393 {
 394   int i = 0;
 395   unsigned width = 0;
 396   while (operand->fields[i] != FLD_NIL)
 397     width += fields[operand->fields[i++]].width;
 398   assert (width > 0 && width < 32);
 399   return width;
 400 }
 401
 402 static inline const aarch64_operand *
 403 get_operand_from_code (enum aarch64_opnd code)
 404 {
 405   return aarch64_operands + code;
 406 }
 407 \f
 408 /* Operand qualifier and operand constraint checking.  */
 409
 410 int aarch64_match_operands_constraint (aarch64_inst *,
 411                                        aarch64_operand_error *);
 412
 413 /* Operand qualifier related functions.  */
 414 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 415 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 416 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 417 int aarch64_find_best_match (const aarch64_inst *,
 418                              const aarch64_opnd_qualifier_seq_t *,
 419                              int, aarch64_opnd_qualifier_t *, int *);
 420
 421 static inline void
 422 reset_operand_qualifier (aarch64_inst *inst, int idx)
 423 {
 424   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 425   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 426 }
 427 \f
 428 /* Inline functions operating on instruction bit-field(s).  */
 429
 430 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 431
 432 static inline aarch64_insn
 433 gen_mask (int width)
 434 {
 435   return ((aarch64_insn) 1 << width) - 1;
 436 }
 437
 438 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 439 static inline int
 440 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 441 {
 442   const aarch64_field *field = &fields[kind];
 443   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 444     return 0;
 445   ret->lsb = field->lsb + lsb_rel;
 446   ret->width = width;
 447   return 1;
 448 }
 449
 450 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 451    of the opcode.  */
 452
 453 static inline void
 454 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 455                 aarch64_insn value, aarch64_insn mask)
 456 {
 457   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 458           && field->lsb + field->width <= 32);
 459   value &= gen_mask (field->width);
 460   value <<= field->lsb;
 461   /* In some opcodes, field can be part of the base opcode, e.g. the size
 462      field in FADD.  The following helps avoid corrupt the base opcode.  */
 463   value &= ~mask;
 464   *code |= value;
 465 }
 466
 467 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 468    mask of the opcode.  */
 469
 470 static inline aarch64_insn
 471 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 472                  aarch64_insn mask)
 473 {
 474   aarch64_insn value;
 475   /* Clear any bit that is a part of the base opcode.  */
 476   code &= ~mask;
 477   value = (code >> field->lsb) & gen_mask (field->width);
 478   return value;
 479 }
 480
 481 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 482    of the opcode.  */
 483
 484 static inline void
 485 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 486               aarch64_insn value, aarch64_insn mask)
 487 {
 488   insert_field_2 (&fields[kind], code, value, mask);
 489 }
 490
 491 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 492    base mask of the opcode.  */
 493
 494 static inline aarch64_insn
 495 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 496                aarch64_insn mask)
 497 {
 498   return extract_field_2 (&fields[kind], code, mask);
 499 }
 500
 501 extern aarch64_insn
 502 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 503 \f
 504 /* Inline functions selecting operand to do the encoding/decoding for a
 505    certain instruction bit-field.  */
 506
 507 /* Select the operand to do the encoding/decoding of the 'sf' field.
 508    The heuristic-based rule is that the result operand is respected more.  */
 509
 510 static inline int
 511 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 512 {
 513   int idx = -1;
 514   if (aarch64_get_operand_class (opcode->operands[0])
 515       == AARCH64_OPND_CLASS_INT_REG)
 516     /* normal case.  */
 517     idx = 0;
 518   else if (aarch64_get_operand_class (opcode->operands[1])
 519            == AARCH64_OPND_CLASS_INT_REG)
 520     /* e.g. float2fix.  */
 521     idx = 1;
 522   else
 523     { assert (0); abort (); }
 524   return idx;
 525 }
 526
 527 /* Select the operand to do the encoding/decoding of the 'type' field in
 528    the floating-point instructions.
 529    The heuristic-based rule is that the source operand is respected more.  */
 530
 531 static inline int
 532 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 533 {
 534   int idx;
 535   if (aarch64_get_operand_class (opcode->operands[1])
 536       == AARCH64_OPND_CLASS_FP_REG)
 537     /* normal case.  */
 538     idx = 1;
 539   else if (aarch64_get_operand_class (opcode->operands[0])
 540            == AARCH64_OPND_CLASS_FP_REG)
 541     /* e.g. float2fix.  */
 542     idx = 0;
 543   else
 544     { assert (0); abort (); }
 545   return idx;
 546 }
 547
 548 /* Select the operand to do the encoding/decoding of the 'size' field in
 549    the AdvSIMD scalar instructions.
 550    The heuristic-based rule is that the destination operand is respected
 551    more.  */
 552
 553 static inline int
 554 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 555 {
 556   int src_size = 0, dst_size = 0;
 557   if (aarch64_get_operand_class (opcode->operands[0])
 558       == AARCH64_OPND_CLASS_SISD_REG)
 559     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 560   if (aarch64_get_operand_class (opcode->operands[1])
 561       == AARCH64_OPND_CLASS_SISD_REG)
 562     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 563   if (src_size == dst_size && src_size == 0)
 564     { assert (0); abort (); }
 565   /* When the result is not a sisd register or it is a long operantion.  */
 566   if (dst_size == 0 || dst_size == src_size << 1)
 567     return 1;
 568   else
 569     return 0;
 570 }
 571
 572 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 573    the AdvSIMD instructions.  */
 574
 575 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 576 \f
 577 /* Miscellaneous.  */
 578
 579 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 580 enum aarch64_modifier_kind
 581 aarch64_get_operand_modifier_from_value (aarch64_insn, bool);
 582
 583
 584 bool aarch64_wide_constant_p (uint64_t, int, unsigned int *);
 585 bool aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 586 int aarch64_shrink_expanded_imm8 (uint64_t);
 587
 588 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 589 static inline void
 590 copy_operand_info (aarch64_inst *inst, int dst, int src)
 591 {
 592   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 593           && src < AARCH64_MAX_OPND_NUM);
 594   memcpy (&inst->operands[dst], &inst->operands[src],
 595           sizeof (aarch64_opnd_info));
 596   inst->operands[dst].idx = dst;
 597 }
 598
 599 /* A primitive log caculator.  */
 600
 601 static inline unsigned int
 602 get_logsz (unsigned int size)
 603 {
 604   const unsigned char ls[16] =
 605     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 606   if (size > 16)
 607     {
 608       assert (0);
 609       return -1;
 610     }
 611   assert (ls[size - 1] != (unsigned char)-1);
 612   return ls[size - 1];
 613 }
 614
 615 #endif /* OPCODES_AARCH64_OPC_H */