1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
2 Copyright (C) 2012-2023 Free Software Foundation, Inc.
3 Contributed by ARM Ltd.
5 This file is part of the GNU opcodes library.
7 This library is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3, or (at your option)
12 It is distributed in the hope that it will be useful, but WITHOUT
13 ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
14 or FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public
15 License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program; see the file COPYING3. If not,
19 see <http://www.gnu.org/licenses/>. */
21 #ifndef OPCODES_AARCH64_OPC_H
22 #define OPCODES_AARCH64_OPC_H
25 #include "opcode/aarch64.h"
27 /* Instruction fields.
28 Keep this sorted alphanumerically and synced with the fields array
30 enum aarch64_field_kind
215 /* Field description. */
222 typedef struct aarch64_field aarch64_field
;
224 extern const aarch64_field fields
[];
226 /* Operand description. */
228 struct aarch64_operand
230 enum aarch64_operand_class op_class
;
232 /* Name of the operand code; used mainly for the purpose of internal
238 /* The associated instruction bit-fields; no operand has more than 4
240 enum aarch64_field_kind fields
[5];
242 /* Brief description */
246 typedef struct aarch64_operand aarch64_operand
;
248 extern const aarch64_operand aarch64_operands
[];
251 verify_constraints (const struct aarch64_inst
*, const aarch64_insn
, bfd_vma
,
252 bool, aarch64_operand_error
*, aarch64_instr_sequence
*);
256 #define OPD_F_HAS_INSERTER 0x00000001
257 #define OPD_F_HAS_EXTRACTOR 0x00000002
258 #define OPD_F_SEXT 0x00000004 /* Require sign-extension. */
259 #define OPD_F_SHIFT_BY_2 0x00000008 /* Need to left shift the field
260 value by 2 to get the value
261 of an immediate operand. */
262 #define OPD_F_MAYBE_SP 0x00000010 /* May potentially be SP. */
263 #define OPD_F_OD_MASK 0x000001e0 /* Operand-dependent data. */
264 #define OPD_F_OD_LSB 5
265 #define OPD_F_NO_ZR 0x00000200 /* ZR index not allowed. */
266 #define OPD_F_SHIFT_BY_3 0x00000400 /* Need to left shift the field
267 value by 3 to get the value
268 of an immediate operand. */
269 #define OPD_F_SHIFT_BY_4 0x00000800 /* Need to left shift the field
270 value by 4 to get the value
271 of an immediate operand. */
274 /* Register flags. */
277 #define F_DEPRECATED (1 << 0) /* Deprecated system register. */
280 #define F_ARCHEXT (1 << 1) /* Architecture dependent system register. */
283 #define F_HASXT (1 << 2) /* System instruction register <Xt>
287 #define F_REG_READ (1 << 3) /* Register can only be used to read values
291 #define F_REG_WRITE (1 << 4) /* Register can only be written to but not
295 #define F_REG_IN_CRM (1 << 5) /* Register extra encoding in CRm. */
298 #define F_REG_ALIAS (1 << 6) /* Register name aliases another. */
301 #define F_REG_128 (1 << 7) /* System regsister implementable as 128-bit wide. */
303 /* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
304 Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
305 In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below
306 macros to encode and decode CRm encoding.
308 #define PSTATE_ENCODE_CRM(val) (val << 6)
309 #define PSTATE_DECODE_CRM(flags) ((flags >> 6) & 0x0f)
312 #define F_IMM_IN_CRM (1 << 10) /* Immediate extra encoding in CRm. */
314 /* Also CRm may contain, in addition to <pstatefield> immediate.
315 E.g. CRm[0] <imm1> at bit 0 for SME. Use below macros to encode and decode
318 #define PSTATE_ENCODE_CRM_IMM(mask) (mask << 11)
319 #define PSTATE_DECODE_CRM_IMM(mask) ((mask >> 11) & 0x0f)
321 /* Helper macro to ENCODE CRm and its immediate. */
322 #define PSTATE_ENCODE_CRM_AND_IMM(CVAL,IMASK) \
323 (F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \
324 | F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK))
326 /* Bits [15, 18] contain the maximum value for an immediate MSR. */
327 #define F_REG_MAX_VALUE(X) ((X) << 15)
328 #define F_GET_REG_MAX_VALUE(X) (((X) >> 15) & 0x0f)
330 /* HINT operand flags. */
331 #define HINT_OPD_F_NOPRINT (1 << 0) /* Should not be printed. */
333 /* Encode 7-bit HINT #imm in the lower 8 bits. Use higher bits for flags. */
334 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
335 #define HINT_FLAG(val) (val >> 8)
336 #define HINT_VAL(val) (val & 0xff)
339 operand_has_inserter (const aarch64_operand
*operand
)
341 return (operand
->flags
& OPD_F_HAS_INSERTER
) != 0;
345 operand_has_extractor (const aarch64_operand
*operand
)
347 return (operand
->flags
& OPD_F_HAS_EXTRACTOR
) != 0;
351 operand_need_sign_extension (const aarch64_operand
*operand
)
353 return (operand
->flags
& OPD_F_SEXT
) != 0;
357 operand_need_shift_by_two (const aarch64_operand
*operand
)
359 return (operand
->flags
& OPD_F_SHIFT_BY_2
) != 0;
363 operand_need_shift_by_three (const aarch64_operand
*operand
)
365 return (operand
->flags
& OPD_F_SHIFT_BY_3
) != 0;
369 operand_need_shift_by_four (const aarch64_operand
*operand
)
371 return (operand
->flags
& OPD_F_SHIFT_BY_4
) != 0;
375 operand_maybe_stack_pointer (const aarch64_operand
*operand
)
377 return (operand
->flags
& OPD_F_MAYBE_SP
) != 0;
380 /* Return the value of the operand-specific data field (OPD_F_OD_MASK). */
381 static inline unsigned int
382 get_operand_specific_data (const aarch64_operand
*operand
)
384 return (operand
->flags
& OPD_F_OD_MASK
) >> OPD_F_OD_LSB
;
387 /* Return the width of field number N of operand *OPERAND. */
388 static inline unsigned
389 get_operand_field_width (const aarch64_operand
*operand
, unsigned n
)
391 assert (operand
->fields
[n
] != FLD_NIL
);
392 return fields
[operand
->fields
[n
]].width
;
395 /* Return the total width of the operand *OPERAND. */
396 static inline unsigned
397 get_operand_fields_width (const aarch64_operand
*operand
)
401 while (operand
->fields
[i
] != FLD_NIL
)
402 width
+= fields
[operand
->fields
[i
++]].width
;
403 assert (width
> 0 && width
< 32);
407 static inline const aarch64_operand
*
408 get_operand_from_code (enum aarch64_opnd code
)
410 return aarch64_operands
+ code
;
413 /* Operand qualifier and operand constraint checking. */
415 int aarch64_match_operands_constraint (aarch64_inst
*,
416 aarch64_operand_error
*);
418 /* Operand qualifier related functions. */
419 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t
);
420 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t
);
421 aarch64_insn
aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t
);
422 int aarch64_find_best_match (const aarch64_inst
*,
423 const aarch64_opnd_qualifier_seq_t
*,
424 int, aarch64_opnd_qualifier_t
*, int *);
427 reset_operand_qualifier (aarch64_inst
*inst
, int idx
)
429 assert (idx
>=0 && idx
< aarch64_num_of_operands (inst
->opcode
));
430 inst
->operands
[idx
].qualifier
= AARCH64_OPND_QLF_NIL
;
433 /* Inline functions operating on instruction bit-field(s). */
435 /* Generate a mask that has WIDTH number of consecutive 1s. */
437 static inline aarch64_insn
440 return ((aarch64_insn
) 1 << width
) - 1;
443 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0. */
445 gen_sub_field (enum aarch64_field_kind kind
, int lsb_rel
, int width
, aarch64_field
*ret
)
447 const aarch64_field
*field
= &fields
[kind
];
448 if (lsb_rel
< 0 || width
<= 0 || lsb_rel
+ width
> field
->width
)
450 ret
->lsb
= field
->lsb
+ lsb_rel
;
455 /* Insert VALUE into FIELD of CODE. MASK can be zero or the base mask
459 insert_field_2 (const aarch64_field
*field
, aarch64_insn
*code
,
460 aarch64_insn value
, aarch64_insn mask
)
462 assert (field
->width
< 32 && field
->width
>= 1 && field
->lsb
>= 0
463 && field
->lsb
+ field
->width
<= 32);
464 value
&= gen_mask (field
->width
);
465 value
<<= field
->lsb
;
466 /* In some opcodes, field can be part of the base opcode, e.g. the size
467 field in FADD. The following helps avoid corrupt the base opcode. */
472 /* Extract FIELD of CODE and return the value. MASK can be zero or the base
473 mask of the opcode. */
475 static inline aarch64_insn
476 extract_field_2 (const aarch64_field
*field
, aarch64_insn code
,
480 /* Clear any bit that is a part of the base opcode. */
482 value
= (code
>> field
->lsb
) & gen_mask (field
->width
);
486 /* Insert VALUE into field KIND of CODE. MASK can be zero or the base mask
490 insert_field (enum aarch64_field_kind kind
, aarch64_insn
*code
,
491 aarch64_insn value
, aarch64_insn mask
)
493 insert_field_2 (&fields
[kind
], code
, value
, mask
);
496 /* Extract field KIND of CODE and return the value. MASK can be zero or the
497 base mask of the opcode. */
499 static inline aarch64_insn
500 extract_field (enum aarch64_field_kind kind
, aarch64_insn code
,
503 return extract_field_2 (&fields
[kind
], code
, mask
);
507 extract_fields (aarch64_insn code
, aarch64_insn mask
, ...);
509 /* Inline functions selecting operand to do the encoding/decoding for a
510 certain instruction bit-field. */
512 /* Select the operand to do the encoding/decoding of the 'sf' field.
513 The heuristic-based rule is that the result operand is respected more. */
516 select_operand_for_sf_field_coding (const aarch64_opcode
*opcode
)
519 if (aarch64_get_operand_class (opcode
->operands
[0])
520 == AARCH64_OPND_CLASS_INT_REG
)
523 else if (aarch64_get_operand_class (opcode
->operands
[1])
524 == AARCH64_OPND_CLASS_INT_REG
)
525 /* e.g. float2fix. */
528 { assert (0); abort (); }
532 /* Select the operand to do the encoding/decoding of the 'type' field in
533 the floating-point instructions.
534 The heuristic-based rule is that the source operand is respected more. */
537 select_operand_for_fptype_field_coding (const aarch64_opcode
*opcode
)
540 if (aarch64_get_operand_class (opcode
->operands
[1])
541 == AARCH64_OPND_CLASS_FP_REG
)
544 else if (aarch64_get_operand_class (opcode
->operands
[0])
545 == AARCH64_OPND_CLASS_FP_REG
)
546 /* e.g. float2fix. */
549 { assert (0); abort (); }
553 /* Select the operand to do the encoding/decoding of the 'size' field in
554 the AdvSIMD scalar instructions.
555 The heuristic-based rule is that the destination operand is respected
559 select_operand_for_scalar_size_field_coding (const aarch64_opcode
*opcode
)
561 int src_size
= 0, dst_size
= 0;
562 if (aarch64_get_operand_class (opcode
->operands
[0])
563 == AARCH64_OPND_CLASS_SISD_REG
)
564 dst_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][0]);
565 if (aarch64_get_operand_class (opcode
->operands
[1])
566 == AARCH64_OPND_CLASS_SISD_REG
)
567 src_size
= aarch64_get_qualifier_esize (opcode
->qualifiers_list
[0][1]);
568 if (src_size
== dst_size
&& src_size
== 0)
569 { assert (0); abort (); }
570 /* When the result is not a sisd register or it is a long operantion. */
571 if (dst_size
== 0 || dst_size
== src_size
<< 1)
577 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
578 the AdvSIMD instructions. */
580 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode
*);
584 aarch64_insn
aarch64_get_operand_modifier_value (enum aarch64_modifier_kind
);
585 enum aarch64_modifier_kind
586 aarch64_get_operand_modifier_from_value (aarch64_insn
, bool);
589 bool aarch64_wide_constant_p (uint64_t, int, unsigned int *);
590 bool aarch64_logical_immediate_p (uint64_t, int, aarch64_insn
*);
591 int aarch64_shrink_expanded_imm8 (uint64_t);
593 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST]. */
595 copy_operand_info (aarch64_inst
*inst
, int dst
, int src
)
597 assert (dst
>= 0 && src
>= 0 && dst
< AARCH64_MAX_OPND_NUM
598 && src
< AARCH64_MAX_OPND_NUM
);
599 memcpy (&inst
->operands
[dst
], &inst
->operands
[src
],
600 sizeof (aarch64_opnd_info
));
601 inst
->operands
[dst
].idx
= dst
;
604 /* A primitive log caculator. */
606 static inline unsigned int
607 get_logsz (unsigned int size
)
609 const unsigned char ls
[16] =
610 {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
616 assert (ls
[size
- 1] != (unsigned char)-1);
620 #endif /* OPCODES_AARCH64_OPC_H */