opcodes/aarch64-opc.h

   1 /* aarch64-opc.h -- Header file for aarch64-opc.c and aarch64-opc-2.c.
   2    Copyright (C) 2012-2023 Free Software Foundation, Inc.
   3    Contributed by ARM Ltd.
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this program; see the file COPYING3. If not,
  19    see <http://www.gnu.org/licenses/>.  */
  20
  21 #ifndef OPCODES_AARCH64_OPC_H
  22 #define OPCODES_AARCH64_OPC_H
  23
  24 #include <string.h>
  25 #include "opcode/aarch64.h"
  26
  27 /* Instruction fields.
  28    Keep this sorted alphanumerically and synced with the fields array
  29    in aarch64-opc.c.  */
  30 enum aarch64_field_kind
  31 {
  32   FLD_NIL,
  33   FLD_CRm,
  34   FLD_CRm_dsb_nxs,
  35   FLD_CRn,
  36   FLD_CSSC_imm8,
  37   FLD_H,
  38   FLD_L,
  39   FLD_LSE128_Rt,
  40   FLD_LSE128_Rt2,
  41   FLD_M,
  42   FLD_N,
  43   FLD_Q,
  44   FLD_Ra,
  45   FLD_Rd,
  46   FLD_Rm,
  47   FLD_Rn,
  48   FLD_Rs,
  49   FLD_Rt,
  50   FLD_Rt2,
  51   FLD_S,
  52   FLD_SM3_imm2,
  53   FLD_SME_Pdx2,
  54   FLD_SME_Pm,
  55   FLD_SME_PNd3,
  56   FLD_SME_PNn3,
  57   FLD_SME_Q,
  58   FLD_SME_Rm,
  59   FLD_SME_Rv,
  60   FLD_SME_V,
  61   FLD_SME_VL_10,
  62   FLD_SME_VL_13,
  63   FLD_SME_ZAda_2b,
  64   FLD_SME_ZAda_3b,
  65   FLD_SME_Zdn2,
  66   FLD_SME_Zdn4,
  67   FLD_SME_Zm,
  68   FLD_SME_Zm2,
  69   FLD_SME_Zm4,
  70   FLD_SME_Zn2,
  71   FLD_SME_Zn4,
  72   FLD_SME_ZtT,
  73   FLD_SME_Zt3,
  74   FLD_SME_Zt2,
  75   FLD_SME_i1,
  76   FLD_SME_size_12,
  77   FLD_SME_size_22,
  78   FLD_SME_sz_23,
  79   FLD_SME_tszh,
  80   FLD_SME_tszl,
  81   FLD_SME_zero_mask,
  82   FLD_SVE_M_4,
  83   FLD_SVE_M_14,
  84   FLD_SVE_M_16,
  85   FLD_SVE_N,
  86   FLD_SVE_Pd,
  87   FLD_SVE_Pg3,
  88   FLD_SVE_Pg4_5,
  89   FLD_SVE_Pg4_10,
  90   FLD_SVE_Pg4_16,
  91   FLD_SVE_Pm,
  92   FLD_SVE_Pn,
  93   FLD_SVE_Pt,
  94   FLD_SVE_Rm,
  95   FLD_SVE_Rn,
  96   FLD_SVE_Vd,
  97   FLD_SVE_Vm,
  98   FLD_SVE_Vn,
  99   FLD_SVE_Za_5,
 100   FLD_SVE_Za_16,
 101   FLD_SVE_Zd,
 102   FLD_SVE_Zm_5,
 103   FLD_SVE_Zm_16,
 104   FLD_SVE_Zn,
 105   FLD_SVE_Zt,
 106   FLD_SVE_i1,
 107   FLD_SVE_i2h,
 108   FLD_SVE_i3h,
 109   FLD_SVE_i3h2,
 110   FLD_SVE_i3l,
 111   FLD_SVE_imm3,
 112   FLD_SVE_imm4,
 113   FLD_SVE_imm5,
 114   FLD_SVE_imm5b,
 115   FLD_SVE_imm6,
 116   FLD_SVE_imm7,
 117   FLD_SVE_imm8,
 118   FLD_SVE_imm9,
 119   FLD_SVE_immr,
 120   FLD_SVE_imms,
 121   FLD_SVE_msz,
 122   FLD_SVE_pattern,
 123   FLD_SVE_prfop,
 124   FLD_SVE_rot1,
 125   FLD_SVE_rot2,
 126   FLD_SVE_rot3,
 127   FLD_SVE_size,
 128   FLD_SVE_sz,
 129   FLD_SVE_sz2,
 130   FLD_SVE_tsz,
 131   FLD_SVE_tszh,
 132   FLD_SVE_tszl_8,
 133   FLD_SVE_tszl_19,
 134   FLD_SVE_xs_14,
 135   FLD_SVE_xs_22,
 136   FLD_S_imm10,
 137   FLD_abc,
 138   FLD_asisdlso_opcode,
 139   FLD_b40,
 140   FLD_b5,
 141   FLD_cmode,
 142   FLD_cond,
 143   FLD_cond2,
 144   FLD_defgh,
 145   FLD_hw,
 146   FLD_imm1_0,
 147   FLD_imm1_2,
 148   FLD_imm1_8,
 149   FLD_imm1_10,
 150   FLD_imm1_15,
 151   FLD_imm1_16,
 152   FLD_imm2_0,
 153   FLD_imm2_1,
 154   FLD_imm2_8,
 155   FLD_imm2_10,
 156   FLD_imm2_12,
 157   FLD_imm2_15,
 158   FLD_imm2_16,
 159   FLD_imm2_19,
 160   FLD_imm3_0,
 161   FLD_imm3_5,
 162   FLD_imm3_10,
 163   FLD_imm3_12,
 164   FLD_imm3_14,
 165   FLD_imm3_15,
 166   FLD_imm4_0,
 167   FLD_imm4_5,
 168   FLD_imm4_10,
 169   FLD_imm4_11,
 170   FLD_imm4_14,
 171   FLD_imm5,
 172   FLD_imm6_10,
 173   FLD_imm6_15,
 174   FLD_imm7,
 175   FLD_imm8,
 176   FLD_imm9,
 177   FLD_imm12,
 178   FLD_imm14,
 179   FLD_imm16_0,
 180   FLD_imm16_5,
 181   FLD_imm19,
 182   FLD_imm26,
 183   FLD_immb,
 184   FLD_immh,
 185   FLD_immhi,
 186   FLD_immlo,
 187   FLD_immr,
 188   FLD_imms,
 189   FLD_index,
 190   FLD_index2,
 191   FLD_ldst_size,
 192   FLD_len,
 193   FLD_lse_sz,
 194   FLD_nzcv,
 195   FLD_op,
 196   FLD_op0,
 197   FLD_op1,
 198   FLD_op2,
 199   FLD_opc,
 200   FLD_opc1,
 201   FLD_opcode,
 202   FLD_option,
 203   FLD_rotate1,
 204   FLD_rotate2,
 205   FLD_rotate3,
 206   FLD_scale,
 207   FLD_sf,
 208   FLD_shift,
 209   FLD_size,
 210   FLD_sz,
 211   FLD_type,
 212   FLD_vldst_size,
 213 };
 214
 215 /* Field description.  */
 216 struct aarch64_field
 217 {
 218   int lsb;
 219   int width;
 220 };
 221
 222 typedef struct aarch64_field aarch64_field;
 223
 224 extern const aarch64_field fields[];
 225 \f
 226 /* Operand description.  */
 227
 228 struct aarch64_operand
 229 {
 230   enum aarch64_operand_class op_class;
 231
 232   /* Name of the operand code; used mainly for the purpose of internal
 233      debugging.  */
 234   const char *name;
 235
 236   unsigned int flags;
 237
 238   /* The associated instruction bit-fields; no operand has more than 4
 239      bit-fields */
 240   enum aarch64_field_kind fields[5];
 241
 242   /* Brief description */
 243   const char *desc;
 244 };
 245
 246 typedef struct aarch64_operand aarch64_operand;
 247
 248 extern const aarch64_operand aarch64_operands[];
 249
 250 enum err_type
 251 verify_constraints (const struct aarch64_inst *, const aarch64_insn, bfd_vma,
 252                     bool, aarch64_operand_error *, aarch64_instr_sequence*);
 253
 254 /* Operand flags.  */
 255
 256 #define OPD_F_HAS_INSERTER      0x00000001
 257 #define OPD_F_HAS_EXTRACTOR     0x00000002
 258 #define OPD_F_SEXT              0x00000004      /* Require sign-extension.  */
 259 #define OPD_F_SHIFT_BY_2        0x00000008      /* Need to left shift the field
 260                                                    value by 2 to get the value
 261                                                    of an immediate operand.  */
 262 #define OPD_F_MAYBE_SP          0x00000010      /* May potentially be SP.  */
 263 #define OPD_F_OD_MASK           0x000001e0      /* Operand-dependent data.  */
 264 #define OPD_F_OD_LSB            5
 265 #define OPD_F_NO_ZR             0x00000200      /* ZR index not allowed.  */
 266 #define OPD_F_SHIFT_BY_3        0x00000400      /* Need to left shift the field
 267                                                    value by 3 to get the value
 268                                                    of an immediate operand.  */
 269 #define OPD_F_SHIFT_BY_4        0x00000800      /* Need to left shift the field
 270                                                    value by 4 to get the value
 271                                                    of an immediate operand.  */
 272
 273
 274 /* Register flags.  */
 275
 276 #undef F_DEPRECATED
 277 #define F_DEPRECATED    (1 << 0)  /* Deprecated system register.  */
 278
 279 #undef F_ARCHEXT
 280 #define F_ARCHEXT       (1 << 1)  /* Architecture dependent system register.  */
 281
 282 #undef F_HASXT
 283 #define F_HASXT         (1 << 2)  /* System instruction register <Xt>
 284                                      operand.  */
 285
 286 #undef F_REG_READ
 287 #define F_REG_READ      (1 << 3)  /* Register can only be used to read values
 288                                      out of.  */
 289
 290 #undef F_REG_WRITE
 291 #define F_REG_WRITE     (1 << 4)  /* Register can only be written to but not
 292                                      read from.  */
 293
 294 #undef F_REG_IN_CRM
 295 #define F_REG_IN_CRM    (1 << 5)  /* Register extra encoding in CRm.  */
 296
 297 #undef F_REG_ALIAS
 298 #define F_REG_ALIAS     (1 << 6)  /* Register name aliases another.  */
 299
 300 #undef F_REG_128
 301 #define F_REG_128       (1 << 7) /* System regsister implementable as 128-bit wide.  */
 302
 303 /* PSTATE field name for the MSR instruction this is encoded in "op1:op2:CRm".
 304    Part of CRm can be used to encode <pstatefield>. E.g. CRm[3:1] for SME.
 305    In order to set/get full PSTATE field name use flag F_REG_IN_CRM and below
 306    macros to encode and decode CRm encoding.
 307 */
 308 #define PSTATE_ENCODE_CRM(val) (val << 6)
 309 #define PSTATE_DECODE_CRM(flags) ((flags >> 6) & 0x0f)
 310
 311 #undef F_IMM_IN_CRM
 312 #define F_IMM_IN_CRM    (1 << 10)  /* Immediate extra encoding in CRm.  */
 313
 314 /* Also CRm may contain, in addition to <pstatefield> immediate.
 315    E.g. CRm[0] <imm1> at bit 0 for SME. Use below macros to encode and decode
 316    immediate mask.
 317 */
 318 #define PSTATE_ENCODE_CRM_IMM(mask) (mask << 11)
 319 #define PSTATE_DECODE_CRM_IMM(mask) ((mask >> 11) & 0x0f)
 320
 321 /* Helper macro to ENCODE CRm and its immediate.  */
 322 #define PSTATE_ENCODE_CRM_AND_IMM(CVAL,IMASK) \
 323         (F_REG_IN_CRM | PSTATE_ENCODE_CRM(CVAL) \
 324          | F_IMM_IN_CRM | PSTATE_ENCODE_CRM_IMM(IMASK))
 325
 326 /* Bits [15, 18] contain the maximum value for an immediate MSR.  */
 327 #define F_REG_MAX_VALUE(X) ((X) << 15)
 328 #define F_GET_REG_MAX_VALUE(X) (((X) >> 15) & 0x0f)
 329
 330 /* HINT operand flags.  */
 331 #define HINT_OPD_F_NOPRINT      (1 << 0)  /* Should not be printed.  */
 332
 333 /* Encode 7-bit HINT #imm in the lower 8 bits.  Use higher bits for flags.  */
 334 #define HINT_ENCODE(flag, val) ((flag << 8) | val)
 335 #define HINT_FLAG(val) (val >> 8)
 336 #define HINT_VAL(val) (val & 0xff)
 337
 338 static inline bool
 339 operand_has_inserter (const aarch64_operand *operand)
 340 {
 341   return (operand->flags & OPD_F_HAS_INSERTER) != 0;
 342 }
 343
 344 static inline bool
 345 operand_has_extractor (const aarch64_operand *operand)
 346 {
 347   return (operand->flags & OPD_F_HAS_EXTRACTOR) != 0;
 348 }
 349
 350 static inline bool
 351 operand_need_sign_extension (const aarch64_operand *operand)
 352 {
 353   return (operand->flags & OPD_F_SEXT) != 0;
 354 }
 355
 356 static inline bool
 357 operand_need_shift_by_two (const aarch64_operand *operand)
 358 {
 359   return (operand->flags & OPD_F_SHIFT_BY_2) != 0;
 360 }
 361
 362 static inline bool
 363 operand_need_shift_by_three (const aarch64_operand *operand)
 364 {
 365   return (operand->flags & OPD_F_SHIFT_BY_3) != 0;
 366 }
 367
 368 static inline bool
 369 operand_need_shift_by_four (const aarch64_operand *operand)
 370 {
 371   return (operand->flags & OPD_F_SHIFT_BY_4) != 0;
 372 }
 373
 374 static inline bool
 375 operand_maybe_stack_pointer (const aarch64_operand *operand)
 376 {
 377   return (operand->flags & OPD_F_MAYBE_SP) != 0;
 378 }
 379
 380 /* Return the value of the operand-specific data field (OPD_F_OD_MASK).  */
 381 static inline unsigned int
 382 get_operand_specific_data (const aarch64_operand *operand)
 383 {
 384   return (operand->flags & OPD_F_OD_MASK) >> OPD_F_OD_LSB;
 385 }
 386
 387 /* Return the width of field number N of operand *OPERAND.  */
 388 static inline unsigned
 389 get_operand_field_width (const aarch64_operand *operand, unsigned n)
 390 {
 391   assert (operand->fields[n] != FLD_NIL);
 392   return fields[operand->fields[n]].width;
 393 }
 394
 395 /* Return the total width of the operand *OPERAND.  */
 396 static inline unsigned
 397 get_operand_fields_width (const aarch64_operand *operand)
 398 {
 399   int i = 0;
 400   unsigned width = 0;
 401   while (operand->fields[i] != FLD_NIL)
 402     width += fields[operand->fields[i++]].width;
 403   assert (width > 0 && width < 32);
 404   return width;
 405 }
 406
 407 static inline const aarch64_operand *
 408 get_operand_from_code (enum aarch64_opnd code)
 409 {
 410   return aarch64_operands + code;
 411 }
 412 \f
 413 /* Operand qualifier and operand constraint checking.  */
 414
 415 int aarch64_match_operands_constraint (aarch64_inst *,
 416                                        aarch64_operand_error *);
 417
 418 /* Operand qualifier related functions.  */
 419 const char* aarch64_get_qualifier_name (aarch64_opnd_qualifier_t);
 420 unsigned char aarch64_get_qualifier_nelem (aarch64_opnd_qualifier_t);
 421 aarch64_insn aarch64_get_qualifier_standard_value (aarch64_opnd_qualifier_t);
 422 int aarch64_find_best_match (const aarch64_inst *,
 423                              const aarch64_opnd_qualifier_seq_t *,
 424                              int, aarch64_opnd_qualifier_t *, int *);
 425
 426 static inline void
 427 reset_operand_qualifier (aarch64_inst *inst, int idx)
 428 {
 429   assert (idx >=0 && idx < aarch64_num_of_operands (inst->opcode));
 430   inst->operands[idx].qualifier = AARCH64_OPND_QLF_NIL;
 431 }
 432 \f
 433 /* Inline functions operating on instruction bit-field(s).  */
 434
 435 /* Generate a mask that has WIDTH number of consecutive 1s.  */
 436
 437 static inline aarch64_insn
 438 gen_mask (int width)
 439 {
 440   return ((aarch64_insn) 1 << width) - 1;
 441 }
 442
 443 /* LSB_REL is the relative location of the lsb in the sub field, starting from 0.  */
 444 static inline int
 445 gen_sub_field (enum aarch64_field_kind kind, int lsb_rel, int width, aarch64_field *ret)
 446 {
 447   const aarch64_field *field = &fields[kind];
 448   if (lsb_rel < 0 || width <= 0 || lsb_rel + width > field->width)
 449     return 0;
 450   ret->lsb = field->lsb + lsb_rel;
 451   ret->width = width;
 452   return 1;
 453 }
 454
 455 /* Insert VALUE into FIELD of CODE.  MASK can be zero or the base mask
 456    of the opcode.  */
 457
 458 static inline void
 459 insert_field_2 (const aarch64_field *field, aarch64_insn *code,
 460                 aarch64_insn value, aarch64_insn mask)
 461 {
 462   assert (field->width < 32 && field->width >= 1 && field->lsb >= 0
 463           && field->lsb + field->width <= 32);
 464   value &= gen_mask (field->width);
 465   value <<= field->lsb;
 466   /* In some opcodes, field can be part of the base opcode, e.g. the size
 467      field in FADD.  The following helps avoid corrupt the base opcode.  */
 468   value &= ~mask;
 469   *code |= value;
 470 }
 471
 472 /* Extract FIELD of CODE and return the value.  MASK can be zero or the base
 473    mask of the opcode.  */
 474
 475 static inline aarch64_insn
 476 extract_field_2 (const aarch64_field *field, aarch64_insn code,
 477                  aarch64_insn mask)
 478 {
 479   aarch64_insn value;
 480   /* Clear any bit that is a part of the base opcode.  */
 481   code &= ~mask;
 482   value = (code >> field->lsb) & gen_mask (field->width);
 483   return value;
 484 }
 485
 486 /* Insert VALUE into field KIND of CODE.  MASK can be zero or the base mask
 487    of the opcode.  */
 488
 489 static inline void
 490 insert_field (enum aarch64_field_kind kind, aarch64_insn *code,
 491               aarch64_insn value, aarch64_insn mask)
 492 {
 493   insert_field_2 (&fields[kind], code, value, mask);
 494 }
 495
 496 /* Extract field KIND of CODE and return the value.  MASK can be zero or the
 497    base mask of the opcode.  */
 498
 499 static inline aarch64_insn
 500 extract_field (enum aarch64_field_kind kind, aarch64_insn code,
 501                aarch64_insn mask)
 502 {
 503   return extract_field_2 (&fields[kind], code, mask);
 504 }
 505
 506 extern aarch64_insn
 507 extract_fields (aarch64_insn code, aarch64_insn mask, ...);
 508 \f
 509 /* Inline functions selecting operand to do the encoding/decoding for a
 510    certain instruction bit-field.  */
 511
 512 /* Select the operand to do the encoding/decoding of the 'sf' field.
 513    The heuristic-based rule is that the result operand is respected more.  */
 514
 515 static inline int
 516 select_operand_for_sf_field_coding (const aarch64_opcode *opcode)
 517 {
 518   int idx = -1;
 519   if (aarch64_get_operand_class (opcode->operands[0])
 520       == AARCH64_OPND_CLASS_INT_REG)
 521     /* normal case.  */
 522     idx = 0;
 523   else if (aarch64_get_operand_class (opcode->operands[1])
 524            == AARCH64_OPND_CLASS_INT_REG)
 525     /* e.g. float2fix.  */
 526     idx = 1;
 527   else
 528     { assert (0); abort (); }
 529   return idx;
 530 }
 531
 532 /* Select the operand to do the encoding/decoding of the 'type' field in
 533    the floating-point instructions.
 534    The heuristic-based rule is that the source operand is respected more.  */
 535
 536 static inline int
 537 select_operand_for_fptype_field_coding (const aarch64_opcode *opcode)
 538 {
 539   int idx;
 540   if (aarch64_get_operand_class (opcode->operands[1])
 541       == AARCH64_OPND_CLASS_FP_REG)
 542     /* normal case.  */
 543     idx = 1;
 544   else if (aarch64_get_operand_class (opcode->operands[0])
 545            == AARCH64_OPND_CLASS_FP_REG)
 546     /* e.g. float2fix.  */
 547     idx = 0;
 548   else
 549     { assert (0); abort (); }
 550   return idx;
 551 }
 552
 553 /* Select the operand to do the encoding/decoding of the 'size' field in
 554    the AdvSIMD scalar instructions.
 555    The heuristic-based rule is that the destination operand is respected
 556    more.  */
 557
 558 static inline int
 559 select_operand_for_scalar_size_field_coding (const aarch64_opcode *opcode)
 560 {
 561   int src_size = 0, dst_size = 0;
 562   if (aarch64_get_operand_class (opcode->operands[0])
 563       == AARCH64_OPND_CLASS_SISD_REG)
 564     dst_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][0]);
 565   if (aarch64_get_operand_class (opcode->operands[1])
 566       == AARCH64_OPND_CLASS_SISD_REG)
 567     src_size = aarch64_get_qualifier_esize (opcode->qualifiers_list[0][1]);
 568   if (src_size == dst_size && src_size == 0)
 569     { assert (0); abort (); }
 570   /* When the result is not a sisd register or it is a long operantion.  */
 571   if (dst_size == 0 || dst_size == src_size << 1)
 572     return 1;
 573   else
 574     return 0;
 575 }
 576
 577 /* Select the operand to do the encoding/decoding of the 'size:Q' fields in
 578    the AdvSIMD instructions.  */
 579
 580 int aarch64_select_operand_for_sizeq_field_coding (const aarch64_opcode *);
 581 \f
 582 /* Miscellaneous.  */
 583
 584 aarch64_insn aarch64_get_operand_modifier_value (enum aarch64_modifier_kind);
 585 enum aarch64_modifier_kind
 586 aarch64_get_operand_modifier_from_value (aarch64_insn, bool);
 587
 588
 589 bool aarch64_wide_constant_p (uint64_t, int, unsigned int *);
 590 bool aarch64_logical_immediate_p (uint64_t, int, aarch64_insn *);
 591 int aarch64_shrink_expanded_imm8 (uint64_t);
 592
 593 /* Copy the content of INST->OPERANDS[SRC] to INST->OPERANDS[DST].  */
 594 static inline void
 595 copy_operand_info (aarch64_inst *inst, int dst, int src)
 596 {
 597   assert (dst >= 0 && src >= 0 && dst < AARCH64_MAX_OPND_NUM
 598           && src < AARCH64_MAX_OPND_NUM);
 599   memcpy (&inst->operands[dst], &inst->operands[src],
 600           sizeof (aarch64_opnd_info));
 601   inst->operands[dst].idx = dst;
 602 }
 603
 604 /* A primitive log caculator.  */
 605
 606 static inline unsigned int
 607 get_logsz (unsigned int size)
 608 {
 609   const unsigned char ls[16] =
 610     {0, 1, -1, 2, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1, 4};
 611   if (size > 16)
 612     {
 613       assert (0);
 614       return -1;
 615     }
 616   assert (ls[size - 1] != (unsigned char)-1);
 617   return ls[size - 1];
 618 }
 619
 620 #endif /* OPCODES_AARCH64_OPC_H */