| blob | c7994e307f80ae749a8119dfaf2124fddd90a46c |
1 2017-12-20 Jim Wilson <jimw@sifive.com>
3 * riscv-opc.c (match_c_add_with_hint, match_c_lui_with_hint): New.
4 (riscv_opcodes) <li>: Delete "d,0" line. Change Cj to Co.
5 <andi, and, add, addiw, addw, c.addi>: Change Cj to Co.
6 <add>: Add explanatory comment for 4-operand add instruction.
7 <c.nop>: Add support for immediate operand.
8 <c.mv, c.add>: Use match_c_add_with_hint instead of match_c_add.
9 <c.lui>: Use match_c_lui_with_hint instead of match_c_lui.
10 <c.li, c.slli>: Use match_opcode instead of match_rd_nonzero.
12 2017-12-19 Tamar Christina <tamar.christina@arm.com>
14 PR gas/22559
15 * aarch64-asm.c (aarch64_ins_reglane): Change AARCH64_OPND_QLF_S_B to
16 AARCH64_OPND_QLF_S_4B
17 * aarch64-dis.c (aarch64_ext_reglane): Change AARCH64_OPND_QLF_S_B to
18 AARCH64_OPND_QLF_S_4B
19 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
20 * aarch64-tbl.h (QL_V2DOT): Change S_B to S_4B.
22 2017-12-19 Tamar Christina <tamar.christina@arm.com>
24 PR gas/22529
25 * aarch64-opc.c (aarch64_opnd_qualifiers): Add 4b variant.
27 2017-12-18 Jan Beulich <jbeulich@suse.com>
29 * i386-gen.c (operand_type_init): Delete OPERAND_TYPE_REGYMM and
30 OPERAND_TYPE_REGZMM entries.
31 * i386-opc.h (enum of opcode modifiers): Extend comment.
32 i386-opc.tbl (vaddpd, vaddps, vaddsubpd, vaddsubps, vandnpd,
33 vandnps, vandpd, vandps, vblendpd, vblendps, vblendvpd,
34 vblendvps, vbroadcastss, vcmpeq_ospd, vcmpeq_osps, vcmpeqpd,
35 vcmpeqps, vcmpeq_uqpd, vcmpeq_uqps, vcmpeq_uspd, vcmpeq_usps,
36 vcmpfalse_ospd, vcmpfalse_osps, vcmpfalsepd, vcmpfalseps,
37 vcmpge_oqpd, vcmpge_oqps, vcmpgepd, vcmpgeps, vcmpgt_oqpd,
38 vcmpgt_oqps, vcmpgtpd, vcmpgtps, vcmple_oqpd, vcmple_oqps,
39 vcmplepd, vcmpleps, vcmplt_oqpd, vcmplt_oqps, vcmpltpd,
40 vcmpltps, vcmpneq_oqpd, vcmpneq_oqps, vcmpneq_ospd,
41 vcmpneq_osps, vcmpneqpd, vcmpneqps, vcmpneq_uspd, vcmpneq_usps,
42 vcmpngepd, vcmpngeps, vcmpnge_uqpd, vcmpnge_uqps, vcmpngtpd,
43 vcmpngtps, vcmpngt_uqpd, vcmpngt_uqps, vcmpnlepd, vcmpnleps,
44 vcmpnle_uqpd, vcmpnle_uqps, vcmpnltpd, vcmpnltps, vcmpnlt_uqpd,
45 vcmpnlt_uqps, vcmpordpd, vcmpordps, vcmpord_spd, vcmpord_sps,
46 vcmppd, vcmpps, vcmptruepd, vcmptrueps, vcmptrue_uspd,
47 vcmptrue_usps, vcmpunordpd, vcmpunordps, vcmpunord_spd,
48 vcmpunord_sps, vcvtdq2ps, vcvtpd2dq, vcvtpd2ps, vcvtps2dq,
49 vcvttpd2dq, vcvttps2dq, vdivpd, vdivps, vdpps, vhaddpd, vhaddps,
50 vhsubpd, vhsubps, vlddqu, vmaskmovpd, vmaskmovps, vmaxpd,
51 vmaxps, vminpd, vminps, vmovapd, vmovaps, vmovdqa, vmovdqu,
52 vmovmskpd, vmovmskps, vmovntdq, vmovntpd, vmovntps, vmovshdup,
53 vmovsldup, vmovupd, vmovups, vmulpd, vmulps, vorpd, vorps,
54 vpermilpd, vpermilps, vptest, vrcpps, vroundpd, vroundps,
55 vrsqrtps, vshufpd, vshufps, vsqrtpd, vsqrtps, vsubpd, vsubps,
56 vtestpd, vtestps, vunpckhpd, vunpckhps, vunpcklpd, vunpcklps,
57 vxorpd, vxorps, vpblendd, vpbroadcastb, vpbroadcastd,
58 vpbroadcastw, vpbroadcastq, vpmaskmovd, vpmaskmovq, vpsllvd,
59 vpsllvq, vpsravd, vpsravq, vpsrlvd, vpsrlvq): Fold 128- and
60 256-bit forms. Use CheckRegSize instead of IgnoreSize where
61 appropriate. Drop Xmmword and Ymmword from the results where
62 possible.
63 * i386-tbl.h: Re-generate.
65 2017-12-18 Jan Beulich <jbeulich@suse.com>
67 * i386-gen.c (operand_type_shorthands): Add RegXMM, RegYMM, and
68 RegZMM.
69 (opcode_modifiers): Drop FirstXmm0.
70 (operand_types): Replace RegXMM, RegYMM, and RegZMM with just
71 RegSIMD.
72 * i386-opc.h (enum of opcode modifiers): Drop FirstXmm0.
73 (struct i386_opcode_modifier): Drop firstxmm0.
74 (enum of operand types): Replace RegXMM, RegYMM, and RegZMM with
75 just RegSIMD. Extend comment.
76 (union i386_operand_type): Replace regxmm, regymm, and regzmm
77 with just regsimd.
78 * i386-opc.tbl (blendvpd, blendvps, pblendvb, sha256rnds2): Use
79 Acc|Xmmword.
80 * i386-reg.tbl (xmm0): Add Acc.
81 * i386-init.h, i386-tbl.h: Re-generate.
83 2017-12-18 Jan Beulich <jbeulich@suse.com>
85 * i386-gen.c (operand_type_shorthands): Add FloatAcc and
86 FloatReg.
87 (operand_types): Drop FloatAcc and FloatReg.
88 * i386-opc.h (enum of operand types): Likewise. Extend comment.
89 (union i386_operand_type): Drop floatacc and floatreg.
90 * i386-reg.tbl (st, st(0)): Replace FloatAcc by Acc.
91 * i386-init.h, i386-tbl.h: Re-generate.
93 2017-12-18 Jan Beulich <jbeulich@suse.com>
95 * i386-gen.c (operand_type_shorthands): New.
96 (opcode_modifiers): Replace Reg<N> with just Reg.
97 (set_bitfield_from_cpu_flag_init): Rename to
98 set_bitfield_from_shorthand. Drop value parameter. Process
99 operand_type_shorthands.
100 (set_bitfield): Adjust call accordingly.
101 * i386-opc.h (enum of operand types): Replace Reg<N> with just
102 Reg.
103 (union i386_operand_type): Replace reg<N> with just reg.
104 * i386-opc.tbl (extractps, pextrb, pextrw, pinsrb, pinsrw,
105 vextractps, vpextrb, vpextrw, vpinsrb, vpinsrw): Split into
106 separate register and memory forms.
107 * i386-reg.tbl (al): Drop Byte.
108 (ax): Drop Word.
109 (eax): Drop Dword.
110 (rax): Drop Qword.
111 * i386-init.h, i386-tbl.h: Re-generate.
113 2017-12-15 Dimitar Dimitrov <dimitar@dinux.eu>
115 * disassemble.c (disassemble_init_for_target): Don't put PRU
116 between powerpc and rs6000 cases.
118 2017-12-15 Jan Beulich <jbeulich@suse.com>
120 * i386-opc.tbl (adc, add, and, cmp, cmps, in, ins, lods, mov,
121 movabs, movq, movs, or, out, outs, ptwrite, rcl, rcr, rol, ror,
122 sal, sar, sbb, scas, scmp, shl, shr, slod, smov, ssca, ssto,
123 stos, sub, test, xor): Drop CheckRegSize from variants not
124 allowing for two (or more) register operands.
125 * i386-tbl.h: Re-generate.
127 2017-12-13 Jim Wilson <jimw@sifive.com>
129 PR 22599
130 * riscv-opc.c (riscv_opcodes) <fsrmi, fsflagsi>: New.
132 2017-12-13 Dimitar Dimitrov <dimitar@dinux.eu>
134 * disassemble.c: Enable disassembler_needs_relocs for PRU.
136 2017-12-11 Petr Pavlu <petr.pavlu@arm.com>
137 Renlin Li <renlin.li@arm.com>
139 * aarch64-dis.c (print_insn_aarch64): Move symbol section check ...
140 (get_sym_code_type): Here.
142 2017-12-03 Alan Modra <amodra@gmail.com>
144 * ppc-opc.c (extract_li20): Rewrite.
146 2017-12-01 Peter Bergner <bergner@vnet.ibm.com>
148 * opcodes/ppc-dis.c (disassemble_init_powerpc): Fix white space.
149 (operand_value_powerpc): Update return and argument type.
150 <value, top>: Update type.
151 (skip_optional_operands): Update argument type.
152 (lookup_powerpc): Likewise.
153 (lookup_vle): Likewise.
154 <table_opcd, table_mask, insn2>: Update type.
155 (lookup_spe2): Update argument type.
156 <table_opcd, table_mask, insn2>: Update type.
157 (print_insn_powerpc) <insn, value>: Update type.
158 Use PPC_INT_FMT for printing instructions and operands.
159 * opcodes/ppc-opc.c (insert_arx, extract_arx, insert_ary, extract_ary,
160 insert_rx, extract_rx, insert_ry, extract_ry, insert_bat, extract_bat,
161 insert_bba, extract_bba, insert_bdm, extract_bdm, insert_bdp,
162 extract_bdp, valid_bo_pre_v2, valid_bo_post_v2, valid_bo, insert_bo,
163 extract_bo, insert_boe, extract_boe, insert_dcmxs, extract_dcmxs,
164 insert_dxd, extract_dxd, insert_dxdn, extract_dxdn, insert_fxm,
165 extract_fxm, insert_li20, extract_li20, insert_ls, extract_ls,
166 insert_esync, extract_esync, insert_mbe, extract_mbe, insert_mb6,
167 extract_mb6, extract_nb, insert_nbi, insert_nsi, extract_nsi,
168 insert_ral, extract_ral, insert_ram, extract_ram, insert_raq,
169 extract_raq, insert_ras, extract_ras, insert_rbs, extract_rbs,
170 insert_rbx, extract_rbx, insert_sci8, extract_sci8, insert_sci8n,
171 extract_sci8n, insert_sd4h, extract_sd4h, insert_sd4w, extract_sd4w,
172 insert_oimm, extract_oimm, insert_sh6, extract_sh6, insert_spr,
173 extract_spr, insert_sprg, extract_sprg, insert_tbr, extract_tbr,
174 insert_xt6, extract_xt6, insert_xtq6, extract_xtq6, insert_xa6,
175 extract_xa6, insert_xb6, extract_xb6, insert_xb6s, extract_xb6s,
176 insert_xc6, extract_xc6, insert_dm, extract_dm, insert_vlesi,
177 extract_vlesi, insert_vlensi, extract_vlensi, insert_vleui,
178 extract_vleui, insert_vleil, extract_vleil, insert_evuimm1_ex0,
179 extract_evuimm1_ex0, insert_evuimm2_ex0, extract_evuimm2_ex0,
180 insert_evuimm4_ex0, extract_evuimm4_ex0, insert_evuimm8_ex0,
181 extract_evuimm8_ex0, insert_evuimm_lt8, extract_evuimm_lt8,
182 insert_evuimm_lt16, extract_evuimm_lt16, insert_rD_rS_even,
183 extract_rD_rS_even, insert_off_lsp, extract_off_lsp, insert_off_spe2,
184 extract_off_spe2, insert_Ddd, extract_Ddd): Update types.
185 (OP, OPTO, OPL, OPVUP, OPVUPRT, A, AFRALFRC_MASK, B, BD8, BD8IO, BD15,
186 BD24, BBO, Y_MASK , AT1_MASK, AT2_MASK, BBOCB, C_LK, C, CTX, UCTX,
187 DX, EVSEL, IA16, I16A, I16L, IM7, LI20, MME, MD, MDS, SC, SC_MASK,
188 SCI8, SCI8BF, SD4, SE_IM5, SE_R, SE_RR, VX, VX_LSP, VX_RA_CONST,
189 VX_RB_CONST, VX_SPE_CRFD, VX_SPE2_CLR, VX_SPE2_SPLATB, VX_SPE2_OCTET,
190 VX_SPE2_DDHH, VX_SPE2_HH, VX_SPE2_EVMAR, VX_SPE2_EVMAR_MASK, VXA,
191 VXR, VXASH, X, EX, XX2, XX3, XX3RC, XX4, Z, XWRA_MASK, XLRT_MASK,
192 XRLARB_MASK, XLRAND_MASK, XRTLRA_MASK, XRTLRARB_MASK, XRTARARB_MASK,
193 XRTBFRARB_MASK, XOPL, XOPL2, XRCL, XRT, XRTRA, XCMP_MASK, XCMPL_MASK,
194 XTO, XTLB, XSYNC, XEH_MASK, XDSS, XFL, XISEL, XL, XLO, XLYLK, XLOCB,
195 XMBAR, XO, XOPS, XS, XFXM, XSPR, XUC, XW, APU): Update types in casts.
197 2017-11-29 Jan Beulich <jbeulich@suse.com>
199 * i386-gen.c (active_cpu_flags, active_isstring, enum stage):
200 New.
201 (output_cpu_flags): Update active_cpu_flags.
202 (process_i386_opcode_modifier): Update active_isstring.
203 (output_operand_type): Rename "macro" parameter to "stage",
204 changing its type.
205 (process_i386_operand_type): Likewise. Track presence of
206 BaseIndex and emit DispN accordingly.
207 (output_i386_opcode, process_i386_registers,
208 process_i386_initializers): Adjust calls to
209 process_i386_operand_type() for its changed parameter type.
210 * i386-opc.tbl: Drop Disp8, Disp16, Disp32, and Disp32S from
211 all insns operands having BaseIndex set.
212 * i386-tbl.h: Re-generate.
214 2017-11-29 Jan Beulich <jbeulich@suse.com>
216 * i386-gen.c (operand_type_init): Remove OPERAND_TYPE_VEC_DISP8
217 entry.
218 (operand_types): Remove Vec_Disp8 entry.
219 * i386-opc.h (Vec_Disp8): Delete.
220 (union i386_operand_type): Remove vec_disp8.
221 (i386-opc.tbl): Remove Vec_Disp8.
222 * i386-init.h, i386-tbl.h: Re-generate.
224 2017-11-29 Stefan Stroe <stroestefan@gmail.com>
226 * po/Make-in (datadir): Define as @datadir@.
227 (localedir): Define as @localedir@.
228 (gnulocaledir, gettextsrcdir): Use @datarootdir@.
230 2017-11-27 Nick Clifton <nickc@redhat.com>
232 * po/zh_CN.po: Updated simplified Chinese translation.
234 2017-11-24 Jan Beulich <jbeulich@suse.com>
236 * i386-dis.c (float_mem): Add suffixes to fi* in the "de" and
237 "df" groups.
239 2017-11-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
241 * i386-opc.tbl: Add Disp8MemShift for AVX512 VAES instructions.
242 * i386-tbl.h: Regenerate.
244 2017-11-23 Jan Beulich <jbeulich@suse.com>
246 * i386-dis.c (OP_E_memory): Also shift the 8-bit immediate in
247 the 16-bit addressing case.
249 2017-11-23 Jan Beulich <jbeulich@suse.com>
251 * i386-dis.c (dis386_twobyte): Correct ud1. Add ud0.
252 (twobyte_has_modrm): Set flag for index 0xb9 and 0xff.
253 * i386-opc.tbl (ud1, ud2b): Add operands.
254 (ud0): New.
255 * i386-tbl.h: Re-generate.
257 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
259 * i386-opc.tbl: Remove Vec_Disp8 from vgf2p8mulb.
260 * i386-tbl.h: Regenerate.
262 2017-11-22 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
264 * i386-opc.tbl: Remove Vec_Disp8 from vpcompressb and vpexpandb.
265 * i386-tbl.h: Regenerate.
267 2017-11-22 Claudiu Zissulescu <claziss@synopsys.com>
269 *arc-opc (insert_rhv2): Check h-regs range.
271 2017-11-21 Claudiu Zissulescu <claziss@synopsys.com>
273 * arc-dis.c (print_insn_arc): Pretty print pc-relative offsets.
274 * arc-opc.c (SIMM21_A16_5): Make it pc-relative.
276 2017-11-16 Tamar Christina <tamar.christina@arm.com>
278 * aarch64-tbl.h (aarch64_feature_fp_16_v8_2): Require AARCH64_FEATURE_F16_FML
279 and AARCH64_FEATURE_F16.
281 2017-11-16 Tamar Christina <tamar.christina@arm.com>
283 * aarch64-tbl.h (sha512h, sha512h2, sha512su0, sha512su1, eor3): New.
284 (rax1, xar, bcax, sm3ss1, sm3tt1a, sm3tt1b, sm3tt2a, sm3tt2b): New.
285 (sm3partw1, sm3partw2, sm4e, sm4ekey, fmlal, fmlsl): New.
286 (fmlal2, fmlsl2, cfinv, rmif, setf8, setf16, stlurb): New.
287 (ldapurb, ldapursb, stlurh, ldapurh, ldapursh, stlur): New.
288 (ldapur, ldapursw, stlur): New.
289 * aarch64-dis-2.c: Regenerate.
291 2017-11-16 Jan Beulich <jbeulich@suse.com>
293 (get_valid_dis386): Never flag bad opcode when
294 vex.register_specifier is beyond 7. Always store all four
295 bits of it. Move 16-/32-bit override in EVEX handling after
296 all to be overridden bits have been set.
297 (OP_VEX): Mask vex.register_specifier outside of 64-bit mode.
298 Use rex to determine GPR register set.
299 (OP_EX_VexReg, OP_Vex_2src_1, OP_Vex_2src_2, OP_REG_VexI4,
300 OP_LWP_E): Mask vex.register_specifier outside of 64-bit mode.
302 2017-11-15 Jan Beulich <jbeulich@suse.com>
304 * i386-dis.c (OP_VEX, OP_LWPCB_E, OP_LWP_E): Use rex to
305 determine GPR register set.
307 2017-11-15 Jan Beulich <jbeulich@suse.com>
309 * i386-dis.c (VEXI4_Fixup, VexI4): Delete.
310 (prefix_table, xop_table, vex_len_table): Remove VexI4 uses.
311 (OP_EX_VexW): Move setting of vex_w_done. Update codep on 2nd
312 pass.
313 (OP_REG_VexI4): Drop low 4 bits check.
315 2017-11-15 Jan Beulich <jbeulich@suse.com>
317 * i386-reg.tbl (axl): Remove Acc and Byte.
318 * i386-tbl.h: Re-generate.
320 2017-11-14 Jan Beulich <jbeulich@suse.com>
322 * i386-dis.c (VPCOM_Fixup, VPCOM, xop_cmp_op): New.
323 (vex_len_table): Use VPCOM.
325 2017-11-14 Jan Beulich <jbeulich@suse.com>
327 * i386-dis-evex.h (evex_table[EVEX_W_0F3A3E_P_2]): Use VPCMP.
328 (evex_table[EVEX_W_0F3A3F_P_2]): Likewise.
329 * i386-opc.tbl (vpcmpeqb, vpcmpgtb, vpcmpeqw, vpcmpgtw, vpcmpuw,
330 vpcmpw): Move up.
331 (vpcmpeqb, vpcmpleb, vpcmpltb, vpcmpneqb, vpcmpnleb, vpcmpnltb,
332 vpcmpequb, vpcmpleub, vpcmpltub, vpcmpnequb, vpcmpnleub,
333 vpcmpnltub, vpcmpeqw, vpcmplew, vpcmpltw, vpcmpneqw, vpcmpnlew,
334 vpcmpnltw, vpcmpequw, vpcmpleuw, vpcmpltuw, vpcmpnequw, vpcmpnleuw,
335 vpcmpnltuw): New.
336 * i386-tbl.h: Re-generate.
338 2017-11-14 Jan Beulich <jbeulich@suse.com>
340 * i386-opc.tbl (cmps, ins, lods, movs, outs, scas, scmp, slod,
341 smov, ssca, stos, ssto, xlat): Drop Disp*.
342 * i386-tbl.h: Re-generate.
344 2017-11-13 Jan Beulich <jbeulich@suse.com>
346 * i386-opc.tbl (fxsave64, fxrstor64, xsave64, xrstor64,
347 xsaveopt64): Add No_qSuf.
348 * i386-tbl.h: Re-generate.
350 2017-11-09 Tamar Christina <tamar.christina@arm.com>
352 * aarch64-opc.c (aarch64_sys_regs): Add ARMv8.4-a registers;
353 dit, vstcr_el2, vsttbr_el2, cnthvs_tval_el2, cnthvs_cval_el2,
354 cnthvs_ctl_el2, cnthps_tval_el2, cnthps_cval_el2, cnthps_ctl_el2,
355 sder32_el2, vncr_el2.
356 (aarch64_sys_reg_supported_p): Likewise.
357 (aarch64_pstatefields): Add dit register.
358 (aarch64_pstatefield_supported_p): Likewise.
359 (aarch64_sys_regs_tlbi): Add vmalle1os, vae1os, aside1os, vaae1os,
360 vale1os, vaale1os, ipas2e1os, ipas2le1os, vae2os, vale2os, vmalls12e1os,
361 vae3os, vale3os, alle2os, alle1os, alle3os, rvae1, rvaae1, rvale1,
362 rvaale1, rvae1is, rvaae1is, rvale1is, rvaale1is, rvae1os, rvaae1os,
363 rvale1os, rvaale1os, ripas2e1is, ripas2le1is, ripas2e1, ripas2le1,
364 ripas2e1os, ripas2le1os, rvae2, rvale2, rvae2is, rvale2is, rvae2os,
365 rvale2os, rvae3, rvale3, rvae3is, rvale3is, rvae3os, rvale3os.
367 2017-11-09 Tamar Christina <tamar.christina@arm.com>
369 * aarch64-tbl.h (QL_SHA512UPT, QL_V2SAME2D, QL_V3SAME2D): New.
370 (QL_V4SAME16B, QL_V4SAME4S, QL_XAR, QL_SM3TT, QL_V3FML2S): New.
371 (QL_V3FML4S, QL_V2FML2S, QL_V2FML4S, QL_RMIF, QL_SETF): New.
372 (QL_STLW, QL_STLX): New.
374 2017-11-09 Tamar Christina <tamar.christina@arm.com>
376 * aarch64-asm.h (ins_addr_offset): New.
377 * aarch64-asm.c (aarch64_ins_reglane): Add cryptosm3.
378 (aarch64_ins_addr_offset): New.
379 * aarch64-asm-2.c: Regenerate.
380 * aarch64-dis.h (ext_addr_offset): New.
381 * aarch64-dis.c (aarch64_ext_reglane): Add cryptosm3.
382 (aarch64_ext_addr_offset): New.
383 * aarch64-dis-2.c: Regenerate.
384 * aarch64-opc.h (aarch64_field_kind): Add FLD_imm6_2,
385 FLD_imm4_2 and FLD_SM3_imm2.
386 * aarch64-opc.c (fields): Add FLD_imm6_2,
387 FLD_imm4_2 and FLD_SM3_imm2.
388 (operand_general_constraint_met_p): Add AARCH64_OPND_ADDR_OFFSET.
389 (aarch64_print_operand): Add AARCH64_OPND_Va, AARCH64_OPND_SM3_IMM2,
390 AARCH64_OPND_MASK, AARCH64_OPND_IMM_2 and AARCH64_OPND_ADDR_OFFSET.
391 * aarch64-opc-2.c (Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2): New.
392 * aarch64-tbl.h
393 (aarch64_opcode_table): Add Va, MASK, IMM_2, ADDR_OFFSET, SM3_IMM2.
395 2017-11-09 Tamar Christina <tamar.christina@arm.com>
397 * aarch64-tbl.h
398 (aarch64_feature_v8_4, aarch64_feature_crypto_v8_2): New.
399 (aarch64_feature_sm4, aarch64_feature_sha3): New.
400 (aarch64_feature_fp_16_v8_2): New.
401 (ARMV8_4, SHA3, SM4, CRYPTO_V8_2, FP_F16_V8_2): New.
402 (V8_4_INSN, CRYPTO_V8_2_INSN): New.
403 (SHA3_INSN, SM4_INSN, FP16_V8_2_INSN): New.
405 2017-11-08 Tamar Christina <tamar.christina@arm.com>
407 * aarch64-tbl.h (aarch64_feature_crypto): Add AES and SHA2.
408 (aarch64_feature_sha2, aarch64_feature_aes): New.
409 (SHA2, AES): New.
410 (AES_INSN, SHA2_INSN): New.
411 (pmull, pmull2, aese, aesd, aesmc, aesimc): Change to AES_INS.
412 (sha1h, sha1su1, sha256su0, sha1c, sha1p,
413 sha1m, sha1su0, sha256h, sha256h2, sha256su1):
414 Change to SHA2_INS.
416 2017-11-08 Jiong Wang <jiong.wang@arm.com>
417 Tamar Christina <tamar.christina@arm.com>
419 * arm-dis.c (coprocessor_opcodes): New entries for ARMv8.2-A new
420 FP16 instructions, including vfmal.f16 and vfmsl.f16.
422 2017-11-07 Andrew Burgess <andrew.burgess@embecosm.com>
424 * arc-nps400-tbl.h: Change incorrect use of NONE to MISC.
426 2017-11-07 Alan Modra <amodra@gmail.com>
428 * opintl.h: Formatting, comment fixes.
429 (gettext, ngettext): Redefine when ENABLE_NLS.
430 (ngettext, dngettext, dcngettext): Define when !ENABLE_NLS.
431 (_): Define using gettext.
432 (textdomain, bindtextdomain): Use safer "do nothing".
434 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
436 * arc-dis.c (print_hex): New variable.
437 (parse_option): Check for hex option.
438 (print_insn_arc): Use hexadecimal representation for short
439 immediate values when requested.
440 (print_arc_disassembler_options): Add hex option to the list.
442 2017-11-03 Claudiu Zissulescu <claziss@synopsys.com>
444 * arc-tbl.h (abss, abssh, adc, adcs, adds, aslacc, asls, aslsacc)
445 (asrs, asrsr, cbflyhf0r, cbflyhf1r, cmacchfr, cmacchnfr, cmachfr)
446 (cmachnfr, cmpychfr, cmpychnfr, cmpyhfmr, cmpyhfr, cmpyhnfr, divf)
447 (dmachbl, dmachbm, dmachf, dmachfr, dmacwhf, dmpyhbl, dmpyhbm)
448 (dmpyhf, dmpyhfr, dmpyhwf, dmpywhf, dsync, flagacc, getacc, macdf)
449 (macf, macfr, macwhfl, macwhflr, macwhfm, macwhfmr, macwhkl)
450 (macwhkul, macwhl, macwhul, mpydf, mpyf, mpyfr, mpywhfl, mpywhflr)
451 (mpywhfm, mpywhfmr, mpywhkl, mpywhkul, mpywhl, mpywhul, msubdf)
452 (msubf, msubfr, msubwhfl, msubwhflr, msubwhfm, msubwhfmr, mul64)
453 (negs, negsh, normacc, qmachf, qmpyh, qmpyhf, rndh, satf, sath)
454 (sbcs, setacc, sflag, sqrt, sqrtf, subs, swi_s, vabs2h, vabss2h)
455 (vadd4b, vadds2, vadds2h, vadds4h, vaddsubs, vaddsubs2h)
456 (vaddsubs4h, valgn2h, vasl2h, vasls2h, vasr2h, vasrs2h, vasrsr2h)
457 (vext2bhl, vext2bhlf, vext2bhm, vext2bhmf, vlsr2h, vmac2hf)
458 (vmac2hfr, vmac2hnfr, vmax2h, vmin2h, vmpy2h, vmpy2hf, vmpy2hfr)
459 (vmpy2hwf, vmsub2hf, vmsub2hfr, vmsub2hnfr, vneg2h, vnegs2h)
460 (vnorm2h, vpack2hbl, vpack2hblf, vpack2hbm, vpack2hbmf, vpack2hl)
461 (vpack2hm, vperm, vrep2hl, vrep2hm, vsext2bhl, vsext2bhm, vsub4b)
462 (vsubadds, vsubadds2h, vsubadds4h, vsubs2, vsubs2h, vsubs4h):
463 Changed opcodes.
464 (prealloc, prefetch*): Place them before ld instruction.
465 * arc-opc.c (skip_this_opcode): Add ARITH class.
467 2017-10-25 Alan Modra <amodra@gmail.com>
469 PR 22348
470 * cr16-dis.c (cr16_cinvs, instruction, cr16_currInsn): Make static.
471 (cr16_words, cr16_allWords, processing_argument_number): Likewise.
472 (imm4flag, size_changed): Likewise.
473 * crx-dis.c (crx_cinvs, NUMCINVS, instruction, currInsn): Likewise.
474 (words, allWords, processing_argument_number): Likewise.
475 (cst4flag, size_changed): Likewise.
476 * crx-opc.c (crx_cst4_map): Rename from cst4_map.
477 (crx_cst4_maps): Rename from cst4_maps.
478 (crx_no_op_insn): Rename from no_op_insn.
480 2017-10-24 Andrew Waterman <andrew@sifive.com>
482 * riscv-opc.c (match_c_addi16sp) : New function.
483 (match_c_addi4spn): New function.
484 (match_c_lui): Don't allow 0-immediate encodings.
485 (riscv_opcodes) <addi>: Use the above functions.
486 <add>: Likewise.
487 <c.addi4spn>: Likewise.
488 <c.addi16sp>: Likewise.
490 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
492 * i386-init.h: Regenerate
493 * i386-tbl.h: Likewise
495 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
497 * i386-dis.c (enum): Add PREFIX_EVEX_0F3854, PREFIX_EVEX_0F388F.
498 (enum): Add EVEX_W_0F3854_P_2.
499 * i386-dis-evex.h (evex_table): Updated.
500 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_BITALG,
501 CPU_ANY_AVX512_BITALG_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
502 (cpu_flags): Add CpuAVX512_BITALG.
503 * i386-opc.h (enum): Add CpuAVX512_BITALG.
504 (i386_cpu_flags): Add cpuavx512_bitalg..
505 * i386-opc.tbl: Add Intel AVX512_BITALG instructions.
506 * i386-init.h: Regenerate.
507 * i386-tbl.h: Likewise.
509 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
511 * i386-dis.c (enum): Add PREFIX_EVEX_0F3850, PREFIX_EVEX_0F3851.
512 * i386-dis-evex.h (evex_table): Updated.
513 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VNNI,
514 CPU_ANY_AVX512_VNNI_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
515 (cpu_flags): Add CpuAVX512_VNNI.
516 * i386-opc.h (enum): Add CpuAVX512_VNNI.
517 (i386_cpu_flags): Add cpuavx512_vnni.
518 * i386-opc.tbl Add Intel AVX512_VNNI instructions.
519 * i386-init.h: Regenerate.
520 * i386-tbl.h: Likewise.
522 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
524 * i386-dis.c (enum): Add PREFIX_EVEX_0F3A44.
525 (enum): Remove VEX_LEN_0F3A44_P_2.
526 (vex_len_table): Ditto.
527 (enum): Remove VEX_W_0F3A44_P_2.
528 (vew_w_table): Ditto.
529 (prefix_table): Adjust instructions (see prefixes above).
530 * i386-dis-evex.h (evex_table):
531 Add new instructions (see prefixes above).
532 * i386-gen.c (cpu_flag_init): Add VPCLMULQDQ.
533 (bitfield_cpu_flags): Ditto.
534 * i386-opc.h (enum): Ditto.
535 (i386_cpu_flags): Ditto.
536 (CpuUnused): Comment out to avoid zero-width field problem.
537 * i386-opc.tbl (vpclmulqdq): New instruction.
538 * i386-init.h: Regenerate.
539 * i386-tbl.h: Ditto.
541 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
543 * i386-dis.c (enum): Add PREFIX_EVEX_0F38DC, PREFIX_EVEX_0F38DD,
544 PREFIX_EVEX_0F38DE, PREFIX_EVEX_0F38DF.
545 (enum): Remove VEX_LEN_0F38DC_P_2, VEX_LEN_0F38DD_P_2,
546 VEX_LEN_0F38DE_P_2, VEX_LEN_0F38DF_P_2.
547 (vex_len_table): Ditto.
548 (enum): Remove VEX_W_0F38DC_P_2, VEX_W_0F38DD_P_2,
549 VEX_W_0F38DE_P_2, VEX_W_0F38DF_P_2.
550 (vew_w_table): Ditto.
551 (prefix_table): Adjust instructions (see prefixes above).
552 * i386-dis-evex.h (evex_table):
553 Add new instructions (see prefixes above).
554 * i386-gen.c (cpu_flag_init): Add VAES.
555 (bitfield_cpu_flags): Ditto.
556 * i386-opc.h (enum): Ditto.
557 (i386_cpu_flags): Ditto.
558 * i386-opc.tbl (vaes{enc,dec}{last,}): New instructions.
559 * i386-init.h: Regenerate.
560 * i386-tbl.h: Ditto.
562 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
564 * i386-dis.c (enum): Add PREFIX_0F38CF, PREFIX_0F3ACE, PREFIX_0F3ACF,
565 PREFIX_VEX_0F38CF, PREFIX_VEX_0F3ACE, PREFIX_VEX_0F3ACF,
566 PREFIX_EVEX_0F38CF, PREFIX_EVEX_0F3ACE, PREFIX_EVEX_0F3ACF.
567 (enum): Add VEX_W_0F38CF_P_2, VEX_W_0F3ACE_P_2, VEX_W_0F3ACF_P_2,
568 EVEX_W_0F3ACE_P_2, EVEX_W_0F3ACF_P_2.
569 (prefix_table): Updated (see prefixes above).
570 (three_byte_table): Likewise.
571 (vex_w_table): Likewise.
572 * i386-dis-evex.h: Likewise.
573 * i386-gen.c (cpu_flag_init): Add CPU_GFNI_FLAGS, CpuGFNI.
574 (cpu_flags): Add CpuGFNI.
575 * i386-opc.h (enum): Add CpuGFNI.
576 (i386_cpu_flags): Add cpugfni.
577 * i386-opc.tbl: Add Intel GFNI instructions.
578 * i386-init.h: Regenerate.
579 * i386-tbl.h: Likewise.
581 2017-10-23 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
583 * i386-dis.c (enum): Add b_scalar_mode, w_scalar_mode.
584 Define EXbScalar and EXwScalar for OP_EX.
585 (enum): Add PREFIX_EVEX_0F3862, PREFIX_EVEX_0F3863,
586 PREFIX_EVEX_0F3870, PREFIX_EVEX_0F3871, PREFIX_EVEX_0F3872,
587 PREFIX_EVEX_0F3873, PREFIX_EVEX_0F3A70, PREFIX_EVEX_0F3A71,
588 PREFIX_EVEX_0F3A72, PREFIX_EVEX_0F3A73.
589 (enum): Add EVEX_W_0F3862_P_2, EVEX_W_0F3863_P_2,
590 EVEX_W_0F3870_P_2, EVEX_W_0F3871_P_2, EVEX_W_0F3872_P_2,
591 EVEX_W_0F3873_P_2, EVEX_W_0F3A70_P_2, EVEX_W_0F3A71_P_2,
592 EVEX_W_0F3A72_P_2, EVEX_W_0F3A73_P_2.
593 (intel_operand_size): Handle b_scalar_mode and w_scalar_mode.
594 (OP_E_memory): Likewise.
595 * i386-dis-evex.h: Updated.
596 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VBMI2,
597 CPU_ANY_AVX512_VBMI2_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
598 (cpu_flags): Add CpuAVX512_VBMI2.
599 * i386-opc.h (enum): Add CpuAVX512_VBMI2.
600 (i386_cpu_flags): Add cpuavx512_vbmi2.
601 * i386-opc.tbl: Add Intel AVX512_VBMI2 instructions.
602 * i386-init.h: Regenerate.
603 * i386-tbl.h: Likewise.
605 2017-10-18 Eric Botcazou <ebotcazou@adacore.com>
607 * visium-dis.c (disassem_class1) <case 0>: Print the operands.
609 2017-10-12 James Bowman <james.bowman@ftdichip.com>
611 * ft32-dis.c (print_insn_ft32): Replace FT32_FLD_K8 with K15.
612 * ft32-opc.c (ft32_opc_info): Replace FT32_FLD_K8 with
613 K15. Add jmpix pattern.
615 2017-10-09 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
617 * s390-opc.txt (prno, tpei, irbm): New instructions added.
619 2017-10-09 Heiko Carstens <heiko.carstens@de.ibm.com>
621 * s390-opc.c (INSTR_SI_RD): New macro.
622 (INSTR_S_RD): Adjust example instruction.
623 * s390-opc.txt (lpsw, ssm, ts): Change S_RD instruction format to
624 SI_RD.
626 2017-10-01 Alexander Fedotov <alfedotov@gmail.com>
628 * ppc-opc.c (vle_opcodes): Add e_lmvsprw, e_lmvgprw,
629 e_lmvsrrw, e_lmvcsrrw and e_lmvcsrrw as official mnemonics for
630 VLE multimple load/store instructions. Old e_ldm* variants are
631 kept as aliases.
632 Add missing e_lmvmcsrrw and e_stmvmcsrrw.
634 2017-09-27 Nick Clifton <nickc@redhat.com>
636 PR 22179
637 * riscv-opc.c (riscv_opcodes): Add fmv.x.w and fmv.w.x as the new
638 names for the fmv.x.s and fmv.s.x instructions respectively.
640 2017-09-26 do <do@nerilex.org>
642 PR 22123
643 * m68k-opc.c (m68k_opcodes): Allow macw and macl instructions to
644 be used on CPUs that have emacs support.
646 2017-09-21 Sergio Durigan Junior <sergiodj@redhat.com>
648 * aarch64-opc.c (expand_fp_imm): Initialize 'imm'.
650 2017-09-09 Kamil Rytarowski <n54@gmx.com>
652 * nds32-asm.c: Rename __BIT() to N32_BIT().
653 * nds32-asm.h: Likewise.
654 * nds32-dis.c: Likewise.
656 2017-09-09 H.J. Lu <hongjiu.lu@intel.com>
658 * i386-dis.c (last_active_prefix): Removed.
659 (ckprefix): Don't set last_active_prefix.
660 (NOTRACK_Fixup): Don't check last_active_prefix.
662 2017-08-31 Nick Clifton <nickc@redhat.com>
664 * po/fr.po: Updated French translation.
666 2017-08-31 James Bowman <james.bowman@ftdichip.com>
668 * ft32-dis.c (print_insn_ft32): Correct display of non-address
669 fields.
671 2017-08-23 Alexander Fedotov <alexander.fedotov@nxp.com>
672 Edmar Wienskoski <edmar.wienskoski@nxp.com>
674 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_SPE2 and
675 PPC_OPCODE_EFS2 flag to "e200z4" entry.
676 New entries efs2 and spe2.
677 Add PPC_OPCODE_SPE2 and PPC_OPCODE_EFS2 flag to "vle" entry.
678 (SPE2_OPCD_SEGS): New macro.
679 (spe2_opcd_indices): New.
680 (disassemble_init_powerpc): Handle SPE2 opcodes.
681 (lookup_spe2): New function.
682 (print_insn_powerpc): call lookup_spe2.
683 * ppc-opc.c (insert_evuimm1_ex0): New function.
684 (extract_evuimm1_ex0): Likewise.
685 (insert_evuimm_lt8): Likewise.
686 (extract_evuimm_lt8): Likewise.
687 (insert_off_spe2): Likewise.
688 (extract_off_spe2): Likewise.
689 (insert_Ddd): Likewise.
690 (extract_Ddd): Likewise.
691 (DD): New operand.
692 (EVUIMM_LT8): Likewise.
693 (EVUIMM_LT16): Adjust.
694 (MMMM): New operand.
695 (EVUIMM_1): Likewise.
696 (EVUIMM_1_EX0): Likewise.
697 (EVUIMM_2): Adjust.
698 (NNN): New operand.
699 (VX_OFF_SPE2): Likewise.
700 (BBB): Likewise.
701 (DDD): Likewise.
702 (VX_MASK_DDD): New mask.
703 (HH): New operand.
704 (VX_RA_CONST): New macro.
705 (VX_RA_CONST_MASK): Likewise.
706 (VX_RB_CONST): Likewise.
707 (VX_RB_CONST_MASK): Likewise.
708 (VX_OFF_SPE2_MASK): Likewise.
709 (VX_SPE_CRFD): Likewise.
710 (VX_SPE_CRFD_MASK VX): Likewise.
711 (VX_SPE2_CLR): Likewise.
712 (VX_SPE2_CLR_MASK): Likewise.
713 (VX_SPE2_SPLATB): Likewise.
714 (VX_SPE2_SPLATB_MASK): Likewise.
715 (VX_SPE2_OCTET): Likewise.
716 (VX_SPE2_OCTET_MASK): Likewise.
717 (VX_SPE2_DDHH): Likewise.
718 (VX_SPE2_DDHH_MASK): Likewise.
719 (VX_SPE2_HH): Likewise.
720 (VX_SPE2_HH_MASK): Likewise.
721 (VX_SPE2_EVMAR): Likewise.
722 (VX_SPE2_EVMAR_MASK): Likewise.
723 (PPCSPE2): Likewise.
724 (PPCEFS2): Likewise.
725 (vle_opcodes): Add EFS2 and some missing SPE opcodes.
726 (powerpc_macros): Map old SPE instructions have new names
727 with the same opcodes. Add SPE2 instructions which just are
728 mapped to SPE2.
729 (spe2_opcodes): Add SPE2 opcodes.
731 2017-08-23 Alan Modra <amodra@gmail.com>
733 * ppc-opc.c: Formatting and comment fixes. Move insert and
734 extract functions earlier, deleting forward declarations.
735 (insert_nbi, insert_raq, insert_rbx): Expand use of RT_MASK and
736 RA_MASK.
738 2017-08-22 Palmer Dabbelt <palmer@dabbelt.com>
740 * riscv-opc.c (riscv_opcodes): Mark "c.nop" as an alias.
742 2017-08-21 Alexander Fedotov <alexander.fedotov@nxp.com>
743 Edmar Wienskoski <edmar.wienskoski@nxp.com>
745 * ppc-opc.c (insert_evuimm2_ex0): New function.
746 (extract_evuimm2_ex0): Likewise.
747 (insert_evuimm4_ex0): Likewise.
748 (extract_evuimm4_ex0): Likewise.
749 (insert_evuimm8_ex0): Likewise.
750 (extract_evuimm8_ex0): Likewise.
751 (insert_evuimm_lt16): Likewise.
752 (extract_evuimm_lt16): Likewise.
753 (insert_rD_rS_even): Likewise.
754 (extract_rD_rS_even): Likewise.
755 (insert_off_lsp): Likewise.
756 (extract_off_lsp): Likewise.
757 (RD_EVEN): New operand.
758 (RS_EVEN): Likewise.
759 (RSQ): Adjust.
760 (EVUIMM_LT16): New operand.
761 (HTM_SI): Adjust.
762 (EVUIMM_2_EX0): New operand.
763 (EVUIMM_4): Adjust.
764 (EVUIMM_4_EX0): New operand.
765 (EVUIMM_8): Adjust.
766 (EVUIMM_8_EX0): New operand.
767 (WS): Adjust.
768 (VX_OFF): New operand.
769 (VX_LSP): New macro.
770 (VX_LSP_MASK): Likewise.
771 (VX_LSP_OFF_MASK): Likewise.
772 (PPC_OPCODE_LSP): Likewise.
773 (vle_opcodes): Add LSP opcodes.
774 * ppc-dis.c (ppc_mopt): Add PPC_OPCODE_LSP flag to "vle" entry.
776 2017-08-09 Jiong Wang <jiong.wang@arm.com>
778 * arm-dis.c (thumb32_opcodes): Use format 'R' instead of 'S' for
779 register operands in CRC instructions.
780 (print_insn_thumb32): Remove "<bitfield>S" support. Updated the
781 comments.
783 2017-08-07 H.J. Lu <hongjiu.lu@intel.com>
785 * disassemble.c (disassembler): Mark big and mach with
786 ATTRIBUTE_UNUSED.
788 2017-08-07 Maciej W. Rozycki <macro@imgtec.com>
790 * disassemble.c (disassembler): Remove arch/mach/endian
791 assertions.
793 2017-07-25 Nick Clifton <nickc@redhat.com>
795 PR 21739
796 * arc-opc.c (insert_rhv2): Use lower case first letter in error
797 message.
798 (insert_r0): Likewise.
799 (insert_r1): Likewise.
800 (insert_r2): Likewise.
801 (insert_r3): Likewise.
802 (insert_sp): Likewise.
803 (insert_gp): Likewise.
804 (insert_pcl): Likewise.
805 (insert_blink): Likewise.
806 (insert_ilink1): Likewise.
807 (insert_ilink2): Likewise.
808 (insert_ras): Likewise.
809 (insert_rbs): Likewise.
810 (insert_rcs): Likewise.
811 (insert_simm3s): Likewise.
812 (insert_rrange): Likewise.
813 (insert_r13el): Likewise.
814 (insert_fpel): Likewise.
815 (insert_blinkel): Likewise.
816 (insert_pclel): Likewise.
817 (insert_nps_bitop_size_2b): Likewise.
818 (insert_nps_imm_offset): Likewise.
819 (insert_nps_imm_entry): Likewise.
820 (insert_nps_size_16bit): Likewise.
821 (insert_nps_##NAME##_pos): Likewise.
822 (insert_nps_##NAME): Likewise.
823 (insert_nps_bitop_ins_ext): Likewise.
824 (insert_nps_##NAME): Likewise.
825 (insert_nps_min_hofs): Likewise.
826 (insert_nps_##NAME): Likewise.
827 (insert_nps_rbdouble_64): Likewise.
828 (insert_nps_misc_imm_offset): Likewise.
829 * riscv-dis.c (print_riscv_disassembler_options): Fix typo in
830 option description.
832 2017-07-24 Laurent Desnogues <laurent.desnogues@arm.com>
833 Jiong Wang <jiong.wang@arm.com>
835 * aarch64-gen.c (print_decision_tree_1): Reverse the index of PATTERN to
836 correct the print.
837 * aarch64-dis-2.c: Regenerated.
839 2017-07-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
841 * s390-mkopc.c (main): Enable z14 as CPU string in the opcode
842 table.
844 2017-07-20 Nick Clifton <nickc@redhat.com>
846 * po/de.po: Updated German translation.
848 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
850 * arc-regs.h (sec_stat): New aux register.
851 (aux_kernel_sp): Likewise.
852 (aux_sec_u_sp): Likewise.
853 (aux_sec_k_sp): Likewise.
854 (sec_vecbase_build): Likewise.
855 (nsc_table_top): Likewise.
856 (nsc_table_base): Likewise.
857 (ersec_stat): Likewise.
858 (aux_sec_except): Likewise.
860 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
862 * arc-opc.c (extract_uimm12_20): New function.
863 (UIMM12_20): New operand.
864 (SIMM3_5_S): Adjust.
865 * arc-tbl.h (sjli): Add new instruction.
867 2017-07-19 Claudiu Zissulescu <claziss@synopsys.com>
868 John Eric Martin <John.Martin@emmicro-us.com>
870 * arc-opc.c (UIMM10_6_S_JLIOFF): Define.
871 (UIMM3_23): Adjust accordingly.
872 * arc-regs.h: Add/correct jli_base register.
873 * arc-tbl.h (jli_s): Likewise.
875 2017-07-18 Nick Clifton <nickc@redhat.com>
877 PR 21775
878 * aarch64-opc.c: Fix spelling typos.
879 * i386-dis.c: Likewise.
881 2017-07-14 Ravi Bangoria <ravi.bangoria@linux.vnet.ibm.com>
883 * dis-buf.c (buffer_read_memory): Change type of end_addr_offset,
884 max_addr_offset and octets variables to size_t.
886 2017-07-12 Alan Modra <amodra@gmail.com>
888 * po/da.po: Update from translationproject.org/latest/opcodes/.
889 * po/de.po: Likewise.
890 * po/es.po: Likewise.
891 * po/fi.po: Likewise.
892 * po/fr.po: Likewise.
893 * po/id.po: Likewise.
894 * po/it.po: Likewise.
895 * po/nl.po: Likewise.
896 * po/pt_BR.po: Likewise.
897 * po/ro.po: Likewise.
898 * po/sv.po: Likewise.
899 * po/tr.po: Likewise.
900 * po/uk.po: Likewise.
901 * po/vi.po: Likewise.
902 * po/zh_CN.po: Likewise.
904 2017-07-11 Yao Qi <yao.qi@linaro.org>
905 Alan Modra <amodra@gmail.com>
907 * cgen.sh: Mark generated files read-only.
908 * epiphany-asm.c: Regenerate.
909 * epiphany-desc.c: Regenerate.
910 * epiphany-desc.h: Regenerate.
911 * epiphany-dis.c: Regenerate.
912 * epiphany-ibld.c: Regenerate.
913 * epiphany-opc.c: Regenerate.
914 * epiphany-opc.h: Regenerate.
915 * fr30-asm.c: Regenerate.
916 * fr30-desc.c: Regenerate.
917 * fr30-desc.h: Regenerate.
918 * fr30-dis.c: Regenerate.
919 * fr30-ibld.c: Regenerate.
920 * fr30-opc.c: Regenerate.
921 * fr30-opc.h: Regenerate.
922 * frv-asm.c: Regenerate.
923 * frv-desc.c: Regenerate.
924 * frv-desc.h: Regenerate.
925 * frv-dis.c: Regenerate.
926 * frv-ibld.c: Regenerate.
927 * frv-opc.c: Regenerate.
928 * frv-opc.h: Regenerate.
929 * ip2k-asm.c: Regenerate.
930 * ip2k-desc.c: Regenerate.
931 * ip2k-desc.h: Regenerate.
932 * ip2k-dis.c: Regenerate.
933 * ip2k-ibld.c: Regenerate.
934 * ip2k-opc.c: Regenerate.
935 * ip2k-opc.h: Regenerate.
936 * iq2000-asm.c: Regenerate.
937 * iq2000-desc.c: Regenerate.
938 * iq2000-desc.h: Regenerate.
939 * iq2000-dis.c: Regenerate.
940 * iq2000-ibld.c: Regenerate.
941 * iq2000-opc.c: Regenerate.
942 * iq2000-opc.h: Regenerate.
943 * lm32-asm.c: Regenerate.
944 * lm32-desc.c: Regenerate.
945 * lm32-desc.h: Regenerate.
946 * lm32-dis.c: Regenerate.
947 * lm32-ibld.c: Regenerate.
948 * lm32-opc.c: Regenerate.
949 * lm32-opc.h: Regenerate.
950 * lm32-opinst.c: Regenerate.
951 * m32c-asm.c: Regenerate.
952 * m32c-desc.c: Regenerate.
953 * m32c-desc.h: Regenerate.
954 * m32c-dis.c: Regenerate.
955 * m32c-ibld.c: Regenerate.
956 * m32c-opc.c: Regenerate.
957 * m32c-opc.h: Regenerate.
958 * m32r-asm.c: Regenerate.
959 * m32r-desc.c: Regenerate.
960 * m32r-desc.h: Regenerate.
961 * m32r-dis.c: Regenerate.
962 * m32r-ibld.c: Regenerate.
963 * m32r-opc.c: Regenerate.
964 * m32r-opc.h: Regenerate.
965 * m32r-opinst.c: Regenerate.
966 * mep-asm.c: Regenerate.
967 * mep-desc.c: Regenerate.
968 * mep-desc.h: Regenerate.
969 * mep-dis.c: Regenerate.
970 * mep-ibld.c: Regenerate.
971 * mep-opc.c: Regenerate.
972 * mep-opc.h: Regenerate.
973 * mt-asm.c: Regenerate.
974 * mt-desc.c: Regenerate.
975 * mt-desc.h: Regenerate.
976 * mt-dis.c: Regenerate.
977 * mt-ibld.c: Regenerate.
978 * mt-opc.c: Regenerate.
979 * mt-opc.h: Regenerate.
980 * or1k-asm.c: Regenerate.
981 * or1k-desc.c: Regenerate.
982 * or1k-desc.h: Regenerate.
983 * or1k-dis.c: Regenerate.
984 * or1k-ibld.c: Regenerate.
985 * or1k-opc.c: Regenerate.
986 * or1k-opc.h: Regenerate.
987 * or1k-opinst.c: Regenerate.
988 * xc16x-asm.c: Regenerate.
989 * xc16x-desc.c: Regenerate.
990 * xc16x-desc.h: Regenerate.
991 * xc16x-dis.c: Regenerate.
992 * xc16x-ibld.c: Regenerate.
993 * xc16x-opc.c: Regenerate.
994 * xc16x-opc.h: Regenerate.
995 * xstormy16-asm.c: Regenerate.
996 * xstormy16-desc.c: Regenerate.
997 * xstormy16-desc.h: Regenerate.
998 * xstormy16-dis.c: Regenerate.
999 * xstormy16-ibld.c: Regenerate.
1000 * xstormy16-opc.c: Regenerate.
1001 * xstormy16-opc.h: Regenerate.
1003 2017-07-07 Alan Modra <amodra@gmail.com>
1005 * cgen-dis.in: Include disassemble.h, not dis-asm.h.
1006 * m32c-dis.c: Regenerate.
1007 * mep-dis.c: Regenerate.
1009 2017-07-05 Borislav Petkov <bp@suse.de>
1011 * i386-dis.c: Enable ModRM.reg /6 aliases.
1013 2017-07-04 Ramana Radhakrishnan <ramana.radhakrishnan@arm.com>
1015 * opcodes/arm-dis.c: Support MVFR2 in disassembly
1016 with vmrs and vmsr.
1018 2017-07-04 Tristan Gingold <gingold@adacore.com>
1020 * configure: Regenerate.
1022 2017-07-03 Tristan Gingold <gingold@adacore.com>
1024 * po/opcodes.pot: Regenerate.
1026 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
1028 * mips-opc.c (mips_builtin_opcodes): Move "lsa" and "dlsa"
1029 entries to the MSA ASE instruction block.
1031 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
1032 Maciej W. Rozycki <macro@imgtec.com>
1034 * micromips-opc.c (XPA, XPAVZ): New macros.
1035 (micromips_opcodes): Add "mfhc0", "mfhgc0", "mthc0" and
1036 "mthgc0".
1038 2017-06-30 Andrew Bennett <andrew.bennett@imgtec.com>
1039 Maciej W. Rozycki <macro@imgtec.com>
1041 * micromips-opc.c (I36): New macro.
1042 (micromips_opcodes): Add "eretnc".
1044 2017-06-30 Maciej W. Rozycki <macro@imgtec.com>
1045 Andrew Bennett <andrew.bennett@imgtec.com>
1047 * mips-dis.c (mips_calculate_combination_ases): Handle the
1048 ASE_XPA_VIRT flag.
1049 (parse_mips_ase_option): New function.
1050 (parse_mips_dis_option): Factor out ASE option handling to the
1051 new function. Call `mips_calculate_combination_ases'.
1052 * mips-opc.c (XPAVZ): New macro.
1053 (mips_builtin_opcodes): Correct ISA and ASE flags for "mfhc0",
1054 "mfhgc0", "mthc0" and "mthgc0".
1056 2017-06-29 Maciej W. Rozycki <macro@imgtec.com>
1058 * mips-dis.c (mips_calculate_combination_ases): New function.
1059 (mips_convert_abiflags_ases): Factor out ASE_MIPS16E2_MT
1060 calculation to the new function.
1061 (set_default_mips_dis_options): Call the new function.
1063 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1065 * arc-dis.c (parse_disassembler_options): Use
1066 FOR_EACH_DISASSEMBLER_OPTION.
1068 2017-06-29 Anton Kolesov <Anton.Kolesov@synopsys.com>
1070 * arc-dis.c (parse_option): Use disassembler_options_cmp to compare
1071 disassembler option strings.
1072 (parse_cpu_option): Likewise.
1074 2017-06-28 Tamar Christina <tamar.christina@arm.com>
1076 * aarch64-asm.c (aarch64_ins_reglane): Added 4B dotprod.
1077 * aarch64-dis.c (aarch64_ext_reglane): Likewise.
1078 * aarch64-tbl.h (QL_V3DOT, QL_V2DOT): New.
1079 (aarch64_feature_dotprod, DOT_INSN): New.
1080 (udot, sdot): New.
1081 * aarch64-dis-2.c: Regenerated.
1083 2017-06-28 Jiong Wang <jiong.wang@arm.com>
1085 * arm-dis.c (coprocessor_opcodes): New entries for vsdot and vudot.
1087 2017-06-28 Maciej W. Rozycki <macro@imgtec.com>
1088 Matthew Fortune <matthew.fortune@imgtec.com>
1089 Andrew Bennett <andrew.bennett@imgtec.com>
1091 * mips-formats.h (INT_BIAS): New macro.
1092 (INT_ADJ): Redefine in INT_BIAS terms.
1093 * mips-dis.c (mips_arch_choices): Add "interaptiv-mr2" entry.
1094 (mips_print_save_restore): New function.
1095 (print_insn_arg) <OP_SAVE_RESTORE_LIST>: Update comment.
1096 (validate_insn_args) <OP_SAVE_RESTORE_LIST>: Remove `abort'
1097 call.
1098 (print_insn_args): Handle OP_SAVE_RESTORE_LIST.
1099 (print_mips16_insn_arg): Call `mips_print_save_restore' for
1100 OP_SAVE_RESTORE_LIST handling, factored out from here.
1101 * mips-opc.c (decode_mips_operand) <'-'> <'m'>: New case.
1102 (RD_31, RD_SP, WR_SP, MOD_SP, IAMR2): New macros.
1103 (mips_builtin_opcodes): Add "restore" and "save" entries.
1104 * mips16-opc.c (decode_mips16_operand) <'n', 'o'>: New cases.
1105 (IAMR2): New macro.
1106 (mips16_opcodes): Add "copyw" and "ucopyw" entries.
1108 2017-06-23 Andrew Waterman <andrew@sifive.com>
1110 * riscv-opc.c (riscv_opcodes): Mark I-type SLT instruction as an
1111 alias; do not mark SLTI instruction as an alias.
1113 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1115 * i386-dis.c (RM_0FAE_REG_5): Removed.
1116 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1117 (PREFIX_MOD_3_0F01_REG_5_RM_0): New.
1118 (PREFIX_MOD_3_0FAE_REG_5): Likewise.
1119 (prefix_table): Remove PREFIX_MOD_3_0F01_REG_5_RM_1. Add
1120 PREFIX_MOD_3_0F01_REG_5_RM_0.
1121 (prefix_table): Update PREFIX_MOD_0_0FAE_REG_5. Add
1122 PREFIX_MOD_3_0FAE_REG_5.
1123 (mod_table): Update MOD_0FAE_REG_5.
1124 (rm_table): Update RM_0F01_REG_5. Remove RM_0FAE_REG_5.
1125 * i386-opc.tbl: Update incsspd, incsspq and setssbsy.
1126 * i386-tbl.h: Regenerated.
1128 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1130 * i386-dis.c (prefix_table): Replace savessp with saveprevssp.
1131 * i386-opc.tbl: Likewise.
1132 * i386-tbl.h: Regenerated.
1134 2017-06-21 H.J. Lu <hongjiu.lu@intel.com>
1136 * i386-dis.c (reg_table): Swap indirEv with NOTRACK on "call{&|}"
1137 and "jmp{&|}".
1138 (NOTRACK_Fixup): Support memory indirect branch with NOTRACK
1139 prefix.
1141 2017-06-19 Nick Clifton <nickc@redhat.com>
1143 PR binutils/21614
1144 * score-dis.c (score_opcodes): Add sentinel.
1146 2017-06-16 Alan Modra <amodra@gmail.com>
1148 * rx-decode.c: Regenerate.
1150 2017-06-15 H.J. Lu <hongjiu.lu@intel.com>
1152 PR binutils/21594
1153 * i386-dis.c (OP_E_register): Check valid bnd register.
1154 (OP_G): Likewise.
1156 2017-06-15 Nick Clifton <nickc@redhat.com>
1158 PR binutils/21595
1159 * aarch64-dis.c (aarch64_ext_ldst_reglist): Check for an out of
1160 range value.
1162 2017-06-15 Nick Clifton <nickc@redhat.com>
1164 PR binutils/21588
1165 * rl78-decode.opc (OP_BUF_LEN): Define.
1166 (GETBYTE): Check for the index exceeding OP_BUF_LEN.
1167 (rl78_decode_opcode): Use OP_BUF_LEN as the length of the op_buf
1168 array.
1169 * rl78-decode.c: Regenerate.
1171 2017-06-15 Nick Clifton <nickc@redhat.com>
1173 PR binutils/21586
1174 * bfin-dis.c (gregs): Clip index to prevent overflow.
1175 (regs): Likewise.
1176 (regs_lo): Likewise.
1177 (regs_hi): Likewise.
1179 2017-06-14 Nick Clifton <nickc@redhat.com>
1181 PR binutils/21576
1182 * score7-dis.c (score_opcodes): Add sentinel.
1184 2017-06-14 Yao Qi <yao.qi@linaro.org>
1186 * aarch64-dis.c: Include disassemble.h instead of dis-asm.h.
1187 * arm-dis.c: Likewise.
1188 * ia64-dis.c: Likewise.
1189 * mips-dis.c: Likewise.
1190 * spu-dis.c: Likewise.
1191 * disassemble.h (print_insn_aarch64): New declaration, moved from
1192 include/dis-asm.h.
1193 (print_insn_big_arm, print_insn_big_mips): Likewise.
1194 (print_insn_i386, print_insn_ia64): Likewise.
1195 (print_insn_little_arm, print_insn_little_mips): Likewise.
1197 2017-06-14 Nick Clifton <nickc@redhat.com>
1199 PR binutils/21587
1200 * rx-decode.opc: Include libiberty.h
1201 (GET_SCALE): New macro - validates access to SCALE array.
1202 (GET_PSCALE): New macro - validates access to PSCALE array.
1203 (DIs, SIs, S2Is, rx_disp): Use new macros.
1204 * rx-decode.c: Regenerate.
1206 2017-07-14 Andre Vieira <andre.simoesdiasvieira@arm.com>
1208 * arm-dis.c (print_insn_arm): Remove bogus entry for bx.
1210 2017-05-30 Anton Kolesov <anton.kolesov@synopsys.com>
1212 * arc-dis.c (enforced_isa_mask): Declare.
1213 (cpu_types): Likewise.
1214 (parse_cpu_option): New function.
1215 (parse_disassembler_options): Use it.
1216 (print_insn_arc): Use enforced_isa_mask.
1217 (print_arc_disassembler_options): Document new options.
1219 2017-05-24 Yao Qi <yao.qi@linaro.org>
1221 * alpha-dis.c: Include disassemble.h, don't include
1222 dis-asm.h.
1223 * avr-dis.c, bfin-dis.c, cr16-dis.c: Likewise.
1224 * crx-dis.c, d10v-dis.c, d30v-dis.c: Likewise.
1225 * disassemble.c, dlx-dis.c, epiphany-dis.c: Likewise.
1226 * fr30-dis.c, ft32-dis.c, h8300-dis.c, h8500-dis.c: Likewise.
1227 * hppa-dis.c, i370-dis.c, i386-dis.c: Likewise.
1228 * i860-dis.c, i960-dis.c, ip2k-dis.c: Likewise.
1229 * iq2000-dis.c, lm32-dis.c, m10200-dis.c: Likewise.
1230 * m10300-dis.c, m32r-dis.c, m68hc11-dis.c: Likewise.
1231 * m68k-dis.c, m88k-dis.c, mcore-dis.c: Likewise.
1232 * metag-dis.c, microblaze-dis.c, mmix-dis.c: Likewise.
1233 * moxie-dis.c, msp430-dis.c, mt-dis.c:
1234 * nds32-dis.c, nios2-dis.c, ns32k-dis.c: Likewise.
1235 * or1k-dis.c, pdp11-dis.c, pj-dis.c: Likewise.
1236 * ppc-dis.c, pru-dis.c, riscv-dis.c: Likewise.
1237 * rl78-dis.c, s390-dis.c, score-dis.c: Likewise.
1238 * sh-dis.c, sh64-dis.c, tic30-dis.c: Likewise.
1239 * tic4x-dis.c, tic54x-dis.c, tic6x-dis.c: Likewise.
1240 * tic80-dis.c, tilegx-dis.c, tilepro-dis.c: Likewise.
1241 * v850-dis.c, vax-dis.c, visium-dis.c: Likewise.
1242 * w65-dis.c, wasm32-dis.c, xc16x-dis.c: Likewise.
1243 * xgate-dis.c, xstormy16-dis.c, xtensa-dis.c: Likewise.
1244 * z80-dis.c, z8k-dis.c: Likewise.
1245 * disassemble.h: New file.
1247 2017-05-24 Yao Qi <yao.qi@linaro.org>
1249 * rl78-dis.c (rl78_get_disassembler): If parameter abfd
1250 is NULL, set cpu to E_FLAG_RL78_ANY_CPU.
1252 2017-05-24 Yao Qi <yao.qi@linaro.org>
1254 * disassemble.c (disassembler): Add arguments a, big and mach.
1255 Use them.
1257 2017-05-22 H.J. Lu <hongjiu.lu@intel.com>
1259 * i386-dis.c (NOTRACK_Fixup): New.
1260 (NOTRACK): Likewise.
1261 (NOTRACK_PREFIX): Likewise.
1262 (last_active_prefix): Likewise.
1263 (reg_table): Use NOTRACK on indirect call and jmp.
1264 (ckprefix): Set last_active_prefix.
1265 (prefix_name): Return "notrack" for NOTRACK_PREFIX.
1266 * i386-gen.c (opcode_modifiers): Add NoTrackPrefixOk.
1267 * i386-opc.h (NoTrackPrefixOk): New.
1268 (i386_opcode_modifier): Add notrackprefixok.
1269 * i386-opc.tbl: Add NoTrackPrefixOk to indirect call and jmp.
1270 Add notrack.
1271 * i386-tbl.h: Regenerated.
1273 2017-05-19 Jose E. Marchesi <jose.marchesi@oracle.com>
1275 * sparc-dis.c (MASK_V9): Include SPARC_OPCODE_ARCH_M8.
1276 (X_IMM2): Define.
1277 (compute_arch_mask): Handle bfd_mach_sparc_v8plusm8 and
1278 bfd_mach_sparc_v9m8.
1279 (print_insn_sparc): Handle new operand types.
1280 * sparc-opc.c (MASK_M8): Define.
1281 (v6): Add MASK_M8.
1282 (v6notlet): Likewise.
1283 (v7): Likewise.
1284 (v8): Likewise.
1285 (v9): Likewise.
1286 (v9a): Likewise.
1287 (v9b): Likewise.
1288 (v9c): Likewise.
1289 (v9d): Likewise.
1290 (v9e): Likewise.
1291 (v9v): Likewise.
1292 (v9m): Likewise.
1293 (v9andleon): Likewise.
1294 (m8): Define.
1295 (HWS_VM8): Define.
1296 (HWS2_VM8): Likewise.
1297 (sparc_opcode_archs): Add entry for "m8".
1298 (sparc_opcodes): Add OSA2017 and M8 instructions
1299 dictunpack, fpcmp{ule,ugt,eq,ne,de,ur}{8,16,32}shl,
1300 fpx{ll,ra,rl}64x,
1301 ldm{sh,uh,sw,uw,x,ux}, ldm{sh,uh,sw,uw,x,ux}a, ldmf{s,d},
1302 ldmf{s,d}a, on{add,sub,mul,div}, rdentropy, revbitsb,
1303 revbytes{h,w,x}, rle_burst, rle_length, sha3, stm{h,w,x},
1304 stm{h,w,x}a, stmf{s,d}, stmf{s,d}a.
1305 (asi_table): New M8 ASIs ASI_CORE_COMMIT_COUNT,
1306 ASI_CORE_SELECT_COUNT, ASI_ARF_ECC_REG, ASI_ITLB_PROBE, ASI_DSFAR,
1307 ASI_DTLB_PROBE_PRIMARY, ASI_DTLB_PROBE_REAL,
1308 ASI_CORE_SELECT_COMMIT_NHT.
1310 2017-05-18 Alan Modra <amodra@gmail.com>
1312 * aarch64-asm.c: Don't compare boolean values against TRUE or FALSE.
1313 * aarch64-dis.c: Likewise.
1314 * aarch64-gen.c: Likewise.
1315 * aarch64-opc.c: Likewise.
1317 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1318 Matthew Fortune <matthew.fortune@imgtec.com>
1320 * mips-dis.c (mips_arch_choices): Add ASE_MIPS16E2 and
1321 ASE_MIPS16E2_MT flags to the unnamed MIPS16 entry.
1322 (mips_convert_abiflags_ases): Handle the AFL_ASE_MIPS16E2 flag.
1323 (print_insn_arg) <OP_REG28>: Add handler.
1324 (validate_insn_args) <OP_REG28>: Handle.
1325 (print_mips16_insn_arg): Handle MIPS16 instructions that require
1326 32-bit encoding and 9-bit immediates.
1327 (print_insn_mips16): Handle MIPS16 instructions that require
1328 32-bit encoding and MFC0/MTC0 operand decoding.
1329 * mips16-opc.c (decode_mips16_operand) <'>', '9', 'G', 'N', 'O'>
1330 <'Q', 'T', 'b', 'c', 'd', 'r', 'u'>: Add handlers.
1331 (RD_C0, WR_C0, E2, E2MT): New macros.
1332 (mips16_opcodes): Add entries for MIPS16e2 instructions:
1333 GP-relative "addiu" and its "addu" spelling, "andi", "cache",
1334 "di", "ehb", "ei", "ext", "ins", GP-relative "lb", "lbu", "lh",
1335 "lhu", and "lw" instructions, "ll", "lui", "lwl", "lwr", "mfc0",
1336 "movn", "movtn", "movtz", "movz", "mtc0", "ori", "pause",
1337 "pref", "rdhwr", "sc", GP-relative "sb", "sh" and "sw"
1338 instructions, "swl", "swr", "sync" and its "sync_acquire",
1339 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" aliases,
1340 "xori", "dmt", "dvpe", "emt" and "evpe". Add split
1341 regular/extended entries for original MIPS16 ISA revision
1342 instructions whose extended forms are subdecoded in the MIPS16e2
1343 ISA revision: "li", "sll" and "srl".
1345 2017-05-15 Maciej W. Rozycki <macro@imgtec.com>
1347 * mips-dis.c (print_insn_args) <default>: Remove an MT ASE
1348 reference in CP0 move operand decoding.
1350 2017-05-12 Maciej W. Rozycki <macro@imgtec.com>
1352 * mips16-opc.c (decode_mips16_operand) <'6'>: Switch the operand
1353 type to hexadecimal.
1354 (mips16_opcodes): Add operandless "break" and "sdbbp" entries.
1356 2017-05-11 Maciej W. Rozycki <macro@imgtec.com>
1358 * mips-opc.c (mips_builtin_opcodes): Mark "synciobdma", "syncs",
1359 "syncw", "syncws", "sync_acquire", "sync_mb", "sync_release",
1360 "sync_rmb" and "sync_wmb" as aliases.
1361 * micromips-opc.c (micromips_opcodes): Mark "sync_acquire",
1362 "sync_mb", "sync_release", "sync_rmb" and "sync_wmb" as aliases.
1364 2017-05-10 Claudiu Zissulescu <claziss@synopsys.com>
1366 * arc-dis.c (parse_option): Update quarkse_em option..
1367 * arc-ext-tbl.h (dsp_fp_flt2i, dsp_fp_i2flt): Change subclass to
1368 QUARKSE1.
1369 (dsp_fp_div, dsp_fp_cmp): Change subclass to QUARKSE2.
1371 2017-05-03 Kito Cheng <kito.cheng@gmail.com>
1373 * riscv-dis.c (print_insn_args): Handle 'Co' operands.
1375 2017-05-01 Michael Clark <michaeljclark@mac.com>
1377 * riscv-opc.c (riscv_opcodes) <call>: Use RA not T1 as a temporary
1378 register.
1380 2017-05-02 Maciej W. Rozycki <macro@imgtec.com>
1382 * mips-dis.c (print_insn_arg): Only clear the ISA bit for jumps
1383 and branches and not synthetic data instructions.
1385 2017-05-02 Bernd Edlinger <bernd.edlinger@hotmail.de>
1387 * arm-dis.c (print_insn_thumb32): Fix value_in_comment.
1389 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1391 * arc-dis.c (print_insn_arc): Smartly print enter/leave mnemonics.
1392 * arc-opc.c (insert_r13el): New function.
1393 (R13_EL): Define.
1394 * arc-tbl.h: Add new enter/leave variants.
1396 2017-04-25 Claudiu Zissulescu <claziss@synopsys.com>
1398 * arc-tbl.h: Reorder NOP entry to be before MOV instructions.
1400 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1402 * mips-dis.c (print_mips_disassembler_options): Add
1403 `no-aliases'.
1405 2017-04-25 Maciej W. Rozycki <macro@imgtec.com>
1407 * mips16-opc.c (AL): New macro.
1408 (mips16_opcodes): Mark "nop", "la", "dla", and synthetic forms
1409 of "ld" and "lw" as aliases.
1411 2017-04-24 Tamar Christina <tamar.christina@arm.com>
1413 * aarch64-opc.c (aarch64_logical_immediate_p): Update DEBUG_TRACE
1414 arguments.
1416 2017-04-22 Alexander Fedotov <alfedotov@gmail.com>
1417 Alan Modra <amodra@gmail.com>
1419 * ppc-opc.c (ELEV): Define.
1420 (vle_opcodes): Add se_rfgi and e_sc.
1421 (powerpc_opcodes): Enable lbdx, lhdx, lwdx, stbdx, sthdx, stwdx
1422 for E200Z4.
1424 2017-04-21 Jose E. Marchesi <jose.marchesi@oracle.com>
1426 * sparc-opc.c (sparc_opcodes): Mark RETT instructions as v6notv9.
1428 2017-04-21 Nick Clifton <nickc@redhat.com>
1430 PR binutils/21380
1431 * aarch64-tbl.h (aarch64_opcode_table): Fix masks for LD1R, LD2R,
1432 LD3R and LD4R.
1434 2017-04-13 Alan Modra <amodra@gmail.com>
1436 * epiphany-desc.c: Regenerate.
1437 * fr30-desc.c: Regenerate.
1438 * frv-desc.c: Regenerate.
1439 * ip2k-desc.c: Regenerate.
1440 * iq2000-desc.c: Regenerate.
1441 * lm32-desc.c: Regenerate.
1442 * m32c-desc.c: Regenerate.
1443 * m32r-desc.c: Regenerate.
1444 * mep-desc.c: Regenerate.
1445 * mt-desc.c: Regenerate.
1446 * or1k-desc.c: Regenerate.
1447 * xc16x-desc.c: Regenerate.
1448 * xstormy16-desc.c: Regenerate.
1450 2017-04-11 Alan Modra <amodra@gmail.com>
1452 * ppc-dis.c (ppc_opts): Remove PPC_OPCODE_ALTIVEC2,
1453 PPC_OPCODE_VSX3, PPC_OPCODE_HTM and "htm". Formatting. Set
1454 PPC_OPCODE_TMR for e6500.
1455 * ppc-opc.c (PPCVEC2): Define as PPC_OPCODE_POWER8|PPC_OPCODE_E6500.
1456 (PPCVEC3): Define as PPC_OPCODE_POWER9.
1457 (PPCVSX2): Define as PPC_OPCODE_POWER8.
1458 (PPCVSX3): Define as PPC_OPCODE_POWER9.
1459 (PPCHTM): Define as PPC_OPCODE_POWER8.
1460 (powerpc_opcodes <mftmr, mttmr>): Remove now unnecessary E6500.
1462 2017-04-10 Alan Modra <amodra@gmail.com>
1464 * ppc-dis.c (ppc_opts <476>): Remove PPC_OPCODE_440.
1465 * ppc-opc.c (MULHW): Add PPC_OPCODE_476.
1466 (powerpc_opcodes): Adjust PPC440, PPC464 and PPC476 insns to suit
1467 removal of PPC_OPCODE_440 from ppc476 cpu selection bits.
1469 2017-04-09 Pip Cet <pipcet@gmail.com>
1471 * wasm32-dis.c (print_insn_wasm32): Avoid DECIMAL_DIG, specify
1472 appropriate floating-point precision directly.
1474 2017-04-07 Alan Modra <amodra@gmail.com>
1476 * ppc-opc.c (powerpc_opcodes <mviwsplt, mvidsplt, lvexbx, lvepxl,
1477 lvexhx, lvepx, lvexwx, stvexbx, stvexhx, stvexwx, lvtrx, lvtlx,
1478 lvswx, stvfrx, stvflx, stvswx, lvsm, stvepxl, lvtrxl, stvepx,
1479 lvtlxl, lvswxl, stvfrxl, stvflxl, stvswxl>): Enable E6500 only
1480 vector instructions with E6500 not PPCVEC2.
1482 2017-04-06 Pip Cet <pipcet@gmail.com>
1484 * Makefile.am: Add wasm32-dis.c.
1485 * configure.ac: Add wasm32-dis.c to wasm32 target.
1486 * disassemble.c: Add wasm32 disassembler code.
1487 * wasm32-dis.c: New file.
1488 * Makefile.in: Regenerate.
1489 * configure: Regenerate.
1490 * po/POTFILES.in: Regenerate.
1491 * po/opcodes.pot: Regenerate.
1493 2017-04-05 Pedro Alves <palves@redhat.com>
1495 * arc-dis.c (parse_option, parse_disassembler_options): Constify.
1496 * arm-dis.c (parse_arm_disassembler_options): Constify.
1497 * ppc-dis.c (powerpc_init_dialect): Constify local.
1498 * vax-dis.c (parse_disassembler_options): Constify.
1500 2017-04-03 Palmer Dabbelt <palmer@dabbelt.com>
1502 * riscv-dis.c (riscv_disassemble_insn): Change "_gp" to
1503 RISCV_GP_SYMBOL.
1505 2017-03-30 Pip Cet <pipcet@gmail.com>
1507 * configure.ac: Add (empty) bfd_wasm32_arch target.
1508 * configure: Regenerate
1509 * po/opcodes.pot: Regenerate.
1511 2017-03-29 Sheldon Lobo <sheldon.lobo@oracle.com>
1513 Add support for missing SPARC ASIs from UA2005, UA2007, OSA2011, &
1514 OSA2015.
1515 * opcodes/sparc-opc.c (asi_table): New ASIs.
1517 2017-03-29 Alan Modra <amodra@gmail.com>
1519 * ppc-dis.c (ppc_opts): Set PPC_OPCODE_PPC for "any" flags. Add
1520 "raw" option.
1521 (lookup_powerpc): Don't special case -1 dialect. Handle
1522 PPC_OPCODE_RAW.
1523 (print_insn_powerpc): Mask out PPC_OPCODE_ANY on first
1524 lookup_powerpc call, pass it on second.
1526 2017-03-27 Alan Modra <amodra@gmail.com>
1528 PR 21303
1529 * ppc-dis.c (struct ppc_mopt): Comment.
1530 (ppc_opts <e200z4>): Move PPC_OPCODE_VLE from .sticky to .cpu.
1532 2017-03-27 Rinat Zelig <rinat@mellanox.com>
1534 * arc-nps400-tbl.h: Add Ultra Ip and Miscellaneous instructions format.
1535 * arc-opc.c: Add defines. e.g. F_NJ, F_NM , F_NO_T, F_NPS_SR,
1536 F_NPS_M, F_NPS_CORE, F_NPS_ALL.
1537 (insert_nps_misc_imm_offset): New function.
1538 (extract_nps_misc imm_offset): New function.
1539 (arc_num_flag_operands): Add F_NJ, F_NM, F_NO_T.
1540 (arc_flag_special_cases): Add F_NJ, F_NM, F_NO_T.
1542 2017-03-21 Andreas Krebbel <krebbel@linux.vnet.ibm.com>
1544 * s390-mkopc.c (main): Remove vx2 check.
1545 * s390-opc.txt: Remove vx2 instruction flags.
1547 2017-03-21 Rinat Zelig <rinat@mellanox.com>
1549 * arc-nps400-tbl.h: Add cp32/cp16 instructions format.
1550 * arc-opc.c: Add F_NPS_NA, NPS_DMA_IMM_ENTRY, NPS_DMA_IMM_OFFSET.
1551 (insert_nps_imm_offset): New function.
1552 (extract_nps_imm_offset): New function.
1553 (insert_nps_imm_entry): New function.
1554 (extract_nps_imm_entry): New function.
1556 2017-03-17 Alan Modra <amodra@gmail.com>
1558 PR 21248
1559 * ppc-opc.c (powerpc_opcodes): Enable mfivor32, mfivor33,
1560 mtivor32, and mtivor33 for e6500. Move mfibatl and mfibatu after
1561 those spr mnemonics they alias. Similarly for mtibatl, mtibatu.
1563 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1565 * riscv-opc.c (riscv_opcodes> <c.li>: Use the 'o' immediate encoding.
1566 <c.andi>: Likewise.
1567 <c.addiw> Likewise.
1569 2017-03-14 Kito Cheng <kito.cheng@gmail.com>
1571 * riscv-opc.c (riscv_opcodes) <c.addi>: Use match_opcode.
1573 2017-03-13 Andrew Waterman <andrew@sifive.com>
1575 * riscv-opc.c (riscv_opcodes) <srli/C>: Use match_opcode.
1576 <srl> Likewise.
1577 <srai> Likewise.
1578 <sra> Likewise.
1580 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1582 * i386-gen.c (opcode_modifiers): Replace S with Load.
1583 * i386-opc.h (S): Removed.
1584 (Load): New.
1585 (i386_opcode_modifier): Replace s with load.
1586 * i386-opc.tbl: Add {disp8}, {disp32}, {swap}, {vex2}, {vex3}
1587 and {evex}. Replace S with Load.
1588 * i386-tbl.h: Regenerated.
1590 2017-03-09 H.J. Lu <hongjiu.lu@intel.com>
1592 * i386-opc.tbl: Use CpuCET on rdsspq.
1593 * i386-tbl.h: Regenerated.
1595 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1597 * ppc-dis.c (ppc_opts) <altivec>: Do not use PPC_OPCODE_ALTIVEC2;
1598 <vsx>: Do not use PPC_OPCODE_VSX3;
1600 2017-03-08 Peter Bergner <bergner@vnet.ibm.com>
1602 * ppc-opc.c (powerpc_opcodes) <lnia>: New extended mnemonic.
1604 2017-03-06 H.J. Lu <hongjiu.lu@intel.com>
1606 * i386-dis.c (REG_0F1E_MOD_3): New enum.
1607 (MOD_0F1E_PREFIX_1): Likewise.
1608 (MOD_0F38F5_PREFIX_2): Likewise.
1609 (MOD_0F38F6_PREFIX_0): Likewise.
1610 (RM_0F1E_MOD_3_REG_7): Likewise.
1611 (PREFIX_MOD_0_0F01_REG_5): Likewise.
1612 (PREFIX_MOD_3_0F01_REG_5_RM_1): Likewise.
1613 (PREFIX_MOD_3_0F01_REG_5_RM_2): Likewise.
1614 (PREFIX_0F1E): Likewise.
1615 (PREFIX_MOD_0_0FAE_REG_5): Likewise.
1616 (PREFIX_0F38F5): Likewise.
1617 (dis386_twobyte): Use PREFIX_0F1E.
1618 (reg_table): Add REG_0F1E_MOD_3.
1619 (prefix_table): Add PREFIX_MOD_0_0F01_REG_5,
1620 PREFIX_MOD_3_0F01_REG_5_RM_1, PREFIX_MOD_3_0F01_REG_5_RM_2,
1621 PREFIX_0F1E, PREFIX_MOD_0_0FAE_REG_5 and PREFIX_0F38F5. Update
1622 PREFIX_0FAE_REG_6 and PREFIX_0F38F6.
1623 (three_byte_table): Use PREFIX_0F38F5.
1624 (mod_table): Use PREFIX_MOD_0_0F01_REG_5, PREFIX_MOD_0_0FAE_REG_5.
1625 Add MOD_0F1E_PREFIX_1, MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0.
1626 (rm_table): Add MOD_0F38F5_PREFIX_2, MOD_0F38F6_PREFIX_0,
1627 RM_0F1E_MOD_3_REG_7. Use PREFIX_MOD_3_0F01_REG_5_RM_1 and
1628 PREFIX_MOD_3_0F01_REG_5_RM_2.
1629 * i386-gen.c (cpu_flag_init): Add CPU_CET_FLAGS.
1630 (cpu_flags): Add CpuCET.
1631 * i386-opc.h (CpuCET): New enum.
1632 (CpuUnused): Commented out.
1633 (i386_cpu_flags): Add cpucet.
1634 * i386-opc.tbl: Add Intel CET instructions.
1635 * i386-init.h: Regenerated.
1636 * i386-tbl.h: Likewise.
1638 2017-03-06 Alan Modra <amodra@gmail.com>
1640 PR 21124
1641 * ppc-opc.c (extract_esync, extract_ls, extract_ral, extract_ram)
1642 (extract_raq, extract_ras, extract_rbx): New functions.
1643 (powerpc_operands): Use opposite corresponding insert function.
1644 (Q_MASK): Define.
1645 (powerpc_opcodes): Apply Q_MASK to all quad insns with even
1646 register restriction.
1648 2017-02-28 Peter Bergner <bergner@vnet.ibm.com>
1650 * disassemble.c Include "safe-ctype.h".
1651 (disassemble_init_for_target): Handle s390 init.
1652 (remove_whitespace_and_extra_commas): New function.
1653 (disassembler_options_cmp): Likewise.
1654 * arm-dis.c: Include "libiberty.h".
1655 (NUM_ELEM): Delete.
1656 (regnames): Use long disassembler style names.
1657 Add force-thumb and no-force-thumb options.
1658 (NUM_ARM_REGNAMES): Rename from this...
1659 (NUM_ARM_OPTIONS): ...to this. Use ARRAY_SIZE.
1660 (get_arm_regname_num_options): Delete.
1661 (set_arm_regname_option): Likewise.
1662 (get_arm_regnames): Likewise.
1663 (parse_disassembler_options): Likewise.
1664 (parse_arm_disassembler_option): Rename from this...
1665 (parse_arm_disassembler_options): ...to this. Make static.
1666 Use new FOR_EACH_DISASSEMBLER_OPTION macro to scan over options.
1667 (print_insn): Use parse_arm_disassembler_options.
1668 (disassembler_options_arm): New function.
1669 (print_arm_disassembler_options): Handle updated regnames.
1670 * ppc-dis.c: Include "libiberty.h".
1671 (ppc_opts): Add "32" and "64" entries.
1672 (ppc_parse_cpu): Use ARRAY_SIZE and disassembler_options_cmp.
1673 (powerpc_init_dialect): Add break to switch statement.
1674 Use new FOR_EACH_DISASSEMBLER_OPTION macro.
1675 (disassembler_options_powerpc): New function.
1676 (print_ppc_disassembler_options): Use ARRAY_SIZE.
1677 Remove printing of "32" and "64".
1678 * s390-dis.c: Include "libiberty.h".
1679 (init_flag): Remove unneeded variable.
1680 (struct s390_options_t): New structure type.
1681 (options): New structure.
1682 (init_disasm): Rename from this...
1683 (disassemble_init_s390): ...to this. Add initializations for
1684 current_arch_mask and option_use_insn_len_bits_p. Remove init_flag.
1685 (print_insn_s390): Delete call to init_disasm.
1686 (disassembler_options_s390): New function.
1687 (print_s390_disassembler_options): Print using information from
1688 struct 'options'.
1689 * po/opcodes.pot: Regenerate.
1691 2017-02-28 Jan Beulich <jbeulich@suse.com>
1693 * i386-dis.c (PCMPESTR_Fixup): New.
1694 (VEX_W_0F3A60_P_2, VEX_W_0F3A61_P_2): Delete.
1695 (prefix_table): Use PCMPESTR_Fixup.
1696 (vex_len_table): Make VPCMPESTR{I,M} entries leaf ones and use
1697 PCMPESTR_Fixup.
1698 (vex_w_table): Delete VPCMPESTR{I,M} entries.
1699 * i386-opc.tbl (pcmpestri, pcmpestrm, vpcmpestri, vpcmpestrm):
1700 Split 64-bit and non-64-bit variants.
1701 * opcodes/i386-tbl.h: Re-generate.
1703 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1705 * aarch64-tbl.h (OP_SVE_HMH, OP_SVE_VMU_HSD, OP_SVE_VMVU_HSD)
1706 (OP_SVE_VMVV_HSD, OP_SVE_VMVVU_HSD, OP_SVE_VM_HSD, OP_SVE_VUVV_HSD)
1707 (OP_SVE_VUV_HSD, OP_SVE_VU_HSD, OP_SVE_VVVU_H, OP_SVE_VVVU_S)
1708 (OP_SVE_VVVU_HSD, OP_SVE_VVV_D, OP_SVE_VVV_D_H, OP_SVE_VVV_H)
1709 (OP_SVE_VVV_HSD, OP_SVE_VVV_S, OP_SVE_VVV_S_B, OP_SVE_VVV_SD_BH)
1710 (OP_SVE_VV_BHSDQ, OP_SVE_VV_HSD, OP_SVE_VZVV_HSD, OP_SVE_VZV_HSD)
1711 (OP_SVE_V_HSD): New macros.
1712 (OP_SVE_VMU_SD, OP_SVE_VMVU_SD, OP_SVE_VM_SD, OP_SVE_VUVV_SD)
1713 (OP_SVE_VU_SD, OP_SVE_VVVU_SD, OP_SVE_VVV_SD, OP_SVE_VZVV_SD)
1714 (OP_SVE_VZV_SD, OP_SVE_V_SD): Delete.
1715 (aarch64_opcode_table): Add new SVE instructions.
1716 (aarch64_opcode_table): Use imm_rotate{1,2} instead of imm_rotate
1717 for rotation operands. Add new SVE operands.
1718 * aarch64-asm.h (ins_sve_addr_ri_s4): New inserter.
1719 (ins_sve_quad_index): Likewise.
1720 (ins_imm_rotate): Split into...
1721 (ins_imm_rotate1, ins_imm_rotate2): ...these two inserters.
1722 * aarch64-asm.c (aarch64_ins_imm_rotate): Split into...
1723 (aarch64_ins_imm_rotate1, aarch64_ins_imm_rotate2): ...these two
1724 functions.
1725 (aarch64_ins_sve_addr_ri_s4): New function.
1726 (aarch64_ins_sve_quad_index): Likewise.
1727 (do_misc_encoding): Handle "MOV Zn.Q, Qm".
1728 * aarch64-asm-2.c: Regenerate.
1729 * aarch64-dis.h (ext_sve_addr_ri_s4): New extractor.
1730 (ext_sve_quad_index): Likewise.
1731 (ext_imm_rotate): Split into...
1732 (ext_imm_rotate1, ext_imm_rotate2): ...these two extractors.
1733 * aarch64-dis.c (aarch64_ext_imm_rotate): Split into...
1734 (aarch64_ext_imm_rotate1, aarch64_ext_imm_rotate2): ...these two
1735 functions.
1736 (aarch64_ext_sve_addr_ri_s4): New function.
1737 (aarch64_ext_sve_quad_index): Likewise.
1738 (aarch64_ext_sve_index): Allow quad indices.
1739 (do_misc_decoding): Likewise.
1740 * aarch64-dis-2.c: Regenerate.
1741 * aarch64-opc.h (FLD_SVE_i3h, FLD_SVE_rot1, FLD_SVE_rot2): New
1742 aarch64_field_kinds.
1743 (OPD_F_OD_MASK): Widen by one bit.
1744 (OPD_F_NO_ZR): Bump accordingly.
1745 (get_operand_field_width): New function.
1746 * aarch64-opc.c (fields): Add new SVE fields.
1747 (operand_general_constraint_met_p): Handle new SVE operands.
1748 (aarch64_print_operand): Likewise.
1749 * aarch64-opc-2.c: Regenerate.
1751 2017-02-24 Richard Sandiford <richard.sandiford@arm.com>
1753 * aarch64-tbl.h (aarch64_feature_simd_v8_3): Replace with...
1754 (aarch64_feature_compnum): ...this.
1755 (SIMD_V8_3): Replace with...
1756 (COMPNUM): ...this.
1757 (CNUM_INSN): New macro.
1758 (aarch64_opcode_table): Use it for the complex number instructions.
1760 2017-02-24 Jan Beulich <jbeulich@suse.com>
1762 * i386-dis.c (reg_table): REG_F6/1 and REG_F7/1 decode as TEST.
1764 2017-02-23 Sheldon Lobo <sheldon.lobo@oracle.com>
1766 Add support for associating SPARC ASIs with an architecture level.
1767 * include/opcode/sparc.h (sparc_asi): New sparc_asi struct.
1768 * opcodes/sparc-opc.c (asi_table): Updated asi_table and encoding/
1769 decoding of SPARC ASIs.
1771 2017-02-23 Jan Beulich <jbeulich@suse.com>
1773 * i386-dis.c (get_valid_dis386): Don't special case VEX opcode
1774 82. For 3-byte VEX only special case opcode 77 in VEX_0F space.
1776 2017-02-21 Jan Beulich <jbeulich@suse.com>
1778 * aarch64-asm.c (convert_bfc_to_bfm): Copy operand 0 to operand
1779 1 (instead of to itself). Correct typo.
1781 2017-02-14 Andrew Waterman <andrew@sifive.com>
1783 * riscv-opc.c (riscv_opcodes): Add sfence.vma instruction and
1784 pseudoinstructions.
1786 2017-02-15 Richard Sandiford <richard.sandiford@arm.com>
1788 * aarch64-opc.c (aarch64_sys_regs): Add SVE registers.
1789 (aarch64_sys_reg_supported_p): Handle them.
1791 2017-02-15 Claudiu Zissulescu <claziss@synopsys.com>
1793 * arc-opc.c (UIMM6_20R): Define.
1794 (SIMM12_20): Use above.
1795 (SIMM12_20R): Define.
1796 (SIMM3_5_S): Use above.
1797 (UIMM7_A32_11R_S): Define.
1798 (UIMM7_9_S): Use above.
1799 (UIMM3_13R_S): Define.
1800 (SIMM11_A32_7_S): Use above.
1801 (SIMM9_8R): Define.
1802 (UIMM10_A32_8_S): Use above.
1803 (UIMM8_8R_S): Define.
1804 (W6): Use above.
1805 (arc_relax_opcodes): Use all above defines.
1807 2017-02-15 Vineet Gupta <vgupta@synopsys.com>
1809 * arc-regs.h: Distinguish some of the registers different on
1810 ARC700 and HS38 cpus.
1812 2017-02-14 Alan Modra <amodra@gmail.com>
1814 PR 21118
1815 * ppc-opc.c (powerpc_operands): Flag SPR, SPRG and TBR entries
1816 with PPC_OPERAND_SPR. Flag PSQ and PSQM with PPC_OPERAND_GQR.
1818 2017-02-11 Stafford Horne <shorne@gmail.com>
1819 Alan Modra <amodra@gmail.com>
1821 * cgen-opc.c (cgen_lookup_insn): Delete buf and base_insn temps.
1822 Use insn_bytes_value and insn_int_value directly instead. Don't
1823 free allocated memory until function exit.
1825 2017-02-10 Nicholas Piggin <npiggin@gmail.com>
1827 * ppc-opc.c (powerpc_opcodes) <scv, rfscv>: New mnemonics.
1829 2017-02-03 Nick Clifton <nickc@redhat.com>
1831 PR 21096
1832 * aarch64-opc.c (print_register_list): Ensure that the register
1833 list index will fir into the tb buffer.
1834 (print_register_offset_address): Likewise.
1835 * tic6x-dis.c (print_insn_tic6x): Increase size of func_unit_buf.
1837 2017-01-27 Alexis Deruell <alexis.deruelle@gmail.com>
1839 PR 21056
1840 * tic6x-dis.c (print_insn_tic6x): Correct displaying of parallel
1841 instructions when the previous fetch packet ends with a 32-bit
1842 instruction.
1844 2017-01-24 Dimitar Dimitrov <dimitar@dinux.eu>
1846 * pru-opc.c: Remove vague reference to a future GDB port.
1848 2017-01-20 Nick Clifton <nickc@redhat.com>
1850 * po/ga.po: Updated Irish translation.
1852 2017-01-18 Szabolcs Nagy <szabolcs.nagy@arm.com>
1854 * arm-dis.c (coprocessor_opcodes): Fix vcmla mask and disassembly.
1856 2017-01-13 Yao Qi <yao.qi@linaro.org>
1858 * m68k-dis.c (match_insn_m68k): Extend comments. Return -1
1859 if FETCH_DATA returns 0.
1860 (m68k_scan_mask): Likewise.
1861 (print_insn_m68k): Update code to handle -1 return value.
1863 2017-01-13 Yao Qi <yao.qi@linaro.org>
1865 * m68k-dis.c (enum print_insn_arg_error): New.
1866 (NEXTBYTE): Replace -3 with
1867 PRINT_INSN_ARG_MEMORY_ERROR.
1868 (NEXTULONG): Likewise.
1869 (NEXTSINGLE): Likewise.
1870 (NEXTDOUBLE): Likewise.
1871 (NEXTDOUBLE): Likewise.
1872 (NEXTPACKED): Likewise.
1873 (FETCH_ARG): Likewise.
1874 (FETCH_DATA): Update comments.
1875 (print_insn_arg): Update comments. Replace magic numbers with
1876 enum.
1877 (match_insn_m68k): Likewise.
1879 2017-01-12 Igor Tsimbalist <igor.v.tsimbalist@intel.com>
1881 * i386-dis.c (enum): Add PREFIX_EVEX_0F3855, EVEX_W_0F3855_P_2.
1882 * i386-dis-evex.h (evex_table): Updated.
1883 * i386-gen.c (cpu_flag_init): Add CPU_AVX512_VPOPCNTDQ_FLAGS,
1884 CPU_ANY_AVX512_VPOPCNTDQ_FLAGS. Update CPU_ANY_AVX512F_FLAGS.
1885 (cpu_flags): Add CpuAVX512_VPOPCNTDQ.
1886 * i386-opc.h (enum): (AVX512_VPOPCNTDQ): New.
1887 (i386_cpu_flags): Add cpuavx512_vpopcntdq.
1888 * i386-opc.tbl: Add Intel AVX512_VPOPCNTDQ instructions.
1889 * i386-init.h: Regenerate.
1890 * i386-tbl.h: Ditto.
1892 2017-01-12 Yao Qi <yao.qi@linaro.org>
1894 * msp430-dis.c (msp430_singleoperand): Return -1 if
1895 msp430dis_opcode_signed returns false.
1896 (msp430_doubleoperand): Likewise.
1897 (msp430_branchinstr): Return -1 if
1898 msp430dis_opcode_unsigned returns false.
1899 (msp430x_calla_instr): Likewise.
1900 (print_insn_msp430): Likewise.
1902 2017-01-05 Nick Clifton <nickc@redhat.com>
1904 PR 20946
1905 * frv-desc.c (lookup_mach_via_bfd_name): Return NULL if the name
1906 could not be matched.
1907 (frv_cgen_cpu_open): Allow for lookup_mach_via_bfd_name returning
1908 NULL.
1910 2017-01-04 Szabolcs Nagy <szabolcs.nagy@arm.com>
1912 * aarch64-tbl.h (RCPC, RCPC_INSN): Define.
1913 (aarch64_opcode_table): Use RCPC_INSN.
1915 2017-01-03 Kito Cheng <kito.cheng@gmail.com>
1917 * riscv-opc.c (riscv-opcodes): Add support for the "q" ISA
1918 extension.
1919 * riscv-opcodes/all-opcodes: Likewise.
1921 2017-01-03 Dilyan Palauzov <dilyan.palauzov@aegee.org>
1923 * riscv-dis.c (print_insn_args): Add fall through comment.
1925 2017-01-03 Nick Clifton <nickc@redhat.com>
1927 * po/sr.po: New Serbian translation.
1928 * configure.ac (ALL_LINGUAS): Add sr.
1929 * configure: Regenerate.
1931 2017-01-02 Alan Modra <amodra@gmail.com>
1933 * epiphany-desc.h: Regenerate.
1934 * epiphany-opc.h: Regenerate.
1935 * fr30-desc.h: Regenerate.
1936 * fr30-opc.h: Regenerate.
1937 * frv-desc.h: Regenerate.
1938 * frv-opc.h: Regenerate.
1939 * ip2k-desc.h: Regenerate.
1940 * ip2k-opc.h: Regenerate.
1941 * iq2000-desc.h: Regenerate.
1942 * iq2000-opc.h: Regenerate.
1943 * lm32-desc.h: Regenerate.
1944 * lm32-opc.h: Regenerate.
1945 * m32c-desc.h: Regenerate.
1946 * m32c-opc.h: Regenerate.
1947 * m32r-desc.h: Regenerate.
1948 * m32r-opc.h: Regenerate.
1949 * mep-desc.h: Regenerate.
1950 * mep-opc.h: Regenerate.
1951 * mt-desc.h: Regenerate.
1952 * mt-opc.h: Regenerate.
1953 * or1k-desc.h: Regenerate.
1954 * or1k-opc.h: Regenerate.
1955 * xc16x-desc.h: Regenerate.
1956 * xc16x-opc.h: Regenerate.
1957 * xstormy16-desc.h: Regenerate.
1958 * xstormy16-opc.h: Regenerate.
1960 2017-01-02 Alan Modra <amodra@gmail.com>
1962 Update year range in copyright notice of all files.
1964 For older changes see ChangeLog-2016
1965 \f
1966 Copyright (C) 2017 Free Software Foundation, Inc.
1968 Copying and distribution of this file, with or without modification,
1969 are permitted in any medium without royalty provided the copyright
1970 notice and this notice are preserved.
1972 Local Variables:
1973 mode: change-log
1974 left-margin: 8
1975 fill-column: 74
1976 version-control: never
1977 End: