opcodes/xc16x-desc.c

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data for xc16x.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2019 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include "ansidecl.h"
  30 #include "bfd.h"
  31 #include "symcat.h"
  32 #include "xc16x-desc.h"
  33 #include "xc16x-opc.h"
  34 #include "opintl.h"
  35 #include "libiberty.h"
  36 #include "xregex.h"
  37
  38 /* Attributes.  */
  39
  40 static const CGEN_ATTR_ENTRY bool_attr[] =
  41 {
  42   { "#f", 0 },
  43   { "#t", 1 },
  44   { 0, 0 }
  45 };
  46
  47 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  48 {
  49   { "base", MACH_BASE },
  50   { "xc16x", MACH_XC16X },
  51   { "max", MACH_MAX },
  52   { 0, 0 }
  53 };
  54
  55 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  56 {
  57   { "xc16x", ISA_XC16X },
  58   { "max", ISA_MAX },
  59   { 0, 0 }
  60 };
  61
  62 static const CGEN_ATTR_ENTRY PIPE_attr[] ATTRIBUTE_UNUSED =
  63 {
  64   { "NONE", PIPE_NONE },
  65   { "OS", PIPE_OS },
  66   { 0, 0 }
  67 };
  68
  69 const CGEN_ATTR_TABLE xc16x_cgen_ifield_attr_table[] =
  70 {
  71   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  72   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  73   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  74   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  75   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  76   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  77   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  78   { "RELOC", &bool_attr[0], &bool_attr[0] },
  79   { 0, 0, 0 }
  80 };
  81
  82 const CGEN_ATTR_TABLE xc16x_cgen_hardware_attr_table[] =
  83 {
  84   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  85   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  86   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  87   { "PC", &bool_attr[0], &bool_attr[0] },
  88   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  89   { 0, 0, 0 }
  90 };
  91
  92 const CGEN_ATTR_TABLE xc16x_cgen_operand_attr_table[] =
  93 {
  94   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  95   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  96   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  97   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  98   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  99   { "SIGNED", &bool_attr[0], &bool_attr[0] },
 100   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
 101   { "RELAX", &bool_attr[0], &bool_attr[0] },
 102   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
 103   { "RELOC", &bool_attr[0], &bool_attr[0] },
 104   { "HASH-PREFIX", &bool_attr[0], &bool_attr[0] },
 105   { "DOT-PREFIX", &bool_attr[0], &bool_attr[0] },
 106   { "POF-PREFIX", &bool_attr[0], &bool_attr[0] },
 107   { "PAG-PREFIX", &bool_attr[0], &bool_attr[0] },
 108   { "SOF-PREFIX", &bool_attr[0], &bool_attr[0] },
 109   { "SEG-PREFIX", &bool_attr[0], &bool_attr[0] },
 110   { 0, 0, 0 }
 111 };
 112
 113 const CGEN_ATTR_TABLE xc16x_cgen_insn_attr_table[] =
 114 {
 115   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 116   { "PIPE", & PIPE_attr[0], & PIPE_attr[0] },
 117   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 118   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 119   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 120   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 121   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 122   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 123   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 124   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 125   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 126   { "PBB", &bool_attr[0], &bool_attr[0] },
 127   { 0, 0, 0 }
 128 };
 129
 130 /* Instruction set variants.  */
 131
 132 static const CGEN_ISA xc16x_cgen_isa_table[] = {
 133   { "xc16x", 16, 32, 16, 32 },
 134   { 0, 0, 0, 0, 0 }
 135 };
 136
 137 /* Machine variants.  */
 138
 139 static const CGEN_MACH xc16x_cgen_mach_table[] = {
 140   { "xc16x", "xc16x", MACH_XC16X, 32 },
 141   { 0, 0, 0, 0 }
 142 };
 143
 144 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_gr_names_entries[] =
 145 {
 146   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 147   { "r1", 1, {0, {{{0, 0}}}}, 0, 0 },
 148   { "r2", 2, {0, {{{0, 0}}}}, 0, 0 },
 149   { "r3", 3, {0, {{{0, 0}}}}, 0, 0 },
 150   { "r4", 4, {0, {{{0, 0}}}}, 0, 0 },
 151   { "r5", 5, {0, {{{0, 0}}}}, 0, 0 },
 152   { "r6", 6, {0, {{{0, 0}}}}, 0, 0 },
 153   { "r7", 7, {0, {{{0, 0}}}}, 0, 0 },
 154   { "r8", 8, {0, {{{0, 0}}}}, 0, 0 },
 155   { "r9", 9, {0, {{{0, 0}}}}, 0, 0 },
 156   { "r10", 10, {0, {{{0, 0}}}}, 0, 0 },
 157   { "r11", 11, {0, {{{0, 0}}}}, 0, 0 },
 158   { "r12", 12, {0, {{{0, 0}}}}, 0, 0 },
 159   { "r13", 13, {0, {{{0, 0}}}}, 0, 0 },
 160   { "r14", 14, {0, {{{0, 0}}}}, 0, 0 },
 161   { "r15", 15, {0, {{{0, 0}}}}, 0, 0 }
 162 };
 163
 164 CGEN_KEYWORD xc16x_cgen_opval_gr_names =
 165 {
 166   & xc16x_cgen_opval_gr_names_entries[0],
 167   16,
 168   0, 0, 0, 0, ""
 169 };
 170
 171 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_ext_names_entries[] =
 172 {
 173   { "0x1", 0, {0, {{{0, 0}}}}, 0, 0 },
 174   { "0x2", 1, {0, {{{0, 0}}}}, 0, 0 },
 175   { "0x3", 2, {0, {{{0, 0}}}}, 0, 0 },
 176   { "0x4", 3, {0, {{{0, 0}}}}, 0, 0 },
 177   { "1", 0, {0, {{{0, 0}}}}, 0, 0 },
 178   { "2", 1, {0, {{{0, 0}}}}, 0, 0 },
 179   { "3", 2, {0, {{{0, 0}}}}, 0, 0 },
 180   { "4", 3, {0, {{{0, 0}}}}, 0, 0 }
 181 };
 182
 183 CGEN_KEYWORD xc16x_cgen_opval_ext_names =
 184 {
 185   & xc16x_cgen_opval_ext_names_entries[0],
 186   8,
 187   0, 0, 0, 0, ""
 188 };
 189
 190 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_psw_names_entries[] =
 191 {
 192   { "IEN", 136, {0, {{{0, 0}}}}, 0, 0 },
 193   { "r0.11", 240, {0, {{{0, 0}}}}, 0, 0 },
 194   { "r1.11", 241, {0, {{{0, 0}}}}, 0, 0 },
 195   { "r2.11", 242, {0, {{{0, 0}}}}, 0, 0 },
 196   { "r3.11", 243, {0, {{{0, 0}}}}, 0, 0 },
 197   { "r4.11", 244, {0, {{{0, 0}}}}, 0, 0 },
 198   { "r5.11", 245, {0, {{{0, 0}}}}, 0, 0 },
 199   { "r6.11", 246, {0, {{{0, 0}}}}, 0, 0 },
 200   { "r7.11", 247, {0, {{{0, 0}}}}, 0, 0 },
 201   { "r8.11", 248, {0, {{{0, 0}}}}, 0, 0 },
 202   { "r9.11", 249, {0, {{{0, 0}}}}, 0, 0 },
 203   { "r10.11", 250, {0, {{{0, 0}}}}, 0, 0 },
 204   { "r11.11", 251, {0, {{{0, 0}}}}, 0, 0 },
 205   { "r12.11", 252, {0, {{{0, 0}}}}, 0, 0 },
 206   { "r13.11", 253, {0, {{{0, 0}}}}, 0, 0 },
 207   { "r14.11", 254, {0, {{{0, 0}}}}, 0, 0 },
 208   { "r15.11", 255, {0, {{{0, 0}}}}, 0, 0 }
 209 };
 210
 211 CGEN_KEYWORD xc16x_cgen_opval_psw_names =
 212 {
 213   & xc16x_cgen_opval_psw_names_entries[0],
 214   17,
 215   0, 0, 0, 0, ""
 216 };
 217
 218 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb_names_entries[] =
 219 {
 220   { "rl0", 0, {0, {{{0, 0}}}}, 0, 0 },
 221   { "rh0", 1, {0, {{{0, 0}}}}, 0, 0 },
 222   { "rl1", 2, {0, {{{0, 0}}}}, 0, 0 },
 223   { "rh1", 3, {0, {{{0, 0}}}}, 0, 0 },
 224   { "rl2", 4, {0, {{{0, 0}}}}, 0, 0 },
 225   { "rh2", 5, {0, {{{0, 0}}}}, 0, 0 },
 226   { "rl3", 6, {0, {{{0, 0}}}}, 0, 0 },
 227   { "rh3", 7, {0, {{{0, 0}}}}, 0, 0 },
 228   { "rl4", 8, {0, {{{0, 0}}}}, 0, 0 },
 229   { "rh4", 9, {0, {{{0, 0}}}}, 0, 0 },
 230   { "rl5", 10, {0, {{{0, 0}}}}, 0, 0 },
 231   { "rh5", 11, {0, {{{0, 0}}}}, 0, 0 },
 232   { "rl6", 12, {0, {{{0, 0}}}}, 0, 0 },
 233   { "rh6", 13, {0, {{{0, 0}}}}, 0, 0 },
 234   { "rl7", 14, {0, {{{0, 0}}}}, 0, 0 },
 235   { "rh7", 15, {0, {{{0, 0}}}}, 0, 0 }
 236 };
 237
 238 CGEN_KEYWORD xc16x_cgen_opval_grb_names =
 239 {
 240   & xc16x_cgen_opval_grb_names_entries[0],
 241   16,
 242   0, 0, 0, 0, ""
 243 };
 244
 245 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_conditioncode_names_entries[] =
 246 {
 247   { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
 248   { "cc_NET", 1, {0, {{{0, 0}}}}, 0, 0 },
 249   { "cc_Z", 2, {0, {{{0, 0}}}}, 0, 0 },
 250   { "cc_EQ", 2, {0, {{{0, 0}}}}, 0, 0 },
 251   { "cc_NZ", 3, {0, {{{0, 0}}}}, 0, 0 },
 252   { "cc_NE", 3, {0, {{{0, 0}}}}, 0, 0 },
 253   { "cc_V", 4, {0, {{{0, 0}}}}, 0, 0 },
 254   { "cc_NV", 5, {0, {{{0, 0}}}}, 0, 0 },
 255   { "cc_N", 6, {0, {{{0, 0}}}}, 0, 0 },
 256   { "cc_NN", 7, {0, {{{0, 0}}}}, 0, 0 },
 257   { "cc_ULT", 8, {0, {{{0, 0}}}}, 0, 0 },
 258   { "cc_UGE", 9, {0, {{{0, 0}}}}, 0, 0 },
 259   { "cc_C", 8, {0, {{{0, 0}}}}, 0, 0 },
 260   { "cc_NC", 9, {0, {{{0, 0}}}}, 0, 0 },
 261   { "cc_SGT", 10, {0, {{{0, 0}}}}, 0, 0 },
 262   { "cc_SLE", 11, {0, {{{0, 0}}}}, 0, 0 },
 263   { "cc_SLT", 12, {0, {{{0, 0}}}}, 0, 0 },
 264   { "cc_SGE", 13, {0, {{{0, 0}}}}, 0, 0 },
 265   { "cc_UGT", 14, {0, {{{0, 0}}}}, 0, 0 },
 266   { "cc_ULE", 15, {0, {{{0, 0}}}}, 0, 0 }
 267 };
 268
 269 CGEN_KEYWORD xc16x_cgen_opval_conditioncode_names =
 270 {
 271   & xc16x_cgen_opval_conditioncode_names_entries[0],
 272   20,
 273   0, 0, 0, 0, ""
 274 };
 275
 276 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_extconditioncode_names_entries[] =
 277 {
 278   { "cc_UC", 0, {0, {{{0, 0}}}}, 0, 0 },
 279   { "cc_NET", 2, {0, {{{0, 0}}}}, 0, 0 },
 280   { "cc_Z", 4, {0, {{{0, 0}}}}, 0, 0 },
 281   { "cc_EQ", 4, {0, {{{0, 0}}}}, 0, 0 },
 282   { "cc_NZ", 6, {0, {{{0, 0}}}}, 0, 0 },
 283   { "cc_NE", 6, {0, {{{0, 0}}}}, 0, 0 },
 284   { "cc_V", 8, {0, {{{0, 0}}}}, 0, 0 },
 285   { "cc_NV", 10, {0, {{{0, 0}}}}, 0, 0 },
 286   { "cc_N", 12, {0, {{{0, 0}}}}, 0, 0 },
 287   { "cc_NN", 14, {0, {{{0, 0}}}}, 0, 0 },
 288   { "cc_ULT", 16, {0, {{{0, 0}}}}, 0, 0 },
 289   { "cc_UGE", 18, {0, {{{0, 0}}}}, 0, 0 },
 290   { "cc_C", 16, {0, {{{0, 0}}}}, 0, 0 },
 291   { "cc_NC", 18, {0, {{{0, 0}}}}, 0, 0 },
 292   { "cc_SGT", 20, {0, {{{0, 0}}}}, 0, 0 },
 293   { "cc_SLE", 22, {0, {{{0, 0}}}}, 0, 0 },
 294   { "cc_SLT", 24, {0, {{{0, 0}}}}, 0, 0 },
 295   { "cc_SGE", 26, {0, {{{0, 0}}}}, 0, 0 },
 296   { "cc_UGT", 28, {0, {{{0, 0}}}}, 0, 0 },
 297   { "cc_ULE", 30, {0, {{{0, 0}}}}, 0, 0 },
 298   { "cc_nusr0", 1, {0, {{{0, 0}}}}, 0, 0 },
 299   { "cc_nusr1", 3, {0, {{{0, 0}}}}, 0, 0 },
 300   { "cc_usr0", 5, {0, {{{0, 0}}}}, 0, 0 },
 301   { "cc_usr1", 7, {0, {{{0, 0}}}}, 0, 0 }
 302 };
 303
 304 CGEN_KEYWORD xc16x_cgen_opval_extconditioncode_names =
 305 {
 306   & xc16x_cgen_opval_extconditioncode_names_entries[0],
 307   24,
 308   0, 0, 0, 0, ""
 309 };
 310
 311 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_grb8_names_entries[] =
 312 {
 313   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
 314   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
 315   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
 316   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
 317   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
 318   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
 319   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
 320   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
 321   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
 322   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
 323   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
 324   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
 325   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
 326   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
 327   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
 328   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
 329   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
 330   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
 331   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
 332   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
 333   { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
 334   { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
 335   { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
 336   { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
 337   { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
 338   { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
 339   { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
 340   { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
 341   { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
 342   { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
 343   { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
 344   { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
 345   { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
 346   { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
 347   { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
 348   { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
 349 };
 350
 351 CGEN_KEYWORD xc16x_cgen_opval_grb8_names =
 352 {
 353   & xc16x_cgen_opval_grb8_names_entries[0],
 354   36,
 355   0, 0, 0, 0, ""
 356 };
 357
 358 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_r8_names_entries[] =
 359 {
 360   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
 361   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
 362   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
 363   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
 364   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
 365   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
 366   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
 367   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
 368   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
 369   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
 370   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
 371   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
 372   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
 373   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
 374   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
 375   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
 376   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
 377   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
 378   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
 379   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
 380   { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
 381   { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
 382   { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
 383   { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
 384   { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
 385   { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
 386   { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
 387   { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
 388   { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
 389   { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
 390   { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
 391   { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
 392   { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
 393   { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
 394   { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
 395   { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
 396 };
 397
 398 CGEN_KEYWORD xc16x_cgen_opval_r8_names =
 399 {
 400   & xc16x_cgen_opval_r8_names_entries[0],
 401   36,
 402   0, 0, 0, 0, ""
 403 };
 404
 405 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regmem8_names_entries[] =
 406 {
 407   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
 408   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
 409   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
 410   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
 411   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
 412   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
 413   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
 414   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
 415   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
 416   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
 417   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
 418   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
 419   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
 420   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
 421   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
 422   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
 423   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
 424   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
 425   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
 426   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
 427   { "r0", 240, {0, {{{0, 0}}}}, 0, 0 },
 428   { "r1", 241, {0, {{{0, 0}}}}, 0, 0 },
 429   { "r2", 242, {0, {{{0, 0}}}}, 0, 0 },
 430   { "r3", 243, {0, {{{0, 0}}}}, 0, 0 },
 431   { "r4", 244, {0, {{{0, 0}}}}, 0, 0 },
 432   { "r5", 245, {0, {{{0, 0}}}}, 0, 0 },
 433   { "r6", 246, {0, {{{0, 0}}}}, 0, 0 },
 434   { "r7", 247, {0, {{{0, 0}}}}, 0, 0 },
 435   { "r8", 248, {0, {{{0, 0}}}}, 0, 0 },
 436   { "r9", 249, {0, {{{0, 0}}}}, 0, 0 },
 437   { "r10", 250, {0, {{{0, 0}}}}, 0, 0 },
 438   { "r11", 251, {0, {{{0, 0}}}}, 0, 0 },
 439   { "r12", 252, {0, {{{0, 0}}}}, 0, 0 },
 440   { "r13", 253, {0, {{{0, 0}}}}, 0, 0 },
 441   { "r14", 254, {0, {{{0, 0}}}}, 0, 0 },
 442   { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
 443 };
 444
 445 CGEN_KEYWORD xc16x_cgen_opval_regmem8_names =
 446 {
 447   & xc16x_cgen_opval_regmem8_names_entries[0],
 448   36,
 449   0, 0, 0, 0, ""
 450 };
 451
 452 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regdiv8_names_entries[] =
 453 {
 454   { "r0", 0, {0, {{{0, 0}}}}, 0, 0 },
 455   { "r1", 17, {0, {{{0, 0}}}}, 0, 0 },
 456   { "r2", 34, {0, {{{0, 0}}}}, 0, 0 },
 457   { "r3", 51, {0, {{{0, 0}}}}, 0, 0 },
 458   { "r4", 68, {0, {{{0, 0}}}}, 0, 0 },
 459   { "r5", 85, {0, {{{0, 0}}}}, 0, 0 },
 460   { "r6", 102, {0, {{{0, 0}}}}, 0, 0 },
 461   { "r7", 119, {0, {{{0, 0}}}}, 0, 0 },
 462   { "r8", 136, {0, {{{0, 0}}}}, 0, 0 },
 463   { "r9", 153, {0, {{{0, 0}}}}, 0, 0 },
 464   { "r10", 170, {0, {{{0, 0}}}}, 0, 0 },
 465   { "r11", 187, {0, {{{0, 0}}}}, 0, 0 },
 466   { "r12", 204, {0, {{{0, 0}}}}, 0, 0 },
 467   { "r13", 221, {0, {{{0, 0}}}}, 0, 0 },
 468   { "r14", 238, {0, {{{0, 0}}}}, 0, 0 },
 469   { "r15", 255, {0, {{{0, 0}}}}, 0, 0 }
 470 };
 471
 472 CGEN_KEYWORD xc16x_cgen_opval_regdiv8_names =
 473 {
 474   & xc16x_cgen_opval_regdiv8_names_entries[0],
 475   16,
 476   0, 0, 0, 0, ""
 477 };
 478
 479 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name_entries[] =
 480 {
 481   { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
 482   { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
 483   { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
 484   { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
 485   { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
 486   { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
 487   { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
 488   { "0x8", 8, {0, {{{0, 0}}}}, 0, 0 },
 489   { "0x9", 9, {0, {{{0, 0}}}}, 0, 0 },
 490   { "0xa", 10, {0, {{{0, 0}}}}, 0, 0 },
 491   { "0xb", 11, {0, {{{0, 0}}}}, 0, 0 },
 492   { "0xc", 12, {0, {{{0, 0}}}}, 0, 0 },
 493   { "0xd", 13, {0, {{{0, 0}}}}, 0, 0 },
 494   { "0xe", 14, {0, {{{0, 0}}}}, 0, 0 },
 495   { "0xf", 15, {0, {{{0, 0}}}}, 0, 0 },
 496   { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
 497   { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
 498   { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
 499   { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
 500   { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
 501   { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
 502   { "7", 7, {0, {{{0, 0}}}}, 0, 0 },
 503   { "8", 8, {0, {{{0, 0}}}}, 0, 0 },
 504   { "9", 9, {0, {{{0, 0}}}}, 0, 0 },
 505   { "10", 10, {0, {{{0, 0}}}}, 0, 0 },
 506   { "11", 11, {0, {{{0, 0}}}}, 0, 0 },
 507   { "12", 12, {0, {{{0, 0}}}}, 0, 0 },
 508   { "13", 13, {0, {{{0, 0}}}}, 0, 0 },
 509   { "14", 14, {0, {{{0, 0}}}}, 0, 0 },
 510   { "15", 15, {0, {{{0, 0}}}}, 0, 0 }
 511 };
 512
 513 CGEN_KEYWORD xc16x_cgen_opval_reg0_name =
 514 {
 515   & xc16x_cgen_opval_reg0_name_entries[0],
 516   30,
 517   0, 0, 0, 0, ""
 518 };
 519
 520 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_reg0_name1_entries[] =
 521 {
 522   { "0x1", 1, {0, {{{0, 0}}}}, 0, 0 },
 523   { "0x2", 2, {0, {{{0, 0}}}}, 0, 0 },
 524   { "0x3", 3, {0, {{{0, 0}}}}, 0, 0 },
 525   { "0x4", 4, {0, {{{0, 0}}}}, 0, 0 },
 526   { "0x5", 5, {0, {{{0, 0}}}}, 0, 0 },
 527   { "0x6", 6, {0, {{{0, 0}}}}, 0, 0 },
 528   { "0x7", 7, {0, {{{0, 0}}}}, 0, 0 },
 529   { "1", 1, {0, {{{0, 0}}}}, 0, 0 },
 530   { "2", 2, {0, {{{0, 0}}}}, 0, 0 },
 531   { "3", 3, {0, {{{0, 0}}}}, 0, 0 },
 532   { "4", 4, {0, {{{0, 0}}}}, 0, 0 },
 533   { "5", 5, {0, {{{0, 0}}}}, 0, 0 },
 534   { "6", 6, {0, {{{0, 0}}}}, 0, 0 },
 535   { "7", 7, {0, {{{0, 0}}}}, 0, 0 }
 536 };
 537
 538 CGEN_KEYWORD xc16x_cgen_opval_reg0_name1 =
 539 {
 540   & xc16x_cgen_opval_reg0_name1_entries[0],
 541   14,
 542   0, 0, 0, 0, ""
 543 };
 544
 545 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_regbmem8_names_entries[] =
 546 {
 547   { "dpp0", 0, {0, {{{0, 0}}}}, 0, 0 },
 548   { "dpp1", 1, {0, {{{0, 0}}}}, 0, 0 },
 549   { "dpp2", 2, {0, {{{0, 0}}}}, 0, 0 },
 550   { "dpp3", 3, {0, {{{0, 0}}}}, 0, 0 },
 551   { "psw", 136, {0, {{{0, 0}}}}, 0, 0 },
 552   { "cp", 8, {0, {{{0, 0}}}}, 0, 0 },
 553   { "mdl", 7, {0, {{{0, 0}}}}, 0, 0 },
 554   { "mdh", 6, {0, {{{0, 0}}}}, 0, 0 },
 555   { "mdc", 135, {0, {{{0, 0}}}}, 0, 0 },
 556   { "sp", 9, {0, {{{0, 0}}}}, 0, 0 },
 557   { "csp", 4, {0, {{{0, 0}}}}, 0, 0 },
 558   { "vecseg", 137, {0, {{{0, 0}}}}, 0, 0 },
 559   { "stkov", 10, {0, {{{0, 0}}}}, 0, 0 },
 560   { "stkun", 11, {0, {{{0, 0}}}}, 0, 0 },
 561   { "cpucon1", 12, {0, {{{0, 0}}}}, 0, 0 },
 562   { "cpucon2", 13, {0, {{{0, 0}}}}, 0, 0 },
 563   { "zeros", 142, {0, {{{0, 0}}}}, 0, 0 },
 564   { "ones", 143, {0, {{{0, 0}}}}, 0, 0 },
 565   { "spseg", 134, {0, {{{0, 0}}}}, 0, 0 },
 566   { "tfr", 214, {0, {{{0, 0}}}}, 0, 0 },
 567   { "rl0", 240, {0, {{{0, 0}}}}, 0, 0 },
 568   { "rh0", 241, {0, {{{0, 0}}}}, 0, 0 },
 569   { "rl1", 242, {0, {{{0, 0}}}}, 0, 0 },
 570   { "rh1", 243, {0, {{{0, 0}}}}, 0, 0 },
 571   { "rl2", 244, {0, {{{0, 0}}}}, 0, 0 },
 572   { "rh2", 245, {0, {{{0, 0}}}}, 0, 0 },
 573   { "rl3", 246, {0, {{{0, 0}}}}, 0, 0 },
 574   { "rh3", 247, {0, {{{0, 0}}}}, 0, 0 },
 575   { "rl4", 248, {0, {{{0, 0}}}}, 0, 0 },
 576   { "rh4", 249, {0, {{{0, 0}}}}, 0, 0 },
 577   { "rl5", 250, {0, {{{0, 0}}}}, 0, 0 },
 578   { "rh5", 251, {0, {{{0, 0}}}}, 0, 0 },
 579   { "rl6", 252, {0, {{{0, 0}}}}, 0, 0 },
 580   { "rh6", 253, {0, {{{0, 0}}}}, 0, 0 },
 581   { "rl7", 254, {0, {{{0, 0}}}}, 0, 0 },
 582   { "rh7", 255, {0, {{{0, 0}}}}, 0, 0 }
 583 };
 584
 585 CGEN_KEYWORD xc16x_cgen_opval_regbmem8_names =
 586 {
 587   & xc16x_cgen_opval_regbmem8_names_entries[0],
 588   36,
 589   0, 0, 0, 0, ""
 590 };
 591
 592 static CGEN_KEYWORD_ENTRY xc16x_cgen_opval_memgr8_names_entries[] =
 593 {
 594   { "dpp0", 65024, {0, {{{0, 0}}}}, 0, 0 },
 595   { "dpp1", 65026, {0, {{{0, 0}}}}, 0, 0 },
 596   { "dpp2", 65028, {0, {{{0, 0}}}}, 0, 0 },
 597   { "dpp3", 65030, {0, {{{0, 0}}}}, 0, 0 },
 598   { "psw", 65296, {0, {{{0, 0}}}}, 0, 0 },
 599   { "cp", 65040, {0, {{{0, 0}}}}, 0, 0 },
 600   { "mdl", 65038, {0, {{{0, 0}}}}, 0, 0 },
 601   { "mdh", 65036, {0, {{{0, 0}}}}, 0, 0 },
 602   { "mdc", 65294, {0, {{{0, 0}}}}, 0, 0 },
 603   { "sp", 65042, {0, {{{0, 0}}}}, 0, 0 },
 604   { "csp", 65032, {0, {{{0, 0}}}}, 0, 0 },
 605   { "vecseg", 65298, {0, {{{0, 0}}}}, 0, 0 },
 606   { "stkov", 65044, {0, {{{0, 0}}}}, 0, 0 },
 607   { "stkun", 65046, {0, {{{0, 0}}}}, 0, 0 },
 608   { "cpucon1", 65048, {0, {{{0, 0}}}}, 0, 0 },
 609   { "cpucon2", 65050, {0, {{{0, 0}}}}, 0, 0 },
 610   { "zeros", 65308, {0, {{{0, 0}}}}, 0, 0 },
 611   { "ones", 65310, {0, {{{0, 0}}}}, 0, 0 },
 612   { "spseg", 65292, {0, {{{0, 0}}}}, 0, 0 },
 613   { "tfr", 65452, {0, {{{0, 0}}}}, 0, 0 }
 614 };
 615
 616 CGEN_KEYWORD xc16x_cgen_opval_memgr8_names =
 617 {
 618   & xc16x_cgen_opval_memgr8_names_entries[0],
 619   20,
 620   0, 0, 0, 0, ""
 621 };
 622
 623
 624 /* The hardware table.  */
 625
 626 #define A(a) (1 << CGEN_HW_##a)
 627
 628 const CGEN_HW_ENTRY xc16x_cgen_hw_table[] =
 629 {
 630   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 631   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 632   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 633   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 634   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 635   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
 636   { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 637   { "h-cr", HW_H_CR, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_gr_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 638   { "h-ext", HW_H_EXT, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_ext_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 639   { "h-psw", HW_H_PSW, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_psw_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 640   { "h-grb", HW_H_GRB, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 641   { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_conditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 642   { "h-ecc", HW_H_ECC, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_extconditioncode_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 643   { "h-grb8", HW_H_GRB8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_grb8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 644   { "h-r8", HW_H_R8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_r8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 645   { "h-regmem8", HW_H_REGMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regmem8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 646   { "h-regdiv8", HW_H_REGDIV8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regdiv8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 647   { "h-r0", HW_H_R0, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 648   { "h-r01", HW_H_R01, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_reg0_name1, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 649   { "h-regbmem8", HW_H_REGBMEM8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_regbmem8_names, { 0|A(CACHE_ADDR)|A(PROFILE), { { { (1<<MACH_BASE), 0 } } } } },
 650   { "h-memgr8", HW_H_MEMGR8, CGEN_ASM_KEYWORD, (PTR) & xc16x_cgen_opval_memgr8_names, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 651   { "h-cond", HW_H_COND, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 652   { "h-cbit", HW_H_CBIT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 653   { "h-sgtdis", HW_H_SGTDIS, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 654   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 655 };
 656
 657 #undef A
 658
 659
 660 /* The instruction field table.  */
 661
 662 #define A(a) (1 << CGEN_IFLD_##a)
 663
 664 const CGEN_IFLD xc16x_cgen_ifld_table[] =
 665 {
 666   { XC16X_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 667   { XC16X_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 668   { XC16X_F_OP1, "f-op1", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 669   { XC16X_F_OP2, "f-op2", 0, 32, 3, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 670   { XC16X_F_CONDCODE, "f-condcode", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 671   { XC16X_F_ICONDCODE, "f-icondcode", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 672   { XC16X_F_RCOND, "f-rcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 673   { XC16X_F_QCOND, "f-qcond", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 674   { XC16X_F_EXTCCODE, "f-extccode", 0, 32, 15, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 675   { XC16X_F_R0, "f-r0", 0, 32, 9, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 676   { XC16X_F_R1, "f-r1", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 677   { XC16X_F_R2, "f-r2", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 678   { XC16X_F_R3, "f-r3", 0, 32, 12, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 679   { XC16X_F_R4, "f-r4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 680   { XC16X_F_UIMM2, "f-uimm2", 0, 32, 13, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 681   { XC16X_F_UIMM3, "f-uimm3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 682   { XC16X_F_UIMM4, "f-uimm4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 683   { XC16X_F_UIMM7, "f-uimm7", 0, 32, 15, 7, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 684   { XC16X_F_UIMM8, "f-uimm8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 685   { XC16X_F_UIMM16, "f-uimm16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 686   { XC16X_F_MEMORY, "f-memory", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 687   { XC16X_F_MEMGR8, "f-memgr8", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 688   { XC16X_F_REL8, "f-rel8", 0, 32, 15, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 689   { XC16X_F_RELHI8, "f-relhi8", 0, 32, 23, 8, { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 690   { XC16X_F_REG8, "f-reg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 691   { XC16X_F_REGMEM8, "f-regmem8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 692   { XC16X_F_REGOFF8, "f-regoff8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 693   { XC16X_F_REGHI8, "f-reghi8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 694   { XC16X_F_REGB8, "f-regb8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 695   { XC16X_F_SEG8, "f-seg8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 696   { XC16X_F_SEGNUM8, "f-segnum8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 697   { XC16X_F_MASK8, "f-mask8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 698   { XC16X_F_PAGENUM, "f-pagenum", 0, 32, 25, 10, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 699   { XC16X_F_DATAHI8, "f-datahi8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 700   { XC16X_F_DATA8, "f-data8", 0, 32, 23, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 701   { XC16X_F_OFFSET16, "f-offset16", 0, 32, 31, 16, { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 702   { XC16X_F_OP_BIT1, "f-op-bit1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 703   { XC16X_F_OP_BIT2, "f-op-bit2", 0, 32, 11, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 704   { XC16X_F_OP_BIT4, "f-op-bit4", 0, 32, 11, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 705   { XC16X_F_OP_BIT3, "f-op-bit3", 0, 32, 10, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 706   { XC16X_F_OP_2BIT, "f-op-2bit", 0, 32, 10, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 707   { XC16X_F_OP_BITONE, "f-op-bitone", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 708   { XC16X_F_OP_ONEBIT, "f-op-onebit", 0, 32, 9, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 709   { XC16X_F_OP_1BIT, "f-op-1bit", 0, 32, 8, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 710   { XC16X_F_OP_LBIT4, "f-op-lbit4", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 711   { XC16X_F_OP_LBIT2, "f-op-lbit2", 0, 32, 15, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 712   { XC16X_F_OP_BIT8, "f-op-bit8", 0, 32, 31, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 713   { XC16X_F_OP_BIT16, "f-op-bit16", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 714   { XC16X_F_QBIT, "f-qbit", 0, 32, 7, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 715   { XC16X_F_QLOBIT, "f-qlobit", 0, 32, 31, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 716   { XC16X_F_QHIBIT, "f-qhibit", 0, 32, 27, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 717   { XC16X_F_QLOBIT2, "f-qlobit2", 0, 32, 27, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 718   { XC16X_F_POF, "f-pof", 0, 32, 31, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 719   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 720 };
 721
 722 #undef A
 723
 724
 725
 726 /* multi ifield declarations */
 727
 728
 729
 730 /* multi ifield definitions */
 731
 732
 733 /* The operand table.  */
 734
 735 #define A(a) (1 << CGEN_OPERAND_##a)
 736 #define OPERAND(op) XC16X_OPERAND_##op
 737
 738 const CGEN_OPERAND xc16x_cgen_operand_table[] =
 739 {
 740 /* pc: program counter */
 741   { "pc", XC16X_OPERAND_PC, HW_H_PC, 0, 0,
 742     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_NIL] } },
 743     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 744 /* sr: source register */
 745   { "sr", XC16X_OPERAND_SR, HW_H_GR, 11, 4,
 746     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
 747     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 748 /* dr: destination register */
 749   { "dr", XC16X_OPERAND_DR, HW_H_GR, 15, 4,
 750     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
 751     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 752 /* dri: destination register */
 753   { "dri", XC16X_OPERAND_DRI, HW_H_GR, 11, 4,
 754     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R4] } },
 755     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 756 /* srb: source register */
 757   { "srb", XC16X_OPERAND_SRB, HW_H_GRB, 11, 4,
 758     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
 759     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 760 /* drb: destination register */
 761   { "drb", XC16X_OPERAND_DRB, HW_H_GRB, 15, 4,
 762     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
 763     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 764 /* sr2: 2 bit source register */
 765   { "sr2", XC16X_OPERAND_SR2, HW_H_GR, 9, 2,
 766     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R0] } },
 767     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 768 /* src1: source register 1 */
 769   { "src1", XC16X_OPERAND_SRC1, HW_H_GR, 15, 4,
 770     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R1] } },
 771     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 772 /* src2: source register 2 */
 773   { "src2", XC16X_OPERAND_SRC2, HW_H_GR, 11, 4,
 774     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_R2] } },
 775     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 776 /* srdiv: source register 2 */
 777   { "srdiv", XC16X_OPERAND_SRDIV, HW_H_REGDIV8, 15, 8,
 778     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
 779     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 780 /* RegNam: PSW bits */
 781   { "RegNam", XC16X_OPERAND_REGNAM, HW_H_PSW, 15, 8,
 782     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
 783     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 784 /* uimm2: 2 bit unsigned number */
 785   { "uimm2", XC16X_OPERAND_UIMM2, HW_H_EXT, 13, 2,
 786     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM2] } },
 787     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 788 /* uimm3: 3 bit unsigned number */
 789   { "uimm3", XC16X_OPERAND_UIMM3, HW_H_R01, 10, 3,
 790     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM3] } },
 791     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 792 /* uimm4: 4 bit unsigned number */
 793   { "uimm4", XC16X_OPERAND_UIMM4, HW_H_UINT, 15, 4,
 794     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
 795     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 796 /* uimm7: 7 bit trap number */
 797   { "uimm7", XC16X_OPERAND_UIMM7, HW_H_UINT, 15, 7,
 798     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM7] } },
 799     { 0|A(HASH_PREFIX)|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 800 /* uimm8: 8 bit unsigned immediate */
 801   { "uimm8", XC16X_OPERAND_UIMM8, HW_H_UINT, 23, 8,
 802     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM8] } },
 803     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 804 /* uimm16: 16 bit unsigned immediate */
 805   { "uimm16", XC16X_OPERAND_UIMM16, HW_H_UINT, 31, 16,
 806     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
 807     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 808 /* upof16: 16 bit unsigned immediate */
 809   { "upof16", XC16X_OPERAND_UPOF16, HW_H_ADDR, 31, 16,
 810     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
 811     { 0|A(POF_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 812 /* reg8: 8 bit word register number */
 813   { "reg8", XC16X_OPERAND_REG8, HW_H_R8, 15, 8,
 814     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REG8] } },
 815     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 816 /* regmem8: 8 bit word register number */
 817   { "regmem8", XC16X_OPERAND_REGMEM8, HW_H_REGMEM8, 15, 8,
 818     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
 819     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 820 /* regbmem8: 8 bit byte register number */
 821   { "regbmem8", XC16X_OPERAND_REGBMEM8, HW_H_REGBMEM8, 15, 8,
 822     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGMEM8] } },
 823     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 824 /* regoff8: 8 bit word register number */
 825   { "regoff8", XC16X_OPERAND_REGOFF8, HW_H_R8, 15, 8,
 826     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGOFF8] } },
 827     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 828 /* reghi8: 8 bit word register number */
 829   { "reghi8", XC16X_OPERAND_REGHI8, HW_H_R8, 23, 8,
 830     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGHI8] } },
 831     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 832 /* regb8: 8 bit byte register number */
 833   { "regb8", XC16X_OPERAND_REGB8, HW_H_GRB8, 15, 8,
 834     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
 835     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 836 /* genreg: 8 bit word register number */
 837   { "genreg", XC16X_OPERAND_GENREG, HW_H_R8, 15, 8,
 838     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REGB8] } },
 839     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 840 /* seg: 8 bit segment number */
 841   { "seg", XC16X_OPERAND_SEG, HW_H_UINT, 15, 8,
 842     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
 843     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 844 /* seghi8: 8 bit hi segment number */
 845   { "seghi8", XC16X_OPERAND_SEGHI8, HW_H_UINT, 23, 8,
 846     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEGNUM8] } },
 847     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 848 /* caddr: 16 bit address offset */
 849   { "caddr", XC16X_OPERAND_CADDR, HW_H_ADDR, 31, 16,
 850     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
 851     { 0|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 852 /* rel: 8 bit signed relative offset */
 853   { "rel", XC16X_OPERAND_REL, HW_H_SINT, 15, 8,
 854     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_REL8] } },
 855     { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 856 /* relhi: hi 8 bit signed relative offset */
 857   { "relhi", XC16X_OPERAND_RELHI, HW_H_SINT, 23, 8,
 858     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_RELHI8] } },
 859     { 0|A(RELOC)|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 860 /* condbit: condition bit */
 861   { "condbit", XC16X_OPERAND_CONDBIT, HW_H_COND, 0, 0,
 862     { 0, { (const PTR) 0 } },
 863     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 864 /* bit1: gap of 1 bit */
 865   { "bit1", XC16X_OPERAND_BIT1, HW_H_UINT, 11, 1,
 866     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT1] } },
 867     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 868 /* bit2: gap of 2 bits */
 869   { "bit2", XC16X_OPERAND_BIT2, HW_H_UINT, 11, 2,
 870     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT2] } },
 871     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 872 /* bit4: gap of 4 bits */
 873   { "bit4", XC16X_OPERAND_BIT4, HW_H_UINT, 11, 4,
 874     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT4] } },
 875     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 876 /* lbit4: gap of 4 bits */
 877   { "lbit4", XC16X_OPERAND_LBIT4, HW_H_UINT, 15, 4,
 878     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT4] } },
 879     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 880 /* lbit2: gap of 2 bits */
 881   { "lbit2", XC16X_OPERAND_LBIT2, HW_H_UINT, 15, 2,
 882     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_LBIT2] } },
 883     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 884 /* bit8: gap of 8 bits */
 885   { "bit8", XC16X_OPERAND_BIT8, HW_H_UINT, 31, 8,
 886     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_BIT8] } },
 887     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 888 /* u4: gap of 4 bits */
 889   { "u4", XC16X_OPERAND_U4, HW_H_R0, 15, 4,
 890     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM4] } },
 891     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 892 /* bitone: field of 1 bit */
 893   { "bitone", XC16X_OPERAND_BITONE, HW_H_UINT, 9, 1,
 894     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_ONEBIT] } },
 895     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 896 /* bit01: field of 1 bit */
 897   { "bit01", XC16X_OPERAND_BIT01, HW_H_UINT, 8, 1,
 898     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OP_1BIT] } },
 899     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 900 /* cond: condition code */
 901   { "cond", XC16X_OPERAND_COND, HW_H_CC, 7, 4,
 902     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_CONDCODE] } },
 903     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 904 /* icond: indirect condition code */
 905   { "icond", XC16X_OPERAND_ICOND, HW_H_CC, 15, 4,
 906     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_ICONDCODE] } },
 907     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 908 /* extcond: extended condition code */
 909   { "extcond", XC16X_OPERAND_EXTCOND, HW_H_ECC, 15, 5,
 910     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_EXTCCODE] } },
 911     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 912 /* memory: 16 bit memory */
 913   { "memory", XC16X_OPERAND_MEMORY, HW_H_ADDR, 31, 16,
 914     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMORY] } },
 915     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 916 /* memgr8: 16 bit memory */
 917   { "memgr8", XC16X_OPERAND_MEMGR8, HW_H_MEMGR8, 31, 16,
 918     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MEMGR8] } },
 919     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 920 /* cbit: carry bit */
 921   { "cbit", XC16X_OPERAND_CBIT, HW_H_CBIT, 0, 0,
 922     { 0, { (const PTR) 0 } },
 923     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 924 /* qbit: bit addr */
 925   { "qbit", XC16X_OPERAND_QBIT, HW_H_UINT, 7, 4,
 926     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QBIT] } },
 927     { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 928 /* qlobit: bit addr */
 929   { "qlobit", XC16X_OPERAND_QLOBIT, HW_H_UINT, 31, 4,
 930     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QLOBIT] } },
 931     { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 932 /* qhibit: bit addr */
 933   { "qhibit", XC16X_OPERAND_QHIBIT, HW_H_UINT, 27, 4,
 934     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_QHIBIT] } },
 935     { 0|A(DOT_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 936 /* mask8: 8 bit mask */
 937   { "mask8", XC16X_OPERAND_MASK8, HW_H_UINT, 23, 8,
 938     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_MASK8] } },
 939     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 940 /* masklo8: 8 bit mask */
 941   { "masklo8", XC16X_OPERAND_MASKLO8, HW_H_UINT, 31, 8,
 942     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
 943     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 944 /* pagenum: 10 bit page number */
 945   { "pagenum", XC16X_OPERAND_PAGENUM, HW_H_UINT, 25, 10,
 946     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_PAGENUM] } },
 947     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 948 /* data8: 8 bit data */
 949   { "data8", XC16X_OPERAND_DATA8, HW_H_UINT, 23, 8,
 950     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATA8] } },
 951     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 952 /* datahi8: 8 bit data */
 953   { "datahi8", XC16X_OPERAND_DATAHI8, HW_H_UINT, 31, 8,
 954     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_DATAHI8] } },
 955     { 0|A(HASH_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 956 /* sgtdisbit: segmentation enable bit */
 957   { "sgtdisbit", XC16X_OPERAND_SGTDISBIT, HW_H_SGTDIS, 0, 0,
 958     { 0, { (const PTR) 0 } },
 959     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 960 /* upag16: 16 bit unsigned immediate */
 961   { "upag16", XC16X_OPERAND_UPAG16, HW_H_UINT, 31, 16,
 962     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_UIMM16] } },
 963     { 0|A(PAG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 964 /* useg8: 8 bit segment  */
 965   { "useg8", XC16X_OPERAND_USEG8, HW_H_UINT, 15, 8,
 966     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_SEG8] } },
 967     { 0|A(SEG_PREFIX), { { { (1<<MACH_BASE), 0 } } } }  },
 968 /* useg16: 16 bit address offset */
 969   { "useg16", XC16X_OPERAND_USEG16, HW_H_UINT, 31, 16,
 970     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
 971     { 0|A(SEG_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 972 /* usof16: 16 bit address offset */
 973   { "usof16", XC16X_OPERAND_USOF16, HW_H_UINT, 31, 16,
 974     { 0, { (const PTR) &xc16x_cgen_ifld_table[XC16X_F_OFFSET16] } },
 975     { 0|A(SOF_PREFIX)|A(RELOC)|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 976 /* hash: # prefix */
 977   { "hash", XC16X_OPERAND_HASH, HW_H_SINT, 0, 0,
 978     { 0, { (const PTR) 0 } },
 979     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 980 /* dot: . prefix */
 981   { "dot", XC16X_OPERAND_DOT, HW_H_SINT, 0, 0,
 982     { 0, { (const PTR) 0 } },
 983     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 984 /* pof: pof: prefix */
 985   { "pof", XC16X_OPERAND_POF, HW_H_SINT, 0, 0,
 986     { 0, { (const PTR) 0 } },
 987     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 988 /* pag: pag: prefix */
 989   { "pag", XC16X_OPERAND_PAG, HW_H_SINT, 0, 0,
 990     { 0, { (const PTR) 0 } },
 991     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 992 /* sof: sof: prefix */
 993   { "sof", XC16X_OPERAND_SOF, HW_H_SINT, 0, 0,
 994     { 0, { (const PTR) 0 } },
 995     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 996 /* segm: seg: prefix */
 997   { "segm", XC16X_OPERAND_SEGM, HW_H_SINT, 0, 0,
 998     { 0, { (const PTR) 0 } },
 999     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
1000 /* sentinel */
1001   { 0, 0, 0, 0, 0,
1002     { 0, { (const PTR) 0 } },
1003     { 0, { { { (1<<MACH_BASE), 0 } } } } }
1004 };
1005
1006 #undef A
1007
1008
1009 /* The instruction table.  */
1010
1011 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
1012 #define A(a) (1 << CGEN_INSN_##a)
1013
1014 static const CGEN_IBASE xc16x_cgen_insn_table[MAX_INSNS] =
1015 {
1016   /* Special null first entry.
1017      A `num' value of zero is thus invalid.
1018      Also, the special `invalid' insn resides here.  */
1019   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_NONE, 0 } } } } },
1020 /* add $reg8,$pof$upof16 */
1021   {
1022     XC16X_INSN_ADDRPOF, "addrpof", "add", 32,
1023     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1024   },
1025 /* sub $reg8,$pof$upof16 */
1026   {
1027     XC16X_INSN_SUBRPOF, "subrpof", "sub", 32,
1028     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1029   },
1030 /* addb $regb8,$pof$upof16 */
1031   {
1032     XC16X_INSN_ADDBRPOF, "addbrpof", "addb", 32,
1033     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1034   },
1035 /* subb $regb8,$pof$upof16 */
1036   {
1037     XC16X_INSN_SUBBRPOF, "subbrpof", "subb", 32,
1038     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1039   },
1040 /* add $reg8,$pag$upag16 */
1041   {
1042     XC16X_INSN_ADDRPAG, "addrpag", "add", 32,
1043     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1044   },
1045 /* sub $reg8,$pag$upag16 */
1046   {
1047     XC16X_INSN_SUBRPAG, "subrpag", "sub", 32,
1048     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1049   },
1050 /* addb $regb8,$pag$upag16 */
1051   {
1052     XC16X_INSN_ADDBRPAG, "addbrpag", "addb", 32,
1053     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1054   },
1055 /* subb $regb8,$pag$upag16 */
1056   {
1057     XC16X_INSN_SUBBRPAG, "subbrpag", "subb", 32,
1058     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1059   },
1060 /* addc $reg8,$pof$upof16 */
1061   {
1062     XC16X_INSN_ADDCRPOF, "addcrpof", "addc", 32,
1063     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1064   },
1065 /* subc $reg8,$pof$upof16 */
1066   {
1067     XC16X_INSN_SUBCRPOF, "subcrpof", "subc", 32,
1068     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1069   },
1070 /* addcb $regb8,$pof$upof16 */
1071   {
1072     XC16X_INSN_ADDCBRPOF, "addcbrpof", "addcb", 32,
1073     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1074   },
1075 /* subcb $regb8,$pof$upof16 */
1076   {
1077     XC16X_INSN_SUBCBRPOF, "subcbrpof", "subcb", 32,
1078     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1079   },
1080 /* addc $reg8,$pag$upag16 */
1081   {
1082     XC16X_INSN_ADDCRPAG, "addcrpag", "addc", 32,
1083     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1084   },
1085 /* subc $reg8,$pag$upag16 */
1086   {
1087     XC16X_INSN_SUBCRPAG, "subcrpag", "subc", 32,
1088     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1089   },
1090 /* addcb $regb8,$pag$upag16 */
1091   {
1092     XC16X_INSN_ADDCBRPAG, "addcbrpag", "addcb", 32,
1093     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1094   },
1095 /* subcb $regb8,$pag$upag16 */
1096   {
1097     XC16X_INSN_SUBCBRPAG, "subcbrpag", "subcb", 32,
1098     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1099   },
1100 /* add $pof$upof16,$reg8 */
1101   {
1102     XC16X_INSN_ADDRPOFR, "addrpofr", "add", 32,
1103     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1104   },
1105 /* sub $pof$upof16,$reg8 */
1106   {
1107     XC16X_INSN_SUBRPOFR, "subrpofr", "sub", 32,
1108     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1109   },
1110 /* addb $pof$upof16,$regb8 */
1111   {
1112     XC16X_INSN_ADDBRPOFR, "addbrpofr", "addb", 32,
1113     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1114   },
1115 /* subb $pof$upof16,$regb8 */
1116   {
1117     XC16X_INSN_SUBBRPOFR, "subbrpofr", "subb", 32,
1118     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1119   },
1120 /* addc $pof$upof16,$reg8 */
1121   {
1122     XC16X_INSN_ADDCRPOFR, "addcrpofr", "addc", 32,
1123     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1124   },
1125 /* subc $pof$upof16,$reg8 */
1126   {
1127     XC16X_INSN_SUBCRPOFR, "subcrpofr", "subc", 32,
1128     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1129   },
1130 /* addcb $pof$upof16,$regb8 */
1131   {
1132     XC16X_INSN_ADDCBRPOFR, "addcbrpofr", "addcb", 32,
1133     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1134   },
1135 /* subcb $pof$upof16,$regb8 */
1136   {
1137     XC16X_INSN_SUBCBRPOFR, "subcbrpofr", "subcb", 32,
1138     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1139   },
1140 /* add $reg8,$hash$pof$uimm16 */
1141   {
1142     XC16X_INSN_ADDRHPOF, "addrhpof", "add", 32,
1143     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1144   },
1145 /* sub $reg8,$hash$pof$uimm16 */
1146   {
1147     XC16X_INSN_SUBRHPOF, "subrhpof", "sub", 32,
1148     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1149   },
1150 /* add $reg8,$hash$pag$uimm16 */
1151   {
1152     XC16X_INSN_ADDBRHPOF, "addbrhpof", "add", 32,
1153     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1154   },
1155 /* sub $reg8,$hash$pag$uimm16 */
1156   {
1157     XC16X_INSN_SUBBRHPOF, "subbrhpof", "sub", 32,
1158     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1159   },
1160 /* add $dr,$hash$pof$uimm3 */
1161   {
1162     XC16X_INSN_ADDRHPOF3, "addrhpof3", "add", 16,
1163     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1164   },
1165 /* sub $dr,$hash$pof$uimm3 */
1166   {
1167     XC16X_INSN_SUBRHPOF3, "subrhpof3", "sub", 16,
1168     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1169   },
1170 /* addb $drb,$hash$pag$uimm3 */
1171   {
1172     XC16X_INSN_ADDBRHPAG3, "addbrhpag3", "addb", 16,
1173     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1174   },
1175 /* subb $drb,$hash$pag$uimm3 */
1176   {
1177     XC16X_INSN_SUBBRHPAG3, "subbrhpag3", "subb", 16,
1178     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1179   },
1180 /* add $dr,$hash$pag$uimm3 */
1181   {
1182     XC16X_INSN_ADDRHPAG3, "addrhpag3", "add", 16,
1183     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1184   },
1185 /* sub $dr,$hash$pag$uimm3 */
1186   {
1187     XC16X_INSN_SUBRHPAG3, "subrhpag3", "sub", 16,
1188     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1189   },
1190 /* addb $drb,$hash$pof$uimm3 */
1191   {
1192     XC16X_INSN_ADDBRHPOF3, "addbrhpof3", "addb", 16,
1193     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1194   },
1195 /* subb $drb,$hash$pof$uimm3 */
1196   {
1197     XC16X_INSN_SUBBRHPOF3, "subbrhpof3", "subb", 16,
1198     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1199   },
1200 /* addb $regb8,$hash$pof$uimm8 */
1201   {
1202     XC16X_INSN_ADDRBHPOF, "addrbhpof", "addb", 32,
1203     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1204   },
1205 /* subb $regb8,$hash$pof$uimm8 */
1206   {
1207     XC16X_INSN_SUBRBHPOF, "subrbhpof", "subb", 32,
1208     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1209   },
1210 /* addb $regb8,$hash$pag$uimm8 */
1211   {
1212     XC16X_INSN_ADDBRHPAG, "addbrhpag", "addb", 32,
1213     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1214   },
1215 /* subb $regb8,$hash$pag$uimm8 */
1216   {
1217     XC16X_INSN_SUBBRHPAG, "subbrhpag", "subb", 32,
1218     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1219   },
1220 /* addc $reg8,$hash$pof$uimm16 */
1221   {
1222     XC16X_INSN_ADDCRHPOF, "addcrhpof", "addc", 32,
1223     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1224   },
1225 /* subc $reg8,$hash$pof$uimm16 */
1226   {
1227     XC16X_INSN_SUBCRHPOF, "subcrhpof", "subc", 32,
1228     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1229   },
1230 /* addc $reg8,$hash$pag$uimm16 */
1231   {
1232     XC16X_INSN_ADDCBRHPOF, "addcbrhpof", "addc", 32,
1233     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1234   },
1235 /* subc $reg8,$hash$pag$uimm16 */
1236   {
1237     XC16X_INSN_SUBCBRHPOF, "subcbrhpof", "subc", 32,
1238     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1239   },
1240 /* addc $dr,$hash$pof$uimm3 */
1241   {
1242     XC16X_INSN_ADDCRHPOF3, "addcrhpof3", "addc", 16,
1243     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1244   },
1245 /* subc $dr,$hash$pof$uimm3 */
1246   {
1247     XC16X_INSN_SUBCRHPOF3, "subcrhpof3", "subc", 16,
1248     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1249   },
1250 /* addcb $drb,$hash$pag$uimm3 */
1251   {
1252     XC16X_INSN_ADDCBRHPAG3, "addcbrhpag3", "addcb", 16,
1253     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1254   },
1255 /* subcb $drb,$hash$pag$uimm3 */
1256   {
1257     XC16X_INSN_SUBCBRHPAG3, "subcbrhpag3", "subcb", 16,
1258     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1259   },
1260 /* addc $dr,$hash$pag$uimm3 */
1261   {
1262     XC16X_INSN_ADDCRHPAG3, "addcrhpag3", "addc", 16,
1263     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1264   },
1265 /* subc $dr,$hash$pag$uimm3 */
1266   {
1267     XC16X_INSN_SUBCRHPAG3, "subcrhpag3", "subc", 16,
1268     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1269   },
1270 /* addcb $drb,$hash$pof$uimm3 */
1271   {
1272     XC16X_INSN_ADDCBRHPOF3, "addcbrhpof3", "addcb", 16,
1273     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1274   },
1275 /* subcb $drb,$hash$pof$uimm3 */
1276   {
1277     XC16X_INSN_SUBCBRHPOF3, "subcbrhpof3", "subcb", 16,
1278     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1279   },
1280 /* addcb $regb8,$hash$pof$uimm8 */
1281   {
1282     XC16X_INSN_ADDCRBHPOF, "addcrbhpof", "addcb", 32,
1283     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1284   },
1285 /* subcb $regb8,$hash$pof$uimm8 */
1286   {
1287     XC16X_INSN_SUBCRBHPOF, "subcrbhpof", "subcb", 32,
1288     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1289   },
1290 /* addcb $regb8,$hash$pag$uimm8 */
1291   {
1292     XC16X_INSN_ADDCBRHPAG, "addcbrhpag", "addcb", 32,
1293     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1294   },
1295 /* subcb $regb8,$hash$pag$uimm8 */
1296   {
1297     XC16X_INSN_SUBCBRHPAG, "subcbrhpag", "subcb", 32,
1298     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1299   },
1300 /* add $dr,$hash$uimm3 */
1301   {
1302     XC16X_INSN_ADDRI, "addri", "add", 16,
1303     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1304   },
1305 /* sub $dr,$hash$uimm3 */
1306   {
1307     XC16X_INSN_SUBRI, "subri", "sub", 16,
1308     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1309   },
1310 /* addb $drb,$hash$uimm3 */
1311   {
1312     XC16X_INSN_ADDBRI, "addbri", "addb", 16,
1313     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1314   },
1315 /* subb $drb,$hash$uimm3 */
1316   {
1317     XC16X_INSN_SUBBRI, "subbri", "subb", 16,
1318     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1319   },
1320 /* add $reg8,$hash$uimm16 */
1321   {
1322     XC16X_INSN_ADDRIM, "addrim", "add", 32,
1323     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1324   },
1325 /* sub $reg8,$hash$uimm16 */
1326   {
1327     XC16X_INSN_SUBRIM, "subrim", "sub", 32,
1328     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1329   },
1330 /* addb $regb8,$hash$uimm8 */
1331   {
1332     XC16X_INSN_ADDBRIM, "addbrim", "addb", 32,
1333     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1334   },
1335 /* subb $regb8,$hash$uimm8 */
1336   {
1337     XC16X_INSN_SUBBRIM, "subbrim", "subb", 32,
1338     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1339   },
1340 /* addc $dr,$hash$uimm3 */
1341   {
1342     XC16X_INSN_ADDCRI, "addcri", "addc", 16,
1343     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1344   },
1345 /* subc $dr,$hash$uimm3 */
1346   {
1347     XC16X_INSN_SUBCRI, "subcri", "subc", 16,
1348     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1349   },
1350 /* addcb $drb,$hash$uimm3 */
1351   {
1352     XC16X_INSN_ADDCBRI, "addcbri", "addcb", 16,
1353     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1354   },
1355 /* subcb $drb,$hash$uimm3 */
1356   {
1357     XC16X_INSN_SUBCBRI, "subcbri", "subcb", 16,
1358     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1359   },
1360 /* addc $reg8,$hash$uimm16 */
1361   {
1362     XC16X_INSN_ADDCRIM, "addcrim", "addc", 32,
1363     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1364   },
1365 /* subc $reg8,$hash$uimm16 */
1366   {
1367     XC16X_INSN_SUBCRIM, "subcrim", "subc", 32,
1368     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1369   },
1370 /* addcb $regb8,$hash$uimm8 */
1371   {
1372     XC16X_INSN_ADDCBRIM, "addcbrim", "addcb", 32,
1373     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1374   },
1375 /* subcb $regb8,$hash$uimm8 */
1376   {
1377     XC16X_INSN_SUBCBRIM, "subcbrim", "subcb", 32,
1378     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1379   },
1380 /* add $dr,$sr */
1381   {
1382     XC16X_INSN_ADDR, "addr", "add", 16,
1383     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1384   },
1385 /* sub $dr,$sr */
1386   {
1387     XC16X_INSN_SUBR, "subr", "sub", 16,
1388     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1389   },
1390 /* addb $drb,$srb */
1391   {
1392     XC16X_INSN_ADDBR, "addbr", "addb", 16,
1393     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1394   },
1395 /* subb $drb,$srb */
1396   {
1397     XC16X_INSN_SUBBR, "subbr", "subb", 16,
1398     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1399   },
1400 /* add $dr,[$sr2] */
1401   {
1402     XC16X_INSN_ADD2, "add2", "add", 16,
1403     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1404   },
1405 /* sub $dr,[$sr2] */
1406   {
1407     XC16X_INSN_SUB2, "sub2", "sub", 16,
1408     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1409   },
1410 /* addb $drb,[$sr2] */
1411   {
1412     XC16X_INSN_ADDB2, "addb2", "addb", 16,
1413     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1414   },
1415 /* subb $drb,[$sr2] */
1416   {
1417     XC16X_INSN_SUBB2, "subb2", "subb", 16,
1418     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1419   },
1420 /* add $dr,[$sr2+] */
1421   {
1422     XC16X_INSN_ADD2I, "add2i", "add", 16,
1423     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1424   },
1425 /* sub $dr,[$sr2+] */
1426   {
1427     XC16X_INSN_SUB2I, "sub2i", "sub", 16,
1428     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1429   },
1430 /* addb $drb,[$sr2+] */
1431   {
1432     XC16X_INSN_ADDB2I, "addb2i", "addb", 16,
1433     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1434   },
1435 /* subb $drb,[$sr2+] */
1436   {
1437     XC16X_INSN_SUBB2I, "subb2i", "subb", 16,
1438     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1439   },
1440 /* addc $dr,$sr */
1441   {
1442     XC16X_INSN_ADDCR, "addcr", "addc", 16,
1443     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1444   },
1445 /* subc $dr,$sr */
1446   {
1447     XC16X_INSN_SUBCR, "subcr", "subc", 16,
1448     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1449   },
1450 /* addcb $drb,$srb */
1451   {
1452     XC16X_INSN_ADDBCR, "addbcr", "addcb", 16,
1453     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1454   },
1455 /* subcb $drb,$srb */
1456   {
1457     XC16X_INSN_SUBBCR, "subbcr", "subcb", 16,
1458     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1459   },
1460 /* addc $dr,[$sr2] */
1461   {
1462     XC16X_INSN_ADDCR2, "addcr2", "addc", 16,
1463     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1464   },
1465 /* subc $dr,[$sr2] */
1466   {
1467     XC16X_INSN_SUBCR2, "subcr2", "subc", 16,
1468     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1469   },
1470 /* addcb $drb,[$sr2] */
1471   {
1472     XC16X_INSN_ADDBCR2, "addbcr2", "addcb", 16,
1473     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1474   },
1475 /* subcb $drb,[$sr2] */
1476   {
1477     XC16X_INSN_SUBBCR2, "subbcr2", "subcb", 16,
1478     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1479   },
1480 /* addc $dr,[$sr2+] */
1481   {
1482     XC16X_INSN_ADDCR2I, "addcr2i", "addc", 16,
1483     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1484   },
1485 /* subc $dr,[$sr2+] */
1486   {
1487     XC16X_INSN_SUBCR2I, "subcr2i", "subc", 16,
1488     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1489   },
1490 /* addcb $drb,[$sr2+] */
1491   {
1492     XC16X_INSN_ADDBCR2I, "addbcr2i", "addcb", 16,
1493     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1494   },
1495 /* subcb $drb,[$sr2+] */
1496   {
1497     XC16X_INSN_SUBBCR2I, "subbcr2i", "subcb", 16,
1498     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1499   },
1500 /* add $regmem8,$memgr8 */
1501   {
1502     XC16X_INSN_ADDRM2, "addrm2", "add", 32,
1503     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1504   },
1505 /* add $memgr8,$regmem8 */
1506   {
1507     XC16X_INSN_ADDRM3, "addrm3", "add", 32,
1508     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1509   },
1510 /* add $reg8,$memory */
1511   {
1512     XC16X_INSN_ADDRM, "addrm", "add", 32,
1513     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1514   },
1515 /* add $memory,$reg8 */
1516   {
1517     XC16X_INSN_ADDRM1, "addrm1", "add", 32,
1518     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1519   },
1520 /* sub $regmem8,$memgr8 */
1521   {
1522     XC16X_INSN_SUBRM3, "subrm3", "sub", 32,
1523     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1524   },
1525 /* sub $memgr8,$regmem8 */
1526   {
1527     XC16X_INSN_SUBRM2, "subrm2", "sub", 32,
1528     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1529   },
1530 /* sub $reg8,$memory */
1531   {
1532     XC16X_INSN_SUBRM1, "subrm1", "sub", 32,
1533     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1534   },
1535 /* sub $memory,$reg8 */
1536   {
1537     XC16X_INSN_SUBRM, "subrm", "sub", 32,
1538     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1539   },
1540 /* addb $regbmem8,$memgr8 */
1541   {
1542     XC16X_INSN_ADDBRM2, "addbrm2", "addb", 32,
1543     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1544   },
1545 /* addb $memgr8,$regbmem8 */
1546   {
1547     XC16X_INSN_ADDBRM3, "addbrm3", "addb", 32,
1548     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1549   },
1550 /* addb $regb8,$memory */
1551   {
1552     XC16X_INSN_ADDBRM, "addbrm", "addb", 32,
1553     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1554   },
1555 /* addb $memory,$regb8 */
1556   {
1557     XC16X_INSN_ADDBRM1, "addbrm1", "addb", 32,
1558     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1559   },
1560 /* subb $regbmem8,$memgr8 */
1561   {
1562     XC16X_INSN_SUBBRM3, "subbrm3", "subb", 32,
1563     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1564   },
1565 /* subb $memgr8,$regbmem8 */
1566   {
1567     XC16X_INSN_SUBBRM2, "subbrm2", "subb", 32,
1568     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1569   },
1570 /* subb $regb8,$memory */
1571   {
1572     XC16X_INSN_SUBBRM1, "subbrm1", "subb", 32,
1573     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1574   },
1575 /* subb $memory,$regb8 */
1576   {
1577     XC16X_INSN_SUBBRM, "subbrm", "subb", 32,
1578     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1579   },
1580 /* addc $regmem8,$memgr8 */
1581   {
1582     XC16X_INSN_ADDCRM2, "addcrm2", "addc", 32,
1583     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1584   },
1585 /* addc $memgr8,$regmem8 */
1586   {
1587     XC16X_INSN_ADDCRM3, "addcrm3", "addc", 32,
1588     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1589   },
1590 /* addc $reg8,$memory */
1591   {
1592     XC16X_INSN_ADDCRM, "addcrm", "addc", 32,
1593     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1594   },
1595 /* addc $memory,$reg8 */
1596   {
1597     XC16X_INSN_ADDCRM1, "addcrm1", "addc", 32,
1598     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1599   },
1600 /* subc $regmem8,$memgr8 */
1601   {
1602     XC16X_INSN_SUBCRM3, "subcrm3", "subc", 32,
1603     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1604   },
1605 /* subc $memgr8,$regmem8 */
1606   {
1607     XC16X_INSN_SUBCRM2, "subcrm2", "subc", 32,
1608     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1609   },
1610 /* subc $reg8,$memory */
1611   {
1612     XC16X_INSN_SUBCRM1, "subcrm1", "subc", 32,
1613     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1614   },
1615 /* subc $memory,$reg8 */
1616   {
1617     XC16X_INSN_SUBCRM, "subcrm", "subc", 32,
1618     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1619   },
1620 /* addcb $regbmem8,$memgr8 */
1621   {
1622     XC16X_INSN_ADDCBRM2, "addcbrm2", "addcb", 32,
1623     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1624   },
1625 /* addcb $memgr8,$regbmem8 */
1626   {
1627     XC16X_INSN_ADDCBRM3, "addcbrm3", "addcb", 32,
1628     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1629   },
1630 /* addcb $regb8,$memory */
1631   {
1632     XC16X_INSN_ADDCBRM, "addcbrm", "addcb", 32,
1633     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1634   },
1635 /* addcb $memory,$regb8 */
1636   {
1637     XC16X_INSN_ADDCBRM1, "addcbrm1", "addcb", 32,
1638     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1639   },
1640 /* subcb $regbmem8,$memgr8 */
1641   {
1642     XC16X_INSN_SUBCBRM3, "subcbrm3", "subcb", 32,
1643     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1644   },
1645 /* subcb $memgr8,$regbmem8 */
1646   {
1647     XC16X_INSN_SUBCBRM2, "subcbrm2", "subcb", 32,
1648     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1649   },
1650 /* subcb $regb8,$memory */
1651   {
1652     XC16X_INSN_SUBCBRM1, "subcbrm1", "subcb", 32,
1653     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1654   },
1655 /* subcb $memory,$regb8 */
1656   {
1657     XC16X_INSN_SUBCBRM, "subcbrm", "subcb", 32,
1658     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1659   },
1660 /* mul $src1,$src2 */
1661   {
1662     XC16X_INSN_MULS, "muls", "mul", 16,
1663     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1664   },
1665 /* mulu $src1,$src2 */
1666   {
1667     XC16X_INSN_MULU, "mulu", "mulu", 16,
1668     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1669   },
1670 /* div $srdiv */
1671   {
1672     XC16X_INSN_DIV, "div", "div", 16,
1673     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1674   },
1675 /* divl $srdiv */
1676   {
1677     XC16X_INSN_DIVL, "divl", "divl", 16,
1678     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1679   },
1680 /* divlu $srdiv */
1681   {
1682     XC16X_INSN_DIVLU, "divlu", "divlu", 16,
1683     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1684   },
1685 /* divu $srdiv */
1686   {
1687     XC16X_INSN_DIVU, "divu", "divu", 16,
1688     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1689   },
1690 /* cpl $dr */
1691   {
1692     XC16X_INSN_CPL, "cpl", "cpl", 16,
1693     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1694   },
1695 /* cplb $drb */
1696   {
1697     XC16X_INSN_CPLB, "cplb", "cplb", 16,
1698     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1699   },
1700 /* neg $dr */
1701   {
1702     XC16X_INSN_NEG, "neg", "neg", 16,
1703     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1704   },
1705 /* negb $drb */
1706   {
1707     XC16X_INSN_NEGB, "negb", "negb", 16,
1708     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1709   },
1710 /* and $dr,$sr */
1711   {
1712     XC16X_INSN_ANDR, "andr", "and", 16,
1713     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1714   },
1715 /* or $dr,$sr */
1716   {
1717     XC16X_INSN_ORR, "orr", "or", 16,
1718     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1719   },
1720 /* xor $dr,$sr */
1721   {
1722     XC16X_INSN_XORR, "xorr", "xor", 16,
1723     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1724   },
1725 /* andb $drb,$srb */
1726   {
1727     XC16X_INSN_ANDBR, "andbr", "andb", 16,
1728     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1729   },
1730 /* orb $drb,$srb */
1731   {
1732     XC16X_INSN_ORBR, "orbr", "orb", 16,
1733     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1734   },
1735 /* xorb $drb,$srb */
1736   {
1737     XC16X_INSN_XORBR, "xorbr", "xorb", 16,
1738     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1739   },
1740 /* and $dr,$hash$uimm3 */
1741   {
1742     XC16X_INSN_ANDRI, "andri", "and", 16,
1743     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1744   },
1745 /* or $dr,$hash$uimm3 */
1746   {
1747     XC16X_INSN_ORRI, "orri", "or", 16,
1748     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1749   },
1750 /* xor $dr,$hash$uimm3 */
1751   {
1752     XC16X_INSN_XORRI, "xorri", "xor", 16,
1753     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1754   },
1755 /* andb $drb,$hash$uimm3 */
1756   {
1757     XC16X_INSN_ANDBRI, "andbri", "andb", 16,
1758     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1759   },
1760 /* orb $drb,$hash$uimm3 */
1761   {
1762     XC16X_INSN_ORBRI, "orbri", "orb", 16,
1763     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1764   },
1765 /* xorb $drb,$hash$uimm3 */
1766   {
1767     XC16X_INSN_XORBRI, "xorbri", "xorb", 16,
1768     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1769   },
1770 /* and $reg8,$hash$uimm16 */
1771   {
1772     XC16X_INSN_ANDRIM, "andrim", "and", 32,
1773     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1774   },
1775 /* or $reg8,$hash$uimm16 */
1776   {
1777     XC16X_INSN_ORRIM, "orrim", "or", 32,
1778     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1779   },
1780 /* xor $reg8,$hash$uimm16 */
1781   {
1782     XC16X_INSN_XORRIM, "xorrim", "xor", 32,
1783     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1784   },
1785 /* andb $regb8,$hash$uimm8 */
1786   {
1787     XC16X_INSN_ANDBRIM, "andbrim", "andb", 32,
1788     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1789   },
1790 /* orb $regb8,$hash$uimm8 */
1791   {
1792     XC16X_INSN_ORBRIM, "orbrim", "orb", 32,
1793     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1794   },
1795 /* xorb $regb8,$hash$uimm8 */
1796   {
1797     XC16X_INSN_XORBRIM, "xorbrim", "xorb", 32,
1798     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1799   },
1800 /* and $dr,[$sr2] */
1801   {
1802     XC16X_INSN_AND2, "and2", "and", 16,
1803     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1804   },
1805 /* or $dr,[$sr2] */
1806   {
1807     XC16X_INSN_OR2, "or2", "or", 16,
1808     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1809   },
1810 /* xor $dr,[$sr2] */
1811   {
1812     XC16X_INSN_XOR2, "xor2", "xor", 16,
1813     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1814   },
1815 /* andb $drb,[$sr2] */
1816   {
1817     XC16X_INSN_ANDB2, "andb2", "andb", 16,
1818     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1819   },
1820 /* orb $drb,[$sr2] */
1821   {
1822     XC16X_INSN_ORB2, "orb2", "orb", 16,
1823     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1824   },
1825 /* xorb $drb,[$sr2] */
1826   {
1827     XC16X_INSN_XORB2, "xorb2", "xorb", 16,
1828     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1829   },
1830 /* and $dr,[$sr2+] */
1831   {
1832     XC16X_INSN_AND2I, "and2i", "and", 16,
1833     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1834   },
1835 /* or $dr,[$sr2+] */
1836   {
1837     XC16X_INSN_OR2I, "or2i", "or", 16,
1838     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1839   },
1840 /* xor $dr,[$sr2+] */
1841   {
1842     XC16X_INSN_XOR2I, "xor2i", "xor", 16,
1843     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1844   },
1845 /* andb $drb,[$sr2+] */
1846   {
1847     XC16X_INSN_ANDB2I, "andb2i", "andb", 16,
1848     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1849   },
1850 /* orb $drb,[$sr2+] */
1851   {
1852     XC16X_INSN_ORB2I, "orb2i", "orb", 16,
1853     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1854   },
1855 /* xorb $drb,[$sr2+] */
1856   {
1857     XC16X_INSN_XORB2I, "xorb2i", "xorb", 16,
1858     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1859   },
1860 /* and $pof$reg8,$upof16 */
1861   {
1862     XC16X_INSN_ANDPOFR, "andpofr", "and", 32,
1863     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1864   },
1865 /* or $pof$reg8,$upof16 */
1866   {
1867     XC16X_INSN_ORPOFR, "orpofr", "or", 32,
1868     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1869   },
1870 /* xor $pof$reg8,$upof16 */
1871   {
1872     XC16X_INSN_XORPOFR, "xorpofr", "xor", 32,
1873     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1874   },
1875 /* andb $pof$regb8,$upof16 */
1876   {
1877     XC16X_INSN_ANDBPOFR, "andbpofr", "andb", 32,
1878     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1879   },
1880 /* orb $pof$regb8,$upof16 */
1881   {
1882     XC16X_INSN_ORBPOFR, "orbpofr", "orb", 32,
1883     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1884   },
1885 /* xorb $pof$regb8,$upof16 */
1886   {
1887     XC16X_INSN_XORBPOFR, "xorbpofr", "xorb", 32,
1888     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1889   },
1890 /* and $pof$upof16,$reg8 */
1891   {
1892     XC16X_INSN_ANDRPOFR, "andrpofr", "and", 32,
1893     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1894   },
1895 /* or $pof$upof16,$reg8 */
1896   {
1897     XC16X_INSN_ORRPOFR, "orrpofr", "or", 32,
1898     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1899   },
1900 /* xor $pof$upof16,$reg8 */
1901   {
1902     XC16X_INSN_XORRPOFR, "xorrpofr", "xor", 32,
1903     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1904   },
1905 /* andb $pof$upof16,$regb8 */
1906   {
1907     XC16X_INSN_ANDBRPOFR, "andbrpofr", "andb", 32,
1908     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1909   },
1910 /* orb $pof$upof16,$regb8 */
1911   {
1912     XC16X_INSN_ORBRPOFR, "orbrpofr", "orb", 32,
1913     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1914   },
1915 /* xorb $pof$upof16,$regb8 */
1916   {
1917     XC16X_INSN_XORBRPOFR, "xorbrpofr", "xorb", 32,
1918     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1919   },
1920 /* and $regmem8,$memgr8 */
1921   {
1922     XC16X_INSN_ANDRM2, "andrm2", "and", 32,
1923     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1924   },
1925 /* and $memgr8,$regmem8 */
1926   {
1927     XC16X_INSN_ANDRM3, "andrm3", "and", 32,
1928     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1929   },
1930 /* and $reg8,$memory */
1931   {
1932     XC16X_INSN_ANDRM, "andrm", "and", 32,
1933     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1934   },
1935 /* and $memory,$reg8 */
1936   {
1937     XC16X_INSN_ANDRM1, "andrm1", "and", 32,
1938     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1939   },
1940 /* or $regmem8,$memgr8 */
1941   {
1942     XC16X_INSN_ORRM3, "orrm3", "or", 32,
1943     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1944   },
1945 /* or $memgr8,$regmem8 */
1946   {
1947     XC16X_INSN_ORRM2, "orrm2", "or", 32,
1948     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1949   },
1950 /* or $reg8,$memory */
1951   {
1952     XC16X_INSN_ORRM1, "orrm1", "or", 32,
1953     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1954   },
1955 /* or $memory,$reg8 */
1956   {
1957     XC16X_INSN_ORRM, "orrm", "or", 32,
1958     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1959   },
1960 /* xor $regmem8,$memgr8 */
1961   {
1962     XC16X_INSN_XORRM3, "xorrm3", "xor", 32,
1963     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1964   },
1965 /* xor $memgr8,$regmem8 */
1966   {
1967     XC16X_INSN_XORRM2, "xorrm2", "xor", 32,
1968     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1969   },
1970 /* xor $reg8,$memory */
1971   {
1972     XC16X_INSN_XORRM1, "xorrm1", "xor", 32,
1973     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1974   },
1975 /* xor $memory,$reg8 */
1976   {
1977     XC16X_INSN_XORRM, "xorrm", "xor", 32,
1978     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1979   },
1980 /* andb $regbmem8,$memgr8 */
1981   {
1982     XC16X_INSN_ANDBRM2, "andbrm2", "andb", 32,
1983     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1984   },
1985 /* andb $memgr8,$regbmem8 */
1986   {
1987     XC16X_INSN_ANDBRM3, "andbrm3", "andb", 32,
1988     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1989   },
1990 /* andb $regb8,$memory */
1991   {
1992     XC16X_INSN_ANDBRM, "andbrm", "andb", 32,
1993     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1994   },
1995 /* andb $memory,$regb8 */
1996   {
1997     XC16X_INSN_ANDBRM1, "andbrm1", "andb", 32,
1998     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
1999   },
2000 /* orb $regbmem8,$memgr8 */
2001   {
2002     XC16X_INSN_ORBRM3, "orbrm3", "orb", 32,
2003     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2004   },
2005 /* orb $memgr8,$regbmem8 */
2006   {
2007     XC16X_INSN_ORBRM2, "orbrm2", "orb", 32,
2008     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2009   },
2010 /* orb $regb8,$memory */
2011   {
2012     XC16X_INSN_ORBRM1, "orbrm1", "orb", 32,
2013     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2014   },
2015 /* orb $memory,$regb8 */
2016   {
2017     XC16X_INSN_ORBRM, "orbrm", "orb", 32,
2018     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2019   },
2020 /* xorb $regbmem8,$memgr8 */
2021   {
2022     XC16X_INSN_XORBRM3, "xorbrm3", "xorb", 32,
2023     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2024   },
2025 /* xorb $memgr8,$regbmem8 */
2026   {
2027     XC16X_INSN_XORBRM2, "xorbrm2", "xorb", 32,
2028     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2029   },
2030 /* xorb $regb8,$memory */
2031   {
2032     XC16X_INSN_XORBRM1, "xorbrm1", "xorb", 32,
2033     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2034   },
2035 /* xorb $memory,$regb8 */
2036   {
2037     XC16X_INSN_XORBRM, "xorbrm", "xorb", 32,
2038     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2039   },
2040 /* mov $dr,$sr */
2041   {
2042     XC16X_INSN_MOVR, "movr", "mov", 16,
2043     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2044   },
2045 /* movb $drb,$srb */
2046   {
2047     XC16X_INSN_MOVRB, "movrb", "movb", 16,
2048     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2049   },
2050 /* mov $dri,$hash$u4 */
2051   {
2052     XC16X_INSN_MOVRI, "movri", "mov", 16,
2053     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2054   },
2055 /* movb $srb,$hash$u4 */
2056   {
2057     XC16X_INSN_MOVBRI, "movbri", "movb", 16,
2058     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2059   },
2060 /* mov $reg8,$hash$uimm16 */
2061   {
2062     XC16X_INSN_MOVI, "movi", "mov", 32,
2063     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2064   },
2065 /* movb $regb8,$hash$uimm8 */
2066   {
2067     XC16X_INSN_MOVBI, "movbi", "movb", 32,
2068     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2069   },
2070 /* mov $dr,[$sr] */
2071   {
2072     XC16X_INSN_MOVR2, "movr2", "mov", 16,
2073     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2074   },
2075 /* movb $drb,[$sr] */
2076   {
2077     XC16X_INSN_MOVBR2, "movbr2", "movb", 16,
2078     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2079   },
2080 /* mov [$sr],$dr */
2081   {
2082     XC16X_INSN_MOVRI2, "movri2", "mov", 16,
2083     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2084   },
2085 /* movb [$sr],$drb */
2086   {
2087     XC16X_INSN_MOVBRI2, "movbri2", "movb", 16,
2088     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2089   },
2090 /* mov [-$sr],$dr */
2091   {
2092     XC16X_INSN_MOVRI3, "movri3", "mov", 16,
2093     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2094   },
2095 /* movb [-$sr],$drb */
2096   {
2097     XC16X_INSN_MOVBRI3, "movbri3", "movb", 16,
2098     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2099   },
2100 /* mov $dr,[$sr+] */
2101   {
2102     XC16X_INSN_MOV2I, "mov2i", "mov", 16,
2103     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2104   },
2105 /* movb $drb,[$sr+] */
2106   {
2107     XC16X_INSN_MOVB2I, "movb2i", "movb", 16,
2108     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2109   },
2110 /* mov [$dr],[$sr] */
2111   {
2112     XC16X_INSN_MOV6I, "mov6i", "mov", 16,
2113     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2114   },
2115 /* movb [$dr],[$sr] */
2116   {
2117     XC16X_INSN_MOVB6I, "movb6i", "movb", 16,
2118     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2119   },
2120 /* mov [$dr+],[$sr] */
2121   {
2122     XC16X_INSN_MOV7I, "mov7i", "mov", 16,
2123     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2124   },
2125 /* movb [$dr+],[$sr] */
2126   {
2127     XC16X_INSN_MOVB7I, "movb7i", "movb", 16,
2128     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2129   },
2130 /* mov [$dr],[$sr+] */
2131   {
2132     XC16X_INSN_MOV8I, "mov8i", "mov", 16,
2133     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2134   },
2135 /* movb [$dr],[$sr+] */
2136   {
2137     XC16X_INSN_MOVB8I, "movb8i", "movb", 16,
2138     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2139   },
2140 /* mov $dr,[$sr+$hash$uimm16] */
2141   {
2142     XC16X_INSN_MOV9I, "mov9i", "mov", 32,
2143     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2144   },
2145 /* movb $drb,[$sr+$hash$uimm16] */
2146   {
2147     XC16X_INSN_MOVB9I, "movb9i", "movb", 32,
2148     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2149   },
2150 /* mov [$sr+$hash$uimm16],$dr */
2151   {
2152     XC16X_INSN_MOV10I, "mov10i", "mov", 32,
2153     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2154   },
2155 /* movb [$sr+$hash$uimm16],$drb */
2156   {
2157     XC16X_INSN_MOVB10I, "movb10i", "movb", 32,
2158     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2159   },
2160 /* mov [$src2],$memory */
2161   {
2162     XC16X_INSN_MOVRI11, "movri11", "mov", 32,
2163     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2164   },
2165 /* movb [$src2],$memory */
2166   {
2167     XC16X_INSN_MOVBRI11, "movbri11", "movb", 32,
2168     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2169   },
2170 /* mov $memory,[$src2] */
2171   {
2172     XC16X_INSN_MOVRI12, "movri12", "mov", 32,
2173     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2174   },
2175 /* movb $memory,[$src2] */
2176   {
2177     XC16X_INSN_MOVBRI12, "movbri12", "movb", 32,
2178     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2179   },
2180 /* mov $regoff8,$hash$pof$upof16 */
2181   {
2182     XC16X_INSN_MOVEHM5, "movehm5", "mov", 32,
2183     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2184   },
2185 /* mov $regoff8,$hash$pag$upag16 */
2186   {
2187     XC16X_INSN_MOVEHM6, "movehm6", "mov", 32,
2188     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2189   },
2190 /* mov $regoff8,$hash$segm$useg16 */
2191   {
2192     XC16X_INSN_MOVEHM7, "movehm7", "mov", 32,
2193     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2194   },
2195 /* mov $regoff8,$hash$sof$usof16 */
2196   {
2197     XC16X_INSN_MOVEHM8, "movehm8", "mov", 32,
2198     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2199   },
2200 /* movb $regb8,$hash$pof$uimm8 */
2201   {
2202     XC16X_INSN_MOVEHM9, "movehm9", "movb", 32,
2203     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2204   },
2205 /* movb $regoff8,$hash$pag$uimm8 */
2206   {
2207     XC16X_INSN_MOVEHM10, "movehm10", "movb", 32,
2208     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2209   },
2210 /* mov $regoff8,$pof$upof16 */
2211   {
2212     XC16X_INSN_MOVRMP, "movrmp", "mov", 32,
2213     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2214   },
2215 /* movb $regb8,$pof$upof16 */
2216   {
2217     XC16X_INSN_MOVRMP1, "movrmp1", "movb", 32,
2218     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2219   },
2220 /* mov $regoff8,$pag$upag16 */
2221   {
2222     XC16X_INSN_MOVRMP2, "movrmp2", "mov", 32,
2223     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2224   },
2225 /* movb $regb8,$pag$upag16 */
2226   {
2227     XC16X_INSN_MOVRMP3, "movrmp3", "movb", 32,
2228     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2229   },
2230 /* mov $pof$upof16,$regoff8 */
2231   {
2232     XC16X_INSN_MOVRMP4, "movrmp4", "mov", 32,
2233     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2234   },
2235 /* movb $pof$upof16,$regb8 */
2236   {
2237     XC16X_INSN_MOVRMP5, "movrmp5", "movb", 32,
2238     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2239   },
2240 /* mov $dri,$hash$pof$u4 */
2241   {
2242     XC16X_INSN_MOVEHM1, "movehm1", "mov", 16,
2243     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2244   },
2245 /* movb $srb,$hash$pof$u4 */
2246   {
2247     XC16X_INSN_MOVEHM2, "movehm2", "movb", 16,
2248     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2249   },
2250 /* mov $dri,$hash$pag$u4 */
2251   {
2252     XC16X_INSN_MOVEHM3, "movehm3", "mov", 16,
2253     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2254   },
2255 /* movb $srb,$hash$pag$u4 */
2256   {
2257     XC16X_INSN_MOVEHM4, "movehm4", "movb", 16,
2258     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2259   },
2260 /* mov $regmem8,$memgr8 */
2261   {
2262     XC16X_INSN_MVE12, "mve12", "mov", 32,
2263     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2264   },
2265 /* mov $memgr8,$regmem8 */
2266   {
2267     XC16X_INSN_MVE13, "mve13", "mov", 32,
2268     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2269   },
2270 /* mov $reg8,$memory */
2271   {
2272     XC16X_INSN_MOVER12, "mover12", "mov", 32,
2273     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2274   },
2275 /* mov $memory,$reg8 */
2276   {
2277     XC16X_INSN_MVR13, "mvr13", "mov", 32,
2278     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2279   },
2280 /* movb $regbmem8,$memgr8 */
2281   {
2282     XC16X_INSN_MVER12, "mver12", "movb", 32,
2283     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2284   },
2285 /* movb $memgr8,$regbmem8 */
2286   {
2287     XC16X_INSN_MVER13, "mver13", "movb", 32,
2288     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2289   },
2290 /* movb $regb8,$memory */
2291   {
2292     XC16X_INSN_MOVR12, "movr12", "movb", 32,
2293     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2294   },
2295 /* movb $memory,$regb8 */
2296   {
2297     XC16X_INSN_MOVR13, "movr13", "movb", 32,
2298     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2299   },
2300 /* movbs $sr,$drb */
2301   {
2302     XC16X_INSN_MOVBSRR, "movbsrr", "movbs", 16,
2303     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2304   },
2305 /* movbz $sr,$drb */
2306   {
2307     XC16X_INSN_MOVBZRR, "movbzrr", "movbz", 16,
2308     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2309   },
2310 /* movbs $regmem8,$pof$upof16 */
2311   {
2312     XC16X_INSN_MOVBSRPOFM, "movbsrpofm", "movbs", 32,
2313     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2314   },
2315 /* movbs $pof$upof16,$regbmem8 */
2316   {
2317     XC16X_INSN_MOVBSPOFMR, "movbspofmr", "movbs", 32,
2318     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2319   },
2320 /* movbz $reg8,$pof$upof16 */
2321   {
2322     XC16X_INSN_MOVBZRPOFM, "movbzrpofm", "movbz", 32,
2323     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2324   },
2325 /* movbz $pof$upof16,$regb8 */
2326   {
2327     XC16X_INSN_MOVBZPOFMR, "movbzpofmr", "movbz", 32,
2328     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2329   },
2330 /* movbs $regmem8,$memgr8 */
2331   {
2332     XC16X_INSN_MOVEBS14, "movebs14", "movbs", 32,
2333     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2334   },
2335 /* movbs $memgr8,$regbmem8 */
2336   {
2337     XC16X_INSN_MOVEBS15, "movebs15", "movbs", 32,
2338     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2339   },
2340 /* movbs $reg8,$memory */
2341   {
2342     XC16X_INSN_MOVERBS14, "moverbs14", "movbs", 32,
2343     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2344   },
2345 /* movbs $memory,$regb8 */
2346   {
2347     XC16X_INSN_MOVRBS15, "movrbs15", "movbs", 32,
2348     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2349   },
2350 /* movbz $regmem8,$memgr8 */
2351   {
2352     XC16X_INSN_MOVEBZ14, "movebz14", "movbz", 32,
2353     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2354   },
2355 /* movbz $memgr8,$regbmem8 */
2356   {
2357     XC16X_INSN_MOVEBZ15, "movebz15", "movbz", 32,
2358     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2359   },
2360 /* movbz $reg8,$memory */
2361   {
2362     XC16X_INSN_MOVERBZ14, "moverbz14", "movbz", 32,
2363     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2364   },
2365 /* movbz $memory,$regb8 */
2366   {
2367     XC16X_INSN_MOVRBZ15, "movrbz15", "movbz", 32,
2368     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2369   },
2370 /* movbs $sr,$drb */
2371   {
2372     XC16X_INSN_MOVRBS, "movrbs", "movbs", 16,
2373     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2374   },
2375 /* movbz $sr,$drb */
2376   {
2377     XC16X_INSN_MOVRBZ, "movrbz", "movbz", 16,
2378     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2379   },
2380 /* jmpa+ $extcond,$caddr */
2381   {
2382     XC16X_INSN_JMPA0, "jmpa0", "jmpa+", 32,
2383     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2384   },
2385 /* jmpa $extcond,$caddr */
2386   {
2387     XC16X_INSN_JMPA1, "jmpa1", "jmpa", 32,
2388     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2389   },
2390 /* jmpa- $extcond,$caddr */
2391   {
2392     XC16X_INSN_JMPA_, "jmpa-", "jmpa-", 32,
2393     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2394   },
2395 /* jmpi $icond,[$sr] */
2396   {
2397     XC16X_INSN_JMPI, "jmpi", "jmpi", 16,
2398     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2399   },
2400 /* jmpr $cond,$rel */
2401   {
2402     XC16X_INSN_JMPR_NENZ, "jmpr_nenz", "jmpr", 16,
2403     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2404   },
2405 /* jmpr $cond,$rel */
2406   {
2407     XC16X_INSN_JMPR_SGT, "jmpr_sgt", "jmpr", 16,
2408     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2409   },
2410 /* jmpr $cond,$rel */
2411   {
2412     XC16X_INSN_JMPR_Z, "jmpr_z", "jmpr", 16,
2413     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2414   },
2415 /* jmpr $cond,$rel */
2416   {
2417     XC16X_INSN_JMPR_V, "jmpr_v", "jmpr", 16,
2418     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2419   },
2420 /* jmpr $cond,$rel */
2421   {
2422     XC16X_INSN_JMPR_NV, "jmpr_nv", "jmpr", 16,
2423     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2424   },
2425 /* jmpr $cond,$rel */
2426   {
2427     XC16X_INSN_JMPR_N, "jmpr_n", "jmpr", 16,
2428     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2429   },
2430 /* jmpr $cond,$rel */
2431   {
2432     XC16X_INSN_JMPR_NN, "jmpr_nn", "jmpr", 16,
2433     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2434   },
2435 /* jmpr $cond,$rel */
2436   {
2437     XC16X_INSN_JMPR_C, "jmpr_c", "jmpr", 16,
2438     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2439   },
2440 /* jmpr $cond,$rel */
2441   {
2442     XC16X_INSN_JMPR_NC, "jmpr_nc", "jmpr", 16,
2443     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2444   },
2445 /* jmpr $cond,$rel */
2446   {
2447     XC16X_INSN_JMPR_EQ, "jmpr_eq", "jmpr", 16,
2448     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2449   },
2450 /* jmpr $cond,$rel */
2451   {
2452     XC16X_INSN_JMPR_NE, "jmpr_ne", "jmpr", 16,
2453     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2454   },
2455 /* jmpr $cond,$rel */
2456   {
2457     XC16X_INSN_JMPR_ULT, "jmpr_ult", "jmpr", 16,
2458     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2459   },
2460 /* jmpr $cond,$rel */
2461   {
2462     XC16X_INSN_JMPR_ULE, "jmpr_ule", "jmpr", 16,
2463     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2464   },
2465 /* jmpr $cond,$rel */
2466   {
2467     XC16X_INSN_JMPR_UGE, "jmpr_uge", "jmpr", 16,
2468     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2469   },
2470 /* jmpr $cond,$rel */
2471   {
2472     XC16X_INSN_JMPR_UGT, "jmpr_ugt", "jmpr", 16,
2473     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2474   },
2475 /* jmpr $cond,$rel */
2476   {
2477     XC16X_INSN_JMPR_SLE, "jmpr_sle", "jmpr", 16,
2478     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2479   },
2480 /* jmpr $cond,$rel */
2481   {
2482     XC16X_INSN_JMPR_SGE, "jmpr_sge", "jmpr", 16,
2483     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2484   },
2485 /* jmpr $cond,$rel */
2486   {
2487     XC16X_INSN_JMPR_NET, "jmpr_net", "jmpr", 16,
2488     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2489   },
2490 /* jmpr $cond,$rel */
2491   {
2492     XC16X_INSN_JMPR_UC, "jmpr_uc", "jmpr", 16,
2493     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2494   },
2495 /* jmpr $cond,$rel */
2496   {
2497     XC16X_INSN_JMPR_SLT, "jmpr_slt", "jmpr", 16,
2498     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2499   },
2500 /* jmps $hash$segm$useg8,$hash$sof$usof16 */
2501   {
2502     XC16X_INSN_JMPSEG, "jmpseg", "jmps", 32,
2503     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2504   },
2505 /* jmps $seg,$caddr */
2506   {
2507     XC16X_INSN_JMPS, "jmps", "jmps", 32,
2508     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2509   },
2510 /* jb $genreg$dot$qlobit,$relhi */
2511   {
2512     XC16X_INSN_JB, "jb", "jb", 32,
2513     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2514   },
2515 /* jbc $genreg$dot$qlobit,$relhi */
2516   {
2517     XC16X_INSN_JBC, "jbc", "jbc", 32,
2518     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2519   },
2520 /* jnb $genreg$dot$qlobit,$relhi */
2521   {
2522     XC16X_INSN_JNB, "jnb", "jnb", 32,
2523     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2524   },
2525 /* jnbs $genreg$dot$qlobit,$relhi */
2526   {
2527     XC16X_INSN_JNBS, "jnbs", "jnbs", 32,
2528     { 0|A(UNCOND_CTI)|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2529   },
2530 /* calla+ $extcond,$caddr */
2531   {
2532     XC16X_INSN_CALLA0, "calla0", "calla+", 32,
2533     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2534   },
2535 /* calla $extcond,$caddr */
2536   {
2537     XC16X_INSN_CALLA1, "calla1", "calla", 32,
2538     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2539   },
2540 /* calla- $extcond,$caddr */
2541   {
2542     XC16X_INSN_CALLA_, "calla-", "calla-", 32,
2543     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2544   },
2545 /* calli $icond,[$sr] */
2546   {
2547     XC16X_INSN_CALLI, "calli", "calli", 16,
2548     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2549   },
2550 /* callr $rel */
2551   {
2552     XC16X_INSN_CALLR, "callr", "callr", 16,
2553     { 0|A(COND_CTI)|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2554   },
2555 /* calls $hash$segm$useg8,$hash$sof$usof16 */
2556   {
2557     XC16X_INSN_CALLSEG, "callseg", "calls", 32,
2558     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2559   },
2560 /* calls $seg,$caddr */
2561   {
2562     XC16X_INSN_CALLS, "calls", "calls", 32,
2563     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2564   },
2565 /* pcall $reg8,$caddr */
2566   {
2567     XC16X_INSN_PCALL, "pcall", "pcall", 32,
2568     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2569   },
2570 /* trap $hash$uimm7 */
2571   {
2572     XC16X_INSN_TRAP, "trap", "trap", 16,
2573     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2574   },
2575 /* ret */
2576   {
2577     XC16X_INSN_RET, "ret", "ret", 16,
2578     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2579   },
2580 /* rets */
2581   {
2582     XC16X_INSN_RETS, "rets", "rets", 16,
2583     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2584   },
2585 /* retp $reg8 */
2586   {
2587     XC16X_INSN_RETP, "retp", "retp", 16,
2588     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2589   },
2590 /* reti */
2591   {
2592     XC16X_INSN_RETI, "reti", "reti", 16,
2593     { 0|A(UNCOND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2594   },
2595 /* pop $reg8 */
2596   {
2597     XC16X_INSN_POP, "pop", "pop", 16,
2598     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2599   },
2600 /* push $reg8 */
2601   {
2602     XC16X_INSN_PUSH, "push", "push", 16,
2603     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2604   },
2605 /* scxt $reg8,$hash$uimm16 */
2606   {
2607     XC16X_INSN_SCXTI, "scxti", "scxt", 32,
2608     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2609   },
2610 /* scxt $reg8,$pof$upof16 */
2611   {
2612     XC16X_INSN_SCXTRPOFM, "scxtrpofm", "scxt", 32,
2613     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2614   },
2615 /* scxt $regmem8,$memgr8 */
2616   {
2617     XC16X_INSN_SCXTMG, "scxtmg", "scxt", 32,
2618     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2619   },
2620 /* scxt $reg8,$memory */
2621   {
2622     XC16X_INSN_SCXTM, "scxtm", "scxt", 32,
2623     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2624   },
2625 /* nop */
2626   {
2627     XC16X_INSN_NOP, "nop", "nop", 16,
2628     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2629   },
2630 /* srst */
2631   {
2632     XC16X_INSN_SRSTM, "srstm", "srst", 32,
2633     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2634   },
2635 /* idle */
2636   {
2637     XC16X_INSN_IDLEM, "idlem", "idle", 32,
2638     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2639   },
2640 /* pwrdn */
2641   {
2642     XC16X_INSN_PWRDNM, "pwrdnm", "pwrdn", 32,
2643     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2644   },
2645 /* diswdt */
2646   {
2647     XC16X_INSN_DISWDTM, "diswdtm", "diswdt", 32,
2648     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2649   },
2650 /* enwdt */
2651   {
2652     XC16X_INSN_ENWDTM, "enwdtm", "enwdt", 32,
2653     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2654   },
2655 /* einit */
2656   {
2657     XC16X_INSN_EINITM, "einitm", "einit", 32,
2658     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2659   },
2660 /* srvwdt */
2661   {
2662     XC16X_INSN_SRVWDTM, "srvwdtm", "srvwdt", 32,
2663     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2664   },
2665 /* sbrk */
2666   {
2667     XC16X_INSN_SBRK, "sbrk", "sbrk", 16,
2668     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2669   },
2670 /* atomic $hash$uimm2 */
2671   {
2672     XC16X_INSN_ATOMIC, "atomic", "atomic", 16,
2673     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2674   },
2675 /* extr $hash$uimm2 */
2676   {
2677     XC16X_INSN_EXTR, "extr", "extr", 16,
2678     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2679   },
2680 /* extp $sr,$hash$uimm2 */
2681   {
2682     XC16X_INSN_EXTP, "extp", "extp", 16,
2683     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2684   },
2685 /* extp $hash$pagenum,$hash$uimm2 */
2686   {
2687     XC16X_INSN_EXTP1, "extp1", "extp", 32,
2688     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2689   },
2690 /* extp $hash$pag$upag16,$hash$uimm2 */
2691   {
2692     XC16X_INSN_EXTPG1, "extpg1", "extp", 32,
2693     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2694   },
2695 /* extpr $sr,$hash$uimm2 */
2696   {
2697     XC16X_INSN_EXTPR, "extpr", "extpr", 16,
2698     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2699   },
2700 /* extpr $hash$pagenum,$hash$uimm2 */
2701   {
2702     XC16X_INSN_EXTPR1, "extpr1", "extpr", 32,
2703     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2704   },
2705 /* exts $sr,$hash$uimm2 */
2706   {
2707     XC16X_INSN_EXTS, "exts", "exts", 16,
2708     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2709   },
2710 /* exts $hash$seghi8,$hash$uimm2 */
2711   {
2712     XC16X_INSN_EXTS1, "exts1", "exts", 32,
2713     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2714   },
2715 /* extsr $sr,$hash$uimm2 */
2716   {
2717     XC16X_INSN_EXTSR, "extsr", "extsr", 16,
2718     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2719   },
2720 /* extsr $hash$seghi8,$hash$uimm2 */
2721   {
2722     XC16X_INSN_EXTSR1, "extsr1", "extsr", 32,
2723     { 0|A(COND_CTI), { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2724   },
2725 /* prior $dr,$sr */
2726   {
2727     XC16X_INSN_PRIOR, "prior", "prior", 16,
2728     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2729   },
2730 /* bclr $RegNam */
2731   {
2732     XC16X_INSN_BCLR18, "bclr18", "bclr", 16,
2733     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2734   },
2735 /* bclr $reg8$dot$qbit */
2736   {
2737     XC16X_INSN_BCLR0, "bclr0", "bclr", 16,
2738     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2739   },
2740 /* bclr $reg8$dot$qbit */
2741   {
2742     XC16X_INSN_BCLR1, "bclr1", "bclr", 16,
2743     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2744   },
2745 /* bclr $reg8$dot$qbit */
2746   {
2747     XC16X_INSN_BCLR2, "bclr2", "bclr", 16,
2748     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2749   },
2750 /* bclr $reg8$dot$qbit */
2751   {
2752     XC16X_INSN_BCLR3, "bclr3", "bclr", 16,
2753     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2754   },
2755 /* bclr $reg8$dot$qbit */
2756   {
2757     XC16X_INSN_BCLR4, "bclr4", "bclr", 16,
2758     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2759   },
2760 /* bclr $reg8$dot$qbit */
2761   {
2762     XC16X_INSN_BCLR5, "bclr5", "bclr", 16,
2763     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2764   },
2765 /* bclr $reg8$dot$qbit */
2766   {
2767     XC16X_INSN_BCLR6, "bclr6", "bclr", 16,
2768     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2769   },
2770 /* bclr $reg8$dot$qbit */
2771   {
2772     XC16X_INSN_BCLR7, "bclr7", "bclr", 16,
2773     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2774   },
2775 /* bclr $reg8$dot$qbit */
2776   {
2777     XC16X_INSN_BCLR8, "bclr8", "bclr", 16,
2778     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2779   },
2780 /* bclr $reg8$dot$qbit */
2781   {
2782     XC16X_INSN_BCLR9, "bclr9", "bclr", 16,
2783     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2784   },
2785 /* bclr $reg8$dot$qbit */
2786   {
2787     XC16X_INSN_BCLR10, "bclr10", "bclr", 16,
2788     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2789   },
2790 /* bclr $reg8$dot$qbit */
2791   {
2792     XC16X_INSN_BCLR11, "bclr11", "bclr", 16,
2793     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2794   },
2795 /* bclr $reg8$dot$qbit */
2796   {
2797     XC16X_INSN_BCLR12, "bclr12", "bclr", 16,
2798     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2799   },
2800 /* bclr $reg8$dot$qbit */
2801   {
2802     XC16X_INSN_BCLR13, "bclr13", "bclr", 16,
2803     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2804   },
2805 /* bclr $reg8$dot$qbit */
2806   {
2807     XC16X_INSN_BCLR14, "bclr14", "bclr", 16,
2808     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2809   },
2810 /* bclr $reg8$dot$qbit */
2811   {
2812     XC16X_INSN_BCLR15, "bclr15", "bclr", 16,
2813     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2814   },
2815 /* bset $RegNam */
2816   {
2817     XC16X_INSN_BSET19, "bset19", "bset", 16,
2818     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2819   },
2820 /* bset $reg8$dot$qbit */
2821   {
2822     XC16X_INSN_BSET0, "bset0", "bset", 16,
2823     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2824   },
2825 /* bset $reg8$dot$qbit */
2826   {
2827     XC16X_INSN_BSET1, "bset1", "bset", 16,
2828     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2829   },
2830 /* bset $reg8$dot$qbit */
2831   {
2832     XC16X_INSN_BSET2, "bset2", "bset", 16,
2833     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2834   },
2835 /* bset $reg8$dot$qbit */
2836   {
2837     XC16X_INSN_BSET3, "bset3", "bset", 16,
2838     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2839   },
2840 /* bset $reg8$dot$qbit */
2841   {
2842     XC16X_INSN_BSET4, "bset4", "bset", 16,
2843     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2844   },
2845 /* bset $reg8$dot$qbit */
2846   {
2847     XC16X_INSN_BSET5, "bset5", "bset", 16,
2848     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2849   },
2850 /* bset $reg8$dot$qbit */
2851   {
2852     XC16X_INSN_BSET6, "bset6", "bset", 16,
2853     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2854   },
2855 /* bset $reg8$dot$qbit */
2856   {
2857     XC16X_INSN_BSET7, "bset7", "bset", 16,
2858     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2859   },
2860 /* bset $reg8$dot$qbit */
2861   {
2862     XC16X_INSN_BSET8, "bset8", "bset", 16,
2863     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2864   },
2865 /* bset $reg8$dot$qbit */
2866   {
2867     XC16X_INSN_BSET9, "bset9", "bset", 16,
2868     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2869   },
2870 /* bset $reg8$dot$qbit */
2871   {
2872     XC16X_INSN_BSET10, "bset10", "bset", 16,
2873     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2874   },
2875 /* bset $reg8$dot$qbit */
2876   {
2877     XC16X_INSN_BSET11, "bset11", "bset", 16,
2878     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2879   },
2880 /* bset $reg8$dot$qbit */
2881   {
2882     XC16X_INSN_BSET12, "bset12", "bset", 16,
2883     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2884   },
2885 /* bset $reg8$dot$qbit */
2886   {
2887     XC16X_INSN_BSET13, "bset13", "bset", 16,
2888     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2889   },
2890 /* bset $reg8$dot$qbit */
2891   {
2892     XC16X_INSN_BSET14, "bset14", "bset", 16,
2893     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2894   },
2895 /* bset $reg8$dot$qbit */
2896   {
2897     XC16X_INSN_BSET15, "bset15", "bset", 16,
2898     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2899   },
2900 /* bmov $reghi8$dot$qhibit,$reg8$dot$qlobit */
2901   {
2902     XC16X_INSN_BMOV, "bmov", "bmov", 32,
2903     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2904   },
2905 /* bmovn $reghi8$dot$qhibit,$reg8$dot$qlobit */
2906   {
2907     XC16X_INSN_BMOVN, "bmovn", "bmovn", 32,
2908     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2909   },
2910 /* band $reghi8$dot$qhibit,$reg8$dot$qlobit */
2911   {
2912     XC16X_INSN_BAND, "band", "band", 32,
2913     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2914   },
2915 /* bor $reghi8$dot$qhibit,$reg8$dot$qlobit */
2916   {
2917     XC16X_INSN_BOR, "bor", "bor", 32,
2918     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2919   },
2920 /* bxor $reghi8$dot$qhibit,$reg8$dot$qlobit */
2921   {
2922     XC16X_INSN_BXOR, "bxor", "bxor", 32,
2923     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2924   },
2925 /* bcmp $reghi8$dot$qhibit,$reg8$dot$qlobit */
2926   {
2927     XC16X_INSN_BCMP, "bcmp", "bcmp", 32,
2928     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2929   },
2930 /* bfldl $reg8,$hash$mask8,$hash$datahi8 */
2931   {
2932     XC16X_INSN_BFLDL, "bfldl", "bfldl", 32,
2933     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2934   },
2935 /* bfldh $reg8,$hash$masklo8,$hash$data8 */
2936   {
2937     XC16X_INSN_BFLDH, "bfldh", "bfldh", 32,
2938     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2939   },
2940 /* cmp $src1,$src2 */
2941   {
2942     XC16X_INSN_CMPR, "cmpr", "cmp", 16,
2943     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2944   },
2945 /* cmpb $drb,$srb */
2946   {
2947     XC16X_INSN_CMPBR, "cmpbr", "cmpb", 16,
2948     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2949   },
2950 /* cmp $src1,$hash$uimm3 */
2951   {
2952     XC16X_INSN_CMPRI, "cmpri", "cmp", 16,
2953     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2954   },
2955 /* cmpb $drb,$hash$uimm3 */
2956   {
2957     XC16X_INSN_CMPBRI, "cmpbri", "cmpb", 16,
2958     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2959   },
2960 /* cmp $reg8,$hash$uimm16 */
2961   {
2962     XC16X_INSN_CMPI, "cmpi", "cmp", 32,
2963     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2964   },
2965 /* cmpb $regb8,$hash$uimm8 */
2966   {
2967     XC16X_INSN_CMPBI, "cmpbi", "cmpb", 32,
2968     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2969   },
2970 /* cmp $dr,[$sr2] */
2971   {
2972     XC16X_INSN_CMPR2, "cmpr2", "cmp", 16,
2973     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2974   },
2975 /* cmpb $drb,[$sr2] */
2976   {
2977     XC16X_INSN_CMPBR2, "cmpbr2", "cmpb", 16,
2978     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2979   },
2980 /* cmp $dr,[$sr2+] */
2981   {
2982     XC16X_INSN_CMP2I, "cmp2i", "cmp", 16,
2983     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2984   },
2985 /* cmpb $drb,[$sr2+] */
2986   {
2987     XC16X_INSN_CMPB2I, "cmpb2i", "cmpb", 16,
2988     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2989   },
2990 /* cmp $reg8,$pof$upof16 */
2991   {
2992     XC16X_INSN_CMP04, "cmp04", "cmp", 32,
2993     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2994   },
2995 /* cmpb $regb8,$pof$upof16 */
2996   {
2997     XC16X_INSN_CMPB4, "cmpb4", "cmpb", 32,
2998     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
2999   },
3000 /* cmp $regmem8,$memgr8 */
3001   {
3002     XC16X_INSN_CMP004, "cmp004", "cmp", 32,
3003     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3004   },
3005 /* cmp $reg8,$memory */
3006   {
3007     XC16X_INSN_CMP0004, "cmp0004", "cmp", 32,
3008     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3009   },
3010 /* cmpb $regbmem8,$memgr8 */
3011   {
3012     XC16X_INSN_CMPB04, "cmpb04", "cmpb", 32,
3013     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3014   },
3015 /* cmpb $regb8,$memory */
3016   {
3017     XC16X_INSN_CMPB004, "cmpb004", "cmpb", 32,
3018     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3019   },
3020 /* cmpd1 $sr,$hash$uimm4 */
3021   {
3022     XC16X_INSN_CMPD1RI, "cmpd1ri", "cmpd1", 16,
3023     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3024   },
3025 /* cmpd2 $sr,$hash$uimm4 */
3026   {
3027     XC16X_INSN_CMPD2RI, "cmpd2ri", "cmpd2", 16,
3028     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3029   },
3030 /* cmpi1 $sr,$hash$uimm4 */
3031   {
3032     XC16X_INSN_CMPI1RI, "cmpi1ri", "cmpi1", 16,
3033     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3034   },
3035 /* cmpi2 $sr,$hash$uimm4 */
3036   {
3037     XC16X_INSN_CMPI2RI, "cmpi2ri", "cmpi2", 16,
3038     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3039   },
3040 /* cmpd1 $reg8,$hash$uimm16 */
3041   {
3042     XC16X_INSN_CMPD1RIM, "cmpd1rim", "cmpd1", 32,
3043     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3044   },
3045 /* cmpd2 $reg8,$hash$uimm16 */
3046   {
3047     XC16X_INSN_CMPD2RIM, "cmpd2rim", "cmpd2", 32,
3048     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3049   },
3050 /* cmpi1 $reg8,$hash$uimm16 */
3051   {
3052     XC16X_INSN_CMPI1RIM, "cmpi1rim", "cmpi1", 32,
3053     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3054   },
3055 /* cmpi2 $reg8,$hash$uimm16 */
3056   {
3057     XC16X_INSN_CMPI2RIM, "cmpi2rim", "cmpi2", 32,
3058     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3059   },
3060 /* cmpd1 $reg8,$pof$upof16 */
3061   {
3062     XC16X_INSN_CMPD1RP, "cmpd1rp", "cmpd1", 32,
3063     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3064   },
3065 /* cmpd2 $reg8,$pof$upof16 */
3066   {
3067     XC16X_INSN_CMPD2RP, "cmpd2rp", "cmpd2", 32,
3068     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3069   },
3070 /* cmpi1 $reg8,$pof$upof16 */
3071   {
3072     XC16X_INSN_CMPI1RP, "cmpi1rp", "cmpi1", 32,
3073     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3074   },
3075 /* cmpi2 $reg8,$pof$upof16 */
3076   {
3077     XC16X_INSN_CMPI2RP, "cmpi2rp", "cmpi2", 32,
3078     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3079   },
3080 /* cmpd1 $regmem8,$memgr8 */
3081   {
3082     XC16X_INSN_CMPD1RM, "cmpd1rm", "cmpd1", 32,
3083     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3084   },
3085 /* cmpd2 $regmem8,$memgr8 */
3086   {
3087     XC16X_INSN_CMPD2RM, "cmpd2rm", "cmpd2", 32,
3088     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3089   },
3090 /* cmpi1 $regmem8,$memgr8 */
3091   {
3092     XC16X_INSN_CMPI1RM, "cmpi1rm", "cmpi1", 32,
3093     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3094   },
3095 /* cmpi2 $regmem8,$memgr8 */
3096   {
3097     XC16X_INSN_CMPI2RM, "cmpi2rm", "cmpi2", 32,
3098     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3099   },
3100 /* cmpd1 $reg8,$memory */
3101   {
3102     XC16X_INSN_CMPD1RMI, "cmpd1rmi", "cmpd1", 32,
3103     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3104   },
3105 /* cmpd2 $reg8,$memory */
3106   {
3107     XC16X_INSN_CMPD2RMI, "cmpd2rmi", "cmpd2", 32,
3108     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3109   },
3110 /* cmpi1 $reg8,$memory */
3111   {
3112     XC16X_INSN_CMPI1RMI, "cmpi1rmi", "cmpi1", 32,
3113     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3114   },
3115 /* cmpi2 $reg8,$memory */
3116   {
3117     XC16X_INSN_CMPI2RMI, "cmpi2rmi", "cmpi2", 32,
3118     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3119   },
3120 /* shl $dr,$sr */
3121   {
3122     XC16X_INSN_SHLR, "shlr", "shl", 16,
3123     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3124   },
3125 /* shr $dr,$sr */
3126   {
3127     XC16X_INSN_SHRR, "shrr", "shr", 16,
3128     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3129   },
3130 /* rol $dr,$sr */
3131   {
3132     XC16X_INSN_ROLR, "rolr", "rol", 16,
3133     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3134   },
3135 /* ror $dr,$sr */
3136   {
3137     XC16X_INSN_RORR, "rorr", "ror", 16,
3138     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3139   },
3140 /* ashr $dr,$sr */
3141   {
3142     XC16X_INSN_ASHRR, "ashrr", "ashr", 16,
3143     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3144   },
3145 /* shl $sr,$hash$uimm4 */
3146   {
3147     XC16X_INSN_SHLRI, "shlri", "shl", 16,
3148     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3149   },
3150 /* shr $sr,$hash$uimm4 */
3151   {
3152     XC16X_INSN_SHRRI, "shrri", "shr", 16,
3153     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3154   },
3155 /* rol $sr,$hash$uimm4 */
3156   {
3157     XC16X_INSN_ROLRI, "rolri", "rol", 16,
3158     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3159   },
3160 /* ror $sr,$hash$uimm4 */
3161   {
3162     XC16X_INSN_RORRI, "rorri", "ror", 16,
3163     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3164   },
3165 /* ashr $sr,$hash$uimm4 */
3166   {
3167     XC16X_INSN_ASHRRI, "ashrri", "ashr", 16,
3168     { 0, { { { (1<<MACH_BASE), 0 } }, { { PIPE_OS, 0 } } } }
3169   },
3170 };
3171
3172 #undef OP
3173 #undef A
3174
3175 /* Initialize anything needed to be done once, before any cpu_open call.  */
3176
3177 static void
3178 init_tables (void)
3179 {
3180 }
3181
3182 #ifndef opcodes_error_handler
3183 #define opcodes_error_handler(...) \
3184   fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
3185 #endif
3186
3187 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
3188 static void build_hw_table      (CGEN_CPU_TABLE *);
3189 static void build_ifield_table  (CGEN_CPU_TABLE *);
3190 static void build_operand_table (CGEN_CPU_TABLE *);
3191 static void build_insn_table    (CGEN_CPU_TABLE *);
3192 static void xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *);
3193
3194 /* Subroutine of xc16x_cgen_cpu_open to look up a mach via its bfd name.  */
3195
3196 static const CGEN_MACH *
3197 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
3198 {
3199   while (table->name)
3200     {
3201       if (strcmp (name, table->bfd_name) == 0)
3202         return table;
3203       ++table;
3204     }
3205   return NULL;
3206 }
3207
3208 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
3209
3210 static void
3211 build_hw_table (CGEN_CPU_TABLE *cd)
3212 {
3213   int i;
3214   int machs = cd->machs;
3215   const CGEN_HW_ENTRY *init = & xc16x_cgen_hw_table[0];
3216   /* MAX_HW is only an upper bound on the number of selected entries.
3217      However each entry is indexed by it's enum so there can be holes in
3218      the table.  */
3219   const CGEN_HW_ENTRY **selected =
3220     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
3221
3222   cd->hw_table.init_entries = init;
3223   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
3224   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
3225   /* ??? For now we just use machs to determine which ones we want.  */
3226   for (i = 0; init[i].name != NULL; ++i)
3227     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
3228         & machs)
3229       selected[init[i].type] = &init[i];
3230   cd->hw_table.entries = selected;
3231   cd->hw_table.num_entries = MAX_HW;
3232 }
3233
3234 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
3235
3236 static void
3237 build_ifield_table (CGEN_CPU_TABLE *cd)
3238 {
3239   cd->ifld_table = & xc16x_cgen_ifld_table[0];
3240 }
3241
3242 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.  */
3243
3244 static void
3245 build_operand_table (CGEN_CPU_TABLE *cd)
3246 {
3247   int i;
3248   int machs = cd->machs;
3249   const CGEN_OPERAND *init = & xc16x_cgen_operand_table[0];
3250   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
3251      However each entry is indexed by it's enum so there can be holes in
3252      the table.  */
3253   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
3254
3255   cd->operand_table.init_entries = init;
3256   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
3257   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
3258   /* ??? For now we just use mach to determine which ones we want.  */
3259   for (i = 0; init[i].name != NULL; ++i)
3260     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
3261         & machs)
3262       selected[init[i].type] = &init[i];
3263   cd->operand_table.entries = selected;
3264   cd->operand_table.num_entries = MAX_OPERANDS;
3265 }
3266
3267 /* Subroutine of xc16x_cgen_cpu_open to build the hardware table.
3268    ??? This could leave out insns not supported by the specified mach/isa,
3269    but that would cause errors like "foo only supported by bar" to become
3270    "unknown insn", so for now we include all insns and require the app to
3271    do the checking later.
3272    ??? On the other hand, parsing of such insns may require their hardware or
3273    operand elements to be in the table [which they mightn't be].  */
3274
3275 static void
3276 build_insn_table (CGEN_CPU_TABLE *cd)
3277 {
3278   int i;
3279   const CGEN_IBASE *ib = & xc16x_cgen_insn_table[0];
3280   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
3281
3282   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
3283   for (i = 0; i < MAX_INSNS; ++i)
3284     insns[i].base = &ib[i];
3285   cd->insn_table.init_entries = insns;
3286   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
3287   cd->insn_table.num_init_entries = MAX_INSNS;
3288 }
3289
3290 /* Subroutine of xc16x_cgen_cpu_open to rebuild the tables.  */
3291
3292 static void
3293 xc16x_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
3294 {
3295   int i;
3296   CGEN_BITSET *isas = cd->isas;
3297   unsigned int machs = cd->machs;
3298
3299   cd->int_insn_p = CGEN_INT_INSN_P;
3300
3301   /* Data derived from the isa spec.  */
3302 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
3303   cd->default_insn_bitsize = UNSET;
3304   cd->base_insn_bitsize = UNSET;
3305   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
3306   cd->max_insn_bitsize = 0;
3307   for (i = 0; i < MAX_ISAS; ++i)
3308     if (cgen_bitset_contains (isas, i))
3309       {
3310         const CGEN_ISA *isa = & xc16x_cgen_isa_table[i];
3311
3312         /* Default insn sizes of all selected isas must be
3313            equal or we set the result to 0, meaning "unknown".  */
3314         if (cd->default_insn_bitsize == UNSET)
3315           cd->default_insn_bitsize = isa->default_insn_bitsize;
3316         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
3317           ; /* This is ok.  */
3318         else
3319           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
3320
3321         /* Base insn sizes of all selected isas must be equal
3322            or we set the result to 0, meaning "unknown".  */
3323         if (cd->base_insn_bitsize == UNSET)
3324           cd->base_insn_bitsize = isa->base_insn_bitsize;
3325         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
3326           ; /* This is ok.  */
3327         else
3328           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
3329
3330         /* Set min,max insn sizes.  */
3331         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
3332           cd->min_insn_bitsize = isa->min_insn_bitsize;
3333         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
3334           cd->max_insn_bitsize = isa->max_insn_bitsize;
3335       }
3336
3337   /* Data derived from the mach spec.  */
3338   for (i = 0; i < MAX_MACHS; ++i)
3339     if (((1 << i) & machs) != 0)
3340       {
3341         const CGEN_MACH *mach = & xc16x_cgen_mach_table[i];
3342
3343         if (mach->insn_chunk_bitsize != 0)
3344         {
3345           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
3346             {
3347               opcodes_error_handler
3348                 (/* xgettext:c-format */
3349                  _("internal error: xc16x_cgen_rebuild_tables: "
3350                    "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
3351                  cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
3352               abort ();
3353             }
3354
3355           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
3356         }
3357       }
3358
3359   /* Determine which hw elements are used by MACH.  */
3360   build_hw_table (cd);
3361
3362   /* Build the ifield table.  */
3363   build_ifield_table (cd);
3364
3365   /* Determine which operands are used by MACH/ISA.  */
3366   build_operand_table (cd);
3367
3368   /* Build the instruction table.  */
3369   build_insn_table (cd);
3370 }
3371
3372 /* Initialize a cpu table and return a descriptor.
3373    It's much like opening a file, and must be the first function called.
3374    The arguments are a set of (type/value) pairs, terminated with
3375    CGEN_CPU_OPEN_END.
3376
3377    Currently supported values:
3378    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
3379    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
3380    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
3381    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
3382    CGEN_CPU_OPEN_END:     terminates arguments
3383
3384    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
3385    precluded.  */
3386
3387 CGEN_CPU_DESC
3388 xc16x_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
3389 {
3390   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
3391   static int init_p;
3392   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
3393   unsigned int machs = 0; /* 0 = "unspecified" */
3394   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
3395   va_list ap;
3396
3397   if (! init_p)
3398     {
3399       init_tables ();
3400       init_p = 1;
3401     }
3402
3403   memset (cd, 0, sizeof (*cd));
3404
3405   va_start (ap, arg_type);
3406   while (arg_type != CGEN_CPU_OPEN_END)
3407     {
3408       switch (arg_type)
3409         {
3410         case CGEN_CPU_OPEN_ISAS :
3411           isas = va_arg (ap, CGEN_BITSET *);
3412           break;
3413         case CGEN_CPU_OPEN_MACHS :
3414           machs = va_arg (ap, unsigned int);
3415           break;
3416         case CGEN_CPU_OPEN_BFDMACH :
3417           {
3418             const char *name = va_arg (ap, const char *);
3419             const CGEN_MACH *mach =
3420               lookup_mach_via_bfd_name (xc16x_cgen_mach_table, name);
3421
3422             if (mach != NULL)
3423               machs |= 1 << mach->num;
3424             break;
3425           }
3426         case CGEN_CPU_OPEN_ENDIAN :
3427           endian = va_arg (ap, enum cgen_endian);
3428           break;
3429         default :
3430           opcodes_error_handler
3431             (/* xgettext:c-format */
3432              _("internal error: xc16x_cgen_cpu_open: "
3433                "unsupported argument `%d'"),
3434              arg_type);
3435           abort (); /* ??? return NULL? */
3436         }
3437       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
3438     }
3439   va_end (ap);
3440
3441   /* Mach unspecified means "all".  */
3442   if (machs == 0)
3443     machs = (1 << MAX_MACHS) - 1;
3444   /* Base mach is always selected.  */
3445   machs |= 1;
3446   if (endian == CGEN_ENDIAN_UNKNOWN)
3447     {
3448       /* ??? If target has only one, could have a default.  */
3449       opcodes_error_handler
3450         (/* xgettext:c-format */
3451          _("internal error: xc16x_cgen_cpu_open: no endianness specified"));
3452       abort ();
3453     }
3454
3455   cd->isas = cgen_bitset_copy (isas);
3456   cd->machs = machs;
3457   cd->endian = endian;
3458   /* FIXME: for the sparc case we can determine insn-endianness statically.
3459      The worry here is where both data and insn endian can be independently
3460      chosen, in which case this function will need another argument.
3461      Actually, will want to allow for more arguments in the future anyway.  */
3462   cd->insn_endian = endian;
3463
3464   /* Table (re)builder.  */
3465   cd->rebuild_tables = xc16x_cgen_rebuild_tables;
3466   xc16x_cgen_rebuild_tables (cd);
3467
3468   /* Default to not allowing signed overflow.  */
3469   cd->signed_overflow_ok_p = 0;
3470
3471   return (CGEN_CPU_DESC) cd;
3472 }
3473
3474 /* Cover fn to xc16x_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
3475    MACH_NAME is the bfd name of the mach.  */
3476
3477 CGEN_CPU_DESC
3478 xc16x_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
3479 {
3480   return xc16x_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
3481                                CGEN_CPU_OPEN_ENDIAN, endian,
3482                                CGEN_CPU_OPEN_END);
3483 }
3484
3485 /* Close a cpu table.
3486    ??? This can live in a machine independent file, but there's currently
3487    no place to put this file (there's no libcgen).  libopcodes is the wrong
3488    place as some simulator ports use this but they don't use libopcodes.  */
3489
3490 void
3491 xc16x_cgen_cpu_close (CGEN_CPU_DESC cd)
3492 {
3493   unsigned int i;
3494   const CGEN_INSN *insns;
3495
3496   if (cd->macro_insn_table.init_entries)
3497     {
3498       insns = cd->macro_insn_table.init_entries;
3499       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
3500         if (CGEN_INSN_RX ((insns)))
3501           regfree (CGEN_INSN_RX (insns));
3502     }
3503
3504   if (cd->insn_table.init_entries)
3505     {
3506       insns = cd->insn_table.init_entries;
3507       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
3508         if (CGEN_INSN_RX (insns))
3509           regfree (CGEN_INSN_RX (insns));
3510     }
3511
3512   if (cd->macro_insn_table.init_entries)
3513     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
3514
3515   if (cd->insn_table.init_entries)
3516     free ((CGEN_INSN *) cd->insn_table.init_entries);
3517
3518   if (cd->hw_table.entries)
3519     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
3520
3521   if (cd->operand_table.entries)
3522     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
3523
3524   free (cd);
3525 }
3526