opcodes/mt-desc.c

   1 /* DO NOT EDIT!  -*- buffer-read-only: t -*- vi:set ro:  */
   2 /* CPU data for mt.
   3
   4 THIS FILE IS MACHINE GENERATED WITH CGEN.
   5
   6 Copyright (C) 1996-2019 Free Software Foundation, Inc.
   7
   8 This file is part of the GNU Binutils and/or GDB, the GNU debugger.
   9
  10    This file is free software; you can redistribute it and/or modify
  11    it under the terms of the GNU General Public License as published by
  12    the Free Software Foundation; either version 3, or (at your option)
  13    any later version.
  14
  15    It is distributed in the hope that it will be useful, but WITHOUT
  16    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  17    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  18    License for more details.
  19
  20    You should have received a copy of the GNU General Public License along
  21    with this program; if not, write to the Free Software Foundation, Inc.,
  22    51 Franklin Street - Fifth Floor, Boston, MA 02110-1301, USA.
  23
  24 */
  25
  26 #include "sysdep.h"
  27 #include <stdio.h>
  28 #include <stdarg.h>
  29 #include "ansidecl.h"
  30 #include "bfd.h"
  31 #include "symcat.h"
  32 #include "mt-desc.h"
  33 #include "mt-opc.h"
  34 #include "opintl.h"
  35 #include "libiberty.h"
  36 #include "xregex.h"
  37
  38 /* Attributes.  */
  39
  40 static const CGEN_ATTR_ENTRY bool_attr[] =
  41 {
  42   { "#f", 0 },
  43   { "#t", 1 },
  44   { 0, 0 }
  45 };
  46
  47 static const CGEN_ATTR_ENTRY MACH_attr[] ATTRIBUTE_UNUSED =
  48 {
  49   { "base", MACH_BASE },
  50   { "ms1", MACH_MS1 },
  51   { "ms1_003", MACH_MS1_003 },
  52   { "ms2", MACH_MS2 },
  53   { "max", MACH_MAX },
  54   { 0, 0 }
  55 };
  56
  57 static const CGEN_ATTR_ENTRY ISA_attr[] ATTRIBUTE_UNUSED =
  58 {
  59   { "mt", ISA_MT },
  60   { "max", ISA_MAX },
  61   { 0, 0 }
  62 };
  63
  64 const CGEN_ATTR_TABLE mt_cgen_ifield_attr_table[] =
  65 {
  66   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  67   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  68   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  69   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  70   { "RESERVED", &bool_attr[0], &bool_attr[0] },
  71   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  72   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  73   { 0, 0, 0 }
  74 };
  75
  76 const CGEN_ATTR_TABLE mt_cgen_hardware_attr_table[] =
  77 {
  78   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  79   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  80   { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
  81   { "PC", &bool_attr[0], &bool_attr[0] },
  82   { "PROFILE", &bool_attr[0], &bool_attr[0] },
  83   { 0, 0, 0 }
  84 };
  85
  86 const CGEN_ATTR_TABLE mt_cgen_operand_attr_table[] =
  87 {
  88   { "MACH", & MACH_attr[0], & MACH_attr[0] },
  89   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
  90   { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
  91   { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
  92   { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
  93   { "SIGNED", &bool_attr[0], &bool_attr[0] },
  94   { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
  95   { "RELAX", &bool_attr[0], &bool_attr[0] },
  96   { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
  97   { 0, 0, 0 }
  98 };
  99
 100 const CGEN_ATTR_TABLE mt_cgen_insn_attr_table[] =
 101 {
 102   { "MACH", & MACH_attr[0], & MACH_attr[0] },
 103   { "ALIAS", &bool_attr[0], &bool_attr[0] },
 104   { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
 105   { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
 106   { "COND-CTI", &bool_attr[0], &bool_attr[0] },
 107   { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
 108   { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
 109   { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
 110   { "RELAXED", &bool_attr[0], &bool_attr[0] },
 111   { "NO-DIS", &bool_attr[0], &bool_attr[0] },
 112   { "PBB", &bool_attr[0], &bool_attr[0] },
 113   { "LOAD-DELAY", &bool_attr[0], &bool_attr[0] },
 114   { "MEMORY-ACCESS", &bool_attr[0], &bool_attr[0] },
 115   { "AL-INSN", &bool_attr[0], &bool_attr[0] },
 116   { "IO-INSN", &bool_attr[0], &bool_attr[0] },
 117   { "BR-INSN", &bool_attr[0], &bool_attr[0] },
 118   { "JAL-HAZARD", &bool_attr[0], &bool_attr[0] },
 119   { "USES-FRDR", &bool_attr[0], &bool_attr[0] },
 120   { "USES-FRDRRR", &bool_attr[0], &bool_attr[0] },
 121   { "USES-FRSR1", &bool_attr[0], &bool_attr[0] },
 122   { "USES-FRSR2", &bool_attr[0], &bool_attr[0] },
 123   { "SKIPA", &bool_attr[0], &bool_attr[0] },
 124   { 0, 0, 0 }
 125 };
 126
 127 /* Instruction set variants.  */
 128
 129 static const CGEN_ISA mt_cgen_isa_table[] = {
 130   { "mt", 32, 32, 32, 32 },
 131   { 0, 0, 0, 0, 0 }
 132 };
 133
 134 /* Machine variants.  */
 135
 136 static const CGEN_MACH mt_cgen_mach_table[] = {
 137   { "ms1", "ms1", MACH_MS1, 0 },
 138   { "ms1-003", "ms1-003", MACH_MS1_003, 0 },
 139   { "ms2", "ms2", MACH_MS2, 0 },
 140   { 0, 0, 0, 0 }
 141 };
 142
 143 static CGEN_KEYWORD_ENTRY mt_cgen_opval_msys_syms_entries[] =
 144 {
 145   { "DUP", 1, {0, {{{0, 0}}}}, 0, 0 },
 146   { "XX", 0, {0, {{{0, 0}}}}, 0, 0 }
 147 };
 148
 149 CGEN_KEYWORD mt_cgen_opval_msys_syms =
 150 {
 151   & mt_cgen_opval_msys_syms_entries[0],
 152   2,
 153   0, 0, 0, 0, ""
 154 };
 155
 156 static CGEN_KEYWORD_ENTRY mt_cgen_opval_h_spr_entries[] =
 157 {
 158   { "R0", 0, {0, {{{0, 0}}}}, 0, 0 },
 159   { "R1", 1, {0, {{{0, 0}}}}, 0, 0 },
 160   { "R2", 2, {0, {{{0, 0}}}}, 0, 0 },
 161   { "R3", 3, {0, {{{0, 0}}}}, 0, 0 },
 162   { "R4", 4, {0, {{{0, 0}}}}, 0, 0 },
 163   { "R5", 5, {0, {{{0, 0}}}}, 0, 0 },
 164   { "R6", 6, {0, {{{0, 0}}}}, 0, 0 },
 165   { "R7", 7, {0, {{{0, 0}}}}, 0, 0 },
 166   { "R8", 8, {0, {{{0, 0}}}}, 0, 0 },
 167   { "R9", 9, {0, {{{0, 0}}}}, 0, 0 },
 168   { "R10", 10, {0, {{{0, 0}}}}, 0, 0 },
 169   { "R11", 11, {0, {{{0, 0}}}}, 0, 0 },
 170   { "R12", 12, {0, {{{0, 0}}}}, 0, 0 },
 171   { "fp", 12, {0, {{{0, 0}}}}, 0, 0 },
 172   { "R13", 13, {0, {{{0, 0}}}}, 0, 0 },
 173   { "sp", 13, {0, {{{0, 0}}}}, 0, 0 },
 174   { "R14", 14, {0, {{{0, 0}}}}, 0, 0 },
 175   { "ra", 14, {0, {{{0, 0}}}}, 0, 0 },
 176   { "R15", 15, {0, {{{0, 0}}}}, 0, 0 },
 177   { "ira", 15, {0, {{{0, 0}}}}, 0, 0 }
 178 };
 179
 180 CGEN_KEYWORD mt_cgen_opval_h_spr =
 181 {
 182   & mt_cgen_opval_h_spr_entries[0],
 183   20,
 184   0, 0, 0, 0, ""
 185 };
 186
 187
 188 /* The hardware table.  */
 189
 190 #define A(a) (1 << CGEN_HW_##a)
 191
 192 const CGEN_HW_ENTRY mt_cgen_hw_table[] =
 193 {
 194   { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 195   { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 196   { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 197   { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 198   { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 199   { "h-spr", HW_H_SPR, CGEN_ASM_KEYWORD, (PTR) & mt_cgen_opval_h_spr, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 200   { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { { { (1<<MACH_BASE), 0 } } } } },
 201   { 0, 0, CGEN_ASM_NONE, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 202 };
 203
 204 #undef A
 205
 206
 207 /* The instruction field table.  */
 208
 209 #define A(a) (1 << CGEN_IFLD_##a)
 210
 211 const CGEN_IFLD mt_cgen_ifld_table[] =
 212 {
 213   { MT_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 214   { MT_F_ANYOF, "f-anyof", 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 215   { MT_F_MSYS, "f-msys", 0, 32, 31, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 216   { MT_F_OPC, "f-opc", 0, 32, 30, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 217   { MT_F_IMM, "f-imm", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 218   { MT_F_UU24, "f-uu24", 0, 32, 23, 24, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 219   { MT_F_SR1, "f-sr1", 0, 32, 23, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 220   { MT_F_SR2, "f-sr2", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 221   { MT_F_DR, "f-dr", 0, 32, 19, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 222   { MT_F_DRRR, "f-drrr", 0, 32, 15, 4, { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 223   { MT_F_IMM16U, "f-imm16u", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 224   { MT_F_IMM16S, "f-imm16s", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 225   { MT_F_IMM16A, "f-imm16a", 0, 32, 15, 16, { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 226   { MT_F_UU4A, "f-uu4a", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 227   { MT_F_UU4B, "f-uu4b", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 228   { MT_F_UU12, "f-uu12", 0, 32, 11, 12, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 229   { MT_F_UU8, "f-uu8", 0, 32, 15, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 230   { MT_F_UU16, "f-uu16", 0, 32, 15, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 231   { MT_F_UU1, "f-uu1", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 232   { MT_F_MSOPC, "f-msopc", 0, 32, 30, 5, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 233   { MT_F_UU_26_25, "f-uu-26-25", 0, 32, 25, 26, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 234   { MT_F_MASK, "f-mask", 0, 32, 25, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 235   { MT_F_BANKADDR, "f-bankaddr", 0, 32, 25, 13, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 236   { MT_F_RDA, "f-rda", 0, 32, 25, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 237   { MT_F_UU_2_25, "f-uu-2-25", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 238   { MT_F_RBBC, "f-rbbc", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 239   { MT_F_PERM, "f-perm", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 240   { MT_F_MODE, "f-mode", 0, 32, 25, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 241   { MT_F_UU_1_24, "f-uu-1-24", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 242   { MT_F_WR, "f-wr", 0, 32, 24, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 243   { MT_F_FBINCR, "f-fbincr", 0, 32, 23, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 244   { MT_F_UU_2_23, "f-uu-2-23", 0, 32, 23, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 245   { MT_F_XMODE, "f-xmode", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 246   { MT_F_A23, "f-a23", 0, 32, 23, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 247   { MT_F_MASK1, "f-mask1", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 248   { MT_F_CR, "f-cr", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 249   { MT_F_TYPE, "f-type", 0, 32, 21, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 250   { MT_F_INCAMT, "f-incamt", 0, 32, 19, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 251   { MT_F_CBS, "f-cbs", 0, 32, 19, 2, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 252   { MT_F_UU_1_19, "f-uu-1-19", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 253   { MT_F_BALL, "f-ball", 0, 32, 19, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 254   { MT_F_COLNUM, "f-colnum", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 255   { MT_F_BRC, "f-brc", 0, 32, 18, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 256   { MT_F_INCR, "f-incr", 0, 32, 17, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 257   { MT_F_FBDISP, "f-fbdisp", 0, 32, 15, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 258   { MT_F_UU_4_15, "f-uu-4-15", 0, 32, 15, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 259   { MT_F_LENGTH, "f-length", 0, 32, 15, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 260   { MT_F_UU_1_15, "f-uu-1-15", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 261   { MT_F_RC, "f-rc", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 262   { MT_F_RCNUM, "f-rcnum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 263   { MT_F_ROWNUM, "f-rownum", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 264   { MT_F_CBX, "f-cbx", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 265   { MT_F_ID, "f-id", 0, 32, 14, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 266   { MT_F_SIZE, "f-size", 0, 32, 13, 14, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 267   { MT_F_ROWNUM1, "f-rownum1", 0, 32, 12, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 268   { MT_F_UU_3_11, "f-uu-3-11", 0, 32, 11, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 269   { MT_F_RC1, "f-rc1", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 270   { MT_F_CCB, "f-ccb", 0, 32, 11, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 271   { MT_F_CBRB, "f-cbrb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 272   { MT_F_CDB, "f-cdb", 0, 32, 10, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 273   { MT_F_ROWNUM2, "f-rownum2", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 274   { MT_F_CELL, "f-cell", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 275   { MT_F_UU_3_9, "f-uu-3-9", 0, 32, 9, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 276   { MT_F_CONTNUM, "f-contnum", 0, 32, 8, 9, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 277   { MT_F_UU_1_6, "f-uu-1-6", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 278   { MT_F_DUP, "f-dup", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 279   { MT_F_RC2, "f-rc2", 0, 32, 6, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 280   { MT_F_CTXDISP, "f-ctxdisp", 0, 32, 5, 6, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 281   { MT_F_IMM16L, "f-imm16l", 0, 32, 23, 16, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 282   { MT_F_LOOPO, "f-loopo", 0, 32, 7, 8, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 283   { MT_F_CB1SEL, "f-cb1sel", 0, 32, 25, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 284   { MT_F_CB2SEL, "f-cb2sel", 0, 32, 22, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 285   { MT_F_CB1INCR, "f-cb1incr", 0, 32, 19, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } }  },
 286   { MT_F_CB2INCR, "f-cb2incr", 0, 32, 13, 6, { 0|A(SIGNED), { { { (1<<MACH_BASE), 0 } } } }  },
 287   { MT_F_RC3, "f-rc3", 0, 32, 7, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 288   { MT_F_MSYSFRSR2, "f-msysfrsr2", 0, 32, 19, 4, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 289   { MT_F_BRC2, "f-brc2", 0, 32, 14, 3, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 290   { MT_F_BALL2, "f-ball2", 0, 32, 15, 1, { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 291   { 0, 0, 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } }
 292 };
 293
 294 #undef A
 295
 296
 297
 298 /* multi ifield declarations */
 299
 300
 301
 302 /* multi ifield definitions */
 303
 304
 305 /* The operand table.  */
 306
 307 #define A(a) (1 << CGEN_OPERAND_##a)
 308 #define OPERAND(op) MT_OPERAND_##op
 309
 310 const CGEN_OPERAND mt_cgen_operand_table[] =
 311 {
 312 /* pc: program counter */
 313   { "pc", MT_OPERAND_PC, HW_H_PC, 0, 0,
 314     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_NIL] } },
 315     { 0|A(SEM_ONLY), { { { (1<<MACH_BASE), 0 } } } }  },
 316 /* frsr1: register */
 317   { "frsr1", MT_OPERAND_FRSR1, HW_H_SPR, 23, 4,
 318     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR1] } },
 319     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 320 /* frsr2: register */
 321   { "frsr2", MT_OPERAND_FRSR2, HW_H_SPR, 19, 4,
 322     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SR2] } },
 323     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 324 /* frdr: register */
 325   { "frdr", MT_OPERAND_FRDR, HW_H_SPR, 19, 4,
 326     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DR] } },
 327     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 328 /* frdrrr: register */
 329   { "frdrrr", MT_OPERAND_FRDRRR, HW_H_SPR, 15, 4,
 330     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DRRR] } },
 331     { 0|A(ABS_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 332 /* imm16: immediate value - sign extd */
 333   { "imm16", MT_OPERAND_IMM16, HW_H_SINT, 15, 16,
 334     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
 335     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 336 /* imm16z: immediate value - zero extd */
 337   { "imm16z", MT_OPERAND_IMM16Z, HW_H_UINT, 15, 16,
 338     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16U] } },
 339     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 340 /* imm16o: immediate value */
 341   { "imm16o", MT_OPERAND_IMM16O, HW_H_UINT, 15, 16,
 342     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16S] } },
 343     { 0|A(PCREL_ADDR), { { { (1<<MACH_BASE), 0 } } } }  },
 344 /* rc: rc */
 345   { "rc", MT_OPERAND_RC, HW_H_UINT, 15, 1,
 346     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC] } },
 347     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 348 /* rcnum: rcnum */
 349   { "rcnum", MT_OPERAND_RCNUM, HW_H_UINT, 14, 3,
 350     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RCNUM] } },
 351     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 352 /* contnum: context number */
 353   { "contnum", MT_OPERAND_CONTNUM, HW_H_UINT, 8, 9,
 354     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CONTNUM] } },
 355     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 356 /* rbbc: omega network configuration */
 357   { "rbbc", MT_OPERAND_RBBC, HW_H_UINT, 25, 2,
 358     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RBBC] } },
 359     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 360 /* colnum: column number */
 361   { "colnum", MT_OPERAND_COLNUM, HW_H_UINT, 18, 3,
 362     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_COLNUM] } },
 363     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 364 /* rownum: row number */
 365   { "rownum", MT_OPERAND_ROWNUM, HW_H_UINT, 14, 3,
 366     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM] } },
 367     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 368 /* rownum1: row number */
 369   { "rownum1", MT_OPERAND_ROWNUM1, HW_H_UINT, 12, 3,
 370     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM1] } },
 371     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 372 /* rownum2: row number */
 373   { "rownum2", MT_OPERAND_ROWNUM2, HW_H_UINT, 9, 3,
 374     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ROWNUM2] } },
 375     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 376 /* rc1: rc1 */
 377   { "rc1", MT_OPERAND_RC1, HW_H_UINT, 11, 1,
 378     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC1] } },
 379     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 380 /* rc2: rc2 */
 381   { "rc2", MT_OPERAND_RC2, HW_H_UINT, 6, 1,
 382     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC2] } },
 383     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 384 /* cbrb: data-bus orientation */
 385   { "cbrb", MT_OPERAND_CBRB, HW_H_UINT, 10, 1,
 386     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBRB] } },
 387     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 388 /* cell: cell */
 389   { "cell", MT_OPERAND_CELL, HW_H_UINT, 9, 3,
 390     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CELL] } },
 391     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 392 /* dup: dup */
 393   { "dup", MT_OPERAND_DUP, HW_H_UINT, 6, 1,
 394     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_DUP] } },
 395     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 396 /* ctxdisp: context displacement */
 397   { "ctxdisp", MT_OPERAND_CTXDISP, HW_H_UINT, 5, 6,
 398     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CTXDISP] } },
 399     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 400 /* fbdisp: frame buffer displacement */
 401   { "fbdisp", MT_OPERAND_FBDISP, HW_H_UINT, 15, 6,
 402     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBDISP] } },
 403     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 404 /* type: type */
 405   { "type", MT_OPERAND_TYPE, HW_H_UINT, 21, 2,
 406     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_TYPE] } },
 407     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 408 /* mask: mask */
 409   { "mask", MT_OPERAND_MASK, HW_H_UINT, 25, 16,
 410     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK] } },
 411     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 412 /* bankaddr: bank address */
 413   { "bankaddr", MT_OPERAND_BANKADDR, HW_H_UINT, 25, 13,
 414     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BANKADDR] } },
 415     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 416 /* incamt: increment amount */
 417   { "incamt", MT_OPERAND_INCAMT, HW_H_UINT, 19, 8,
 418     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCAMT] } },
 419     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 420 /* xmode: xmode */
 421   { "xmode", MT_OPERAND_XMODE, HW_H_UINT, 23, 1,
 422     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_XMODE] } },
 423     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 424 /* mask1: mask1 */
 425   { "mask1", MT_OPERAND_MASK1, HW_H_UINT, 22, 3,
 426     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MASK1] } },
 427     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 428 /* ball: b_all */
 429   { "ball", MT_OPERAND_BALL, HW_H_UINT, 19, 1,
 430     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL] } },
 431     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 432 /* brc: b_r_c */
 433   { "brc", MT_OPERAND_BRC, HW_H_UINT, 18, 3,
 434     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC] } },
 435     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 436 /* rda: rd */
 437   { "rda", MT_OPERAND_RDA, HW_H_UINT, 25, 1,
 438     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RDA] } },
 439     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 440 /* wr: wr */
 441   { "wr", MT_OPERAND_WR, HW_H_UINT, 24, 1,
 442     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_WR] } },
 443     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 444 /* ball2: b_all2 */
 445   { "ball2", MT_OPERAND_BALL2, HW_H_UINT, 15, 1,
 446     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BALL2] } },
 447     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 448 /* brc2: b_r_c2 */
 449   { "brc2", MT_OPERAND_BRC2, HW_H_UINT, 14, 3,
 450     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_BRC2] } },
 451     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 452 /* perm: perm */
 453   { "perm", MT_OPERAND_PERM, HW_H_UINT, 25, 2,
 454     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_PERM] } },
 455     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 456 /* a23: a23 */
 457   { "a23", MT_OPERAND_A23, HW_H_UINT, 23, 1,
 458     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_A23] } },
 459     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 460 /* cr: c-r */
 461   { "cr", MT_OPERAND_CR, HW_H_UINT, 22, 3,
 462     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CR] } },
 463     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 464 /* cbs: cbs */
 465   { "cbs", MT_OPERAND_CBS, HW_H_UINT, 19, 2,
 466     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBS] } },
 467     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 468 /* incr: incr */
 469   { "incr", MT_OPERAND_INCR, HW_H_UINT, 17, 6,
 470     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_INCR] } },
 471     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 472 /* length: length */
 473   { "length", MT_OPERAND_LENGTH, HW_H_UINT, 15, 3,
 474     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LENGTH] } },
 475     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 476 /* cbx: cbx */
 477   { "cbx", MT_OPERAND_CBX, HW_H_UINT, 14, 3,
 478     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CBX] } },
 479     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 480 /* ccb: ccb */
 481   { "ccb", MT_OPERAND_CCB, HW_H_UINT, 11, 1,
 482     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CCB] } },
 483     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 484 /* cdb: cdb */
 485   { "cdb", MT_OPERAND_CDB, HW_H_UINT, 10, 1,
 486     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CDB] } },
 487     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 488 /* mode: mode */
 489   { "mode", MT_OPERAND_MODE, HW_H_UINT, 25, 2,
 490     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_MODE] } },
 491     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 492 /* id: i/d */
 493   { "id", MT_OPERAND_ID, HW_H_UINT, 14, 1,
 494     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_ID] } },
 495     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 496 /* size: size */
 497   { "size", MT_OPERAND_SIZE, HW_H_UINT, 13, 14,
 498     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_SIZE] } },
 499     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 500 /* fbincr: fb incr */
 501   { "fbincr", MT_OPERAND_FBINCR, HW_H_UINT, 23, 4,
 502     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_FBINCR] } },
 503     { 0, { { { (1<<MACH_BASE), 0 } } } }  },
 504 /* loopsize: immediate value */
 505   { "loopsize", MT_OPERAND_LOOPSIZE, HW_H_UINT, 7, 8,
 506     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_LOOPO] } },
 507     { 0|A(PCREL_ADDR), { { { (1<<MACH_MS2), 0 } } } }  },
 508 /* imm16l: immediate value */
 509   { "imm16l", MT_OPERAND_IMM16L, HW_H_UINT, 23, 16,
 510     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_IMM16L] } },
 511     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
 512 /* rc3: rc3 */
 513   { "rc3", MT_OPERAND_RC3, HW_H_UINT, 7, 1,
 514     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_RC3] } },
 515     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
 516 /* cb1sel: cb1sel */
 517   { "cb1sel", MT_OPERAND_CB1SEL, HW_H_UINT, 25, 3,
 518     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1SEL] } },
 519     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
 520 /* cb2sel: cb2sel */
 521   { "cb2sel", MT_OPERAND_CB2SEL, HW_H_UINT, 22, 3,
 522     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2SEL] } },
 523     { 0, { { { (1<<MACH_MS2), 0 } } } }  },
 524 /* cb1incr: cb1incr */
 525   { "cb1incr", MT_OPERAND_CB1INCR, HW_H_SINT, 19, 6,
 526     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB1INCR] } },
 527     { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
 528 /* cb2incr: cb2incr */
 529   { "cb2incr", MT_OPERAND_CB2INCR, HW_H_SINT, 13, 6,
 530     { 0, { (const PTR) &mt_cgen_ifld_table[MT_F_CB2INCR] } },
 531     { 0|A(SIGNED), { { { (1<<MACH_MS2), 0 } } } }  },
 532 /* sentinel */
 533   { 0, 0, 0, 0, 0,
 534     { 0, { (const PTR) 0 } },
 535     { 0, { { { (1<<MACH_BASE), 0 } } } } }
 536 };
 537
 538 #undef A
 539
 540
 541 /* The instruction table.  */
 542
 543 #define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
 544 #define A(a) (1 << CGEN_INSN_##a)
 545
 546 static const CGEN_IBASE mt_cgen_insn_table[MAX_INSNS] =
 547 {
 548   /* Special null first entry.
 549      A `num' value of zero is thus invalid.
 550      Also, the special `invalid' insn resides here.  */
 551   { 0, 0, 0, 0, { 0, { { { (1<<MACH_BASE), 0 } } } } },
 552 /* add $frdrrr,$frsr1,$frsr2 */
 553   {
 554     MT_INSN_ADD, "add", "add", 32,
 555     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 556   },
 557 /* addu $frdrrr,$frsr1,$frsr2 */
 558   {
 559     MT_INSN_ADDU, "addu", "addu", 32,
 560     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 561   },
 562 /* addi $frdr,$frsr1,#$imm16 */
 563   {
 564     MT_INSN_ADDI, "addi", "addi", 32,
 565     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 566   },
 567 /* addui $frdr,$frsr1,#$imm16z */
 568   {
 569     MT_INSN_ADDUI, "addui", "addui", 32,
 570     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 571   },
 572 /* sub $frdrrr,$frsr1,$frsr2 */
 573   {
 574     MT_INSN_SUB, "sub", "sub", 32,
 575     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 576   },
 577 /* subu $frdrrr,$frsr1,$frsr2 */
 578   {
 579     MT_INSN_SUBU, "subu", "subu", 32,
 580     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 581   },
 582 /* subi $frdr,$frsr1,#$imm16 */
 583   {
 584     MT_INSN_SUBI, "subi", "subi", 32,
 585     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 586   },
 587 /* subui $frdr,$frsr1,#$imm16z */
 588   {
 589     MT_INSN_SUBUI, "subui", "subui", 32,
 590     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 591   },
 592 /* mul $frdrrr,$frsr1,$frsr2 */
 593   {
 594     MT_INSN_MUL, "mul", "mul", 32,
 595     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 596   },
 597 /* muli $frdr,$frsr1,#$imm16 */
 598   {
 599     MT_INSN_MULI, "muli", "muli", 32,
 600     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 601   },
 602 /* and $frdrrr,$frsr1,$frsr2 */
 603   {
 604     MT_INSN_AND, "and", "and", 32,
 605     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 606   },
 607 /* andi $frdr,$frsr1,#$imm16z */
 608   {
 609     MT_INSN_ANDI, "andi", "andi", 32,
 610     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 611   },
 612 /* or $frdrrr,$frsr1,$frsr2 */
 613   {
 614     MT_INSN_OR, "or", "or", 32,
 615     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 616   },
 617 /* nop */
 618   {
 619     MT_INSN_NOP, "nop", "nop", 32,
 620     { 0, { { { (1<<MACH_BASE), 0 } } } }
 621   },
 622 /* ori $frdr,$frsr1,#$imm16z */
 623   {
 624     MT_INSN_ORI, "ori", "ori", 32,
 625     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 626   },
 627 /* xor $frdrrr,$frsr1,$frsr2 */
 628   {
 629     MT_INSN_XOR, "xor", "xor", 32,
 630     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 631   },
 632 /* xori $frdr,$frsr1,#$imm16z */
 633   {
 634     MT_INSN_XORI, "xori", "xori", 32,
 635     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 636   },
 637 /* nand $frdrrr,$frsr1,$frsr2 */
 638   {
 639     MT_INSN_NAND, "nand", "nand", 32,
 640     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 641   },
 642 /* nandi $frdr,$frsr1,#$imm16z */
 643   {
 644     MT_INSN_NANDI, "nandi", "nandi", 32,
 645     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 646   },
 647 /* nor $frdrrr,$frsr1,$frsr2 */
 648   {
 649     MT_INSN_NOR, "nor", "nor", 32,
 650     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 651   },
 652 /* nori $frdr,$frsr1,#$imm16z */
 653   {
 654     MT_INSN_NORI, "nori", "nori", 32,
 655     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 656   },
 657 /* xnor $frdrrr,$frsr1,$frsr2 */
 658   {
 659     MT_INSN_XNOR, "xnor", "xnor", 32,
 660     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 661   },
 662 /* xnori $frdr,$frsr1,#$imm16z */
 663   {
 664     MT_INSN_XNORI, "xnori", "xnori", 32,
 665     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 666   },
 667 /* ldui $frdr,#$imm16z */
 668   {
 669     MT_INSN_LDUI, "ldui", "ldui", 32,
 670     { 0|A(USES_FRDR)|A(AL_INSN), { { { (1<<MACH_BASE), 0 } } } }
 671   },
 672 /* lsl $frdrrr,$frsr1,$frsr2 */
 673   {
 674     MT_INSN_LSL, "lsl", "lsl", 32,
 675     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
 676   },
 677 /* lsli $frdr,$frsr1,#$imm16 */
 678   {
 679     MT_INSN_LSLI, "lsli", "lsli", 32,
 680     { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
 681   },
 682 /* lsr $frdrrr,$frsr1,$frsr2 */
 683   {
 684     MT_INSN_LSR, "lsr", "lsr", 32,
 685     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
 686   },
 687 /* lsri $frdr,$frsr1,#$imm16 */
 688   {
 689     MT_INSN_LSRI, "lsri", "lsri", 32,
 690     { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
 691   },
 692 /* asr $frdrrr,$frsr1,$frsr2 */
 693   {
 694     MT_INSN_ASR, "asr", "asr", 32,
 695     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR), { { { (1<<MACH_BASE), 0 } } } }
 696   },
 697 /* asri $frdr,$frsr1,#$imm16 */
 698   {
 699     MT_INSN_ASRI, "asri", "asri", 32,
 700     { 0|A(USES_FRSR1)|A(USES_FRDR), { { { (1<<MACH_BASE), 0 } } } }
 701   },
 702 /* brlt $frsr1,$frsr2,$imm16o */
 703   {
 704     MT_INSN_BRLT, "brlt", "brlt", 32,
 705     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(USES_FRDRRR)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
 706   },
 707 /* brle $frsr1,$frsr2,$imm16o */
 708   {
 709     MT_INSN_BRLE, "brle", "brle", 32,
 710     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
 711   },
 712 /* breq $frsr1,$frsr2,$imm16o */
 713   {
 714     MT_INSN_BREQ, "breq", "breq", 32,
 715     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
 716   },
 717 /* brne $frsr1,$frsr2,$imm16o */
 718   {
 719     MT_INSN_BRNE, "brne", "brne", 32,
 720     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_BASE), 0 } } } }
 721   },
 722 /* jmp $imm16o */
 723   {
 724     MT_INSN_JMP, "jmp", "jmp", 32,
 725     { 0|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
 726   },
 727 /* jal $frdrrr,$frsr1 */
 728   {
 729     MT_INSN_JAL, "jal", "jal", 32,
 730     { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
 731   },
 732 /* dbnz $frsr1,$imm16o */
 733   {
 734     MT_INSN_DBNZ, "dbnz", "dbnz", 32,
 735     { 0|A(USES_FRSR1)|A(DELAY_SLOT)|A(BR_INSN), { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 736   },
 737 /* ei */
 738   {
 739     MT_INSN_EI, "ei", "ei", 32,
 740     { 0, { { { (1<<MACH_BASE), 0 } } } }
 741   },
 742 /* di */
 743   {
 744     MT_INSN_DI, "di", "di", 32,
 745     { 0, { { { (1<<MACH_BASE), 0 } } } }
 746   },
 747 /* si $frdrrr */
 748   {
 749     MT_INSN_SI, "si", "si", 32,
 750     { 0|A(USES_FRDR)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
 751   },
 752 /* reti $frsr1 */
 753   {
 754     MT_INSN_RETI, "reti", "reti", 32,
 755     { 0|A(JAL_HAZARD)|A(USES_FRSR1)|A(BR_INSN)|A(DELAY_SLOT), { { { (1<<MACH_BASE), 0 } } } }
 756   },
 757 /* ldw $frdr,$frsr1,#$imm16 */
 758   {
 759     MT_INSN_LDW, "ldw", "ldw", 32,
 760     { 0|A(USES_FRSR1)|A(USES_FRDR)|A(MEMORY_ACCESS)|A(LOAD_DELAY), { { { (1<<MACH_BASE), 0 } } } }
 761   },
 762 /* stw $frsr2,$frsr1,#$imm16 */
 763   {
 764     MT_INSN_STW, "stw", "stw", 32,
 765     { 0|A(USES_FRSR2)|A(USES_FRSR1)|A(MEMORY_ACCESS), { { { (1<<MACH_BASE), 0 } } } }
 766   },
 767 /* break */
 768   {
 769     MT_INSN_BREAK, "break", "break", 32,
 770     { 0, { { { (1<<MACH_BASE), 0 } } } }
 771   },
 772 /* iflush */
 773   {
 774     MT_INSN_IFLUSH, "iflush", "iflush", 32,
 775     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 776   },
 777 /* ldctxt $frsr1,$frsr2,#$rc,#$rcnum,#$contnum */
 778   {
 779     MT_INSN_LDCTXT, "ldctxt", "ldctxt", 32,
 780     { 0, { { { (1<<MACH_MS1), 0 } } } }
 781   },
 782 /* ldfb $frsr1,$frsr2,#$imm16z */
 783   {
 784     MT_INSN_LDFB, "ldfb", "ldfb", 32,
 785     { 0, { { { (1<<MACH_MS1), 0 } } } }
 786   },
 787 /* stfb $frsr1,$frsr2,#$imm16z */
 788   {
 789     MT_INSN_STFB, "stfb", "stfb", 32,
 790     { 0, { { { (1<<MACH_MS1), 0 } } } }
 791   },
 792 /* fbcb $frsr1,#$rbbc,#$ball,#$brc,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
 793   {
 794     MT_INSN_FBCB, "fbcb", "fbcb", 32,
 795     { 0, { { { (1<<MACH_MS1)|(1<<MACH_MS1_003), 0 } } } }
 796   },
 797 /* mfbcb $frsr1,#$rbbc,$frsr2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
 798   {
 799     MT_INSN_MFBCB, "mfbcb", "mfbcb", 32,
 800     { 0, { { { (1<<MACH_BASE), 0 } } } }
 801   },
 802 /* fbcci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
 803   {
 804     MT_INSN_FBCCI, "fbcci", "fbcci", 32,
 805     { 0, { { { (1<<MACH_BASE), 0 } } } }
 806   },
 807 /* fbrci $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
 808   {
 809     MT_INSN_FBRCI, "fbrci", "fbrci", 32,
 810     { 0, { { { (1<<MACH_BASE), 0 } } } }
 811   },
 812 /* fbcri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
 813   {
 814     MT_INSN_FBCRI, "fbcri", "fbcri", 32,
 815     { 0, { { { (1<<MACH_BASE), 0 } } } }
 816   },
 817 /* fbrri $frsr1,#$rbbc,#$ball,#$brc,#$fbdisp,#$cell,#$dup,#$ctxdisp */
 818   {
 819     MT_INSN_FBRRI, "fbrri", "fbrri", 32,
 820     { 0, { { { (1<<MACH_BASE), 0 } } } }
 821   },
 822 /* mfbcci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
 823   {
 824     MT_INSN_MFBCCI, "mfbcci", "mfbcci", 32,
 825     { 0, { { { (1<<MACH_BASE), 0 } } } }
 826   },
 827 /* mfbrci $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
 828   {
 829     MT_INSN_MFBRCI, "mfbrci", "mfbrci", 32,
 830     { 0, { { { (1<<MACH_BASE), 0 } } } }
 831   },
 832 /* mfbcri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
 833   {
 834     MT_INSN_MFBCRI, "mfbcri", "mfbcri", 32,
 835     { 0, { { { (1<<MACH_BASE), 0 } } } }
 836   },
 837 /* mfbrri $frsr1,#$rbbc,$frsr2,#$fbdisp,#$cell,#$dup,#$ctxdisp */
 838   {
 839     MT_INSN_MFBRRI, "mfbrri", "mfbrri", 32,
 840     { 0, { { { (1<<MACH_BASE), 0 } } } }
 841   },
 842 /* fbcbdr $frsr1,#$rbbc,$frsr2,#$ball2,#$brc2,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
 843   {
 844     MT_INSN_FBCBDR, "fbcbdr", "fbcbdr", 32,
 845     { 0, { { { (1<<MACH_BASE), 0 } } } }
 846   },
 847 /* rcfbcb #$rbbc,#$type,#$ball,#$brc,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
 848   {
 849     MT_INSN_RCFBCB, "rcfbcb", "rcfbcb", 32,
 850     { 0, { { { (1<<MACH_BASE), 0 } } } }
 851   },
 852 /* mrcfbcb $frsr2,#$rbbc,#$type,#$rownum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
 853   {
 854     MT_INSN_MRCFBCB, "mrcfbcb", "mrcfbcb", 32,
 855     { 0, { { { (1<<MACH_BASE), 0 } } } }
 856   },
 857 /* cbcast #$mask,#$rc2,#$ctxdisp */
 858   {
 859     MT_INSN_CBCAST, "cbcast", "cbcast", 32,
 860     { 0, { { { (1<<MACH_BASE), 0 } } } }
 861   },
 862 /* dupcbcast #$mask,#$cell,#$rc2,#$ctxdisp */
 863   {
 864     MT_INSN_DUPCBCAST, "dupcbcast", "dupcbcast", 32,
 865     { 0, { { { (1<<MACH_BASE), 0 } } } }
 866   },
 867 /* wfbi #$bankaddr,#$rownum1,#$cell,#$dup,#$ctxdisp */
 868   {
 869     MT_INSN_WFBI, "wfbi", "wfbi", 32,
 870     { 0, { { { (1<<MACH_BASE), 0 } } } }
 871   },
 872 /* wfb $frsr1,$frsr2,#$fbdisp,#$rownum2,#$ctxdisp */
 873   {
 874     MT_INSN_WFB, "wfb", "wfb", 32,
 875     { 0, { { { (1<<MACH_BASE), 0 } } } }
 876   },
 877 /* rcrisc $frdrrr,#$rbbc,$frsr1,#$colnum,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
 878   {
 879     MT_INSN_RCRISC, "rcrisc", "rcrisc", 32,
 880     { 0, { { { (1<<MACH_BASE), 0 } } } }
 881   },
 882 /* fbcbinc $frsr1,#$rbbc,#$incamt,#$rc1,#$cbrb,#$cell,#$dup,#$ctxdisp */
 883   {
 884     MT_INSN_FBCBINC, "fbcbinc", "fbcbinc", 32,
 885     { 0, { { { (1<<MACH_BASE), 0 } } } }
 886   },
 887 /* rcxmode $frsr2,#$rda,#$wr,#$xmode,#$mask1,#$fbdisp,#$rownum2,#$rc2,#$ctxdisp */
 888   {
 889     MT_INSN_RCXMODE, "rcxmode", "rcxmode", 32,
 890     { 0, { { { (1<<MACH_BASE), 0 } } } }
 891   },
 892 /* intlvr $frsr1,#$mode,$frsr2,#$id,#$size */
 893   {
 894     MT_INSN_INTERLEAVER, "interleaver", "intlvr", 32,
 895     { 0, { { { (1<<MACH_BASE), 0 } } } }
 896   },
 897 /* wfbinc #$rda,#$wr,#$fbincr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
 898   {
 899     MT_INSN_WFBINC, "wfbinc", "wfbinc", 32,
 900     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 901   },
 902 /* mwfbinc $frsr2,#$rda,#$wr,#$fbincr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
 903   {
 904     MT_INSN_MWFBINC, "mwfbinc", "mwfbinc", 32,
 905     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 906   },
 907 /* wfbincr $frsr1,#$rda,#$wr,#$ball,#$colnum,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
 908   {
 909     MT_INSN_WFBINCR, "wfbincr", "wfbincr", 32,
 910     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 911   },
 912 /* mwfbincr $frsr1,$frsr2,#$rda,#$wr,#$length,#$rownum1,#$rownum2,#$dup,#$ctxdisp */
 913   {
 914     MT_INSN_MWFBINCR, "mwfbincr", "mwfbincr", 32,
 915     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 916   },
 917 /* fbcbincs #$perm,#$a23,#$cr,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
 918   {
 919     MT_INSN_FBCBINCS, "fbcbincs", "fbcbincs", 32,
 920     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 921   },
 922 /* mfbcbincs $frsr1,#$perm,#$cbs,#$incr,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
 923   {
 924     MT_INSN_MFBCBINCS, "mfbcbincs", "mfbcbincs", 32,
 925     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 926   },
 927 /* fbcbincrs $frsr1,#$perm,#$ball,#$colnum,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
 928   {
 929     MT_INSN_FBCBINCRS, "fbcbincrs", "fbcbincrs", 32,
 930     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 931   },
 932 /* mfbcbincrs $frsr1,$frsr2,#$perm,#$cbx,#$ccb,#$cdb,#$rownum2,#$dup,#$ctxdisp */
 933   {
 934     MT_INSN_MFBCBINCRS, "mfbcbincrs", "mfbcbincrs", 32,
 935     { 0, { { { (1<<MACH_MS1_003)|(1<<MACH_MS2), 0 } } } }
 936   },
 937 /* loop $frsr1,$loopsize */
 938   {
 939     MT_INSN_LOOP, "loop", "loop", 32,
 940     { 0|A(USES_FRSR1)|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
 941   },
 942 /* loopi #$imm16l,$loopsize */
 943   {
 944     MT_INSN_LOOPI, "loopi", "loopi", 32,
 945     { 0|A(DELAY_SLOT), { { { (1<<MACH_MS2), 0 } } } }
 946   },
 947 /* dfbc #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
 948   {
 949     MT_INSN_DFBC, "dfbc", "dfbc", 32,
 950     { 0, { { { (1<<MACH_MS2), 0 } } } }
 951   },
 952 /* dwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc2,#$ctxdisp */
 953   {
 954     MT_INSN_DWFB, "dwfb", "dwfb", 32,
 955     { 0, { { { (1<<MACH_MS2), 0 } } } }
 956   },
 957 /* fbwfb #$cb1sel,#$cb2sel,#$cb1incr,#$cb2incr,#$rc3,#$rc2,#$ctxdisp */
 958   {
 959     MT_INSN_FBWFB, "fbwfb", "fbwfb", 32,
 960     { 0, { { { (1<<MACH_MS2), 0 } } } }
 961   },
 962 /* dfbr #$cb1sel,#$cb2sel,$frsr2,#$length,#$rownum1,#$rownum2,#$rc2,#$ctxdisp */
 963   {
 964     MT_INSN_DFBR, "dfbr", "dfbr", 32,
 965     { 0|A(USES_FRSR2), { { { (1<<MACH_MS2), 0 } } } }
 966   },
 967 };
 968
 969 #undef OP
 970 #undef A
 971
 972 /* Initialize anything needed to be done once, before any cpu_open call.  */
 973
 974 static void
 975 init_tables (void)
 976 {
 977 }
 978
 979 #ifndef opcodes_error_handler
 980 #define opcodes_error_handler(...) \
 981   fprintf (stderr, __VA_ARGS__); fputc ('\n', stderr)
 982 #endif
 983
 984 static const CGEN_MACH * lookup_mach_via_bfd_name (const CGEN_MACH *, const char *);
 985 static void build_hw_table      (CGEN_CPU_TABLE *);
 986 static void build_ifield_table  (CGEN_CPU_TABLE *);
 987 static void build_operand_table (CGEN_CPU_TABLE *);
 988 static void build_insn_table    (CGEN_CPU_TABLE *);
 989 static void mt_cgen_rebuild_tables (CGEN_CPU_TABLE *);
 990
 991 /* Subroutine of mt_cgen_cpu_open to look up a mach via its bfd name.  */
 992
 993 static const CGEN_MACH *
 994 lookup_mach_via_bfd_name (const CGEN_MACH *table, const char *name)
 995 {
 996   while (table->name)
 997     {
 998       if (strcmp (name, table->bfd_name) == 0)
 999         return table;
1000       ++table;
1001     }
1002   return NULL;
1003 }
1004
1005 /* Subroutine of mt_cgen_cpu_open to build the hardware table.  */
1006
1007 static void
1008 build_hw_table (CGEN_CPU_TABLE *cd)
1009 {
1010   int i;
1011   int machs = cd->machs;
1012   const CGEN_HW_ENTRY *init = & mt_cgen_hw_table[0];
1013   /* MAX_HW is only an upper bound on the number of selected entries.
1014      However each entry is indexed by it's enum so there can be holes in
1015      the table.  */
1016   const CGEN_HW_ENTRY **selected =
1017     (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1018
1019   cd->hw_table.init_entries = init;
1020   cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1021   memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1022   /* ??? For now we just use machs to determine which ones we want.  */
1023   for (i = 0; init[i].name != NULL; ++i)
1024     if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1025         & machs)
1026       selected[init[i].type] = &init[i];
1027   cd->hw_table.entries = selected;
1028   cd->hw_table.num_entries = MAX_HW;
1029 }
1030
1031 /* Subroutine of mt_cgen_cpu_open to build the hardware table.  */
1032
1033 static void
1034 build_ifield_table (CGEN_CPU_TABLE *cd)
1035 {
1036   cd->ifld_table = & mt_cgen_ifld_table[0];
1037 }
1038
1039 /* Subroutine of mt_cgen_cpu_open to build the hardware table.  */
1040
1041 static void
1042 build_operand_table (CGEN_CPU_TABLE *cd)
1043 {
1044   int i;
1045   int machs = cd->machs;
1046   const CGEN_OPERAND *init = & mt_cgen_operand_table[0];
1047   /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1048      However each entry is indexed by it's enum so there can be holes in
1049      the table.  */
1050   const CGEN_OPERAND **selected = xmalloc (MAX_OPERANDS * sizeof (* selected));
1051
1052   cd->operand_table.init_entries = init;
1053   cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1054   memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1055   /* ??? For now we just use mach to determine which ones we want.  */
1056   for (i = 0; init[i].name != NULL; ++i)
1057     if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1058         & machs)
1059       selected[init[i].type] = &init[i];
1060   cd->operand_table.entries = selected;
1061   cd->operand_table.num_entries = MAX_OPERANDS;
1062 }
1063
1064 /* Subroutine of mt_cgen_cpu_open to build the hardware table.
1065    ??? This could leave out insns not supported by the specified mach/isa,
1066    but that would cause errors like "foo only supported by bar" to become
1067    "unknown insn", so for now we include all insns and require the app to
1068    do the checking later.
1069    ??? On the other hand, parsing of such insns may require their hardware or
1070    operand elements to be in the table [which they mightn't be].  */
1071
1072 static void
1073 build_insn_table (CGEN_CPU_TABLE *cd)
1074 {
1075   int i;
1076   const CGEN_IBASE *ib = & mt_cgen_insn_table[0];
1077   CGEN_INSN *insns = xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1078
1079   memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1080   for (i = 0; i < MAX_INSNS; ++i)
1081     insns[i].base = &ib[i];
1082   cd->insn_table.init_entries = insns;
1083   cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1084   cd->insn_table.num_init_entries = MAX_INSNS;
1085 }
1086
1087 /* Subroutine of mt_cgen_cpu_open to rebuild the tables.  */
1088
1089 static void
1090 mt_cgen_rebuild_tables (CGEN_CPU_TABLE *cd)
1091 {
1092   int i;
1093   CGEN_BITSET *isas = cd->isas;
1094   unsigned int machs = cd->machs;
1095
1096   cd->int_insn_p = CGEN_INT_INSN_P;
1097
1098   /* Data derived from the isa spec.  */
1099 #define UNSET (CGEN_SIZE_UNKNOWN + 1)
1100   cd->default_insn_bitsize = UNSET;
1101   cd->base_insn_bitsize = UNSET;
1102   cd->min_insn_bitsize = 65535; /* Some ridiculously big number.  */
1103   cd->max_insn_bitsize = 0;
1104   for (i = 0; i < MAX_ISAS; ++i)
1105     if (cgen_bitset_contains (isas, i))
1106       {
1107         const CGEN_ISA *isa = & mt_cgen_isa_table[i];
1108
1109         /* Default insn sizes of all selected isas must be
1110            equal or we set the result to 0, meaning "unknown".  */
1111         if (cd->default_insn_bitsize == UNSET)
1112           cd->default_insn_bitsize = isa->default_insn_bitsize;
1113         else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1114           ; /* This is ok.  */
1115         else
1116           cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1117
1118         /* Base insn sizes of all selected isas must be equal
1119            or we set the result to 0, meaning "unknown".  */
1120         if (cd->base_insn_bitsize == UNSET)
1121           cd->base_insn_bitsize = isa->base_insn_bitsize;
1122         else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1123           ; /* This is ok.  */
1124         else
1125           cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1126
1127         /* Set min,max insn sizes.  */
1128         if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1129           cd->min_insn_bitsize = isa->min_insn_bitsize;
1130         if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1131           cd->max_insn_bitsize = isa->max_insn_bitsize;
1132       }
1133
1134   /* Data derived from the mach spec.  */
1135   for (i = 0; i < MAX_MACHS; ++i)
1136     if (((1 << i) & machs) != 0)
1137       {
1138         const CGEN_MACH *mach = & mt_cgen_mach_table[i];
1139
1140         if (mach->insn_chunk_bitsize != 0)
1141         {
1142           if (cd->insn_chunk_bitsize != 0 && cd->insn_chunk_bitsize != mach->insn_chunk_bitsize)
1143             {
1144               opcodes_error_handler
1145                 (/* xgettext:c-format */
1146                  _("internal error: mt_cgen_rebuild_tables: "
1147                    "conflicting insn-chunk-bitsize values: `%d' vs. `%d'"),
1148                  cd->insn_chunk_bitsize, mach->insn_chunk_bitsize);
1149               abort ();
1150             }
1151
1152           cd->insn_chunk_bitsize = mach->insn_chunk_bitsize;
1153         }
1154       }
1155
1156   /* Determine which hw elements are used by MACH.  */
1157   build_hw_table (cd);
1158
1159   /* Build the ifield table.  */
1160   build_ifield_table (cd);
1161
1162   /* Determine which operands are used by MACH/ISA.  */
1163   build_operand_table (cd);
1164
1165   /* Build the instruction table.  */
1166   build_insn_table (cd);
1167 }
1168
1169 /* Initialize a cpu table and return a descriptor.
1170    It's much like opening a file, and must be the first function called.
1171    The arguments are a set of (type/value) pairs, terminated with
1172    CGEN_CPU_OPEN_END.
1173
1174    Currently supported values:
1175    CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1176    CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1177    CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1178    CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1179    CGEN_CPU_OPEN_END:     terminates arguments
1180
1181    ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1182    precluded.  */
1183
1184 CGEN_CPU_DESC
1185 mt_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1186 {
1187   CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
1188   static int init_p;
1189   CGEN_BITSET *isas = 0;  /* 0 = "unspecified" */
1190   unsigned int machs = 0; /* 0 = "unspecified" */
1191   enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
1192   va_list ap;
1193
1194   if (! init_p)
1195     {
1196       init_tables ();
1197       init_p = 1;
1198     }
1199
1200   memset (cd, 0, sizeof (*cd));
1201
1202   va_start (ap, arg_type);
1203   while (arg_type != CGEN_CPU_OPEN_END)
1204     {
1205       switch (arg_type)
1206         {
1207         case CGEN_CPU_OPEN_ISAS :
1208           isas = va_arg (ap, CGEN_BITSET *);
1209           break;
1210         case CGEN_CPU_OPEN_MACHS :
1211           machs = va_arg (ap, unsigned int);
1212           break;
1213         case CGEN_CPU_OPEN_BFDMACH :
1214           {
1215             const char *name = va_arg (ap, const char *);
1216             const CGEN_MACH *mach =
1217               lookup_mach_via_bfd_name (mt_cgen_mach_table, name);
1218
1219             if (mach != NULL)
1220               machs |= 1 << mach->num;
1221             break;
1222           }
1223         case CGEN_CPU_OPEN_ENDIAN :
1224           endian = va_arg (ap, enum cgen_endian);
1225           break;
1226         default :
1227           opcodes_error_handler
1228             (/* xgettext:c-format */
1229              _("internal error: mt_cgen_cpu_open: "
1230                "unsupported argument `%d'"),
1231              arg_type);
1232           abort (); /* ??? return NULL? */
1233         }
1234       arg_type = va_arg (ap, enum cgen_cpu_open_arg);
1235     }
1236   va_end (ap);
1237
1238   /* Mach unspecified means "all".  */
1239   if (machs == 0)
1240     machs = (1 << MAX_MACHS) - 1;
1241   /* Base mach is always selected.  */
1242   machs |= 1;
1243   if (endian == CGEN_ENDIAN_UNKNOWN)
1244     {
1245       /* ??? If target has only one, could have a default.  */
1246       opcodes_error_handler
1247         (/* xgettext:c-format */
1248          _("internal error: mt_cgen_cpu_open: no endianness specified"));
1249       abort ();
1250     }
1251
1252   cd->isas = cgen_bitset_copy (isas);
1253   cd->machs = machs;
1254   cd->endian = endian;
1255   /* FIXME: for the sparc case we can determine insn-endianness statically.
1256      The worry here is where both data and insn endian can be independently
1257      chosen, in which case this function will need another argument.
1258      Actually, will want to allow for more arguments in the future anyway.  */
1259   cd->insn_endian = endian;
1260
1261   /* Table (re)builder.  */
1262   cd->rebuild_tables = mt_cgen_rebuild_tables;
1263   mt_cgen_rebuild_tables (cd);
1264
1265   /* Default to not allowing signed overflow.  */
1266   cd->signed_overflow_ok_p = 0;
1267
1268   return (CGEN_CPU_DESC) cd;
1269 }
1270
1271 /* Cover fn to mt_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
1272    MACH_NAME is the bfd name of the mach.  */
1273
1274 CGEN_CPU_DESC
1275 mt_cgen_cpu_open_1 (const char *mach_name, enum cgen_endian endian)
1276 {
1277   return mt_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
1278                                CGEN_CPU_OPEN_ENDIAN, endian,
1279                                CGEN_CPU_OPEN_END);
1280 }
1281
1282 /* Close a cpu table.
1283    ??? This can live in a machine independent file, but there's currently
1284    no place to put this file (there's no libcgen).  libopcodes is the wrong
1285    place as some simulator ports use this but they don't use libopcodes.  */
1286
1287 void
1288 mt_cgen_cpu_close (CGEN_CPU_DESC cd)
1289 {
1290   unsigned int i;
1291   const CGEN_INSN *insns;
1292
1293   if (cd->macro_insn_table.init_entries)
1294     {
1295       insns = cd->macro_insn_table.init_entries;
1296       for (i = 0; i < cd->macro_insn_table.num_init_entries; ++i, ++insns)
1297         if (CGEN_INSN_RX ((insns)))
1298           regfree (CGEN_INSN_RX (insns));
1299     }
1300
1301   if (cd->insn_table.init_entries)
1302     {
1303       insns = cd->insn_table.init_entries;
1304       for (i = 0; i < cd->insn_table.num_init_entries; ++i, ++insns)
1305         if (CGEN_INSN_RX (insns))
1306           regfree (CGEN_INSN_RX (insns));
1307     }
1308
1309   if (cd->macro_insn_table.init_entries)
1310     free ((CGEN_INSN *) cd->macro_insn_table.init_entries);
1311
1312   if (cd->insn_table.init_entries)
1313     free ((CGEN_INSN *) cd->insn_table.init_entries);
1314
1315   if (cd->hw_table.entries)
1316     free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
1317
1318   if (cd->operand_table.entries)
1319     free ((CGEN_HW_ENTRY *) cd->operand_table.entries);
1320
1321   free (cd);
1322 }
1323