| blob | 49d0f65611311fbe62886e02d79e5a8aa1d3f194 |
1 /* 32-bit ELF support for ARM
2 Copyright (C) 1998-2014 Free Software Foundation, Inc.
4 This file is part of BFD, the Binary File Descriptor library.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program; if not, write to the Free Software
18 Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
19 MA 02110-1301, USA. */
22 #include <limits.h>
33 /* Return the relocation section associated with NAME. HTAB is the
34 bfd's elf32_arm_link_hash_entry. */
35 #define RELOC_SECTION(HTAB, NAME) \
38 /* Return size of a relocation entry. HTAB is the bfd's
39 elf32_arm_link_hash_entry. */
40 #define RELOC_SIZE(HTAB) \
41 ((HTAB)->use_rel \
42 ? sizeof (Elf32_External_Rel) \
43 : sizeof (Elf32_External_Rela))
45 /* Return function to swap relocations in. HTAB is the bfd's
46 elf32_arm_link_hash_entry. */
47 #define SWAP_RELOC_IN(HTAB) \
48 ((HTAB)->use_rel \
49 ? bfd_elf32_swap_reloc_in \
50 : bfd_elf32_swap_reloca_in)
52 /* Return function to swap relocations out. HTAB is the bfd's
53 elf32_arm_link_hash_entry. */
54 #define SWAP_RELOC_OUT(HTAB) \
55 ((HTAB)->use_rel \
56 ? bfd_elf32_swap_reloc_out \
57 : bfd_elf32_swap_reloca_out)
59 #define elf_info_to_howto 0
60 #define elf_info_to_howto_rel elf32_arm_info_to_howto
62 #define ARM_ELF_ABI_VERSION 0
63 #define ARM_ELF_OS_ABI_VERSION ELFOSABI_ARM
65 /* The Adjusted Place, as defined by AAELF. */
66 #define Pa(X) ((X) & 0xfffffffc)
73 /* Note: code such as elf32_arm_reloc_type_lookup expect to use e.g.
74 R_ARM_PC24 as an index into this, and find the R_ARM_PC24 HOWTO
75 in that slot. */
78 {
79 /* No relocation. */
108 /* 32 bit absolute */
123 /* standard 32bit pc-relative reloc */
138 /* 8 bit absolute - R_ARM_LDR_PC_G0 in AAELF */
153 /* 16 bit absolute */
168 /* 12 bit absolute */
197 /* 8 bit absolute */
296 /* BLX instruction for the ARM. */
311 /* BLX instruction for the Thumb. */
326 /* Dynamic TLS relocations. */
370 /* Relocs used in ARM Linux */
834 /* These are declared as 13-bit signed relocations because we can
835 address -4095 .. 4095(base) by altering ADDW to SUBW or vice
836 versa. */
893 /* Group relocations. */
1273 /* End of group relocations. */
1487 /* GNU extension to record C++ vtable member usage */
1502 /* GNU extension to record C++ vtable hierarchy */
1545 /* TLS relocations */
1658 /* 112-127 private relocations. */
1676 /* R_ARM_ME_TOO, obsolete. */
1692 };
1694 /* 160 onwards: */
1696 {
1710 };
1712 /* 249-255 extended, currently unused, relocations: */
1714 {
1770 };
1774 {
1786 }
1788 static void
1791 {
1796 }
1798 struct elf32_arm_reloc_map
1799 {
1800 bfd_reloc_code_real_type bfd_reloc_val;
1802 };
1804 /* All entries in this list must also be present in elf32_arm_howto_table. */
1806 {
1893 };
1897 bfd_reloc_code_real_type code)
1898 {
1906 }
1911 {
1930 }
1932 /* Support for core dump NOTE sections. */
1934 static bfd_boolean
1936 {
1941 {
1946 /* pr_cursig */
1949 /* pr_pid */
1952 /* pr_reg */
1957 }
1959 /* Make a ".reg/999" section. */
1962 }
1964 static bfd_boolean
1966 {
1968 {
1979 }
1981 /* Note that for some reason, a spurious space is tacked
1982 onto the end of the args in some (at least one anyway)
1983 implementations, so strip it off if it exists. */
1984 {
1990 }
1993 }
1998 {
2000 {
2005 {
2017 }
2020 {
2039 }
2040 }
2041 }
2043 #define TARGET_LITTLE_SYM arm_elf32_le_vec
2045 #define TARGET_BIG_SYM arm_elf32_be_vec
2048 #define elf_backend_grok_prstatus elf32_arm_nabi_grok_prstatus
2049 #define elf_backend_grok_psinfo elf32_arm_nabi_grok_psinfo
2050 #define elf_backend_write_core_note elf32_arm_nabi_write_core_note
2055 /* In lieu of proper flags, assume all EABIv4 or later objects are
2056 interworkable. */
2057 #define INTERWORK_FLAG(abfd) \
2058 (EF_ARM_EABI_VERSION (elf_elfheader (abfd)->e_flags) >= EF_ARM_EABI_VER4 \
2059 || (elf_elfheader (abfd)->e_flags & EF_ARM_INTERWORK) \
2060 || ((abfd)->flags & BFD_LINKER_CREATED))
2062 /* The linker script knows the section names for placement.
2063 The entry_names are used to do simple name mangling on the stubs.
2064 Given a function name, and its type, the stub can be found. The
2065 name can be changed. The only requirement is the %s be present. */
2080 /* The name of the dynamic interpreter. This is put in the .interp
2081 section. */
2085 {
2089 };
2092 {
2100 + dl_tlsdesc_lazy_resolver(GOT) */
2102 };
2104 #ifdef FOUR_WORD_PLT
2106 /* The first entry in a procedure linkage table looks like
2107 this. It is set up so that any shared library function that is
2108 called before the relocation has been set up calls the dynamic
2109 linker first. */
2111 {
2116 };
2118 /* Subsequent entries in a procedure linkage table look like
2119 this. */
2121 {
2126 };
2130 /* The first entry in a procedure linkage table looks like
2131 this. It is set up so that any shared library function that is
2132 called before the relocation has been set up calls the dynamic
2133 linker first. */
2135 {
2141 };
2143 /* By default subsequent entries in a procedure linkage table look like
2144 this. Offsets that don't fit into 28 bits will cause link error. */
2146 {
2150 };
2152 /* When explicitly asked, we'll use this "long" entry format
2153 which can cope with arbitrary displacements. */
2155 {
2160 };
2166 /* The first entry in a procedure linkage table looks like this.
2167 It is set up so that any shared library function that is called before the
2168 relocation has been set up calls the dynamic linker first. */
2170 {
2171 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2172 an instruction maybe encoded to one or two array elements. */
2175 /* add lr, pc */
2178 };
2180 /* Subsequent entries in a procedure linkage table for thumb only target
2181 look like this. */
2183 {
2184 /* NOTE: As this is a mixture of 16-bit and 32-bit instructions,
2185 an instruction maybe encoded to one or two array elements. */
2190 /* nop */
2191 };
2193 /* The format of the first entry in the procedure linkage table
2194 for a VxWorks executable. */
2196 {
2201 };
2203 /* The format of subsequent entries in a VxWorks executable. */
2205 {
2212 };
2214 /* The format of entries in a VxWorks shared library. */
2216 {
2223 };
2225 /* An initial stub used if the PLT entry is referenced from Thumb code. */
2226 #define PLT_THUMB_STUB_SIZE 4
2228 {
2231 };
2233 /* The entries in a PLT when using a DLL-based target with multiple
2234 address spaces. */
2236 {
2239 };
2241 /* The first entry in a procedure linkage table looks like
2242 this. It is set up so that any shared library function that is
2243 called before the relocation has been set up calls the dynamic
2244 linker first. */
2246 {
2247 /* First bundle: */
2252 /* Second bundle: */
2257 /* Third bundle: */
2261 /* .Lplt_tail: */
2263 /* Fourth bundle: */
2268 };
2269 #define ARM_NACL_PLT_TAIL_OFFSET (11 * 4)
2271 /* Subsequent entries in a procedure linkage table look like this. */
2273 {
2278 };
2280 #define ARM_MAX_FWD_BRANCH_OFFSET ((((1 << 23) - 1) << 2) + 8)
2281 #define ARM_MAX_BWD_BRANCH_OFFSET ((-((1 << 23) << 2)) + 8)
2282 #define THM_MAX_FWD_BRANCH_OFFSET ((1 << 22) -2 + 4)
2283 #define THM_MAX_BWD_BRANCH_OFFSET (-(1 << 22) + 4)
2284 #define THM2_MAX_FWD_BRANCH_OFFSET (((1 << 24) - 2) + 4)
2285 #define THM2_MAX_BWD_BRANCH_OFFSET (-(1 << 24) + 4)
2286 #define THM2_MAX_FWD_COND_BRANCH_OFFSET (((1 << 20) -2) + 4)
2287 #define THM2_MAX_BWD_COND_BRANCH_OFFSET (-(1 << 20) + 4)
2289 enum stub_insn_type
2290 {
2292 THUMB32_TYPE,
2293 ARM_TYPE,
2294 DATA_TYPE
2295 };
2297 #define THUMB16_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 0}
2298 /* A bit of a hack. A Thumb conditional branch, in which the proper condition
2299 is inserted in arm_build_one_stub(). */
2300 #define THUMB16_BCOND_INSN(X) {(X), THUMB16_TYPE, R_ARM_NONE, 1}
2301 #define THUMB32_INSN(X) {(X), THUMB32_TYPE, R_ARM_NONE, 0}
2302 #define THUMB32_B_INSN(X, Z) {(X), THUMB32_TYPE, R_ARM_THM_JUMP24, (Z)}
2303 #define ARM_INSN(X) {(X), ARM_TYPE, R_ARM_NONE, 0}
2304 #define ARM_REL_INSN(X, Z) {(X), ARM_TYPE, R_ARM_JUMP24, (Z)}
2305 #define DATA_WORD(X,Y,Z) {(X), DATA_TYPE, (Y), (Z)}
2308 {
2309 bfd_vma data;
2315 /* Arm/Thumb -> Arm/Thumb long branch stub. On V5T and above, use blx
2316 to reach the stub if necessary. */
2318 {
2321 };
2323 /* V4T Arm -> Thumb long branch stub. Used on V4T where blx is not
2324 available. */
2326 {
2330 };
2332 /* Thumb -> Thumb long branch stub. Used on M-profile architectures. */
2334 {
2342 };
2344 /* V4T Thumb -> Thumb long branch stub. Using the stack is not
2345 allowed. */
2347 {
2353 };
2355 /* V4T Thumb -> ARM long branch stub. Used on V4T where blx is not
2356 available. */
2358 {
2363 };
2365 /* V4T Thumb -> ARM short branch stub. Shorter variant of the above
2366 one, when the destination is close enough. */
2368 {
2372 };
2374 /* ARM/Thumb -> ARM long branch stub, PIC. On V5T and above, use
2375 blx to reach the stub if necessary. */
2377 {
2381 };
2383 /* ARM/Thumb -> Thumb long branch stub, PIC. On V5T and above, use
2384 blx to reach the stub if necessary. We can not add into pc;
2385 it is not guaranteed to mode switch (different in ARMv6 and
2386 ARMv7). */
2388 {
2393 };
2395 /* V4T ARM -> ARM long branch stub, PIC. */
2397 {
2402 };
2404 /* V4T Thumb -> ARM long branch stub, PIC. */
2406 {
2412 };
2414 /* Thumb -> Thumb long branch stub, PIC. Used on M-profile
2415 architectures. */
2417 {
2425 };
2427 /* V4T Thumb -> Thumb long branch stub, PIC. Using the stack is not
2428 allowed. */
2430 {
2437 };
2439 /* Thumb2/ARM -> TLS trampoline. Lowest common denominator, which is a
2440 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2442 {
2446 };
2448 /* V4T Thumb -> TLS trampoline. lowest common denominator, which is a
2449 long PIC stub. We can use r1 as a scratch -- and cannot use ip. */
2451 {
2457 };
2459 /* NaCl ARM -> ARM long branch stub. */
2461 {
2470 };
2472 /* NaCl ARM -> ARM long branch stub, PIC. */
2474 {
2483 };
2486 /* Cortex-A8 erratum-workaround stubs. */
2488 /* Stub used for conditional branches (which may be beyond +/-1MB away, so we
2489 can't use a conditional branch to reach this stub). */
2492 {
2496 };
2498 /* Stub used for b.w and bl.w instructions. */
2501 {
2503 };
2506 {
2508 };
2510 /* Stub used for Thumb-2 blx.w instructions. We modified the original blx.w
2511 instruction (which switches to ARM mode) to point to this stub. Jump to the
2512 real destination using an ARM-mode branch. */
2515 {
2517 };
2519 /* For each section group there can be a specially created linker section
2520 to hold the stubs for that group. The name of the stub section is based
2521 upon the name of another section within that group with the suffix below
2522 applied.
2524 PR 13049: STUB_SUFFIX used to be ".stub", but this allowed the user to
2525 create what appeared to be a linker stub section when it actually
2526 contained user code/data. For example, consider this fragment:
2528 const char * stubborn_problems[] = { "np" };
2530 If this is compiled with "-fPIC -fdata-sections" then gcc produces a
2531 section called:
2533 .data.rel.local.stubborn_problems
2535 This then causes problems in arm32_arm_build_stubs() as it triggers:
2537 // Ignore non-stub sections.
2538 if (!strstr (stub_sec->name, STUB_SUFFIX))
2539 continue;
2541 And so the section would be ignored instead of being processed. Hence
2542 the change in definition of STUB_SUFFIX to a name that cannot be a valid
2543 C identifier. */
2546 /* One entry per long/short branch stub defined above. */
2547 #define DEF_STUBS \
2548 DEF_STUB(long_branch_any_any) \
2549 DEF_STUB(long_branch_v4t_arm_thumb) \
2550 DEF_STUB(long_branch_thumb_only) \
2551 DEF_STUB(long_branch_v4t_thumb_thumb) \
2552 DEF_STUB(long_branch_v4t_thumb_arm) \
2553 DEF_STUB(short_branch_v4t_thumb_arm) \
2554 DEF_STUB(long_branch_any_arm_pic) \
2555 DEF_STUB(long_branch_any_thumb_pic) \
2556 DEF_STUB(long_branch_v4t_thumb_thumb_pic) \
2557 DEF_STUB(long_branch_v4t_arm_thumb_pic) \
2558 DEF_STUB(long_branch_v4t_thumb_arm_pic) \
2559 DEF_STUB(long_branch_thumb_only_pic) \
2560 DEF_STUB(long_branch_any_tls_pic) \
2561 DEF_STUB(long_branch_v4t_thumb_tls_pic) \
2562 DEF_STUB(long_branch_arm_nacl) \
2563 DEF_STUB(long_branch_arm_nacl_pic) \
2564 DEF_STUB(a8_veneer_b_cond) \
2565 DEF_STUB(a8_veneer_b) \
2566 DEF_STUB(a8_veneer_bl) \
2567 DEF_STUB(a8_veneer_blx)
2569 #define DEF_STUB(x) arm_stub_##x,
2570 enum elf32_arm_stub_type
2571 {
2572 arm_stub_none,
2573 DEF_STUBS
2574 /* Note the first a8_veneer type. */
2575 arm_stub_a8_veneer_lwm = arm_stub_a8_veneer_b_cond
2576 };
2577 #undef DEF_STUB
2580 {
2585 #define DEF_STUB(x) {elf32_arm_stub_##x, ARRAY_SIZE(elf32_arm_stub_##x)},
2587 {
2589 DEF_STUBS
2590 };
2592 struct elf32_arm_stub_hash_entry
2593 {
2594 /* Base hash table entry structure. */
2597 /* The stub section. */
2600 /* Offset within stub_sec of the beginning of this stub. */
2601 bfd_vma stub_offset;
2603 /* Given the symbol's value and its section we can determine its final
2604 value when building the stubs (so the stub knows where to jump). */
2605 bfd_vma target_value;
2608 /* Offset to apply to relocation referencing target_value. */
2609 bfd_vma target_addend;
2611 /* The instruction which caused this stub to be generated (only valid for
2612 Cortex-A8 erratum workaround stubs at present). */
2615 /* The stub type. */
2617 /* Its encoding size in bytes. */
2619 /* Its template. */
2621 /* The size of the template (number of entries). */
2624 /* The symbol table entry, if any, that this was derived from. */
2627 /* Type of branch. */
2630 /* Where this stub is being called from, or, in the case of combined
2631 stub sections, the first input section in the group. */
2634 /* The name for the local symbol at the start of this stub. The
2635 stub name in the hash table has to be unique; this does not, so
2636 it can be friendlier. */
2638 };
2640 /* Used to build a map of a section. This is required for mixed-endian
2641 code/data. */
2644 {
2645 bfd_vma vma;
2647 }
2648 elf32_arm_section_map;
2650 /* Information about a VFP11 erratum veneer, or a branch to such a veneer. */
2653 {
2654 VFP11_ERRATUM_BRANCH_TO_ARM_VENEER,
2655 VFP11_ERRATUM_BRANCH_TO_THUMB_VENEER,
2656 VFP11_ERRATUM_ARM_VENEER,
2657 VFP11_ERRATUM_THUMB_VENEER
2658 }
2659 elf32_vfp11_erratum_type;
2662 {
2664 bfd_vma vma;
2665 union
2666 {
2667 struct
2668 {
2672 struct
2673 {
2678 elf32_vfp11_erratum_type type;
2679 }
2680 elf32_vfp11_erratum_list;
2683 {
2684 DELETE_EXIDX_ENTRY,
2685 INSERT_EXIDX_CANTUNWIND_AT_END
2686 }
2687 arm_unwind_edit_type;
2689 /* A (sorted) list of edits to apply to an unwind table. */
2691 {
2692 arm_unwind_edit_type type;
2693 /* Note: we sometimes want to insert an unwind entry corresponding to a
2694 section different from the one we're currently writing out, so record the
2695 (text) section this edit relates to here. */
2699 }
2700 arm_unwind_table_edit;
2703 {
2704 /* Information about mapping symbols. */
2709 /* Information about CPU errata. */
2712 /* Information about unwind tables. */
2713 union
2714 {
2715 /* Unwind info attached to a text section. */
2716 struct
2717 {
2721 /* Unwind info attached to an .ARM.exidx section. */
2722 struct
2723 {
2728 }
2729 _arm_elf_section_data;
2731 #define elf32_arm_section_data(sec) \
2732 ((_arm_elf_section_data *) elf_section_data (sec))
2734 /* A fix which might be required for Cortex-A8 Thumb-2 branch/TLB erratum.
2735 These fixes are subject to a relaxation procedure (in elf32_arm_size_stubs),
2736 so may be created multiple times: we use an array of these entries whilst
2737 relaxing which we can refresh easily, then create stubs for each potentially
2738 erratum-triggering instruction once we've settled on a solution. */
2740 struct a8_erratum_fix
2741 {
2744 bfd_vma offset;
2745 bfd_vma addend;
2750 };
2752 /* A table of relocs applied to branches which might trigger Cortex-A8
2753 erratum. */
2755 struct a8_erratum_reloc
2756 {
2757 bfd_vma from;
2758 bfd_vma destination;
2763 bfd_boolean non_a8_stub;
2764 };
2766 /* The size of the thread control block. */
2767 #define TCB_SIZE 8
2769 /* ARM-specific information about a PLT entry, over and above the usual
2770 gotplt_union. */
2771 struct arm_plt_info
2772 {
2773 /* We reference count Thumb references to a PLT entry separately,
2774 so that we can emit the Thumb trampoline only if needed. */
2775 bfd_signed_vma thumb_refcount;
2777 /* Some references from Thumb code may be eliminated by BL->BLX
2778 conversion, so record them separately. */
2779 bfd_signed_vma maybe_thumb_refcount;
2781 /* How many of the recorded PLT accesses were from non-call relocations.
2782 This information is useful when deciding whether anything takes the
2783 address of an STT_GNU_IFUNC PLT. A value of 0 means that all
2784 non-call references to the function should resolve directly to the
2785 real runtime target. */
2788 /* Since PLT entries have variable size if the Thumb prologue is
2789 used, we need to record the index into .got.plt instead of
2790 recomputing it from the PLT offset. */
2791 bfd_signed_vma got_offset;
2792 };
2794 /* Information about an .iplt entry for a local STT_GNU_IFUNC symbol. */
2795 struct arm_local_iplt_info
2796 {
2797 /* The information that is usually found in the generic ELF part of
2798 the hash table entry. */
2801 /* The information that is usually found in the ARM-specific part of
2802 the hash table entry. */
2805 /* A list of all potential dynamic relocations against this symbol. */
2807 };
2809 struct elf_arm_obj_tdata
2810 {
2813 /* tls_type for each local got entry. */
2816 /* GOTPLT entries for TLS descriptors. */
2819 /* Information for local symbols that need entries in .iplt. */
2822 /* Zero to warn when linking objects with incompatible enum sizes. */
2825 /* Zero to warn when linking objects with incompatible wchar_t sizes. */
2827 };
2829 #define elf_arm_tdata(bfd) \
2830 ((struct elf_arm_obj_tdata *) (bfd)->tdata.any)
2832 #define elf32_arm_local_got_tls_type(bfd) \
2833 (elf_arm_tdata (bfd)->local_got_tls_type)
2835 #define elf32_arm_local_tlsdesc_gotent(bfd) \
2836 (elf_arm_tdata (bfd)->local_tlsdesc_gotent)
2838 #define elf32_arm_local_iplt(bfd) \
2839 (elf_arm_tdata (bfd)->local_iplt)
2841 #define is_arm_elf(bfd) \
2842 (bfd_get_flavour (bfd) == bfd_target_elf_flavour \
2843 && elf_tdata (bfd) != NULL \
2844 && elf_object_id (bfd) == ARM_ELF_DATA)
2846 static bfd_boolean
2848 {
2850 ARM_ELF_DATA);
2851 }
2853 #define elf32_arm_hash_entry(ent) ((struct elf32_arm_link_hash_entry *)(ent))
2855 /* Arm ELF linker hash entry. */
2856 struct elf32_arm_link_hash_entry
2857 {
2860 /* Track dynamic relocs copied for this symbol. */
2863 /* ARM-specific PLT information. */
2866 #define GOT_UNKNOWN 0
2867 #define GOT_NORMAL 1
2868 #define GOT_TLS_GD 2
2869 #define GOT_TLS_IE 4
2870 #define GOT_TLS_GDESC 8
2871 #define GOT_TLS_GD_ANY_P(type) ((type & GOT_TLS_GD) || (type & GOT_TLS_GDESC))
2874 /* True if the symbol's PLT entry is in .iplt rather than .plt. */
2879 /* Offset of the GOTPLT entry reserved for the TLS descriptor,
2880 starting at the end of the jump table. */
2881 bfd_vma tlsdesc_got;
2883 /* The symbol marking the real symbol location for exported thumb
2884 symbols with Arm stubs. */
2887 /* A pointer to the most recently used stub hash entry against this
2888 symbol. */
2890 };
2892 /* Traverse an arm ELF linker hash table. */
2893 #define elf32_arm_link_hash_traverse(table, func, info) \
2894 (elf_link_hash_traverse \
2895 (&(table)->root, \
2896 (bfd_boolean (*) (struct elf_link_hash_entry *, void *)) (func), \
2897 (info)))
2899 /* Get the ARM elf linker hash table from a link_info structure. */
2900 #define elf32_arm_hash_table(info) \
2901 (elf_hash_table_id ((struct elf_link_hash_table *) ((info)->hash)) \
2902 == ARM_ELF_DATA ? ((struct elf32_arm_link_hash_table *) ((info)->hash)) : NULL)
2904 #define arm_stub_hash_lookup(table, string, create, copy) \
2905 ((struct elf32_arm_stub_hash_entry *) \
2906 bfd_hash_lookup ((table), (string), (create), (copy)))
2908 /* Array to keep track of which stub sections have been created, and
2909 information on stub grouping. */
2910 struct map_stub
2911 {
2912 /* This is the section to which stubs in the group will be
2913 attached. */
2915 /* The stub section. */
2917 };
2919 #define elf32_arm_compute_jump_table_size(htab) \
2920 ((htab)->next_tls_desc_index * 4)
2922 /* ARM ELF linker hash table. */
2923 struct elf32_arm_link_hash_table
2924 {
2925 /* The main hash table. */
2928 /* The size in bytes of the section containing the Thumb-to-ARM glue. */
2929 bfd_size_type thumb_glue_size;
2931 /* The size in bytes of the section containing the ARM-to-Thumb glue. */
2932 bfd_size_type arm_glue_size;
2934 /* The size in bytes of section containing the ARMv4 BX veneers. */
2935 bfd_size_type bx_glue_size;
2937 /* Offsets of ARMv4 BX veneers. Bit1 set if present, and Bit0 set when
2938 veneer has been populated. */
2941 /* The size in bytes of the section containing glue for VFP11 erratum
2942 veneers. */
2943 bfd_size_type vfp11_erratum_glue_size;
2945 /* A table of fix locations for Cortex-A8 Thumb-2 branch/TLB erratum. This
2946 holds Cortex-A8 erratum fix locations between elf32_arm_size_stubs() and
2947 elf32_arm_write_section(). */
2951 /* An arbitrary input BFD chosen to hold the glue sections. */
2954 /* Nonzero to output a BE8 image. */
2957 /* Zero if R_ARM_TARGET1 means R_ARM_ABS32.
2958 Nonzero if R_ARM_TARGET1 means R_ARM_REL32. */
2961 /* The relocation to use for R_ARM_TARGET2 relocations. */
2964 /* 0 = Ignore R_ARM_V4BX.
2965 1 = Convert BX to MOV PC.
2966 2 = Generate v4 interworing stubs. */
2969 /* Whether we should fix the Cortex-A8 Thumb-2 branch/TLB erratum. */
2972 /* Whether we should fix the ARM1176 BLX immediate issue. */
2975 /* Nonzero if the ARM/Thumb BLX instructions are available for use. */
2978 /* What sort of code sequences we should look for which may trigger the
2979 VFP11 denorm erratum. */
2980 bfd_arm_vfp11_fix vfp11_fix;
2982 /* Global counter for the number of fixes we have emitted. */
2985 /* Nonzero to force PIC branch veneers. */
2988 /* The number of bytes in the initial entry in the PLT. */
2989 bfd_size_type plt_header_size;
2991 /* The number of bytes in the subsequent PLT etries. */
2992 bfd_size_type plt_entry_size;
2994 /* True if the target system is VxWorks. */
2997 /* True if the target system is Symbian OS. */
3000 /* True if the target system is Native Client. */
3003 /* True if the target uses REL relocations. */
3006 /* The index of the next unused R_ARM_TLS_DESC slot in .rel.plt. */
3007 bfd_vma next_tls_desc_index;
3009 /* How many R_ARM_TLS_DESC relocations were generated so far. */
3010 bfd_vma num_tls_desc;
3012 /* Short-cuts to get to dynamic linker sections. */
3016 /* The (unloaded but important) VxWorks .rela.plt.unloaded section. */
3019 /* The offset into splt of the PLT entry for the TLS descriptor
3020 resolver. Special values are 0, if not necessary (or not found
3021 to be necessary yet), and -1 if needed but not determined
3022 yet. */
3023 bfd_vma dt_tlsdesc_plt;
3025 /* The offset into sgot of the GOT entry used by the PLT entry
3026 above. */
3027 bfd_vma dt_tlsdesc_got;
3029 /* Offset in .plt section of tls_arm_trampoline. */
3030 bfd_vma tls_trampoline;
3032 /* Data for R_ARM_TLS_LDM32 relocations. */
3033 union
3034 {
3035 bfd_signed_vma refcount;
3036 bfd_vma offset;
3039 /* Small local sym cache. */
3042 /* For convenience in allocate_dynrelocs. */
3045 /* The amount of space used by the reserved portion of the sgotplt
3046 section, plus whatever space is used by the jump slots. */
3047 bfd_vma sgotplt_jump_table_size;
3049 /* The stub hash table. */
3052 /* Linker stub bfd. */
3055 /* Linker call-backs. */
3059 /* Array to keep track of which stub sections have been created, and
3060 information on stub grouping. */
3063 /* Number of elements in stub_group. */
3066 /* Assorted information used by elf32_arm_size_stubs. */
3070 };
3072 /* Create an entry in an ARM ELF linker hash table. */
3078 {
3082 /* Allocate the structure if it has not already been allocated by a
3083 subclass. */
3090 /* Call the allocation method of the superclass. */
3095 {
3107 }
3110 }
3112 /* Ensure that we have allocated bookkeeping structures for ABFD's local
3113 symbols. */
3115 static bfd_boolean
3117 {
3119 {
3120 bfd_size_type num_syms;
3121 bfd_size_type size;
3143 }
3145 }
3147 /* Return the .iplt information for local symbol R_SYMNDX, which belongs
3148 to input bfd ABFD. Create the information if it doesn't already exist.
3149 Return null if an allocation fails. */
3153 {
3164 }
3166 /* Try to obtain PLT information for the symbol with index R_SYMNDX
3167 in ABFD's symbol table. If the symbol is global, H points to its
3168 hash table entry, otherwise H is null.
3170 Return true if the symbol does have PLT information. When returning
3171 true, point *ROOT_PLT at the target-independent reference count/offset
3172 union and *ARM_PLT at the ARM-specific information. */
3174 static bfd_boolean
3178 {
3182 {
3186 }
3198 }
3200 /* Return true if the PLT described by ARM_PLT requires a Thumb stub
3201 before it. */
3203 static bfd_boolean
3206 {
3212 }
3214 /* Return a pointer to the head of the dynamic reloc list that should
3215 be used for local symbol ISYM, which is symbol number R_SYMNDX in
3216 ABFD's symbol table. Return null if an error occurs. */
3221 {
3223 {
3230 }
3231 else
3232 {
3233 /* Track dynamic relocs needed for local syms too.
3234 We really need local syms available to do this
3235 easily. Oh well. */
3245 }
3246 }
3248 /* Initialize an entry in the stub hash table. */
3254 {
3255 /* Allocate the structure if it has not already been allocated by a
3256 subclass. */
3258 {
3263 }
3265 /* Call the allocation method of the superclass. */
3268 {
3271 /* Initialize the local fields. */
3286 }
3289 }
3291 /* Create .got, .gotplt, and .rel(a).got sections in DYNOBJ, and set up
3292 shortcuts to them in our hash table. */
3294 static bfd_boolean
3296 {
3303 /* BPABI objects never have a GOT, or associated sections. */
3311 }
3313 /* Create the .iplt, .rel(a).iplt and .igot.plt sections. */
3315 static bfd_boolean
3317 {
3322 flagword flags;
3330 {
3337 }
3340 {
3348 }
3351 {
3357 }
3359 }
3361 /* Determine if we're dealing with a Thumb only architecture. */
3363 static bfd_boolean
3365 {
3367 Tag_CPU_arch);
3377 Tag_CPU_arch_profile);
3380 }
3382 /* Determine if we're dealing with a Thumb-2 object. */
3384 static bfd_boolean
3386 {
3388 Tag_CPU_arch);
3390 }
3392 /* Create .plt, .rel(a).plt, .got, .got.plt, .rel(a).got, .dynbss, and
3393 .rel(a).bss sections in DYNOBJ, and set up shortcuts to them in our
3394 hash table. */
3396 static bfd_boolean
3398 {
3417 {
3422 {
3424 htab->plt_entry_size
3426 }
3427 else
3428 {
3429 htab->plt_header_size
3431 htab->plt_entry_size
3433 }
3434 }
3435 else
3436 {
3437 /* PR ld/16017
3438 Test for thumb only architectures. Note - we cannot just call
3439 using_thumb_only() as the attributes in the output bfd have not been
3440 initialised at this point, so instead we use the input bfd. */
3445 {
3448 }
3450 }
3459 }
3461 /* Copy the extra info we tack onto an elf_link_hash_entry. */
3463 static void
3467 {
3474 {
3476 {
3480 /* Add reloc counts against the indirect sym to the direct sym
3481 list. Merge any entries against the same section. */
3483 {
3488 {
3493 }
3496 }
3498 }
3502 }
3505 {
3506 /* Copy over PLT info. */
3514 /* We should only allocate a function to .iplt once the final
3515 symbol information is known. */
3519 {
3522 }
3523 }
3526 }
3528 /* Destroy an ARM elf linker hash table. */
3530 static void
3532 {
3538 }
3540 /* Create an ARM elf linker hash table. */
3544 {
3553 elf32_arm_link_hash_newfunc,
3555 ARM_ELF_DATA))
3556 {
3559 }
3562 #ifdef FOUR_WORD_PLT
3565 #else
3568 #endif
3574 {
3577 }
3581 }
3583 /* Determine what kind of NOPs are available. */
3585 static bfd_boolean
3587 {
3589 Tag_CPU_arch);
3594 }
3596 static bfd_boolean
3598 {
3600 Tag_CPU_arch);
3603 }
3605 static bfd_boolean
3607 {
3609 {
3623 }
3624 }
3626 /* Determine the type of stub needed, if any, for a call. */
3628 static enum elf32_arm_stub_type
3635 bfd_vma destination,
3639 {
3640 bfd_vma location;
3641 bfd_signed_vma branch_offset;
3663 /* Determine where the call point is. */
3670 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
3671 are considering a function call relocation. */
3677 /* For TLS call relocs, it is the caller's responsibility to provide
3678 the address of the appropriate trampoline. */
3684 {
3689 else
3692 {
3695 /* Note when dealing with PLT entries: the main PLT stub is in
3696 ARM mode, so if the branch is in Thumb mode, another
3697 Thumb->ARM stub will be inserted later just before the ARM
3698 PLT stub. We don't take this extra distance into account
3699 here, because if a long branch stub is needed, we'll add a
3700 Thumb->Arm one and branch directly to the ARM PLT entry
3701 because it avoids spreading offset corrections in several
3702 places. */
3709 }
3710 }
3711 /* Calls to STT_GNU_IFUNC symbols should go through a PLT. */
3718 {
3719 /* Handle cases where:
3720 - this call goes too far (different Thumb/Thumb2 max
3721 distance)
3722 - it's a Thumb->Arm call and blx is not available, or it's a
3723 Thumb->Arm branch (not bl). A stub is needed in this case,
3724 but only if this call is not through a PLT entry. Indeed,
3725 PLT stubs handle mode switching already.
3726 */
3730 || (thumb2
3733 || (thumb2
3743 {
3745 {
3746 /* Thumb to thumb. */
3748 {
3750 /* PIC stubs. */
3753 /* V5T and above. Stub starts with ARM code, so
3754 we must be able to switch mode before
3755 reaching it, which is only possible for 'bl'
3756 (ie R_ARM_THM_CALL relocation). */
3757 ? arm_stub_long_branch_any_thumb_pic
3758 /* On V4T, use Thumb code only. */
3761 /* non-PIC stubs. */
3764 /* V5T and above. */
3765 ? arm_stub_long_branch_any_any
3766 /* V4T. */
3768 }
3769 else
3770 {
3772 /* PIC stub. */
3773 ? arm_stub_long_branch_thumb_only_pic
3774 /* non-PIC stub. */
3776 }
3777 }
3778 else
3779 {
3780 /* Thumb to arm. */
3784 {
3789 }
3791 stub_type =
3793 /* PIC stubs. */
3795 /* TLS PIC stubs. */
3799 /* V5T PIC and above. */
3800 ? arm_stub_long_branch_any_arm_pic
3801 /* V4T PIC stub. */
3804 /* non-PIC stubs. */
3806 /* V5T and above. */
3807 ? arm_stub_long_branch_any_any
3808 /* V4T. */
3811 /* Handle v4t short branches. */
3816 }
3817 }
3818 }
3823 {
3825 {
3826 /* Arm to thumb. */
3831 {
3836 }
3838 /* We have an extra 2-bytes reach because of
3839 the mode change (bit 24 (H) of BLX encoding). */
3845 {
3847 /* PIC stubs. */
3849 /* V5T and above. */
3850 ? arm_stub_long_branch_any_thumb_pic
3851 /* V4T stub. */
3854 /* non-PIC stubs. */
3856 /* V5T and above. */
3857 ? arm_stub_long_branch_any_any
3858 /* V4T. */
3860 }
3861 }
3862 else
3863 {
3864 /* Arm to arm. */
3867 {
3868 stub_type =
3870 /* PIC stubs. */
3872 /* TLS PIC Stub. */
3873 ? arm_stub_long_branch_any_tls_pic
3875 ? arm_stub_long_branch_arm_nacl_pic
3877 /* non-PIC stubs. */
3879 ? arm_stub_long_branch_arm_nacl
3881 }
3882 }
3883 }
3885 /* If a stub is needed, record the actual destination type. */
3890 }
3892 /* Build a name for an entry in the stub hash table. */
3900 {
3902 bfd_size_type len;
3905 {
3914 }
3915 else
3916 {
3928 }
3931 }
3933 /* Look up an entry in the stub hash. Stub entries are cached because
3934 creating the stub name takes a bit of time. */
3943 {
3951 /* If this input section is part of a group of sections sharing one
3952 stub section, then use the id of the first section in the group.
3953 Stub names need to include a section id, as there may well be
3954 more than one stub used to reach say, printf, and we need to
3955 distinguish between them. */
3962 {
3964 }
3965 else
3966 {
3979 }
3982 }
3984 /* Find or create a stub section. Returns a pointer to the stub section, and
3985 the section to which the stub section will be attached (in *LINK_SEC_P).
3986 LINK_SEC_P may be NULL. */
3991 {
4000 {
4003 {
4005 bfd_size_type len;
4021 }
4023 }
4029 }
4031 /* Add a new stub entry to the stub hash. Not all fields of the new
4032 stub entry are initialised. */
4038 {
4047 /* Enter this entry into the linker stub hash table. */
4051 {
4054 stub_name);
4056 }
4063 }
4065 /* Store an Arm insn into an output section not processed by
4066 elf32_arm_write_section. */
4068 static void
4071 {
4074 else
4076 }
4078 /* Store a 16-bit Thumb insn into an output section not processed by
4079 elf32_arm_write_section. */
4081 static void
4084 {
4087 else
4089 }
4091 /* If it's possible to change R_TYPE to a more efficient access
4092 model, return the new reloc type. */
4094 static unsigned
4097 {
4103 /* We do not support relaxations for Old TLS models. */
4105 {
4112 }
4115 }
4117 static bfd_reloc_status_type elf32_arm_final_link_relocate
4123 static unsigned int
4125 {
4127 {
4156 }
4157 }
4159 static bfd_boolean
4162 {
4163 #define MAXRELOCS 3
4170 bfd_vma sym_value;
4179 /* Massage our args to the form they really have. */
4191 /* We have to do less-strictly-aligned fixes last. */
4194 /* Make a note of the offset within the stubs for this entry. */
4200 /* This is the address of the stub destination. */
4210 {
4212 {
4214 {
4217 {
4218 /* We've borrowed the reloc_addend field to mean we should
4219 insert a condition code into this (Thumb-1 branch)
4220 instruction. See THUMB16_BCOND_INSN. */
4223 }
4226 }
4236 {
4239 }
4246 /* Handle cases where the target is encoded within the
4247 instruction. */
4249 {
4252 }
4266 }
4267 }
4271 /* Stub size has already been computed in arm_size_one_stub. Check
4272 consistency. */
4275 /* Destination is Thumb. Force bit 0 to 1 to reflect this. */
4279 /* Assume there is at least one and at most MAXRELOCS entries to relocate
4280 in each stub. */
4288 {
4289 Elf_Internal_Rela rel;
4290 bfd_boolean unresolved_reloc;
4292 enum arm_st_branch_type branch_type
4303 /* The first relocation in the elf32_arm_stub_a8_veneer_b_cond[]
4304 template should refer back to the instruction after the original
4305 branch. */
4308 /* There may be unintended consequences if this is not true. */
4311 /* Note: _bfd_final_link_relocate doesn't handle these relocations
4312 properly. We should probably use this function unconditionally,
4313 rather than only for certain relocations listed in the enclosing
4314 conditional, for the sake of consistency. */
4321 }
4322 else
4323 {
4324 Elf_Internal_Rela rel;
4325 bfd_boolean unresolved_reloc;
4342 }
4345 #undef MAXRELOCS
4346 }
4348 /* Calculate the template, template size and instruction size for a stub.
4349 Return value is the instruction size. */
4351 static unsigned int
4355 {
4370 {
4372 {
4386 }
4387 }
4390 }
4392 /* As above, but don't actually build the stub. Just bump offset so
4393 we know stub section sizes. */
4395 static bfd_boolean
4398 {
4403 /* Massage our args to the form they really have. */
4420 }
4422 /* External entry points for sizing and building linker stubs. */
4424 /* Set up various things so that we can make a list of input sections
4425 for each output section included in the link. Returns -1 on error,
4426 0 when no stubs will be needed, and 1 on success. */
4428 int
4431 {
4437 bfd_size_type amt;
4445 /* Count the number of input BFDs and find the top input section id. */
4449 {
4454 {
4457 }
4458 }
4467 /* We can't use output_bfd->section_count here to find the top output
4468 section index as some sections may have been removed, and
4469 _bfd_strip_section_from_output doesn't renumber the indices. */
4473 {
4476 }
4485 /* For sections we aren't interested in, mark their entries with a
4486 value we can check later. */
4488 do
4495 {
4498 }
4501 }
4503 /* The linker repeatedly calls this function for each input section,
4504 in the order that input sections are linked into output sections.
4505 Build lists of input sections to determine groupings between which
4506 we may insert linker stubs. */
4508 void
4511 {
4518 {
4522 {
4523 /* Steal the link_sec pointer for our list. */
4524 #define PREV_SEC(sec) (htab->stub_group[(sec)->id].link_sec)
4525 /* This happens to make the list in reverse order,
4526 which we reverse later. */
4529 }
4530 }
4531 }
4533 /* See whether we can group stub sections together. Grouping stub
4534 sections may result in fewer stubs. More importantly, we need to
4535 put all .init* and .fini* stubs at the end of the .init or
4536 .fini output sections respectively, because glibc splits the
4537 _init and _fini functions into multiple parts. Putting a stub in
4538 the middle of a function is not a good idea. */
4540 static void
4542 bfd_size_type stub_group_size,
4543 bfd_boolean stubs_always_after_branch)
4544 {
4547 do
4548 {
4555 /* Reverse the list: we must avoid placing stubs at the
4556 beginning of the section because the beginning of the text
4557 section may be required for an interrupt vector in bare metal
4558 code. */
4559 #define NEXT_SEC PREV_SEC
4562 {
4563 /* Pop from tail. */
4567 /* Push on head. */
4570 }
4573 {
4577 bfd_vma end_of_next;
4581 {
4585 /* End of NEXT is too far from start, so stop. */
4587 /* Add NEXT to the group. */
4589 }
4591 /* OK, the size from the start to the start of CURR is less
4592 than stub_group_size and thus can be handled by one stub
4593 section. (Or the head section is itself larger than
4594 stub_group_size, in which case we may be toast.)
4595 We should really be keeping track of the total size of
4596 stubs added here, as stubs contribute to the final output
4597 section size. */
4598 do
4599 {
4601 /* Set up this stub group. */
4603 }
4606 /* But wait, there's more! Input sections up to stub_group_size
4607 bytes after the stub section can be handled by it too. */
4609 {
4613 {
4616 /* End of NEXT is too far from stubs, so stop. */
4618 /* Add NEXT to the stub group. */
4622 }
4623 }
4625 }
4626 }
4630 #undef PREV_SEC
4631 #undef NEXT_SEC
4632 }
4634 /* Comparison function for sorting/searching relocations relating to Cortex-A8
4635 erratum fix. */
4637 static int
4639 {
4647 else
4649 }
4654 /* Helper function to scan code for sequences which might trigger the Cortex-A8
4655 branch/TLB erratum. Fill in the table described by A8_FIXES_P,
4656 NUM_A8_FIXES_P, A8_FIX_TABLE_SIZE_P. Returns true if an error occurs, false
4657 otherwise. */
4659 static bfd_boolean
4669 {
4682 {
4686 bfd_vma base_vma;
4705 {
4716 /* Span is entirely within a single 4KB region: skip scanning. */
4721 /* Scan for 32-bit Thumb-2 branches which span two 4K regions, where:
4723 * The opcode is BLX.W, BL.W, B.W, Bcc.W
4724 * The branch target is in the same 4KB region as the
4725 first half of the branch.
4726 * The instruction before the branch is a 32-bit
4727 length non-branch instruction. */
4729 {
4738 {
4739 /* Load the rest of the insn (in manual-friendly order). */
4742 /* Encoding T4: B<c>.W. */
4744 /* Encoding T1: BL<c>.W. */
4746 /* Encoding T2: BLX<c>.W. */
4748 /* Encoding T3: B<c>.W (not permitted in IT block). */
4751 }
4756 && insn_32bit
4757 && is_32bit_branch
4758 && last_was_32bit
4760 {
4764 bfd_vma target;
4776 {
4780 /* We don't care about the error returned from this
4781 function, only if there is glue or not. */
4788 /* Keep a simpler condition, for the sake of clarity. */
4794 {
4798 else
4800 }
4801 }
4803 /* Check if we have an offending branch instruction. */
4806 /* We've already made a stub for this instruction, e.g.
4807 it's a long branch or a Thumb->ARM stub. Assume that
4808 stub will suffice to work around the A8 erratum (see
4809 setting of always_after_branch above). */
4810 ;
4812 {
4821 }
4823 {
4843 }
4846 {
4849 /* The original instruction is a BL, but the target is
4850 an ARM instruction. If we were not making a stub,
4851 the BL would have been converted to a BLX. Use the
4852 BLX stub instead in that case. */
4855 {
4859 }
4860 /* Conversely, if the original instruction was
4861 BLX but the target is Thumb mode, use the BL
4862 stub. */
4865 {
4869 }
4874 /* If we found a relocation, use the proper destination,
4875 not the offset in the (unrelocated) instruction.
4876 Note this is always done if we switched the stub type
4877 above. */
4879 offset =
4882 /* If the stub will use a Thumb-mode branch to a
4883 PLT target, redirect it to the preceding Thumb
4884 entry point. */
4890 /* The BLX stub is ARM-mode code. Adjust the offset to
4891 take the different PC value (+8 instead of +4) into
4892 account. */
4897 {
4901 {
4907 }
4910 {
4911 /* If we're doing a subsequent scan,
4912 check if we've found the same fix as
4913 before, and try and reuse the stub
4914 name. */
4918 {
4922 }
4923 }
4926 {
4930 }
4942 num_a8_fixes++;
4943 }
4944 }
4945 }
4950 }
4951 }
4955 }
4962 }
4964 /* Determine and set the size of the stub section for a final link.
4966 The basic idea here is to examine all the relocations looking for
4967 PC-relative calls to a target that is unreachable with a "bl"
4968 instruction. */
4970 bfd_boolean
4974 bfd_signed_vma group_size,
4978 {
4979 bfd_size_type stub_group_size;
4980 bfd_boolean stubs_always_after_branch;
4991 {
4996 }
4998 /* Propagate mach to stub bfd, because it may not have been
4999 finalized when we created stub_bfd. */
5003 /* Stash our params away. */
5009 /* The Cortex-A8 erratum fix depends on stubs not being in the same 4K page
5010 as the first half of a 32-bit branch straddling two 4K pages. This is a
5011 crude way of enforcing that. */
5017 else
5021 {
5022 /* Default values. */
5023 /* Thumb branch range is +-4MB has to be used as the default
5024 maximum size (a given section can contain both ARM and Thumb
5025 code, so the worst case has to be taken into account).
5027 This value is 24K less than that, which allows for 2025
5028 12-byte stubs. If we exceed that, then we will fail to link.
5029 The user will have to relink with an explicit group size
5030 option. */
5032 }
5036 /* If we're applying the cortex A8 fix, we need to determine the
5037 program header size now, because we cannot change it later --
5038 that could alter section placements. Notice the A8 erratum fix
5039 ends up requiring the section addresses to remain unchanged
5040 modulo the page size. That's something we cannot represent
5041 inside BFD, and we don't want to force the section alignment to
5042 be the page size. */
5047 {
5058 {
5068 /* We'll need the symbol table in a second. */
5073 /* Walk over each section attached to the input bfd. */
5077 {
5080 /* If there aren't any relocs, then there's nothing more
5081 to do. */
5087 /* If this section is a link-once section that will be
5088 discarded, then don't create any stubs. */
5093 /* Get the relocs. */
5094 internal_relocs
5100 /* Now examine each relocation. */
5104 {
5109 bfd_vma sym_value;
5110 bfd_vma destination;
5123 {
5125 error_ret_free_internal:
5129 }
5133 hash = elf32_arm_hash_entry
5137 /* Only look for stubs on branch instructions, or
5138 non-relaxed TLSCALL */
5151 : (elf32_arm_local_got_tls_type
5156 /* Now determine the call target, its name, value,
5157 section. */
5165 {
5166 /* A non-relaxed TLS call. The target is the
5167 plt-resident trampoline and nothing to do
5168 with the symbol. */
5175 }
5177 {
5178 /* It's a local symbol. */
5182 {
5183 local_syms
5186 local_syms
5192 }
5201 else
5202 sym_sec =
5206 /* This is an undefined symbol. It can never
5207 be resolved. */
5217 sym_name
5221 }
5222 else
5223 {
5224 /* It's an external symbol. */
5232 {
5239 /* For a destination in a shared library,
5240 use the PLT stub as target address to
5241 decide whether a branch stub is
5242 needed. */
5247 {
5251 destination = (sym_value
5254 }
5259 }
5262 {
5263 /* For a shared library, use the PLT stub as
5264 target address to decide whether a long
5265 branch stub is needed.
5266 For absolute code, they cannot be handled. */
5274 {
5278 destination = (sym_value
5281 }
5282 else
5284 }
5285 else
5286 {
5289 }
5293 }
5295 do
5296 {
5297 /* Determine what (if any) linker stub is needed. */
5305 /* Support for grouping stub sections. */
5308 /* Get the name of this stub. */
5314 /* We've either created a stub for this reloc already,
5315 or we are about to. */
5318 stub_entry = arm_stub_hash_lookup
5322 {
5323 /* The proper stub has already been created. */
5327 }
5330 htab);
5332 {
5335 }
5350 {
5353 }
5355 /* For historical reasons, use the existing names for
5356 ARM-to-Thumb and Thumb-to-ARM stubs. */
5368 else
5370 sym_name);
5373 }
5376 /* Look for relocations which might trigger Cortex-A8
5377 erratum. */
5383 {
5389 {
5390 /* Found a candidate. Note we haven't checked the
5391 destination is within 4K here: if we do so (and
5392 don't create an entry in a8_relocs) we can't tell
5393 that a branch should have been relocated when
5394 scanning later. */
5396 {
5402 }
5412 num_a8_relocs++;
5413 }
5414 }
5415 }
5417 /* We're done with the internal relocs, free them. */
5420 }
5423 {
5424 /* Sort relocs which might apply to Cortex-A8 erratum. */
5429 /* Scan for branches which might trigger Cortex-A8 erratum. */
5436 }
5437 }
5445 /* OK, we've added some stubs. Find out the new size of the
5446 stub sections. */
5450 {
5451 /* Ignore non-stub sections. */
5456 }
5460 /* Add Cortex-A8 erratum veneers to stub section sizes too. */
5463 {
5470 stub_sec->size
5472 NULL);
5473 }
5476 /* Ask the linker to do its stuff. */
5478 }
5480 /* Add stubs for Cortex-A8 erratum fixes now. */
5482 {
5484 {
5497 {
5500 stub_name);
5502 }
5521 }
5523 /* Stash the Cortex-A8 erratum fix array for use later in
5524 elf32_arm_write_section(). */
5527 }
5528 else
5529 {
5532 }
5535 error_ret_free_local:
5537 }
5539 /* Build all the stubs associated with the current output file. The
5540 stubs are kept in a hash table attached to the main linker hash
5541 table. We also set up the .plt entries for statically linked PIC
5542 functions here. This function is called via arm_elf_finish in the
5543 linker. */
5545 bfd_boolean
5547 {
5559 {
5560 bfd_size_type size;
5562 /* Ignore non-stub sections. */
5566 /* Allocate memory to hold the linker stubs. */
5572 }
5574 /* Build the stubs as directed by the stub hash table. */
5578 {
5579 /* Place the cortex a8 stubs last. */
5582 }
5585 }
5587 /* Locate the Thumb encoded calling stub for NAME. */
5593 {
5598 /* We need a pointer to the armelf specific hash table. */
5610 hash = elf_link_hash_lookup
5621 }
5623 /* Locate the ARM encoded calling stub for NAME. */
5629 {
5634 /* We need a pointer to the elfarm specific hash table. */
5646 myh = elf_link_hash_lookup
5657 }
5659 /* ARM->Thumb glue (static images):
5661 .arm
5662 __func_from_arm:
5663 ldr r12, __func_addr
5664 bx r12
5665 __func_addr:
5666 .word func @ behave as if you saw a ARM_32 reloc.
5668 (v5t static images)
5669 .arm
5670 __func_from_arm:
5671 ldr pc, __func_addr
5672 __func_addr:
5673 .word func @ behave as if you saw a ARM_32 reloc.
5675 (relocatable images)
5676 .arm
5677 __func_from_arm:
5678 ldr r12, __func_offset
5679 add r12, r12, pc
5680 bx r12
5681 __func_offset:
5682 .word func - . */
5684 #define ARM2THUMB_STATIC_GLUE_SIZE 12
5689 #define ARM2THUMB_V5_STATIC_GLUE_SIZE 8
5693 #define ARM2THUMB_PIC_GLUE_SIZE 16
5698 /* Thumb->ARM: Thumb->(non-interworking aware) ARM
5700 .thumb .thumb
5701 .align 2 .align 2
5702 __func_from_thumb: __func_from_thumb:
5703 bx pc push {r6, lr}
5704 nop ldr r6, __func_addr
5705 .arm mov lr, pc
5706 b func bx r6
5707 .arm
5708 ;; back_to_thumb
5709 ldmia r13! {r6, lr}
5710 bx lr
5711 __func_addr:
5712 .word func */
5714 #define THUMB2ARM_GLUE_SIZE 8
5719 #define VFP11_ERRATUM_VENEER_SIZE 8
5721 #define ARM_BX_VENEER_SIZE 12
5726 #ifndef ELFARM_NABI_C_INCLUDED
5727 static void
5729 {
5734 {
5735 /* Do not include empty glue sections in the output. */
5737 {
5741 }
5743 }
5754 }
5756 bfd_boolean
5758 {
5766 ARM2THUMB_GLUE_SECTION_NAME);
5770 THUMB2ARM_GLUE_SECTION_NAME);
5774 VFP11_ERRATUM_VENEER_SECTION_NAME);
5778 ARM_BX_GLUE_SECTION_NAME);
5781 }
5783 /* Allocate space and symbols for calling a Thumb function from Arm mode.
5784 returns the symbol identifying the stub. */
5789 {
5796 bfd_vma val;
5797 bfd_size_type size;
5803 s = bfd_get_linker_section
5815 myh = elf_link_hash_lookup
5819 {
5820 /* We've already seen this guy. */
5823 }
5825 /* The only trick here is using hash_table->arm_glue_size as the value.
5826 Even though the section isn't allocated yet, this is where we will be
5827 putting it. The +1 on the value marks that the stub has not been
5828 output yet - not that it is a Thumb function. */
5846 else
5853 }
5855 /* Allocate space for ARMv4 BX veneers. */
5857 static void
5859 {
5865 bfd_vma val;
5867 /* BX PC does not need a veneer. */
5875 /* Check if this veneer has already been allocated. */
5879 s = bfd_get_linker_section
5884 /* Add symbol for veneer. */
5892 myh = elf_link_hash_lookup
5910 }
5913 /* Add an entry to the code/data map for section SEC. */
5915 static void
5917 {
5922 {
5927 }
5932 {
5937 }
5940 {
5943 }
5944 }
5947 /* Record information about a VFP11 denorm-erratum veneer. Only ARM-mode
5948 veneers are handled for now. */
5950 static bfd_vma
5956 {
5962 bfd_vma val;
5970 s = bfd_get_linker_section
5985 myh = elf_link_hash_lookup
6000 /* Link veneer back to calling location. */
6014 /* A symbol for the return from the veneer. */
6018 myh = elf_link_hash_lookup
6035 /* Generate a mapping symbol for the veneer section, and explicitly add an
6036 entry for that symbol to the code/data map for the section. */
6038 {
6040 /* FIXME: Creates an ARM symbol. Thumb mode will need attention if it
6041 ever requires this erratum fix. */
6051 /* The elf32_arm_init_maps function only cares about symbols from input
6052 BFDs. We must make a note of this generated mapping symbol
6053 ourselves so that code byteswapping works properly in
6054 elf32_arm_write_section. */
6056 }
6062 /* The offset of the veneer. */
6064 }
6066 #define ARM_GLUE_SECTION_FLAGS \
6067 (SEC_ALLOC | SEC_LOAD | SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_CODE \
6068 | SEC_READONLY | SEC_LINKER_CREATED)
6070 /* Create a fake section for use by the ARM backend of the linker. */
6072 static bfd_boolean
6074 {
6079 /* Already made. */
6088 /* Set the gc mark to prevent the section from being removed by garbage
6089 collection, despite the fact that no relocs refer to this section. */
6093 }
6095 /* Set size of .plt entries. This function is called from the
6096 linker scripts in ld/emultempl/{armelf}.em. */
6098 void
6100 {
6102 }
6104 /* Add the glue sections to ABFD. This function is called from the
6105 linker scripts in ld/emultempl/{armelf}.em. */
6107 bfd_boolean
6110 {
6111 /* If we are only performing a partial
6112 link do not bother adding the glue. */
6120 }
6122 /* Select a BFD to be used to hold the sections used by the glue code.
6123 This function is called from the linker scripts in ld/emultempl/
6124 {armelf/pe}.em. */
6126 bfd_boolean
6128 {
6131 /* If we are only performing a partial link
6132 do not bother getting a bfd to hold the glue. */
6136 /* Make sure we don't attach the glue sections to a dynamic object. */
6145 /* Save the bfd for later use. */
6149 }
6151 static void
6153 {
6157 Tag_CPU_arch);
6160 {
6163 }
6164 else
6165 {
6168 }
6169 }
6171 bfd_boolean
6174 {
6183 /* If we are only performing a partial link do not bother
6184 to construct any glue. */
6188 /* Here we have a bfd that is to be included on the link. We have a
6189 hook to do reloc rummaging, before section sizes are nailed down. */
6196 {
6198 abfd);
6200 }
6202 /* PR 5398: If we have not decided to include any loadable sections in
6203 the output then we will not have a glue owner bfd. This is OK, it
6204 just means that there is nothing else for us to do here. */
6208 /* Rummage around all the relocs and map the glue vectors. */
6215 {
6224 /* Load the relocs. */
6225 internal_relocs
6233 {
6242 /* These are the only relocation types we care about. */
6247 /* Get the section contents if we haven't done so already. */
6249 {
6250 /* Get cached copy if it exists. */
6253 else
6254 {
6255 /* Go get them off disk. */
6258 }
6259 }
6262 {
6268 }
6270 /* If the relocation is not against a symbol it cannot concern us. */
6273 /* We don't care about local symbols. */
6277 /* This is an external symbol. */
6282 /* If the relocation is against a static symbol it must be within
6283 the current section and so cannot be a cross ARM/Thumb relocation. */
6287 /* If the call will go through a PLT entry then we do not need
6288 glue. */
6293 {
6295 /* This one is a call from arm code. We need to look up
6296 the target of the call. If it is a thumb target, we
6297 insert glue. */
6304 }
6305 }
6316 }
6320 error_return:
6329 }
6330 #endif
6333 /* Initialise maps of ARM/Thumb/data for input BFDs. */
6335 void
6337 {
6342 /* PR 7093: Make sure that we are dealing with an arm elf binary. */
6352 /* Obtain a buffer full of symbols for this BFD. The hdr->sh_info field
6353 should contain the number of local symbols, which should come before any
6354 global symbols. Mapping symbols are always local. */
6356 NULL);
6358 /* No internal symbols read? Skip this BFD. */
6363 {
6370 {
6375 BFD_ARM_SPECIAL_SYM_TYPE_MAP))
6377 }
6378 }
6379 }
6382 /* Auto-select enabling of Cortex-A8 erratum fix if the user didn't explicitly
6383 say what they wanted. */
6385 void
6387 {
6395 {
6396 /* Turn on Cortex-A8 erratum workaround for ARMv7-A. */
6401 else
6403 }
6404 }
6407 void
6409 {
6415 /* We assume that ARMv7+ does not need the VFP11 denorm erratum fix. */
6417 {
6419 {
6426 /* Give a warning, but do as the user requests anyway. */
6429 }
6430 }
6432 /* For earlier architectures, we might need the workaround, but do not
6433 enable it by default. If users is running with broken hardware, they
6434 must enable the erratum fix explicitly. */
6436 }
6439 enum bfd_arm_vfp11_pipe
6440 {
6441 VFP11_FMAC,
6442 VFP11_LS,
6443 VFP11_DS,
6444 VFP11_BAD
6445 };
6447 /* Return a VFP register number. This is encoded as RX:X for single-precision
6448 registers, or X:RX for double-precision registers, where RX is the group of
6449 four bits in the instruction encoding and X is the single extension bit.
6450 RX and X fields are specified using their lowest (starting) bit. The return
6451 value is:
6453 0...31: single-precision registers s0...s31
6454 32...63: double-precision registers d0...d31.
6456 Although X should be zero for VFP11 (encoding d0...d15 only), we might
6457 encounter VFP3 instructions, so we allow the full range for DP registers. */
6459 static unsigned int
6462 {
6465 else
6467 }
6469 /* Set bits in *WMASK according to a register number REG as encoded by
6470 bfd_arm_vfp11_regno(). Ignore d16-d31. */
6472 static void
6474 {
6479 }
6481 /* Return TRUE if WMASK overwrites anything in REGS. */
6483 static bfd_boolean
6485 {
6489 {
6502 }
6505 }
6507 /* In this function, we're interested in two things: finding input registers
6508 for VFP data-processing instructions, and finding the set of registers which
6509 arbitrary VFP instructions may write to. We use a 32-bit unsigned int to
6510 hold the written set, so FLDM etc. are easy to deal with (we're only
6511 interested in 32 SP registers or 16 dp registers, due to the VFP version
6512 implemented by the chip in question). DP registers are marked by setting
6513 both SP registers in the write mask). */
6515 static enum bfd_arm_vfp11_pipe
6518 {
6523 {
6533 {
6555 vfp_binop:
6563 {
6568 {
6582 /* These instructions will not bounce due to underflow. */
6588 /* fsqrt cannot underflow, but it can (perhaps) overwrite
6589 registers to cause the erratum in previous instructions. */
6595 {
6600 /* Only FCVTSD can underflow. */
6607 }
6612 }
6613 }
6618 }
6619 }
6620 /* Two-register transfer. */
6622 {
6626 {
6629 else
6630 {
6633 }
6634 }
6637 }
6639 {
6644 {
6651 {
6659 }
6669 }
6672 }
6673 /* Single-register transfer. Note L==0. */
6675 {
6680 {
6683 /* Mark fmdhr and fmdlr as writing to the whole of the DP
6684 destination register. I don't know if this is exactly right,
6685 but it is the conservative choice. */
6691 }
6694 }
6697 }
6703 /* Look for potentially-troublesome code sequences which might trigger the
6704 VFP11 denormal/antidependency erratum. See, e.g., the ARM1136 errata sheet
6705 (available from ARM) for details of the erratum. A short version is
6706 described in ld.texinfo. */
6708 bfd_boolean
6710 {
6721 /* We use a simple FSM to match troublesome VFP11 instruction sequences.
6722 The states transition as follows:
6724 0 -> 1 (vector) or 0 -> 2 (scalar)
6725 A VFP FMAC-pipeline instruction has been seen. Fill
6726 regs[0]..regs[numregs-1] with its input operands. Remember this
6727 instruction in 'first_fmac'.
6729 1 -> 2
6730 Any instruction, except for a VFP instruction which overwrites
6731 regs[*].
6733 1 -> 3 [ -> 0 ] or
6734 2 -> 3 [ -> 0 ]
6735 A VFP instruction has been seen which overwrites any of regs[*].
6736 We must make a veneer! Reset state to 0 before examining next
6737 instruction.
6739 2 -> 0
6740 If we fail to match anything in state 2, reset to state 0 and reset
6741 the instruction pointer to the instruction after 'first_fmac'.
6743 If the VFP11 vector mode is in use, there must be at least two unrelated
6744 instructions between anti-dependent VFP11 instructions to properly avoid
6745 triggering the erratum, hence the use of the extra state 1. */
6747 /* If we are only performing a partial link do not bother
6748 to construct any glue. */
6752 /* Skip if this bfd does not correspond to an ELF image. */
6756 /* We should have chosen a fix type by the time we get here. */
6762 /* Skip this BFD if it corresponds to an executable or dynamic object. */
6767 {
6771 /* If we don't have executable progbits, we're not interested in this
6772 section. Also skip if section is to be excluded. */
6792 elf32_arm_compare_mapping);
6795 {
6801 /* FIXME: Only ARM mode is supported at present. We may need to
6802 support Thumb-2 mode also at some point. */
6807 {
6822 {
6826 /* I'm assuming the VFP11 erratum can trigger with denorm
6827 operands on either the FMAC or the DS pipeline. This might
6828 lead to slightly overenthusiastic veneer insertion. */
6830 {
6834 }
6838 {
6841 other_regs,
6845 numregs))
6847 else
6849 }
6853 {
6856 other_regs,
6860 numregs))
6862 else
6863 {
6866 }
6867 }
6872 }
6875 {
6884 {
6891 }
6894 first_fmac);
6902 }
6905 }
6906 }
6912 }
6916 error_return:
6922 }
6924 /* Find virtual-memory addresses for VFP11 erratum veneers and return locations
6925 after sections have been laid out, using specially-named symbols. */
6927 void
6930 {
6938 /* Skip if this bfd does not correspond to an ELF image. */
6950 {
6955 {
6957 bfd_vma vma;
6960 {
6963 /* Find veneer symbol. */
6967 myh = elf_link_hash_lookup
6983 /* Find return location. */
6987 myh = elf_link_hash_lookup
7003 }
7004 }
7005 }
7008 }
7011 /* Set target relocation values needed during linking. */
7013 void
7020 bfd_arm_vfp11_fix vfp11_fix,
7024 {
7038 else
7039 {
7041 target2_type);
7042 }
7053 }
7055 /* Replace the target offset of a Thumb bl or b.w instruction. */
7057 static void
7059 {
7060 bfd_vma upper;
7061 bfd_vma lower;
7078 }
7080 /* Thumb code calling an ARM function. */
7082 static int
7090 bfd_vma offset,
7091 bfd_signed_vma addend,
7092 bfd_vma val,
7094 {
7096 bfd_vma my_offset;
7112 THUMB2ARM_GLUE_SECTION_NAME);
7119 {
7123 {
7130 }
7141 ret_offset =
7142 /* Address of destination of the stub. */
7145 /* Offset from the start of the current section
7146 to the start of the stubs. */
7148 /* Offset of the start of this stub from the start of the stubs. */
7149 + my_offset
7150 /* Address of the start of the current section. */
7152 /* The branch instruction is 4 bytes into the stub. */
7154 /* ARM branches work from the pc of the instruction + 8. */
7160 }
7164 /* Now go back and fix up the original BL insn to point to here. */
7165 ret_offset =
7166 /* Address of where the stub is located. */
7168 /* Address of where the BL is located. */
7171 /* Addend in the relocation. */
7172 - addend
7173 /* Biassing for PC-relative addressing. */
7179 }
7181 /* Populate an Arm to Thumb stub. Returns the stub symbol. */
7189 bfd_vma val,
7192 {
7193 bfd_vma my_offset;
7209 {
7213 {
7218 }
7225 {
7226 /* For relocatable objects we can't use absolute addresses,
7227 so construct the address from a relative offset. */
7228 /* TODO: If the offset is small it's probably worth
7229 constructing the address with adds. */
7236 /* Adjust the offset by 4 for the position of the add,
7237 and 8 for the pipeline offset. */
7244 }
7246 {
7250 /* It's a thumb address. Add the low order bit. */
7253 }
7254 else
7255 {
7262 /* It's a thumb address. Add the low order bit. */
7267 }
7268 }
7273 }
7275 /* Arm code calling a Thumb function. */
7277 static int
7285 bfd_vma offset,
7286 bfd_signed_vma addend,
7287 bfd_vma val,
7289 {
7291 bfd_vma my_offset;
7302 ARM2THUMB_GLUE_SECTION_NAME);
7316 /* Somehow these are both 4 too far, so subtract 8. */
7318 + my_offset
7330 }
7332 /* Populate Arm stub for an exported Thumb function. */
7334 static bfd_boolean
7336 {
7343 bfd_vma val;
7347 /* Allocate stubs for exported Thumb functions on v4t. */
7356 ARM2THUMB_GLUE_SECTION_NAME);
7374 }
7376 /* Populate ARMv4 BX veneers. Returns the absolute adress of the veneer. */
7378 static bfd_vma
7380 {
7382 bfd_vma glue_addr;
7391 ARM_BX_GLUE_SECTION_NAME);
7401 {
7407 }
7410 }
7412 /* Generate Arm stubs for exported Thumb symbols. */
7413 static void
7416 {
7420 /* Ignore this if we are not called by the ELF backend linker. */
7427 /* If blx is available then exported Thumb symbols are OK and there is
7428 nothing to do. */
7433 link_info);
7434 }
7436 /* Reserve space for COUNT dynamic relocations in relocation selection
7437 SRELOC. */
7439 static void
7441 bfd_size_type count)
7442 {
7450 }
7452 /* Reserve space for COUNT R_ARM_IRELATIVE relocations. If the link is
7453 dynamic, the relocations should go in SRELOC, otherwise they should
7454 go in the special .rel.iplt section. */
7456 static void
7458 bfd_size_type count)
7459 {
7465 else
7466 {
7469 }
7470 }
7472 /* Add relocation REL to the end of relocation section SRELOC. */
7474 static void
7477 {
7492 }
7494 /* Allocate room for a PLT entry described by ROOT_PLT and ARM_PLT.
7495 IS_IPLT_ENTRY says whether the entry belongs to .iplt rather than
7496 to .plt. */
7498 static void
7500 bfd_boolean is_iplt_entry,
7503 {
7511 {
7515 /* NaCl uses a special first entry in .iplt too. */
7519 /* Allocate room for an R_ARM_IRELATIVE relocation in .rel.iplt. */
7521 }
7522 else
7523 {
7527 /* Allocate room for an R_JUMP_SLOT relocation in .rel.plt. */
7530 /* If this is the first .plt entry, make room for the special
7531 first entry. */
7536 }
7538 /* Allocate the PLT entry itself, including any leading Thumb stub. */
7545 {
7546 /* We also need to make an entry in the .got.plt section, which
7547 will be placed in the .got section by the linker script. */
7550 else
7553 }
7554 }
7556 static bfd_vma
7558 {
7560 }
7562 static bfd_vma
7564 {
7566 }
7568 /* Fill in a PLT entry and its associated GOT slot. If DYNINDX == -1,
7569 the entry lives in .iplt and resolves to (*SYM_VALUE)().
7570 Otherwise, DYNINDX is the index of the symbol in the dynamic
7571 symbol table and SYM_VALUE is undefined.
7573 ROOT_PLT points to the offset of the PLT entry from the start of its
7574 section (.iplt or .plt). ARM_PLT points to the symbol's ARM-specific
7575 bookkeeping information.
7577 Returns FALSE if there was a problem. */
7579 static bfd_boolean
7584 {
7590 bfd_vma plt_index;
7591 Elf_Internal_Rela rel;
7592 bfd_vma plt_header_size;
7593 bfd_vma got_header_size;
7597 /* Pick the appropriate sections and sizes. */
7599 {
7604 /* There are no reserved entries in .igot.plt, and no special
7605 first entry in .iplt. */
7608 }
7609 else
7610 {
7617 }
7620 /* Fill in the entry in the procedure linkage table. */
7622 {
7631 /* Fill in the entry in the .rel.plt section. */
7637 /* Get the index in the procedure linkage table which
7638 corresponds to this symbol. This is the index of this symbol
7639 in all the symbols for which we are making plt entries. The
7640 first entry in the procedure linkage table is reserved. */
7643 }
7644 else
7645 {
7652 /* Get the offset into the .(i)got.plt table of the entry that
7653 corresponds to this function. */
7656 /* Get the index in the procedure linkage table which
7657 corresponds to this symbol. This is the index of this symbol
7658 in all the symbols for which we are making plt entries.
7659 After the reserved .got.plt entries, all symbols appear in
7660 the same order as in .plt. */
7663 /* Calculate the address of the GOT entry. */
7668 /* ...and the address of the PLT entry. */
7675 {
7677 bfd_vma val;
7680 {
7688 else
7690 }
7691 }
7693 {
7695 bfd_vma val;
7698 {
7708 else
7710 }
7715 /* Create the .rela.plt.unloaded R_ARM_ABS32 relocation
7716 referencing the GOT for this PLT entry. */
7723 /* Create the R_ARM_ABS32 relocation referencing the
7724 beginning of the PLT for this GOT entry. */
7729 }
7731 {
7732 /* Calculate the displacement between the PLT slot and the
7733 common tail that's part of the special initial PLT slot. */
7734 int32_t tail_displacement
7744 /* Calculate the displacement between the PLT slot and the entry
7745 in the GOT. The offset accounts for the value produced by
7746 adding to pc in the penultimate instruction of the PLT stub. */
7747 got_displacement = (got_address
7750 /* NaCl does not support interworking at all. */
7768 }
7770 {
7771 /* PR ld/16017: Generate thumb only PLT entries. */
7773 {
7774 /* FIXME: We ought to be able to generate thumb-1 PLT
7775 instructions... */
7777 output_bfd);
7779 }
7781 /* Calculate the displacement between the PLT slot and the entry in
7782 the GOT. The 12-byte offset accounts for the value produced by
7783 adding to pc in the 3rd instruction of the PLT stub. */
7786 /* As we are using 32 bit instructions we have to use 'put_arm_insn'
7787 instead of 'put_thumb_insn'. */
7808 }
7809 else
7810 {
7811 /* Calculate the displacement between the PLT slot and the
7812 entry in the GOT. The eight-byte offset accounts for the
7813 value produced by adding to pc in the first instruction
7814 of the PLT stub. */
7818 {
7823 }
7826 {
7841 #ifdef FOUR_WORD_PLT
7843 #endif
7844 }
7845 else
7846 {
7863 }
7864 }
7866 /* Fill in the entry in the .rel(a).(i)plt section. */
7870 {
7871 /* .igot.plt entries use IRELATIVE relocations against SYM_VALUE.
7872 The dynamic linker or static executable then calls SYM_VALUE
7873 to determine the correct run-time value of the .igot.plt entry. */
7876 }
7877 else
7878 {
7882 }
7884 /* Fill in the entry in the global offset table. */
7887 }
7891 else
7892 {
7895 }
7898 }
7900 /* Some relocations map to different relocations depending on the
7901 target. Return the real relocation. */
7903 static int
7906 {
7908 {
7912 else
7920 }
7921 }
7923 /* Return the base VMA address which should be subtracted from real addresses
7924 when resolving @dtpoff relocation.
7925 This is PT_TLS segment p_vaddr. */
7927 static bfd_vma
7929 {
7930 /* If tls_sec is NULL, we should have signalled an error already. */
7934 }
7936 /* Return the relocation value for @tpoff relocation
7937 if STT_TLS virtual address is ADDRESS. */
7939 static bfd_vma
7941 {
7943 bfd_vma base;
7945 /* If tls_sec is NULL, we should have signalled an error already. */
7950 }
7952 /* Perform an R_ARM_ABS12 relocation on the field pointed to by DATA.
7953 VALUE is the relocation value. */
7955 static bfd_reloc_status_type
7957 {
7964 }
7966 /* Handle TLS relaxations. Relaxing is possible for symbols that use
7967 R_ARM_GOTDESC, R_ARM_{,THM_}TLS_CALL or
7968 R_ARM_{,THM_}TLS_DESCSEQ relocations, during a static link.
7970 Return bfd_reloc_ok if we're done, bfd_reloc_continue if the caller
7971 is to then call final_link_relocate. Return other values in the
7972 case of error.
7974 FIXME:When --emit-relocs is in effect, we'll emit relocs describing
7975 the pre-relaxed code. It would be nice if the relocs were updated
7976 to match the optimization. */
7978 static bfd_reloc_status_type
7982 {
7986 {
7993 else
7994 {
7998 else
8000 }
8005 /* Thumb insn. */
8008 {
8010 /* nop */
8012 }
8014 {
8016 /* nop */
8018 else
8019 /* ldr rx,[ry] */
8021 }
8023 {
8025 /* nop */
8027 else
8028 /* mov r0, rx */
8031 }
8032 else
8033 {
8035 /* It's a 32 bit instruction, fetch the rest of it for
8036 error generation. */
8043 }
8047 /* arm insn. */
8050 {
8052 /* mov rx, ry */
8055 }
8057 {
8059 /* nop */
8061 else
8062 /* ldr rx,[ry] */
8065 }
8067 {
8069 /* nop */
8071 else
8072 /* mov r0, rx */
8075 }
8076 else
8077 {
8082 }
8086 /* GD->IE relaxation, turn the instruction into 'nop' or
8087 'ldr r0, [pc,r0]' */
8093 /* GD->IE relaxation. */
8095 /* add r0,pc; ldr r0, [r0] */
8098 /* nop.w */
8100 else
8101 /* nop; nop */
8107 }
8109 }
8111 /* For a given value of n, calculate the value of G_n as required to
8112 deal with group relocations. We return it in the form of an
8113 encoded constant-and-rotation, together with the final residual. If n is
8114 specified as less than zero, then final_residual is filled with the
8115 input value and no further action is performed. */
8117 static bfd_vma
8119 {
8121 bfd_vma g_n;
8126 {
8129 /* Calculate which part of the value to mask. */
8132 else
8133 {
8136 /* Determine the most significant bit in the residual and
8137 align the resulting value to a 2-bit boundary. */
8142 /* The desired shift is now (msb - 6), or zero, whichever
8143 is the greater. */
8147 }
8149 /* Calculate g_n in 32-bit as well as encoded constant+rotation form. */
8154 /* Calculate the residual for the next time around. */
8156 }
8161 }
8163 /* Given an ARM instruction, determine whether it is an ADD or a SUB.
8164 Returns 1 if it is an ADD, -1 if it is a SUB, and 0 otherwise. */
8166 static int
8168 {
8178 }
8180 /* Perform a relocation as part of a final link. */
8182 static bfd_reloc_status_type
8189 bfd_vma value,
8198 {
8208 bfd_vma addend;
8209 bfd_signed_vma signed_addend;
8211 bfd_vma dynreloc_value;
8216 bfd_vma plt_offset;
8217 bfd_vma gotplt_offset;
8218 bfd_boolean has_iplt_entry;
8226 /* Some relocation types map to different relocations depending on the
8227 target. We pick the right one here. */
8230 /* It is possible to have linker relaxations on some TLS access
8231 models. Update our information here. */
8237 /* If the start address has been set, then set the EF_ARM_HASENTRY
8238 flag. Setting this more than once is redundant, but the cost is
8239 not too high, and it keeps the code simple.
8241 The test is done here, rather than somewhere else, because the
8242 start address is only set just before the final link commences.
8244 Note - if the user deliberately sets a start address of 0, the
8245 flag will not be set. */
8256 else
8262 {
8266 {
8270 }
8271 else
8273 }
8274 else
8277 /* ST_BRANCH_TO_ARM is nonsense to thumb-only targets when we
8278 are resolving a function call relocation. */
8285 /* Record the symbol information that should be used in dynamic
8286 relocations. */
8292 /* Find out whether the symbol has a PLT. Set ST_VALUE, BRANCH_TYPE and
8293 VALUE appropriately for relocations that we resolve at link time. */
8297 {
8302 {
8306 /* Populate .iplt entries here, because not all of them will
8307 be seen by finish_dynamic_symbol. The lower bit is set if
8308 we have already populated the entry. */
8310 plt_offset--;
8311 else
8312 {
8316 else
8318 }
8320 /* Static relocations always resolve to the .iplt entry. */
8327 /* If there are non-call relocations that resolve to the .iplt
8328 entry, then all dynamic ones must too. */
8330 {
8333 }
8334 }
8335 else
8336 /* We populate the .plt entry in finish_dynamic_symbol. */
8338 }
8339 else
8340 {
8344 }
8347 {
8349 /* We don't need to find a value for this symbol. It's just a
8350 marker. */
8368 /* Handle relocations which should use the PLT entry. ABS32/REL32
8369 will use the symbol's value, which may point to a PLT entry, but we
8370 don't need to handle that here. If we created a PLT entry, all
8371 branches in this object should go to it, except if the PLT is too
8372 far away, in which case a long branch stub should be inserted. */
8379 {
8380 /* If we've created a .plt section, and assigned a PLT entry
8381 to this function, it must either be a STT_GNU_IFUNC reference
8382 or not be known to bind locally. In other cases, we should
8383 have cleared the PLT entry by now. */
8393 }
8395 /* When generating a shared object or relocatable executable, these
8396 relocations are copied into the output file to be resolved at
8397 run time. */
8415 {
8416 Elf_Internal_Rela outrel;
8422 {
8428 }
8452 else
8453 {
8456 /* This symbol is local, or marked to become local. */
8459 {
8462 /* On Symbian OS, the data segment and text segement
8463 can be relocated independently. Therefore, we
8464 must indicate the segment to which this
8465 relocation is relative. The BPABI allows us to
8466 use any symbol in the right segment; we just use
8467 the section symbol as it is convenient. (We
8468 cannot use the symbol given by "h" directly as it
8469 will not appear in the dynamic symbol table.)
8471 Note that the dynamic linker ignores the section
8472 symbol value, so we don't subtract osec->vma
8473 from the emitted reloc addend. */
8476 else
8480 {
8486 else
8489 }
8491 }
8492 else
8493 /* On SVR4-ish systems, the dynamic loader cannot
8494 relocate the text and data segments independently,
8495 so the symbol does not matter. */
8498 /* We have an STT_GNU_IFUNC symbol that doesn't resolve
8499 to the .iplt entry. Instead, every non-call reference
8500 must use an R_ARM_IRELATIVE relocation to obtain the
8501 correct run-time address. */
8503 else
8507 else
8509 }
8513 /* If this reloc is against an external symbol, we do not want to
8514 fiddle with the addend. Otherwise, we need to include the symbol
8515 value so that it becomes an addend for the dynamic reloc. */
8522 }
8524 {
8533 {
8537 {
8538 /* Check for Arm calling Arm function. */
8539 /* FIXME: Should we translate the instruction into a BL
8540 instruction instead ? */
8544 input_bfd,
8546 }
8548 {
8549 /* Check for Arm calling Thumb function. */
8551 {
8556 error_message))
8558 else
8560 }
8561 }
8563 /* Check if a stub has to be inserted because the
8564 destination is too far or we are changing mode. */
8568 {
8579 {
8580 /* The target is out of reach, so redirect the
8581 branch to the local stub for this function. */
8585 stub_type);
8586 {
8594 }
8595 }
8596 else
8597 {
8598 /* If the call goes through a PLT entry, make sure to
8599 check distance to the right destination address. */
8601 {
8606 /* The PLT entry is in ARM mode, regardless of the
8607 target function. */
8609 }
8610 }
8611 }
8613 /* The ARM ELF ABI says that this reloc is computed as: S - P + A
8614 where:
8615 S is the address of the symbol in the relocation.
8616 P is address of the instruction being relocated.
8617 A is the addend (extracted from the instruction) in bytes.
8619 S is held in 'value'.
8620 P is the base address of the section containing the
8621 instruction plus the offset of the reloc into that
8622 section, ie:
8623 (input_section->output_section->vma +
8624 input_section->output_offset +
8625 rel->r_offset).
8626 A is the addend, converted into bytes, ie:
8627 (signed_addend * 4)
8629 Note: None of these operations have knowledge of the pipeline
8630 size of the processor, thus it is up to the assembler to
8631 encode this information into the addend. */
8637 else
8638 /* RELA addends do not have to be adjusted by howto->size. */
8644 /* A branch to an undefined weak symbol is turned into a jump to
8645 the next instruction unless a PLT entry will be created.
8646 Do the same for local undefined symbols (but not for STN_UNDEF).
8647 The jump to the next instruction is optimized as a NOP depending
8648 on the architecture. */
8652 {
8657 else
8659 }
8660 else
8661 {
8662 /* Perform a signed range check. */
8673 {
8674 /* Set the H bit in the BLX instruction. */
8676 {
8679 else
8681 }
8683 /* Select the correct instruction (BL or BLX). */
8684 /* Only if we are not handling a BL to a stub. In this
8685 case, mode switching is performed by the stub. */
8689 {
8692 }
8693 }
8694 }
8695 }
8727 {
8728 /* Check for overflow. */
8731 }
8737 }
8743 /* PR 16202: Refectch the addend using the correct size. */
8748 /* There is no way to tell whether the user intended to use a signed or
8749 unsigned addend. When checking for overflow we accept either,
8750 as specified by the AAELF. */
8758 /* PR 16202: Refectch the addend using the correct size. */
8763 /* See comment for R_ARM_ABS8. */
8771 /* Support ldr and str instructions for the thumb. */
8773 {
8774 /* Need to refetch addend. */
8776 /* ??? Need to determine shift amount from operand size. */
8778 }
8781 /* ??? Isn't value unsigned? */
8785 /* ??? Value needs to be properly shifted into place first. */
8791 /* Corresponds to: addw.w reg, pc, #offset (and similarly for subw). */
8792 {
8793 bfd_vma insn;
8794 bfd_signed_vma relocation;
8800 {
8805 }
8827 }
8830 /* PR 10073: This reloc is not generated by the GNU toolchain,
8831 but it is supported for compatibility with third party libraries
8832 generated by other compilers, specifically the ARM/IAR. */
8833 {
8834 bfd_vma insn;
8835 bfd_signed_vma relocation;
8849 /* We do not check for overflow of this reloc. Although strictly
8850 speaking this is incorrect, it appears to be necessary in order
8851 to work with IAR generated relocs. Since GCC and GAS do not
8852 generate R_ARM_THM_PC8 relocs, the lack of a check should not be
8853 a problem for them. */
8861 }
8864 /* Corresponds to: ldr.w reg, [pc, #offset]. */
8865 {
8866 bfd_vma insn;
8867 bfd_signed_vma relocation;
8873 {
8877 }
8897 }
8902 /* Thumb BL (branch long instruction). */
8903 {
8904 bfd_vma relocation;
8905 bfd_vma reloc_sign;
8909 bfd_signed_vma reloc_signed_max;
8910 bfd_signed_vma reloc_signed_min;
8911 bfd_vma check;
8912 bfd_signed_vma signed_check;
8916 /* A branch to an undefined weak symbol is turned into a jump to
8917 the next instruction unless a PLT entry will be created.
8918 The jump to the next instruction is optimized as a NOP.W for
8919 Thumb-2 enabled architectures. */
8922 {
8924 {
8927 }
8928 else
8929 {
8932 }
8934 }
8936 /* Fetch the addend. We use the Thumb-2 encoding (backwards compatible
8937 with Thumb-1) involving the J1 and J2 bits. */
8939 {
8949 /* Sign extend. */
8953 }
8956 {
8957 /* Check for Thumb to Thumb call. */
8958 /* FIXME: Should we translate the instruction into a BL
8959 instruction instead ? */
8963 input_bfd,
8965 }
8966 else
8967 {
8968 /* If it is not a call to Thumb, assume call to Arm.
8969 If it is a call relative to a section name, then it is not a
8970 function call at all, but rather a long jump. Calls through
8971 the PLT do not require stubs. */
8973 {
8975 {
8976 /* Convert BL to BLX. */
8978 }
8981 {
8985 error_message))
8987 else
8989 }
8990 }
8994 {
8995 /* Make sure this is a BL. */
8997 }
8998 }
9002 {
9003 /* Check if a stub has to be inserted because the destination
9004 is too far. */
9016 {
9017 /* The target is out of reach or we are changing modes, so
9018 redirect the branch to the local stub for this
9019 function. */
9023 stub_type);
9025 {
9032 }
9034 /* If this call becomes a call to Arm, force BLX. */
9036 {
9041 }
9042 }
9043 }
9045 /* Handle calls via the PLT. */
9047 {
9055 {
9056 /* If the Thumb BLX instruction is available, convert
9057 the BL to a BLX instruction to call the ARM-mode
9058 PLT entry. */
9061 }
9062 else
9063 {
9065 /* Target the Thumb stub before the ARM PLT entry. */
9068 }
9070 }
9080 /* If this is a signed value, the rightshift just dropped
9081 leading 1 bits (assuming twos complement). */
9084 else
9087 /* Calculate the permissable maximum and minimum values for
9088 this relocation according to whether we're relocating for
9089 Thumb-2 or not. */
9096 /* Assumes two's complement. */
9101 /* For a BLX instruction, make sure that the relocation is rounded up
9102 to a word boundary. This follows the semantics of the instruction
9103 which specifies that bit 1 of the target address will come from bit
9104 1 of the base address. */
9107 /* Put RELOCATION back into the insn. Assumes two's complement.
9108 We use the Thumb-2 encoding, which is safe even if dealing with
9109 a Thumb-1 instruction by virtue of our overflow check above. */
9119 /* Put the relocated value back in the object file: */
9124 }
9128 /* Thumb32 conditional branch instruction. */
9129 {
9130 bfd_vma relocation;
9136 bfd_signed_vma signed_check;
9141 /* Need to refetch the addend, reconstruct the top three bits,
9142 and squish the two 11 bit pieces together. */
9144 {
9158 }
9160 /* Handle calls via the PLT. */
9162 {
9166 /* Target the Thumb stub before the ARM PLT entry. */
9169 }
9178 {
9182 stub_type);
9184 {
9188 }
9189 }
9200 /* Put RELOCATION back into the insn. */
9201 {
9210 }
9212 /* Put the relocated value back in the object file: */
9217 }
9222 /* Thumb B (branch) instruction). */
9223 {
9224 bfd_signed_vma relocation;
9227 bfd_signed_vma signed_check;
9229 /* CZB cannot jump backward. */
9234 {
9235 /* Need to refetch addend. */
9238 {
9242 }
9243 else
9245 /* The value in the insn has been right shifted. We need to
9246 undo this, so that we can perform the address calculation
9247 in terms of bytes. */
9249 }
9261 else
9267 /* Assumes two's complement. */
9272 }
9277 {
9278 bfd_vma insn;
9279 bfd_vma relocation;
9283 {
9284 /* Extract the addend. */
9287 }
9297 }
9305 /* Relocation is relative to the start of the
9306 global offset table. */
9312 /* If we are addressing a Thumb function, we need to adjust the
9313 address by one, so that attempts to call the function pointer will
9314 correctly interpret it as Thumb code. */
9318 /* Note that sgot->output_offset is not involved in this
9319 calculation. We always want the start of .got. If we
9320 define _GLOBAL_OFFSET_TABLE in a different way, as is
9321 permitted by the ABI, we might have to change this
9322 calculation. */
9329 /* Use global offset table as symbol value. */
9343 /* Relocation is to the entry for this symbol in the
9344 global offset table. */
9351 {
9352 /* We have a relocation against a locally-binding STT_GNU_IFUNC
9353 symbol, and the relocation resolves directly to the runtime
9354 target rather than to the .iplt entry. This means that any
9355 .got entry would be the same value as the .igot.plt entry,
9356 so there's no point creating both. */
9359 }
9361 {
9362 bfd_vma off;
9367 {
9368 /* We have already processsed one GOT relocation against
9369 this symbol. */
9374 }
9375 else
9376 {
9377 Elf_Internal_Rela outrel;
9380 {
9381 /* If the symbol doesn't resolve locally in a static
9382 object, we have an undefined reference. If the
9383 symbol doesn't resolve locally in a dynamic object,
9384 it should be resolved by the dynamic linker. */
9386 {
9389 }
9390 else
9393 }
9394 else
9395 {
9402 else
9405 }
9407 /* The GOT entry is initialized to zero by default.
9408 See if we should install a different value. */
9411 {
9415 }
9418 {
9423 }
9425 }
9427 }
9428 else
9429 {
9430 bfd_vma off;
9437 /* The offset must always be a multiple of 4. We use the
9438 least significant bit to record whether we have already
9439 generated the necessary reloc. */
9442 else
9443 {
9448 {
9449 Elf_Internal_Rela outrel;
9457 else
9460 }
9463 }
9466 }
9482 {
9483 bfd_vma off;
9492 else
9493 {
9494 /* If we don't know the module number, create a relocation
9495 for it. */
9497 {
9498 Elf_Internal_Rela outrel;
9513 }
9514 else
9518 }
9526 }
9535 {
9543 {
9544 bfd_boolean dyn;
9549 {
9552 }
9556 }
9557 else
9558 {
9563 }
9565 /* Linker relaxations happens from one of the
9566 R_ARM_{GOTDESC,CALL,DESCSEQ} relocations to IE or LE. */
9574 else
9575 {
9577 Elf_Internal_Rela outrel;
9580 /* The GOT entries have not been initialized yet. Do it
9581 now, and emit any relocations. If both an IE GOT and a
9582 GD GOT are necessary, we emit the GD first. */
9588 {
9591 }
9594 {
9597 /* We should have relaxed, unless this is an undefined
9598 weak symbol. */
9607 + offplt
9619 /* For globals, the first word in the relocation gets
9620 the relocation index and the top bit set, or zero,
9621 if we're binding now. For locals, it gets the
9622 symbol's offset in the tls section. */
9630 /* Second word in the relocation is always zero. */
9634 }
9636 {
9638 {
9654 else
9655 {
9658 R_ARM_TLS_DTPOFF32);
9667 }
9668 }
9669 else
9670 {
9671 /* If we are not emitting relocations for a
9672 general dynamic reference, then we must be in a
9673 static link or an executable link with the
9674 symbol binding locally. Mark it as belonging
9675 to module 1, the executable. */
9680 }
9683 }
9686 {
9688 {
9691 else
9703 }
9704 else
9708 }
9712 else
9714 }
9723 {
9724 bfd_signed_vma offset;
9725 /* TLS stubs are arm mode. The original symbol is a
9726 data object, so branch_type is bogus. */
9728 enum elf32_arm_stub_type stub_type
9736 {
9738 = elf32_arm_get_stub_entry
9744 }
9745 else
9751 {
9761 }
9762 else
9763 {
9764 /* Thumb blx encodes the offset in a complicated
9765 fashion. */
9775 {
9777 }
9778 else
9779 {
9781 /* Round up the offset to a word boundary. */
9783 }
9795 }
9796 }
9797 /* These relocations needs special care, as besides the fact
9798 they point somewhere in .gotplt, the addend must be
9799 adjusted accordingly depending on the type of instruction
9800 we refer to. */
9802 {
9811 {
9818 /* bl/blx */
9821 /* add */
9823 else
9824 {
9830 }
9831 }
9832 else
9833 {
9837 {
9853 }
9854 }
9862 }
9863 else
9872 }
9876 {
9882 }
9883 else
9892 {
9895 /* Ensure that we have a BX instruction. */
9899 {
9900 /* Branch to veneer. */
9901 bfd_vma glue_addr;
9908 }
9909 else
9910 {
9911 /* Preserve Rm (lowest four bits) and the condition code
9912 (highest four bits). Other bits encode MOV PC,Rm. */
9914 }
9917 }
9924 /* Until we properly support segment-base-relative addressing then
9925 we assume the segment base to be zero, as for the group relocations.
9926 Thus R_ARM_MOVW_BREL_NC has the same semantics as R_ARM_MOVW_ABS_NC
9927 and R_ARM_MOVT_BREL has the same semantics as R_ARM_MOVT_ABS. */
9931 {
9935 {
9938 }
9960 }
9967 /* Until we properly support segment-base-relative addressing then
9968 we assume the segment base to be zero, as for the above relocations.
9969 Thus R_ARM_THM_MOVW_BREL_NC has the same semantics as
9970 R_ARM_THM_MOVW_ABS_NC and R_ARM_THM_MOVT_BREL has the same semantics
9971 as R_ARM_THM_MOVT_ABS. */
9975 {
9976 bfd_vma insn;
9982 {
9988 }
10014 }
10027 {
10031 /* sb is the origin of the *segment* containing the symbol. */
10033 bfd_vma residual;
10034 bfd_vma g_n;
10035 bfd_signed_vma signed_value;
10038 /* Determine which group of bits to select. */
10040 {
10062 }
10064 /* If REL, extract the addend from the insn. If RELA, it will
10065 have already been fetched for us. */
10067 {
10074 else
10075 {
10076 /* Compensate for the fact that in the instruction, the
10077 rotation is stored in multiples of 2 bits. */
10080 /* Rotate "constant" right by "rotation" bits. */
10083 }
10085 /* Determine if the instruction is an ADD or a SUB.
10086 (For REL, this determines the sign of the addend.) */
10089 {
10095 }
10098 }
10100 /* Compute the value (X) to go in the place. */
10106 /* PC relative. */
10108 else
10109 /* Section base relative. */
10112 /* If the target symbol is a Thumb function, then set the
10113 Thumb bit in the address. */
10117 /* Calculate the value of the relevant G_n, in encoded
10118 constant-with-rotation format. */
10122 /* Check for overflow if required. */
10129 {
10135 }
10137 /* Mask out the value and the ADD/SUB part of the opcode; take care
10138 not to destroy the S bit. */
10141 /* Set the opcode according to whether the value to go in the
10142 place is negative. */
10145 else
10148 /* Encode the offset. */
10152 }
10161 {
10165 /* sb is the origin of the *segment* containing the symbol. */
10167 bfd_vma residual;
10168 bfd_signed_vma signed_value;
10171 /* Determine which groups of bits to calculate. */
10173 {
10191 }
10193 /* If REL, extract the addend from the insn. If RELA, it will
10194 have already been fetched for us. */
10196 {
10199 }
10201 /* Compute the value (X) to go in the place. */
10205 /* PC relative. */
10207 else
10208 /* Section base relative. */
10211 /* Calculate the value of the relevant G_{n-1} to obtain
10212 the residual at that stage. */
10215 /* Check for overflow. */
10217 {
10223 }
10225 /* Mask out the value and U bit. */
10228 /* Set the U bit if the value to go in the place is non-negative. */
10232 /* Encode the offset. */
10236 }
10245 {
10249 /* sb is the origin of the *segment* containing the symbol. */
10251 bfd_vma residual;
10252 bfd_signed_vma signed_value;
10255 /* Determine which groups of bits to calculate. */
10257 {
10275 }
10277 /* If REL, extract the addend from the insn. If RELA, it will
10278 have already been fetched for us. */
10280 {
10283 }
10285 /* Compute the value (X) to go in the place. */
10289 /* PC relative. */
10291 else
10292 /* Section base relative. */
10295 /* Calculate the value of the relevant G_{n-1} to obtain
10296 the residual at that stage. */
10299 /* Check for overflow. */
10301 {
10307 }
10309 /* Mask out the value and U bit. */
10312 /* Set the U bit if the value to go in the place is non-negative. */
10316 /* Encode the offset. */
10320 }
10329 {
10333 /* sb is the origin of the *segment* containing the symbol. */
10335 bfd_vma residual;
10336 bfd_signed_vma signed_value;
10339 /* Determine which groups of bits to calculate. */
10341 {
10359 }
10361 /* If REL, extract the addend from the insn. If RELA, it will
10362 have already been fetched for us. */
10364 {
10367 }
10369 /* Compute the value (X) to go in the place. */
10373 /* PC relative. */
10375 else
10376 /* Section base relative. */
10379 /* Calculate the value of the relevant G_{n-1} to obtain
10380 the residual at that stage. */
10383 /* Check for overflow. (The absolute value to go in the place must be
10384 divisible by four and, after having been divided by four, must
10385 fit in eight bits.) */
10387 {
10393 }
10395 /* Mask out the value and U bit. */
10398 /* Set the U bit if the value to go in the place is non-negative. */
10402 /* Encode the offset. */
10406 }
10411 }
10412 }
10414 /* Add INCREMENT to the reloc (of type HOWTO) at ADDRESS. */
10415 static void
10419 bfd_signed_vma increment)
10420 {
10421 bfd_signed_vma addend;
10425 {
10443 }
10444 else
10445 {
10446 bfd_vma contents;
10450 /* Get the (signed) value from the instruction. */
10453 {
10454 bfd_signed_vma mask;
10459 }
10461 /* Add in the increment, (which is a byte value). */
10463 {
10475 /* Should we check for overflow here ? */
10477 /* Drop any undesired bits. */
10480 }
10485 }
10486 }
10488 #define IS_ARM_TLS_RELOC(R_TYPE) \
10489 ((R_TYPE) == R_ARM_TLS_GD32 \
10490 || (R_TYPE) == R_ARM_TLS_LDO32 \
10491 || (R_TYPE) == R_ARM_TLS_LDM32 \
10492 || (R_TYPE) == R_ARM_TLS_DTPOFF32 \
10493 || (R_TYPE) == R_ARM_TLS_DTPMOD32 \
10494 || (R_TYPE) == R_ARM_TLS_TPOFF32 \
10495 || (R_TYPE) == R_ARM_TLS_LE32 \
10496 || (R_TYPE) == R_ARM_TLS_IE32 \
10497 || IS_ARM_TLS_GNU_RELOC (R_TYPE))
10499 /* Specific set of relocations for the gnu tls dialect. */
10500 #define IS_ARM_TLS_GNU_RELOC(R_TYPE) \
10501 ((R_TYPE) == R_ARM_TLS_GOTDESC \
10502 || (R_TYPE) == R_ARM_TLS_CALL \
10503 || (R_TYPE) == R_ARM_THM_TLS_CALL \
10504 || (R_TYPE) == R_ARM_TLS_DESCSEQ \
10505 || (R_TYPE) == R_ARM_THM_TLS_DESCSEQ)
10507 /* Relocate an ARM ELF section. */
10509 static bfd_boolean
10518 {
10536 {
10543 bfd_vma relocation;
10544 bfd_reloc_status_type r;
10545 arelent bfd_reloc;
10566 {
10571 /* An object file might have a reference to a local
10572 undefined symbol. This is a daft object file, but we
10573 should at least do something about it. V4BX & NONE
10574 relocations do not use the symbol and are explicitly
10575 allowed to use the undefined symbol, so allow those.
10576 Likewise for relocations against STN_UNDEF. */
10582 {
10589 }
10592 {
10599 {
10604 {
10626 {
10632 }
10636 /* Get the (signed) value from the instruction. */
10639 {
10640 bfd_signed_vma mask;
10645 }
10647 }
10650 addend =
10655 /* Cases here must match those in the preceding
10656 switch statement. */
10658 {
10681 }
10682 }
10683 }
10684 else
10686 }
10687 else
10688 {
10697 }
10704 {
10705 /* This is a relocatable link. We don't have to change
10706 anything, unless the reloc is against a section symbol,
10707 in which case we have to adjust according to where the
10708 section symbol winds up in the output section. */
10710 {
10714 else
10716 }
10718 }
10722 else
10723 {
10724 name = (bfd_elf_string_from_elf_section
10728 }
10736 {
10741 input_bfd,
10742 input_section,
10745 name);
10746 }
10748 /* We call elf32_arm_final_link_relocate unless we're completely
10749 done, i.e., the relaxation produced the final output we want,
10750 and we won't let anybody mess with it. Also, we have to do
10751 addend adjustments in case of a R_ARM_TLS_GOTDESC relocation
10752 both in relaxed and non-relaxed cases. */
10758 {
10761 /* This may have been marked unresolved because it came from
10762 a shared library. But we've just dealt with that. */
10764 }
10765 else
10776 /* Dynamic relocs are not propagated for SEC_DEBUGGING sections
10777 because such sections are not SEC_ALLOC and thus ld.so will
10778 not process them. */
10784 {
10787 input_bfd,
10788 input_section,
10793 }
10796 {
10798 {
10800 /* If the overflowing reloc was to an undefined symbol,
10801 we have already printed one error message and there
10802 is no point complaining again. */
10828 /* error_message should already be set. */
10833 /* Fall through. */
10835 common_error:
10842 }
10843 }
10844 }
10847 }
10849 /* Add a new unwind edit to the list described by HEAD, TAIL. If TINDEX is zero,
10850 adds the edit to the start of the list. (The list must be built in order of
10851 ascending TINDEX: the function's callers are primarily responsible for
10852 maintaining that condition). */
10854 static void
10857 arm_unwind_edit_type type,
10860 {
10869 {
10879 }
10880 else
10881 {
10888 }
10889 }
10893 /* Increase the size of EXIDX_SEC by ADJUST bytes. ADJUST mau be negative. */
10894 static void
10896 {
10904 /* Adjust size of output section. */
10906 }
10908 /* Insert an EXIDX_CANTUNWIND marker at the end of a section. */
10909 static void
10911 {
10921 }
10923 /* Scan .ARM.exidx tables, and create a list describing edits which should be
10924 made to those tables, such that:
10926 1. Regions without unwind data are marked with EXIDX_CANTUNWIND entries.
10927 2. Duplicate entries are merged together (EXIDX_CANTUNWIND, or unwind
10928 codes which have been inlined into the index).
10930 If MERGE_EXIDX_ENTRIES is false, duplicate entries are not merged.
10932 The edits are applied when the tables are written
10933 (in elf32_arm_write_section). */
10935 bfd_boolean
10939 bfd_boolean merge_exidx_entries)
10940 {
10947 /* Walk over all EXIDX sections, and create backlinks from the corrsponding
10948 text sections. */
10950 {
10954 {
10962 {
10963 Elf_Internal_Shdr *linked_hdr
10971 /* Link this .ARM.exidx section back from the text section it
10972 describes. */
10974 }
10975 }
10976 }
10978 /* Walk all text sections in order of increasing VMA. Eilminate duplicate
10979 index table entries (EXIDX_CANTUNWIND and inlined unwind opcodes),
10980 and add EXIDX_CANTUNWIND entries for sections with no unwind table data. */
10983 {
10990 bfd_vma j;
11001 {
11002 /* Section has no unwind data. */
11006 /* Ignore zero sized sections. */
11013 }
11015 /* Skip /DISCARD/ sections. */
11032 /* An error? */
11036 {
11041 /* An EXIDX_CANTUNWIND entry. */
11043 {
11047 }
11048 /* Inlined unwinding data. Merge if equal to previous. */
11050 {
11056 }
11057 /* Normal table entry. In theory we could merge these too,
11058 but duplicate entries are likely to be much less common. */
11059 else
11063 {
11068 }
11071 }
11073 /* Free contents if we allocated it ourselves. */
11077 /* Record edits to be applied later (in elf32_arm_write_section). */
11086 }
11088 /* Add terminating CANTUNWIND entry. */
11093 }
11095 static bfd_boolean
11098 {
11114 }
11116 static bfd_boolean
11118 {
11125 /* Invoke the regular ELF backend linker to do all the work. */
11129 /* Process stub sections (eg BE8 encoding, ...). */
11133 {
11135 /* Only process it once, in its link_sec slot. */
11137 {
11143 }
11144 }
11146 /* Write out any glue sections now that we have created all the
11147 stubs. */
11149 {
11152 ARM2THUMB_GLUE_SECTION_NAME))
11157 THUMB2ARM_GLUE_SECTION_NAME))
11162 VFP11_ERRATUM_VENEER_SECTION_NAME))
11167 ARM_BX_GLUE_SECTION_NAME))
11169 }
11172 }
11174 /* Return a best guess for the machine number based on the attributes. */
11176 static unsigned int
11178 {
11182 {
11188 {
11195 {
11203 {
11209 {
11213 }
11214 }
11215 }
11218 }
11222 }
11223 }
11225 /* Set the right machine number. */
11227 static bfd_boolean
11229 {
11235 {
11238 else
11240 }
11244 }
11246 /* Function to keep ARM specific flags in the ELF header. */
11248 static bfd_boolean
11250 {
11253 {
11255 {
11258 (_("Warning: Not setting interworking flag of %B since it has already been specified as non-interworking"),
11259 abfd);
11260 else
11261 _bfd_error_handler
11263 abfd);
11264 }
11265 }
11266 else
11267 {
11270 }
11273 }
11275 /* Copy backend specific data from one object module to another. */
11277 static bfd_boolean
11279 {
11280 flagword in_flags;
11281 flagword out_flags;
11292 {
11293 /* Cannot mix APCS26 and APCS32 code. */
11297 /* Cannot mix float APCS and non-float APCS code. */
11301 /* If the src and dest have different interworking flags
11302 then turn off the interworking bit. */
11304 {
11306 _bfd_error_handler
11307 (_("Warning: Clearing the interworking flag of %B because non-interworking code in %B has been linked with it"),
11311 }
11313 /* Likewise for PIC, though don't warn for this case. */
11316 }
11322 }
11324 /* Values for Tag_ABI_PCS_R9_use. */
11325 enum
11326 {
11327 AEABI_R9_V6,
11328 AEABI_R9_SB,
11329 AEABI_R9_TLS,
11330 AEABI_R9_unused
11331 };
11333 /* Values for Tag_ABI_PCS_RW_data. */
11334 enum
11335 {
11336 AEABI_PCS_RW_data_absolute,
11337 AEABI_PCS_RW_data_PCrel,
11338 AEABI_PCS_RW_data_SBrel,
11339 AEABI_PCS_RW_data_unused
11340 };
11342 /* Values for Tag_ABI_enum_size. */
11343 enum
11344 {
11345 AEABI_enum_unused,
11346 AEABI_enum_short,
11347 AEABI_enum_wide,
11348 AEABI_enum_forced_wide
11349 };
11351 /* Determine whether an object attribute tag takes an integer, a
11352 string or both. */
11354 static int
11356 {
11365 else
11367 }
11369 /* The ABI defines that Tag_conformance should be emitted first, and that
11370 Tag_nodefaults should be second (if either is defined). This sets those
11371 two positions, and bumps up the position of all the remaining tags to
11372 compensate. */
11373 static int
11375 {
11385 }
11387 /* Attribute numbers >=64 (mod 128) can be safely ignored. */
11388 static bfd_boolean
11390 {
11392 {
11393 _bfd_error_handler
11398 }
11399 else
11400 {
11401 _bfd_error_handler
11405 }
11406 }
11408 /* Read the architecture from the Tag_also_compatible_with attribute, if any.
11409 Returns -1 if no architecture could be read. */
11411 static int
11413 {
11417 /* Note: the tag and its argument below are uleb128 values, though
11418 currently-defined values fit in one byte for each. */
11425 /* This tag is "safely ignorable", so don't complain if it looks funny. */
11427 }
11429 /* Set, or unset, the architecture of the Tag_also_compatible_with attribute.
11430 The tag is removed if ARCH is -1. */
11432 static void
11434 {
11439 {
11442 }
11444 /* Note: the tag and its argument below are uleb128 values, though
11445 currently-defined values fit in one byte for each. */
11451 }
11453 /* Combine two values for Tag_CPU_arch, taking secondary compatibility tags
11454 into account. */
11456 static int
11459 {
11460 #define T(X) TAG_CPU_ARCH_##X
11463 {
11473 };
11475 {
11486 };
11488 {
11500 };
11502 {
11515 };
11517 {
11531 };
11533 {
11548 };
11550 {
11566 };
11568 {
11585 };
11587 {
11588 v6t2,
11589 v6k,
11590 v7,
11591 v6_m,
11592 v6s_m,
11593 v7e_m,
11594 v8,
11595 /* Pseudo-architecture. */
11596 v4t_plus_v6_m
11597 };
11599 /* Check we've not got a higher architecture than we know about. */
11602 {
11605 }
11607 /* Override old tag if we have a Tag_also_compatible_with on the output. */
11613 /* And override the new tag if we have a Tag_also_compatible_with on the
11614 input. */
11623 /* Architectures before V6KZ add features monotonically. */
11629 /* Use Tag_CPU_arch == V4T and Tag_also_compatible_with (Tag_CPU_arch V6_M)
11630 as the canonical version. */
11632 {
11635 }
11636 else
11640 {
11644 }
11647 #undef T
11648 }
11650 /* Query attributes object to see if integer divide instructions may be
11651 present in an object. */
11652 static bfd_boolean
11654 {
11659 {
11661 /* Integer divide allowed if instruction contained in archetecture. */
11666 else
11670 /* Integer divide explicitly prohibited. */
11674 /* Unrecognised case - treat as allowing divide everywhere. */
11676 /* Integer divide allowed in ARM state. */
11678 }
11679 }
11681 /* Query attributes object to see if integer divide instructions are
11682 forbidden to be in the object. This is not the inverse of
11683 elf32_arm_attributes_accept_div. */
11684 static bfd_boolean
11686 {
11688 }
11690 /* Merge EABI object attributes from IBFD into OBFD. Raise an error if there
11691 are conflicting attributes. */
11693 static bfd_boolean
11695 {
11698 /* Some tags have 0 = don't care, 1 = strong requirement,
11699 2 = weak requirement. */
11704 /* Skip the linker stubs file. This preserves previous behavior
11705 of accepting unknown attributes in the first input file - but
11706 is that a bug? */
11711 {
11712 /* This is the first object. Copy the attributes. */
11717 /* Use the Tag_null value to indicate the attributes have been
11718 initialized. */
11721 /* We do not output objects with Tag_MPextension_use_legacy - we move
11722 the attribute's value to Tag_MPextension_use. */
11724 {
11728 {
11729 _bfd_error_handler
11733 }
11739 }
11742 }
11746 /* This needs to happen before Tag_ABI_FP_number_model is merged. */
11748 {
11749 /* Ignore mismatches if the object doesn't use floating point. */
11753 {
11754 _bfd_error_handler
11759 }
11760 }
11763 {
11764 /* Merge this attribute with existing attributes. */
11766 {
11769 /* These are merged after Tag_CPU_arch. */
11774 /* Use the first value seen. */
11778 {
11783 {
11784 /* These aren't real CPU names, but we can't guess
11785 that from the architecture version alone. */
11799 "ARM v8"
11800 };
11802 /* Merge Tag_CPU_arch and Tag_also_compatible_with. */
11808 secondary_compat);
11810 /* Return with error if failed to merge. */
11818 /* Merge Tag_CPU_name and Tag_CPU_raw_name. */
11822 {
11823 /* The output architecture has been changed to match the
11824 input architecture. Use the input names. */
11831 }
11832 else
11833 {
11836 }
11838 /* If we still don't have a value for Tag_CPU_name,
11839 make one up now. Tag_CPU_raw_name remains blank. */
11844 }
11851 /* ??? Do Advanced_SIMD (NEON) and WMMX conflict? */
11860 /* Use the largest value specified. */
11867 /* Use the smallest value specified. */
11876 {
11877 /* This error message should be enabled once all non-conformant
11878 binaries in the toolchain have had the attributes set
11879 properly.
11880 _bfd_error_handler
11881 (_("error: %B: 8-byte data alignment conflicts with %B"),
11882 obfd, ibfd);
11883 result = FALSE; */
11884 }
11885 /* Fall through. */
11888 /* Use the "greatest" from the sequence 0, 2, 1, or the largest
11889 value if greater than 2 (for future-proofing). */
11897 /* The virtualization tag effectively stores two bits of
11898 information: the intended use of TrustZone (in bit 0), and the
11899 intended use of Virtualization (in bit 1). */
11904 {
11907 else
11908 {
11909 _bfd_error_handler
11914 }
11915 }
11920 {
11921 /* 0 will merge with anything.
11922 'A' and 'S' merge to 'A'.
11923 'R' and 'S' merge to 'R'.
11924 'M' and 'A|R|S' is an error. */
11933 else
11934 {
11935 _bfd_error_handler
11937 ibfd,
11941 }
11942 }
11945 {
11946 /* Tag_ABI_HardFP_use is handled along with Tag_FP_arch since
11947 the meaning of Tag_ABI_HardFP_use depends on Tag_FP_arch
11948 when it's 0. It might mean absence of FP hardware if
11949 Tag_FP_arch is zero, otherwise it is effectively SP + DP. */
11951 #define VFP_VERSION_COUNT 8
11952 static const struct
11953 {
11957 {
11966 };
11971 /* If the output has no requirement about FP hardware,
11972 follow the requirement of the input. */
11974 {
11980 }
11981 /* If the input has no requirement about FP hardware, do
11982 nothing. */
11984 {
11987 }
11989 /* Both the input and the output have nonzero Tag_FP_arch.
11990 So Tag_ABI_HardFP_use is (SP & DP) when it's zero. */
11992 /* If both the input and the output have zero Tag_ABI_HardFP_use,
11993 do nothing. */
11996 ;
11997 /* If the input and the output have different Tag_ABI_HardFP_use,
11998 the combination of them is 3 (SP & DP). */
12003 /* Now we can handle Tag_FP_arch. */
12005 /* Values of VFP_VERSION_COUNT or more aren't defined, so just
12006 pick the biggest. */
12009 {
12012 }
12013 /* The output uses the superset of input features
12014 (ISA version) and registers. */
12021 /* This assumes all possible supersets are also a valid
12022 options. */
12024 {
12028 }
12030 }
12036 {
12037 /* It's sometimes ok to mix different configs, so this is only
12038 a warning. */
12039 _bfd_error_handler
12041 }
12047 {
12048 _bfd_error_handler
12051 }
12059 {
12060 _bfd_error_handler
12062 ibfd);
12064 }
12065 /* Use the smallest value specified. */
12072 {
12073 _bfd_error_handler
12074 (_("warning: %B uses %u-byte wchar_t yet the output is to use %u-byte wchar_t; use of wchar_t values across objects may fail"),
12076 }
12082 {
12085 {
12086 /* The existing object is compatible with anything.
12087 Use whatever requirements the new object has. */
12089 }
12093 {
12104 _bfd_error_handler
12105 (_("warning: %B uses %s enums yet the output is to use %s enums; use of enum values across objects may fail"),
12107 }
12108 }
12111 /* Aready done. */
12115 {
12116 _bfd_error_handler
12120 }
12123 /* Merged in target-independent code. */
12126 /* This is handled along with Tag_FP_arch. */
12130 {
12132 {
12133 _bfd_error_handler
12137 }
12138 }
12144 /* A value of zero on input means that the divide instruction may
12145 be used if available in the base architecture as specified via
12146 Tag_CPU_arch and Tag_CPU_arch_profile. A value of 1 means that
12147 the user did not want divide instructions. A value of 2
12148 explicitly means that divide instructions were allowed in ARM
12149 and Thumb state. */
12163 /* We don't output objects with Tag_MPextension_use_legacy - we
12164 move the value to Tag_MPextension_use. */
12166 {
12168 {
12169 _bfd_error_handler
12172 ibfd);
12174 }
12175 }
12183 /* This tag is set if it exists, but the value is unused (and is
12184 typically zero). We don't actually need to do anything here -
12185 the merge happens automatically when the type flags are merged
12186 below. */
12189 /* Already done in Tag_CPU_arch. */
12192 /* Keep the attribute if it matches. Throw it away otherwise.
12193 No attribute means no claim to conform. */
12200 result
12202 }
12204 /* If out_attr was copied from in_attr then it won't have a type yet. */
12207 }
12209 /* Merge Tag_compatibility attributes and any common GNU ones. */
12213 /* Check for any attributes not known on ARM. */
12217 }
12220 /* Return TRUE if the two EABI versions are incompatible. */
12222 static bfd_boolean
12224 {
12225 /* v4 and v5 are the same spec before and after it was released,
12226 so allow mixing them. */
12232 }
12234 /* Merge backend specific data from an object file to the output
12235 object file when linking. */
12237 static bfd_boolean
12240 /* Display the flags field. */
12242 static bfd_boolean
12244 {
12250 /* Print normal ELF private data. */
12254 /* Ignore init flag - it may not be set, despite the flags field
12255 containing valid data. */
12257 /* xgettext:c-format */
12261 {
12263 /* The following flag bits are GNU extensions and not part of the
12264 official ARM ELF extended ABI. Hence they are only decoded if
12265 the EABI version is not set. */
12271 else
12278 else
12307 else
12318 else
12350 eabi:
12363 }
12381 }
12383 static int
12385 {
12387 {
12392 /* If the symbol is not an object, return the STT_ARM_16BIT flag.
12393 This allows us to distinguish between data used by Thumb instructions
12394 and non-data (which is probably code) inside Thumb regions of an
12395 executable. */
12402 }
12405 }
12413 {
12416 {
12420 }
12423 }
12425 /* Update the got entry reference counts for the section being removed. */
12427 static bfd_boolean
12432 {
12456 {
12461 bfd_boolean call_reloc_p;
12462 bfd_boolean may_become_dynamic_p;
12463 bfd_boolean may_need_local_target_p;
12469 {
12474 }
12484 {
12490 {
12493 }
12495 {
12498 }
12519 {
12522 }
12523 /* Fall through. */
12536 /* Should the interworking branches be here also? */
12539 {
12542 {
12545 }
12546 else
12548 }
12549 else
12555 }
12559 {
12560 /* If PLT refcount book-keeping is wrong and too low, we'll
12561 see a zero value (going to -1) for the root PLT reference
12562 count. */
12564 {
12567 }
12568 else
12569 /* A value of -1 means the symbol has become local, forced
12570 or seeing a hidden definition. Any other negative value
12571 is an error. */
12583 }
12586 {
12592 else
12593 {
12603 }
12606 {
12607 /* Everything must go for SEC. */
12610 }
12611 }
12612 }
12615 }
12617 /* Look through the relocs for a section during the first phase. */
12619 static bfd_boolean
12622 {
12630 bfd_boolean call_reloc_p;
12631 bfd_boolean may_become_dynamic_p;
12632 bfd_boolean may_need_local_target_p;
12646 /* Create dynamic sections for relocatable executables so that we can
12647 copy relocations. */
12650 {
12653 }
12668 {
12680 /* PR 9934: It is possible to have relocations that do not
12681 refer to symbols, thus it is also possible to have an
12682 object file containing relocations but no symbol table. */
12684 {
12686 r_symndx);
12688 }
12693 {
12695 {
12696 /* A local symbol. */
12701 }
12702 else
12703 {
12709 /* PR15323, ref flags aren't set for references in the
12710 same object. */
12712 }
12713 }
12721 /* Could be done earlier, if h were already available. */
12724 {
12734 /* This symbol requires a global offset table entry. */
12735 {
12739 {
12750 }
12756 {
12759 }
12760 else
12761 {
12762 /* This is a global offset table entry for a local symbol. */
12767 }
12769 /* If a variable is accessed with both tls methods, two
12770 slots may be created. */
12775 /* We will already have issued an error message if there
12776 is a TLS/non-TLS mismatch, based on the symbol
12777 type. So just combine any TLS types needed. */
12782 /* If the symbol is accessed in both IE and GDESC
12783 method, we're able to relax. Turn off the GDESC flag,
12784 without messing up with any other kind of tls types
12785 that may be involved. */
12790 {
12793 else
12795 }
12796 }
12797 /* Fall through. */
12802 /* Fall through. */
12824 /* VxWorks uses dynamic R_ARM_ABS12 relocations for
12825 ldr __GOTT_INDEX__ offsets. */
12827 {
12830 }
12831 /* Fall through. */
12838 {
12840 (_("%B: relocation %s against `%s' can not be used when making a shared object; recompile with -fPIC"),
12845 }
12847 /* Fall through. */
12851 {
12853 }
12854 /* Fall through. */
12862 /* Should the interworking branches be listed here? */
12865 {
12868 {
12869 /* In shared libraries and relocatable executables,
12870 we treat local relative references as calls;
12871 see the related SYMBOL_CALLS_LOCAL code in
12872 allocate_dynrelocs. */
12875 }
12876 else
12877 /* We are creating a shared library or relocatable
12878 executable, and this is a reloc against a global symbol,
12879 or a non-PC-relative reloc against a local symbol.
12880 We may need to copy the reloc into the output. */
12882 }
12883 else
12887 /* This relocation describes the C++ object vtable hierarchy.
12888 Reconstruct it for later use during GC. */
12894 /* This relocation describes which C++ vtable entries are actually
12895 used. Record for later use during GC. */
12902 }
12905 {
12907 /* We may need a .plt entry if the function this reloc
12908 refers to is in a different object, regardless of the
12909 symbol's type. We can't tell for sure yet, because
12910 something later might force the symbol local. */
12913 /* If this reloc is in a read-only section, we might
12914 need a copy reloc. We can't check reliably at this
12915 stage whether the section is read-only, as input
12916 sections have not yet been mapped to output sections.
12917 Tentatively set the flag for now, and correct in
12918 adjust_dynamic_symbol. */
12920 }
12924 {
12930 {
12933 }
12934 else
12935 {
12941 }
12943 /* If the symbol is a function that doesn't bind locally,
12944 this relocation will need a PLT entry. */
12951 /* It's too early to use htab->use_blx here, so we have to
12952 record possible blx references separately from
12953 relocs that definitely need a thumb stub. */
12961 }
12964 {
12967 /* Create a reloc section in dynobj. */
12969 {
12970 sreloc = _bfd_elf_make_dynamic_reloc_section
12976 /* BPABI objects never have dynamic relocations mapped. */
12978 {
12979 flagword flags;
12984 }
12985 }
12987 /* If this is a global symbol, count the number of
12988 relocations we need for this symbol. */
12991 else
12992 {
12996 }
13000 {
13011 }
13016 }
13017 }
13020 }
13022 /* Unwinding tables are not referenced directly. This pass marks them as
13023 required if the corresponding code section is marked. */
13025 static bfd_boolean
13027 elf_gc_mark_hook_fn gc_mark_hook)
13028 {
13031 bfd_boolean again;
13035 /* Marking EH data may cause additional code sections to be marked,
13036 requiring multiple passes. */
13039 {
13042 {
13050 {
13059 {
13063 }
13064 }
13065 }
13066 }
13069 }
13071 /* Treat mapping symbols as special target symbols. */
13073 static bfd_boolean
13075 {
13077 BFD_ARM_SPECIAL_SYM_TYPE_ANY);
13078 }
13080 /* This is a copy of elf_find_function() from elf.c except that
13081 ARM mapping symbols are ignored when looking for function names
13082 and STT_ARM_TFUNC is considered to a function type. */
13084 static bfd_boolean
13088 bfd_vma offset,
13091 {
13098 {
13104 {
13113 /* Skip mapping symbols. */
13116 BFD_ARM_SPECIAL_SYM_TYPE_ANY))
13118 /* Fall through. */
13122 {
13125 }
13127 }
13128 }
13139 }
13142 /* Find the nearest line to a particular section and offset, for error
13143 reporting. This code is a duplicate of the code in elf.c, except
13144 that it uses arm_elf_find_function. */
13146 static bfd_boolean
13150 bfd_vma offset,
13155 {
13163 {
13167 functionname_ptr);
13170 }
13172 /* Skip _bfd_dwarf1_find_nearest_line since no known ARM toolchain
13173 uses DWARF1. */
13193 }
13195 static bfd_boolean
13200 {
13201 bfd_boolean found;
13206 }
13208 /* Adjust a symbol defined by a dynamic object and referenced by a
13209 regular object. The current definition is in some section of the
13210 dynamic object, but we're not including those sections. We have to
13211 change the definition to something the rest of the link can
13212 understand. */
13214 static bfd_boolean
13217 {
13229 /* Make sure we know what is going on here. */
13240 /* If this is a function, put it in the procedure linkage table. We
13241 will fill in the contents of the procedure linkage table later,
13242 when we know the address of the .got section. */
13244 {
13245 /* Calls to STT_GNU_IFUNC symbols always use a PLT, even if the
13246 symbol binds locally. */
13252 {
13253 /* This case can occur if we saw a PLT32 reloc in an input
13254 file, but the symbol was never referred to by a dynamic
13255 object, or if all references were garbage collected. In
13256 such a case, we don't actually need to build a procedure
13257 linkage table, and we can just do a PC24 reloc instead. */
13263 }
13266 }
13267 else
13268 {
13269 /* It's possible that we incorrectly decided a .plt reloc was
13270 needed for an R_ARM_PC24 or similar reloc to a non-function sym
13271 in check_relocs. We can't decide accurately between function
13272 and non-function syms in check-relocs; Objects loaded later in
13273 the link may change h->type. So fix it now. */
13278 }
13280 /* If this is a weak symbol, and there is a real definition, the
13281 processor independent code will have arranged for us to see the
13282 real definition first, and we can just use the same value. */
13284 {
13290 }
13292 /* If there are no non-GOT references, we do not need a copy
13293 relocation. */
13297 /* This is a reference to a symbol defined by a dynamic object which
13298 is not a function. */
13300 /* If we are creating a shared library, we must presume that the
13301 only references to the symbol are via the global offset table.
13302 For such cases we need not do anything here; the relocations will
13303 be handled correctly by relocate_section. Relocatable executables
13304 can reference data in shared objects directly, so we don't need to
13305 do anything here. */
13309 /* We must allocate the symbol in our .dynbss section, which will
13310 become part of the .bss section of the executable. There will be
13311 an entry for this symbol in the .dynsym section. The dynamic
13312 object will contain position independent code, so all references
13313 from the dynamic object to this symbol will go through the global
13314 offset table. The dynamic linker will use the .dynsym entry to
13315 determine the address it must put in the global offset table, so
13316 both the dynamic object and the regular object will refer to the
13317 same memory location for the variable. */
13321 /* We must generate a R_ARM_COPY reloc to tell the dynamic linker to
13322 copy the initial value out of the dynamic object and into the
13323 runtime process image. We need to remember the offset into the
13324 .rel(a).bss section we are going to use. */
13326 {
13332 }
13335 }
13337 /* Allocate space in .plt, .got and associated reloc sections for
13338 dynamic relocs. */
13340 static bfd_boolean
13342 {
13360 {
13361 /* Make sure this symbol is output as a dynamic symbol.
13362 Undefined weak syms won't yet be marked as dynamic. */
13365 {
13368 }
13370 /* If the call in the PLT entry binds locally, the associated
13371 GOT entry should use an R_ARM_IRELATIVE relocation instead of
13372 the usual R_ARM_JUMP_SLOT. Put it in the .iplt section rather
13373 than the .plt section. */
13375 {
13379 /* All non-call references can be resolved directly.
13380 This means that they can (and in some cases, must)
13381 resolve directly to the run-time target, rather than
13382 to the PLT. That in turns means that any .got entry
13383 would be equal to the .igot.plt entry, so there's
13384 no point having both. */
13386 }
13391 {
13394 /* If this symbol is not defined in a regular file, and we are
13395 not generating a shared library, then set the symbol to this
13396 location in the .plt. This is required to make function
13397 pointers compare as equal between the normal executable and
13398 the shared library. */
13401 {
13405 /* Make sure the function is not marked as Thumb, in case
13406 it is the target of an ABS32 relocation, which will
13407 point to the PLT entry. */
13409 }
13411 /* VxWorks executables have a second set of relocations for
13412 each PLT entry. They go in a separate relocation section,
13413 which is processed by the kernel loader. */
13415 {
13416 /* There is a relocation for the initial PLT entry:
13417 an R_ARM_32 relocation for _GLOBAL_OFFSET_TABLE_. */
13421 /* There are two extra relocations for each subsequent
13422 PLT entry: an R_ARM_32 relocation for the GOT entry,
13423 and an R_ARM_32 relocation for the PLT entry. */
13425 }
13426 }
13427 else
13428 {
13431 }
13432 }
13433 else
13434 {
13437 }
13443 {
13445 bfd_boolean dyn;
13449 /* Make sure this symbol is output as a dynamic symbol.
13450 Undefined weak syms won't yet be marked as dynamic. */
13453 {
13456 }
13459 {
13467 /* Non-TLS symbols need one GOT slot. */
13469 else
13470 {
13472 {
13473 /* R_ARM_TLS_DESC needs 2 GOT slots. */
13474 eh->tlsdesc_got
13479 /* plt.got_offset needs to know there's a TLS_DESC
13480 reloc in the middle of .got.plt. */
13482 }
13485 {
13486 /* R_ARM_TLS_GD32 needs 2 consecutive GOT slots. If
13487 the symbol is both GD and GDESC, got.offset may
13488 have been overwritten. */
13491 }
13494 /* R_ARM_TLS_IE32 needs one GOT slot. */
13496 }
13510 {
13518 {
13520 /* GDESC needs a trampoline to jump to. */
13522 }
13524 /* Only GD needs it. GDESC just emits one relocation per
13525 2 entries. */
13528 }
13530 {
13532 /* Reserve room for the GOT entry's R_ARM_GLOB_DAT relocation. */
13534 }
13537 /* No non-call references resolve the STT_GNU_IFUNC's PLT entry;
13538 they all resolve dynamically instead. Reserve room for the
13539 GOT entry's R_ARM_IRELATIVE relocation. */
13543 /* Reserve room for the GOT entry's R_ARM_RELATIVE relocation. */
13545 }
13546 }
13547 else
13550 /* Allocate stubs for exported Thumb functions on v4t. */
13555 {
13562 /* Create a new symbol to regist the real location of the function. */
13576 /* Point the symbol at the stub. */
13581 }
13586 /* In the shared -Bsymbolic case, discard space allocated for
13587 dynamic pc-relative relocs against symbols which turn out to be
13588 defined in regular objects. For the normal shared case, discard
13589 space for pc-relative relocs that have become local due to symbol
13590 visibility changes. */
13593 {
13594 /* Relocs that use pc_count are PC-relative forms, which will appear
13595 on something like ".long foo - ." or "movw REG, foo - .". We want
13596 calls to protected symbols to resolve directly to the function
13597 rather than going via the plt. If people want function pointer
13598 comparisons to work as expected then they should avoid writing
13599 assembly like ".long foo - .". */
13601 {
13605 {
13610 else
13612 }
13613 }
13616 {
13620 {
13623 else
13625 }
13626 }
13628 /* Also discard relocs on undefined weak syms with non-default
13629 visibility. */
13632 {
13636 /* Make sure undefined weak symbols are output as a dynamic
13637 symbol in PIEs. */
13640 {
13643 }
13644 }
13648 {
13649 /* Output absolute symbols so that we can create relocations
13650 against them. For normal symbols we output a relocation
13651 against the section that contains them. */
13654 }
13656 }
13657 else
13658 {
13659 /* For the non-shared case, discard space for relocs against
13660 symbols which turn out to need copy relocs or are not
13661 dynamic. */
13669 {
13670 /* Make sure this symbol is output as a dynamic symbol.
13671 Undefined weak syms won't yet be marked as dynamic. */
13674 {
13677 }
13679 /* If that succeeded, we know we'll be keeping all the
13680 relocs. */
13683 }
13687 keep: ;
13688 }
13690 /* Finally, allocate space. */
13692 {
13698 else
13700 }
13703 }
13705 /* Find any dynamic relocs that apply to read-only sections. */
13707 static bfd_boolean
13709 {
13715 {
13719 {
13724 /* Not an error, just cut short the traversal. */
13726 }
13727 }
13729 }
13731 void
13734 {
13742 }
13744 /* Set the sizes of the dynamic sections. */
13746 static bfd_boolean
13749 {
13752 bfd_boolean plt;
13753 bfd_boolean relocs;
13766 {
13767 /* Set the contents of the .interp section to the interpreter. */
13769 {
13774 }
13775 }
13777 /* Set up .got offsets for local syms, and space for local dynamic
13778 relocs. */
13780 {
13786 bfd_size_type locsymcount;
13796 {
13801 {
13804 {
13805 /* Input section has been discarded, either because
13806 it is a copy of a linkonce section or due to
13807 linker script /DISCARD/, so we'll be discarding
13808 the relocs too. */
13809 }
13813 {
13814 /* Relocations in vxworks .tls_vars sections are
13815 handled specially by the loader. */
13816 }
13818 {
13823 }
13824 }
13825 }
13843 {
13847 {
13851 {
13856 /* All references to the PLT are calls, so all
13857 non-call references can resolve directly to the
13858 run-time target. This means that the .got entry
13859 would be the same as the .igot.plt entry, so there's
13860 no point creating both. */
13862 }
13863 else
13864 {
13867 }
13870 {
13876 else
13878 }
13879 }
13881 {
13886 /* TLS_GD relocs need an 8-byte structure in the GOT. */
13889 {
13894 /* plt.got_offset needs to know there's a TLS_DESC
13895 reloc in the middle of .got.plt. */
13897 }
13902 {
13903 /* If the symbol is both GD and GDESC, *local_got
13904 may have been overwritten. */
13907 }
13913 /* If all references to an STT_GNU_IFUNC PLT are calls,
13914 then all non-call references, including this GOT entry,
13915 resolve directly to the run-time target. */
13921 {
13927 {
13931 }
13932 }
13933 }
13934 else
13936 }
13937 }
13940 {
13941 /* Allocate two GOT entries and one dynamic relocation (if necessary)
13942 for R_ARM_TLS_LDM32 relocations. */
13947 }
13948 else
13951 /* Allocate global sym .plt and .got entries, and space for global
13952 sym dynamic relocs. */
13955 /* Here we rummage through the found bfds to collect glue information. */
13957 {
13961 /* Initialise mapping tables for code/data. */
13966 /* xgettext:c-format */
13969 }
13971 /* Allocate space for the glue sections now that we've sized them. */
13974 /* For every jump slot reserved in the sgotplt, reloc_count is
13975 incremented. However, when we reserve space for TLS descriptors,
13976 it's not incremented, so in order to compute the space reserved
13977 for them, it suffices to multiply the reloc count by the jump
13978 slot size. */
13983 {
13990 /* If we're not using lazy TLS relocations, don't generate the
13991 PLT and GOT entries they require. */
13993 {
13999 }
14000 }
14002 /* The check_relocs and adjust_dynamic_symbol entry points have
14003 determined the sizes of the various dynamic sections. Allocate
14004 memory for them. */
14008 {
14014 /* It's OK to base decisions on the section name, because none
14015 of the dynobj section names depend upon the input files. */
14019 {
14020 /* Remember whether there is a PLT. */
14022 }
14024 {
14026 {
14027 /* Remember whether there are any reloc sections other
14028 than .rel(a).plt and .rela.plt.unloaded. */
14032 /* We use the reloc_count field as a counter if we need
14033 to copy relocs into the output file. */
14035 }
14036 }
14042 {
14043 /* It's not one of our sections, so don't allocate space. */
14045 }
14048 {
14049 /* If we don't need this section, strip it from the
14050 output file. This is mostly to handle .rel(a).bss and
14051 .rel(a).plt. We must create both sections in
14052 create_dynamic_sections, because they must be created
14053 before the linker maps input sections to output
14054 sections. The linker does that before
14055 adjust_dynamic_symbol is called, and it is that
14056 function which decides whether anything needs to go
14057 into these sections. */
14060 }
14065 /* Allocate memory for the section contents. */
14069 }
14072 {
14073 /* Add some entries to the .dynamic section. We fill in the
14074 values later, in elf32_arm_finish_dynamic_sections, but we
14075 must add the entries now so that we get the correct size for
14076 the .dynamic section. The DT_DEBUG entry is filled in by the
14077 dynamic linker and used by the debugger. */
14078 #define add_dynamic_entry(TAG, VAL) \
14079 _bfd_elf_add_dynamic_entry (info, TAG, VAL)
14082 {
14085 }
14088 {
14100 }
14103 {
14105 {
14110 }
14111 else
14112 {
14117 }
14118 }
14120 /* If any dynamic relocs apply to a read-only section,
14121 then we need a DT_TEXTREL entry. */
14124 info);
14127 {
14130 }
14134 }
14135 #undef add_dynamic_entry
14138 }
14140 /* Size sections even though they're not dynamic. We use it to setup
14141 _TLS_MODULE_BASE_, if needed. */
14143 static bfd_boolean
14146 {
14155 {
14158 tlsbase = elf_link_hash_lookup
14162 {
14178 }
14179 }
14181 }
14183 /* Finish up dynamic symbol handling. We set the contents of various
14184 dynamic sections here. */
14186 static bfd_boolean
14191 {
14202 {
14204 {
14209 }
14212 {
14213 /* Mark the symbol as undefined, rather than as defined in
14214 the .plt section. Leave the value alone. */
14216 /* If the symbol is weak, we do need to clear the value.
14217 Otherwise, the PLT entry would provide a definition for
14218 the symbol even if the symbol wasn't defined anywhere,
14219 and so the symbol would never be NULL. */
14222 }
14224 {
14225 /* At least one non-call relocation references this .iplt entry,
14226 so the .iplt entry is the function's canonical address. */
14234 }
14235 }
14238 {
14240 Elf_Internal_Rela rel;
14242 /* This symbol needs a copy reloc. Set it up. */
14256 }
14258 /* Mark _DYNAMIC and _GLOBAL_OFFSET_TABLE_ as absolute. On VxWorks,
14259 the _GLOBAL_OFFSET_TABLE_ symbol is not absolute: it is relative
14260 to the ".got" section. */
14266 }
14268 static void
14272 {
14276 {
14279 /* Emit mov pc,rx if bx is not permitted. */
14283 }
14284 }
14286 /* Install the special first PLT entry for elf32-arm-nacl. Unlike
14287 other variants, NaCl needs this entry in a static executable's
14288 .iplt too. When we're handling that case, GOT_DISPLACEMENT is
14289 zero. For .iplt really only the last bundle is useful, and .iplt
14290 could have a shorter first entry, with each individual PLT entry's
14291 relative branch calculated differently so it targets the last
14292 bundle instead of the instruction before it (labelled .Lplt_tail
14293 above). But it's simpler to keep the size and layout of PLT0
14294 consistent with the dynamic case, at the cost of some dead code at
14295 the start of .iplt and the one dead store to the stack at the start
14296 of .Lplt_tail. */
14297 static void
14300 {
14316 }
14318 /* Finish up the dynamic sections. */
14320 static bfd_boolean
14322 {
14335 /* A broken linker script might have discarded the dynamic sections.
14336 Catch this here so that we do not seg-fault later on. */
14342 {
14354 {
14355 Elf_Internal_Dyn dyn;
14362 {
14395 get_vma:
14398 {
14399 /* PR ld/14397: Issue an error message if a required section is missing. */
14404 }
14407 else
14408 /* In the BPABI, tags in the PT_DYNAMIC section point
14409 at the file offset, not the memory address, for the
14410 convenience of the post linker. */
14415 get_vma_if_bpabi:
14430 {
14431 /* My reading of the SVR4 ABI indicates that the
14432 procedure linkage table relocs (DT_JMPREL) should be
14433 included in the overall relocs (DT_REL). This is
14434 what Solaris does. However, UnixWare can not handle
14435 that case. Therefore, we override the DT_RELSZ entry
14436 here to make it not include the JMPREL relocs. Since
14437 the linker script arranges for .rel(a).plt to follow all
14438 other relocation sections, we don't have to worry
14439 about changing the DT_REL entry. */
14445 }
14446 /* Fall through. */
14450 /* In the BPABI, the DT_REL tag must point at the file
14451 offset, not the VMA, of the first relocation
14452 section. So, we use code similar to that in
14453 elflink.c, but do not check for SHF_ALLOC on the
14454 relcoation section, since relocations sections are
14455 never allocated under the BPABI. The comments above
14456 about Unixware notwithstanding, we include all of the
14457 relocations here. */
14459 {
14465 {
14466 Elf_Internal_Shdr *hdr
14469 {
14476 }
14477 }
14479 }
14496 /* Set the bottom bit of DT_INIT/FINI if the
14497 corresponding function is Thumb. */
14503 get_sym:
14504 /* If it wasn't set by elf_bfd_final_link
14505 then there is nothing to adjust. */
14507 {
14513 {
14516 }
14517 }
14519 }
14520 }
14522 /* Fill in the first entry in the procedure linkage table. */
14524 {
14528 /* Calculate the addresses of the GOT and PLT. */
14533 {
14534 /* The VxWorks GOT is relocated by the dynamic linker.
14535 Therefore, we must emit relocations rather than simply
14536 computing the values now. */
14537 Elf_Internal_Rela rel;
14548 /* Generate a relocation for _GLOBAL_OFFSET_TABLE_. */
14554 }
14559 {
14571 }
14572 else
14573 {
14586 #ifdef FOUR_WORD_PLT
14587 /* The displacement value goes in the otherwise-unused
14588 last word of the second entry. */
14590 #else
14592 #endif
14593 }
14594 }
14596 /* UnixWare sets the entsize of .plt to 4, although that doesn't
14597 really seem like the right value. */
14602 {
14603 bfd_vma got_address
14607 bfd_vma plt_address
14623 }
14626 {
14630 #ifdef FOUR_WORD_PLT
14633 #endif
14634 }
14637 {
14638 /* Correct the .rel(a).plt.unloaded relocations. They will have
14639 incorrect symbol indexes. */
14648 {
14649 Elf_Internal_Rela rel;
14660 }
14661 }
14662 }
14665 /* NaCl uses a special first entry in .iplt too. */
14668 /* Fill in the first three entries in the global offset table. */
14670 {
14672 {
14675 else
14681 }
14684 }
14687 }
14689 static void
14690 elf32_arm_post_process_headers (bfd * abfd, struct bfd_link_info * link_info ATTRIBUTE_UNUSED)
14691 {
14699 else
14704 {
14708 }
14712 {
14716 else
14718 }
14719 }
14721 static enum elf_reloc_type_class
14725 {
14727 {
14736 }
14737 }
14739 static void
14741 {
14743 }
14745 /* Return TRUE if this is an unwinding table entry. */
14747 static bfd_boolean
14749 {
14752 }
14755 /* Set the type and flags for an ARM section. We do this by
14756 the section name, which is a hack, but ought to work. */
14758 static bfd_boolean
14760 {
14766 {
14769 }
14771 }
14773 /* Handle an ARM specific section when reading an object file. This is
14774 called when bfd_section_from_shdr finds a section with an unknown
14775 type. */
14777 static bfd_boolean
14782 {
14783 /* There ought to be a place to keep ELF backend specific flags, but
14784 at the moment there isn't one. We just keep track of the
14785 sections by their name, instead. Fortunately, the ABI gives
14786 names for all the ARM specific sections, so we will probably get
14787 away with this. */
14789 {
14797 }
14803 }
14807 {
14810 else
14812 }
14815 {
14824 enum map_symbol_type
14825 {
14826 ARM_MAP_ARM,
14827 ARM_MAP_THUMB,
14828 ARM_MAP_DATA
14829 };
14832 /* Output a single mapping symbol. */
14834 static bfd_boolean
14837 bfd_vma offset)
14838 {
14840 Elf_Internal_Sym sym;
14852 }
14854 /* Output mapping symbols for the PLT entry described by ROOT_PLT and ARM_PLT.
14855 IS_IPLT_ENTRY_P says whether the PLT is in .iplt rather than .plt. */
14857 static bfd_boolean
14859 bfd_boolean is_iplt_entry_p,
14862 {
14874 {
14877 }
14878 else
14879 {
14882 }
14888 {
14893 }
14895 {
14904 }
14906 {
14909 }
14911 {
14914 }
14915 else
14916 {
14917 bfd_boolean thumb_stub_p;
14921 {
14924 }
14925 #ifdef FOUR_WORD_PLT
14930 #else
14931 /* A three-word PLT with no Thumb thunk contains only Arm code,
14932 so only need to output a mapping symbol for the first PLT entry and
14933 entries with thumb thunks. */
14935 {
14938 }
14939 #endif
14940 }
14943 }
14945 /* Output mapping symbols for PLT entries associated with H. */
14947 static bfd_boolean
14949 {
14957 /* When warning symbols are created, they **replace** the "real"
14958 entry in the hash table, thus we never get to see the real
14959 symbol in a hash traversal. So look at it now. */
14965 }
14967 /* Output a single local symbol for a generated stub. */
14969 static bfd_boolean
14972 {
14973 Elf_Internal_Sym sym;
14984 }
14986 static bfd_boolean
14989 {
14992 bfd_vma addr;
15001 /* Massage our args to the form they really have. */
15007 /* Ensure this stub is attached to the current section being
15008 processed. */
15017 {
15031 }
15036 {
15038 {
15055 }
15058 {
15062 }
15065 {
15082 }
15083 }
15086 }
15088 /* Output mapping symbols for linker generated sections,
15089 and for those data-only sections that do not have a
15090 $d. */
15092 static bfd_boolean
15097 Elf_Internal_Sym *,
15098 asection *,
15100 {
15101 output_arch_syminfo osi;
15103 bfd_vma offset;
15104 bfd_size_type size;
15117 /* Add a $d mapping symbol to data-only sections that
15118 don't have any mapping symbol. This may result in (harmless) redundant
15119 mapping symbols. */
15123 {
15128 {
15133 == SEC_HAS_CONTENTS
15138 {
15143 }
15144 }
15145 }
15147 /* ARM->Thumb glue. */
15149 {
15151 ARM2THUMB_GLUE_SECTION_NAME);
15160 else
15164 {
15167 }
15168 }
15170 /* Thumb->ARM glue. */
15172 {
15174 THUMB2ARM_GLUE_SECTION_NAME);
15181 {
15184 }
15185 }
15187 /* ARMv4 BX veneers. */
15189 {
15191 ARM_BX_GLUE_SECTION_NAME);
15197 }
15199 /* Long calls stubs. */
15201 {
15207 {
15208 /* Ignore non-stub sections. */
15218 }
15219 }
15221 /* Finally, output mapping symbols for the PLT. */
15223 {
15228 /* Output mapping symbols for the plt header. SymbianOS does not have a
15229 plt header. */
15231 {
15232 /* VxWorks shared libraries have no PLT header. */
15234 {
15239 }
15240 }
15242 {
15245 }
15247 {
15254 }
15256 {
15259 #ifndef FOUR_WORD_PLT
15262 #endif
15263 }
15264 }
15266 {
15267 /* NaCl uses a special first entry in .iplt too. */
15273 }
15276 {
15281 {
15287 {
15295 }
15296 }
15297 }
15299 {
15300 /* Mapping symbols for the lazy tls trampoline. */
15307 }
15309 {
15310 /* Mapping symbols for the tls trampoline. */
15313 #ifdef FOUR_WORD_PLT
15317 #endif
15318 }
15321 }
15323 /* Allocate target specific section data. */
15325 static bfd_boolean
15327 {
15329 {
15337 }
15340 }
15343 /* Used to order a list of mapping symbols by address. */
15345 static int
15347 {
15356 /* Ensure results do not depend on the host qsort for objects with
15357 multiple mapping symbols at the same address by sorting on type
15358 after vma. */
15362 else
15364 }
15366 /* Add OFFSET to lower 31 bits of ADDR, leaving other bits unmodified. */
15368 static unsigned long
15370 {
15372 }
15374 /* Copy an .ARM.exidx table entry, adding OFFSET to (applied) PREL31
15375 relocations. */
15377 static void
15379 {
15383 /* High bit of first word is supposed to be zero. */
15387 /* If the high bit of the first word is clear, and the bit pattern is not 0x1
15388 (EXIDX_CANTUNWIND), this is an offset to an .ARM.extab entry. */
15394 }
15396 /* Data for make_branch_to_a8_stub(). */
15398 struct a8_branch_to_stub_data
15399 {
15402 };
15405 /* Helper to insert branches to Cortex-A8 erratum stubs in the right
15406 places for a particular section. */
15408 static bfd_boolean
15411 {
15417 bfd_signed_vma branch_offset;
15446 /* We attempt to avoid this condition by setting stubs_always_after_branch
15447 in elf32_arm_size_stubs if we've enabled the Cortex-A8 erratum workaround.
15448 This check is just to be on the safe side... */
15450 {
15454 }
15457 {
15468 {
15473 jump24:
15475 {
15476 /* There's not much we can do apart from complain if this
15477 happens. */
15481 }
15483 /* i1 = not(j1 eor s), so:
15484 not i1 = j1 eor s
15485 j1 = (not i1) eor s. */
15497 }
15503 }
15509 }
15511 /* Do code byteswapping. Return FALSE afterwards so that the section is
15512 written out as normal. */
15514 static bfd_boolean
15519 {
15525 bfd_vma ptr;
15526 bfd_vma end;
15528 bfd_byte tmp;
15534 /* If this section has not been allocated an _arm_elf_section_data
15535 structure then we cannot record anything. */
15545 {
15550 {
15554 {
15556 {
15557 bfd_vma branch_to_veneer;
15558 /* Original condition code of instruction, plus bit mask for
15559 ARM B instruction. */
15563 /* The instruction is before the label. */
15566 /* Above offset included in -4 below. */
15580 }
15584 {
15585 bfd_vma branch_from_veneer;
15588 /* Take size of veneer into account. */
15597 /* Original instruction. */
15604 /* Branch back to insn after original insn. */
15610 }
15615 }
15616 }
15617 }
15620 {
15621 arm_unwind_table_edit *edit_node
15623 /* Now, sec->size is the size of the section we will write. The original
15624 size (before we merged duplicate entries and inserted EXIDX_CANTUNWIND
15625 markers) was sec->rawsize. (This isn't the case if we perform no
15626 edits, then rawsize will be zero and we should use size). */
15633 {
15635 {
15639 {
15642 out_index++;
15643 in_index++;
15644 }
15648 {
15650 {
15652 in_index++;
15657 {
15665 /* Note: this is meant to be equivalent to an
15666 R_ARM_PREL31 relocation. These synthetic
15667 EXIDX_CANTUNWIND markers are not relocated by the
15668 usual BFD method. */
15672 /* First address we can't unwind. */
15676 /* Code for EXIDX_CANTUNWIND. */
15680 out_index++;
15682 }
15684 }
15687 }
15688 }
15689 else
15690 {
15691 /* No more edits, copy remaining entries verbatim. */
15694 out_index++;
15695 in_index++;
15696 }
15697 }
15701 edited_contents,
15705 }
15707 /* Fix code to point to Cortex-A8 erratum stubs. */
15709 {
15717 }
15723 {
15728 {
15731 else
15735 {
15737 /* Byte swap code words. */
15739 {
15747 }
15751 /* Byte swap code halfwords. */
15753 {
15758 }
15762 /* Leave data alone. */
15764 }
15766 }
15767 }
15775 }
15777 /* Mangle thumb function symbols as we read them in. */
15779 static bfd_boolean
15784 {
15788 /* New EABI objects mark thumb function symbols by setting the low bit of
15789 the address. */
15792 {
15794 {
15797 }
15798 else
15800 }
15802 {
15805 }
15808 else
15812 }
15815 /* Mangle thumb function symbols as we write them out. */
15817 static void
15822 {
15823 Elf_Internal_Sym newsym;
15825 /* We convert STT_ARM_TFUNC symbols into STT_FUNC with the low bit
15826 of the address set, as per the new EABI. We do this unconditionally
15827 because objcopy does not set the elf header flags until after
15828 it writes out the symbol table. */
15830 {
15835 {
15836 /* Do this only for defined symbols. At link type, the static
15837 linker will simulate the work of dynamic linker of resolving
15838 symbols and will carry over the thumbness of found symbols to
15839 the output symbol table. It's not clear how it happens, but
15840 the thumbness of undefined symbols can well be different at
15841 runtime, and writing '1' for them will be confusing for users
15842 and possibly for dynamic linker itself.
15843 */
15845 }
15848 }
15850 }
15852 /* Add the PT_ARM_EXIDX program header. */
15854 static bfd_boolean
15857 {
15863 {
15864 /* If there is already a PT_ARM_EXIDX header, then we do not
15865 want to add another one. This situation arises when running
15866 "strip"; the input binary already has the header. */
15871 {
15882 }
15883 }
15886 }
15888 /* We may add a PT_ARM_EXIDX program header. */
15890 static int
15893 {
15899 else
15901 }
15903 /* Hook called by the linker routine which adds symbols from an object
15904 file. */
15906 static bfd_boolean
15910 {
15926 }
15928 /* We use this to override swap_symbol_in and swap_symbol_out. */
15930 {
15943 bfd_elf32_write_out_phdrs,
15944 bfd_elf32_write_shdrs_and_ehdr,
15945 bfd_elf32_checksum_contents,
15946 bfd_elf32_write_relocs,
15947 elf32_arm_swap_symbol_in,
15948 elf32_arm_swap_symbol_out,
15949 bfd_elf32_slurp_reloc_table,
15950 bfd_elf32_slurp_symbol_table,
15951 bfd_elf32_swap_dyn_in,
15952 bfd_elf32_swap_dyn_out,
15953 bfd_elf32_swap_reloc_in,
15954 bfd_elf32_swap_reloc_out,
15955 bfd_elf32_swap_reloca_in,
15956 bfd_elf32_swap_reloca_out
15957 };
15959 static bfd_vma
15961 {
15962 /* V7 BE8 code is always little endian. */
15967 }
15969 static bfd_vma
15971 {
15972 /* V7 BE8 code is always little endian. */
15977 }
15979 /* Return size of plt0 entry starting at ADDR
15980 or (bfd_vma) -1 if size can not be determined. */
15982 static bfd_vma
15984 {
15985 bfd_vma first_word;
15986 bfd_vma plt0_size;
15994 else
15995 /* We don't yet handle this PLT format. */
15999 }
16001 /* Return size of plt entry starting at offset OFFSET
16002 of plt section located at address START
16003 or (bfd_vma) -1 if size can not be determined. */
16005 static bfd_vma
16007 {
16008 bfd_vma first_insn;
16012 /* PLT entry size if fixed on Thumb-only platforms. */
16016 /* Respect Thumb stub if necessary. */
16018 {
16020 }
16022 /* Strip immediate from first add. */
16025 #ifdef FOUR_WORD_PLT
16028 #else
16033 #endif
16034 else
16035 /* We don't yet handle this PLT format. */
16039 }
16041 /* Implementation is shamelessly borrowed from _bfd_elf_get_synthetic_symtab. */
16043 static long
16050 {
16059 bfd_vma offset;
16088 {
16092 }
16098 {
16102 }
16116 {
16124 /* Undefined syms won't have BSF_LOCAL or BSF_GLOBAL set. Since
16125 we are defining a symbol, ensure one of them is set. */
16137 {
16144 ;
16148 }
16153 }
16156 }
16158 #define ELF_ARCH bfd_arch_arm
16159 #define ELF_TARGET_ID ARM_ELF_DATA
16160 #define ELF_MACHINE_CODE EM_ARM
16161 #ifdef __QNXTARGET__
16162 #define ELF_MAXPAGESIZE 0x1000
16163 #else
16164 #define ELF_MAXPAGESIZE 0x10000
16165 #endif
16166 #define ELF_MINPAGESIZE 0x1000
16167 #define ELF_COMMONPAGESIZE 0x1000
16169 #define bfd_elf32_mkobject elf32_arm_mkobject
16171 #define bfd_elf32_bfd_copy_private_bfd_data elf32_arm_copy_private_bfd_data
16172 #define bfd_elf32_bfd_merge_private_bfd_data elf32_arm_merge_private_bfd_data
16173 #define bfd_elf32_bfd_set_private_flags elf32_arm_set_private_flags
16174 #define bfd_elf32_bfd_print_private_bfd_data elf32_arm_print_private_bfd_data
16175 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_link_hash_table_create
16176 #define bfd_elf32_bfd_reloc_type_lookup elf32_arm_reloc_type_lookup
16177 #define bfd_elf32_bfd_reloc_name_lookup elf32_arm_reloc_name_lookup
16178 #define bfd_elf32_find_nearest_line elf32_arm_find_nearest_line
16179 #define bfd_elf32_find_inliner_info elf32_arm_find_inliner_info
16180 #define bfd_elf32_new_section_hook elf32_arm_new_section_hook
16181 #define bfd_elf32_bfd_is_target_special_symbol elf32_arm_is_target_special_symbol
16182 #define bfd_elf32_bfd_final_link elf32_arm_final_link
16183 #define bfd_elf32_get_synthetic_symtab elf32_arm_get_synthetic_symtab
16185 #define elf_backend_get_symbol_type elf32_arm_get_symbol_type
16186 #define elf_backend_gc_mark_hook elf32_arm_gc_mark_hook
16187 #define elf_backend_gc_mark_extra_sections elf32_arm_gc_mark_extra_sections
16188 #define elf_backend_gc_sweep_hook elf32_arm_gc_sweep_hook
16189 #define elf_backend_check_relocs elf32_arm_check_relocs
16190 #define elf_backend_relocate_section elf32_arm_relocate_section
16191 #define elf_backend_write_section elf32_arm_write_section
16192 #define elf_backend_adjust_dynamic_symbol elf32_arm_adjust_dynamic_symbol
16193 #define elf_backend_create_dynamic_sections elf32_arm_create_dynamic_sections
16194 #define elf_backend_finish_dynamic_symbol elf32_arm_finish_dynamic_symbol
16195 #define elf_backend_finish_dynamic_sections elf32_arm_finish_dynamic_sections
16196 #define elf_backend_size_dynamic_sections elf32_arm_size_dynamic_sections
16197 #define elf_backend_always_size_sections elf32_arm_always_size_sections
16198 #define elf_backend_init_index_section _bfd_elf_init_2_index_sections
16199 #define elf_backend_post_process_headers elf32_arm_post_process_headers
16200 #define elf_backend_reloc_type_class elf32_arm_reloc_type_class
16201 #define elf_backend_object_p elf32_arm_object_p
16202 #define elf_backend_fake_sections elf32_arm_fake_sections
16203 #define elf_backend_section_from_shdr elf32_arm_section_from_shdr
16204 #define elf_backend_final_write_processing elf32_arm_final_write_processing
16205 #define elf_backend_copy_indirect_symbol elf32_arm_copy_indirect_symbol
16206 #define elf_backend_size_info elf32_arm_size_info
16207 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
16208 #define elf_backend_additional_program_headers elf32_arm_additional_program_headers
16209 #define elf_backend_output_arch_local_syms elf32_arm_output_arch_local_syms
16210 #define elf_backend_begin_write_processing elf32_arm_begin_write_processing
16211 #define elf_backend_add_symbol_hook elf32_arm_add_symbol_hook
16213 #define elf_backend_can_refcount 1
16214 #define elf_backend_can_gc_sections 1
16215 #define elf_backend_plt_readonly 1
16216 #define elf_backend_want_got_plt 1
16217 #define elf_backend_want_plt_sym 0
16218 #define elf_backend_may_use_rel_p 1
16219 #define elf_backend_may_use_rela_p 0
16220 #define elf_backend_default_use_rela_p 0
16222 #define elf_backend_got_header_size 12
16224 #undef elf_backend_obj_attrs_vendor
16226 #undef elf_backend_obj_attrs_section
16228 #undef elf_backend_obj_attrs_arg_type
16229 #define elf_backend_obj_attrs_arg_type elf32_arm_obj_attrs_arg_type
16230 #undef elf_backend_obj_attrs_section_type
16231 #define elf_backend_obj_attrs_section_type SHT_ARM_ATTRIBUTES
16232 #define elf_backend_obj_attrs_order elf32_arm_obj_attrs_order
16233 #define elf_backend_obj_attrs_handle_unknown elf32_arm_obj_attrs_handle_unknown
16237 /* Native Client targets. */
16239 #undef TARGET_LITTLE_SYM
16240 #define TARGET_LITTLE_SYM arm_elf32_nacl_le_vec
16241 #undef TARGET_LITTLE_NAME
16243 #undef TARGET_BIG_SYM
16244 #define TARGET_BIG_SYM arm_elf32_nacl_be_vec
16245 #undef TARGET_BIG_NAME
16248 /* Like elf32_arm_link_hash_table_create -- but overrides
16249 appropriately for NaCl. */
16253 {
16258 {
16266 }
16268 }
16270 /* Since NaCl doesn't use the ARM-specific unwind format, we don't
16271 really need to use elf32_arm_modify_segment_map. But we do it
16272 anyway just to reduce gratuitous differences with the stock ARM backend. */
16274 static bfd_boolean
16276 {
16279 }
16281 static void
16283 {
16286 }
16288 static bfd_vma
16291 {
16295 }
16297 #undef elf32_bed
16298 #define elf32_bed elf32_arm_nacl_bed
16299 #undef bfd_elf32_bfd_link_hash_table_create
16300 #define bfd_elf32_bfd_link_hash_table_create \
16301 elf32_arm_nacl_link_hash_table_create
16302 #undef elf_backend_plt_alignment
16303 #define elf_backend_plt_alignment 4
16304 #undef elf_backend_modify_segment_map
16305 #define elf_backend_modify_segment_map elf32_arm_nacl_modify_segment_map
16306 #undef elf_backend_modify_program_headers
16307 #define elf_backend_modify_program_headers nacl_modify_program_headers
16308 #undef elf_backend_final_write_processing
16309 #define elf_backend_final_write_processing elf32_arm_nacl_final_write_processing
16310 #undef bfd_elf32_get_synthetic_symtab
16311 #undef elf_backend_plt_sym_val
16312 #define elf_backend_plt_sym_val elf32_arm_nacl_plt_sym_val
16314 #undef ELF_MINPAGESIZE
16315 #undef ELF_COMMONPAGESIZE
16320 /* Reset to defaults. */
16321 #undef elf_backend_plt_alignment
16322 #undef elf_backend_modify_segment_map
16323 #define elf_backend_modify_segment_map elf32_arm_modify_segment_map
16324 #undef elf_backend_modify_program_headers
16325 #undef elf_backend_final_write_processing
16326 #define elf_backend_final_write_processing elf32_arm_final_write_processing
16327 #undef ELF_MINPAGESIZE
16328 #define ELF_MINPAGESIZE 0x1000
16329 #undef ELF_COMMONPAGESIZE
16330 #define ELF_COMMONPAGESIZE 0x1000
16333 /* VxWorks Targets. */
16335 #undef TARGET_LITTLE_SYM
16336 #define TARGET_LITTLE_SYM arm_elf32_vxworks_le_vec
16337 #undef TARGET_LITTLE_NAME
16339 #undef TARGET_BIG_SYM
16340 #define TARGET_BIG_SYM arm_elf32_vxworks_be_vec
16341 #undef TARGET_BIG_NAME
16344 /* Like elf32_arm_link_hash_table_create -- but overrides
16345 appropriately for VxWorks. */
16349 {
16354 {
16359 }
16361 }
16363 static void
16365 {
16368 }
16370 #undef elf32_bed
16371 #define elf32_bed elf32_arm_vxworks_bed
16373 #undef bfd_elf32_bfd_link_hash_table_create
16374 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_vxworks_link_hash_table_create
16375 #undef elf_backend_final_write_processing
16376 #define elf_backend_final_write_processing elf32_arm_vxworks_final_write_processing
16377 #undef elf_backend_emit_relocs
16378 #define elf_backend_emit_relocs elf_vxworks_emit_relocs
16380 #undef elf_backend_may_use_rel_p
16381 #define elf_backend_may_use_rel_p 0
16382 #undef elf_backend_may_use_rela_p
16383 #define elf_backend_may_use_rela_p 1
16384 #undef elf_backend_default_use_rela_p
16385 #define elf_backend_default_use_rela_p 1
16386 #undef elf_backend_want_plt_sym
16387 #define elf_backend_want_plt_sym 1
16388 #undef ELF_MAXPAGESIZE
16389 #define ELF_MAXPAGESIZE 0x1000
16394 /* Merge backend specific data from an object file to the output
16395 object file when linking. */
16397 static bfd_boolean
16399 {
16400 flagword out_flags;
16401 flagword in_flags;
16405 /* Check if we have the same endianness. */
16415 /* The input BFD must have had its flags initialised. */
16416 /* The following seems bogus to me -- The flags are initialized in
16417 the assembler but I don't think an elf_flags_init field is
16418 written into the object. */
16419 /* BFD_ASSERT (elf_flags_init (ibfd)); */
16424 /* In theory there is no reason why we couldn't handle this. However
16425 in practice it isn't even close to working and there is no real
16426 reason to want it. */
16430 {
16432 ibfd);
16434 }
16437 {
16438 /* If the input is the default architecture and had the default
16439 flags then do not bother setting the flags for the output
16440 architecture, instead allow future merges to do this. If no
16441 future merges ever set these flags then they will retain their
16442 uninitialised values, which surprise surprise, correspond
16443 to the default values. */
16456 }
16458 /* Determine what should happen if the input ARM architecture
16459 does not match the output ARM architecture. */
16463 /* Identical flags must be compatible. */
16467 /* Check to see if the input BFD actually contains any sections. If
16468 not, its flags may not have been initialised either, but it
16469 cannot actually cause any incompatiblity. Do not short-circuit
16470 dynamic objects; their section list may be emptied by
16471 elf_link_add_object_symbols.
16473 Also check to see if there are no code sections in the input.
16474 In this case there is no need to check for code specific flags.
16475 XXX - do we need to worry about floating-point format compatability
16476 in data sections ? */
16478 {
16483 {
16484 /* Ignore synthetic glue sections. */
16487 {
16495 }
16496 }
16500 }
16502 /* Complain about various flag mismatches. */
16505 {
16506 _bfd_error_handler
16512 }
16514 /* Not sure what needs to be checked for EABI versions >= 1. */
16515 /* VxWorks libraries do not use these flags. */
16519 {
16521 {
16522 _bfd_error_handler
16528 }
16531 {
16533 _bfd_error_handler
16534 (_("error: %B passes floats in float registers, whereas %B passes them in integer registers"),
16536 else
16537 _bfd_error_handler
16538 (_("error: %B passes floats in integer registers, whereas %B passes them in float registers"),
16542 }
16545 {
16547 _bfd_error_handler
16550 else
16551 _bfd_error_handler
16556 }
16559 {
16561 _bfd_error_handler
16564 else
16565 _bfd_error_handler
16570 }
16572 #ifdef EF_ARM_SOFT_FLOAT
16574 {
16575 /* We can allow interworking between code that is VFP format
16576 layout, and uses either soft float or integer regs for
16577 passing floating point arguments and results. We already
16578 know that the APCS_FLOAT flags match; similarly for VFP
16579 flags. */
16582 {
16584 _bfd_error_handler
16587 else
16588 _bfd_error_handler
16593 }
16594 }
16595 #endif
16597 /* Interworking mismatch is only a warning. */
16599 {
16601 {
16602 _bfd_error_handler
16605 }
16606 else
16607 {
16608 _bfd_error_handler
16611 }
16612 }
16613 }
16616 }
16619 /* Symbian OS Targets. */
16621 #undef TARGET_LITTLE_SYM
16622 #define TARGET_LITTLE_SYM arm_elf32_symbian_le_vec
16623 #undef TARGET_LITTLE_NAME
16625 #undef TARGET_BIG_SYM
16626 #define TARGET_BIG_SYM arm_elf32_symbian_be_vec
16627 #undef TARGET_BIG_NAME
16630 /* Like elf32_arm_link_hash_table_create -- but overrides
16631 appropriately for Symbian OS. */
16635 {
16640 {
16643 /* There is no PLT header for Symbian OS. */
16645 /* The PLT entries are each one instruction and one word. */
16648 /* Symbian uses armv5t or above, so use_blx is always true. */
16651 }
16653 }
16655 static const struct bfd_elf_special_section
16656 elf32_arm_symbian_special_sections[] =
16657 {
16658 /* In a BPABI executable, the dynamic linking sections do not go in
16659 the loadable read-only segment. The post-linker may wish to
16660 refer to these sections, but they are not part of the final
16661 program image. */
16667 /* These sections do not need to be writable as the SymbianOS
16668 postlinker will arrange things so that no dynamic relocation is
16669 required. */
16674 };
16676 static void
16679 {
16680 /* BPABI objects are never loaded directly by an OS kernel; they are
16681 processed by a postlinker first, into an OS-specific format. If
16682 the D_PAGED bit is set on the file, BFD will align segments on
16683 page boundaries, so that an OS can directly map the file. With
16684 BPABI objects, that just results in wasted space. In addition,
16685 because we clear the D_PAGED bit, map_sections_to_segments will
16686 recognize that the program headers should not be mapped into any
16687 loadable segment. */
16690 }
16692 static bfd_boolean
16695 {
16699 /* BPABI shared libraries and executables should have a PT_DYNAMIC
16700 segment. However, because the .dynamic section is not marked
16701 with SEC_LOAD, the generic ELF code will not create such a
16702 segment. */
16705 {
16711 {
16715 }
16716 }
16718 /* Also call the generic arm routine. */
16720 }
16722 /* Return address for Ith PLT stub in section PLT, for relocation REL
16723 or (bfd_vma) -1 if it should not be included. */
16725 static bfd_vma
16728 {
16730 }
16733 #undef elf32_bed
16734 #define elf32_bed elf32_arm_symbian_bed
16736 /* The dynamic sections are not allocated on SymbianOS; the postlinker
16737 will process them and then discard them. */
16738 #undef ELF_DYNAMIC_SEC_FLAGS
16739 #define ELF_DYNAMIC_SEC_FLAGS \
16740 (SEC_HAS_CONTENTS | SEC_IN_MEMORY | SEC_LINKER_CREATED)
16742 #undef elf_backend_emit_relocs
16744 #undef bfd_elf32_bfd_link_hash_table_create
16745 #define bfd_elf32_bfd_link_hash_table_create elf32_arm_symbian_link_hash_table_create
16746 #undef elf_backend_special_sections
16747 #define elf_backend_special_sections elf32_arm_symbian_special_sections
16748 #undef elf_backend_begin_write_processing
16749 #define elf_backend_begin_write_processing elf32_arm_symbian_begin_write_processing
16750 #undef elf_backend_final_write_processing
16751 #define elf_backend_final_write_processing elf32_arm_final_write_processing
16753 #undef elf_backend_modify_segment_map
16754 #define elf_backend_modify_segment_map elf32_arm_symbian_modify_segment_map
16756 /* There is no .got section for BPABI objects, and hence no header. */
16757 #undef elf_backend_got_header_size
16758 #define elf_backend_got_header_size 0
16760 /* Similarly, there is no .got.plt section. */
16761 #undef elf_backend_want_got_plt
16762 #define elf_backend_want_got_plt 0
16764 #undef elf_backend_plt_sym_val
16765 #define elf_backend_plt_sym_val elf32_arm_symbian_plt_sym_val
16767 #undef elf_backend_may_use_rel_p
16768 #define elf_backend_may_use_rel_p 1
16769 #undef elf_backend_may_use_rela_p
16770 #define elf_backend_may_use_rela_p 0
16771 #undef elf_backend_default_use_rela_p
16772 #define elf_backend_default_use_rela_p 0
16773 #undef elf_backend_want_plt_sym
16774 #define elf_backend_want_plt_sym 0
16775 #undef ELF_MAXPAGESIZE
16776 #define ELF_MAXPAGESIZE 0x8000