gdb/s12z-tdep.c

   1 /* Target-dependent code for the S12Z, for the GDB.
   2    Copyright (C) 2018-2024 Free Software Foundation, Inc.
   3
   4    This file is part of GDB.
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3 of the License, or
   9    (at your option) any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 /* Much of this file is shamelessly copied from or1k-tdep.c and others.  */
  20
  21 #include "defs.h"
  22
  23 #include "arch-utils.h"
  24 #include "dwarf2/frame.h"
  25 #include "gdbsupport/errors.h"
  26 #include "frame-unwind.h"
  27 #include "gdbcore.h"
  28 #include "gdbcmd.h"
  29 #include "inferior.h"
  30 #include "opcode/s12z.h"
  31 #include "trad-frame.h"
  32 #include "remote.h"
  33 #include "opcodes/s12z-opc.h"
  34 #include "gdbarch.h"
  35 #include "disasm.h"
  36
  37 /* Two of the registers included in S12Z_N_REGISTERS are
  38    the CCH and CCL "registers" which are just views into
  39    the CCW register.  */
  40 #define N_PHYSICAL_REGISTERS (S12Z_N_REGISTERS - 2)
  41
  42
  43 /*  A permutation of all the physical registers.   Indexing this array
  44     with an integer from gdb's internal representation will return the
  45     register enum.  */
  46 static const int reg_perm[N_PHYSICAL_REGISTERS] =
  47   {
  48    REG_D0,
  49    REG_D1,
  50    REG_D2,
  51    REG_D3,
  52    REG_D4,
  53    REG_D5,
  54    REG_D6,
  55    REG_D7,
  56    REG_X,
  57    REG_Y,
  58    REG_S,
  59    REG_P,
  60    REG_CCW
  61   };
  62
  63 /*  The inverse of the above permutation.  Indexing this
  64     array with a register enum (e.g. REG_D2) will return the register
  65     number in gdb's internal representation.  */
  66 static const int inv_reg_perm[N_PHYSICAL_REGISTERS] =
  67   {
  68    2, 3, 4, 5,      /* d2, d3, d4, d5 */
  69    0, 1,            /* d0, d1 */
  70    6, 7,            /* d6, d7 */
  71    8, 9, 10, 11, 12 /* x, y, s, p, ccw */
  72   };
  73
  74 /*  Return the name of the register REGNUM.  */
  75 static const char *
  76 s12z_register_name (struct gdbarch *gdbarch, int regnum)
  77 {
  78   /*  Registers is declared in opcodes/s12z.h.   */
  79   return registers[reg_perm[regnum]].name;
  80 }
  81
  82 static CORE_ADDR
  83 s12z_skip_prologue (struct gdbarch *gdbarch, CORE_ADDR pc)
  84 {
  85   CORE_ADDR start_pc = 0;
  86
  87   if (find_pc_partial_function (pc, NULL, &start_pc, NULL))
  88     {
  89       CORE_ADDR prologue_end = skip_prologue_using_sal (gdbarch, pc);
  90
  91       if (prologue_end != 0)
  92         return prologue_end;
  93     }
  94
  95   warning (_("%s Failed to find end of prologue PC = %08x"),
  96            __FUNCTION__, (unsigned int) pc);
  97
  98   return pc;
  99 }
 100
 101 static struct type *
 102 s12z_register_type (struct gdbarch *gdbarch, int reg_nr)
 103 {
 104   switch (registers[reg_perm[reg_nr]].bytes)
 105     {
 106     case 1:
 107       return builtin_type (gdbarch)->builtin_uint8;
 108     case 2:
 109       return builtin_type (gdbarch)->builtin_uint16;
 110     case 3:
 111       return builtin_type (gdbarch)->builtin_uint24;
 112     case 4:
 113       return builtin_type (gdbarch)->builtin_uint32;
 114     default:
 115       return builtin_type (gdbarch)->builtin_uint32;
 116     }
 117   return builtin_type (gdbarch)->builtin_int0;
 118 }
 119
 120
 121 static int
 122 s12z_dwarf_reg_to_regnum (struct gdbarch *gdbarch, int num)
 123 {
 124   switch (num)
 125     {
 126     case 15:      return REG_S;
 127     case 7:       return REG_X;
 128     case 8:       return REG_Y;
 129     case 42:      return REG_D0;
 130     case 43:      return REG_D1;
 131     case 44:      return REG_D2;
 132     case 45:      return REG_D3;
 133     case 46:      return REG_D4;
 134     case 47:      return REG_D5;
 135     case 48:      return REG_D6;
 136     case 49:      return REG_D7;
 137     }
 138   return -1;
 139 }
 140
 141
 142 /* Support functions for frame handling.  */
 143
 144 /* A struct (based on mem_read_abstraction_base) to read memory
 145    through the disassemble_info API.  */
 146 struct mem_read_abstraction
 147 {
 148   struct mem_read_abstraction_base base; /* The parent struct.  */
 149   bfd_vma memaddr;                  /* Where to read from.  */
 150   struct disassemble_info* info;  /* The disassembler  to use for reading.  */
 151 };
 152
 153 /* Advance the reader by one byte.  */
 154 static void
 155 advance (struct mem_read_abstraction_base *b)
 156 {
 157   struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b;
 158   mra->memaddr++;
 159 }
 160
 161 /* Return the current position of the reader.  */
 162 static bfd_vma
 163 posn (struct mem_read_abstraction_base *b)
 164 {
 165   struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b;
 166   return mra->memaddr;
 167 }
 168
 169 /* Read the N bytes at OFFSET  using B.  The bytes read are stored in BYTES.
 170    It is the caller's responsibility to ensure that this is of at least N
 171    in size.  */
 172 static int
 173 abstract_read_memory (struct mem_read_abstraction_base *b,
 174                       int offset,
 175                       size_t n, bfd_byte *bytes)
 176 {
 177   struct mem_read_abstraction *mra = (struct mem_read_abstraction *) b;
 178
 179   int status =
 180     (*mra->info->read_memory_func) (mra->memaddr + offset,
 181                                     bytes, n, mra->info);
 182
 183   if (status != 0)
 184     {
 185       (*mra->info->memory_error_func) (status, mra->memaddr, mra->info);
 186       return -1;
 187     }
 188
 189   return 0;
 190 }
 191
 192
 193 /* Return the stack adjustment caused by a push or pull instruction.  */
 194 static int
 195 push_pull_get_stack_adjustment (int n_operands,
 196                                 struct operand *const *operands)
 197 {
 198   int stack_adjustment = 0;
 199   gdb_assert (n_operands > 0);
 200   if (operands[0]->cl == OPND_CL_REGISTER_ALL)
 201     stack_adjustment = 26;  /* All the regs are involved.  */
 202   else if (operands[0]->cl == OPND_CL_REGISTER_ALL16)
 203     stack_adjustment = 4 * 2; /* All four 16 bit regs are involved.  */
 204   else
 205     for (int i = 0; i < n_operands; ++i)
 206       {
 207         if (operands[i]->cl != OPND_CL_REGISTER)
 208           continue; /* I don't think this can ever happen.  */
 209         const struct register_operand *op
 210           = (const struct register_operand *) operands[i];
 211         switch (op->reg)
 212           {
 213           case REG_X:
 214           case REG_Y:
 215             stack_adjustment += 3;
 216             break;
 217           case REG_D7:
 218           case REG_D6:
 219             stack_adjustment += 4;
 220             break;
 221           case REG_D2:
 222           case REG_D3:
 223           case REG_D4:
 224           case REG_D5:
 225             stack_adjustment += 2;
 226             break;
 227           case REG_D0:
 228           case REG_D1:
 229           case REG_CCL:
 230           case REG_CCH:
 231             stack_adjustment += 1;
 232             break;
 233           default:
 234             gdb_assert_not_reached ("Invalid register in push/pull operation.");
 235             break;
 236           }
 237       }
 238   return stack_adjustment;
 239 }
 240
 241 /* Initialize a prologue cache.  */
 242
 243 static struct trad_frame_cache *
 244 s12z_frame_cache (const frame_info_ptr &this_frame, void **prologue_cache)
 245 {
 246   struct trad_frame_cache *info;
 247
 248   CORE_ADDR this_sp;
 249   CORE_ADDR this_sp_for_id;
 250
 251   CORE_ADDR start_addr;
 252   CORE_ADDR end_addr;
 253
 254   /* Nothing to do if we already have this info.  */
 255   if (NULL != *prologue_cache)
 256     return (struct trad_frame_cache *) *prologue_cache;
 257
 258   /* Get a new prologue cache and populate it with default values.  */
 259   info = trad_frame_cache_zalloc (this_frame);
 260   *prologue_cache = info;
 261
 262   /* Find the start address of this function (which is a normal frame, even
 263      if the next frame is the sentinel frame) and the end of its prologue.  */
 264   CORE_ADDR this_pc = get_frame_pc (this_frame);
 265   struct gdbarch *gdbarch = get_frame_arch (this_frame);
 266   find_pc_partial_function (this_pc, NULL, &start_addr, NULL);
 267
 268   /* Get the stack pointer if we have one (if there's no process executing
 269      yet we won't have a frame.  */
 270   this_sp = (NULL == this_frame) ? 0 :
 271     get_frame_register_unsigned (this_frame, REG_S);
 272
 273   /* Return early if GDB couldn't find the function.  */
 274   if (start_addr == 0)
 275     {
 276       warning (_("Couldn't find function including address %s SP is %s"),
 277                paddress (gdbarch, this_pc),
 278                paddress (gdbarch, this_sp));
 279
 280       /* JPB: 28-Apr-11.  This is a temporary patch, to get round GDB
 281          crashing right at the beginning.  Build the frame ID as best we
 282          can.  */
 283       trad_frame_set_id (info, frame_id_build (this_sp, this_pc));
 284
 285       return info;
 286     }
 287
 288   /* The default frame base of this frame (for ID purposes only - frame
 289      base is an overloaded term) is its stack pointer.  For now we use the
 290      value of the SP register in this frame.  However if the PC is in the
 291      prologue of this frame, before the SP has been set up, then the value
 292      will actually be that of the prev frame, and we'll need to adjust it
 293      later.  */
 294   trad_frame_set_this_base (info, this_sp);
 295   this_sp_for_id = this_sp;
 296
 297   /* We should only examine code that is in the prologue.  This is all code
 298      up to (but not including) end_addr.  We should only populate the cache
 299      while the address is up to (but not including) the PC or end_addr,
 300      whichever is first.  */
 301   end_addr = s12z_skip_prologue (gdbarch, start_addr);
 302
 303   /* All the following analysis only occurs if we are in the prologue and
 304      have executed the code.  Check we have a sane prologue size, and if
 305      zero we are frameless and can give up here.  */
 306   if (end_addr < start_addr)
 307     error (_("end addr %s is less than start addr %s"),
 308            paddress (gdbarch, end_addr), paddress (gdbarch, start_addr));
 309
 310   CORE_ADDR addr = start_addr; /* Where we have got to?  */
 311   int frame_size = 0;
 312   int saved_frame_size = 0;
 313
 314   struct gdb_non_printing_memory_disassembler dis (gdbarch);
 315
 316   struct mem_read_abstraction mra;
 317   mra.base.read = (int (*)(mem_read_abstraction_base*,
 318                            int, size_t, bfd_byte*)) abstract_read_memory;
 319   mra.base.advance = advance ;
 320   mra.base.posn = posn;
 321   mra.info = dis.disasm_info ();
 322
 323   while (this_pc > addr)
 324     {
 325       enum optr optr = OP_INVALID;
 326       short osize;
 327       int n_operands = 0;
 328       struct operand *operands[6];
 329       mra.memaddr = addr;
 330       int n_bytes =
 331         decode_s12z (&optr, &osize, &n_operands, operands,
 332                      (mem_read_abstraction_base *) &mra);
 333
 334       switch (optr)
 335         {
 336         case OP_tbNE:
 337         case OP_tbPL:
 338         case OP_tbMI:
 339         case OP_tbGT:
 340         case OP_tbLE:
 341         case OP_dbNE:
 342         case OP_dbEQ:
 343         case OP_dbPL:
 344         case OP_dbMI:
 345         case OP_dbGT:
 346         case OP_dbLE:
 347           /* Conditional Branches.   If any of these are encountered, then
 348              it is likely that a RTS will terminate it.  So we need to save
 349              the frame size so it can be restored.  */
 350           saved_frame_size = frame_size;
 351           break;
 352         case OP_rts:
 353           /* Restore the frame size from a previously saved value.  */
 354           frame_size = saved_frame_size;
 355           break;
 356         case OP_push:
 357           frame_size += push_pull_get_stack_adjustment (n_operands, operands);
 358           break;
 359         case OP_pull:
 360           frame_size -= push_pull_get_stack_adjustment (n_operands, operands);
 361           break;
 362         case OP_lea:
 363           if (operands[0]->cl == OPND_CL_REGISTER)
 364             {
 365               int reg = ((struct register_operand *) (operands[0]))->reg;
 366               if ((reg == REG_S) && (operands[1]->cl == OPND_CL_MEMORY))
 367                 {
 368                   const struct memory_operand *mo
 369                     = (const struct memory_operand * ) operands[1];
 370                   if (mo->n_regs == 1 && !mo->indirect
 371                       && mo->regs[0] == REG_S
 372                       && mo->mutation == OPND_RM_NONE)
 373                     {
 374                       /* LEA S, (xxx, S) -- Decrement the stack.   This is
 375                          almost certainly the start of a frame.  */
 376                       int simm = (signed char)  mo->base_offset;
 377                       frame_size -= simm;
 378                     }
 379                 }
 380             }
 381           break;
 382         default:
 383           break;
 384         }
 385       addr += n_bytes;
 386       for (int o = 0; o < n_operands; ++o)
 387         free (operands[o]);
 388     }
 389
 390   /* If the PC has not actually got to this point, then the frame
 391      base will be wrong, and we adjust it. */
 392   if (this_pc < addr)
 393     {
 394       /* Only do if executing.  */
 395       if (0 != this_sp)
 396         {
 397           this_sp_for_id = this_sp - frame_size;
 398           trad_frame_set_this_base (info, this_sp_for_id);
 399         }
 400       trad_frame_set_reg_value (info, REG_S, this_sp + 3);
 401       trad_frame_set_reg_addr (info, REG_P, this_sp);
 402     }
 403   else
 404     {
 405       gdb_assert (this_sp == this_sp_for_id);
 406       /* The stack pointer of the prev frame is frame_size greater
 407          than the stack pointer of this frame plus one address
 408          size (caused by the JSR or BSR).  */
 409       trad_frame_set_reg_value (info, REG_S,
 410                                 this_sp + frame_size + 3);
 411       trad_frame_set_reg_addr (info, REG_P, this_sp + frame_size);
 412     }
 413
 414
 415   /* Build the frame ID.  */
 416   trad_frame_set_id (info, frame_id_build (this_sp_for_id, start_addr));
 417
 418   return info;
 419 }
 420
 421 /* Implement the this_id function for the stub unwinder.  */
 422 static void
 423 s12z_frame_this_id (const frame_info_ptr &this_frame,
 424                     void **prologue_cache, struct frame_id *this_id)
 425 {
 426   struct trad_frame_cache *info = s12z_frame_cache (this_frame,
 427                                                     prologue_cache);
 428
 429   trad_frame_get_id (info, this_id);
 430 }
 431
 432
 433 /* Implement the prev_register function for the stub unwinder.  */
 434 static struct value *
 435 s12z_frame_prev_register (const frame_info_ptr &this_frame,
 436                           void **prologue_cache, int regnum)
 437 {
 438   struct trad_frame_cache *info = s12z_frame_cache (this_frame,
 439                                                     prologue_cache);
 440
 441   return trad_frame_get_register (info, this_frame, regnum);
 442 }
 443
 444 /* Data structures for the normal prologue-analysis-based unwinder.  */
 445 static const struct frame_unwind s12z_frame_unwind = {
 446   "s12z prologue",
 447   NORMAL_FRAME,
 448   default_frame_unwind_stop_reason,
 449   s12z_frame_this_id,
 450   s12z_frame_prev_register,
 451   NULL,
 452   default_frame_sniffer,
 453   NULL,
 454 };
 455
 456
 457 constexpr gdb_byte s12z_break_insn[] = {0x00};
 458
 459 typedef BP_MANIPULATION (s12z_break_insn) s12z_breakpoint;
 460
 461 struct s12z_gdbarch_tdep : gdbarch_tdep_base
 462 {
 463 };
 464
 465 /*  A vector of human readable characters representing the
 466     bits in the CCW register.  Unused bits are represented as '-'.
 467     Lowest significant bit comes first.  */
 468 static const char ccw_bits[] =
 469   {
 470    'C',  /* Carry  */
 471    'V',  /* Two's Complement Overflow  */
 472    'Z',  /* Zero  */
 473    'N',  /* Negative  */
 474    'I',  /* Interrupt  */
 475    '-',
 476    'X',  /* Non-Maskable Interrupt  */
 477    'S',  /* STOP Disable  */
 478    '0',  /*  Interrupt priority level */
 479    '0',  /*  ditto  */
 480    '0',  /*  ditto  */
 481    '-',
 482    '-',
 483    '-',
 484    '-',
 485    'U'   /* User/Supervisor State.  */
 486   };
 487
 488 /* Print a human readable representation of the CCW register.
 489    For example: "u----000SX-Inzvc" corresponds to the value
 490    0xD0.  */
 491 static void
 492 s12z_print_ccw_info (struct gdbarch *gdbarch,
 493                      struct ui_file *file,
 494                      const frame_info_ptr &frame,
 495                      int reg)
 496 {
 497   value *v = value_of_register (reg, get_next_frame_sentinel_okay (frame));
 498   const char *name = gdbarch_register_name (gdbarch, reg);
 499   uint32_t ccw = value_as_long (v);
 500   gdb_puts (name, file);
 501   size_t len = strlen (name);
 502   const int stop_1 = 15;
 503   const int stop_2 = 17;
 504   for (int i = 0; i < stop_1 - len; ++i)
 505     gdb_putc (' ', file);
 506   gdb_printf (file, "0x%04x", ccw);
 507   for (int i = 0; i < stop_2 - len; ++i)
 508     gdb_putc (' ', file);
 509   for (int b = 15; b >= 0; --b)
 510     {
 511       if (ccw & (0x1u << b))
 512         {
 513           if (ccw_bits[b] == 0)
 514             gdb_putc ('1', file);
 515           else
 516             gdb_putc (ccw_bits[b], file);
 517         }
 518       else
 519         gdb_putc (tolower (ccw_bits[b]), file);
 520     }
 521   gdb_putc ('\n', file);
 522 }
 523
 524 static void
 525 s12z_print_registers_info (struct gdbarch *gdbarch,
 526                             struct ui_file *file,
 527                             const frame_info_ptr &frame,
 528                             int regnum, int print_all)
 529 {
 530   const int numregs = (gdbarch_num_regs (gdbarch)
 531                        + gdbarch_num_pseudo_regs (gdbarch));
 532
 533   if (regnum == -1)
 534     {
 535       for (int reg = 0; reg < numregs; reg++)
 536         {
 537           if (REG_CCW == reg_perm[reg])
 538             {
 539               s12z_print_ccw_info (gdbarch, file, frame, reg);
 540               continue;
 541             }
 542           default_print_registers_info (gdbarch, file, frame, reg, print_all);
 543         }
 544     }
 545   else if (REG_CCW == reg_perm[regnum])
 546     s12z_print_ccw_info (gdbarch, file, frame, regnum);
 547   else
 548     default_print_registers_info (gdbarch, file, frame, regnum, print_all);
 549 }
 550
 551 \f
 552
 553
 554 static void
 555 s12z_extract_return_value (struct type *type, struct regcache *regcache,
 556                               void *valbuf)
 557 {
 558   int reg = -1;
 559
 560   switch (type->length ())
 561     {
 562     case 0:   /* Nothing to do */
 563       return;
 564
 565     case 1:
 566       reg = REG_D0;
 567       break;
 568
 569     case 2:
 570       reg = REG_D2;
 571       break;
 572
 573     case 3:
 574       reg = REG_X;
 575       break;
 576
 577     case 4:
 578       reg = REG_D6;
 579       break;
 580
 581     default:
 582       error (_("bad size for return value"));
 583       return;
 584     }
 585
 586   regcache->cooked_read (inv_reg_perm[reg], (gdb_byte *) valbuf);
 587 }
 588
 589 static enum return_value_convention
 590 s12z_return_value (struct gdbarch *gdbarch, struct value *function,
 591                    struct type *type, struct regcache *regcache,
 592                    gdb_byte *readbuf, const gdb_byte *writebuf)
 593 {
 594   if (type->code () == TYPE_CODE_STRUCT
 595       || type->code () == TYPE_CODE_UNION
 596       || type->code () == TYPE_CODE_ARRAY
 597       || type->length () > 4)
 598     return RETURN_VALUE_STRUCT_CONVENTION;
 599
 600   if (readbuf)
 601     s12z_extract_return_value (type, regcache, readbuf);
 602
 603   return RETURN_VALUE_REGISTER_CONVENTION;
 604 }
 605
 606
 607 static void
 608 show_bdccsr_command (const char *args, int from_tty)
 609 {
 610   struct string_file output;
 611   target_rcmd ("bdccsr", &output);
 612
 613   gdb_printf ("The current BDCCSR value is %s\n", output.string().c_str());
 614 }
 615
 616 static struct gdbarch *
 617 s12z_gdbarch_init (struct gdbarch_info info, struct gdbarch_list *arches)
 618 {
 619   gdbarch *gdbarch
 620     = gdbarch_alloc (&info, gdbarch_tdep_up (new s12z_gdbarch_tdep));
 621
 622   add_cmd ("bdccsr", class_support, show_bdccsr_command,
 623            _("Show the current value of the microcontroller's BDCCSR."),
 624            &maintenanceinfolist);
 625
 626   /* Target data types.  */
 627   set_gdbarch_short_bit (gdbarch, 16);
 628   set_gdbarch_int_bit (gdbarch, 16);
 629   set_gdbarch_long_bit (gdbarch, 32);
 630   set_gdbarch_long_long_bit (gdbarch, 32);
 631   set_gdbarch_ptr_bit (gdbarch, 24);
 632   set_gdbarch_addr_bit (gdbarch, 24);
 633   set_gdbarch_char_signed (gdbarch, 0);
 634
 635   set_gdbarch_ps_regnum (gdbarch, REG_CCW);
 636   set_gdbarch_pc_regnum (gdbarch, REG_P);
 637   set_gdbarch_sp_regnum (gdbarch, REG_S);
 638
 639
 640   set_gdbarch_print_registers_info (gdbarch, s12z_print_registers_info);
 641
 642   set_gdbarch_breakpoint_kind_from_pc (gdbarch,
 643                                        s12z_breakpoint::kind_from_pc);
 644   set_gdbarch_sw_breakpoint_from_kind (gdbarch,
 645                                        s12z_breakpoint::bp_from_kind);
 646
 647   set_gdbarch_num_regs (gdbarch, N_PHYSICAL_REGISTERS);
 648   set_gdbarch_register_name (gdbarch, s12z_register_name);
 649   set_gdbarch_skip_prologue (gdbarch, s12z_skip_prologue);
 650   set_gdbarch_inner_than (gdbarch, core_addr_lessthan);
 651   set_gdbarch_dwarf2_reg_to_regnum (gdbarch, s12z_dwarf_reg_to_regnum);
 652
 653   set_gdbarch_register_type (gdbarch, s12z_register_type);
 654
 655   frame_unwind_append_unwinder (gdbarch, &s12z_frame_unwind);
 656   /* Currently, the only known producer for this architecture, produces buggy
 657      dwarf CFI.   So don't append a dwarf unwinder until the situation is
 658      better understood.  */
 659
 660   set_gdbarch_return_value (gdbarch, s12z_return_value);
 661
 662   return gdbarch;
 663 }
 664
 665 void _initialize_s12z_tdep ();
 666 void
 667 _initialize_s12z_tdep ()
 668 {
 669   gdbarch_register (bfd_arch_s12z, s12z_gdbarch_init, NULL);
 670 }