1 /* Target-dependent code for the Fujitsu FR-V, for GDB, the GNU Debugger.
3 Copyright (C) 2002-2024 Free Software Foundation, Inc.
5 This file is part of GDB.
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
23 #include "arch-utils.h"
26 #include "frame-unwind.h"
27 #include "frame-base.h"
28 #include "trad-frame.h"
30 #include "sim-regno.h"
31 #include "sim/sim-frv.h"
42 /* Make cgen names unique to prevent ODR conflicts with other targets. */
43 #define GDB_CGEN_REMAP_PREFIX frv
44 #include "cgen-remap.h"
45 #include "opcodes/frv-desc.h"
47 struct frv_unwind_cache
/* was struct frame_extra_info */
49 /* The previous frame's inner-most stack address. Used as this
50 frame ID's stack_addr. */
53 /* The frame's base, optionally used by the high-level debug info. */
56 /* Table indicating the location of each and every register. */
57 trad_frame_saved_reg
*saved_regs
;
60 /* A structure describing a particular variant of the FRV.
61 We allocate and initialize one of these structures when we create
62 the gdbarch object for a variant.
64 At the moment, all the FR variants we support differ only in which
65 registers are present; the portable code of GDB knows that
66 registers whose names are the empty string don't exist, so the
67 `register_names' array captures all the per-variant information we
70 in the future, if we need to have per-variant maps for raw size,
71 virtual type, etc., we should replace register_names with an array
72 of structures, each of which gives all the necessary info for one
73 register. Don't stick parallel arrays in here --- that's so
75 struct frv_gdbarch_tdep
: gdbarch_tdep_base
77 /* Which ABI is in use? */
78 enum frv_abi frv_abi
{};
80 /* How many general-purpose registers does this variant have? */
83 /* How many floating-point registers does this variant have? */
86 /* How many hardware watchpoints can it support? */
87 int num_hw_watchpoints
= 0;
89 /* How many hardware breakpoints can it support? */
90 int num_hw_breakpoints
= 0;
93 const char **register_names
= nullptr;
96 using frv_gdbarch_tdep_up
= std::unique_ptr
<frv_gdbarch_tdep
>;
98 /* Return the FR-V ABI associated with GDBARCH. */
100 frv_abi (struct gdbarch
*gdbarch
)
102 frv_gdbarch_tdep
*tdep
= gdbarch_tdep
<frv_gdbarch_tdep
> (gdbarch
);
103 return tdep
->frv_abi
;
106 /* Fetch the interpreter and executable loadmap addresses (for shared
107 library support) for the FDPIC ABI. Return 0 if successful, -1 if
108 not. (E.g, -1 will be returned if the ABI isn't the FDPIC ABI.) */
110 frv_fdpic_loadmap_addresses (struct gdbarch
*gdbarch
, CORE_ADDR
*interp_addr
,
111 CORE_ADDR
*exec_addr
)
113 if (frv_abi (gdbarch
) != FRV_ABI_FDPIC
)
117 regcache
*regcache
= get_thread_regcache (inferior_thread ());
119 if (interp_addr
!= NULL
)
122 regcache_cooked_read_unsigned (regcache
,
123 fdpic_loadmap_interp_regnum
, &val
);
126 if (exec_addr
!= NULL
)
129 regcache_cooked_read_unsigned (regcache
,
130 fdpic_loadmap_exec_regnum
, &val
);
137 /* Allocate a new variant structure, and set up default values for all
139 static frv_gdbarch_tdep_up
144 frv_gdbarch_tdep_up
var (new frv_gdbarch_tdep
);
146 var
->frv_abi
= FRV_ABI_EABI
;
149 var
->num_hw_watchpoints
= 0;
150 var
->num_hw_breakpoints
= 0;
152 /* By default, don't supply any general-purpose or floating-point
155 = (const char **) xmalloc ((frv_num_regs
+ frv_num_pseudo_regs
)
156 * sizeof (const char *));
157 for (r
= 0; r
< frv_num_regs
+ frv_num_pseudo_regs
; r
++)
158 var
->register_names
[r
] = "";
160 /* Do, however, supply default names for the known special-purpose
163 var
->register_names
[pc_regnum
] = "pc";
164 var
->register_names
[lr_regnum
] = "lr";
165 var
->register_names
[lcr_regnum
] = "lcr";
167 var
->register_names
[psr_regnum
] = "psr";
168 var
->register_names
[ccr_regnum
] = "ccr";
169 var
->register_names
[cccr_regnum
] = "cccr";
170 var
->register_names
[tbr_regnum
] = "tbr";
172 /* Debug registers. */
173 var
->register_names
[brr_regnum
] = "brr";
174 var
->register_names
[dbar0_regnum
] = "dbar0";
175 var
->register_names
[dbar1_regnum
] = "dbar1";
176 var
->register_names
[dbar2_regnum
] = "dbar2";
177 var
->register_names
[dbar3_regnum
] = "dbar3";
179 /* iacc0 (Only found on MB93405.) */
180 var
->register_names
[iacc0h_regnum
] = "iacc0h";
181 var
->register_names
[iacc0l_regnum
] = "iacc0l";
182 var
->register_names
[iacc0_regnum
] = "iacc0";
184 /* fsr0 (Found on FR555 and FR501.) */
185 var
->register_names
[fsr0_regnum
] = "fsr0";
187 /* acc0 - acc7. The architecture provides for the possibility of many
188 more (up to 64 total), but we don't want to make that big of a hole
189 in the G packet. If we need more in the future, we'll add them
191 for (r
= acc0_regnum
; r
<= acc7_regnum
; r
++)
192 var
->register_names
[r
]
193 = xstrprintf ("acc%d", r
- acc0_regnum
).release ();
195 /* accg0 - accg7: These are one byte registers. The remote protocol
196 provides the raw values packed four into a slot. accg0123 and
197 accg4567 correspond to accg0 - accg3 and accg4-accg7 respectively.
198 We don't provide names for accg0123 and accg4567 since the user will
199 likely not want to see these raw values. */
201 for (r
= accg0_regnum
; r
<= accg7_regnum
; r
++)
202 var
->register_names
[r
]
203 = xstrprintf ("accg%d", r
- accg0_regnum
).release ();
207 var
->register_names
[msr0_regnum
] = "msr0";
208 var
->register_names
[msr1_regnum
] = "msr1";
210 /* gner and fner registers. */
211 var
->register_names
[gner0_regnum
] = "gner0";
212 var
->register_names
[gner1_regnum
] = "gner1";
213 var
->register_names
[fner0_regnum
] = "fner0";
214 var
->register_names
[fner1_regnum
] = "fner1";
220 /* Indicate that the variant VAR has NUM_GPRS general-purpose
221 registers, and fill in the names array appropriately. */
223 set_variant_num_gprs (frv_gdbarch_tdep
*var
, int num_gprs
)
227 var
->num_gprs
= num_gprs
;
229 for (r
= 0; r
< num_gprs
; ++r
)
233 xsnprintf (buf
, sizeof (buf
), "gr%d", r
);
234 var
->register_names
[first_gpr_regnum
+ r
] = xstrdup (buf
);
239 /* Indicate that the variant VAR has NUM_FPRS floating-point
240 registers, and fill in the names array appropriately. */
242 set_variant_num_fprs (frv_gdbarch_tdep
*var
, int num_fprs
)
246 var
->num_fprs
= num_fprs
;
248 for (r
= 0; r
< num_fprs
; ++r
)
252 xsnprintf (buf
, sizeof (buf
), "fr%d", r
);
253 var
->register_names
[first_fpr_regnum
+ r
] = xstrdup (buf
);
258 set_variant_abi_fdpic (frv_gdbarch_tdep
*var
)
260 var
->frv_abi
= FRV_ABI_FDPIC
;
261 var
->register_names
[fdpic_loadmap_exec_regnum
] = xstrdup ("loadmap_exec");
262 var
->register_names
[fdpic_loadmap_interp_regnum
]
263 = xstrdup ("loadmap_interp");
267 set_variant_scratch_registers (frv_gdbarch_tdep
*var
)
269 var
->register_names
[scr0_regnum
] = xstrdup ("scr0");
270 var
->register_names
[scr1_regnum
] = xstrdup ("scr1");
271 var
->register_names
[scr2_regnum
] = xstrdup ("scr2");
272 var
->register_names
[scr3_regnum
] = xstrdup ("scr3");
276 frv_register_name (struct gdbarch
*gdbarch
, int reg
)
278 frv_gdbarch_tdep
*tdep
= gdbarch_tdep
<frv_gdbarch_tdep
> (gdbarch
);
279 return tdep
->register_names
[reg
];
284 frv_register_type (struct gdbarch
*gdbarch
, int reg
)
286 if (reg
>= first_fpr_regnum
&& reg
<= last_fpr_regnum
)
287 return builtin_type (gdbarch
)->builtin_float
;
288 else if (reg
== iacc0_regnum
)
289 return builtin_type (gdbarch
)->builtin_int64
;
291 return builtin_type (gdbarch
)->builtin_int32
;
294 static enum register_status
295 frv_pseudo_register_read (struct gdbarch
*gdbarch
, readable_regcache
*regcache
,
296 int reg
, gdb_byte
*buffer
)
298 enum register_status status
;
300 if (reg
== iacc0_regnum
)
302 status
= regcache
->raw_read (iacc0h_regnum
, buffer
);
303 if (status
== REG_VALID
)
304 status
= regcache
->raw_read (iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
306 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
308 /* The accg raw registers have four values in each slot with the
309 lowest register number occupying the first byte. */
311 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
312 int byte_num
= (reg
- accg0_regnum
) % 4;
315 status
= regcache
->raw_read (raw_regnum
, buf
);
316 if (status
== REG_VALID
)
318 memset (buffer
, 0, 4);
319 /* FR-V is big endian, so put the requested byte in the
320 first byte of the buffer allocated to hold the
322 buffer
[0] = buf
[byte_num
];
326 gdb_assert_not_reached ("invalid pseudo register number");
332 frv_pseudo_register_write (struct gdbarch
*gdbarch
, struct regcache
*regcache
,
333 int reg
, const gdb_byte
*buffer
)
335 if (reg
== iacc0_regnum
)
337 regcache
->raw_write (iacc0h_regnum
, buffer
);
338 regcache
->raw_write (iacc0l_regnum
, (bfd_byte
*) buffer
+ 4);
340 else if (accg0_regnum
<= reg
&& reg
<= accg7_regnum
)
342 /* The accg raw registers have four values in each slot with the
343 lowest register number occupying the first byte. */
345 int raw_regnum
= accg0123_regnum
+ (reg
- accg0_regnum
) / 4;
346 int byte_num
= (reg
- accg0_regnum
) % 4;
349 regcache
->raw_read (raw_regnum
, buf
);
350 buf
[byte_num
] = ((bfd_byte
*) buffer
)[0];
351 regcache
->raw_write (raw_regnum
, buf
);
356 frv_register_sim_regno (struct gdbarch
*gdbarch
, int reg
)
358 static const int spr_map
[] =
360 H_SPR_PSR
, /* psr_regnum */
361 H_SPR_CCR
, /* ccr_regnum */
362 H_SPR_CCCR
, /* cccr_regnum */
363 -1, /* fdpic_loadmap_exec_regnum */
364 -1, /* fdpic_loadmap_interp_regnum */
366 H_SPR_TBR
, /* tbr_regnum */
367 H_SPR_BRR
, /* brr_regnum */
368 H_SPR_DBAR0
, /* dbar0_regnum */
369 H_SPR_DBAR1
, /* dbar1_regnum */
370 H_SPR_DBAR2
, /* dbar2_regnum */
371 H_SPR_DBAR3
, /* dbar3_regnum */
372 H_SPR_SCR0
, /* scr0_regnum */
373 H_SPR_SCR1
, /* scr1_regnum */
374 H_SPR_SCR2
, /* scr2_regnum */
375 H_SPR_SCR3
, /* scr3_regnum */
376 H_SPR_LR
, /* lr_regnum */
377 H_SPR_LCR
, /* lcr_regnum */
378 H_SPR_IACC0H
, /* iacc0h_regnum */
379 H_SPR_IACC0L
, /* iacc0l_regnum */
380 H_SPR_FSR0
, /* fsr0_regnum */
381 /* FIXME: Add infrastructure for fetching/setting ACC and ACCG regs. */
382 -1, /* acc0_regnum */
383 -1, /* acc1_regnum */
384 -1, /* acc2_regnum */
385 -1, /* acc3_regnum */
386 -1, /* acc4_regnum */
387 -1, /* acc5_regnum */
388 -1, /* acc6_regnum */
389 -1, /* acc7_regnum */
390 -1, /* acc0123_regnum */
391 -1, /* acc4567_regnum */
392 H_SPR_MSR0
, /* msr0_regnum */
393 H_SPR_MSR1
, /* msr1_regnum */
394 H_SPR_GNER0
, /* gner0_regnum */
395 H_SPR_GNER1
, /* gner1_regnum */
396 H_SPR_FNER0
, /* fner0_regnum */
397 H_SPR_FNER1
, /* fner1_regnum */
400 gdb_assert (reg
>= 0 && reg
< gdbarch_num_regs (gdbarch
));
402 if (first_gpr_regnum
<= reg
&& reg
<= last_gpr_regnum
)
403 return reg
- first_gpr_regnum
+ SIM_FRV_GR0_REGNUM
;
404 else if (first_fpr_regnum
<= reg
&& reg
<= last_fpr_regnum
)
405 return reg
- first_fpr_regnum
+ SIM_FRV_FR0_REGNUM
;
406 else if (pc_regnum
== reg
)
407 return SIM_FRV_PC_REGNUM
;
408 else if (reg
>= first_spr_regnum
409 && reg
< first_spr_regnum
+ sizeof (spr_map
) / sizeof (spr_map
[0]))
411 int spr_reg_offset
= spr_map
[reg
- first_spr_regnum
];
413 if (spr_reg_offset
< 0)
414 return SIM_REGNO_DOES_NOT_EXIST
;
416 return SIM_FRV_SPR0_REGNUM
+ spr_reg_offset
;
419 internal_error (_("Bad register number %d"), reg
);
422 constexpr gdb_byte frv_break_insn
[] = {0xc0, 0x70, 0x00, 0x01};
424 typedef BP_MANIPULATION (frv_break_insn
) frv_breakpoint
;
426 /* Define the maximum number of instructions which may be packed into a
427 bundle (VLIW instruction). */
428 static const int max_instrs_per_bundle
= 8;
430 /* Define the size (in bytes) of an FR-V instruction. */
431 static const int frv_instr_size
= 4;
433 /* Adjust a breakpoint's address to account for the FR-V architecture's
434 constraint that a break instruction must not appear as any but the
435 first instruction in the bundle. */
437 frv_adjust_breakpoint_address (struct gdbarch
*gdbarch
, CORE_ADDR bpaddr
)
439 int count
= max_instrs_per_bundle
;
440 CORE_ADDR addr
= bpaddr
- frv_instr_size
;
441 CORE_ADDR func_start
= get_pc_function_start (bpaddr
);
443 /* Find the end of the previous packing sequence. This will be indicated
444 by either attempting to access some inaccessible memory or by finding
445 an instruction word whose packing bit is set to one. */
446 while (count
-- > 0 && addr
>= func_start
)
448 gdb_byte instr
[frv_instr_size
];
451 status
= target_read_memory (addr
, instr
, sizeof instr
);
456 /* This is a big endian architecture, so byte zero will have most
457 significant byte. The most significant bit of this byte is the
462 addr
-= frv_instr_size
;
466 bpaddr
= addr
+ frv_instr_size
;
472 /* Return true if REG is a caller-saves ("scratch") register,
475 is_caller_saves_reg (int reg
)
477 return ((4 <= reg
&& reg
<= 7)
478 || (14 <= reg
&& reg
<= 15)
479 || (32 <= reg
&& reg
<= 47));
483 /* Return true if REG is a callee-saves register, false otherwise. */
485 is_callee_saves_reg (int reg
)
487 return ((16 <= reg
&& reg
<= 31)
488 || (48 <= reg
&& reg
<= 63));
492 /* Return true if REG is an argument register, false otherwise. */
494 is_argument_reg (int reg
)
496 return (8 <= reg
&& reg
<= 13);
499 /* Scan an FR-V prologue, starting at PC, until frame->PC.
500 If FRAME is non-zero, fill in its saved_regs with appropriate addresses.
501 We assume FRAME's saved_regs array has already been allocated and cleared.
502 Return the first PC value after the prologue.
504 Note that, for unoptimized code, we almost don't need this function
505 at all; all arguments and locals live on the stack, so we just need
506 the FP to find everything. The catch: structures passed by value
507 have their addresses living in registers; they're never spilled to
508 the stack. So if you ever want to be able to get to these
509 arguments in any frame but the top, you'll need to do this serious
510 prologue analysis. */
512 frv_analyze_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
,
513 const frame_info_ptr
&this_frame
,
514 struct frv_unwind_cache
*info
)
516 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
518 /* When writing out instruction bitpatterns, we use the following
519 letters to label instruction fields:
520 P - The parallel bit. We don't use this.
521 J - The register number of GRj in the instruction description.
522 K - The register number of GRk in the instruction description.
523 I - The register number of GRi.
524 S - a signed immediate offset.
525 U - an unsigned immediate offset.
527 The dots below the numbers indicate where hex digit boundaries
528 fall, to make it easier to check the numbers. */
530 /* Non-zero iff we've seen the instruction that initializes the
531 frame pointer for this function's frame. */
534 /* If fp_set is non_zero, then this is the distance from
535 the stack pointer to frame pointer: fp = sp + fp_offset. */
538 /* Total size of frame prior to any alloca operations. */
541 /* Flag indicating if lr has been saved on the stack. */
542 int lr_saved_on_stack
= 0;
544 /* The number of the general-purpose register we saved the return
545 address ("link register") in, or -1 if we haven't moved it yet. */
546 int lr_save_reg
= -1;
548 /* Offset (from sp) at which lr has been saved on the stack. */
550 int lr_sp_offset
= 0;
552 /* If gr_saved[i] is non-zero, then we've noticed that general
553 register i has been saved at gr_sp_offset[i] from the stack
556 int gr_sp_offset
[64];
558 /* The address of the most recently scanned prologue instruction. */
559 CORE_ADDR last_prologue_pc
;
561 /* The address of the next instruction. */
564 /* The upper bound to of the pc values to scan. */
567 memset (gr_saved
, 0, sizeof (gr_saved
));
569 last_prologue_pc
= pc
;
571 /* Try to compute an upper limit (on how far to scan) based on the
573 lim_pc
= skip_prologue_using_sal (gdbarch
, pc
);
574 /* If there's no line number info, lim_pc will be 0. In that case,
575 set the limit to be 100 instructions away from pc. Hopefully, this
576 will be far enough away to account for the entire prologue. Don't
577 worry about overshooting the end of the function. The scan loop
578 below contains some checks to avoid scanning unreasonably far. */
582 /* If we have a frame, we don't want to scan past the frame's pc. This
583 will catch those cases where the pc is in the prologue. */
586 CORE_ADDR frame_pc
= get_frame_pc (this_frame
);
587 if (frame_pc
< lim_pc
)
591 /* Scan the prologue. */
594 gdb_byte buf
[frv_instr_size
];
597 if (target_read_memory (pc
, buf
, sizeof buf
) != 0)
599 op
= extract_signed_integer (buf
, byte_order
);
603 /* The tests in this chain of ifs should be in order of
604 decreasing selectivity, so that more particular patterns get
605 to fire before less particular patterns. */
607 /* Some sort of control transfer instruction: stop scanning prologue.
608 Integer Conditional Branch:
609 X XXXX XX 0000110 XX XXXXXXXXXXXXXXXX
610 Floating-point / media Conditional Branch:
611 X XXXX XX 0000111 XX XXXXXXXXXXXXXXXX
612 LCR Conditional Branch to LR
613 X XXXX XX 0001110 XX XX 001 X XXXXXXXXXX
614 Integer conditional Branches to LR
615 X XXXX XX 0001110 XX XX 010 X XXXXXXXXXX
616 X XXXX XX 0001110 XX XX 011 X XXXXXXXXXX
617 Floating-point/Media Branches to LR
618 X XXXX XX 0001110 XX XX 110 X XXXXXXXXXX
619 X XXXX XX 0001110 XX XX 111 X XXXXXXXXXX
621 X XXXXX X 0001100 XXXXXX XXXXXX XXXXXX
622 X XXXXX X 0001101 XXXXXX XXXXXX XXXXXX
624 X XXXXXX 0001111 XXXXXXXXXXXXXXXXXX
626 X XXXXX X 0000101 XXXXXX XXXXXX XXXXXX
627 Integer Conditional Trap
628 X XXXX XX 0000100 XXXXXX XXXX 00 XXXXXX
629 X XXXX XX 0011100 XXXXXX XXXXXXXXXXXX
630 Floating-point /media Conditional Trap
631 X XXXX XX 0000100 XXXXXX XXXX 01 XXXXXX
632 X XXXX XX 0011101 XXXXXX XXXXXXXXXXXX
634 X XXXX XX 0000100 XXXXXX XXXX 11 XXXXXX
636 X XXXX XX 0000100 XXXXXX XXXX 10 XXXXXX */
637 if ((op
& 0x01d80000) == 0x00180000 /* Conditional branches and Call */
638 || (op
& 0x01f80000) == 0x00300000 /* Jump and Link */
639 || (op
& 0x01f80000) == 0x00100000 /* Return from Trap, Trap */
640 || (op
& 0x01f80000) == 0x00700000) /* Trap immediate */
642 /* Stop scanning; not in prologue any longer. */
646 /* Loading something from memory into fp probably means that
647 we're in the epilogue. Stop scanning the prologue.
649 X 000010 0000010 XXXXXX 000100 XXXXXX
651 X 000010 0110010 XXXXXX XXXXXXXXXXXX */
652 else if ((op
& 0x7ffc0fc0) == 0x04080100
653 || (op
& 0x7ffc0000) == 0x04c80000)
658 /* Setting the FP from the SP:
660 P 000010 0100010 000001 000000000000 = 0x04881000
661 0 111111 1111111 111111 111111111111 = 0x7fffffff
663 We treat this as part of the prologue. */
664 else if ((op
& 0x7fffffff) == 0x04881000)
668 last_prologue_pc
= next_pc
;
671 /* Move the link register to the scratch register grJ, before saving:
673 P 000100 0000011 010000 000111 JJJJJJ = 0x080d01c0
674 0 111111 1111111 111111 111111 000000 = 0x7fffffc0
676 We treat this as part of the prologue. */
677 else if ((op
& 0x7fffffc0) == 0x080d01c0)
679 int gr_j
= op
& 0x3f;
681 /* If we're moving it to a scratch register, that's fine. */
682 if (is_caller_saves_reg (gr_j
))
685 last_prologue_pc
= next_pc
;
689 /* To save multiple callee-saves registers on the stack, at
693 P KKKKKK 0000011 000001 000011 000000 = 0x000c10c0
694 0 000000 1111111 111111 111111 111111 = 0x01ffffff
697 P KKKKKK 0000011 000001 000100 000000 = 0x000c1100
698 0 000000 1111111 111111 111111 111111 = 0x01ffffff
700 We treat this as part of the prologue, and record the register's
701 saved address in the frame structure. */
702 else if ((op
& 0x01ffffff) == 0x000c10c0
703 || (op
& 0x01ffffff) == 0x000c1100)
705 int gr_k
= ((op
>> 25) & 0x3f);
706 int ope
= ((op
>> 6) & 0x3f);
710 /* Is it an std or an stq? */
716 /* Is it really a callee-saves register? */
717 if (is_callee_saves_reg (gr_k
))
719 for (i
= 0; i
< count
; i
++)
721 gr_saved
[gr_k
+ i
] = 1;
722 gr_sp_offset
[gr_k
+ i
] = 4 * i
;
724 last_prologue_pc
= next_pc
;
728 /* Adjusting the stack pointer. (The stack pointer is GR1.)
730 P 000001 0010000 000001 SSSSSSSSSSSS = 0x02401000
731 0 111111 1111111 111111 000000000000 = 0x7ffff000
733 We treat this as part of the prologue. */
734 else if ((op
& 0x7ffff000) == 0x02401000)
738 /* Sign-extend the twelve-bit field.
739 (Isn't there a better way to do this?) */
740 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
743 last_prologue_pc
= pc
;
747 /* If the prologue is being adjusted again, we've
748 likely gone too far; i.e. we're probably in the
754 /* Setting the FP to a constant distance from the SP:
756 P 000010 0010000 000001 SSSSSSSSSSSS = 0x04401000
757 0 111111 1111111 111111 000000000000 = 0x7ffff000
759 We treat this as part of the prologue. */
760 else if ((op
& 0x7ffff000) == 0x04401000)
762 /* Sign-extend the twelve-bit field.
763 (Isn't there a better way to do this?) */
764 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
767 last_prologue_pc
= pc
;
770 /* To spill an argument register to a scratch register:
772 P KKKKKK 0100010 IIIIII 000000000000 = 0x00880000
773 0 000000 1111111 000000 111111111111 = 0x01fc0fff
775 For the time being, we treat this as a prologue instruction,
776 assuming that GRi is an argument register. This one's kind
777 of suspicious, because it seems like it could be part of a
778 legitimate body instruction. But we only come here when the
779 source info wasn't helpful, so we have to do the best we can.
780 Hopefully once GCC and GDB agree on how to emit line number
781 info for prologues, then this code will never come into play. */
782 else if ((op
& 0x01fc0fff) == 0x00880000)
784 int gr_i
= ((op
>> 12) & 0x3f);
786 /* Make sure that the source is an arg register; if it is, we'll
787 treat it as a prologue instruction. */
788 if (is_argument_reg (gr_i
))
789 last_prologue_pc
= next_pc
;
792 /* To spill 16-bit values to the stack:
794 P KKKKKK 1010001 000010 SSSSSSSSSSSS = 0x01442000
795 0 000000 1111111 111111 000000000000 = 0x01fff000
797 And for 8-bit values, we use STB instructions.
799 P KKKKKK 1010000 000010 SSSSSSSSSSSS = 0x01402000
800 0 000000 1111111 111111 000000000000 = 0x01fff000
802 We check that GRk is really an argument register, and treat
803 all such as part of the prologue. */
804 else if ( (op
& 0x01fff000) == 0x01442000
805 || (op
& 0x01fff000) == 0x01402000)
807 int gr_k
= ((op
>> 25) & 0x3f);
809 /* Make sure that GRk is really an argument register; treat
810 it as a prologue instruction if so. */
811 if (is_argument_reg (gr_k
))
812 last_prologue_pc
= next_pc
;
815 /* To save multiple callee-saves register on the stack, at a
819 P KKKKKK 1010011 000001 SSSSSSSSSSSS = 0x014c1000
820 0 000000 1111111 111111 000000000000 = 0x01fff000
823 P KKKKKK 1010100 000001 SSSSSSSSSSSS = 0x01501000
824 0 000000 1111111 111111 000000000000 = 0x01fff000
826 We treat this as part of the prologue, and record the register's
827 saved address in the frame structure. */
828 else if ((op
& 0x01fff000) == 0x014c1000
829 || (op
& 0x01fff000) == 0x01501000)
831 int gr_k
= ((op
>> 25) & 0x3f);
835 /* Is it a stdi or a stqi? */
836 if ((op
& 0x01fff000) == 0x014c1000)
841 /* Is it really a callee-saves register? */
842 if (is_callee_saves_reg (gr_k
))
844 /* Sign-extend the twelve-bit field.
845 (Isn't there a better way to do this?) */
846 int s
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
848 for (i
= 0; i
< count
; i
++)
850 gr_saved
[gr_k
+ i
] = 1;
851 gr_sp_offset
[gr_k
+ i
] = s
+ (4 * i
);
853 last_prologue_pc
= next_pc
;
857 /* Storing any kind of integer register at any constant offset
858 from any other register.
861 P KKKKKK 0000011 IIIIII 000010 000000 = 0x000c0080
862 0 000000 1111111 000000 111111 111111 = 0x01fc0fff
865 P KKKKKK 1010010 IIIIII SSSSSSSSSSSS = 0x01480000
866 0 000000 1111111 000000 000000000000 = 0x01fc0000
868 These could be almost anything, but a lot of prologue
869 instructions fall into this pattern, so let's decode the
870 instruction once, and then work at a higher level. */
871 else if (((op
& 0x01fc0fff) == 0x000c0080)
872 || ((op
& 0x01fc0000) == 0x01480000))
874 int gr_k
= ((op
>> 25) & 0x3f);
875 int gr_i
= ((op
>> 12) & 0x3f);
878 /* Are we storing with gr0 as an offset, or using an
880 if ((op
& 0x01fc0fff) == 0x000c0080)
883 offset
= (((op
& 0xfff) - 0x800) & 0xfff) - 0x800;
885 /* If the address isn't relative to the SP or FP, it's not a
886 prologue instruction. */
887 if (gr_i
!= sp_regnum
&& gr_i
!= fp_regnum
)
889 /* Do nothing; not a prologue instruction. */
892 /* Saving the old FP in the new frame (relative to the SP). */
893 else if (gr_k
== fp_regnum
&& gr_i
== sp_regnum
)
895 gr_saved
[fp_regnum
] = 1;
896 gr_sp_offset
[fp_regnum
] = offset
;
897 last_prologue_pc
= next_pc
;
900 /* Saving callee-saves register(s) on the stack, relative to
902 else if (gr_i
== sp_regnum
903 && is_callee_saves_reg (gr_k
))
906 if (gr_i
== sp_regnum
)
907 gr_sp_offset
[gr_k
] = offset
;
909 gr_sp_offset
[gr_k
] = offset
+ fp_offset
;
910 last_prologue_pc
= next_pc
;
913 /* Saving the scratch register holding the return address. */
914 else if (lr_save_reg
!= -1
915 && gr_k
== lr_save_reg
)
917 lr_saved_on_stack
= 1;
918 if (gr_i
== sp_regnum
)
919 lr_sp_offset
= offset
;
921 lr_sp_offset
= offset
+ fp_offset
;
922 last_prologue_pc
= next_pc
;
925 /* Spilling int-sized arguments to the stack. */
926 else if (is_argument_reg (gr_k
))
927 last_prologue_pc
= next_pc
;
932 if (this_frame
&& info
)
937 /* If we know the relationship between the stack and frame
938 pointers, record the addresses of the registers we noticed.
939 Note that we have to do this as a separate step at the end,
940 because instructions may save relative to the SP, but we need
941 their addresses relative to the FP. */
943 this_base
= get_frame_register_unsigned (this_frame
, fp_regnum
);
945 this_base
= get_frame_register_unsigned (this_frame
, sp_regnum
);
947 for (i
= 0; i
< 64; i
++)
949 info
->saved_regs
[i
].set_addr (this_base
- fp_offset
952 info
->prev_sp
= this_base
- fp_offset
+ framesize
;
953 info
->base
= this_base
;
955 /* If LR was saved on the stack, record its location. */
956 if (lr_saved_on_stack
)
957 info
->saved_regs
[lr_regnum
].set_addr (this_base
- fp_offset
960 /* The call instruction moves the caller's PC in the callee's LR.
961 Since this is an unwind, do the reverse. Copy the location of LR
962 into PC (the address / regnum) so that a request for PC will be
963 converted into a request for the LR. */
964 info
->saved_regs
[pc_regnum
] = info
->saved_regs
[lr_regnum
];
966 /* Save the previous frame's computed SP value. */
967 info
->saved_regs
[sp_regnum
].set_value (info
->prev_sp
);
970 return last_prologue_pc
;
975 frv_skip_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
977 CORE_ADDR func_addr
, func_end
, new_pc
;
981 /* If the line table has entry for a line *within* the function
982 (i.e., not in the prologue, and not past the end), then that's
984 if (find_pc_partial_function (pc
, NULL
, &func_addr
, &func_end
))
986 struct symtab_and_line sal
;
988 sal
= find_pc_line (func_addr
, 0);
990 if (sal
.line
!= 0 && sal
.end
< func_end
)
996 /* The FR-V prologue is at least five instructions long (twenty bytes).
997 If we didn't find a real source location past that, then
998 do a full analysis of the prologue. */
999 if (new_pc
< pc
+ 20)
1000 new_pc
= frv_analyze_prologue (gdbarch
, pc
, 0, 0);
1006 /* Examine the instruction pointed to by PC. If it corresponds to
1007 a call to __main, return the address of the next instruction.
1008 Otherwise, return PC. */
1011 frv_skip_main_prologue (struct gdbarch
*gdbarch
, CORE_ADDR pc
)
1013 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1016 CORE_ADDR orig_pc
= pc
;
1018 if (target_read_memory (pc
, buf
, 4))
1020 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1022 /* In PIC code, GR15 may be loaded from some offset off of FP prior
1023 to the call instruction.
1025 Skip over this instruction if present. It won't be present in
1026 non-PIC code, and even in PIC code, it might not be present.
1027 (This is due to the fact that GR15, the FDPIC register, already
1028 contains the correct value.)
1030 The general form of the LDI is given first, followed by the
1031 specific instruction with the GRi and GRk filled in as FP and
1034 ldi @(GRi, d12), GRk
1035 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x00c80000
1036 0 000000 1111111 000000 000000000000 = 0x01fc0000
1038 ldi @(FP, d12), GR15
1039 P KKKKKK 0110010 IIIIII SSSSSSSSSSSS = 0x1ec82000
1040 0 001111 1111111 000010 000000000000 = 0x7ffff000
1043 if ((op
& 0x7ffff000) == 0x1ec82000)
1046 if (target_read_memory (pc
, buf
, 4))
1048 op
= extract_unsigned_integer (buf
, 4, byte_order
);
1051 /* The format of an FRV CALL instruction is as follows:
1054 P HHHHHH 0001111 LLLLLLLLLLLLLLLLLL = 0x003c0000
1055 0 000000 1111111 000000000000000000 = 0x01fc0000
1058 where label24 is constructed by concatenating the H bits with the
1059 L bits. The call target is PC + (4 * sign_ext(label24)). */
1061 if ((op
& 0x01fc0000) == 0x003c0000)
1064 CORE_ADDR call_dest
;
1065 struct bound_minimal_symbol s
;
1067 displ
= ((op
& 0xfe000000) >> 7) | (op
& 0x0003ffff);
1068 if ((displ
& 0x00800000) != 0)
1069 displ
|= ~((LONGEST
) 0x00ffffff);
1071 call_dest
= pc
+ 4 * displ
;
1072 s
= lookup_minimal_symbol_by_pc (call_dest
);
1074 if (s
.minsym
!= NULL
1075 && s
.minsym
->linkage_name () != NULL
1076 && strcmp (s
.minsym
->linkage_name (), "__main") == 0)
1086 static struct frv_unwind_cache
*
1087 frv_frame_unwind_cache (const frame_info_ptr
&this_frame
,
1088 void **this_prologue_cache
)
1090 struct gdbarch
*gdbarch
= get_frame_arch (this_frame
);
1091 struct frv_unwind_cache
*info
;
1093 if ((*this_prologue_cache
))
1094 return (struct frv_unwind_cache
*) (*this_prologue_cache
);
1096 info
= FRAME_OBSTACK_ZALLOC (struct frv_unwind_cache
);
1097 (*this_prologue_cache
) = info
;
1098 info
->saved_regs
= trad_frame_alloc_saved_regs (this_frame
);
1100 /* Prologue analysis does the rest... */
1101 frv_analyze_prologue (gdbarch
,
1102 get_frame_func (this_frame
), this_frame
, info
);
1108 frv_extract_return_value (struct type
*type
, struct regcache
*regcache
,
1111 struct gdbarch
*gdbarch
= regcache
->arch ();
1112 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1113 int len
= type
->length ();
1118 regcache_cooked_read_unsigned (regcache
, 8, &gpr8_val
);
1119 store_unsigned_integer (valbuf
, len
, byte_order
, gpr8_val
);
1125 regcache_cooked_read_unsigned (regcache
, 8, ®val
);
1126 store_unsigned_integer (valbuf
, 4, byte_order
, regval
);
1127 regcache_cooked_read_unsigned (regcache
, 9, ®val
);
1128 store_unsigned_integer ((bfd_byte
*) valbuf
+ 4, 4, byte_order
, regval
);
1131 internal_error (_("Illegal return value length: %d"), len
);
1135 frv_frame_align (struct gdbarch
*gdbarch
, CORE_ADDR sp
)
1137 /* Require dword alignment. */
1138 return align_down (sp
, 8);
1142 find_func_descr (struct gdbarch
*gdbarch
, CORE_ADDR entry_point
)
1144 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1147 CORE_ADDR start_addr
;
1149 /* If we can't find the function in the symbol table, then we assume
1150 that the function address is already in descriptor form. */
1151 if (!find_pc_partial_function (entry_point
, NULL
, &start_addr
, NULL
)
1152 || entry_point
!= start_addr
)
1155 descr
= frv_fdpic_find_canonical_descriptor (entry_point
);
1160 /* Construct a non-canonical descriptor from space allocated on
1163 descr
= value_as_long (value_allocate_space_in_inferior (8));
1164 store_unsigned_integer (valbuf
, 4, byte_order
, entry_point
);
1165 write_memory (descr
, valbuf
, 4);
1166 store_unsigned_integer (valbuf
, 4, byte_order
,
1167 frv_fdpic_find_global_pointer (entry_point
));
1168 write_memory (descr
+ 4, valbuf
, 4);
1173 frv_convert_from_func_ptr_addr (struct gdbarch
*gdbarch
, CORE_ADDR addr
,
1174 struct target_ops
*targ
)
1176 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1177 CORE_ADDR entry_point
;
1178 CORE_ADDR got_address
;
1180 entry_point
= get_target_memory_unsigned (targ
, addr
, 4, byte_order
);
1181 got_address
= get_target_memory_unsigned (targ
, addr
+ 4, 4, byte_order
);
1183 if (got_address
== frv_fdpic_find_global_pointer (entry_point
))
1190 frv_push_dummy_call (struct gdbarch
*gdbarch
, struct value
*function
,
1191 struct regcache
*regcache
, CORE_ADDR bp_addr
,
1192 int nargs
, struct value
**args
, CORE_ADDR sp
,
1193 function_call_return_method return_method
,
1194 CORE_ADDR struct_addr
)
1196 enum bfd_endian byte_order
= gdbarch_byte_order (gdbarch
);
1199 const gdb_byte
*val
;
1202 struct type
*arg_type
;
1204 enum type_code typecode
;
1208 enum frv_abi abi
= frv_abi (gdbarch
);
1209 CORE_ADDR func_addr
= find_function_addr (function
, NULL
);
1212 printf("Push %d args at sp = %x, struct_return=%d (%x)\n",
1213 nargs
, (int) sp
, struct_return
, struct_addr
);
1217 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1218 stack_space
+= align_up (args
[argnum
]->type ()->length (), 4);
1220 stack_space
-= (6 * 4);
1221 if (stack_space
> 0)
1224 /* Make sure stack is dword aligned. */
1225 sp
= align_down (sp
, 8);
1231 if (return_method
== return_method_struct
)
1232 regcache_cooked_write_unsigned (regcache
, struct_return_regnum
,
1235 for (argnum
= 0; argnum
< nargs
; ++argnum
)
1238 arg_type
= check_typedef (arg
->type ());
1239 len
= arg_type
->length ();
1240 typecode
= arg_type
->code ();
1242 if (typecode
== TYPE_CODE_STRUCT
|| typecode
== TYPE_CODE_UNION
)
1244 store_unsigned_integer (valbuf
, 4, byte_order
,
1246 typecode
= TYPE_CODE_PTR
;
1250 else if (abi
== FRV_ABI_FDPIC
1252 && typecode
== TYPE_CODE_PTR
1253 && arg_type
->target_type ()->code () == TYPE_CODE_FUNC
)
1255 /* The FDPIC ABI requires function descriptors to be passed instead
1257 CORE_ADDR addr
= extract_unsigned_integer
1258 (arg
->contents ().data (), 4, byte_order
);
1259 addr
= find_func_descr (gdbarch
, addr
);
1260 store_unsigned_integer (valbuf
, 4, byte_order
, addr
);
1261 typecode
= TYPE_CODE_PTR
;
1267 val
= arg
->contents ().data ();
1272 int partial_len
= (len
< 4 ? len
: 4);
1276 regval
= extract_unsigned_integer (val
, partial_len
, byte_order
);
1278 printf(" Argnum %d data %x -> reg %d\n",
1279 argnum
, (int) regval
, argreg
);
1281 regcache_cooked_write_unsigned (regcache
, argreg
, regval
);
1287 printf(" Argnum %d data %x -> offset %d (%x)\n",
1288 argnum
, *((int *)val
), stack_offset
,
1289 (int) (sp
+ stack_offset
));
1291 write_memory (sp
+ stack_offset
, val
, partial_len
);
1292 stack_offset
+= align_up (partial_len
, 4);
1299 /* Set the return address. For the frv, the return breakpoint is
1300 always at BP_ADDR. */
1301 regcache_cooked_write_unsigned (regcache
, lr_regnum
, bp_addr
);
1303 if (abi
== FRV_ABI_FDPIC
)
1305 /* Set the GOT register for the FDPIC ABI. */
1306 regcache_cooked_write_unsigned
1307 (regcache
, first_gpr_regnum
+ 15,
1308 frv_fdpic_find_global_pointer (func_addr
));
1311 /* Finally, update the SP register. */
1312 regcache_cooked_write_unsigned (regcache
, sp_regnum
, sp
);
1318 frv_store_return_value (struct type
*type
, struct regcache
*regcache
,
1319 const gdb_byte
*valbuf
)
1321 int len
= type
->length ();
1326 memset (val
, 0, sizeof (val
));
1327 memcpy (val
+ (4 - len
), valbuf
, len
);
1328 regcache
->cooked_write (8, val
);
1332 regcache
->cooked_write (8, valbuf
);
1333 regcache
->cooked_write (9, (bfd_byte
*) valbuf
+ 4);
1336 internal_error (_("Don't know how to return a %d-byte value."), len
);
1339 static enum return_value_convention
1340 frv_return_value (struct gdbarch
*gdbarch
, struct value
*function
,
1341 struct type
*valtype
, struct regcache
*regcache
,
1342 gdb_byte
*readbuf
, const gdb_byte
*writebuf
)
1344 int struct_return
= valtype
->code () == TYPE_CODE_STRUCT
1345 || valtype
->code () == TYPE_CODE_UNION
1346 || valtype
->code () == TYPE_CODE_ARRAY
;
1348 if (writebuf
!= NULL
)
1350 gdb_assert (!struct_return
);
1351 frv_store_return_value (valtype
, regcache
, writebuf
);
1354 if (readbuf
!= NULL
)
1356 gdb_assert (!struct_return
);
1357 frv_extract_return_value (valtype
, regcache
, readbuf
);
1361 return RETURN_VALUE_STRUCT_CONVENTION
;
1363 return RETURN_VALUE_REGISTER_CONVENTION
;
1366 /* Given a GDB frame, determine the address of the calling function's
1367 frame. This will be used to create a new GDB frame struct. */
1370 frv_frame_this_id (const frame_info_ptr
&this_frame
,
1371 void **this_prologue_cache
, struct frame_id
*this_id
)
1373 struct frv_unwind_cache
*info
1374 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1377 struct bound_minimal_symbol msym_stack
;
1380 /* The FUNC is easy. */
1381 func
= get_frame_func (this_frame
);
1383 /* Check if the stack is empty. */
1384 msym_stack
= lookup_minimal_symbol ("_stack", NULL
, NULL
);
1385 if (msym_stack
.minsym
&& info
->base
== msym_stack
.value_address ())
1388 /* Hopefully the prologue analysis either correctly determined the
1389 frame's base (which is the SP from the previous frame), or set
1390 that base to "NULL". */
1391 base
= info
->prev_sp
;
1395 id
= frame_id_build (base
, func
);
1399 static struct value
*
1400 frv_frame_prev_register (const frame_info_ptr
&this_frame
,
1401 void **this_prologue_cache
, int regnum
)
1403 struct frv_unwind_cache
*info
1404 = frv_frame_unwind_cache (this_frame
, this_prologue_cache
);
1405 return trad_frame_get_prev_register (this_frame
, info
->saved_regs
, regnum
);
1408 static const struct frame_unwind frv_frame_unwind
= {
1411 default_frame_unwind_stop_reason
,
1413 frv_frame_prev_register
,
1415 default_frame_sniffer
1419 frv_frame_base_address (const frame_info_ptr
&this_frame
, void **this_cache
)
1421 struct frv_unwind_cache
*info
1422 = frv_frame_unwind_cache (this_frame
, this_cache
);
1426 static const struct frame_base frv_frame_base
= {
1428 frv_frame_base_address
,
1429 frv_frame_base_address
,
1430 frv_frame_base_address
1433 static struct gdbarch
*
1434 frv_gdbarch_init (struct gdbarch_info info
, struct gdbarch_list
*arches
)
1438 /* Check to see if we've already built an appropriate architecture
1439 object for this executable. */
1440 arches
= gdbarch_list_lookup_by_info (arches
, &info
);
1442 return arches
->gdbarch
;
1444 /* Select the right tdep structure for this variant. */
1445 gdbarch
*gdbarch
= gdbarch_alloc (&info
, new_variant ());
1446 frv_gdbarch_tdep
*var
= gdbarch_tdep
<frv_gdbarch_tdep
> (gdbarch
);
1448 switch (info
.bfd_arch_info
->mach
)
1451 case bfd_mach_frvsimple
:
1452 case bfd_mach_fr300
:
1453 case bfd_mach_fr500
:
1454 case bfd_mach_frvtomcat
:
1455 case bfd_mach_fr550
:
1456 set_variant_num_gprs (var
, 64);
1457 set_variant_num_fprs (var
, 64);
1460 case bfd_mach_fr400
:
1461 case bfd_mach_fr450
:
1462 set_variant_num_gprs (var
, 32);
1463 set_variant_num_fprs (var
, 32);
1467 /* Never heard of this variant. */
1471 /* Extract the ELF flags, if available. */
1472 if (info
.abfd
&& bfd_get_flavour (info
.abfd
) == bfd_target_elf_flavour
)
1473 elf_flags
= elf_elfheader (info
.abfd
)->e_flags
;
1475 if (elf_flags
& EF_FRV_FDPIC
)
1476 set_variant_abi_fdpic (var
);
1478 if (elf_flags
& EF_FRV_CPU_FR450
)
1479 set_variant_scratch_registers (var
);
1481 set_gdbarch_short_bit (gdbarch
, 16);
1482 set_gdbarch_int_bit (gdbarch
, 32);
1483 set_gdbarch_long_bit (gdbarch
, 32);
1484 set_gdbarch_long_long_bit (gdbarch
, 64);
1485 set_gdbarch_float_bit (gdbarch
, 32);
1486 set_gdbarch_double_bit (gdbarch
, 64);
1487 set_gdbarch_long_double_bit (gdbarch
, 64);
1488 set_gdbarch_ptr_bit (gdbarch
, 32);
1490 set_gdbarch_num_regs (gdbarch
, frv_num_regs
);
1491 set_gdbarch_num_pseudo_regs (gdbarch
, frv_num_pseudo_regs
);
1493 set_gdbarch_sp_regnum (gdbarch
, sp_regnum
);
1494 set_gdbarch_deprecated_fp_regnum (gdbarch
, fp_regnum
);
1495 set_gdbarch_pc_regnum (gdbarch
, pc_regnum
);
1497 set_gdbarch_register_name (gdbarch
, frv_register_name
);
1498 set_gdbarch_register_type (gdbarch
, frv_register_type
);
1499 set_gdbarch_register_sim_regno (gdbarch
, frv_register_sim_regno
);
1501 set_gdbarch_pseudo_register_read (gdbarch
, frv_pseudo_register_read
);
1502 set_gdbarch_deprecated_pseudo_register_write (gdbarch
,
1503 frv_pseudo_register_write
);
1505 set_gdbarch_skip_prologue (gdbarch
, frv_skip_prologue
);
1506 set_gdbarch_skip_main_prologue (gdbarch
, frv_skip_main_prologue
);
1507 set_gdbarch_breakpoint_kind_from_pc (gdbarch
, frv_breakpoint::kind_from_pc
);
1508 set_gdbarch_sw_breakpoint_from_kind (gdbarch
, frv_breakpoint::bp_from_kind
);
1509 set_gdbarch_adjust_breakpoint_address
1510 (gdbarch
, frv_adjust_breakpoint_address
);
1512 set_gdbarch_return_value (gdbarch
, frv_return_value
);
1515 set_gdbarch_frame_align (gdbarch
, frv_frame_align
);
1516 frame_base_set_default (gdbarch
, &frv_frame_base
);
1517 /* We set the sniffer lower down after the OSABI hooks have been
1520 /* Settings for calling functions in the inferior. */
1521 set_gdbarch_push_dummy_call (gdbarch
, frv_push_dummy_call
);
1523 /* Settings that should be unnecessary. */
1524 set_gdbarch_inner_than (gdbarch
, core_addr_lessthan
);
1526 /* Hardware watchpoint / breakpoint support. */
1527 switch (info
.bfd_arch_info
->mach
)
1530 case bfd_mach_frvsimple
:
1531 case bfd_mach_fr300
:
1532 case bfd_mach_fr500
:
1533 case bfd_mach_frvtomcat
:
1534 /* fr500-style hardware debugging support. */
1535 var
->num_hw_watchpoints
= 4;
1536 var
->num_hw_breakpoints
= 4;
1539 case bfd_mach_fr400
:
1540 case bfd_mach_fr450
:
1541 /* fr400-style hardware debugging support. */
1542 var
->num_hw_watchpoints
= 2;
1543 var
->num_hw_breakpoints
= 4;
1547 /* Otherwise, assume we don't have hardware debugging support. */
1548 var
->num_hw_watchpoints
= 0;
1549 var
->num_hw_breakpoints
= 0;
1553 if (frv_abi (gdbarch
) == FRV_ABI_FDPIC
)
1554 set_gdbarch_convert_from_func_ptr_addr (gdbarch
,
1555 frv_convert_from_func_ptr_addr
);
1557 set_gdbarch_so_ops (gdbarch
, &frv_so_ops
);
1559 /* Hook in ABI-specific overrides, if they have been registered. */
1560 gdbarch_init_osabi (info
, gdbarch
);
1562 /* Set the fallback (prologue based) frame sniffer. */
1563 frame_unwind_append_unwinder (gdbarch
, &frv_frame_unwind
);
1565 /* Enable TLS support. */
1566 set_gdbarch_fetch_tls_load_module_address (gdbarch
,
1567 frv_fetch_objfile_link_map
);
1572 void _initialize_frv_tdep ();
1574 _initialize_frv_tdep ()
1576 gdbarch_register (bfd_arch_frv
, frv_gdbarch_init
);