sim/bfin/dv-bfin_ebiu_ddrc.c

   1 /* Blackfin External Bus Interface Unit (EBIU) DDR Controller (DDRC) Model.
   2
   3    Copyright (C) 2010-2023 Free Software Foundation, Inc.
   4    Contributed by Analog Devices, Inc.
   5
   6    This file is part of simulators.
   7
   8    This program is free software; you can redistribute it and/or modify
   9    it under the terms of the GNU General Public License as published by
  10    the Free Software Foundation; either version 3 of the License, or
  11    (at your option) any later version.
  12
  13    This program is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  20
  21 /* This must come before any other includes.  */
  22 #include "defs.h"
  23
  24 #include "sim-main.h"
  25 #include "devices.h"
  26 #include "dv-bfin_ebiu_ddrc.h"
  27
  28 struct bfin_ebiu_ddrc
  29 {
  30   bu32 base, reg_size, bank_size;
  31
  32   /* Order after here is important -- matches hardware MMR layout.  */
  33   union {
  34     struct { bu32 ddrctl0, ddrctl1, ddrctl2, ddrctl3; };
  35     bu32 ddrctl[4];
  36   };
  37   bu32 ddrque, erradd;
  38   bu16 BFIN_MMR_16(errmst);
  39   bu16 BFIN_MMR_16(rstctl);
  40   bu32 ddrbrc[8], ddrbwc[8];
  41   bu32 ddracct, ddrtact, ddrarct;
  42   bu32 ddrgc[4];
  43   bu32 ddrmcen, ddrmccl;
  44 };
  45 #define mmr_base()      offsetof(struct bfin_ebiu_ddrc, ddrctl0)
  46 #define mmr_offset(mmr) (offsetof(struct bfin_ebiu_ddrc, mmr) - mmr_base())
  47
  48 static const char * const mmr_names[] =
  49 {
  50   "EBIU_DDRCTL0", "EBIU_DDRCTL1", "EBIU_DDRCTL2", "EBIU_DDRCTL3", "EBIU_DDRQUE",
  51   "EBIU_ERRADD", "EBIU_ERRMST", "EBIU_RSTCTL", "EBIU_DDRBRC0", "EBIU_DDRBRC1",
  52   "EBIU_DDRBRC2", "EBIU_DDRBRC3", "EBIU_DDRBRC4", "EBIU_DDRBRC5",
  53   "EBIU_DDRBRC6", "EBIU_DDRBRC7", "EBIU_DDRBWC0", "EBIU_DDRBWC1"
  54   "EBIU_DDRBWC2", "EBIU_DDRBWC3", "EBIU_DDRBWC4", "EBIU_DDRBWC5",
  55   "EBIU_DDRBWC6", "EBIU_DDRBWC7", "EBIU_DDRACCT", "EBIU_DDRTACT",
  56   "EBIU_ARCT", "EBIU_DDRGC0", "EBIU_DDRGC1", "EBIU_DDRGC2", "EBIU_DDRGC3",
  57   "EBIU_DDRMCEN", "EBIU_DDRMCCL",
  58 };
  59 #define mmr_name(off) mmr_names[(off) / 4]
  60
  61 static unsigned
  62 bfin_ebiu_ddrc_io_write_buffer (struct hw *me, const void *source,
  63                                int space, address_word addr, unsigned nr_bytes)
  64 {
  65   struct bfin_ebiu_ddrc *ddrc = hw_data (me);
  66   bu32 mmr_off;
  67   bu32 value;
  68   bu16 *value16p;
  69   bu32 *value32p;
  70   void *valuep;
  71
  72   /* Invalid access mode is higher priority than missing register.  */
  73   if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
  74     return 0;
  75
  76   if (nr_bytes == 4)
  77     value = dv_load_4 (source);
  78   else
  79     value = dv_load_2 (source);
  80
  81   mmr_off = addr - ddrc->base;
  82   valuep = (void *)((uintptr_t)ddrc + mmr_base() + mmr_off);
  83   value16p = valuep;
  84   value32p = valuep;
  85
  86   HW_TRACE_WRITE ();
  87
  88   switch (mmr_off)
  89     {
  90     case mmr_offset(errmst):
  91     case mmr_offset(rstctl):
  92       if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, true))
  93         return 0;
  94       *value16p = value;
  95       break;
  96     default:
  97       if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, true))
  98         return 0;
  99       *value32p = value;
 100       break;
 101     }
 102
 103   return nr_bytes;
 104 }
 105
 106 static unsigned
 107 bfin_ebiu_ddrc_io_read_buffer (struct hw *me, void *dest,
 108                               int space, address_word addr, unsigned nr_bytes)
 109 {
 110   struct bfin_ebiu_ddrc *ddrc = hw_data (me);
 111   bu32 mmr_off;
 112   bu32 *value32p;
 113   bu16 *value16p;
 114   void *valuep;
 115
 116   /* Invalid access mode is higher priority than missing register.  */
 117   if (!dv_bfin_mmr_require_16_32 (me, addr, nr_bytes, true))
 118     return 0;
 119
 120   mmr_off = addr - ddrc->base;
 121   valuep = (void *)((uintptr_t)ddrc + mmr_base() + mmr_off);
 122   value16p = valuep;
 123   value32p = valuep;
 124
 125   HW_TRACE_READ ();
 126
 127   switch (mmr_off)
 128     {
 129     case mmr_offset(errmst):
 130     case mmr_offset(rstctl):
 131       if (!dv_bfin_mmr_require_16 (me, addr, nr_bytes, false))
 132         return 0;
 133       dv_store_2 (dest, *value16p);
 134       break;
 135     default:
 136       if (!dv_bfin_mmr_require_32 (me, addr, nr_bytes, false))
 137         return 0;
 138       dv_store_4 (dest, *value32p);
 139       break;
 140     }
 141
 142   return nr_bytes;
 143 }
 144
 145 static void
 146 attach_bfin_ebiu_ddrc_regs (struct hw *me, struct bfin_ebiu_ddrc *ddrc)
 147 {
 148   address_word attach_address;
 149   int attach_space;
 150   unsigned attach_size;
 151   reg_property_spec reg;
 152
 153   if (hw_find_property (me, "reg") == NULL)
 154     hw_abort (me, "Missing \"reg\" property");
 155
 156   if (!hw_find_reg_array_property (me, "reg", 0, &reg))
 157     hw_abort (me, "\"reg\" property must contain three addr/size entries");
 158
 159   hw_unit_address_to_attach_address (hw_parent (me),
 160                                      &reg.address,
 161                                      &attach_space, &attach_address, me);
 162   hw_unit_size_to_attach_size (hw_parent (me), &reg.size, &attach_size, me);
 163
 164   if (attach_size != BFIN_MMR_EBIU_DDRC_SIZE)
 165     hw_abort (me, "\"reg\" size must be %#x", BFIN_MMR_EBIU_DDRC_SIZE);
 166
 167   hw_attach_address (hw_parent (me),
 168                      0, attach_space, attach_address, attach_size, me);
 169
 170   ddrc->base = attach_address;
 171 }
 172
 173 static void
 174 bfin_ebiu_ddrc_finish (struct hw *me)
 175 {
 176   struct bfin_ebiu_ddrc *ddrc;
 177
 178   ddrc = HW_ZALLOC (me, struct bfin_ebiu_ddrc);
 179
 180   set_hw_data (me, ddrc);
 181   set_hw_io_read_buffer (me, bfin_ebiu_ddrc_io_read_buffer);
 182   set_hw_io_write_buffer (me, bfin_ebiu_ddrc_io_write_buffer);
 183
 184   attach_bfin_ebiu_ddrc_regs (me, ddrc);
 185
 186   /* Initialize the DDRC.  */
 187   ddrc->ddrctl0 = 0x098E8411;
 188   ddrc->ddrctl1 = 0x10026223;
 189   ddrc->ddrctl2 = 0x00000021;
 190   ddrc->ddrctl3 = 0x00000003; /* XXX: MDDR is 0x20 ...  */
 191   ddrc->ddrque = 0x00001115;
 192   ddrc->rstctl = 0x0002;
 193 }
 194
 195 const struct hw_descriptor dv_bfin_ebiu_ddrc_descriptor[] =
 196 {
 197   {"bfin_ebiu_ddrc", bfin_ebiu_ddrc_finish,},
 198   {NULL, NULL},
 199 };