src/main/drivers/timer_stm32f4xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include "platform.h"
  22
  23 #include "common/utils.h"
  24
  25 #include "drivers/dma.h"
  26 #include "drivers/io.h"
  27 #include "drivers/timer_def.h"
  28
  29 #include "stm32f4xx.h"
  30 #include "rcc.h"
  31 #include "timer.h"
  32
  33
  34 const timerDef_t timerDefinitions[HARDWARE_TIMER_DEFINITION_COUNT] = {
  35     { .TIMx = TIM1,  .rcc = RCC_APB2(TIM1),  .inputIrq = TIM1_CC_IRQn},
  36     { .TIMx = TIM2,  .rcc = RCC_APB1(TIM2),  .inputIrq = TIM2_IRQn},
  37     { .TIMx = TIM3,  .rcc = RCC_APB1(TIM3),  .inputIrq = TIM3_IRQn},
  38     { .TIMx = TIM4,  .rcc = RCC_APB1(TIM4),  .inputIrq = TIM4_IRQn},
  39     { .TIMx = TIM5,  .rcc = RCC_APB1(TIM5),  .inputIrq = TIM5_IRQn},
  40     { .TIMx = TIM6,  .rcc = RCC_APB1(TIM6),  .inputIrq = 0},
  41     { .TIMx = TIM7,  .rcc = RCC_APB1(TIM7),  .inputIrq = 0},
  42 #if !defined(STM32F411xE) && !defined(STM32F446xx)
  43     { .TIMx = TIM8,  .rcc = RCC_APB2(TIM8),  .inputIrq = TIM8_CC_IRQn},
  44 #endif
  45     { .TIMx = TIM9,  .rcc = RCC_APB2(TIM9),  .inputIrq = TIM1_BRK_TIM9_IRQn},
  46     { .TIMx = TIM10, .rcc = RCC_APB2(TIM10), .inputIrq = TIM1_UP_TIM10_IRQn},
  47     { .TIMx = TIM11, .rcc = RCC_APB2(TIM11), .inputIrq = TIM1_TRG_COM_TIM11_IRQn},
  48 #ifndef STM32F411xE
  49     { .TIMx = TIM12, .rcc = RCC_APB1(TIM12), .inputIrq = TIM8_BRK_TIM12_IRQn},
  50     { .TIMx = TIM13, .rcc = RCC_APB1(TIM13), .inputIrq = TIM8_UP_TIM13_IRQn},
  51     { .TIMx = TIM14, .rcc = RCC_APB1(TIM14), .inputIrq = TIM8_TRG_COM_TIM14_IRQn},
  52 #endif
  53 };
  54
  55 #if defined(USE_TIMER_MGMT)
  56 const timerHardware_t fullTimerHardware[FULL_TIMER_CHANNEL_COUNT] = {
  57     // Auto-generated from 'timer_def.h'
  58 //PORTA
  59     DEF_TIM(TIM2, CH1, PA0, TIM_USE_ANY, 0, 0),
  60     DEF_TIM(TIM2, CH2, PA1, TIM_USE_ANY, 0, 0),
  61     DEF_TIM(TIM2, CH3, PA2, TIM_USE_ANY, 0, 0),
  62     DEF_TIM(TIM2, CH4, PA3, TIM_USE_ANY, 0, 0),
  63     DEF_TIM(TIM2, CH1, PA5, TIM_USE_ANY, 0, 0),
  64     DEF_TIM(TIM1, CH1N, PA7, TIM_USE_ANY, 0, 0),
  65     DEF_TIM(TIM1, CH1, PA8, TIM_USE_ANY, 0, 0),
  66     DEF_TIM(TIM1, CH2, PA9, TIM_USE_ANY, 0, 0),
  67     DEF_TIM(TIM1, CH3, PA10, TIM_USE_ANY, 0, 0),
  68     DEF_TIM(TIM1, CH1N, PA11, TIM_USE_ANY, 0, 0),
  69     DEF_TIM(TIM2, CH1, PA15, TIM_USE_ANY, 0, 0),
  70
  71     DEF_TIM(TIM5, CH1, PA0, TIM_USE_ANY, 0, 0),
  72     DEF_TIM(TIM5, CH2, PA1, TIM_USE_ANY, 0, 0),
  73     DEF_TIM(TIM5, CH3, PA2, TIM_USE_ANY, 0, 0),
  74     DEF_TIM(TIM5, CH4, PA3, TIM_USE_ANY, 0, 0),
  75     DEF_TIM(TIM3, CH1, PA6, TIM_USE_ANY, 0, 0),
  76     DEF_TIM(TIM3, CH2, PA7, TIM_USE_ANY, 0, 0),
  77
  78     DEF_TIM(TIM9, CH1, PA2, TIM_USE_ANY, 0, 0),
  79     DEF_TIM(TIM9, CH2, PA3, TIM_USE_ANY, 0, 0),
  80     DEF_TIM(TIM8, CH1N, PA5, TIM_USE_ANY, 0, 0),
  81     DEF_TIM(TIM8, CH1N, PA7, TIM_USE_ANY, 0, 0),
  82
  83     DEF_TIM(TIM13, CH1, PA6, TIM_USE_ANY, 0, 0),
  84     DEF_TIM(TIM14, CH1, PA7, TIM_USE_ANY, 0, 0),
  85
  86 //PORTB
  87     DEF_TIM(TIM1, CH2N, PB0, TIM_USE_ANY, 0, 0),
  88     DEF_TIM(TIM1, CH3N, PB1, TIM_USE_ANY, 0, 0),
  89     DEF_TIM(TIM2, CH2, PB3, TIM_USE_ANY, 0, 0),
  90     DEF_TIM(TIM2, CH3, PB10, TIM_USE_ANY, 0, 0),
  91     DEF_TIM(TIM2, CH4, PB11, TIM_USE_ANY, 0, 0),
  92     DEF_TIM(TIM1, CH1N, PB13, TIM_USE_ANY, 0, 0),
  93     DEF_TIM(TIM1, CH2N, PB14, TIM_USE_ANY, 0, 0),
  94     DEF_TIM(TIM1, CH3N, PB15, TIM_USE_ANY, 0, 0),
  95
  96     DEF_TIM(TIM3, CH3, PB0, TIM_USE_ANY, 0, 0),
  97     DEF_TIM(TIM3, CH4, PB1, TIM_USE_ANY, 0, 0),
  98     DEF_TIM(TIM3, CH1, PB4, TIM_USE_ANY, 0, 0),
  99     DEF_TIM(TIM3, CH2, PB5, TIM_USE_ANY, 0, 0),
 100     DEF_TIM(TIM4, CH1, PB6, TIM_USE_ANY, 0, 0),
 101     DEF_TIM(TIM4, CH2, PB7, TIM_USE_ANY, 0, 0),
 102     DEF_TIM(TIM4, CH3, PB8, TIM_USE_ANY, 0, 0),
 103     DEF_TIM(TIM4, CH4, PB9, TIM_USE_ANY, 0, 0),
 104
 105     DEF_TIM(TIM8, CH2N, PB0, TIM_USE_ANY, 0, 0),
 106     DEF_TIM(TIM8, CH3N, PB1, TIM_USE_ANY, 0, 0),
 107     DEF_TIM(TIM10, CH1, PB8, TIM_USE_ANY, 0, 0),
 108     DEF_TIM(TIM11, CH1, PB9, TIM_USE_ANY, 0, 0),
 109     DEF_TIM(TIM8, CH2N, PB14, TIM_USE_ANY, 0, 0),
 110     DEF_TIM(TIM8, CH3N, PB15, TIM_USE_ANY, 0, 0),
 111
 112     DEF_TIM(TIM12, CH1, PB14, TIM_USE_ANY, 0, 0),
 113     DEF_TIM(TIM12, CH2, PB15, TIM_USE_ANY, 0, 0),
 114
 115 //PORTC
 116     DEF_TIM(TIM3, CH1, PC6, TIM_USE_ANY, 0, 0),
 117     DEF_TIM(TIM3, CH2, PC7, TIM_USE_ANY, 0, 0),
 118     DEF_TIM(TIM3, CH3, PC8, TIM_USE_ANY, 0, 0),
 119     DEF_TIM(TIM3, CH4, PC9, TIM_USE_ANY, 0, 0),
 120
 121     DEF_TIM(TIM8, CH1, PC6, TIM_USE_ANY, 0, 0),
 122     DEF_TIM(TIM8, CH2, PC7, TIM_USE_ANY, 0, 0),
 123     DEF_TIM(TIM8, CH3, PC8, TIM_USE_ANY, 0, 0),
 124     DEF_TIM(TIM8, CH4, PC9, TIM_USE_ANY, 0, 0),
 125
 126 //PORTD
 127     DEF_TIM(TIM4, CH1, PD12, TIM_USE_ANY, 0, 0),
 128     DEF_TIM(TIM4, CH2, PD13, TIM_USE_ANY, 0, 0),
 129     DEF_TIM(TIM4, CH3, PD14, TIM_USE_ANY, 0, 0),
 130     DEF_TIM(TIM4, CH4, PD15, TIM_USE_ANY, 0, 0),
 131
 132 //PORTE
 133     DEF_TIM(TIM1, CH1N, PE8, TIM_USE_ANY, 0, 0),
 134     DEF_TIM(TIM1, CH1, PE9, TIM_USE_ANY, 0, 0),
 135     DEF_TIM(TIM1, CH2N, PE10, TIM_USE_ANY, 0, 0),
 136     DEF_TIM(TIM1, CH2, PE11, TIM_USE_ANY, 0, 0),
 137     DEF_TIM(TIM1, CH3N, PE12, TIM_USE_ANY, 0, 0),
 138     DEF_TIM(TIM1, CH3, PE13, TIM_USE_ANY, 0, 0),
 139     DEF_TIM(TIM1, CH4, PE14, TIM_USE_ANY, 0, 0),
 140
 141     DEF_TIM(TIM9, CH1, PE5, TIM_USE_ANY, 0, 0),
 142     DEF_TIM(TIM9, CH2, PE6, TIM_USE_ANY, 0, 0),
 143
 144 //PORTF
 145     DEF_TIM(TIM10, CH1, PF6, TIM_USE_ANY, 0, 0),
 146     DEF_TIM(TIM11, CH1, PF7, TIM_USE_ANY, 0, 0),
 147 };
 148 #endif
 149
 150
 151 /*
 152     need a mapping from dma and timers to pins, and the values should all be set here to the dmaMotors array.
 153     this mapping could be used for both these motors and for led strip.
 154
 155     only certain pins have OC output (already used in normal PWM et al) but then
 156     there are only certain DMA streams/channels available for certain timers and channels.
 157      *** (this may highlight some hardware limitations on some targets) ***
 158
 159     DMA1
 160
 161     Channel Stream0     Stream1     Stream2     Stream3     Stream4     Stream5     Stream6     Stream7
 162     0
 163     1
 164     2       TIM4_CH1                            TIM4_CH2                                        TIM4_CH3
 165     3                   TIM2_CH3                                        TIM2_CH1    TIM2_CH1    TIM2_CH4
 166                                                                                     TIM2_CH4
 167     4
 168     5                               TIM3_CH4                TIM3_CH1    TIM3_CH2                TIM3_CH3
 169     6       TIM5_CH3    TIM5_CH4    TIM5_CH1    TIM5_CH4    TIM5_CH2
 170     7
 171
 172     DMA2
 173
 174     Channel Stream0     Stream1     Stream2     Stream3     Stream4     Stream5     Stream6     Stream7
 175     0                               TIM8_CH1                                        TIM1_CH1
 176                                     TIM8_CH2                                        TIM1_CH2
 177                                     TIM8_CH3                                        TIM1_CH3
 178     1
 179     2
 180     3
 181     4
 182     5
 183     6       TIM1_CH1    TIM1_CH2    TIM1_CH1                TIM1_CH4                TIM1_CH3
 184     7                   TIM8_CH1    TIM8_CH2    TIM8_CH3                                        TIM8_CH4
 185 */
 186
 187 uint32_t timerClock(TIM_TypeDef *tim)
 188 {
 189 #if defined (STM32F411xE)
 190     UNUSED(tim);
 191     return SystemCoreClock;
 192 #elif defined (STM32F40_41xxx) || defined (STM32F446xx)
 193     if (tim == TIM8 || tim == TIM1 || tim == TIM9 || tim == TIM10 || tim == TIM11) {
 194         return SystemCoreClock;
 195     } else {
 196         return SystemCoreClock / 2;
 197     }
 198 #else
 199     #error "No timer clock defined correctly for MCU"
 200 #endif
 201 }