src/main/target/system_stm32f4xx.c

   1 /**
   2   ******************************************************************************
   3   * @file    system_stm32f4xx.c
   4   * @author  MCD Application Team
   5   * @version V1.6.1
   6   * @date    21-October-2015
   7   * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
   8   *          This file contains the system clock configuration for STM32F4xx devices.
   9   *
  10   * 1.  This file provides two functions and one global variable to be called from
  11   *     user application:
  12   *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
  13   *                      and Divider factors, AHB/APBx prescalers and Flash settings),
  14   *                      depending on the configuration made in the clock xls tool.
  15   *                      This function is called at startup just after reset and
  16   *                      before branch to main program. This call is made inside
  17   *                      the "startup_stm32f4xx.s" file.
  18   *
  19   *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
  20   *                                  by the user application to setup the SysTick
  21   *                                  timer or configure other parameters.
  22   *
  23   *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
  24   *                                 be called whenever the core clock is changed
  25   *                                 during program execution.
  26   *
  27   * 2. After each device reset the HSI (16 MHz) is used as system clock source.
  28   *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
  29   *    configure the system clock before to branch to main program.
  30   *
  31   * 3. If the system clock source selected by user fails to startup, the SystemInit()
  32   *    function will do nothing and HSI still used as system clock source. User can
  33   *    add some code to deal with this issue inside the SetSysClock() function.
  34   *
  35   * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
  36   *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
  37   *    through PLL, and you are using different crystal you have to adapt the HSE
  38   *    value to your own configuration.
  39   *
  40   * 5. This file configures the system clock as follows:
  41   *=============================================================================
  42   *=============================================================================
  43   *                    Supported STM32F40xxx/41xxx devices
  44   *-----------------------------------------------------------------------------
  45   *        System Clock source                    | PLL (HSE)
  46   *-----------------------------------------------------------------------------
  47   *        SYSCLK(Hz)                             | 168000000
  48   *-----------------------------------------------------------------------------
  49   *        HCLK(Hz)                               | 168000000
  50   *-----------------------------------------------------------------------------
  51   *        AHB Prescaler                          | 1
  52   *-----------------------------------------------------------------------------
  53   *        APB1 Prescaler                         | 4
  54   *-----------------------------------------------------------------------------
  55   *        APB2 Prescaler                         | 2
  56   *-----------------------------------------------------------------------------
  57   *        HSE Frequency(Hz)                      | 8000000
  58   *-----------------------------------------------------------------------------
  59   *        PLL_M                                  | 10
  60   *-----------------------------------------------------------------------------
  61   *        PLL_N                                  | 420
  62   *-----------------------------------------------------------------------------
  63   *        PLL_P                                  | 2
  64   *-----------------------------------------------------------------------------
  65   *        PLL_Q                                  | 7
  66   *-----------------------------------------------------------------------------
  67   *        PLLI2S_N                               | NA
  68   *-----------------------------------------------------------------------------
  69   *        PLLI2S_R                               | NA
  70   *-----------------------------------------------------------------------------
  71   *        I2S input clock                        | NA
  72   *-----------------------------------------------------------------------------
  73   *        VDD(V)                                 | 3.3
  74   *-----------------------------------------------------------------------------
  75   *        Main regulator output voltage          | Scale1 mode
  76   *-----------------------------------------------------------------------------
  77   *        Flash Latency(WS)                      | 5
  78   *-----------------------------------------------------------------------------
  79   *        Prefetch Buffer                        | ON
  80   *-----------------------------------------------------------------------------
  81   *        Instruction cache                      | ON
  82   *-----------------------------------------------------------------------------
  83   *        Data cache                             | ON
  84   *-----------------------------------------------------------------------------
  85   *        Require 48MHz for USB OTG FS,          | Disabled
  86   *        SDIO and RNG clock                     |
  87   *-----------------------------------------------------------------------------
  88   *=============================================================================
  89   *=============================================================================
  90   *                    Supported STM32F42xxx/43xxx devices
  91   *-----------------------------------------------------------------------------
  92   *        System Clock source                    | PLL (HSE)
  93   *-----------------------------------------------------------------------------
  94   *        SYSCLK(Hz)                             | 180000000
  95   *-----------------------------------------------------------------------------
  96   *        HCLK(Hz)                               | 180000000
  97   *-----------------------------------------------------------------------------
  98   *        AHB Prescaler                          | 1
  99   *-----------------------------------------------------------------------------
 100   *        APB1 Prescaler                         | 4
 101   *-----------------------------------------------------------------------------
 102   *        APB2 Prescaler                         | 2
 103   *-----------------------------------------------------------------------------
 104   *        HSE Frequency(Hz)                      | 25000000
 105   *-----------------------------------------------------------------------------
 106   *        PLL_M                                  | 25
 107   *-----------------------------------------------------------------------------
 108   *        PLL_N                                  | 360
 109   *-----------------------------------------------------------------------------
 110   *        PLL_P                                  | 2
 111   *-----------------------------------------------------------------------------
 112   *        PLL_Q                                  | 7
 113   *-----------------------------------------------------------------------------
 114   *        PLLI2S_N                               | NA
 115   *-----------------------------------------------------------------------------
 116   *        PLLI2S_R                               | NA
 117   *-----------------------------------------------------------------------------
 118   *        I2S input clock                        | NA
 119   *-----------------------------------------------------------------------------
 120   *        VDD(V)                                 | 3.3
 121   *-----------------------------------------------------------------------------
 122   *        Main regulator output voltage          | Scale1 mode
 123   *-----------------------------------------------------------------------------
 124   *        Flash Latency(WS)                      | 5
 125   *-----------------------------------------------------------------------------
 126   *        Prefetch Buffer                        | ON
 127   *-----------------------------------------------------------------------------
 128   *        Instruction cache                      | ON
 129   *-----------------------------------------------------------------------------
 130   *        Data cache                             | ON
 131   *-----------------------------------------------------------------------------
 132   *        Require 48MHz for USB OTG FS,          | Disabled
 133   *        SDIO and RNG clock                     |
 134   *-----------------------------------------------------------------------------
 135   *=============================================================================
 136   *=============================================================================
 137   *                         Supported STM32F401xx devices
 138   *-----------------------------------------------------------------------------
 139   *        System Clock source                    | PLL (HSE)
 140   *-----------------------------------------------------------------------------
 141   *        SYSCLK(Hz)                             | 84000000
 142   *-----------------------------------------------------------------------------
 143   *        HCLK(Hz)                               | 84000000
 144   *-----------------------------------------------------------------------------
 145   *        AHB Prescaler                          | 1
 146   *-----------------------------------------------------------------------------
 147   *        APB1 Prescaler                         | 2
 148   *-----------------------------------------------------------------------------
 149   *        APB2 Prescaler                         | 1
 150   *-----------------------------------------------------------------------------
 151   *        HSE Frequency(Hz)                      | 25000000
 152   *-----------------------------------------------------------------------------
 153   *        PLL_M                                  | 25
 154   *-----------------------------------------------------------------------------
 155   *        PLL_N                                  | 336
 156   *-----------------------------------------------------------------------------
 157   *        PLL_P                                  | 4
 158   *-----------------------------------------------------------------------------
 159   *        PLL_Q                                  | 7
 160   *-----------------------------------------------------------------------------
 161   *        PLLI2S_N                               | NA
 162   *-----------------------------------------------------------------------------
 163   *        PLLI2S_R                               | NA
 164   *-----------------------------------------------------------------------------
 165   *        I2S input clock                        | NA
 166   *-----------------------------------------------------------------------------
 167   *        VDD(V)                                 | 3.3
 168   *-----------------------------------------------------------------------------
 169   *        Main regulator output voltage          | Scale1 mode
 170   *-----------------------------------------------------------------------------
 171   *        Flash Latency(WS)                      | 2
 172   *-----------------------------------------------------------------------------
 173   *        Prefetch Buffer                        | ON
 174   *-----------------------------------------------------------------------------
 175   *        Instruction cache                      | ON
 176   *-----------------------------------------------------------------------------
 177   *        Data cache                             | ON
 178   *-----------------------------------------------------------------------------
 179   *        Require 48MHz for USB OTG FS,          | Disabled
 180   *        SDIO and RNG clock                     |
 181   *-----------------------------------------------------------------------------
 182   *=============================================================================
 183   *=============================================================================
 184   *                Supported STM32F411xx/STM32F410xx devices
 185   *-----------------------------------------------------------------------------
 186   *        System Clock source                    | PLL (HSI)
 187   *-----------------------------------------------------------------------------
 188   *        SYSCLK(Hz)                             | 100000000
 189   *-----------------------------------------------------------------------------
 190   *        HCLK(Hz)                               | 100000000
 191   *-----------------------------------------------------------------------------
 192   *        AHB Prescaler                          | 1
 193   *-----------------------------------------------------------------------------
 194   *        APB1 Prescaler                         | 2
 195   *-----------------------------------------------------------------------------
 196   *        APB2 Prescaler                         | 1
 197   *-----------------------------------------------------------------------------
 198   *        HSI Frequency(Hz)                      | 16000000
 199   *-----------------------------------------------------------------------------
 200   *        PLL_M                                  | 16
 201   *-----------------------------------------------------------------------------
 202   *        PLL_N                                  | 400
 203   *-----------------------------------------------------------------------------
 204   *        PLL_P                                  | 4
 205   *-----------------------------------------------------------------------------
 206   *        PLL_Q                                  | 7
 207   *-----------------------------------------------------------------------------
 208   *        PLLI2S_N                               | NA
 209   *-----------------------------------------------------------------------------
 210   *        PLLI2S_R                               | NA
 211   *-----------------------------------------------------------------------------
 212   *        I2S input clock                        | NA
 213   *-----------------------------------------------------------------------------
 214   *        VDD(V)                                 | 3.3
 215   *-----------------------------------------------------------------------------
 216   *        Main regulator output voltage          | Scale1 mode
 217   *-----------------------------------------------------------------------------
 218   *        Flash Latency(WS)                      | 3
 219   *-----------------------------------------------------------------------------
 220   *        Prefetch Buffer                        | ON
 221   *-----------------------------------------------------------------------------
 222   *        Instruction cache                      | ON
 223   *-----------------------------------------------------------------------------
 224   *        Data cache                             | ON
 225   *-----------------------------------------------------------------------------
 226   *        Require 48MHz for USB OTG FS,          | Disabled
 227   *        SDIO and RNG clock                     |
 228   *-----------------------------------------------------------------------------
 229   *=============================================================================
 230   *=============================================================================
 231   *                         Supported STM32F446xx devices
 232   *-----------------------------------------------------------------------------
 233   *        System Clock source                    | PLL (HSE)
 234   *-----------------------------------------------------------------------------
 235   *        SYSCLK(Hz)                             | 180000000
 236   *-----------------------------------------------------------------------------
 237   *        HCLK(Hz)                               | 180000000
 238   *-----------------------------------------------------------------------------
 239   *        AHB Prescaler                          | 1
 240   *-----------------------------------------------------------------------------
 241   *        APB1 Prescaler                         | 4
 242   *-----------------------------------------------------------------------------
 243   *        APB2 Prescaler                         | 2
 244   *-----------------------------------------------------------------------------
 245   *        HSE Frequency(Hz)                      | 8000000
 246   *-----------------------------------------------------------------------------
 247   *        PLL_M                                  | 8
 248   *-----------------------------------------------------------------------------
 249   *        PLL_N                                  | 360
 250   *-----------------------------------------------------------------------------
 251   *        PLL_P                                  | 2
 252   *-----------------------------------------------------------------------------
 253   *        PLL_Q                                  | 7
 254   *-----------------------------------------------------------------------------
 255   *        PLL_R                                  | NA
 256   *-----------------------------------------------------------------------------
 257   *        PLLI2S_M                               | NA
 258   *-----------------------------------------------------------------------------
 259   *        PLLI2S_N                               | NA
 260   *-----------------------------------------------------------------------------
 261   *        PLLI2S_P                               | NA
 262   *-----------------------------------------------------------------------------
 263   *        PLLI2S_Q                               | NA
 264   *-----------------------------------------------------------------------------
 265   *        PLLI2S_R                               | NA
 266   *-----------------------------------------------------------------------------
 267   *        I2S input clock                        | NA
 268   *-----------------------------------------------------------------------------
 269   *        VDD(V)                                 | 3.3
 270   *-----------------------------------------------------------------------------
 271   *        Main regulator output voltage          | Scale1 mode
 272   *-----------------------------------------------------------------------------
 273   *        Flash Latency(WS)                      | 5
 274   *-----------------------------------------------------------------------------
 275   *        Prefetch Buffer                        | ON
 276   *-----------------------------------------------------------------------------
 277   *        Instruction cache                      | ON
 278   *-----------------------------------------------------------------------------
 279   *        Data cache                             | ON
 280   *-----------------------------------------------------------------------------
 281   *        Require 48MHz for USB OTG FS,          | Disabled
 282   *        SDIO and RNG clock                     |
 283   *-----------------------------------------------------------------------------
 284   *=============================================================================
 285   ******************************************************************************
 286   * @attention
 287   *
 288   * <h2><center>&copy; COPYRIGHT 2015 STMicroelectronics</center></h2>
 289   *
 290   * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
 291   * You may not use this file except in compliance with the License.
 292   * You may obtain a copy of the License at:
 293   *
 294   *        http://www.st.com/software_license_agreement_liberty_v2
 295   *
 296   * Unless required by applicable law or agreed to in writing, software
 297   * distributed under the License is distributed on an "AS IS" BASIS,
 298   * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
 299   * See the License for the specific language governing permissions and
 300   * limitations under the License.
 301   *
 302   ******************************************************************************
 303   */
 304
 305 /** @addtogroup CMSIS
 306   * @{
 307   */
 308
 309 /** @addtogroup stm32f4xx_system
 310   * @{
 311   */
 312
 313 /** @addtogroup STM32F4xx_System_Private_Includes
 314   * @{
 315   */
 316
 317 #include "stm32f4xx.h"
 318 #include "system_stm32f4xx.h"
 319
 320 uint32_t hse_value = HSE_VALUE;
 321
 322 /**
 323   * @}
 324   */
 325
 326 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
 327   * @{
 328   */
 329
 330 /**
 331   * @}
 332   */
 333
 334 /** @addtogroup STM32F4xx_System_Private_Defines
 335   * @{
 336   */
 337
 338 /************************* Miscellaneous Configuration ************************/
 339 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
 340      on STM324xG_EVAL/STM324x7I_EVAL/STM324x9I_EVAL boards as data memory  */
 341 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F469_479xx)
 342 /* #define DATA_IN_ExtSRAM */
 343 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */
 344
 345 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 346 /* #define DATA_IN_ExtSDRAM */
 347 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
 348
 349 #if defined(STM32F410xx) || defined(STM32F411xE)
 350 /*!< Uncomment the following line if you need to clock the STM32F410xx/STM32F411xE by HSE Bypass
 351      through STLINK MCO pin of STM32F103 microcontroller. The frequency cannot be changed
 352      and is fixed at 8 MHz.
 353      Hardware configuration needed for Nucleo Board:
 354      – SB54, SB55 OFF
 355      – R35 removed
 356      – SB16, SB50 ON */
 357 /* #define USE_HSE_BYPASS */
 358
 359 #if defined(USE_HSE_BYPASS)
 360 #define HSE_BYPASS_INPUT_FREQUENCY   8000000
 361 #endif /* USE_HSE_BYPASS */
 362 #endif /* STM32F410xx || STM32F411xE */
 363
 364 /*!< Uncomment the following line if you need to relocate your vector Table in
 365      Internal SRAM. */
 366 /* #define VECT_TAB_SRAM */
 367 #define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field.
 368                                    This value must be a multiple of 0x200. */
 369 /******************************************************************************/
 370
 371 /************************* PLL Parameters *************************************/
 372 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx)
 373  /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
 374 #if defined(COLIBRI)
 375  #define PLL_M      16
 376 #else
 377  #define PLL_M      8
 378 #endif
 379 #elif defined (STM32F446xx)
 380  #define PLL_M      8
 381 #elif defined (STM32F410xx) || defined (STM32F411xE)
 382  #if defined(USE_HSE_BYPASS)
 383   #define PLL_M      8
 384  #else /* !USE_HSE_BYPASS */
 385   #define PLL_M      8
 386  #endif /* USE_HSE_BYPASS */
 387 #else
 388 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
 389
 390 /* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
 391 #define PLL_Q      7
 392
 393 #if defined(STM32F446xx)
 394 /* PLL division factor for I2S, SAI, SYSTEM and SPDIF: Clock =  PLL_VCO / PLLR */
 395 #define PLL_R      7
 396 #endif /* STM32F446xx */
 397
 398 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 399 #define PLL_N      360
 400 /* SYSCLK = PLL_VCO / PLL_P */
 401 #define PLL_P      2
 402 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
 403
 404 #if defined (STM32F40_41xxx)
 405 #define PLL_N      336
 406 /* SYSCLK = PLL_VCO / PLL_P */
 407 #define PLL_P      2
 408 #endif /* STM32F40_41xxx */
 409
 410 #if defined(STM32F401xx)
 411 #define PLL_N      336
 412 /* SYSCLK = PLL_VCO / PLL_P */
 413 #define PLL_P      4
 414 #endif /* STM32F401xx */
 415
 416 #if defined(STM32F410xx) || defined(STM32F411xE)
 417 #define PLL_N      400
 418 /* SYSCLK = PLL_VCO / PLL_P */
 419 #define PLL_P      4
 420 #endif /* STM32F410xx || STM32F411xE */
 421
 422 /******************************************************************************/
 423
 424 /**
 425   * @}
 426   */
 427
 428 /** @addtogroup STM32F4xx_System_Private_Macros
 429   * @{
 430   */
 431
 432 /**
 433   * @}
 434   */
 435
 436 /** @addtogroup STM32F4xx_System_Private_Variables
 437   * @{
 438   */
 439
 440 #if defined(STM32F40_41xxx)
 441   uint32_t SystemCoreClock = 168000000;
 442 #endif /* STM32F40_41xxx */
 443
 444 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 445   uint32_t SystemCoreClock = 180000000;
 446 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
 447
 448 #if defined(STM32F401xx)
 449   uint32_t SystemCoreClock = 84000000;
 450 #endif /* STM32F401xx */
 451
 452 #if defined(STM32F410xx) || defined(STM32F411xE)
 453   uint32_t SystemCoreClock = 100000000;
 454 #endif /* STM32F410xx || STM32F401xE */
 455
 456 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
 457
 458 /**
 459   * @}
 460   */
 461
 462 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
 463   * @{
 464   */
 465
 466 void SetSysClock(void);
 467
 468 #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
 469 static void SystemInit_ExtMemCtl(void);
 470 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 471
 472 /**
 473   * @}
 474   */
 475
 476 /** @addtogroup STM32F4xx_System_Private_Functions
 477   * @{
 478   */
 479
 480 /**
 481   * @brief  Setup the microcontroller system
 482   *         Initialize the Embedded Flash Interface, the PLL and update the
 483   *         SystemFrequency variable.
 484   * @param  None
 485   * @retval None
 486   */
 487 void SystemInit(void)
 488 {
 489   /* FPU settings ------------------------------------------------------------*/
 490   #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
 491     SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));  /* set CP10 and CP11 Full Access */
 492   #endif
 493   /* Reset the RCC clock configuration to the default reset state ------------*/
 494   /* Set HSION bit */
 495   RCC->CR |= (uint32_t)0x00000001;
 496
 497   /* Reset CFGR register */
 498   RCC->CFGR = 0x00000000;
 499
 500   /* Reset HSEON, CSSON and PLLON bits */
 501   RCC->CR &= (uint32_t)0xFEF6FFFF;
 502
 503   /* Reset PLLCFGR register */
 504   RCC->PLLCFGR = 0x24003010;
 505
 506   /* Reset HSEBYP bit */
 507   RCC->CR &= (uint32_t)0xFFFBFFFF;
 508
 509   /* Disable all interrupts */
 510   RCC->CIR = 0x00000000;
 511
 512 #if defined(DATA_IN_ExtSRAM) || defined(DATA_IN_ExtSDRAM)
 513   SystemInit_ExtMemCtl();
 514 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
 515
 516   /* Configure the System clock source, PLL Multiplier and Divider factors,
 517      AHB/APBx prescalers and Flash settings ----------------------------------*/
 518   SetSysClock();
 519
 520   /* Configure the Vector Table location add offset address ------------------*/
 521 #ifdef VECT_TAB_SRAM
 522   SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
 523 #else
 524   SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
 525 #endif
 526 }
 527
 528 /**
 529    * @brief  Update SystemCoreClock variable according to Clock Register Values.
 530   *         The SystemCoreClock variable contains the core clock (HCLK), it can
 531   *         be used by the user application to setup the SysTick timer or configure
 532   *         other parameters.
 533   *
 534   * @note   Each time the core clock (HCLK) changes, this function must be called
 535   *         to update SystemCoreClock variable value. Otherwise, any configuration
 536   *         based on this variable will be incorrect.
 537   *
 538   * @note   - The system frequency computed by this function is not the real
 539   *           frequency in the chip. It is calculated based on the predefined
 540   *           constant and the selected clock source:
 541   *
 542   *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
 543   *
 544   *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
 545   *
 546   *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
 547   *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
 548   *
 549   *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
 550   *             16 MHz) but the real value may vary depending on the variations
 551   *             in voltage and temperature.
 552   *
 553   *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
 554   *              25 MHz), user has to ensure that HSE_VALUE is same as the real
 555   *              frequency of the crystal used. Otherwise, this function may
 556   *              have wrong result.
 557   *
 558   *         - The result of this function could be not correct when using fractional
 559   *           value for HSE crystal.
 560   *
 561   * @param  None
 562   * @retval None
 563   */
 564 void SystemCoreClockUpdate(void)
 565 {
 566   uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
 567 #if defined(STM32F446xx)
 568   uint32_t pllr = 2;
 569 #endif /* STM32F446xx */
 570   /* Get SYSCLK source -------------------------------------------------------*/
 571   tmp = RCC->CFGR & RCC_CFGR_SWS;
 572
 573   switch (tmp)
 574   {
 575     case 0x00:  /* HSI used as system clock source */
 576       SystemCoreClock = HSI_VALUE;
 577       break;
 578     case 0x04:  /* HSE used as system clock source */
 579       SystemCoreClock = HSE_VALUE;
 580       break;
 581     case 0x08:  /* PLL P used as system clock source */
 582        /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 583          SYSCLK = PLL_VCO / PLL_P
 584          */
 585       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 586       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 587
 588 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 589       if (pllsource != 0)
 590       {
 591         /* HSE used as PLL clock source */
 592         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 593       }
 594       else
 595       {
 596         /* HSI used as PLL clock source */
 597         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 598       }
 599 #elif defined(STM32F410xx) || defined(STM32F411xE)
 600 #if defined(USE_HSE_BYPASS)
 601       if (pllsource != 0)
 602       {
 603         /* HSE used as PLL clock source */
 604         pllvco = (HSE_BYPASS_INPUT_FREQUENCY / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 605       }
 606 #else
 607       if (pllsource == 0)
 608       {
 609         /* HSI used as PLL clock source */
 610         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 611       }
 612 #endif /* USE_HSE_BYPASS */
 613 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F446xx || STM32F469_479xx */
 614       pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
 615       SystemCoreClock = pllvco/pllp;
 616       break;
 617 #if defined(STM32F446xx)
 618       case 0x0C:  /* PLL R used as system clock source */
 619        /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
 620          SYSCLK = PLL_VCO / PLL_R
 621          */
 622       pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
 623       pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
 624       if (pllsource != 0)
 625       {
 626         /* HSE used as PLL clock source */
 627         pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 628       }
 629       else
 630       {
 631         /* HSI used as PLL clock source */
 632         pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
 633       }
 634
 635       pllr = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >>28) + 1 ) *2;
 636       SystemCoreClock = pllvco/pllr;
 637       break;
 638 #endif /* STM32F446xx */
 639     default:
 640       SystemCoreClock = HSI_VALUE;
 641       break;
 642   }
 643   /* Compute HCLK frequency --------------------------------------------------*/
 644   /* Get HCLK prescaler */
 645   tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
 646   /* HCLK frequency */
 647   SystemCoreClock >>= tmp;
 648 }
 649
 650 /**
 651   * @brief  Configures the System clock source, PLL Multiplier and Divider factors,
 652   *         AHB/APBx prescalers and Flash settings
 653   * @Note   This function should be called only once the RCC clock configuration
 654   *         is reset to the default reset state (done in SystemInit() function).
 655   * @param  None
 656   * @retval None
 657   */
 658 void SetSysClock(void)
 659 {
 660 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F446xx)|| defined(STM32F469_479xx)
 661 /******************************************************************************/
 662 /*            PLL (clocked by HSE) used as System clock source                */
 663 /******************************************************************************/
 664   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 665
 666   /* Enable HSE */
 667   RCC->CR |= ((uint32_t)RCC_CR_HSEON);
 668
 669   /* Wait till HSE is ready and if Time out is reached exit */
 670   do
 671   {
 672     HSEStatus = RCC->CR & RCC_CR_HSERDY;
 673     StartUpCounter++;
 674   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 675
 676   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 677   {
 678     HSEStatus = (uint32_t)0x01;
 679   }
 680   else
 681   {
 682     HSEStatus = (uint32_t)0x00;
 683   }
 684
 685   if (HSEStatus == (uint32_t)0x01)
 686   {
 687     /* Select regulator voltage output Scale 1 mode */
 688     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
 689     PWR->CR |= PWR_CR_VOS;
 690
 691     /* HCLK = SYSCLK / 1*/
 692     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
 693
 694 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 695     /* PCLK2 = HCLK / 2*/
 696     RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
 697
 698     /* PCLK1 = HCLK / 4*/
 699     RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
 700 #endif /* STM32F40_41xxx || STM32F427_437x || STM32F429_439xx  || STM32F446xx || STM32F469_479xx */
 701
 702 #if defined(STM32F401xx)
 703     /* PCLK2 = HCLK / 2*/
 704     RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
 705
 706     /* PCLK1 = HCLK / 4*/
 707     RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
 708 #endif /* STM32F401xx */
 709
 710 #if defined(STM32F40_41xxx) || defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F401xx) || defined(STM32F469_479xx)
 711     /* Configure the main PLL */
 712     RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
 713                    (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
 714 #endif /* STM32F40_41xxx || STM32F401xx || STM32F427_437x || STM32F429_439xx || STM32F469_479xx */
 715
 716 #if defined(STM32F446xx)
 717     /* Configure the main PLL */
 718     RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
 719                    (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24) | (PLL_R << 28);
 720 #endif /* STM32F446xx */
 721
 722     /* Enable the main PLL */
 723     RCC->CR |= RCC_CR_PLLON;
 724
 725     /* Wait till the main PLL is ready */
 726     while((RCC->CR & RCC_CR_PLLRDY) == 0)
 727     {
 728     }
 729
 730 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 731     /* Enable the Over-drive to extend the clock frequency to 180 Mhz */
 732     PWR->CR |= PWR_CR_ODEN;
 733     while((PWR->CSR & PWR_CSR_ODRDY) == 0)
 734     {
 735     }
 736     PWR->CR |= PWR_CR_ODSWEN;
 737     while((PWR->CSR & PWR_CSR_ODSWRDY) == 0)
 738     {
 739     }
 740     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
 741     FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
 742 #endif /* STM32F427_437x || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
 743
 744 #if defined(STM32F40_41xxx)
 745     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
 746     FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
 747 #endif /* STM32F40_41xxx  */
 748
 749 #if defined(STM32F401xx)
 750     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
 751     FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
 752 #endif /* STM32F401xx */
 753
 754     /* Select the main PLL as system clock source */
 755     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 756     RCC->CFGR |= RCC_CFGR_SW_PLL;
 757
 758     /* Wait till the main PLL is used as system clock source */
 759     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
 760     {
 761     }
 762   }
 763   else
 764   { /* If HSE fails to start-up, the application will have wrong clock
 765          configuration. User can add here some code to deal with this error */
 766   }
 767 #elif defined(STM32F410xx) || defined(STM32F411xE)
 768 #if defined(USE_HSE_BYPASS)
 769 /******************************************************************************/
 770 /*            PLL (clocked by HSE) used as System clock source                */
 771 /******************************************************************************/
 772   __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
 773
 774   /* Enable HSE and HSE BYPASS */
 775   RCC->CR |= ((uint32_t)RCC_CR_HSEON | RCC_CR_HSEBYP);
 776
 777   /* Wait till HSE is ready and if Time out is reached exit */
 778   do
 779   {
 780     HSEStatus = RCC->CR & RCC_CR_HSERDY;
 781     StartUpCounter++;
 782   } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
 783
 784   if ((RCC->CR & RCC_CR_HSERDY) != RESET)
 785   {
 786     HSEStatus = (uint32_t)0x01;
 787   }
 788   else
 789   {
 790     HSEStatus = (uint32_t)0x00;
 791   }
 792
 793   if (HSEStatus == (uint32_t)0x01)
 794   {
 795     /* Select regulator voltage output Scale 1 mode */
 796     RCC->APB1ENR |= RCC_APB1ENR_PWREN;
 797     PWR->CR |= PWR_CR_VOS;
 798
 799     /* HCLK = SYSCLK / 1*/
 800     RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
 801
 802     /* PCLK2 = HCLK / 2*/
 803     RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
 804
 805     /* PCLK1 = HCLK / 4*/
 806     RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
 807
 808     /* Configure the main PLL */
 809     RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
 810                    (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
 811
 812     /* Enable the main PLL */
 813     RCC->CR |= RCC_CR_PLLON;
 814
 815     /* Wait till the main PLL is ready */
 816     while((RCC->CR & RCC_CR_PLLRDY) == 0)
 817     {
 818     }
 819
 820     /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
 821     FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
 822
 823     /* Select the main PLL as system clock source */
 824     RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 825     RCC->CFGR |= RCC_CFGR_SW_PLL;
 826
 827     /* Wait till the main PLL is used as system clock source */
 828     while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
 829     {
 830     }
 831   }
 832   else
 833   { /* If HSE fails to start-up, the application will have wrong clock
 834          configuration. User can add here some code to deal with this error */
 835   }
 836 #else /* HSI will be used as PLL clock source */
 837   /* Select regulator voltage output Scale 1 mode */
 838   RCC->APB1ENR |= RCC_APB1ENR_PWREN;
 839   PWR->CR |= PWR_CR_VOS;
 840
 841   /* HCLK = SYSCLK / 1*/
 842   RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
 843
 844   /* PCLK2 = HCLK / 2*/
 845   RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
 846
 847   /* PCLK1 = HCLK / 4*/
 848   RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
 849
 850   /* Configure the main PLL */
 851   RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) | (PLL_Q << 24);
 852
 853   /* Enable the main PLL */
 854   RCC->CR |= RCC_CR_PLLON;
 855
 856   /* Wait till the main PLL is ready */
 857   while((RCC->CR & RCC_CR_PLLRDY) == 0)
 858   {
 859   }
 860
 861   /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
 862   FLASH->ACR = FLASH_ACR_PRFTEN | FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
 863
 864   /* Select the main PLL as system clock source */
 865   RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
 866   RCC->CFGR |= RCC_CFGR_SW_PLL;
 867
 868   /* Wait till the main PLL is used as system clock source */
 869   while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
 870   {
 871   }
 872 #endif /* USE_HSE_BYPASS */
 873 #endif /* STM32F40_41xxx || STM32F427_437xx || STM32F429_439xx || STM32F401xx || STM32F469_479xx */
 874 }
 875
 876 /**
 877   * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s
 878   *          before jump to __main
 879   * @param  None
 880   * @retval None
 881   */
 882 #ifdef DATA_IN_ExtSRAM
 883 /**
 884   * @brief  Setup the external memory controller.
 885   *         Called in startup_stm32f4xx.s before jump to main.
 886   *         This function configures the external SRAM mounted on STM324xG_EVAL/STM324x7I boards
 887   *         This SRAM will be used as program data memory (including heap and stack).
 888   * @param  None
 889   * @retval None
 890   */
 891 void SystemInit_ExtMemCtl(void)
 892 {
 893 /*-- GPIOs Configuration -----------------------------------------------------*/
 894 /*
 895  +-------------------+--------------------+------------------+--------------+
 896  +                       SRAM pins assignment                               +
 897  +-------------------+--------------------+------------------+--------------+
 898  | PD0  <-> FMC_D2  | PE0  <-> FMC_NBL0 | PF0  <-> FMC_A0 | PG0 <-> FMC_A10 |
 899  | PD1  <-> FMC_D3  | PE1  <-> FMC_NBL1 | PF1  <-> FMC_A1 | PG1 <-> FMC_A11 |
 900  | PD4  <-> FMC_NOE | PE3  <-> FMC_A19  | PF2  <-> FMC_A2 | PG2 <-> FMC_A12 |
 901  | PD5  <-> FMC_NWE | PE4  <-> FMC_A20  | PF3  <-> FMC_A3 | PG3 <-> FMC_A13 |
 902  | PD8  <-> FMC_D13 | PE7  <-> FMC_D4   | PF4  <-> FMC_A4 | PG4 <-> FMC_A14 |
 903  | PD9  <-> FMC_D14 | PE8  <-> FMC_D5   | PF5  <-> FMC_A5 | PG5 <-> FMC_A15 |
 904  | PD10 <-> FMC_D15 | PE9  <-> FMC_D6   | PF12 <-> FMC_A6 | PG9 <-> FMC_NE2 |
 905  | PD11 <-> FMC_A16 | PE10 <-> FMC_D7   | PF13 <-> FMC_A7 |-----------------+
 906  | PD12 <-> FMC_A17 | PE11 <-> FMC_D8   | PF14 <-> FMC_A8 |
 907  | PD13 <-> FMC_A18 | PE12 <-> FMC_D9   | PF15 <-> FMC_A9 |
 908  | PD14 <-> FMC_D0  | PE13 <-> FMC_D10  |-----------------+
 909  | PD15 <-> FMC_D1  | PE14 <-> FMC_D11  |
 910  |                  | PE15 <-> FMC_D12  |
 911  +------------------+------------------+
 912 */
 913    /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
 914   RCC->AHB1ENR   |= 0x00000078;
 915
 916   /* Connect PDx pins to FMC Alternate function */
 917   GPIOD->AFR[0]  = 0x00cc00cc;
 918   GPIOD->AFR[1]  = 0xcccccccc;
 919   /* Configure PDx pins in Alternate function mode */
 920   GPIOD->MODER   = 0xaaaa0a0a;
 921   /* Configure PDx pins speed to 100 MHz */
 922   GPIOD->OSPEEDR = 0xffff0f0f;
 923   /* Configure PDx pins Output type to push-pull */
 924   GPIOD->OTYPER  = 0x00000000;
 925   /* No pull-up, pull-down for PDx pins */
 926   GPIOD->PUPDR   = 0x00000000;
 927
 928   /* Connect PEx pins to FMC Alternate function */
 929   GPIOE->AFR[0]  = 0xcccccccc;
 930   GPIOE->AFR[1]  = 0xcccccccc;
 931   /* Configure PEx pins in Alternate function mode */
 932   GPIOE->MODER   = 0xaaaaaaaa;
 933   /* Configure PEx pins speed to 100 MHz */
 934   GPIOE->OSPEEDR = 0xffffffff;
 935   /* Configure PEx pins Output type to push-pull */
 936   GPIOE->OTYPER  = 0x00000000;
 937   /* No pull-up, pull-down for PEx pins */
 938   GPIOE->PUPDR   = 0x00000000;
 939
 940   /* Connect PFx pins to FMC Alternate function */
 941   GPIOF->AFR[0]  = 0x00cccccc;
 942   GPIOF->AFR[1]  = 0xcccc0000;
 943   /* Configure PFx pins in Alternate function mode */
 944   GPIOF->MODER   = 0xaa000aaa;
 945   /* Configure PFx pins speed to 100 MHz */
 946   GPIOF->OSPEEDR = 0xff000fff;
 947   /* Configure PFx pins Output type to push-pull */
 948   GPIOF->OTYPER  = 0x00000000;
 949   /* No pull-up, pull-down for PFx pins */
 950   GPIOF->PUPDR   = 0x00000000;
 951
 952   /* Connect PGx pins to FMC Alternate function */
 953   GPIOG->AFR[0]  = 0x00cccccc;
 954   GPIOG->AFR[1]  = 0x000000c0;
 955   /* Configure PGx pins in Alternate function mode */
 956   GPIOG->MODER   = 0x00080aaa;
 957   /* Configure PGx pins speed to 100 MHz */
 958   GPIOG->OSPEEDR = 0x000c0fff;
 959   /* Configure PGx pins Output type to push-pull */
 960   GPIOG->OTYPER  = 0x00000000;
 961   /* No pull-up, pull-down for PGx pins */
 962   GPIOG->PUPDR   = 0x00000000;
 963
 964 /*-- FMC Configuration ------------------------------------------------------*/
 965   /* Enable the FMC/FSMC interface clock */
 966   RCC->AHB3ENR         |= 0x00000001;
 967
 968 #if defined(STM32F427_437xx) || defined(STM32F429_439xx) || defined(STM32F446xx) || defined(STM32F469_479xx)
 969   /* Configure and enable Bank1_SRAM2 */
 970   FMC_Bank1->BTCR[2]  = 0x00001011;
 971   FMC_Bank1->BTCR[3]  = 0x00000201;
 972   FMC_Bank1E->BWTR[2] = 0x0fffffff;
 973 #endif /* STM32F427_437xx || STM32F429_439xx || STM32F446xx || STM32F469_479xx */
 974
 975 #if defined(STM32F40_41xxx)
 976   /* Configure and enable Bank1_SRAM2 */
 977   FSMC_Bank1->BTCR[2]  = 0x00001011;
 978   FSMC_Bank1->BTCR[3]  = 0x00000201;
 979   FSMC_Bank1E->BWTR[2] = 0x0fffffff;
 980 #endif  /* STM32F40_41xxx */
 981
 982 /*
 983   Bank1_SRAM2 is configured as follow:
 984   In case of FSMC configuration
 985   NORSRAMTimingStructure.FSMC_AddressSetupTime = 1;
 986   NORSRAMTimingStructure.FSMC_AddressHoldTime = 0;
 987   NORSRAMTimingStructure.FSMC_DataSetupTime = 2;
 988   NORSRAMTimingStructure.FSMC_BusTurnAroundDuration = 0;
 989   NORSRAMTimingStructure.FSMC_CLKDivision = 0;
 990   NORSRAMTimingStructure.FSMC_DataLatency = 0;
 991   NORSRAMTimingStructure.FSMC_AccessMode = FMC_AccessMode_A;
 992
 993   FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
 994   FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
 995   FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_SRAM;
 996   FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
 997   FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
 998   FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
 999   FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
1000   FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
1001   FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
1002   FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
1003   FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
1004   FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
1005   FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
1006   FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
1007   FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &NORSRAMTimingStructure;
1008
1009   In case of FMC configuration
1010   NORSRAMTimingStructure.FMC_AddressSetupTime = 1;
1011   NORSRAMTimingStructure.FMC_AddressHoldTime = 0;
1012   NORSRAMTimingStructure.FMC_DataSetupTime = 2;
1013   NORSRAMTimingStructure.FMC_BusTurnAroundDuration = 0;
1014   NORSRAMTimingStructure.FMC_CLKDivision = 0;
1015   NORSRAMTimingStructure.FMC_DataLatency = 0;
1016   NORSRAMTimingStructure.FMC_AccessMode = FMC_AccessMode_A;
1017
1018   FMC_NORSRAMInitStructure.FMC_Bank = FMC_Bank1_NORSRAM2;
1019   FMC_NORSRAMInitStructure.FMC_DataAddressMux = FMC_DataAddressMux_Disable;
1020   FMC_NORSRAMInitStructure.FMC_MemoryType = FMC_MemoryType_SRAM;
1021   FMC_NORSRAMInitStructure.FMC_MemoryDataWidth = FMC_MemoryDataWidth_16b;
1022   FMC_NORSRAMInitStructure.FMC_BurstAccessMode = FMC_BurstAccessMode_Disable;
1023   FMC_NORSRAMInitStructure.FMC_AsynchronousWait = FMC_AsynchronousWait_Disable;
1024   FMC_NORSRAMInitStructure.FMC_WaitSignalPolarity = FMC_WaitSignalPolarity_Low;
1025   FMC_NORSRAMInitStructure.FMC_WrapMode = FMC_WrapMode_Disable;
1026   FMC_NORSRAMInitStructure.FMC_WaitSignalActive = FMC_WaitSignalActive_BeforeWaitState;
1027   FMC_NORSRAMInitStructure.FMC_WriteOperation = FMC_WriteOperation_Enable;
1028   FMC_NORSRAMInitStructure.FMC_WaitSignal = FMC_WaitSignal_Disable;
1029   FMC_NORSRAMInitStructure.FMC_ExtendedMode = FMC_ExtendedMode_Disable;
1030   FMC_NORSRAMInitStructure.FMC_WriteBurst = FMC_WriteBurst_Disable;
1031   FMC_NORSRAMInitStructure.FMC_ContinousClock = FMC_CClock_SyncOnly;
1032   FMC_NORSRAMInitStructure.FMC_ReadWriteTimingStruct = &NORSRAMTimingStructure;
1033   FMC_NORSRAMInitStructure.FMC_WriteTimingStruct = &NORSRAMTimingStructure;
1034 */
1035
1036 }
1037 #endif /* DATA_IN_ExtSRAM */
1038
1039 #ifdef DATA_IN_ExtSDRAM
1040 /**
1041   * @brief  Setup the external memory controller.
1042   *         Called in startup_stm32f4xx.s before jump to main.
1043   *         This function configures the external SDRAM mounted on STM324x9I_EVAL board
1044   *         This SDRAM will be used as program data memory (including heap and stack).
1045   * @param  None
1046   * @retval None
1047   */
1048 void SystemInit_ExtMemCtl(void)
1049 {
1050   register uint32_t tmpreg = 0, timeout = 0xFFFF;
1051   register uint32_t index;
1052
1053   /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
1054       clock */
1055   RCC->AHB1ENR |= 0x000001FC;
1056
1057   /* Connect PCx pins to FMC Alternate function */
1058   GPIOC->AFR[0]  = 0x0000000c;
1059   GPIOC->AFR[1]  = 0x00007700;
1060   /* Configure PCx pins in Alternate function mode */
1061   GPIOC->MODER   = 0x00a00002;
1062   /* Configure PCx pins speed to 50 MHz */
1063   GPIOC->OSPEEDR = 0x00a00002;
1064   /* Configure PCx pins Output type to push-pull */
1065   GPIOC->OTYPER  = 0x00000000;
1066   /* No pull-up, pull-down for PCx pins */
1067   GPIOC->PUPDR   = 0x00500000;
1068
1069   /* Connect PDx pins to FMC Alternate function */
1070   GPIOD->AFR[0]  = 0x000000CC;
1071   GPIOD->AFR[1]  = 0xCC000CCC;
1072   /* Configure PDx pins in Alternate function mode */
1073   GPIOD->MODER   = 0xA02A000A;
1074   /* Configure PDx pins speed to 50 MHz */
1075   GPIOD->OSPEEDR = 0xA02A000A;
1076   /* Configure PDx pins Output type to push-pull */
1077   GPIOD->OTYPER  = 0x00000000;
1078   /* No pull-up, pull-down for PDx pins */
1079   GPIOD->PUPDR   = 0x00000000;
1080
1081   /* Connect PEx pins to FMC Alternate function */
1082   GPIOE->AFR[0]  = 0xC00000CC;
1083   GPIOE->AFR[1]  = 0xCCCCCCCC;
1084   /* Configure PEx pins in Alternate function mode */
1085   GPIOE->MODER   = 0xAAAA800A;
1086   /* Configure PEx pins speed to 50 MHz */
1087   GPIOE->OSPEEDR = 0xAAAA800A;
1088   /* Configure PEx pins Output type to push-pull */
1089   GPIOE->OTYPER  = 0x00000000;
1090   /* No pull-up, pull-down for PEx pins */
1091   GPIOE->PUPDR   = 0x00000000;
1092
1093   /* Connect PFx pins to FMC Alternate function */
1094   GPIOF->AFR[0]  = 0xcccccccc;
1095   GPIOF->AFR[1]  = 0xcccccccc;
1096   /* Configure PFx pins in Alternate function mode */
1097   GPIOF->MODER   = 0xAA800AAA;
1098   /* Configure PFx pins speed to 50 MHz */
1099   GPIOF->OSPEEDR = 0xAA800AAA;
1100   /* Configure PFx pins Output type to push-pull */
1101   GPIOF->OTYPER  = 0x00000000;
1102   /* No pull-up, pull-down for PFx pins */
1103   GPIOF->PUPDR   = 0x00000000;
1104
1105   /* Connect PGx pins to FMC Alternate function */
1106   GPIOG->AFR[0]  = 0xcccccccc;
1107   GPIOG->AFR[1]  = 0xcccccccc;
1108   /* Configure PGx pins in Alternate function mode */
1109   GPIOG->MODER   = 0xaaaaaaaa;
1110   /* Configure PGx pins speed to 50 MHz */
1111   GPIOG->OSPEEDR = 0xaaaaaaaa;
1112   /* Configure PGx pins Output type to push-pull */
1113   GPIOG->OTYPER  = 0x00000000;
1114   /* No pull-up, pull-down for PGx pins */
1115   GPIOG->PUPDR   = 0x00000000;
1116
1117   /* Connect PHx pins to FMC Alternate function */
1118   GPIOH->AFR[0]  = 0x00C0CC00;
1119   GPIOH->AFR[1]  = 0xCCCCCCCC;
1120   /* Configure PHx pins in Alternate function mode */
1121   GPIOH->MODER   = 0xAAAA08A0;
1122   /* Configure PHx pins speed to 50 MHz */
1123   GPIOH->OSPEEDR = 0xAAAA08A0;
1124   /* Configure PHx pins Output type to push-pull */
1125   GPIOH->OTYPER  = 0x00000000;
1126   /* No pull-up, pull-down for PHx pins */
1127   GPIOH->PUPDR   = 0x00000000;
1128
1129   /* Connect PIx pins to FMC Alternate function */
1130   GPIOI->AFR[0]  = 0xCCCCCCCC;
1131   GPIOI->AFR[1]  = 0x00000CC0;
1132   /* Configure PIx pins in Alternate function mode */
1133   GPIOI->MODER   = 0x0028AAAA;
1134   /* Configure PIx pins speed to 50 MHz */
1135   GPIOI->OSPEEDR = 0x0028AAAA;
1136   /* Configure PIx pins Output type to push-pull */
1137   GPIOI->OTYPER  = 0x00000000;
1138   /* No pull-up, pull-down for PIx pins */
1139   GPIOI->PUPDR   = 0x00000000;
1140
1141 /*-- FMC Configuration ------------------------------------------------------*/
1142   /* Enable the FMC interface clock */
1143   RCC->AHB3ENR |= 0x00000001;
1144
1145   /* Configure and enable SDRAM bank1 */
1146   FMC_Bank5_6->SDCR[0] = 0x000039D0;
1147   FMC_Bank5_6->SDTR[0] = 0x01115351;
1148
1149   /* SDRAM initialization sequence */
1150   /* Clock enable command */
1151   FMC_Bank5_6->SDCMR = 0x00000011;
1152   tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1153   while((tmpreg != 0) & (timeout-- > 0))
1154   {
1155     tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1156   }
1157
1158   /* Delay */
1159   for (index = 0; index<1000; index++);
1160
1161   /* PALL command */
1162   FMC_Bank5_6->SDCMR = 0x00000012;
1163   timeout = 0xFFFF;
1164   while((tmpreg != 0) & (timeout-- > 0))
1165   {
1166   tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1167   }
1168
1169   /* Auto refresh command */
1170   FMC_Bank5_6->SDCMR = 0x00000073;
1171   timeout = 0xFFFF;
1172   while((tmpreg != 0) & (timeout-- > 0))
1173   {
1174   tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1175   }
1176
1177   /* MRD register program */
1178   FMC_Bank5_6->SDCMR = 0x00046014;
1179   timeout = 0xFFFF;
1180   while((tmpreg != 0) & (timeout-- > 0))
1181   {
1182   tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
1183   }
1184
1185   /* Set refresh count */
1186   tmpreg = FMC_Bank5_6->SDRTR;
1187   FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
1188
1189   /* Disable write protection */
1190   tmpreg = FMC_Bank5_6->SDCR[0];
1191   FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
1192
1193 /*
1194   Bank1_SDRAM is configured as follow:
1195
1196   FMC_SDRAMTimingInitStructure.FMC_LoadToActiveDelay = 2;
1197   FMC_SDRAMTimingInitStructure.FMC_ExitSelfRefreshDelay = 6;
1198   FMC_SDRAMTimingInitStructure.FMC_SelfRefreshTime = 4;
1199   FMC_SDRAMTimingInitStructure.FMC_RowCycleDelay = 6;
1200   FMC_SDRAMTimingInitStructure.FMC_WriteRecoveryTime = 2;
1201   FMC_SDRAMTimingInitStructure.FMC_RPDelay = 2;
1202   FMC_SDRAMTimingInitStructure.FMC_RCDDelay = 2;
1203
1204   FMC_SDRAMInitStructure.FMC_Bank = SDRAM_BANK;
1205   FMC_SDRAMInitStructure.FMC_ColumnBitsNumber = FMC_ColumnBits_Number_8b;
1206   FMC_SDRAMInitStructure.FMC_RowBitsNumber = FMC_RowBits_Number_11b;
1207   FMC_SDRAMInitStructure.FMC_SDMemoryDataWidth = FMC_SDMemory_Width_16b;
1208   FMC_SDRAMInitStructure.FMC_InternalBankNumber = FMC_InternalBank_Number_4;
1209   FMC_SDRAMInitStructure.FMC_CASLatency = FMC_CAS_Latency_3;
1210   FMC_SDRAMInitStructure.FMC_WriteProtection = FMC_Write_Protection_Disable;
1211   FMC_SDRAMInitStructure.FMC_SDClockPeriod = FMC_SDClock_Period_2;
1212   FMC_SDRAMInitStructure.FMC_ReadBurst = FMC_Read_Burst_disable;
1213   FMC_SDRAMInitStructure.FMC_ReadPipeDelay = FMC_ReadPipe_Delay_1;
1214   FMC_SDRAMInitStructure.FMC_SDRAMTimingStruct = &FMC_SDRAMTimingInitStructure;
1215 */
1216
1217 }
1218 #endif /* DATA_IN_ExtSDRAM */
1219
1220
1221 /**
1222   * @}
1223   */
1224
1225 /**
1226   * @}
1227   */
1228
1229 /**
1230   * @}
1231   */
1232 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/