CF/BF - Fix CLI being spammed with OSD MSP_DISPLAYPORT messages when OSD
[betaflight.git] / src / main / drivers / dma.h
blobc5831c95e103f5ccd8af5ee9884804749db03f2b
1 /*
2 * This file is part of Cleanflight.
4 * Cleanflight is free software: you can redistribute it and/or modify
5 * it under the terms of the GNU General Public License as published by
6 * the Free Software Foundation, either version 3 of the License, or
7 * (at your option) any later version.
9 * Cleanflight is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
14 * You should have received a copy of the GNU General Public License
15 * along with Cleanflight. If not, see <http://www.gnu.org/licenses/>.
18 #pragma once
20 #include "resource.h"
22 struct dmaChannelDescriptor_s;
23 typedef void (*dmaCallbackHandlerFuncPtr)(struct dmaChannelDescriptor_s *channelDescriptor);
25 typedef struct dmaChannelDescriptor_s {
26 DMA_TypeDef* dma;
27 #if defined(STM32F4) || defined(STM32F7)
28 DMA_Stream_TypeDef* ref;
29 #else
30 DMA_Channel_TypeDef* ref;
31 #endif
32 dmaCallbackHandlerFuncPtr irqHandlerCallback;
33 uint8_t flagsShift;
34 IRQn_Type irqN;
35 uint32_t rcc;
36 uint32_t userParam;
37 resourceOwner_e owner;
38 uint8_t resourceIndex;
39 } dmaChannelDescriptor_t;
41 #if defined(STM32F7)
42 //#define HAL_CLEANINVALIDATECACHE(addr, size) (SCB_CleanInvalidateDCache_by_Addr((uint32_t*)((uint32_t)addr & ~0x1f), ((uint32_t)(addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f)))
43 //#define HAL_CLEANCACHE(addr, size) (SCB_CleanDCache_by_Addr((uint32_t*)((uint32_t)addr & ~0x1f), ((uint32_t)(addr + size + 0x1f) & ~0x1f) - ((uint32_t)addr & ~0x1f)))
44 #endif
46 #if defined(STM32F4) || defined(STM32F7)
47 uint32_t dmaFlag_IT_TCIF(const DMA_Stream_TypeDef *stream);
49 typedef enum {
50 DMA1_ST0_HANDLER = 0,
51 DMA1_ST1_HANDLER,
52 DMA1_ST2_HANDLER,
53 DMA1_ST3_HANDLER,
54 DMA1_ST4_HANDLER,
55 DMA1_ST5_HANDLER,
56 DMA1_ST6_HANDLER,
57 DMA1_ST7_HANDLER,
58 DMA2_ST0_HANDLER,
59 DMA2_ST1_HANDLER,
60 DMA2_ST2_HANDLER,
61 DMA2_ST3_HANDLER,
62 DMA2_ST4_HANDLER,
63 DMA2_ST5_HANDLER,
64 DMA2_ST6_HANDLER,
65 DMA2_ST7_HANDLER,
66 DMA_MAX_DESCRIPTORS
67 } dmaIdentifier_e;
69 #define DMA_MOD_VALUE 8
70 #define DMA_MOD_OFFSET 0
71 #define DMA_OUTPUT_INDEX 0
72 #define DMA_OUTPUT_STRING "DMA%d Stream %d:"
74 #define DEFINE_DMA_CHANNEL(d, s, f, i, r) {.dma = d, .ref = s, .irqHandlerCallback = NULL, .flagsShift = f, .irqN = i, .rcc = r, .userParam = 0, .owner = 0, .resourceIndex = 0 }
75 #define DEFINE_DMA_IRQ_HANDLER(d, s, i) void DMA ## d ## _Stream ## s ## _IRQHandler(void) {\
76 if (dmaDescriptors[i].irqHandlerCallback)\
77 dmaDescriptors[i].irqHandlerCallback(&dmaDescriptors[i]);\
80 #define DMA_CLEAR_FLAG(d, flag) if(d->flagsShift > 31) d->dma->HIFCR = (flag << (d->flagsShift - 32)); else d->dma->LIFCR = (flag << d->flagsShift)
81 #define DMA_GET_FLAG_STATUS(d, flag) (d->flagsShift > 31 ? d->dma->HISR & (flag << (d->flagsShift - 32)): d->dma->LISR & (flag << d->flagsShift))
84 #define DMA_IT_TCIF ((uint32_t)0x00000020)
85 #define DMA_IT_HTIF ((uint32_t)0x00000010)
86 #define DMA_IT_TEIF ((uint32_t)0x00000008)
87 #define DMA_IT_DMEIF ((uint32_t)0x00000004)
88 #define DMA_IT_FEIF ((uint32_t)0x00000001)
90 dmaIdentifier_e dmaGetIdentifier(const DMA_Stream_TypeDef* stream);
91 dmaChannelDescriptor_t* getDmaDescriptor(const DMA_Stream_TypeDef* stream);
93 #else
95 typedef enum {
96 DMA1_CH1_HANDLER = 0,
97 DMA1_CH2_HANDLER,
98 DMA1_CH3_HANDLER,
99 DMA1_CH4_HANDLER,
100 DMA1_CH5_HANDLER,
101 DMA1_CH6_HANDLER,
102 DMA1_CH7_HANDLER,
103 #if defined(STM32F3) || defined(STM32F10X_CL)
104 DMA2_CH1_HANDLER,
105 DMA2_CH2_HANDLER,
106 DMA2_CH3_HANDLER,
107 DMA2_CH4_HANDLER,
108 DMA2_CH5_HANDLER,
109 #endif
110 DMA_MAX_DESCRIPTORS
111 } dmaIdentifier_e;
113 #define DMA_MOD_VALUE 7
114 #define DMA_MOD_OFFSET 1
115 #define DMA_OUTPUT_INDEX 0
116 #define DMA_OUTPUT_STRING "DMA%d Channel %d:"
118 #define DEFINE_DMA_CHANNEL(d, c, f, i, r) {.dma = d, .ref = c, .irqHandlerCallback = NULL, .flagsShift = f, .irqN = i, .rcc = r, .userParam = 0, .owner = 0, .resourceIndex = 0 }
119 #define DEFINE_DMA_IRQ_HANDLER(d, c, i) void DMA ## d ## _Channel ## c ## _IRQHandler(void) {\
120 if (dmaDescriptors[i].irqHandlerCallback)\
121 dmaDescriptors[i].irqHandlerCallback(&dmaDescriptors[i]);\
124 #define DMA_CLEAR_FLAG(d, flag) d->dma->IFCR = (flag << d->flagsShift)
125 #define DMA_GET_FLAG_STATUS(d, flag) (d->dma->ISR & (flag << d->flagsShift))
127 #define DMA_IT_TCIF ((uint32_t)0x00000002)
128 #define DMA_IT_HTIF ((uint32_t)0x00000004)
129 #define DMA_IT_TEIF ((uint32_t)0x00000008)
131 dmaIdentifier_e dmaGetIdentifier(const DMA_Channel_TypeDef* channel);
133 #endif
135 void dmaInit(dmaIdentifier_e identifier, resourceOwner_e owner, uint8_t resourceIndex);
136 void dmaSetHandler(dmaIdentifier_e identifier, dmaCallbackHandlerFuncPtr callback, uint32_t priority, uint32_t userParam);
138 resourceOwner_e dmaGetOwner(dmaIdentifier_e identifier);
139 uint8_t dmaGetResourceIndex(dmaIdentifier_e identifier);