src/main/drivers/system_stm32f7xx.c

   1 /*
   2  * This file is part of Cleanflight.
   3  *
   4  * Cleanflight is free software: you can redistribute it and/or modify
   5  * it under the terms of the GNU General Public License as published by
   6  * the Free Software Foundation, either version 3 of the License, or
   7  * (at your option) any later version.
   8  *
   9  * Cleanflight is distributed in the hope that it will be useful,
  10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
  11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  12  * GNU General Public License for more details.
  13  *
  14  * You should have received a copy of the GNU General Public License
  15  * along with Cleanflight.  If not, see <http://www.gnu.org/licenses/>.
  16  */
  17
  18 #include <string.h>
  19 #include <stdbool.h>
  20 #include <stdint.h>
  21 #include <stdlib.h>
  22
  23 #include "platform.h"
  24
  25 #include "accgyro_mpu.h"
  26 #include "exti.h"
  27 #include "nvic.h"
  28 #include "system.h"
  29
  30
  31 #define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
  32 void SystemClock_Config(void);
  33
  34 void systemReset(void)
  35 {
  36     if (mpuConfiguration.reset)
  37         mpuConfiguration.reset();
  38
  39     __disable_irq();
  40     NVIC_SystemReset();
  41 }
  42
  43 void systemResetToBootloader(void)
  44 {
  45     if (mpuConfiguration.reset)
  46         mpuConfiguration.reset();
  47
  48
  49     (*(__IO uint32_t *) (BKPSRAM_BASE + 4)) = 0xDEADBEEF;   // flag that will be readable after reboot
  50
  51     __disable_irq();
  52     NVIC_SystemReset();
  53 }
  54
  55 void enableGPIOPowerUsageAndNoiseReductions(void)
  56 {
  57
  58     // AHB1
  59     __HAL_RCC_BKPSRAM_CLK_ENABLE();
  60     __HAL_RCC_DTCMRAMEN_CLK_ENABLE();
  61     __HAL_RCC_DMA2_CLK_ENABLE();
  62     __HAL_RCC_DMA2D_CLK_ENABLE();
  63     __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
  64     __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
  65     __HAL_RCC_GPIOA_CLK_ENABLE();
  66     __HAL_RCC_GPIOB_CLK_ENABLE();
  67     __HAL_RCC_GPIOC_CLK_ENABLE();
  68     __HAL_RCC_GPIOD_CLK_ENABLE();
  69     __HAL_RCC_GPIOE_CLK_ENABLE();
  70     __HAL_RCC_GPIOF_CLK_ENABLE();
  71     __HAL_RCC_GPIOG_CLK_ENABLE();
  72     __HAL_RCC_GPIOH_CLK_ENABLE();
  73     __HAL_RCC_GPIOI_CLK_ENABLE();
  74     __HAL_RCC_GPIOJ_CLK_ENABLE();
  75     __HAL_RCC_GPIOK_CLK_ENABLE();
  76
  77     //APB1
  78     __HAL_RCC_TIM2_CLK_ENABLE();
  79     __HAL_RCC_TIM3_CLK_ENABLE();
  80     __HAL_RCC_TIM4_CLK_ENABLE();
  81     __HAL_RCC_TIM5_CLK_ENABLE();
  82     __HAL_RCC_TIM6_CLK_ENABLE();
  83     __HAL_RCC_TIM7_CLK_ENABLE();
  84     __HAL_RCC_TIM12_CLK_ENABLE();
  85     __HAL_RCC_TIM13_CLK_ENABLE();
  86     __HAL_RCC_TIM14_CLK_ENABLE();
  87     __HAL_RCC_LPTIM1_CLK_ENABLE();
  88     __HAL_RCC_SPI2_CLK_ENABLE();
  89     __HAL_RCC_SPI3_CLK_ENABLE();
  90     __HAL_RCC_USART2_CLK_ENABLE();
  91     __HAL_RCC_USART3_CLK_ENABLE();
  92     __HAL_RCC_UART4_CLK_ENABLE();
  93     __HAL_RCC_UART5_CLK_ENABLE();
  94     __HAL_RCC_I2C1_CLK_ENABLE();
  95     __HAL_RCC_I2C2_CLK_ENABLE();
  96     __HAL_RCC_I2C3_CLK_ENABLE();
  97     __HAL_RCC_I2C4_CLK_ENABLE();
  98     __HAL_RCC_CAN1_CLK_ENABLE();
  99     __HAL_RCC_CAN2_CLK_ENABLE();
 100     __HAL_RCC_CEC_CLK_ENABLE();
 101     __HAL_RCC_DAC_CLK_ENABLE();
 102     __HAL_RCC_UART7_CLK_ENABLE();
 103     __HAL_RCC_UART8_CLK_ENABLE();
 104
 105     //APB2
 106     __HAL_RCC_TIM1_CLK_ENABLE();
 107     __HAL_RCC_TIM8_CLK_ENABLE();
 108     __HAL_RCC_USART1_CLK_ENABLE();
 109     __HAL_RCC_USART6_CLK_ENABLE();
 110     __HAL_RCC_ADC1_CLK_ENABLE();
 111     __HAL_RCC_ADC2_CLK_ENABLE();
 112     __HAL_RCC_ADC3_CLK_ENABLE();
 113     __HAL_RCC_SDMMC1_CLK_ENABLE();
 114     __HAL_RCC_SPI1_CLK_ENABLE();
 115     __HAL_RCC_SPI4_CLK_ENABLE();
 116     __HAL_RCC_TIM9_CLK_ENABLE();
 117     __HAL_RCC_TIM10_CLK_ENABLE();
 118     __HAL_RCC_TIM11_CLK_ENABLE();
 119     __HAL_RCC_SPI5_CLK_ENABLE();
 120     __HAL_RCC_SPI6_CLK_ENABLE();
 121     __HAL_RCC_SAI1_CLK_ENABLE();
 122     __HAL_RCC_SAI2_CLK_ENABLE();
 123 //
 124 //    GPIO_InitTypeDef GPIO_InitStructure;
 125 //    GPIO_StructInit(&GPIO_InitStructure);
 126 //    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; // default is un-pulled input
 127 //
 128 //    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_All;
 129 //    GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_11 | GPIO_Pin_12); // leave USB D+/D- alone
 130 //
 131 //    GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_13 | GPIO_Pin_14); // leave JTAG pins alone
 132 //    GPIO_Init(GPIOA, &GPIO_InitStructure);
 133 //
 134 //    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_All;
 135 //    GPIO_Init(GPIOB, &GPIO_InitStructure);
 136 //
 137 //    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_All;
 138 //    GPIO_Init(GPIOC, &GPIO_InitStructure);
 139 //    GPIO_Init(GPIOD, &GPIO_InitStructure);
 140 //    GPIO_Init(GPIOE, &GPIO_InitStructure);
 141 }
 142
 143 bool isMPUSoftReset(void)
 144 {
 145     if (RCC->CSR & RCC_CSR_SFTRSTF)
 146         return true;
 147     else
 148         return false;
 149 }
 150
 151 void systemInit(void)
 152 {
 153     checkForBootLoaderRequest();
 154
 155     //SystemClock_Config();
 156
 157     // Configure NVIC preempt/priority groups
 158     HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUPING);
 159
 160     // cache RCC->CSR value to use it in isMPUSoftreset() and others
 161     cachedRccCsrValue = RCC->CSR;
 162
 163     /* Accounts for OP Bootloader, set the Vector Table base address as specified in .ld file */
 164     //extern void *isr_vector_table_base;
 165     //NVIC_SetVectorTable((uint32_t)&isr_vector_table_base, 0x0);
 166     //__HAL_RCC_USB_OTG_FS_CLK_DISABLE;
 167
 168     //RCC_ClearFlag();
 169
 170     enableGPIOPowerUsageAndNoiseReductions();
 171
 172     // Init cycle counter
 173     cycleCounterInit();
 174
 175     // SysTick
 176     //SysTick_Config(SystemCoreClock / 1000);
 177     HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 178
 179     HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 180 }
 181
 182 void(*bootJump)(void);
 183 void checkForBootLoaderRequest(void)
 184 {
 185     uint32_t bt;
 186     __PWR_CLK_ENABLE();
 187     __BKPSRAM_CLK_ENABLE();
 188     HAL_PWR_EnableBkUpAccess();
 189
 190     bt = (*(__IO uint32_t *) (BKPSRAM_BASE + 4)) ;
 191     if ( bt == 0xDEADBEEF ) {
 192         (*(__IO uint32_t *) (BKPSRAM_BASE + 4)) =  0xCAFEFEED; // Reset our trigger
 193
 194         void (*SysMemBootJump)(void);
 195         __SYSCFG_CLK_ENABLE();
 196         SYSCFG->MEMRMP |= SYSCFG_MEM_BOOT_ADD0 ;
 197         uint32_t p =  (*((uint32_t *) 0x1ff00000));
 198         __set_MSP(p); //Set the main stack pointer to its defualt values
 199         SysMemBootJump = (void (*)(void)) (*((uint32_t *) 0x1ff00004)); // Point the PC to the System Memory reset vector (+4)
 200         SysMemBootJump();
 201         while (1);
 202     }
 203 }