src/main/drivers/system_stm32f7xx.c

   1 /*
   2  * This file is part of Cleanflight and Betaflight.
   3  *
   4  * Cleanflight and Betaflight are free software. You can redistribute
   5  * this software and/or modify this software under the terms of the
   6  * GNU General Public License as published by the Free Software
   7  * Foundation, either version 3 of the License, or (at your option)
   8  * any later version.
   9  *
  10  * Cleanflight and Betaflight are distributed in the hope that they
  11  * will be useful, but WITHOUT ANY WARRANTY; without even the implied
  12  * warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
  13  * See the GNU General Public License for more details.
  14  *
  15  * You should have received a copy of the GNU General Public License
  16  * along with this software.
  17  *
  18  * If not, see <http://www.gnu.org/licenses/>.
  19  */
  20
  21 #include <string.h>
  22 #include <stdbool.h>
  23 #include <stdint.h>
  24 #include <stdlib.h>
  25
  26 #include "platform.h"
  27
  28 #include "drivers/accgyro/accgyro_mpu.h"
  29 #include "drivers/exti.h"
  30 #include "drivers/nvic.h"
  31 #include "drivers/system.h"
  32 #include "drivers/persistent.h"
  33
  34 #include "stm32f7xx_ll_cortex.h"
  35
  36
  37 #define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
  38 void SystemClock_Config(void);
  39
  40 void systemReset(void)
  41 {
  42     __disable_irq();
  43     NVIC_SystemReset();
  44 }
  45
  46 void systemResetToBootloader(void)
  47 {
  48     persistentObjectWrite(PERSISTENT_OBJECT_BOOTLOADER_REQUEST, 0xDEADBEEF);
  49     __disable_irq();
  50     NVIC_SystemReset();
  51 }
  52
  53 void enableGPIOPowerUsageAndNoiseReductions(void)
  54 {
  55
  56     // AHB1
  57     __HAL_RCC_BKPSRAM_CLK_ENABLE();
  58     __HAL_RCC_DTCMRAMEN_CLK_ENABLE();
  59     __HAL_RCC_DMA2_CLK_ENABLE();
  60     __HAL_RCC_USB_OTG_HS_CLK_ENABLE();
  61     __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE();
  62     __HAL_RCC_GPIOA_CLK_ENABLE();
  63     __HAL_RCC_GPIOB_CLK_ENABLE();
  64     __HAL_RCC_GPIOC_CLK_ENABLE();
  65     __HAL_RCC_GPIOD_CLK_ENABLE();
  66     __HAL_RCC_GPIOE_CLK_ENABLE();
  67     __HAL_RCC_GPIOF_CLK_ENABLE();
  68     __HAL_RCC_GPIOG_CLK_ENABLE();
  69     __HAL_RCC_GPIOH_CLK_ENABLE();
  70     __HAL_RCC_GPIOI_CLK_ENABLE();
  71 #ifndef STM32F722xx
  72     __HAL_RCC_DMA2D_CLK_ENABLE();
  73     __HAL_RCC_GPIOJ_CLK_ENABLE();
  74     __HAL_RCC_GPIOK_CLK_ENABLE();
  75 #endif
  76
  77     //APB1
  78     __HAL_RCC_TIM2_CLK_ENABLE();
  79     __HAL_RCC_TIM3_CLK_ENABLE();
  80     __HAL_RCC_TIM4_CLK_ENABLE();
  81     __HAL_RCC_TIM5_CLK_ENABLE();
  82     __HAL_RCC_TIM6_CLK_ENABLE();
  83     __HAL_RCC_TIM7_CLK_ENABLE();
  84     __HAL_RCC_TIM12_CLK_ENABLE();
  85     __HAL_RCC_TIM13_CLK_ENABLE();
  86     __HAL_RCC_TIM14_CLK_ENABLE();
  87     __HAL_RCC_LPTIM1_CLK_ENABLE();
  88     __HAL_RCC_SPI2_CLK_ENABLE();
  89     __HAL_RCC_SPI3_CLK_ENABLE();
  90     __HAL_RCC_USART2_CLK_ENABLE();
  91     __HAL_RCC_USART3_CLK_ENABLE();
  92     __HAL_RCC_UART4_CLK_ENABLE();
  93     __HAL_RCC_UART5_CLK_ENABLE();
  94     __HAL_RCC_I2C1_CLK_ENABLE();
  95     __HAL_RCC_I2C2_CLK_ENABLE();
  96     __HAL_RCC_I2C3_CLK_ENABLE();
  97     __HAL_RCC_CAN1_CLK_ENABLE();
  98     __HAL_RCC_DAC_CLK_ENABLE();
  99     __HAL_RCC_UART7_CLK_ENABLE();
 100     __HAL_RCC_UART8_CLK_ENABLE();
 101 #ifndef STM32F722xx
 102     __HAL_RCC_I2C4_CLK_ENABLE();
 103     __HAL_RCC_CAN2_CLK_ENABLE();
 104     __HAL_RCC_CEC_CLK_ENABLE();
 105 #endif
 106
 107     //APB2
 108     __HAL_RCC_TIM1_CLK_ENABLE();
 109     __HAL_RCC_TIM8_CLK_ENABLE();
 110     __HAL_RCC_USART1_CLK_ENABLE();
 111     __HAL_RCC_USART6_CLK_ENABLE();
 112     __HAL_RCC_ADC1_CLK_ENABLE();
 113     __HAL_RCC_ADC2_CLK_ENABLE();
 114     __HAL_RCC_ADC3_CLK_ENABLE();
 115     __HAL_RCC_SDMMC1_CLK_ENABLE();
 116     __HAL_RCC_SPI1_CLK_ENABLE();
 117     __HAL_RCC_SPI4_CLK_ENABLE();
 118     __HAL_RCC_TIM9_CLK_ENABLE();
 119     __HAL_RCC_TIM10_CLK_ENABLE();
 120     __HAL_RCC_TIM11_CLK_ENABLE();
 121     __HAL_RCC_SPI5_CLK_ENABLE();
 122     __HAL_RCC_SAI1_CLK_ENABLE();
 123     __HAL_RCC_SAI2_CLK_ENABLE();
 124 #ifndef STM32F722xx
 125     __HAL_RCC_SPI6_CLK_ENABLE();
 126 #endif
 127 //
 128 //    GPIO_InitTypeDef GPIO_InitStructure;
 129 //    GPIO_StructInit(&GPIO_InitStructure);
 130 //    GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP; // default is un-pulled input
 131 //
 132 //    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_All;
 133 //    GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_11 | GPIO_Pin_12); // leave USB D+/D- alone
 134 //
 135 //    GPIO_InitStructure.GPIO_Pin &= ~(GPIO_Pin_13 | GPIO_Pin_14); // leave JTAG pins alone
 136 //    GPIO_Init(GPIOA, &GPIO_InitStructure);
 137 //
 138 //    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_All;
 139 //    GPIO_Init(GPIOB, &GPIO_InitStructure);
 140 //
 141 //    GPIO_InitStructure.GPIO_Pin  = GPIO_Pin_All;
 142 //    GPIO_Init(GPIOC, &GPIO_InitStructure);
 143 //    GPIO_Init(GPIOD, &GPIO_InitStructure);
 144 //    GPIO_Init(GPIOE, &GPIO_InitStructure);
 145 }
 146
 147 bool isMPUSoftReset(void)
 148 {
 149     if (cachedRccCsrValue & RCC_CSR_SFTRSTF)
 150         return true;
 151     else
 152         return false;
 153 }
 154
 155 void systemInit(void)
 156 {
 157     checkForBootLoaderRequest();
 158
 159     //  Mark ITCM-RAM as read-only
 160     LL_MPU_ConfigRegion(LL_MPU_REGION_NUMBER0, 0, RAMITCM_BASE, LL_MPU_REGION_SIZE_16KB | LL_MPU_REGION_PRIV_RO_URO);
 161     LL_MPU_Enable(LL_MPU_CTRL_PRIVILEGED_DEFAULT);
 162
 163     //SystemClock_Config();
 164
 165     // Configure NVIC preempt/priority groups
 166     HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITY_GROUPING);
 167
 168     // cache RCC->CSR value to use it in isMPUSoftReset() and others
 169     cachedRccCsrValue = RCC->CSR;
 170
 171     /* Accounts for OP Bootloader, set the Vector Table base address as specified in .ld file */
 172     //extern void *isr_vector_table_base;
 173     //NVIC_SetVectorTable((uint32_t)&isr_vector_table_base, 0x0);
 174     //__HAL_RCC_USB_OTG_FS_CLK_DISABLE;
 175
 176     //RCC_ClearFlag();
 177
 178     enableGPIOPowerUsageAndNoiseReductions();
 179
 180     // Init cycle counter
 181     cycleCounterInit();
 182
 183     // SysTick
 184     //SysTick_Config(SystemCoreClock / 1000);
 185     HAL_SYSTICK_Config(HAL_RCC_GetHCLKFreq()/1000);
 186
 187     HAL_SYSTICK_CLKSourceConfig(SYSTICK_CLKSOURCE_HCLK);
 188 }
 189
 190 void(*bootJump)(void);
 191
 192 void checkForBootLoaderRequest(void)
 193 {
 194     uint32_t bootloaderRequest = persistentObjectRead(PERSISTENT_OBJECT_BOOTLOADER_REQUEST);
 195
 196     persistentObjectWrite(PERSISTENT_OBJECT_BOOTLOADER_REQUEST, 0xCAFEFEED);
 197
 198     if (bootloaderRequest != 0xDEADBEEF) {
 199         return;
 200     }
 201
 202     void (*SysMemBootJump)(void);
 203
 204     __SYSCFG_CLK_ENABLE();
 205     SYSCFG->MEMRMP |= SYSCFG_MEM_BOOT_ADD0 ;
 206
 207     uint32_t p =  (*((uint32_t *) 0x1ff00000));
 208
 209     __set_MSP(p); //Set the main stack pointer to its default values
 210
 211     SysMemBootJump = (void (*)(void)) (*((uint32_t *) 0x1ff00004)); // Point the PC to the System Memory reset vector (+4)
 212     SysMemBootJump();
 213
 214     while (1);
 215 }