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[G4][LIB] Fix LL_DMA_{Set,Get}PeriphRequest
[betaflight.git] / lib / main / STM32G4 / Drivers / STM32G4xx_HAL_Driver / Inc / stm32g4xx_ll_dma.h
blobea0486c5ccebfd2ccca6f297a9a6b2934dd7e929
1 /**
2 ******************************************************************************
3 * @file stm32g4xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef __STM32G4xx_LL_DMA_H
22 #define __STM32G4xx_LL_DMA_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32g4xx.h"
30 #include "stm32g4xx_ll_dmamux.h"
31
32 /** @addtogroup STM32G4xx_LL_Driver
33 * @{
34 */
35
36 #if defined (DMA1) || defined (DMA2)
37
38 /** @defgroup DMA_LL DMA
39 * @{
40 */
41
42 /* Private types -------------------------------------------------------------*/
43 /* Private variables ---------------------------------------------------------*/
44 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
45 * @{
46 */
47 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
48 static const uint8_t CHANNEL_OFFSET_TAB[] =
49 {
50 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
51 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
52 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
53 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
54 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
55 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE)
56 #if defined (DMA1_Channel7)
57 ,
58 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
59 #endif /* DMA1_Channel7 */
60 #if defined (DMA1_Channel8)
61 ,
62 (uint8_t)(DMA1_Channel8_BASE - DMA1_BASE)
63 #endif /* DMA1_Channel8 */
64 };
65 /**
66 * @}
67 */
68
69 /* Private constants ---------------------------------------------------------*/
70 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
71 * @{
72 */
73 /* Define used to get CSELR register offset */
74 #define DMA_CSELR_OFFSET (uint32_t)(DMA1_CSELR_BASE - DMA1_BASE)
75
76 /* Defines used for the bit position in the register and perform offsets */
77 #define DMA_POSITION_CSELR_CXS POSITION_VAL(DMA_CSELR_C1S << ((Channel-1U)*4U))
78 /**
79 * @}
80 */
81
82 /* Private macros ------------------------------------------------------------*/
83 #if defined(USE_FULL_LL_DRIVER)
84 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
85 * @{
86 */
87 /**
88 * @}
89 */
90 #endif /*USE_FULL_LL_DRIVER*/
91
92 /* Exported types ------------------------------------------------------------*/
93 #if defined(USE_FULL_LL_DRIVER)
94 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
95 * @{
96 */
97 typedef struct
98 {
99 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
100 or as Source base address in case of memory to memory transfer direction.
101
102 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
103
104 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
105 or as Destination base address in case of memory to memory transfer direction.
106
107 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
108
109 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
110 from memory to memory or from peripheral to memory.
111 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
112
113 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
114
115 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
116 This parameter can be a value of @ref DMA_LL_EC_MODE
117 @note: The circular buffer mode cannot be used if the memory to memory
118 data transfer direction is configured on the selected Channel
119
120 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
121
122 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
123 is incremented or not.
124 This parameter can be a value of @ref DMA_LL_EC_PERIPH
125
126 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
127
128 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
129 is incremented or not.
130 This parameter can be a value of @ref DMA_LL_EC_MEMORY
131
132 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
133
134 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
135 in case of memory to memory transfer direction.
136 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
137
138 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
139
140 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
141 in case of memory to memory transfer direction.
142 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
143
144 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
145
146 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
147 The data unit is equal to the source buffer configuration set in PeripheralSize
148 or MemorySize parameters depending in the transfer direction.
149 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
150
151 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
152
153 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
154 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
155
156 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
157
158 uint32_t Priority; /*!< Specifies the channel priority level.
159 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
160
161 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
162
163 } LL_DMA_InitTypeDef;
164 /**
165 * @}
166 */
167 #endif /*USE_FULL_LL_DRIVER*/
168
169 /* Exported constants --------------------------------------------------------*/
170 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
171 * @{
172 */
173 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
174 * @brief Flags defines which can be used with LL_DMA_WriteReg function
175 * @{
176 */
177 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
178 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
179 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
180 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
181 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
182 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
183 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
184 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
185 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
186 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
187 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
188 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
189 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
190 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
191 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
192 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
193 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
194 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
195 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
196 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
197 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
198 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
199 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
200 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
201 #if defined (DMA1_Channel7)
202 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
203 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
204 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
205 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
206 #endif /* DMA1_Channel7 */
207 #if defined (DMA1_Channel8)
208 #define LL_DMA_IFCR_CGIF8 DMA_IFCR_CGIF8 /*!< Channel 8 global flag */
209 #define LL_DMA_IFCR_CTCIF8 DMA_IFCR_CTCIF8 /*!< Channel 8 transfer complete flag */
210 #define LL_DMA_IFCR_CHTIF8 DMA_IFCR_CHTIF8 /*!< Channel 8 half transfer flag */
211 #define LL_DMA_IFCR_CTEIF8 DMA_IFCR_CTEIF8 /*!< Channel 8 transfer error flag */
212 #endif /* DMA1_Channel8 */
213 /**
214 * @}
215 */
216
217 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
218 * @brief Flags defines which can be used with LL_DMA_ReadReg function
219 * @{
220 */
221 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
222 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
223 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
224 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
225 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
226 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
227 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
228 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
229 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
230 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
231 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
232 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
233 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
234 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
235 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
236 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
237 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
238 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
239 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
240 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
241 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
242 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
243 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
244 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
245 #if defined (DMA1_Channel7)
246 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
247 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
248 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
249 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
250 #endif /* DMA1_Channel7 */
251 #if defined (DMA1_Channel8)
252 #define LL_DMA_ISR_GIF8 DMA_ISR_GIF8 /*!< Channel 8 global flag */
253 #define LL_DMA_ISR_TCIF8 DMA_ISR_TCIF8 /*!< Channel 8 transfer complete flag */
254 #define LL_DMA_ISR_HTIF8 DMA_ISR_HTIF8 /*!< Channel 8 half transfer flag */
255 #define LL_DMA_ISR_TEIF8 DMA_ISR_TEIF8 /*!< Channel 8 transfer error flag */
256 #endif /* DMA1_Channel8 */
257 /**
258 * @}
259 */
260
261 /** @defgroup DMA_LL_EC_IT IT Defines
262 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
263 * @{
264 */
265 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
266 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
267 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
268 /**
269 * @}
270 */
271
272 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
273 * @{
274 */
275 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
276 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
277 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
278 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
279 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
280 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
281 #if defined (DMA1_Channel7)
282 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
283 #endif /* DMA1_Channel7 */
284 #if defined (DMA1_Channel8)
285 #define LL_DMA_CHANNEL_8 0x00000008U /*!< DMA Channel 8 */
286 #endif /* DMA1_Channel8 */
287 #if defined(USE_FULL_LL_DRIVER)
288 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
289 #endif /*USE_FULL_LL_DRIVER*/
290 /**
291 * @}
292 */
293
294 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
295 * @{
296 */
297 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
298 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
299 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
300 /**
301 * @}
302 */
303
304 /** @defgroup DMA_LL_EC_MODE Transfer mode
305 * @{
306 */
307 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
308 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
309 /**
310 * @}
311 */
312
313 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
314 * @{
315 */
316 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
317 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
318 /**
319 * @}
320 */
321
322 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
323 * @{
324 */
325 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
326 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
327 /**
328 * @}
329 */
330
331 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
332 * @{
333 */
334 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
335 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
336 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
337 /**
338 * @}
339 */
340
341 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
342 * @{
343 */
344 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
345 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
346 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
347 /**
348 * @}
349 */
350
351 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
352 * @{
353 */
354 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
355 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
356 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
357 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
358 /**
359 * @}
360 */
361
362 /**
363 * @}
364 */
365
366 /* Exported macro ------------------------------------------------------------*/
367 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
368 * @{
369 */
370
371 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
372 * @{
373 */
374 /**
375 * @brief Write a value in DMA register
376 * @param __INSTANCE__ DMA Instance
377 * @param __REG__ Register to be written
378 * @param __VALUE__ Value to be written in the register
379 * @retval None
380 */
381 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
382
383 /**
384 * @brief Read a value in DMA register
385 * @param __INSTANCE__ DMA Instance
386 * @param __REG__ Register to be read
387 * @retval Register value
388 */
389 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
390 /**
391 * @}
392 */
393
394 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
395 * @{
396 */
397 /**
398 * @brief Convert DMAx_Channely into DMAx
399 * @param __CHANNEL_INSTANCE__ DMAx_Channely
400 * @retval DMAx
401 */
402 #if defined (DMA1_Channel8)
403 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
404 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel8)) ? DMA2 : DMA1)
405 #else
406 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
407 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel6)) ? DMA2 : DMA1)
408 #endif /* DMA1_Channel8 */
409 /**
410 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
411 * @param __CHANNEL_INSTANCE__ DMAx_Channely
412 * @retval LL_DMA_CHANNEL_y
413 */
414 #if defined (DMA1_Channel8)
415 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
416 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
417 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
418 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
419 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
423 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
424 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
425 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
426 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
427 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel6)) ? LL_DMA_CHANNEL_6 : \
428 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel7)) ? LL_DMA_CHANNEL_7 : \
429 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel7)) ? LL_DMA_CHANNEL_7 : \
430 LL_DMA_CHANNEL_8)
431 #else
432 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
433 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
434 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
435 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
436 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
437 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
438 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
439 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
440 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
441 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
442 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
443 LL_DMA_CHANNEL_6)
444 #endif /* DMA1_Channel8 */
445
446 /**
447 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
448 * @param __DMA_INSTANCE__ DMAx
449 * @param __CHANNEL__ LL_DMA_CHANNEL_y
450 * @retval DMAx_Channely
451 */
452 #if defined (DMA1_Channel8)
453 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
454 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
455 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
456 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
457 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
458 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
459 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
460 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
461 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
462 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
463 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
464 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
465 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA2_Channel6 : \
466 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA1_Channel7 : \
467 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_7))) ? DMA2_Channel7 : \
468 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_8))) ? DMA1_Channel8 : \
469 DMA2_Channel8)
470 #else
471 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
472 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
473 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
474 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
475 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
476 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
477 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
478 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
479 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
480 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
481 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
482 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
483 DMA2_Channel6)
484 #endif /* DMA1_Channel8 */
485
486 /**
487 * @}
488 */
489
490 /**
491 * @}
492 */
493
494 /* Exported functions --------------------------------------------------------*/
495 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
496 * @{
497 */
498
499 /** @defgroup DMA_LL_EF_Configuration Configuration
500 * @{
501 */
502 /**
503 * @brief Enable DMA channel.
504 * @rmtoll CCR EN LL_DMA_EnableChannel
505 * @param DMAx DMAx Instance
506 * @param Channel This parameter can be one of the following values:
507 * @arg @ref LL_DMA_CHANNEL_1
508 * @arg @ref LL_DMA_CHANNEL_2
509 * @arg @ref LL_DMA_CHANNEL_3
510 * @arg @ref LL_DMA_CHANNEL_4
511 * @arg @ref LL_DMA_CHANNEL_5
512 * @arg @ref LL_DMA_CHANNEL_6
513 * @arg @ref LL_DMA_CHANNEL_7 (*)
514 * @arg @ref LL_DMA_CHANNEL_8 (*)
515 * (*) Not on all G4 devices
516 * @retval None
517 */
518 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
519 {
520 register uint32_t dma_base_addr = (uint32_t)DMAx;
521
522 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
523 }
524
525 /**
526 * @brief Disable DMA channel.
527 * @rmtoll CCR EN LL_DMA_DisableChannel
528 * @param DMAx DMAx Instance
529 * @param Channel This parameter can be one of the following values:
530 * @arg @ref LL_DMA_CHANNEL_1
531 * @arg @ref LL_DMA_CHANNEL_2
532 * @arg @ref LL_DMA_CHANNEL_3
533 * @arg @ref LL_DMA_CHANNEL_4
534 * @arg @ref LL_DMA_CHANNEL_5
535 * @arg @ref LL_DMA_CHANNEL_6
536 * @arg @ref LL_DMA_CHANNEL_7 (*)
537 * @arg @ref LL_DMA_CHANNEL_8 (*)
538 * (*) Not on all G4 devices
539 * @retval None
540 */
541 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
542 {
543 register uint32_t dma_base_addr = (uint32_t)DMAx;
544
545 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
546 }
547
548 /**
549 * @brief Check if DMA channel is enabled or disabled.
550 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
551 * @param DMAx DMAx Instance
552 * @param Channel This parameter can be one of the following values:
553 * @arg @ref LL_DMA_CHANNEL_1
554 * @arg @ref LL_DMA_CHANNEL_2
555 * @arg @ref LL_DMA_CHANNEL_3
556 * @arg @ref LL_DMA_CHANNEL_4
557 * @arg @ref LL_DMA_CHANNEL_5
558 * @arg @ref LL_DMA_CHANNEL_6
559 * @arg @ref LL_DMA_CHANNEL_7 (*)
560 * @arg @ref LL_DMA_CHANNEL_8 (*)
561 * (*) Not on all G4 devices
562 * @retval State of bit (1 or 0).
563 */
564 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
565 {
566 register uint32_t dma_base_addr = (uint32_t)DMAx;
567
568 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
569 DMA_CCR_EN) == (DMA_CCR_EN)) ? 1UL : 0UL);
570 }
571
572 /**
573 * @brief Configure all parameters link to DMA transfer.
574 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
575 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
576 * CCR CIRC LL_DMA_ConfigTransfer\n
577 * CCR PINC LL_DMA_ConfigTransfer\n
578 * CCR MINC LL_DMA_ConfigTransfer\n
579 * CCR PSIZE LL_DMA_ConfigTransfer\n
580 * CCR MSIZE LL_DMA_ConfigTransfer\n
581 * CCR PL LL_DMA_ConfigTransfer
582 * @param DMAx DMAx Instance
583 * @param Channel This parameter can be one of the following values:
584 * @arg @ref LL_DMA_CHANNEL_1
585 * @arg @ref LL_DMA_CHANNEL_2
586 * @arg @ref LL_DMA_CHANNEL_3
587 * @arg @ref LL_DMA_CHANNEL_4
588 * @arg @ref LL_DMA_CHANNEL_5
589 * @arg @ref LL_DMA_CHANNEL_6
590 * @arg @ref LL_DMA_CHANNEL_7 (*)
591 * @arg @ref LL_DMA_CHANNEL_8 (*)
592 * (*) Not on all G4 devices
593 * @param Configuration This parameter must be a combination of all the following values:
594 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
595 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
596 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
597 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
598 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
599 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
600 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
601 * @retval None
602 */
603 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
604 {
605 register uint32_t dma_base_addr = (uint32_t)DMAx;
606
607 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
608 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
609 Configuration);
610 }
611
612 /**
613 * @brief Set Data transfer direction (read from peripheral or from memory).
614 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
615 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
616 * @param DMAx DMAx Instance
617 * @param Channel This parameter can be one of the following values:
618 * @arg @ref LL_DMA_CHANNEL_1
619 * @arg @ref LL_DMA_CHANNEL_2
620 * @arg @ref LL_DMA_CHANNEL_3
621 * @arg @ref LL_DMA_CHANNEL_4
622 * @arg @ref LL_DMA_CHANNEL_5
623 * @arg @ref LL_DMA_CHANNEL_6
624 * @arg @ref LL_DMA_CHANNEL_7 (*)
625 * @arg @ref LL_DMA_CHANNEL_8 (*)
626 * (*) Not on all G4 devices
627 * @param Direction This parameter can be one of the following values:
628 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
629 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
630 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
631 * @retval None
632 */
633 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
634 {
635 register uint32_t dma_base_addr = (uint32_t)DMAx;
636
637 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
638 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
639 }
640
641 /**
642 * @brief Get Data transfer direction (read from peripheral or from memory).
643 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
644 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
645 * @param DMAx DMAx Instance
646 * @param Channel This parameter can be one of the following values:
647 * @arg @ref LL_DMA_CHANNEL_1
648 * @arg @ref LL_DMA_CHANNEL_2
649 * @arg @ref LL_DMA_CHANNEL_3
650 * @arg @ref LL_DMA_CHANNEL_4
651 * @arg @ref LL_DMA_CHANNEL_5
652 * @arg @ref LL_DMA_CHANNEL_6
653 * @arg @ref LL_DMA_CHANNEL_7 (*)
654 * @arg @ref LL_DMA_CHANNEL_8 (*)
655 * (*) Not on all G4 devices
656 * @retval Returned value can be one of the following values:
657 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
658 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
659 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
660 */
661 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
662 {
663 register uint32_t dma_base_addr = (uint32_t)DMAx;
664
665 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
666 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
667 }
668
669 /**
670 * @brief Set DMA mode circular or normal.
671 * @note The circular buffer mode cannot be used if the memory-to-memory
672 * data transfer is configured on the selected Channel.
673 * @rmtoll CCR CIRC LL_DMA_SetMode
674 * @param DMAx DMAx Instance
675 * @param Channel This parameter can be one of the following values:
676 * @arg @ref LL_DMA_CHANNEL_1
677 * @arg @ref LL_DMA_CHANNEL_2
678 * @arg @ref LL_DMA_CHANNEL_3
679 * @arg @ref LL_DMA_CHANNEL_4
680 * @arg @ref LL_DMA_CHANNEL_5
681 * @arg @ref LL_DMA_CHANNEL_6
682 * @arg @ref LL_DMA_CHANNEL_7 (*)
683 * @arg @ref LL_DMA_CHANNEL_8 (*)
684 * (*) Not on all G4 devices
685 * @param Mode This parameter can be one of the following values:
686 * @arg @ref LL_DMA_MODE_NORMAL
687 * @arg @ref LL_DMA_MODE_CIRCULAR
688 * @retval None
689 */
690 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
691 {
692 register uint32_t dma_base_addr = (uint32_t)DMAx;
693
694 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
695 Mode);
696 }
697
698 /**
699 * @brief Get DMA mode circular or normal.
700 * @rmtoll CCR CIRC LL_DMA_GetMode
701 * @param DMAx DMAx Instance
702 * @param Channel This parameter can be one of the following values:
703 * @arg @ref LL_DMA_CHANNEL_1
704 * @arg @ref LL_DMA_CHANNEL_2
705 * @arg @ref LL_DMA_CHANNEL_3
706 * @arg @ref LL_DMA_CHANNEL_4
707 * @arg @ref LL_DMA_CHANNEL_5
708 * @arg @ref LL_DMA_CHANNEL_6
709 * @arg @ref LL_DMA_CHANNEL_7 (*)
710 * @arg @ref LL_DMA_CHANNEL_8 (*)
711 * (*) Not on all G4 devices
712 * @retval Returned value can be one of the following values:
713 * @arg @ref LL_DMA_MODE_NORMAL
714 * @arg @ref LL_DMA_MODE_CIRCULAR
715 */
716 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
717 {
718 register uint32_t dma_base_addr = (uint32_t)DMAx;
719
720 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
721 DMA_CCR_CIRC));
722 }
723
724 /**
725 * @brief Set Peripheral increment mode.
726 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
727 * @param DMAx DMAx Instance
728 * @param Channel This parameter can be one of the following values:
729 * @arg @ref LL_DMA_CHANNEL_1
730 * @arg @ref LL_DMA_CHANNEL_2
731 * @arg @ref LL_DMA_CHANNEL_3
732 * @arg @ref LL_DMA_CHANNEL_4
733 * @arg @ref LL_DMA_CHANNEL_5
734 * @arg @ref LL_DMA_CHANNEL_6
735 * @arg @ref LL_DMA_CHANNEL_7 (*)
736 * @arg @ref LL_DMA_CHANNEL_8 (*)
737 * (*) Not on all G4 devices
738 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
739 * @arg @ref LL_DMA_PERIPH_INCREMENT
740 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
741 * @retval None
742 */
743 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
744 {
745 register uint32_t dma_base_addr = (uint32_t)DMAx;
746
747 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
748 PeriphOrM2MSrcIncMode);
749 }
750
751 /**
752 * @brief Get Peripheral increment mode.
753 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
754 * @param DMAx DMAx Instance
755 * @param Channel This parameter can be one of the following values:
756 * @arg @ref LL_DMA_CHANNEL_1
757 * @arg @ref LL_DMA_CHANNEL_2
758 * @arg @ref LL_DMA_CHANNEL_3
759 * @arg @ref LL_DMA_CHANNEL_4
760 * @arg @ref LL_DMA_CHANNEL_5
761 * @arg @ref LL_DMA_CHANNEL_6
762 * @arg @ref LL_DMA_CHANNEL_7 (*)
763 * @arg @ref LL_DMA_CHANNEL_8 (*)
764 * (*) Not on all G4 devices
765 * @retval Returned value can be one of the following values:
766 * @arg @ref LL_DMA_PERIPH_INCREMENT
767 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
768 */
769 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
770 {
771 register uint32_t dma_base_addr = (uint32_t)DMAx;
772
773 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
774 DMA_CCR_PINC));
775 }
776
777 /**
778 * @brief Set Memory increment mode.
779 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
780 * @param DMAx DMAx Instance
781 * @param Channel This parameter can be one of the following values:
782 * @arg @ref LL_DMA_CHANNEL_1
783 * @arg @ref LL_DMA_CHANNEL_2
784 * @arg @ref LL_DMA_CHANNEL_3
785 * @arg @ref LL_DMA_CHANNEL_4
786 * @arg @ref LL_DMA_CHANNEL_5
787 * @arg @ref LL_DMA_CHANNEL_6
788 * @arg @ref LL_DMA_CHANNEL_7 (*)
789 * @arg @ref LL_DMA_CHANNEL_8 (*)
790 * (*) Not on all G4 devices
791 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
792 * @arg @ref LL_DMA_MEMORY_INCREMENT
793 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
794 * @retval None
795 */
796 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
797 {
798 register uint32_t dma_base_addr = (uint32_t)DMAx;
799
800 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
801 MemoryOrM2MDstIncMode);
802 }
803
804 /**
805 * @brief Get Memory increment mode.
806 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
807 * @param DMAx DMAx Instance
808 * @param Channel This parameter can be one of the following values:
809 * @arg @ref LL_DMA_CHANNEL_1
810 * @arg @ref LL_DMA_CHANNEL_2
811 * @arg @ref LL_DMA_CHANNEL_3
812 * @arg @ref LL_DMA_CHANNEL_4
813 * @arg @ref LL_DMA_CHANNEL_5
814 * @arg @ref LL_DMA_CHANNEL_6
815 * @arg @ref LL_DMA_CHANNEL_7 (*)
816 * @arg @ref LL_DMA_CHANNEL_8 (*)
817 * (*) Not on all G4 devices
818 * @retval Returned value can be one of the following values:
819 * @arg @ref LL_DMA_MEMORY_INCREMENT
820 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
821 */
822 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
823 {
824 register uint32_t dma_base_addr = (uint32_t)DMAx;
825
826 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
827 DMA_CCR_MINC));
828 }
829
830 /**
831 * @brief Set Peripheral size.
832 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
833 * @param DMAx DMAx Instance
834 * @param Channel This parameter can be one of the following values:
835 * @arg @ref LL_DMA_CHANNEL_1
836 * @arg @ref LL_DMA_CHANNEL_2
837 * @arg @ref LL_DMA_CHANNEL_3
838 * @arg @ref LL_DMA_CHANNEL_4
839 * @arg @ref LL_DMA_CHANNEL_5
840 * @arg @ref LL_DMA_CHANNEL_6
841 * @arg @ref LL_DMA_CHANNEL_7 (*)
842 * @arg @ref LL_DMA_CHANNEL_8 (*)
843 * (*) Not on all G4 devices
844 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
845 * @arg @ref LL_DMA_PDATAALIGN_BYTE
846 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
847 * @arg @ref LL_DMA_PDATAALIGN_WORD
848 * @retval None
849 */
850 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
851 {
852 register uint32_t dma_base_addr = (uint32_t)DMAx;
853
854 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
855 PeriphOrM2MSrcDataSize);
856 }
857
858 /**
859 * @brief Get Peripheral size.
860 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
861 * @param DMAx DMAx Instance
862 * @param Channel This parameter can be one of the following values:
863 * @arg @ref LL_DMA_CHANNEL_1
864 * @arg @ref LL_DMA_CHANNEL_2
865 * @arg @ref LL_DMA_CHANNEL_3
866 * @arg @ref LL_DMA_CHANNEL_4
867 * @arg @ref LL_DMA_CHANNEL_5
868 * @arg @ref LL_DMA_CHANNEL_6
869 * @arg @ref LL_DMA_CHANNEL_7 (*)
870 * @arg @ref LL_DMA_CHANNEL_8 (*)
871 * (*) Not on all G4 devices
872 * @retval Returned value can be one of the following values:
873 * @arg @ref LL_DMA_PDATAALIGN_BYTE
874 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
875 * @arg @ref LL_DMA_PDATAALIGN_WORD
876 */
877 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
878 {
879 register uint32_t dma_base_addr = (uint32_t)DMAx;
880
881 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
882 DMA_CCR_PSIZE));
883 }
884
885 /**
886 * @brief Set Memory size.
887 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
888 * @param DMAx DMAx Instance
889 * @param Channel This parameter can be one of the following values:
890 * @arg @ref LL_DMA_CHANNEL_1
891 * @arg @ref LL_DMA_CHANNEL_2
892 * @arg @ref LL_DMA_CHANNEL_3
893 * @arg @ref LL_DMA_CHANNEL_4
894 * @arg @ref LL_DMA_CHANNEL_5
895 * @arg @ref LL_DMA_CHANNEL_6
896 * @arg @ref LL_DMA_CHANNEL_7 (*)
897 * @arg @ref LL_DMA_CHANNEL_8 (*)
898 * (*) Not on all G4 devices
899 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
900 * @arg @ref LL_DMA_MDATAALIGN_BYTE
901 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
902 * @arg @ref LL_DMA_MDATAALIGN_WORD
903 * @retval None
904 */
905 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
906 {
907 register uint32_t dma_base_addr = (uint32_t)DMAx;
908
909 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
910 MemoryOrM2MDstDataSize);
911 }
912
913 /**
914 * @brief Get Memory size.
915 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
916 * @param DMAx DMAx Instance
917 * @param Channel This parameter can be one of the following values:
918 * @arg @ref LL_DMA_CHANNEL_1
919 * @arg @ref LL_DMA_CHANNEL_2
920 * @arg @ref LL_DMA_CHANNEL_3
921 * @arg @ref LL_DMA_CHANNEL_4
922 * @arg @ref LL_DMA_CHANNEL_5
923 * @arg @ref LL_DMA_CHANNEL_6
924 * @arg @ref LL_DMA_CHANNEL_7 (*)
925 * @arg @ref LL_DMA_CHANNEL_8 (*)
926 * (*) Not on all G4 devices
927 * @retval Returned value can be one of the following values:
928 * @arg @ref LL_DMA_MDATAALIGN_BYTE
929 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
930 * @arg @ref LL_DMA_MDATAALIGN_WORD
931 */
932 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
933 {
934 register uint32_t dma_base_addr = (uint32_t)DMAx;
935
936 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
937 DMA_CCR_MSIZE));
938 }
939
940 /**
941 * @brief Set Channel priority level.
942 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
943 * @param DMAx DMAx Instance
944 * @param Channel This parameter can be one of the following values:
945 * @arg @ref LL_DMA_CHANNEL_1
946 * @arg @ref LL_DMA_CHANNEL_2
947 * @arg @ref LL_DMA_CHANNEL_3
948 * @arg @ref LL_DMA_CHANNEL_4
949 * @arg @ref LL_DMA_CHANNEL_5
950 * @arg @ref LL_DMA_CHANNEL_6
951 * @arg @ref LL_DMA_CHANNEL_7 (*)
952 * @arg @ref LL_DMA_CHANNEL_8 (*)
953 * (*) Not on all G4 devices
954 * @param Priority This parameter can be one of the following values:
955 * @arg @ref LL_DMA_PRIORITY_LOW
956 * @arg @ref LL_DMA_PRIORITY_MEDIUM
957 * @arg @ref LL_DMA_PRIORITY_HIGH
958 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
959 * @retval None
960 */
961 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
962 {
963 register uint32_t dma_base_addr = (uint32_t)DMAx;
964
965 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
966 Priority);
967 }
968
969 /**
970 * @brief Get Channel priority level.
971 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
972 * @param DMAx DMAx Instance
973 * @param Channel This parameter can be one of the following values:
974 * @arg @ref LL_DMA_CHANNEL_1
975 * @arg @ref LL_DMA_CHANNEL_2
976 * @arg @ref LL_DMA_CHANNEL_3
977 * @arg @ref LL_DMA_CHANNEL_4
978 * @arg @ref LL_DMA_CHANNEL_5
979 * @arg @ref LL_DMA_CHANNEL_6
980 * @arg @ref LL_DMA_CHANNEL_7 (*)
981 * @arg @ref LL_DMA_CHANNEL_8 (*)
982 * (*) Not on all G4 devices
983 * @retval Returned value can be one of the following values:
984 * @arg @ref LL_DMA_PRIORITY_LOW
985 * @arg @ref LL_DMA_PRIORITY_MEDIUM
986 * @arg @ref LL_DMA_PRIORITY_HIGH
987 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
988 */
989 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
990 {
991 register uint32_t dma_base_addr = (uint32_t)DMAx;
992
993 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
994 DMA_CCR_PL));
995 }
996
997 /**
998 * @brief Set Number of data to transfer.
999 * @note This action has no effect if
1000 * channel is enabled.
1001 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
1002 * @param DMAx DMAx Instance
1003 * @param Channel This parameter can be one of the following values:
1004 * @arg @ref LL_DMA_CHANNEL_1
1005 * @arg @ref LL_DMA_CHANNEL_2
1006 * @arg @ref LL_DMA_CHANNEL_3
1007 * @arg @ref LL_DMA_CHANNEL_4
1008 * @arg @ref LL_DMA_CHANNEL_5
1009 * @arg @ref LL_DMA_CHANNEL_6
1010 * @arg @ref LL_DMA_CHANNEL_7 (*)
1011 * @arg @ref LL_DMA_CHANNEL_8 (*)
1012 * (*) Not on all G4 devices
1013 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
1014 * @retval None
1015 */
1016 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
1017 {
1018 register uint32_t dma_base_addr = (uint32_t)DMAx;
1019
1020 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
1021 DMA_CNDTR_NDT, NbData);
1022 }
1023
1024 /**
1025 * @brief Get Number of data to transfer.
1026 * @note Once the channel is enabled, the return value indicate the
1027 * remaining bytes to be transmitted.
1028 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
1029 * @param DMAx DMAx Instance
1030 * @param Channel This parameter can be one of the following values:
1031 * @arg @ref LL_DMA_CHANNEL_1
1032 * @arg @ref LL_DMA_CHANNEL_2
1033 * @arg @ref LL_DMA_CHANNEL_3
1034 * @arg @ref LL_DMA_CHANNEL_4
1035 * @arg @ref LL_DMA_CHANNEL_5
1036 * @arg @ref LL_DMA_CHANNEL_6
1037 * @arg @ref LL_DMA_CHANNEL_7 (*)
1038 * @arg @ref LL_DMA_CHANNEL_8 (*)
1039 * (*) Not on all G4 devices
1040 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1041 */
1042 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
1043 {
1044 register uint32_t dma_base_addr = (uint32_t)DMAx;
1045
1046 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
1047 DMA_CNDTR_NDT));
1048 }
1049
1050 /**
1051 * @brief Configure the Source and Destination addresses.
1052 * @note This API must not be called when the DMA channel is enabled.
1053 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
1054 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
1055 * CMAR MA LL_DMA_ConfigAddresses
1056 * @param DMAx DMAx Instance
1057 * @param Channel This parameter can be one of the following values:
1058 * @arg @ref LL_DMA_CHANNEL_1
1059 * @arg @ref LL_DMA_CHANNEL_2
1060 * @arg @ref LL_DMA_CHANNEL_3
1061 * @arg @ref LL_DMA_CHANNEL_4
1062 * @arg @ref LL_DMA_CHANNEL_5
1063 * @arg @ref LL_DMA_CHANNEL_6
1064 * @arg @ref LL_DMA_CHANNEL_7 (*)
1065 * @arg @ref LL_DMA_CHANNEL_8 (*)
1066 * (*) Not on all G4 devices
1067 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1068 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1069 * @param Direction This parameter can be one of the following values:
1070 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1071 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1072 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1073 * @retval None
1074 */
1075 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
1076 uint32_t DstAddress, uint32_t Direction)
1077 {
1078 register uint32_t dma_base_addr = (uint32_t)DMAx;
1079
1080 /* Direction Memory to Periph */
1081 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1082 {
1083 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
1084 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
1085 }
1086 /* Direction Periph to Memory and Memory to Memory */
1087 else
1088 {
1089 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
1090 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
1091 }
1092 }
1093
1094 /**
1095 * @brief Set the Memory address.
1096 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1097 * @note This API must not be called when the DMA channel is enabled.
1098 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
1099 * @param DMAx DMAx Instance
1100 * @param Channel This parameter can be one of the following values:
1101 * @arg @ref LL_DMA_CHANNEL_1
1102 * @arg @ref LL_DMA_CHANNEL_2
1103 * @arg @ref LL_DMA_CHANNEL_3
1104 * @arg @ref LL_DMA_CHANNEL_4
1105 * @arg @ref LL_DMA_CHANNEL_5
1106 * @arg @ref LL_DMA_CHANNEL_6
1107 * @arg @ref LL_DMA_CHANNEL_7 (*)
1108 * @arg @ref LL_DMA_CHANNEL_8 (*)
1109 * (*) Not on all G4 devices
1110 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1111 * @retval None
1112 */
1113 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1114 {
1115 register uint32_t dma_base_addr = (uint32_t)DMAx;
1116
1117 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1118 }
1119
1120 /**
1121 * @brief Set the Peripheral address.
1122 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1123 * @note This API must not be called when the DMA channel is enabled.
1124 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
1125 * @param DMAx DMAx Instance
1126 * @param Channel This parameter can be one of the following values:
1127 * @arg @ref LL_DMA_CHANNEL_1
1128 * @arg @ref LL_DMA_CHANNEL_2
1129 * @arg @ref LL_DMA_CHANNEL_3
1130 * @arg @ref LL_DMA_CHANNEL_4
1131 * @arg @ref LL_DMA_CHANNEL_5
1132 * @arg @ref LL_DMA_CHANNEL_6
1133 * @arg @ref LL_DMA_CHANNEL_7 (*)
1134 * @arg @ref LL_DMA_CHANNEL_8 (*)
1135 * (*) Not on all G4 devices
1136 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1137 * @retval None
1138 */
1139 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1140 {
1141 register uint32_t dma_base_addr = (uint32_t)DMAx;
1142
1143 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
1144 }
1145
1146 /**
1147 * @brief Get Memory address.
1148 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1149 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1150 * @param DMAx DMAx Instance
1151 * @param Channel This parameter can be one of the following values:
1152 * @arg @ref LL_DMA_CHANNEL_1
1153 * @arg @ref LL_DMA_CHANNEL_2
1154 * @arg @ref LL_DMA_CHANNEL_3
1155 * @arg @ref LL_DMA_CHANNEL_4
1156 * @arg @ref LL_DMA_CHANNEL_5
1157 * @arg @ref LL_DMA_CHANNEL_6
1158 * @arg @ref LL_DMA_CHANNEL_7 (*)
1159 * @arg @ref LL_DMA_CHANNEL_8 (*)
1160 * (*) Not on all G4 devices
1161 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1162 */
1163 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1164 {
1165 register uint32_t dma_base_addr = (uint32_t)DMAx;
1166
1167 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1168 }
1169
1170 /**
1171 * @brief Get Peripheral address.
1172 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1173 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1174 * @param DMAx DMAx Instance
1175 * @param Channel This parameter can be one of the following values:
1176 * @arg @ref LL_DMA_CHANNEL_1
1177 * @arg @ref LL_DMA_CHANNEL_2
1178 * @arg @ref LL_DMA_CHANNEL_3
1179 * @arg @ref LL_DMA_CHANNEL_4
1180 * @arg @ref LL_DMA_CHANNEL_5
1181 * @arg @ref LL_DMA_CHANNEL_6
1182 * @arg @ref LL_DMA_CHANNEL_7 (*)
1183 * @arg @ref LL_DMA_CHANNEL_8 (*)
1184 * (*) Not on all G4 devices
1185 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1186 */
1187 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1188 {
1189 register uint32_t dma_base_addr = (uint32_t)DMAx;
1190
1191 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1192 }
1193
1194 /**
1195 * @brief Set the Memory to Memory Source address.
1196 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1197 * @note This API must not be called when the DMA channel is enabled.
1198 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1199 * @param DMAx DMAx Instance
1200 * @param Channel This parameter can be one of the following values:
1201 * @arg @ref LL_DMA_CHANNEL_1
1202 * @arg @ref LL_DMA_CHANNEL_2
1203 * @arg @ref LL_DMA_CHANNEL_3
1204 * @arg @ref LL_DMA_CHANNEL_4
1205 * @arg @ref LL_DMA_CHANNEL_5
1206 * @arg @ref LL_DMA_CHANNEL_6
1207 * @arg @ref LL_DMA_CHANNEL_7 (*)
1208 * @arg @ref LL_DMA_CHANNEL_8 (*)
1209 * (*) Not on all G4 devices
1210 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1211 * @retval None
1212 */
1213 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1214 {
1215 register uint32_t dma_base_addr = (uint32_t)DMAx;
1216
1217 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1218 }
1219
1220 /**
1221 * @brief Set the Memory to Memory Destination address.
1222 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1223 * @note This API must not be called when the DMA channel is enabled.
1224 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1225 * @param DMAx DMAx Instance
1226 * @param Channel This parameter can be one of the following values:
1227 * @arg @ref LL_DMA_CHANNEL_1
1228 * @arg @ref LL_DMA_CHANNEL_2
1229 * @arg @ref LL_DMA_CHANNEL_3
1230 * @arg @ref LL_DMA_CHANNEL_4
1231 * @arg @ref LL_DMA_CHANNEL_5
1232 * @arg @ref LL_DMA_CHANNEL_6
1233 * @arg @ref LL_DMA_CHANNEL_7 (*)
1234 * @arg @ref LL_DMA_CHANNEL_8 (*)
1235 * (*) Not on all G4 devices
1236 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1237 * @retval None
1238 */
1239 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1240 {
1241 register uint32_t dma_base_addr = (uint32_t)DMAx;
1242
1243 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1244 }
1245
1246 /**
1247 * @brief Get the Memory to Memory Source address.
1248 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1249 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1250 * @param DMAx DMAx Instance
1251 * @param Channel This parameter can be one of the following values:
1252 * @arg @ref LL_DMA_CHANNEL_1
1253 * @arg @ref LL_DMA_CHANNEL_2
1254 * @arg @ref LL_DMA_CHANNEL_3
1255 * @arg @ref LL_DMA_CHANNEL_4
1256 * @arg @ref LL_DMA_CHANNEL_5
1257 * @arg @ref LL_DMA_CHANNEL_6
1258 * @arg @ref LL_DMA_CHANNEL_7 (*)
1259 * @arg @ref LL_DMA_CHANNEL_8 (*)
1260 * (*) Not on all G4 devices
1261 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1262 */
1263 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1264 {
1265 register uint32_t dma_base_addr = (uint32_t)DMAx;
1266
1267 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1268 }
1269
1270 /**
1271 * @brief Get the Memory to Memory Destination address.
1272 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1273 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1274 * @param DMAx DMAx Instance
1275 * @param Channel This parameter can be one of the following values:
1276 * @arg @ref LL_DMA_CHANNEL_1
1277 * @arg @ref LL_DMA_CHANNEL_2
1278 * @arg @ref LL_DMA_CHANNEL_3
1279 * @arg @ref LL_DMA_CHANNEL_4
1280 * @arg @ref LL_DMA_CHANNEL_5
1281 * @arg @ref LL_DMA_CHANNEL_6
1282 * @arg @ref LL_DMA_CHANNEL_7 (*)
1283 * @arg @ref LL_DMA_CHANNEL_8 (*)
1284 * (*) Not on all G4 devices
1285 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1286 */
1287 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1288 {
1289 register uint32_t dma_base_addr = (uint32_t)DMAx;
1290
1291 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1292 }
1293
1294 /**
1295 * @brief Set DMA request for DMA instance on Channel x.
1296 * @note Please refer to Reference Manual to get the available mapping of Request value link to Channel Selection.
1297 * @rmtoll CSELR C1S LL_DMA_SetPeriphRequest\n
1298 * CSELR C2S LL_DMA_SetPeriphRequest\n
1299 * CSELR C3S LL_DMA_SetPeriphRequest\n
1300 * CSELR C4S LL_DMA_SetPeriphRequest\n
1301 * CSELR C5S LL_DMA_SetPeriphRequest\n
1302 * CSELR C6S LL_DMA_SetPeriphRequest\n
1303 * CSELR C7S LL_DMA_SetPeriphRequest
1304 * @param DMAx DMAx Instance
1305 * @param Channel This parameter can be one of the following values:
1306 * @arg @ref LL_DMA_CHANNEL_1
1307 * @arg @ref LL_DMA_CHANNEL_2
1308 * @arg @ref LL_DMA_CHANNEL_3
1309 * @arg @ref LL_DMA_CHANNEL_4
1310 * @arg @ref LL_DMA_CHANNEL_5
1311 * @arg @ref LL_DMA_CHANNEL_6
1312 * @arg @ref LL_DMA_CHANNEL_7 (*)
1313 * @arg @ref LL_DMA_CHANNEL_8 (*)
1314 * (*) Not on all G4 devices
1315 * @param PeriphRequest This parameter can be one of the following values:
1316 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1317 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1318 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1319 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1320 * @arg @ref LL_DMAMUX_REQ_ADC1
1321 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1322 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1323 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1324 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1325 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1326 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1327 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1328 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1329 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1330 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1331 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1332 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1333 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1334 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1335 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1336 * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
1337 * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
1338 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1339 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1340 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1341 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1342 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1343 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1344 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1345 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1346 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1347 * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
1348 * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
1349 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1350 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1351 * @arg @ref LL_DMAMUX_REQ_ADC2
1352 * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
1353 * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
1354 * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
1355 * @arg @ref LL_DMAMUX_REQ_QSPI (*)
1356 * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
1357 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1358 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1359 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1360 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1361 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1362 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1363 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1364 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1365 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1366 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1367 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1368 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1369 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1370 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1371 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1372 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1373 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1374 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1375 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1376 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1377 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1378 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1379 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1380 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1381 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1382 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1383 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1384 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1385 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1386 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1387 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
1388 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
1389 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
1390 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
1391 * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
1392 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
1393 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1394 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1395 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1396 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1397 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1398 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1399 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1400 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1401 * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
1402 * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
1403 * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
1404 * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
1405 * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
1406 * @arg @ref LL_DMAMUX_REQ_AES_IN
1407 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1408 * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
1409 * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
1410 * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
1411 * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
1412 * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
1413 * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
1414 * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
1415 * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
1416 * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
1417 * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
1418 * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
1419 * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
1420 * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
1421 * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
1422 * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
1423 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1424 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1425 * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
1426 * @arg @ref LL_DMAMUX_REQ_FMAC_READ
1427 * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
1428 * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
1429 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
1430 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
1431 * (*) Not on all G4 devices
1432 * @retval None
1433 */
1434 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphRequest)
1435 {
1436 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
1437 MODIFY_REG((DMAMUX1_Channel0 + Channel - 1 + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID, PeriphRequest);
1438 }
1439
1440 /**
1441 * @brief Get DMA request for DMA instance on Channel x.
1442 * @rmtoll CSELR C1S LL_DMA_GetPeriphRequest\n
1443 * CSELR C2S LL_DMA_GetPeriphRequest\n
1444 * CSELR C3S LL_DMA_GetPeriphRequest\n
1445 * CSELR C4S LL_DMA_GetPeriphRequest\n
1446 * CSELR C5S LL_DMA_GetPeriphRequest\n
1447 * CSELR C6S LL_DMA_GetPeriphRequest\n
1448 * CSELR C7S LL_DMA_GetPeriphRequest
1449 * @param DMAx DMAx Instance
1450 * @param Channel This parameter can be one of the following values:
1451 * @arg @ref LL_DMA_CHANNEL_1
1452 * @arg @ref LL_DMA_CHANNEL_2
1453 * @arg @ref LL_DMA_CHANNEL_3
1454 * @arg @ref LL_DMA_CHANNEL_4
1455 * @arg @ref LL_DMA_CHANNEL_5
1456 * @arg @ref LL_DMA_CHANNEL_6
1457 * @arg @ref LL_DMA_CHANNEL_7 (*)
1458 * @arg @ref LL_DMA_CHANNEL_8 (*)
1459 * (*) Not on all G4 devices
1460 * @retval Returned value can be one of the following values:
1461 * @arg @ref LL_DMAMUX_REQ_GENERATOR0
1462 * @arg @ref LL_DMAMUX_REQ_GENERATOR1
1463 * @arg @ref LL_DMAMUX_REQ_GENERATOR2
1464 * @arg @ref LL_DMAMUX_REQ_GENERATOR3
1465 * @arg @ref LL_DMAMUX_REQ_ADC1
1466 * @arg @ref LL_DMAMUX_REQ_DAC1_CH1
1467 * @arg @ref LL_DMAMUX_REQ_DAC1_CH2
1468 * @arg @ref LL_DMAMUX_REQ_TIM6_UP
1469 * @arg @ref LL_DMAMUX_REQ_TIM7_UP
1470 * @arg @ref LL_DMAMUX_REQ_SPI1_RX
1471 * @arg @ref LL_DMAMUX_REQ_SPI1_TX
1472 * @arg @ref LL_DMAMUX_REQ_SPI2_RX
1473 * @arg @ref LL_DMAMUX_REQ_SPI2_TX
1474 * @arg @ref LL_DMAMUX_REQ_SPI3_RX
1475 * @arg @ref LL_DMAMUX_REQ_SPI3_TX
1476 * @arg @ref LL_DMAMUX_REQ_I2C1_RX
1477 * @arg @ref LL_DMAMUX_REQ_I2C1_TX
1478 * @arg @ref LL_DMAMUX_REQ_I2C2_RX
1479 * @arg @ref LL_DMAMUX_REQ_I2C2_TX
1480 * @arg @ref LL_DMAMUX_REQ_I2C3_RX
1481 * @arg @ref LL_DMAMUX_REQ_I2C3_TX (*)
1482 * @arg @ref LL_DMAMUX_REQ_I2C4_RX (*)
1483 * @arg @ref LL_DMAMUX_REQ_I2C4_TX
1484 * @arg @ref LL_DMAMUX_REQ_USART1_RX
1485 * @arg @ref LL_DMAMUX_REQ_USART1_TX
1486 * @arg @ref LL_DMAMUX_REQ_USART2_RX
1487 * @arg @ref LL_DMAMUX_REQ_USART2_TX
1488 * @arg @ref LL_DMAMUX_REQ_USART3_RX
1489 * @arg @ref LL_DMAMUX_REQ_USART3_TX
1490 * @arg @ref LL_DMAMUX_REQ_UART4_RX
1491 * @arg @ref LL_DMAMUX_REQ_UART4_TX
1492 * @arg @ref LL_DMAMUX_REQ_UART5_RX (*)
1493 * @arg @ref LL_DMAMUX_REQ_UART5_TX (*)
1494 * @arg @ref LL_DMAMUX_REQ_LPUART1_RX
1495 * @arg @ref LL_DMAMUX_REQ_LPUART1_TX
1496 * @arg @ref LL_DMAMUX_REQ_ADC2
1497 * @arg @ref LL_DMAMUX_REQ_ADC3 (*)
1498 * @arg @ref LL_DMAMUX_REQ_ADC4 (*)
1499 * @arg @ref LL_DMAMUX_REQ_ADC5 (*)
1500 * @arg @ref LL_DMAMUX_REQ_QSPI (*)
1501 * @arg @ref LL_DMAMUX_REQ_DAC2_CH1 (*)
1502 * @arg @ref LL_DMAMUX_REQ_TIM1_CH1
1503 * @arg @ref LL_DMAMUX_REQ_TIM1_CH2
1504 * @arg @ref LL_DMAMUX_REQ_TIM1_CH3
1505 * @arg @ref LL_DMAMUX_REQ_TIM1_CH4
1506 * @arg @ref LL_DMAMUX_REQ_TIM1_UP
1507 * @arg @ref LL_DMAMUX_REQ_TIM1_TRIG
1508 * @arg @ref LL_DMAMUX_REQ_TIM1_COM
1509 * @arg @ref LL_DMAMUX_REQ_TIM8_CH1
1510 * @arg @ref LL_DMAMUX_REQ_TIM8_CH2
1511 * @arg @ref LL_DMAMUX_REQ_TIM8_CH3
1512 * @arg @ref LL_DMAMUX_REQ_TIM8_CH4
1513 * @arg @ref LL_DMAMUX_REQ_TIM8_UP
1514 * @arg @ref LL_DMAMUX_REQ_TIM8_TRIG
1515 * @arg @ref LL_DMAMUX_REQ_TIM8_COM
1516 * @arg @ref LL_DMAMUX_REQ_TIM2_CH1
1517 * @arg @ref LL_DMAMUX_REQ_TIM2_CH2
1518 * @arg @ref LL_DMAMUX_REQ_TIM2_CH3
1519 * @arg @ref LL_DMAMUX_REQ_TIM2_CH4
1520 * @arg @ref LL_DMAMUX_REQ_TIM2_UP
1521 * @arg @ref LL_DMAMUX_REQ_TIM3_CH1
1522 * @arg @ref LL_DMAMUX_REQ_TIM3_CH2
1523 * @arg @ref LL_DMAMUX_REQ_TIM3_CH3
1524 * @arg @ref LL_DMAMUX_REQ_TIM3_CH4
1525 * @arg @ref LL_DMAMUX_REQ_TIM3_UP
1526 * @arg @ref LL_DMAMUX_REQ_TIM3_TRIG
1527 * @arg @ref LL_DMAMUX_REQ_TIM4_CH1
1528 * @arg @ref LL_DMAMUX_REQ_TIM4_CH2
1529 * @arg @ref LL_DMAMUX_REQ_TIM4_CH3
1530 * @arg @ref LL_DMAMUX_REQ_TIM4_CH4
1531 * @arg @ref LL_DMAMUX_REQ_TIM4_UP
1532 * @arg @ref LL_DMAMUX_REQ_TIM5_CH1 (*)
1533 * @arg @ref LL_DMAMUX_REQ_TIM5_CH2 (*)
1534 * @arg @ref LL_DMAMUX_REQ_TIM5_CH3 (*)
1535 * @arg @ref LL_DMAMUX_REQ_TIM5_CH4 (*)
1536 * @arg @ref LL_DMAMUX_REQ_TIM5_UP (*)
1537 * @arg @ref LL_DMAMUX_REQ_TIM5_TRIG (*)
1538 * @arg @ref LL_DMAMUX_REQ_TIM15_CH1
1539 * @arg @ref LL_DMAMUX_REQ_TIM15_UP
1540 * @arg @ref LL_DMAMUX_REQ_TIM15_TRIG
1541 * @arg @ref LL_DMAMUX_REQ_TIM15_COM
1542 * @arg @ref LL_DMAMUX_REQ_TIM16_CH1
1543 * @arg @ref LL_DMAMUX_REQ_TIM16_UP
1544 * @arg @ref LL_DMAMUX_REQ_TIM17_CH1
1545 * @arg @ref LL_DMAMUX_REQ_TIM17_UP
1546 * @arg @ref LL_DMAMUX_REQ_TIM20_CH1 (*)
1547 * @arg @ref LL_DMAMUX_REQ_TIM20_CH2 (*)
1548 * @arg @ref LL_DMAMUX_REQ_TIM20_CH3 (*)
1549 * @arg @ref LL_DMAMUX_REQ_TIM20_CH4 (*)
1550 * @arg @ref LL_DMAMUX_REQ_TIM20_UP (*)
1551 * @arg @ref LL_DMAMUX_REQ_AES_IN
1552 * @arg @ref LL_DMAMUX_REQ_AES_OUT
1553 * @arg @ref LL_DMAMUX_REQ_TIM20_TRIG (*)
1554 * @arg @ref LL_DMAMUX_REQ_TIM20_COM (*)
1555 * @arg @ref LL_DMAMUX_REQ_HRTIM1_M (*)
1556 * @arg @ref LL_DMAMUX_REQ_HRTIM1_A (*)
1557 * @arg @ref LL_DMAMUX_REQ_HRTIM1_B (*)
1558 * @arg @ref LL_DMAMUX_REQ_HRTIM1_C (*)
1559 * @arg @ref LL_DMAMUX_REQ_HRTIM1_D (*)
1560 * @arg @ref LL_DMAMUX_REQ_HRTIM1_E (*)
1561 * @arg @ref LL_DMAMUX_REQ_HRTIM1_F (*)
1562 * @arg @ref LL_DMAMUX_REQ_DAC3_CH1
1563 * @arg @ref LL_DMAMUX_REQ_DAC3_CH2
1564 * @arg @ref LL_DMAMUX_REQ_DAC4_CH1 (*)
1565 * @arg @ref LL_DMAMUX_REQ_DAC4_CH2 (*)
1566 * @arg @ref LL_DMAMUX_REQ_SPI4_RX (*)
1567 * @arg @ref LL_DMAMUX_REQ_SPI4_TX (*)
1568 * @arg @ref LL_DMAMUX_REQ_SAI1_A
1569 * @arg @ref LL_DMAMUX_REQ_SAI1_B
1570 * @arg @ref LL_DMAMUX_REQ_FMAC_WRITE
1571 * @arg @ref LL_DMAMUX_REQ_FMAC_READ
1572 * @arg @ref LL_DMAMUX_REQ_CORDIC_WRITE
1573 * @arg @ref LL_DMAMUX_REQ_CORDIC_READ
1574 * @arg @ref LL_DMAMUX_REQ_UCPD1_RX
1575 * @arg @ref LL_DMAMUX_REQ_UCPD1_TX
1576 * (*) Not on all G4 devices
1577 */
1578 __STATIC_INLINE uint32_t LL_DMA_GetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Channel)
1579 {
1580 uint32_t dmamux_ccr_offset = ((((uint32_t)DMAx ^ (uint32_t)DMA1) >> 10U) * 8U);
1581 return (READ_BIT((DMAMUX1_Channel0 + Channel - 1 + dmamux_ccr_offset)->CCR, DMAMUX_CxCR_DMAREQ_ID));
1582 }
1583
1584 /**
1585 * @}
1586 */
1587
1588 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1589 * @{
1590 */
1591
1592 /**
1593 * @brief Get Channel 1 global interrupt flag.
1594 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1595 * @param DMAx DMAx Instance
1596 * @retval State of bit (1 or 0).
1597 */
1598 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1599 {
1600 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1)) ? 1UL : 0UL);
1601 }
1602
1603 /**
1604 * @brief Get Channel 2 global interrupt flag.
1605 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1606 * @param DMAx DMAx Instance
1607 * @retval State of bit (1 or 0).
1608 */
1609 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1610 {
1611 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2)) ? 1UL : 0UL);
1612 }
1613
1614 /**
1615 * @brief Get Channel 3 global interrupt flag.
1616 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1617 * @param DMAx DMAx Instance
1618 * @retval State of bit (1 or 0).
1619 */
1620 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1621 {
1622 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3)) ? 1UL : 0UL);
1623 }
1624
1625 /**
1626 * @brief Get Channel 4 global interrupt flag.
1627 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1628 * @param DMAx DMAx Instance
1629 * @retval State of bit (1 or 0).
1630 */
1631 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1632 {
1633 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4)) ? 1UL : 0UL);
1634 }
1635
1636 /**
1637 * @brief Get Channel 5 global interrupt flag.
1638 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1639 * @param DMAx DMAx Instance
1640 * @retval State of bit (1 or 0).
1641 */
1642 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1643 {
1644 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5)) ? 1UL : 0UL);
1645 }
1646
1647 /**
1648 * @brief Get Channel 6 global interrupt flag.
1649 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1650 * @param DMAx DMAx Instance
1651 * @retval State of bit (1 or 0).
1652 */
1653 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1654 {
1655 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6)) ? 1UL : 0UL);
1656 }
1657
1658 #if defined (DMA1_Channel7)
1659 /**
1660 * @brief Get Channel 7 global interrupt flag.
1661 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1662 * @param DMAx DMAx Instance
1663 * @retval State of bit (1 or 0).
1664 */
1665 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1666 {
1667 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7)) ? 1UL : 0UL);
1668 }
1669 #endif /* DMA1_Channel7 */
1670
1671 #if defined (DMA1_Channel8)
1672 /**
1673 * @brief Get Channel 8 global interrupt flag.
1674 * @rmtoll ISR GIF8 LL_DMA_IsActiveFlag_GI8
1675 * @param DMAx DMAx Instance
1676 * @retval State of bit (1 or 0).
1677 */
1678 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI8(DMA_TypeDef *DMAx)
1679 {
1680 return ((READ_BIT(DMAx->ISR, DMA_ISR_GIF8) == (DMA_ISR_GIF8)) ? 1UL : 0UL);
1681 }
1682 #endif /* DMA1_Channel8 */
1683
1684 /**
1685 * @brief Get Channel 1 transfer complete flag.
1686 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1687 * @param DMAx DMAx Instance
1688 * @retval State of bit (1 or 0).
1689 */
1690 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1691 {
1692 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1)) ? 1UL : 0UL);
1693 }
1694
1695 /**
1696 * @brief Get Channel 2 transfer complete flag.
1697 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1698 * @param DMAx DMAx Instance
1699 * @retval State of bit (1 or 0).
1700 */
1701 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1702 {
1703 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2)) ? 1UL : 0UL);
1704 }
1705
1706 /**
1707 * @brief Get Channel 3 transfer complete flag.
1708 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1709 * @param DMAx DMAx Instance
1710 * @retval State of bit (1 or 0).
1711 */
1712 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1713 {
1714 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3)) ? 1UL : 0UL);
1715 }
1716
1717 /**
1718 * @brief Get Channel 4 transfer complete flag.
1719 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1720 * @param DMAx DMAx Instance
1721 * @retval State of bit (1 or 0).
1722 */
1723 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1724 {
1725 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4)) ? 1UL : 0UL);
1726 }
1727
1728 /**
1729 * @brief Get Channel 5 transfer complete flag.
1730 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1731 * @param DMAx DMAx Instance
1732 * @retval State of bit (1 or 0).
1733 */
1734 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1735 {
1736 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5)) ? 1UL : 0UL);
1737 }
1738
1739 /**
1740 * @brief Get Channel 6 transfer complete flag.
1741 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1742 * @param DMAx DMAx Instance
1743 * @retval State of bit (1 or 0).
1744 */
1745 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1746 {
1747 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6)) ? 1UL : 0UL);
1748 }
1749
1750 #if defined (DMA1_Channel7)
1751 /**
1752 * @brief Get Channel 7 transfer complete flag.
1753 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1754 * @param DMAx DMAx Instance
1755 * @retval State of bit (1 or 0).
1756 */
1757 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1758 {
1759 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7)) ? 1UL : 0UL);
1760 }
1761 #endif /* DMA1_Channel7 */
1762
1763 #if defined (DMA1_Channel8)
1764 /**
1765 * @brief Get Channel 8 transfer complete flag.
1766 * @rmtoll ISR TCIF8 LL_DMA_IsActiveFlag_TC8
1767 * @param DMAx DMAx Instance
1768 * @retval State of bit (1 or 0).
1769 */
1770 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC8(DMA_TypeDef *DMAx)
1771 {
1772 return ((READ_BIT(DMAx->ISR, DMA_ISR_TCIF8) == (DMA_ISR_TCIF8)) ? 1UL : 0UL);
1773 }
1774 #endif /* DMA1_Channel8 */
1775
1776 /**
1777 * @brief Get Channel 1 half transfer flag.
1778 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1779 * @param DMAx DMAx Instance
1780 * @retval State of bit (1 or 0).
1781 */
1782 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1783 {
1784 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1)) ? 1UL : 0UL);
1785 }
1786
1787 /**
1788 * @brief Get Channel 2 half transfer flag.
1789 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1790 * @param DMAx DMAx Instance
1791 * @retval State of bit (1 or 0).
1792 */
1793 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1794 {
1795 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2)) ? 1UL : 0UL);
1796 }
1797
1798 /**
1799 * @brief Get Channel 3 half transfer flag.
1800 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1801 * @param DMAx DMAx Instance
1802 * @retval State of bit (1 or 0).
1803 */
1804 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1805 {
1806 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3)) ? 1UL : 0UL);
1807 }
1808
1809 /**
1810 * @brief Get Channel 4 half transfer flag.
1811 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1812 * @param DMAx DMAx Instance
1813 * @retval State of bit (1 or 0).
1814 */
1815 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1816 {
1817 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4)) ? 1UL : 0UL);
1818 }
1819
1820 /**
1821 * @brief Get Channel 5 half transfer flag.
1822 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1823 * @param DMAx DMAx Instance
1824 * @retval State of bit (1 or 0).
1825 */
1826 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1827 {
1828 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5)) ? 1UL : 0UL);
1829 }
1830
1831 /**
1832 * @brief Get Channel 6 half transfer flag.
1833 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1834 * @param DMAx DMAx Instance
1835 * @retval State of bit (1 or 0).
1836 */
1837 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1838 {
1839 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6)) ? 1UL : 0UL);
1840 }
1841
1842 #if defined (DMA1_Channel8)
1843 /**
1844 * @brief Get Channel 7 half transfer flag.
1845 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1846 * @param DMAx DMAx Instance
1847 * @retval State of bit (1 or 0).
1848 */
1849 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1850 {
1851 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7)) ? 1UL : 0UL);
1852 }
1853 #endif /* DMA1_Channel7 */
1854
1855 #if defined (DMA1_Channel8)
1856 /**
1857 * @brief Get Channel 8 half transfer flag.
1858 * @rmtoll ISR HTIF8 LL_DMA_IsActiveFlag_HT8
1859 * @param DMAx DMAx Instance
1860 * @retval State of bit (1 or 0).
1861 */
1862 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT8(DMA_TypeDef *DMAx)
1863 {
1864 return ((READ_BIT(DMAx->ISR, DMA_ISR_HTIF8) == (DMA_ISR_HTIF8)) ? 1UL : 0UL);
1865 }
1866 #endif /* DMA1_Channel8 */
1867
1868 /**
1869 * @brief Get Channel 1 transfer error flag.
1870 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1871 * @param DMAx DMAx Instance
1872 * @retval State of bit (1 or 0).
1873 */
1874 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1875 {
1876 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1)) ? 1UL : 0UL);
1877 }
1878
1879 /**
1880 * @brief Get Channel 2 transfer error flag.
1881 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1882 * @param DMAx DMAx Instance
1883 * @retval State of bit (1 or 0).
1884 */
1885 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1886 {
1887 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2)) ? 1UL : 0UL);
1888 }
1889
1890 /**
1891 * @brief Get Channel 3 transfer error flag.
1892 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1893 * @param DMAx DMAx Instance
1894 * @retval State of bit (1 or 0).
1895 */
1896 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1897 {
1898 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3)) ? 1UL : 0UL);
1899 }
1900
1901 /**
1902 * @brief Get Channel 4 transfer error flag.
1903 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1904 * @param DMAx DMAx Instance
1905 * @retval State of bit (1 or 0).
1906 */
1907 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1908 {
1909 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4)) ? 1UL : 0UL);
1910 }
1911
1912 /**
1913 * @brief Get Channel 5 transfer error flag.
1914 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1915 * @param DMAx DMAx Instance
1916 * @retval State of bit (1 or 0).
1917 */
1918 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1919 {
1920 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5)) ? 1UL : 0UL);
1921 }
1922
1923 /**
1924 * @brief Get Channel 6 transfer error flag.
1925 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1926 * @param DMAx DMAx Instance
1927 * @retval State of bit (1 or 0).
1928 */
1929 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1930 {
1931 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6)) ? 1UL : 0UL);
1932 }
1933
1934 #if defined (DMA1_Channel7)
1935 /**
1936 * @brief Get Channel 7 transfer error flag.
1937 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1938 * @param DMAx DMAx Instance
1939 * @retval State of bit (1 or 0).
1940 */
1941 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1942 {
1943 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7)) ? 1UL : 0UL);
1944 }
1945 #endif /* DMA1_Channel7 */
1946
1947 #if defined (DMA1_Channel8)
1948 /**
1949 * @brief Get Channel 8 transfer error flag.
1950 * @rmtoll ISR TEIF8 LL_DMA_IsActiveFlag_TE8
1951 * @param DMAx DMAx Instance
1952 * @retval State of bit (1 or 0).
1953 */
1954 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE8(DMA_TypeDef *DMAx)
1955 {
1956 return ((READ_BIT(DMAx->ISR, DMA_ISR_TEIF8) == (DMA_ISR_TEIF8)) ? 1UL : 0UL);
1957 }
1958 #endif /* DMA1_Channel8 */
1959
1960 /**
1961 * @brief Clear Channel 1 global interrupt flag.
1962 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1963 * @param DMAx DMAx Instance
1964 * @retval None
1965 */
1966 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1967 {
1968 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1969 }
1970
1971 /**
1972 * @brief Clear Channel 2 global interrupt flag.
1973 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1974 * @param DMAx DMAx Instance
1975 * @retval None
1976 */
1977 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1978 {
1979 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1980 }
1981
1982 /**
1983 * @brief Clear Channel 3 global interrupt flag.
1984 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1985 * @param DMAx DMAx Instance
1986 * @retval None
1987 */
1988 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1989 {
1990 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1991 }
1992
1993 /**
1994 * @brief Clear Channel 4 global interrupt flag.
1995 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1996 * @param DMAx DMAx Instance
1997 * @retval None
1998 */
1999 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
2000 {
2001 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
2002 }
2003
2004 /**
2005 * @brief Clear Channel 5 global interrupt flag.
2006 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
2007 * @param DMAx DMAx Instance
2008 * @retval None
2009 */
2010 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
2011 {
2012 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
2013 }
2014
2015 /**
2016 * @brief Clear Channel 6 global interrupt flag.
2017 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
2018 * @param DMAx DMAx Instance
2019 * @retval None
2020 */
2021 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
2022 {
2023 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
2024 }
2025
2026 #if defined (DMA1_Channel7)
2027 /**
2028 * @brief Clear Channel 7 global interrupt flag.
2029 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
2030 * @param DMAx DMAx Instance
2031 * @retval None
2032 */
2033 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
2034 {
2035 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
2036 }
2037 #endif /* DMA1_Channel7 */
2038
2039 #if defined (DMA1_Channel8)
2040 /**
2041 * @brief Clear Channel 8 global interrupt flag.
2042 * @rmtoll IFCR CGIF8 LL_DMA_ClearFlag_GI8
2043 * @param DMAx DMAx Instance
2044 * @retval None
2045 */
2046 __STATIC_INLINE void LL_DMA_ClearFlag_GI8(DMA_TypeDef *DMAx)
2047 {
2048 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF8);
2049 }
2050 #endif /* DMA1_Channel8 */
2051
2052 /**
2053 * @brief Clear Channel 1 transfer complete flag.
2054 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
2055 * @param DMAx DMAx Instance
2056 * @retval None
2057 */
2058 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2059 {
2060 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
2061 }
2062
2063 /**
2064 * @brief Clear Channel 2 transfer complete flag.
2065 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
2066 * @param DMAx DMAx Instance
2067 * @retval None
2068 */
2069 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2070 {
2071 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
2072 }
2073
2074 /**
2075 * @brief Clear Channel 3 transfer complete flag.
2076 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
2077 * @param DMAx DMAx Instance
2078 * @retval None
2079 */
2080 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2081 {
2082 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
2083 }
2084
2085 /**
2086 * @brief Clear Channel 4 transfer complete flag.
2087 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
2088 * @param DMAx DMAx Instance
2089 * @retval None
2090 */
2091 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2092 {
2093 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
2094 }
2095
2096 /**
2097 * @brief Clear Channel 5 transfer complete flag.
2098 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
2099 * @param DMAx DMAx Instance
2100 * @retval None
2101 */
2102 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2103 {
2104 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
2105 }
2106
2107 /**
2108 * @brief Clear Channel 6 transfer complete flag.
2109 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
2110 * @param DMAx DMAx Instance
2111 * @retval None
2112 */
2113 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2114 {
2115 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
2116 }
2117
2118 #if defined (DMA1_Channel7)
2119 /**
2120 * @brief Clear Channel 7 transfer complete flag.
2121 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
2122 * @param DMAx DMAx Instance
2123 * @retval None
2124 */
2125 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2126 {
2127 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
2128 }
2129 #endif /* DMA1_Channel7 */
2130
2131 #if defined (DMA1_Channel8)
2132 /**
2133 * @brief Clear Channel 8 transfer complete flag.
2134 * @rmtoll IFCR CTCIF8 LL_DMA_ClearFlag_TC8
2135 * @param DMAx DMAx Instance
2136 * @retval None
2137 */
2138 __STATIC_INLINE void LL_DMA_ClearFlag_TC8(DMA_TypeDef *DMAx)
2139 {
2140 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF8);
2141 }
2142 #endif /* DMA1_Channel8 */
2143
2144 /**
2145 * @brief Clear Channel 1 half transfer flag.
2146 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
2147 * @param DMAx DMAx Instance
2148 * @retval None
2149 */
2150 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2151 {
2152 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
2153 }
2154
2155 /**
2156 * @brief Clear Channel 2 half transfer flag.
2157 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
2158 * @param DMAx DMAx Instance
2159 * @retval None
2160 */
2161 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2162 {
2163 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
2164 }
2165
2166 /**
2167 * @brief Clear Channel 3 half transfer flag.
2168 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
2169 * @param DMAx DMAx Instance
2170 * @retval None
2171 */
2172 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2173 {
2174 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
2175 }
2176
2177 /**
2178 * @brief Clear Channel 4 half transfer flag.
2179 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
2180 * @param DMAx DMAx Instance
2181 * @retval None
2182 */
2183 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2184 {
2185 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
2186 }
2187
2188 /**
2189 * @brief Clear Channel 5 half transfer flag.
2190 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
2191 * @param DMAx DMAx Instance
2192 * @retval None
2193 */
2194 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2195 {
2196 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
2197 }
2198
2199 /**
2200 * @brief Clear Channel 6 half transfer flag.
2201 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
2202 * @param DMAx DMAx Instance
2203 * @retval None
2204 */
2205 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2206 {
2207 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
2208 }
2209
2210 #if defined (DMA1_Channel7)
2211 /**
2212 * @brief Clear Channel 7 half transfer flag.
2213 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
2214 * @param DMAx DMAx Instance
2215 * @retval None
2216 */
2217 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2218 {
2219 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
2220 }
2221 #endif /* DMA1_Channel7 */
2222
2223 #if defined (DMA1_Channel8)
2224 /**
2225 * @brief Clear Channel 8 half transfer flag.
2226 * @rmtoll IFCR CHTIF8 LL_DMA_ClearFlag_HT8
2227 * @param DMAx DMAx Instance
2228 * @retval None
2229 */
2230 __STATIC_INLINE void LL_DMA_ClearFlag_HT8(DMA_TypeDef *DMAx)
2231 {
2232 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF8);
2233 }
2234 #endif /* DMA1_Channel8 */
2235
2236 /**
2237 * @brief Clear Channel 1 transfer error flag.
2238 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
2239 * @param DMAx DMAx Instance
2240 * @retval None
2241 */
2242 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2243 {
2244 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
2245 }
2246
2247 /**
2248 * @brief Clear Channel 2 transfer error flag.
2249 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
2250 * @param DMAx DMAx Instance
2251 * @retval None
2252 */
2253 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2254 {
2255 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
2256 }
2257
2258 /**
2259 * @brief Clear Channel 3 transfer error flag.
2260 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
2261 * @param DMAx DMAx Instance
2262 * @retval None
2263 */
2264 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2265 {
2266 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
2267 }
2268
2269 /**
2270 * @brief Clear Channel 4 transfer error flag.
2271 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
2272 * @param DMAx DMAx Instance
2273 * @retval None
2274 */
2275 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2276 {
2277 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
2278 }
2279
2280 /**
2281 * @brief Clear Channel 5 transfer error flag.
2282 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
2283 * @param DMAx DMAx Instance
2284 * @retval None
2285 */
2286 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2287 {
2288 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
2289 }
2290
2291 /**
2292 * @brief Clear Channel 6 transfer error flag.
2293 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
2294 * @param DMAx DMAx Instance
2295 * @retval None
2296 */
2297 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2298 {
2299 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
2300 }
2301
2302 #if defined (DMA1_Channel7)
2303 /**
2304 * @brief Clear Channel 7 transfer error flag.
2305 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
2306 * @param DMAx DMAx Instance
2307 * @retval None
2308 */
2309 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2310 {
2311 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
2312 }
2313 #endif /* DMA1_Channel7 */
2314
2315 #if defined (DMA1_Channel8)
2316 /**
2317 * @brief Clear Channel 8 transfer error flag.
2318 * @rmtoll IFCR CTEIF8 LL_DMA_ClearFlag_TE8
2319 * @param DMAx DMAx Instance
2320 * @retval None
2321 */
2322 __STATIC_INLINE void LL_DMA_ClearFlag_TE8(DMA_TypeDef *DMAx)
2323 {
2324 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF8);
2325 }
2326 #endif /* DMA1_Channel8 */
2327
2328 /**
2329 * @}
2330 */
2331
2332 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2333 * @{
2334 */
2335 /**
2336 * @brief Enable Transfer complete interrupt.
2337 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
2338 * @param DMAx DMAx Instance
2339 * @param Channel This parameter can be one of the following values:
2340 * @arg @ref LL_DMA_CHANNEL_1
2341 * @arg @ref LL_DMA_CHANNEL_2
2342 * @arg @ref LL_DMA_CHANNEL_3
2343 * @arg @ref LL_DMA_CHANNEL_4
2344 * @arg @ref LL_DMA_CHANNEL_5
2345 * @arg @ref LL_DMA_CHANNEL_6
2346 * @arg @ref LL_DMA_CHANNEL_7 (*)
2347 * @arg @ref LL_DMA_CHANNEL_8 (*)
2348 * (*) Not on all G4 devices
2349 * @retval None
2350 */
2351 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2352 {
2353 register uint32_t dma_base_addr = (uint32_t)DMAx;
2354
2355 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
2356 }
2357
2358 /**
2359 * @brief Enable Half transfer interrupt.
2360 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
2361 * @param DMAx DMAx Instance
2362 * @param Channel This parameter can be one of the following values:
2363 * @arg @ref LL_DMA_CHANNEL_1
2364 * @arg @ref LL_DMA_CHANNEL_2
2365 * @arg @ref LL_DMA_CHANNEL_3
2366 * @arg @ref LL_DMA_CHANNEL_4
2367 * @arg @ref LL_DMA_CHANNEL_5
2368 * @arg @ref LL_DMA_CHANNEL_6
2369 * @arg @ref LL_DMA_CHANNEL_7 (*)
2370 * @arg @ref LL_DMA_CHANNEL_8 (*)
2371 * (*) Not on all G4 devices
2372 * @retval None
2373 */
2374 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2375 {
2376 register uint32_t dma_base_addr = (uint32_t)DMAx;
2377
2378 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
2379 }
2380
2381 /**
2382 * @brief Enable Transfer error interrupt.
2383 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
2384 * @param DMAx DMAx Instance
2385 * @param Channel This parameter can be one of the following values:
2386 * @arg @ref LL_DMA_CHANNEL_1
2387 * @arg @ref LL_DMA_CHANNEL_2
2388 * @arg @ref LL_DMA_CHANNEL_3
2389 * @arg @ref LL_DMA_CHANNEL_4
2390 * @arg @ref LL_DMA_CHANNEL_5
2391 * @arg @ref LL_DMA_CHANNEL_6
2392 * @arg @ref LL_DMA_CHANNEL_7 (*)
2393 * @arg @ref LL_DMA_CHANNEL_8 (*)
2394 * (*) Not on all G4 devices
2395 * @retval None
2396 */
2397 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2398 {
2399 register uint32_t dma_base_addr = (uint32_t)DMAx;
2400
2401 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
2402 }
2403
2404 /**
2405 * @brief Disable Transfer complete interrupt.
2406 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
2407 * @param DMAx DMAx Instance
2408 * @param Channel This parameter can be one of the following values:
2409 * @arg @ref LL_DMA_CHANNEL_1
2410 * @arg @ref LL_DMA_CHANNEL_2
2411 * @arg @ref LL_DMA_CHANNEL_3
2412 * @arg @ref LL_DMA_CHANNEL_4
2413 * @arg @ref LL_DMA_CHANNEL_5
2414 * @arg @ref LL_DMA_CHANNEL_6
2415 * @arg @ref LL_DMA_CHANNEL_7 (*)
2416 * @arg @ref LL_DMA_CHANNEL_8 (*)
2417 * (*) Not on all G4 devices
2418 * @retval None
2419 */
2420 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2421 {
2422 register uint32_t dma_base_addr = (uint32_t)DMAx;
2423
2424 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
2425 }
2426
2427 /**
2428 * @brief Disable Half transfer interrupt.
2429 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
2430 * @param DMAx DMAx Instance
2431 * @param Channel This parameter can be one of the following values:
2432 * @arg @ref LL_DMA_CHANNEL_1
2433 * @arg @ref LL_DMA_CHANNEL_2
2434 * @arg @ref LL_DMA_CHANNEL_3
2435 * @arg @ref LL_DMA_CHANNEL_4
2436 * @arg @ref LL_DMA_CHANNEL_5
2437 * @arg @ref LL_DMA_CHANNEL_6
2438 * @arg @ref LL_DMA_CHANNEL_7 (*)
2439 * @arg @ref LL_DMA_CHANNEL_8 (*)
2440 * (*) Not on all G4 devices
2441 * @retval None
2442 */
2443 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2444 {
2445 register uint32_t dma_base_addr = (uint32_t)DMAx;
2446
2447 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
2448 }
2449
2450 /**
2451 * @brief Disable Transfer error interrupt.
2452 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
2453 * @param DMAx DMAx Instance
2454 * @param Channel This parameter can be one of the following values:
2455 * @arg @ref LL_DMA_CHANNEL_1
2456 * @arg @ref LL_DMA_CHANNEL_2
2457 * @arg @ref LL_DMA_CHANNEL_3
2458 * @arg @ref LL_DMA_CHANNEL_4
2459 * @arg @ref LL_DMA_CHANNEL_5
2460 * @arg @ref LL_DMA_CHANNEL_6
2461 * @arg @ref LL_DMA_CHANNEL_7 (*)
2462 * @arg @ref LL_DMA_CHANNEL_8 (*)
2463 * (*) Not on all G4 devices
2464 * @retval None
2465 */
2466 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2467 {
2468 register uint32_t dma_base_addr = (uint32_t)DMAx;
2469
2470 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
2471 }
2472
2473 /**
2474 * @brief Check if Transfer complete Interrupt is enabled.
2475 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
2476 * @param DMAx DMAx Instance
2477 * @param Channel This parameter can be one of the following values:
2478 * @arg @ref LL_DMA_CHANNEL_1
2479 * @arg @ref LL_DMA_CHANNEL_2
2480 * @arg @ref LL_DMA_CHANNEL_3
2481 * @arg @ref LL_DMA_CHANNEL_4
2482 * @arg @ref LL_DMA_CHANNEL_5
2483 * @arg @ref LL_DMA_CHANNEL_6
2484 * @arg @ref LL_DMA_CHANNEL_7 (*)
2485 * @arg @ref LL_DMA_CHANNEL_8 (*)
2486 * (*) Not on all G4 devices
2487 * @retval State of bit (1 or 0).
2488 */
2489 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
2490 {
2491 register uint32_t dma_base_addr = (uint32_t)DMAx;
2492
2493 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
2494 DMA_CCR_TCIE) == (DMA_CCR_TCIE)) ? 1UL : 0UL);
2495 }
2496
2497 /**
2498 * @brief Check if Half transfer Interrupt is enabled.
2499 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
2500 * @param DMAx DMAx Instance
2501 * @param Channel This parameter can be one of the following values:
2502 * @arg @ref LL_DMA_CHANNEL_1
2503 * @arg @ref LL_DMA_CHANNEL_2
2504 * @arg @ref LL_DMA_CHANNEL_3
2505 * @arg @ref LL_DMA_CHANNEL_4
2506 * @arg @ref LL_DMA_CHANNEL_5
2507 * @arg @ref LL_DMA_CHANNEL_6
2508 * @arg @ref LL_DMA_CHANNEL_7 (*)
2509 * @arg @ref LL_DMA_CHANNEL_8 (*)
2510 * (*) Not on all G4 devices
2511 * @retval State of bit (1 or 0).
2512 */
2513 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
2514 {
2515 register uint32_t dma_base_addr = (uint32_t)DMAx;
2516
2517 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
2518 DMA_CCR_HTIE) == (DMA_CCR_HTIE)) ? 1UL : 0UL);
2519 }
2520
2521 /**
2522 * @brief Check if Transfer error Interrupt is enabled.
2523 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
2524 * @param DMAx DMAx Instance
2525 * @param Channel This parameter can be one of the following values:
2526 * @arg @ref LL_DMA_CHANNEL_1
2527 * @arg @ref LL_DMA_CHANNEL_2
2528 * @arg @ref LL_DMA_CHANNEL_3
2529 * @arg @ref LL_DMA_CHANNEL_4
2530 * @arg @ref LL_DMA_CHANNEL_5
2531 * @arg @ref LL_DMA_CHANNEL_6
2532 * @arg @ref LL_DMA_CHANNEL_7 (*)
2533 * @arg @ref LL_DMA_CHANNEL_8 (*)
2534 * (*) Not on all G4 devices
2535 * @retval State of bit (1 or 0).
2536 */
2537 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
2538 {
2539 register uint32_t dma_base_addr = (uint32_t)DMAx;
2540
2541 return ((READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)(dma_base_addr + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
2542 DMA_CCR_TEIE) == (DMA_CCR_TEIE)) ? 1UL : 0UL);
2543 }
2544
2545 /**
2546 * @}
2547 */
2548
2549 #if defined(USE_FULL_LL_DRIVER)
2550 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2551 * @{
2552 */
2553
2554 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
2555 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
2556 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2557
2558 /**
2559 * @}
2560 */
2561 #endif /* USE_FULL_LL_DRIVER */
2562
2563 /**
2564 * @}
2565 */
2566
2567 /**
2568 * @}
2569 */
2570
2571 #endif /* DMA1 || DMA2 */
2572
2573 /**
2574 * @}
2575 */
2576
2577 #ifdef __cplusplus
2578 }
2579 #endif
2580
2581 #endif /* __STM32G4xx_LL_DMA_H */
2582
2583 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/