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F1 and F3 HAL / LL libraries
[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Src / stm32f3xx_ll_adc.c
blob6dc3487394924a67e7c58b86b9b2ad26130a1ad9
1 /**
2 ******************************************************************************
3 * @file stm32f3xx_ll_adc.c
4 * @author MCD Application Team
5 * @brief ADC LL module driver
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
35 #if defined(USE_FULL_LL_DRIVER)
36
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f3xx_ll_adc.h"
39 #include "stm32f3xx_ll_bus.h"
40
41 #ifdef USE_FULL_ASSERT
42 #include "stm32_assert.h"
43 #else
44 #define assert_param(expr) ((void)0U)
45 #endif
46
47 /** @addtogroup STM32F3xx_LL_Driver
48 * @{
49 */
50
51 /* Note: Devices of STM32F3 serie embed 1 out of 2 different ADC IP. b */
52 /* - STM32F30x, STM32F31x, STM32F32x, STM32F33x, STM32F35x, STM32F39x: */
53 /* ADC IP 5Msamples/sec, from 1 to 4 ADC instances and other specific */
54 /* features (refer to reference manual). */
55 /* - STM32F37x: */
56 /* ADC IP 1Msamples/sec, 1 ADC instance */
57 /* This file contains the drivers of these ADC IP, located in 2 area */
58 /* delimited by compilation switches. */
59
60 #if defined(ADC5_V1_1)
61
62 #if defined (ADC1) || defined (ADC2) || defined (ADC3) || defined (ADC4)
63
64 /** @addtogroup ADC_LL ADC
65 * @{
66 */
67
68 /* Private types -------------------------------------------------------------*/
69 /* Private variables ---------------------------------------------------------*/
70 /* Private constants ---------------------------------------------------------*/
71 /** @addtogroup ADC_LL_Private_Constants
72 * @{
73 */
74
75 /* Definitions of ADC hardware constraints delays */
76 /* Note: Only ADC IP HW delays are defined in ADC LL driver driver, */
77 /* not timeout values: */
78 /* Timeout values for ADC operations are dependent to device clock */
79 /* configuration (system clock versus ADC clock), */
80 /* and therefore must be defined in user application. */
81 /* Refer to @ref ADC_LL_EC_HW_DELAYS for description of ADC timeout */
82 /* values definition. */
83 /* Note: ADC timeout values are defined here in CPU cycles to be independent */
84 /* of device clock setting. */
85 /* In user application, ADC timeout values should be defined with */
86 /* temporal values, in function of device clock settings. */
87 /* Highest ratio CPU clock frequency vs ADC clock frequency: */
88 /* - ADC clock from synchronous clock with AHB prescaler 512, */
89 /* APB prescaler 16, ADC prescaler 4. */
90 /* - ADC clock from asynchronous clock (PLL) with prescaler 1, */
91 /* with highest ratio CPU clock frequency vs HSI clock frequency: */
92 /* CPU clock frequency max 72MHz, PLL frequency 72MHz: ratio 1. */
93 /* Unit: CPU cycles. */
94 #define ADC_CLOCK_RATIO_VS_CPU_HIGHEST ((uint32_t) 512U * 16U * 4U)
95 #define ADC_TIMEOUT_DISABLE_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
96 #define ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES (ADC_CLOCK_RATIO_VS_CPU_HIGHEST * 1U)
97
98 /**
99 * @}
100 */
101
102 /* Private macros ------------------------------------------------------------*/
103
104 /** @addtogroup ADC_LL_Private_Macros
105 * @{
106 */
107
108 /* Check of parameters for configuration of ADC hierarchical scope: */
109 /* common to several ADC instances. */
110 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
111 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV1) \
112 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
113 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
114 || ((__CLOCK__) == LL_ADC_CLOCK_ASYNC_DIV1) \
115 )
116
117 /* Check of parameters for configuration of ADC hierarchical scope: */
118 /* ADC instance. */
119 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
120 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
121 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
122 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
123 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
124 )
125
126 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
127 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
128 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
129 )
130
131 #define IS_LL_ADC_LOW_POWER(__LOW_POWER__) \
132 ( ((__LOW_POWER__) == LL_ADC_LP_MODE_NONE) \
133 || ((__LOW_POWER__) == LL_ADC_LP_AUTOWAIT) \
134 )
135
136 /* Check of parameters for configuration of ADC hierarchical scope: */
137 /* ADC group regular */
138 #if defined(STM32F303xE) || defined(STM32F398xx)
139 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
140 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
141 ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
142 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
143 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
144 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
145 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
146 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
147 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
148 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
149 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
150 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
151 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
152 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
153 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
154 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
155 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
156 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
157 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
158 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC12) \
159 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC12) \
160 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC12) \
161 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH2_ADC12) \
162 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH3_ADC12) \
163 ) \
164 : \
165 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
166 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
167 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
168 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
169 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
170 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
171 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
172 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
173 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
174 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
175 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
176 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
177 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
178 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
179 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
180 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
181 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
182 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG0_ADC34) \
183 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_TRG02_ADC34) \
184 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM20_CH1_ADC34) \
185 ) \
186 )
187 #elif defined(STM32F303xC) || defined(STM32F358xx)
188 #define IS_LL_ADC_REG_TRIG_SOURCE(__ADC_INSTANCE__, __REG_TRIG_SOURCE__) \
189 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
190 ? ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
191 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1_ADC12) \
192 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2_ADC12) \
193 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
194 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2_ADC12) \
195 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO_ADC12) \
196 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4_ADC12) \
197 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11_ADC12) \
198 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO_ADC12) \
199 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
200 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
201 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
202 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO_ADC12) \
203 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
204 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO_ADC12) \
205 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
206 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4_ADC12) \
207 ) \
208 : \
209 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
210 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH1_ADC34) \
211 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH3_ADC34) \
212 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
213 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_CH1_ADC34) \
214 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO__ADC34) \
215 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE2_ADC34) \
216 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH1_ADC34) \
217 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO__ADC34) \
218 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO2) \
219 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
220 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
221 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO__ADC34) \
222 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
223 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM7_TRGO_ADC34) \
224 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
225 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH1_ADC34) \
226 ) \
227 )
228 #elif defined(STM32F303x8) || defined(STM32F328xx)
229 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
230 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
231 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
232 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
233 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
234 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
235 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
236 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
237 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
238 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
239 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
240 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
241 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
242 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
243 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
244 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
245 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
246 )
247 #elif defined(STM32F334x8)
248 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
249 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
250 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
251 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
252 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
253 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
254 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
255 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
256 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG1) \
257 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_HRTIM_TRG3) \
258 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
259 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
260 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
261 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
262 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
263 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
264 )
265 #elif defined(STM32F302xC) || defined(STM32F302xE)
266 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
267 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
268 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
269 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
270 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
271 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
272 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
273 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
274 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
275 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
276 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
277 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
278 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
279 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
280 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
281 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
282 )
283 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
284 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
285 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
286 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
287 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
288 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
289 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
290 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
291 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
292 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
293 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
294 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM15_TRGO) \
295 )
296 #endif
297
298 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
299 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
300 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
301 )
302
303 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
304 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
305 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
306 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
307 )
308
309 #define IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(__REG_OVR_DATA_BEHAVIOR__) \
310 ( ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_PRESERVED) \
311 || ((__REG_OVR_DATA_BEHAVIOR__) == LL_ADC_REG_OVR_DATA_OVERWRITTEN) \
312 )
313
314 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
315 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
316 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
317 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
318 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
319 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
320 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
321 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
322 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
323 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
324 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
325 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
326 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
327 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
328 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
329 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
330 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
331 )
332
333 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
334 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
335 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
336 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
337 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
338 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
339 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
340 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
341 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
342 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
343 )
344
345 /* Check of parameters for configuration of ADC hierarchical scope: */
346 /* ADC group injected */
347 #if defined(STM32F303xE) || defined(STM32F398xx)
348 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
349 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
350 ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
351 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
352 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
353 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
354 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
355 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
356 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
357 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
358 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
359 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
360 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
361 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
362 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
363 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
364 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
365 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
366 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
367 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO_ADC12) \
368 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRGO2_ADC12) \
369 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH4_ADC12) \
370 ) \
371 : \
372 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
373 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
374 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
375 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
376 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
377 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
378 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
379 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
380 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
381 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
382 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
383 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
384 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
385 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
386 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
387 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
388 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG_ADC34) \
389 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_TRG2_ADC34) \
390 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM20_CH2) \
391 ) \
392 )
393 #elif defined(STM32F303xC) || defined(STM32F358xx)
394 #define IS_LL_ADC_INJ_TRIG_SOURCE(__ADC_INSTANCE__, __INJ_TRIG_SOURCE__) \
395 ((((__ADC_INSTANCE__) == ADC1) || ((__ADC_INSTANCE__) == ADC2)) \
396 ? ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
397 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
398 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
399 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO_ADC12) \
400 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1_ADC12) \
401 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4_ADC12) \
402 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO_ADC12) \
403 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15_ADC12) \
404 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4_ADC12) \
405 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
406 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
407 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
408 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3_ADC12) \
409 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
410 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1_ADC12) \
411 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO_ADC12) \
412 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
413 ) \
414 : \
415 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
416 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
417 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
418 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH3_ADC34) \
419 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH2_ADC34) \
420 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4__ADC34) \
421 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_CH4_ADC34) \
422 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO__ADC34) \
423 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
424 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
425 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
426 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH3_ADC34) \
427 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
428 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO__ADC34) \
429 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM7_TRGO_ADC34) \
430 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
431 ) \
432 )
433
434 #elif defined(STM32F303x8) || defined(STM32F328xx)
435 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
436 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
437 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
438 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
439 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
440 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
441 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
442 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
443 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
444 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
445 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
446 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
447 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
448 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
449 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
450 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
451 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
452 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
453 )
454 #elif defined(STM32F334x8)
455 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
456 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
457 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
458 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
459 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
460 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
461 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
462 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
463 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
464 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG2) \
465 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_HRTIM_TRG4) \
466 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
467 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
468 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
469 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
470 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
471 )
472 #elif defined(STM32F302xC) || defined(STM32F302xE)
473 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
474 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
475 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
476 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
477 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
478 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
479 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
480 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
481 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
482 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
483 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
484 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_TRGO) \
485 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
486 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
487 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
488 )
489 #elif defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx)
490 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
491 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
492 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
493 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
494 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15) \
495 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
496 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
497 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM15_TRGO) \
498 )
499 #endif
500
501 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
502 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
503 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
504 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
505 )
506
507 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
508 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
509 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
510 )
511
512 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
513 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
514 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
515 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
516 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
517 )
518
519 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
520 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
521 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
522 )
523
524 #if defined(ADC_MULTIMODE_SUPPORT)
525 /* Check of parameters for configuration of ADC hierarchical scope: */
526 /* multimode. */
527 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
528 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
529 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
530 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
531 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
532 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
533 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
534 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
535 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
536 )
537
538 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
539 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
540 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES12_10B) \
541 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_RES8_6B) \
542 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES12_10B) \
543 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_RES8_6B) \
544 )
545
546 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
547 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE) \
548 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_2CYCLES) \
549 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_3CYCLES) \
550 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_4CYCLES) \
551 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
552 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
553 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
554 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
555 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
556 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
557 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
558 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
559 )
560
561 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
562 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
563 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
564 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
565 )
566
567 #endif /* ADC_MULTIMODE_SUPPORT */
568 /**
569 * @}
570 */
571
572
573 /* Private function prototypes -----------------------------------------------*/
574
575 /* Exported functions --------------------------------------------------------*/
576 /** @addtogroup ADC_LL_Exported_Functions
577 * @{
578 */
579
580 /** @addtogroup ADC_LL_EF_Init
581 * @{
582 */
583
584 /**
585 * @brief De-initialize registers of all ADC instances belonging to
586 * the same ADC common instance to their default reset values.
587 * @note This function is performing a hard reset, using high level
588 * clock source RCC ADC reset.
589 * Caution: On this STM32 serie, if several ADC instances are available
590 * on the selected device, RCC ADC reset will reset
591 * all ADC instances belonging to the common ADC instance.
592 * To de-initialize only 1 ADC instance, use
593 * function @ref LL_ADC_DeInit().
594 * @param ADCxy_COMMON ADC common instance
595 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
596 * @retval An ErrorStatus enumeration value:
597 * - SUCCESS: ADC common registers are de-initialized
598 * - ERROR: not applicable
599 */
600 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
601 {
602 /* Check the parameters */
603 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
604
605 /* Force reset of ADC clock (core clock) */
606 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
607 if(ADCxy_COMMON == ADC12_COMMON)
608 {
609 LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
610 }
611 else
612 {
613 LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC34);
614 }
615 #elif defined(ADC1) && defined(ADC2)
616 LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC12);
617 #elif defined(ADC1)
618 LL_AHB1_GRP1_ForceReset (LL_AHB1_GRP1_PERIPH_ADC1);
619 #endif
620
621 /* Release reset of ADC clock (core clock) */
622 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
623 if(ADCxy_COMMON == ADC12_COMMON)
624 {
625 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
626 }
627 else
628 {
629 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC34);
630 }
631 #elif defined(ADC1) && defined(ADC2)
632 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC12);
633 #elif defined(ADC1)
634 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_ADC1);
635 #endif
636
637 return SUCCESS;
638 }
639
640 /**
641 * @brief Initialize some features of ADC common parameters
642 * (all ADC instances belonging to the same ADC common instance)
643 * and multimode (for devices with several ADC instances available).
644 * @note The setting of ADC common parameters is conditioned to
645 * ADC instances state:
646 * All ADC instances belonging to the same ADC common instance
647 * must be disabled.
648 * @param ADCxy_COMMON ADC common instance
649 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
650 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
651 * @retval An ErrorStatus enumeration value:
652 * - SUCCESS: ADC common registers are initialized
653 * - ERROR: ADC common registers are not initialized
654 */
655 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
656 {
657 ErrorStatus status = SUCCESS;
658
659 /* Check the parameters */
660 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
661 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
662
663 #if defined(ADC_MULTIMODE_SUPPORT)
664 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
665 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
666 {
667 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
668 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
669 }
670 #endif /* ADC_MULTIMODE_SUPPORT */
671
672 /* Note: Hardware constraint (refer to description of functions */
673 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
674 /* On this STM32 serie, setting of these features is conditioned to */
675 /* ADC state: */
676 /* All ADC instances of the ADC common group must be disabled. */
677 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
678 {
679 /* Configuration of ADC hierarchical scope: */
680 /* - common to several ADC */
681 /* (all ADC instances belonging to the same ADC common instance) */
682 /* - Set ADC clock (conversion clock) */
683 /* - multimode (if several ADC instances available on the */
684 /* selected device) */
685 /* - Set ADC multimode configuration */
686 /* - Set ADC multimode DMA transfer */
687 /* - Set ADC multimode: delay between 2 sampling phases */
688 #if defined(ADC_MULTIMODE_SUPPORT)
689 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
690 {
691 MODIFY_REG(ADCxy_COMMON->CCR,
692 ADC_CCR_CKMODE
693 | ADC_CCR_DUAL
694 | ADC_CCR_MDMA
695 | ADC_CCR_DELAY
696 ,
697 ADC_CommonInitStruct->CommonClock
698 | ADC_CommonInitStruct->Multimode
699 | ADC_CommonInitStruct->MultiDMATransfer
700 | ADC_CommonInitStruct->MultiTwoSamplingDelay
701 );
702 }
703 else
704 {
705 MODIFY_REG(ADCxy_COMMON->CCR,
706 ADC_CCR_CKMODE
707 | ADC_CCR_DUAL
708 | ADC_CCR_MDMA
709 | ADC_CCR_DELAY
710 ,
711 ADC_CommonInitStruct->CommonClock
712 | LL_ADC_MULTI_INDEPENDENT
713 );
714 }
715 #else
716 LL_ADC_SetCommonClock(ADCxy_COMMON, ADC_CommonInitStruct->CommonClock);
717 #endif
718 }
719 else
720 {
721 /* Initialization error: One or several ADC instances belonging to */
722 /* the same ADC common instance are not disabled. */
723 status = ERROR;
724 }
725
726 return status;
727 }
728
729 /**
730 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
731 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
732 * whose fields will be set to default values.
733 * @retval None
734 */
735 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
736 {
737 /* Set ADC_CommonInitStruct fields to default values */
738 /* Set fields of ADC common */
739 /* (all ADC instances belonging to the same ADC common instance) */
740 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
741
742 #if defined(ADC_MULTIMODE_SUPPORT)
743 /* Set fields of ADC multimode */
744 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
745 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
746 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_1CYCLE;
747 #endif /* ADC_MULTIMODE_SUPPORT */
748 }
749
750 /**
751 * @brief De-initialize registers of the selected ADC instance
752 * to their default reset values.
753 * @note To reset all ADC instances quickly (perform a hard reset),
754 * use function @ref LL_ADC_CommonDeInit().
755 * @note If this functions returns error status, it means that ADC instance
756 * is in an unknown state.
757 * In this case, perform a hard reset using high level
758 * clock source RCC ADC reset.
759 * Caution: On this STM32 serie, if several ADC instances are available
760 * on the selected device, RCC ADC reset will reset
761 * all ADC instances belonging to the common ADC instance.
762 * Refer to function @ref LL_ADC_CommonDeInit().
763 * @param ADCx ADC instance
764 * @retval An ErrorStatus enumeration value:
765 * - SUCCESS: ADC registers are de-initialized
766 * - ERROR: ADC registers are not de-initialized
767 */
768 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
769 {
770 ErrorStatus status = SUCCESS;
771
772 __IO uint32_t timeout_cpu_cycles = 0U;
773
774 /* Check the parameters */
775 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
776
777 /* Disable ADC instance if not already disabled. */
778 if(LL_ADC_IsEnabled(ADCx) == 1U)
779 {
780 /* Set ADC group regular trigger source to SW start to ensure to not */
781 /* have an external trigger event occurring during the conversion stop */
782 /* ADC disable process. */
783 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
784
785 /* Stop potential ADC conversion on going on ADC group regular. */
786 if(LL_ADC_REG_IsConversionOngoing(ADCx) != 0U)
787 {
788 if(LL_ADC_REG_IsStopConversionOngoing(ADCx) == 0U)
789 {
790 LL_ADC_REG_StopConversion(ADCx);
791 }
792 }
793
794 /* Set ADC group injected trigger source to SW start to ensure to not */
795 /* have an external trigger event occurring during the conversion stop */
796 /* ADC disable process. */
797 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
798
799 /* Stop potential ADC conversion on going on ADC group injected. */
800 if(LL_ADC_INJ_IsConversionOngoing(ADCx) != 0U)
801 {
802 if(LL_ADC_INJ_IsStopConversionOngoing(ADCx) == 0U)
803 {
804 LL_ADC_INJ_StopConversion(ADCx);
805 }
806 }
807
808 /* Wait for ADC conversions are effectively stopped */
809 timeout_cpu_cycles = ADC_TIMEOUT_STOP_CONVERSION_CPU_CYCLES;
810 while (( LL_ADC_REG_IsStopConversionOngoing(ADCx)
811 | LL_ADC_INJ_IsStopConversionOngoing(ADCx)) == 1U)
812 {
813 if(timeout_cpu_cycles-- == 0U)
814 {
815 /* Time-out error */
816 status = ERROR;
817 }
818 }
819
820 /* Flush group injected contexts queue (register JSQR): */
821 /* Note: Bit JQM must be set to empty the contexts queue (otherwise */
822 /* contexts queue is maintained with the last active context). */
823 LL_ADC_INJ_SetQueueMode(ADCx, LL_ADC_INJ_QUEUE_2CONTEXTS_END_EMPTY);
824
825 /* Disable the ADC instance */
826 LL_ADC_Disable(ADCx);
827
828 /* Wait for ADC instance is effectively disabled */
829 timeout_cpu_cycles = ADC_TIMEOUT_DISABLE_CPU_CYCLES;
830 while (LL_ADC_IsDisableOngoing(ADCx) == 1U)
831 {
832 if(timeout_cpu_cycles-- == 0U)
833 {
834 /* Time-out error */
835 status = ERROR;
836 }
837 }
838 }
839
840 /* Check whether ADC state is compliant with expected state */
841 if(READ_BIT(ADCx->CR,
842 ( ADC_CR_JADSTP | ADC_CR_ADSTP | ADC_CR_JADSTART | ADC_CR_ADSTART
843 | ADC_CR_ADDIS | ADC_CR_ADEN )
844 )
845 == 0U)
846 {
847 /* ========== Reset ADC registers ========== */
848 /* Reset register IER */
849 CLEAR_BIT(ADCx->IER,
850 ( LL_ADC_IT_ADRDY
851 | LL_ADC_IT_EOC
852 | LL_ADC_IT_EOS
853 | LL_ADC_IT_OVR
854 | LL_ADC_IT_EOSMP
855 | LL_ADC_IT_JEOC
856 | LL_ADC_IT_JEOS
857 | LL_ADC_IT_JQOVF
858 | LL_ADC_IT_AWD1
859 | LL_ADC_IT_AWD2
860 | LL_ADC_IT_AWD3 )
861 );
862
863 /* Reset register ISR */
864 SET_BIT(ADCx->ISR,
865 ( LL_ADC_FLAG_ADRDY
866 | LL_ADC_FLAG_EOC
867 | LL_ADC_FLAG_EOS
868 | LL_ADC_FLAG_OVR
869 | LL_ADC_FLAG_EOSMP
870 | LL_ADC_FLAG_JEOC
871 | LL_ADC_FLAG_JEOS
872 | LL_ADC_FLAG_JQOVF
873 | LL_ADC_FLAG_AWD1
874 | LL_ADC_FLAG_AWD2
875 | LL_ADC_FLAG_AWD3 )
876 );
877
878 /* Reset register CR */
879 /* - Bits ADC_CR_JADSTP, ADC_CR_ADSTP, ADC_CR_JADSTART, ADC_CR_ADSTART, */
880 /* ADC_CR_ADCAL, ADC_CR_ADDIS, ADC_CR_ADEN are in */
881 /* access mode "read-set": no direct reset applicable. */
882 /* - Reset Calibration mode to default setting (single ended). */
883 /* - Disable ADC internal voltage regulator. */
884 /* Note: ADC internal voltage regulator disable is conditioned to */
885 /* ADC state disabled: already done above. */
886 /* Sequence to disable voltage regulator: */
887 /* 1. Set the intermediate state before moving the ADC voltage regulator */
888 /* to disable state. */
889 CLEAR_BIT(ADCx->CR, ADC_CR_ADVREGEN_1 | ADC_CR_ADVREGEN_0 | ADC_CR_ADCALDIF);
890 /* 2. Set ADVREGEN bits to 0x10 */
891 SET_BIT(ADCx->CR, ADC_CR_ADVREGEN_1);
892
893 /* Reset register CFGR */
894 CLEAR_BIT(ADCx->CFGR,
895 ( ADC_CFGR_AWD1CH | ADC_CFGR_JAUTO | ADC_CFGR_JAWD1EN
896 | ADC_CFGR_AWD1EN | ADC_CFGR_AWD1SGL | ADC_CFGR_JQM
897 | ADC_CFGR_JDISCEN | ADC_CFGR_DISCNUM | ADC_CFGR_DISCEN
898 | ADC_CFGR_AUTDLY | ADC_CFGR_CONT | ADC_CFGR_OVRMOD
899 | ADC_CFGR_EXTEN | ADC_CFGR_EXTSEL | ADC_CFGR_ALIGN
900 | ADC_CFGR_RES | ADC_CFGR_DMACFG | ADC_CFGR_DMAEN )
901 );
902
903 /* Reset register SMPR1 */
904 CLEAR_BIT(ADCx->SMPR1,
905 ( ADC_SMPR1_SMP9 | ADC_SMPR1_SMP8 | ADC_SMPR1_SMP7
906 | ADC_SMPR1_SMP6 | ADC_SMPR1_SMP5 | ADC_SMPR1_SMP4
907 | ADC_SMPR1_SMP3 | ADC_SMPR1_SMP2 | ADC_SMPR1_SMP1)
908 );
909
910 /* Reset register SMPR2 */
911 CLEAR_BIT(ADCx->SMPR2,
912 ( ADC_SMPR2_SMP18 | ADC_SMPR2_SMP17 | ADC_SMPR2_SMP16
913 | ADC_SMPR2_SMP15 | ADC_SMPR2_SMP14 | ADC_SMPR2_SMP13
914 | ADC_SMPR2_SMP12 | ADC_SMPR2_SMP11 | ADC_SMPR2_SMP10)
915 );
916
917 /* Reset register TR1 */
918 MODIFY_REG(ADCx->TR1, ADC_TR1_HT1 | ADC_TR1_LT1, ADC_TR1_HT1);
919
920 /* Reset register TR2 */
921 MODIFY_REG(ADCx->TR2, ADC_TR2_HT2 | ADC_TR2_LT2, ADC_TR2_HT2);
922
923 /* Reset register TR3 */
924 MODIFY_REG(ADCx->TR3, ADC_TR3_HT3 | ADC_TR3_LT3, ADC_TR3_HT3);
925
926 /* Reset register SQR1 */
927 CLEAR_BIT(ADCx->SQR1,
928 ( ADC_SQR1_SQ4 | ADC_SQR1_SQ3 | ADC_SQR1_SQ2
929 | ADC_SQR1_SQ1 | ADC_SQR1_L)
930 );
931
932 /* Reset register SQR2 */
933 CLEAR_BIT(ADCx->SQR2,
934 ( ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7
935 | ADC_SQR2_SQ6 | ADC_SQR2_SQ5)
936 );
937
938 /* Reset register SQR3 */
939 CLEAR_BIT(ADCx->SQR3,
940 ( ADC_SQR3_SQ14 | ADC_SQR3_SQ13 | ADC_SQR3_SQ12
941 | ADC_SQR3_SQ11 | ADC_SQR3_SQ10)
942 );
943
944 /* Reset register SQR4 */
945 CLEAR_BIT(ADCx->SQR4, ADC_SQR4_SQ16 | ADC_SQR4_SQ15);
946
947 /* Reset register JSQR */
948 CLEAR_BIT(ADCx->JSQR,
949 ( ADC_JSQR_JL
950 | ADC_JSQR_JEXTSEL | ADC_JSQR_JEXTEN
951 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
952 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
953 );
954
955 /* Flush ADC group injected contexts queue */
956 SET_BIT(ADCx->CFGR, ADC_CFGR_JQM);
957 CLEAR_BIT(ADCx->CFGR, ADC_CFGR_JQM);
958 /* Reset register ISR bit JQOVF (set by previous operation on JSQR) */
959 SET_BIT(ADCx->ISR, LL_ADC_FLAG_JQOVF);
960
961 /* Reset register DR */
962 /* Note: bits in access mode read only, no direct reset applicable */
963
964 /* Reset register OFR1 */
965 CLEAR_BIT(ADCx->OFR1, ADC_OFR1_OFFSET1_EN | ADC_OFR1_OFFSET1_CH | ADC_OFR1_OFFSET1);
966 /* Reset register OFR2 */
967 CLEAR_BIT(ADCx->OFR2, ADC_OFR2_OFFSET2_EN | ADC_OFR2_OFFSET2_CH | ADC_OFR2_OFFSET2);
968 /* Reset register OFR3 */
969 CLEAR_BIT(ADCx->OFR3, ADC_OFR3_OFFSET3_EN | ADC_OFR3_OFFSET3_CH | ADC_OFR3_OFFSET3);
970 /* Reset register OFR4 */
971 CLEAR_BIT(ADCx->OFR4, ADC_OFR4_OFFSET4_EN | ADC_OFR4_OFFSET4_CH | ADC_OFR4_OFFSET4);
972
973 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
974 /* Note: bits in access mode read only, no direct reset applicable */
975
976 /* Reset register AWD2CR */
977 CLEAR_BIT(ADCx->AWD2CR, ADC_AWD2CR_AWD2CH);
978
979 /* Reset register AWD3CR */
980 CLEAR_BIT(ADCx->AWD3CR, ADC_AWD3CR_AWD3CH);
981
982 /* Reset register DIFSEL */
983 CLEAR_BIT(ADCx->DIFSEL, ADC_DIFSEL_DIFSEL);
984
985 /* Reset register CALFACT */
986 CLEAR_BIT(ADCx->CALFACT, ADC_CALFACT_CALFACT_D | ADC_CALFACT_CALFACT_S);
987 }
988 else
989 {
990 /* ADC instance is in an unknown state */
991 /* Need to performing a hard reset of ADC instance, using high level */
992 /* clock source RCC ADC reset. */
993 /* Caution: On this STM32 serie, if several ADC instances are available */
994 /* on the selected device, RCC ADC reset will reset */
995 /* all ADC instances belonging to the common ADC instance. */
996 /* Caution: On this STM32 serie, if several ADC instances are available */
997 /* on the selected device, RCC ADC reset will reset */
998 /* all ADC instances belonging to the common ADC instance. */
999 status = ERROR;
1000 }
1001
1002 return status;
1003 }
1004
1005 /**
1006 * @brief Initialize some features of ADC instance.
1007 * @note These parameters have an impact on ADC scope: ADC instance.
1008 * Affects both group regular and group injected (availability
1009 * of ADC group injected depends on STM32 families).
1010 * Refer to corresponding unitary functions into
1011 * @ref ADC_LL_EF_Configuration_ADC_Instance .
1012 * @note The setting of these parameters by function @ref LL_ADC_Init()
1013 * is conditioned to ADC state:
1014 * ADC instance must be disabled.
1015 * This condition is applied to all ADC features, for efficiency
1016 * and compatibility over all STM32 families. However, the different
1017 * features can be set under different ADC state conditions
1018 * (setting possible with ADC enabled without conversion on going,
1019 * ADC enabled with conversion on going, ...)
1020 * Each feature can be updated afterwards with a unitary function
1021 * and potentially with ADC in a different state than disabled,
1022 * refer to description of each function for setting
1023 * conditioned to ADC state.
1024 * @note After using this function, some other features must be configured
1025 * using LL unitary functions.
1026 * The minimum configuration remaining to be done is:
1027 * - Set ADC group regular or group injected sequencer:
1028 * map channel on the selected sequencer rank.
1029 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1030 * - Set ADC channel sampling time
1031 * Refer to function LL_ADC_SetChannelSamplingTime();
1032 * @param ADCx ADC instance
1033 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1034 * @retval An ErrorStatus enumeration value:
1035 * - SUCCESS: ADC registers are initialized
1036 * - ERROR: ADC registers are not initialized
1037 */
1038 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
1039 {
1040 ErrorStatus status = SUCCESS;
1041
1042 /* Check the parameters */
1043 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1044
1045 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
1046 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
1047 assert_param(IS_LL_ADC_LOW_POWER(ADC_InitStruct->LowPowerMode));
1048
1049 /* Note: Hardware constraint (refer to description of this function): */
1050 /* ADC instance must be disabled. */
1051 if(LL_ADC_IsEnabled(ADCx) == 0U)
1052 {
1053 /* Configuration of ADC hierarchical scope: */
1054 /* - ADC instance */
1055 /* - Set ADC data resolution */
1056 /* - Set ADC conversion data alignment */
1057 /* - Set ADC low power mode */
1058 MODIFY_REG(ADCx->CFGR,
1059 ADC_CFGR_RES
1060 | ADC_CFGR_ALIGN
1061 | ADC_CFGR_AUTDLY
1062 ,
1063 ADC_InitStruct->Resolution
1064 | ADC_InitStruct->DataAlignment
1065 | ADC_InitStruct->LowPowerMode
1066 );
1067
1068 }
1069 else
1070 {
1071 /* Initialization error: ADC instance is not disabled. */
1072 status = ERROR;
1073 }
1074 return status;
1075 }
1076
1077 /**
1078 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
1079 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
1080 * whose fields will be set to default values.
1081 * @retval None
1082 */
1083 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
1084 {
1085 /* Set ADC_InitStruct fields to default values */
1086 /* Set fields of ADC instance */
1087 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
1088 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
1089 ADC_InitStruct->LowPowerMode = LL_ADC_LP_MODE_NONE;
1090
1091 }
1092
1093 /**
1094 * @brief Initialize some features of ADC group regular.
1095 * @note These parameters have an impact on ADC scope: ADC group regular.
1096 * Refer to corresponding unitary functions into
1097 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1098 * (functions with prefix "REG").
1099 * @note The setting of these parameters by function @ref LL_ADC_Init()
1100 * is conditioned to ADC state:
1101 * ADC instance must be disabled.
1102 * This condition is applied to all ADC features, for efficiency
1103 * and compatibility over all STM32 families. However, the different
1104 * features can be set under different ADC state conditions
1105 * (setting possible with ADC enabled without conversion on going,
1106 * ADC enabled with conversion on going, ...)
1107 * Each feature can be updated afterwards with a unitary function
1108 * and potentially with ADC in a different state than disabled,
1109 * refer to description of each function for setting
1110 * conditioned to ADC state.
1111 * @note After using this function, other features must be configured
1112 * using LL unitary functions.
1113 * The minimum configuration remaining to be done is:
1114 * - Set ADC group regular or group injected sequencer:
1115 * map channel on the selected sequencer rank.
1116 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1117 * - Set ADC channel sampling time
1118 * Refer to function LL_ADC_SetChannelSamplingTime();
1119 * @param ADCx ADC instance
1120 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1121 * @retval An ErrorStatus enumeration value:
1122 * - SUCCESS: ADC registers are initialized
1123 * - ERROR: ADC registers are not initialized
1124 */
1125 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1126 {
1127 ErrorStatus status = SUCCESS;
1128
1129 /* Check the parameters */
1130 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1131 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
1132 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADCx, ADC_REG_InitStruct->TriggerSource));
1133 #else
1134 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
1135 #endif
1136 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
1137 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1138 {
1139 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
1140 }
1141 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
1142 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
1143 assert_param(IS_LL_ADC_REG_OVR_DATA_BEHAVIOR(ADC_REG_InitStruct->Overrun));
1144
1145 /* Note: Hardware constraint (refer to description of this function): */
1146 /* ADC instance must be disabled. */
1147 if(LL_ADC_IsEnabled(ADCx) == 0U)
1148 {
1149 /* Configuration of ADC hierarchical scope: */
1150 /* - ADC group regular */
1151 /* - Set ADC group regular trigger source */
1152 /* - Set ADC group regular sequencer length */
1153 /* - Set ADC group regular sequencer discontinuous mode */
1154 /* - Set ADC group regular continuous mode */
1155 /* - Set ADC group regular conversion data transfer: no transfer or */
1156 /* transfer by DMA, and DMA requests mode */
1157 /* - Set ADC group regular overrun behavior */
1158 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
1159 /* setting of trigger source to SW start. */
1160 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1161 {
1162 MODIFY_REG(ADCx->CFGR,
1163 ADC_CFGR_EXTSEL
1164 | ADC_CFGR_EXTEN
1165 | ADC_CFGR_DISCEN
1166 | ADC_CFGR_DISCNUM
1167 | ADC_CFGR_CONT
1168 | ADC_CFGR_DMAEN
1169 | ADC_CFGR_DMACFG
1170 | ADC_CFGR_OVRMOD
1171 ,
1172 ADC_REG_InitStruct->TriggerSource
1173 | ADC_REG_InitStruct->SequencerDiscont
1174 | ADC_REG_InitStruct->ContinuousMode
1175 | ADC_REG_InitStruct->DMATransfer
1176 | ADC_REG_InitStruct->Overrun
1177 );
1178 }
1179 else
1180 {
1181 MODIFY_REG(ADCx->CFGR,
1182 ADC_CFGR_EXTSEL
1183 | ADC_CFGR_EXTEN
1184 | ADC_CFGR_DISCEN
1185 | ADC_CFGR_DISCNUM
1186 | ADC_CFGR_CONT
1187 | ADC_CFGR_DMAEN
1188 | ADC_CFGR_DMACFG
1189 | ADC_CFGR_OVRMOD
1190 ,
1191 ADC_REG_InitStruct->TriggerSource
1192 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1193 | ADC_REG_InitStruct->ContinuousMode
1194 | ADC_REG_InitStruct->DMATransfer
1195 | ADC_REG_InitStruct->Overrun
1196 );
1197 }
1198
1199 /* Set ADC group regular sequencer length and scan direction */
1200 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1201 }
1202 else
1203 {
1204 /* Initialization error: ADC instance is not disabled. */
1205 status = ERROR;
1206 }
1207 return status;
1208 }
1209
1210 /**
1211 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1212 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1213 * whose fields will be set to default values.
1214 * @retval None
1215 */
1216 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1217 {
1218 /* Set ADC_REG_InitStruct fields to default values */
1219 /* Set fields of ADC group regular */
1220 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
1221 /* setting of trigger source to SW start. */
1222 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1223 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1224 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1225 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1226 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
1227 ADC_REG_InitStruct->Overrun = LL_ADC_REG_OVR_DATA_OVERWRITTEN;
1228 }
1229
1230 /**
1231 * @brief Initialize some features of ADC group injected.
1232 * @note These parameters have an impact on ADC scope: ADC group injected.
1233 * Refer to corresponding unitary functions into
1234 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1235 * (functions with prefix "INJ").
1236 * @note The setting of these parameters by function @ref LL_ADC_Init()
1237 * is conditioned to ADC state:
1238 * ADC instance must be disabled.
1239 * This condition is applied to all ADC features, for efficiency
1240 * and compatibility over all STM32 families. However, the different
1241 * features can be set under different ADC state conditions
1242 * (setting possible with ADC enabled without conversion on going,
1243 * ADC enabled with conversion on going, ...)
1244 * Each feature can be updated afterwards with a unitary function
1245 * and potentially with ADC in a different state than disabled,
1246 * refer to description of each function for setting
1247 * conditioned to ADC state.
1248 * @note After using this function, other features must be configured
1249 * using LL unitary functions.
1250 * The minimum configuration remaining to be done is:
1251 * - Set ADC group injected sequencer:
1252 * map channel on the selected sequencer rank.
1253 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1254 * - Set ADC channel sampling time
1255 * Refer to function LL_ADC_SetChannelSamplingTime();
1256 * @note Caution to ADC group injected contexts queue: On this STM32 serie,
1257 * using successively several times this function will appear has
1258 * having no effect.
1259 * This is due to ADC group injected contexts queue (this feature
1260 * cannot be disabled on this STM32 serie).
1261 * To set several features of ADC group injected, use
1262 * function @ref LL_ADC_INJ_ConfigQueueContext().
1263 * @param ADCx ADC instance
1264 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1265 * @retval An ErrorStatus enumeration value:
1266 * - SUCCESS: ADC registers are initialized
1267 * - ERROR: ADC registers are not initialized
1268 */
1269 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1270 {
1271 ErrorStatus status = SUCCESS;
1272
1273 /* Check the parameters */
1274 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1275 #if defined(ADC1) && defined(ADC2) && defined(ADC3) && defined(ADC4)
1276 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADCx, ADC_INJ_InitStruct->TriggerSource));
1277 #else
1278 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
1279 #endif
1280 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1281 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1282 {
1283 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1284 }
1285 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1286
1287 /* Note: Hardware constraint (refer to description of this function): */
1288 /* ADC instance must be disabled. */
1289 if(LL_ADC_IsEnabled(ADCx) == 0U)
1290 {
1291 /* Configuration of ADC hierarchical scope: */
1292 /* - ADC group injected */
1293 /* - Set ADC group injected trigger source */
1294 /* - Set ADC group injected sequencer length */
1295 /* - Set ADC group injected sequencer discontinuous mode */
1296 /* - Set ADC group injected conversion trigger: independent or */
1297 /* from ADC group regular */
1298 /* Note: On this STM32 serie, ADC trigger edge is set to value 0x0 by */
1299 /* setting of trigger source to SW start. */
1300 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1301 {
1302 MODIFY_REG(ADCx->CFGR,
1303 ADC_CFGR_JDISCEN
1304 | ADC_CFGR_JAUTO
1305 ,
1306 ADC_INJ_InitStruct->SequencerDiscont
1307 | ADC_INJ_InitStruct->TrigAuto
1308 );
1309 }
1310 else
1311 {
1312 MODIFY_REG(ADCx->CFGR,
1313 ADC_CFGR_JDISCEN
1314 | ADC_CFGR_JAUTO
1315 ,
1316 LL_ADC_REG_SEQ_DISCONT_DISABLE
1317 | ADC_INJ_InitStruct->TrigAuto
1318 );
1319 }
1320
1321 MODIFY_REG(ADCx->JSQR,
1322 ADC_JSQR_JEXTSEL
1323 | ADC_JSQR_JEXTEN
1324 | ADC_JSQR_JL
1325 ,
1326 ADC_INJ_InitStruct->TriggerSource
1327 | ADC_INJ_InitStruct->SequencerLength
1328 );
1329 }
1330 else
1331 {
1332 /* Initialization error: ADC instance is not disabled. */
1333 status = ERROR;
1334 }
1335 return status;
1336 }
1337
1338 /**
1339 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1340 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1341 * whose fields will be set to default values.
1342 * @retval None
1343 */
1344 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1345 {
1346 /* Set ADC_INJ_InitStruct fields to default values */
1347 /* Set fields of ADC group injected */
1348 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1349 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1350 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1351 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1352 }
1353
1354 /**
1355 * @}
1356 */
1357
1358 /**
1359 * @}
1360 */
1361
1362 /**
1363 * @}
1364 */
1365
1366 #endif /* ADC1 || ADC2 || ADC3 || ADC4 */
1367
1368
1369 #endif /* STM32F301x8 || STM32F302x8 || STM32F302xC || STM32F302xE || STM32F303x8 || STM32F303xC || STM32F303xE || STM32F318xx || STM32F328xx || STM32F334x8 || STM32F358xx || STM32F398xx */
1370
1371 #if defined (ADC1_V2_5)
1372
1373 #if defined (ADC1)
1374
1375 /** @addtogroup ADC_LL ADC
1376 * @{
1377 */
1378
1379 /* Private types -------------------------------------------------------------*/
1380 /* Private variables ---------------------------------------------------------*/
1381 /* Private constants ---------------------------------------------------------*/
1382 /* Private macros ------------------------------------------------------------*/
1383
1384 /** @addtogroup ADC_LL_Private_Macros
1385 * @{
1386 */
1387
1388 /* Check of parameters for configuration of ADC hierarchical scope: */
1389 /* common to several ADC instances. */
1390 /* Check of parameters for configuration of ADC hierarchical scope: */
1391 /* ADC instance. */
1392 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
1393 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
1394 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) )
1395
1396 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
1397 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
1398 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) )
1399
1400 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
1401 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
1402 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) )
1403
1404 /* Check of parameters for configuration of ADC hierarchical scope: */
1405 /* ADC group regular */
1406 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
1407 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
1408 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
1409 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_TRGO) \
1410 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH2) \
1411 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_TRGO) \
1412 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH3) \
1413 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM19_CH4) \
1414 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11))
1415
1416 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
1417 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
1418 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS))
1419
1420 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
1421 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
1422 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED))
1423
1424 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
1425 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
1426 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
1427 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
1428 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
1429 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
1430 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
1431 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
1432 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
1433 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
1434 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
1435 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
1436 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
1437 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
1438 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
1439 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
1440 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS))
1441
1442 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
1443 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
1444 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
1445 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
1446 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
1447 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
1448 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
1449 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
1450 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
1451 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) )
1452
1453 /* Check of parameters for configuration of ADC hierarchical scope: */
1454 /* ADC group injected */
1455 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
1456 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
1457 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
1458 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
1459 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
1460 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
1461 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH1) \
1462 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM19_CH2) \
1463 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_EXTI_LINE15))
1464
1465 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
1466 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
1467 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR))
1468
1469 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
1470 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
1471 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
1472 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
1473 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS))
1474
1475 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
1476 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
1477 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) )
1478
1479 /**
1480 * @}
1481 */
1482
1483
1484 /* Private function prototypes -----------------------------------------------*/
1485
1486 /* Exported functions --------------------------------------------------------*/
1487 /** @addtogroup ADC_LL_Exported_Functions
1488 * @{
1489 */
1490
1491 /** @addtogroup ADC_LL_EF_Init
1492 * @{
1493 */
1494
1495 /**
1496 * @brief De-initialize registers of all ADC instances belonging to
1497 * the same ADC common instance to their default reset values.
1498 * @param ADCxy_COMMON ADC common instance
1499 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
1500 * @retval An ErrorStatus enumeration value:
1501 * - SUCCESS: ADC common registers are de-initialized
1502 * - ERROR: not applicable
1503 */
1504 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
1505 {
1506 /* Check the parameters */
1507 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
1508
1509 /* Force reset of ADC clock (core clock) */
1510 LL_APB2_GRP1_ForceReset (LL_APB2_GRP1_PERIPH_ADC1);
1511
1512 /* Release reset of ADC clock (core clock) */
1513 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC1);
1514
1515 return SUCCESS;
1516 }
1517
1518 /**
1519 * @brief De-initialize registers of the selected ADC instance
1520 * to their default reset values.
1521 * @note To reset all ADC instances quickly (perform a hard reset),
1522 * use function @ref LL_ADC_CommonDeInit().
1523 * @param ADCx ADC instance
1524 * @retval An ErrorStatus enumeration value:
1525 * - SUCCESS: ADC registers are de-initialized
1526 * - ERROR: ADC registers are not de-initialized
1527 */
1528 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
1529 {
1530 ErrorStatus status = SUCCESS;
1531
1532 /* Check the parameters */
1533 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1534
1535 /* Disable ADC instance if not already disabled. */
1536 if(LL_ADC_IsEnabled(ADCx) == 1U)
1537 {
1538 /* Set ADC group regular trigger source to SW start to ensure to not */
1539 /* have an external trigger event occurring during the conversion stop */
1540 /* ADC disable process. */
1541 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
1542
1543 /* Set ADC group injected trigger source to SW start to ensure to not */
1544 /* have an external trigger event occurring during the conversion stop */
1545 /* ADC disable process. */
1546 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
1547
1548 /* Disable the ADC instance */
1549 LL_ADC_Disable(ADCx);
1550 }
1551
1552 /* Check whether ADC state is compliant with expected state */
1553 /* (hardware requirements of bits state to reset registers below) */
1554 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
1555 {
1556 /* ========== Reset ADC registers ========== */
1557 /* Reset register SR */
1558 CLEAR_BIT(ADCx->SR,
1559 ( LL_ADC_FLAG_STRT
1560 | LL_ADC_FLAG_JSTRT
1561 | LL_ADC_FLAG_EOS
1562 | LL_ADC_FLAG_JEOS
1563 | LL_ADC_FLAG_AWD1 )
1564 );
1565
1566 /* Reset register CR1 */
1567 CLEAR_BIT(ADCx->CR1,
1568 ( ADC_CR1_AWDEN | ADC_CR1_JAWDEN
1569 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
1570 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
1571 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
1572 | ADC_CR1_AWDCH )
1573 );
1574
1575 /* Reset register CR2 */
1576 CLEAR_BIT(ADCx->CR2,
1577 ( ADC_CR2_TSVREFE
1578 | ADC_CR2_SWSTART | ADC_CR2_EXTTRIG | ADC_CR2_EXTSEL
1579 | ADC_CR2_JSWSTART | ADC_CR2_JEXTTRIG | ADC_CR2_JEXTSEL
1580 | ADC_CR2_ALIGN | ADC_CR2_DMA
1581 | ADC_CR2_RSTCAL | ADC_CR2_CAL
1582 | ADC_CR2_CONT | ADC_CR2_ADON )
1583 );
1584
1585 /* Reset register SMPR1 */
1586 CLEAR_BIT(ADCx->SMPR1,
1587 ( ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
1588 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
1589 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
1590 );
1591
1592 /* Reset register SMPR2 */
1593 CLEAR_BIT(ADCx->SMPR2,
1594 ( ADC_SMPR2_SMP9
1595 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
1596 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
1597 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
1598 );
1599
1600 /* Reset register JOFR1 */
1601 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
1602 /* Reset register JOFR2 */
1603 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
1604 /* Reset register JOFR3 */
1605 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
1606 /* Reset register JOFR4 */
1607 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
1608
1609 /* Reset register HTR */
1610 SET_BIT(ADCx->HTR, ADC_HTR_HT);
1611 /* Reset register LTR */
1612 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
1613
1614 /* Reset register SQR1 */
1615 CLEAR_BIT(ADCx->SQR1,
1616 ( ADC_SQR1_L
1617 | ADC_SQR1_SQ16
1618 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
1619 );
1620
1621 /* Reset register SQR2 */
1622 CLEAR_BIT(ADCx->SQR2,
1623 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
1624 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
1625 );
1626
1627
1628 /* Reset register JSQR */
1629 CLEAR_BIT(ADCx->JSQR,
1630 ( ADC_JSQR_JL
1631 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
1632 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
1633 );
1634
1635 /* Reset register DR */
1636 /* bits in access mode read only, no direct reset applicable */
1637
1638 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
1639 /* bits in access mode read only, no direct reset applicable */
1640
1641 }
1642
1643 return status;
1644 }
1645
1646 /**
1647 * @brief Initialize some features of ADC instance.
1648 * @note These parameters have an impact on ADC scope: ADC instance.
1649 * Affects both group regular and group injected (availability
1650 * of ADC group injected depends on STM32 families).
1651 * Refer to corresponding unitary functions into
1652 * @ref ADC_LL_EF_Configuration_ADC_Instance .
1653 * @note The setting of these parameters by function @ref LL_ADC_Init()
1654 * is conditioned to ADC state:
1655 * ADC instance must be disabled.
1656 * This condition is applied to all ADC features, for efficiency
1657 * and compatibility over all STM32 families. However, the different
1658 * features can be set under different ADC state conditions
1659 * (setting possible with ADC enabled without conversion on going,
1660 * ADC enabled with conversion on going, ...)
1661 * Each feature can be updated afterwards with a unitary function
1662 * and potentially with ADC in a different state than disabled,
1663 * refer to description of each function for setting
1664 * conditioned to ADC state.
1665 * @note After using this function, some other features must be configured
1666 * using LL unitary functions.
1667 * The minimum configuration remaining to be done is:
1668 * - Set ADC group regular or group injected sequencer:
1669 * map channel on the selected sequencer rank.
1670 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1671 * - Set ADC channel sampling time
1672 * Refer to function LL_ADC_SetChannelSamplingTime();
1673 * @param ADCx ADC instance
1674 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1675 * @retval An ErrorStatus enumeration value:
1676 * - SUCCESS: ADC registers are initialized
1677 * - ERROR: ADC registers are not initialized
1678 */
1679 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
1680 {
1681 ErrorStatus status = SUCCESS;
1682
1683 /* Check the parameters */
1684 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1685
1686 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
1687 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
1688
1689 /* Note: Hardware constraint (refer to description of this function): */
1690 /* ADC instance must be disabled. */
1691 if(LL_ADC_IsEnabled(ADCx) == 0U)
1692 {
1693 /* Configuration of ADC hierarchical scope: */
1694 /* - ADC instance */
1695 /* - Set ADC conversion data alignment */
1696 MODIFY_REG(ADCx->CR1,
1697 ADC_CR1_SCAN
1698 ,
1699 ADC_InitStruct->SequencersScanMode
1700 );
1701
1702 MODIFY_REG(ADCx->CR2,
1703 ADC_CR2_ALIGN
1704 ,
1705 ADC_InitStruct->DataAlignment
1706 );
1707
1708 }
1709 else
1710 {
1711 /* Initialization error: ADC instance is not disabled. */
1712 status = ERROR;
1713 }
1714 return status;
1715 }
1716
1717 /**
1718 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
1719 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
1720 * whose fields will be set to default values.
1721 * @retval None
1722 */
1723 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
1724 {
1725 /* Set ADC_InitStruct fields to default values */
1726 /* Set fields of ADC instance */
1727 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
1728
1729 /* Enable scan mode to have a generic behavior with ADC of other */
1730 /* STM32 families, without this setting available: */
1731 /* ADC group regular sequencer and ADC group injected sequencer depend */
1732 /* only of their own configuration. */
1733 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
1734
1735 }
1736
1737 /**
1738 * @brief Initialize some features of ADC group regular.
1739 * @note These parameters have an impact on ADC scope: ADC group regular.
1740 * Refer to corresponding unitary functions into
1741 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1742 * (functions with prefix "REG").
1743 * @note The setting of these parameters by function @ref LL_ADC_Init()
1744 * is conditioned to ADC state:
1745 * ADC instance must be disabled.
1746 * This condition is applied to all ADC features, for efficiency
1747 * and compatibility over all STM32 families. However, the different
1748 * features can be set under different ADC state conditions
1749 * (setting possible with ADC enabled without conversion on going,
1750 * ADC enabled with conversion on going, ...)
1751 * Each feature can be updated afterwards with a unitary function
1752 * and potentially with ADC in a different state than disabled,
1753 * refer to description of each function for setting
1754 * conditioned to ADC state.
1755 * @note After using this function, other features must be configured
1756 * using LL unitary functions.
1757 * The minimum configuration remaining to be done is:
1758 * - Set ADC group regular or group injected sequencer:
1759 * map channel on the selected sequencer rank.
1760 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
1761 * - Set ADC channel sampling time
1762 * Refer to function LL_ADC_SetChannelSamplingTime();
1763 * @param ADCx ADC instance
1764 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1765 * @retval An ErrorStatus enumeration value:
1766 * - SUCCESS: ADC registers are initialized
1767 * - ERROR: ADC registers are not initialized
1768 */
1769 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1770 {
1771 ErrorStatus status = SUCCESS;
1772
1773 /* Check the parameters */
1774 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1775 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
1776 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
1777 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1778 {
1779 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
1780 }
1781 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
1782 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
1783
1784 /* Note: Hardware constraint (refer to description of this function): */
1785 /* ADC instance must be disabled. */
1786 if(LL_ADC_IsEnabled(ADCx) == 0U)
1787 {
1788 /* Configuration of ADC hierarchical scope: */
1789 /* - ADC group regular */
1790 /* - Set ADC group regular trigger source */
1791 /* - Set ADC group regular sequencer length */
1792 /* - Set ADC group regular sequencer discontinuous mode */
1793 /* - Set ADC group regular continuous mode */
1794 /* - Set ADC group regular conversion data transfer: no transfer or */
1795 /* transfer by DMA, and DMA requests mode */
1796 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
1797 /* ADC conversion. */
1798 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
1799 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1800 {
1801 MODIFY_REG(ADCx->CR1,
1802 ADC_CR1_DISCEN
1803 | ADC_CR1_DISCNUM
1804 ,
1805 ADC_REG_InitStruct->SequencerLength
1806 | ADC_REG_InitStruct->SequencerDiscont
1807 );
1808 }
1809 else
1810 {
1811 MODIFY_REG(ADCx->CR1,
1812 ADC_CR1_DISCEN
1813 | ADC_CR1_DISCNUM
1814 ,
1815 ADC_REG_InitStruct->SequencerLength
1816 | LL_ADC_REG_SEQ_DISCONT_DISABLE
1817 );
1818 }
1819
1820 MODIFY_REG(ADCx->CR2,
1821 ADC_CR2_EXTSEL
1822 | ADC_CR2_CONT
1823 | ADC_CR2_DMA
1824 ,
1825 ADC_REG_InitStruct->TriggerSource
1826 | ADC_REG_InitStruct->ContinuousMode
1827 | ADC_REG_InitStruct->DMATransfer
1828 );
1829
1830 /* Set ADC group regular sequencer length and scan direction */
1831 /* Note: Hardware constraint (refer to description of this function): */
1832 /* Note: If ADC instance feature scan mode is disabled */
1833 /* (refer to ADC instance initialization structure */
1834 /* parameter @ref SequencersScanMode */
1835 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
1836 /* this parameter is discarded. */
1837 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
1838 }
1839 else
1840 {
1841 /* Initialization error: ADC instance is not disabled. */
1842 status = ERROR;
1843 }
1844 return status;
1845 }
1846
1847 /**
1848 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
1849 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
1850 * whose fields will be set to default values.
1851 * @retval None
1852 */
1853 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
1854 {
1855 /* Set ADC_REG_InitStruct fields to default values */
1856 /* Set fields of ADC group regular */
1857 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
1858 /* ADC conversion. */
1859 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
1860 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
1861 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
1862 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
1863 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
1864 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
1865 }
1866
1867 /**
1868 * @brief Initialize some features of ADC group injected.
1869 * @note These parameters have an impact on ADC scope: ADC group injected.
1870 * Refer to corresponding unitary functions into
1871 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
1872 * (functions with prefix "INJ").
1873 * @note The setting of these parameters by function @ref LL_ADC_Init()
1874 * is conditioned to ADC state:
1875 * ADC instance must be disabled.
1876 * This condition is applied to all ADC features, for efficiency
1877 * and compatibility over all STM32 families. However, the different
1878 * features can be set under different ADC state conditions
1879 * (setting possible with ADC enabled without conversion on going,
1880 * ADC enabled with conversion on going, ...)
1881 * Each feature can be updated afterwards with a unitary function
1882 * and potentially with ADC in a different state than disabled,
1883 * refer to description of each function for setting
1884 * conditioned to ADC state.
1885 * @note After using this function, other features must be configured
1886 * using LL unitary functions.
1887 * The minimum configuration remaining to be done is:
1888 * - Set ADC group injected sequencer:
1889 * map channel on the selected sequencer rank.
1890 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
1891 * - Set ADC channel sampling time
1892 * Refer to function LL_ADC_SetChannelSamplingTime();
1893 * @param ADCx ADC instance
1894 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1895 * @retval An ErrorStatus enumeration value:
1896 * - SUCCESS: ADC registers are initialized
1897 * - ERROR: ADC registers are not initialized
1898 */
1899 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1900 {
1901 ErrorStatus status = SUCCESS;
1902
1903 /* Check the parameters */
1904 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
1905 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
1906 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
1907 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
1908 {
1909 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
1910 }
1911 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
1912
1913 /* Note: Hardware constraint (refer to description of this function): */
1914 /* ADC instance must be disabled. */
1915 if(LL_ADC_IsEnabled(ADCx) == 0U)
1916 {
1917 /* Configuration of ADC hierarchical scope: */
1918 /* - ADC group injected */
1919 /* - Set ADC group injected trigger source */
1920 /* - Set ADC group injected sequencer length */
1921 /* - Set ADC group injected sequencer discontinuous mode */
1922 /* - Set ADC group injected conversion trigger: independent or */
1923 /* from ADC group regular */
1924 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
1925 /* ADC conversion. */
1926 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
1927 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
1928 {
1929 MODIFY_REG(ADCx->CR1,
1930 ADC_CR1_JDISCEN
1931 | ADC_CR1_JAUTO
1932 ,
1933 ADC_INJ_InitStruct->SequencerDiscont
1934 | ADC_INJ_InitStruct->TrigAuto
1935 );
1936 }
1937 else
1938 {
1939 MODIFY_REG(ADCx->CR1,
1940 ADC_CR1_JDISCEN
1941 | ADC_CR1_JAUTO
1942 ,
1943 LL_ADC_REG_SEQ_DISCONT_DISABLE
1944 | ADC_INJ_InitStruct->TrigAuto
1945 );
1946 }
1947
1948 MODIFY_REG(ADCx->CR2,
1949 ADC_CR2_JEXTSEL
1950 ,
1951 ADC_INJ_InitStruct->TriggerSource
1952 );
1953
1954 /* Note: Hardware constraint (refer to description of this function): */
1955 /* Note: If ADC instance feature scan mode is disabled */
1956 /* (refer to ADC instance initialization structure */
1957 /* parameter @ref SequencersScanMode */
1958 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
1959 /* this parameter is discarded. */
1960 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
1961 }
1962 else
1963 {
1964 /* Initialization error: ADC instance is not disabled. */
1965 status = ERROR;
1966 }
1967 return status;
1968 }
1969
1970 /**
1971 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
1972 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
1973 * whose fields will be set to default values.
1974 * @retval None
1975 */
1976 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
1977 {
1978 /* Set ADC_INJ_InitStruct fields to default values */
1979 /* Set fields of ADC group injected */
1980 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
1981 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
1982 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
1983 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
1984 }
1985
1986 /**
1987 * @}
1988 */
1989
1990 /**
1991 * @}
1992 */
1993
1994 /**
1995 * @}
1996 */
1997
1998 #endif /* ADC1 */
1999
2000
2001 #endif /* STM32F373xC || STM32F378xx */
2002
2003 /**
2004 * @}
2005 */
2006
2007 #endif /* USE_FULL_LL_DRIVER */
2008
2009 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/