lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_ll_pwr.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_ll_pwr.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of PWR LL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35
  36 /* Define to prevent recursive inclusion -------------------------------------*/
  37 #ifndef __STM32F3xx_LL_PWR_H
  38 #define __STM32F3xx_LL_PWR_H
  39
  40 #ifdef __cplusplus
  41 extern "C" {
  42 #endif
  43
  44 /* Includes ------------------------------------------------------------------*/
  45 #include "stm32f3xx.h"
  46
  47 /** @addtogroup STM32F3xx_LL_Driver
  48   * @{
  49   */
  50
  51 #if defined(PWR)
  52
  53 /** @defgroup PWR_LL PWR
  54   * @{
  55   */
  56
  57 /* Private types -------------------------------------------------------------*/
  58 /* Private variables ---------------------------------------------------------*/
  59 /* Private constants ---------------------------------------------------------*/
  60 /* Private macros ------------------------------------------------------------*/
  61 /* Exported types ------------------------------------------------------------*/
  62 /* Exported constants --------------------------------------------------------*/
  63 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
  64   * @{
  65   */
  66
  67 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
  68   * @brief    Flags defines which can be used with LL_PWR_WriteReg function
  69   * @{
  70   */
  71 #define LL_PWR_CR_CSBF                     PWR_CR_CSBF            /*!< Clear standby flag */
  72 #define LL_PWR_CR_CWUF                     PWR_CR_CWUF            /*!< Clear wakeup flag */
  73 /**
  74   * @}
  75   */
  76
  77 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
  78   * @brief    Flags defines which can be used with LL_PWR_ReadReg function
  79   * @{
  80   */
  81 #define LL_PWR_CSR_WUF                     PWR_CSR_WUF            /*!< Wakeup flag */
  82 #define LL_PWR_CSR_SBF                     PWR_CSR_SBF            /*!< Standby flag */
  83 #if defined(PWR_PVD_SUPPORT)
  84 #define LL_PWR_CSR_PVDO                    PWR_CSR_PVDO           /*!< Power voltage detector output flag */
  85 #endif /* PWR_PVD_SUPPORT */
  86 #if defined(PWR_CSR_VREFINTRDYF)
  87 #define LL_PWR_CSR_VREFINTRDYF             PWR_CSR_VREFINTRDYF    /*!< VREFINT ready flag */
  88 #endif /* PWR_CSR_VREFINTRDYF */
  89 #define LL_PWR_CSR_EWUP1                   PWR_CSR_EWUP1          /*!< Enable WKUP pin 1 */
  90 #define LL_PWR_CSR_EWUP2                   PWR_CSR_EWUP2          /*!< Enable WKUP pin 2 */
  91 #if defined(PWR_CSR_EWUP3)
  92 #define LL_PWR_CSR_EWUP3                   PWR_CSR_EWUP3          /*!< Enable WKUP pin 3 */
  93 #endif /* PWR_CSR_EWUP3 */
  94 /**
  95   * @}
  96   */
  97
  98
  99 /** @defgroup PWR_LL_EC_MODE_PWR Mode Power
 100   * @{
 101   */
 102 #define LL_PWR_MODE_STOP_MAINREGU             0x00000000U                    /*!< Enter Stop mode when the CPU enters deepsleep */
 103 #define LL_PWR_MODE_STOP_LPREGU               (PWR_CR_LPDS)                  /*!< Enter Stop mode (with low power Regulator ON) when the CPU enters deepsleep */
 104 #define LL_PWR_MODE_STANDBY                   (PWR_CR_PDDS)                  /*!< Enter Standby mode when the CPU enters deepsleep */
 105 /**
 106   * @}
 107   */
 108
 109 #if defined(PWR_CR_LPDS)
 110 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE  Regulator Mode In Deep Sleep Mode
 111  * @{
 112  */
 113 #define LL_PWR_REGU_DSMODE_MAIN        0x00000000U           /*!< Voltage Regulator in main mode during deepsleep mode */
 114 #define LL_PWR_REGU_DSMODE_LOW_POWER   (PWR_CR_LPDS)         /*!< Voltage Regulator in low-power mode during deepsleep mode */
 115 /**
 116   * @}
 117   */
 118 #endif /* PWR_CR_LPDS */
 119
 120 #if defined(PWR_PVD_SUPPORT)
 121 /** @defgroup PWR_LL_EC_PVDLEVEL Power Voltage Detector Level
 122   * @{
 123   */
 124 #define LL_PWR_PVDLEVEL_0                  (PWR_CR_PLS_LEV0)      /*!< Voltage threshold detected by PVD 2.2 V */
 125 #define LL_PWR_PVDLEVEL_1                  (PWR_CR_PLS_LEV1)      /*!< Voltage threshold detected by PVD 2.3 V */
 126 #define LL_PWR_PVDLEVEL_2                  (PWR_CR_PLS_LEV2)      /*!< Voltage threshold detected by PVD 2.4 V */
 127 #define LL_PWR_PVDLEVEL_3                  (PWR_CR_PLS_LEV3)      /*!< Voltage threshold detected by PVD 2.5 V */
 128 #define LL_PWR_PVDLEVEL_4                  (PWR_CR_PLS_LEV4)      /*!< Voltage threshold detected by PVD 2.6 V */
 129 #define LL_PWR_PVDLEVEL_5                  (PWR_CR_PLS_LEV5)      /*!< Voltage threshold detected by PVD 2.7 V */
 130 #define LL_PWR_PVDLEVEL_6                  (PWR_CR_PLS_LEV6)      /*!< Voltage threshold detected by PVD 2.8 V */
 131 #define LL_PWR_PVDLEVEL_7                  (PWR_CR_PLS_LEV7)      /*!< Voltage threshold detected by PVD 2.9 V */
 132 /**
 133   * @}
 134   */
 135 #endif /* PWR_PVD_SUPPORT */
 136 /** @defgroup PWR_LL_EC_WAKEUP_PIN  Wakeup Pins
 137   * @{
 138   */
 139 #define LL_PWR_WAKEUP_PIN1                 (PWR_CSR_EWUP1)        /*!< WKUP pin 1 : PA0 */
 140 #define LL_PWR_WAKEUP_PIN2                 (PWR_CSR_EWUP2)        /*!< WKUP pin 2 : PC13 */
 141 #if defined(PWR_CSR_EWUP3)
 142 #define LL_PWR_WAKEUP_PIN3                 (PWR_CSR_EWUP3)        /*!< WKUP pin 3 : PE6 or PA2 according to device */
 143 #endif /* PWR_CSR_EWUP3 */
 144 /**
 145   * @}
 146   */
 147
 148 /** @defgroup PWR_LL_EC_SDADC_ANALOG_X SDADC Analogx
 149   * @{
 150   */
 151 #if defined(SDADC1)
 152 #define LL_PWR_SDADC_ANALOG1              (PWR_CR_ENSD1)   /*!< Enable SDADC1 */
 153 #endif /* SDADC1 */
 154 #if defined(SDADC2)
 155 #define LL_PWR_SDADC_ANALOG2              (PWR_CR_ENSD2)   /*!< Enable SDADC2 */
 156 #endif /* SDADC2 */
 157 #if defined(SDADC3)
 158 #define LL_PWR_SDADC_ANALOG3              (PWR_CR_ENSD3)   /*!< Enable SDADC3 */
 159 #endif /* SDADC3 */
 160 /**
 161   * @}
 162   */
 163 /**
 164   * @}
 165   */
 166
 167
 168 /* Exported macro ------------------------------------------------------------*/
 169 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
 170   * @{
 171   */
 172
 173 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
 174   * @{
 175   */
 176
 177 /**
 178   * @brief  Write a value in PWR register
 179   * @param  __REG__ Register to be written
 180   * @param  __VALUE__ Value to be written in the register
 181   * @retval None
 182   */
 183 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
 184
 185 /**
 186   * @brief  Read a value in PWR register
 187   * @param  __REG__ Register to be read
 188   * @retval Register value
 189   */
 190 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
 191 /**
 192   * @}
 193   */
 194
 195 /**
 196   * @}
 197   */
 198
 199 /* Exported functions --------------------------------------------------------*/
 200 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
 201   * @{
 202   */
 203
 204 /** @defgroup PWR_LL_EF_Configuration Configuration
 205   * @{
 206   */
 207 /**
 208   * @brief  Enables the SDADC peripheral functionality
 209   * @rmtoll CR   ENSD1       LL_PWR_EnableSDADC\n
 210   *         CR   ENSD2       LL_PWR_EnableSDADC\n
 211   *         CR   ENSD3       LL_PWR_EnableSDADC
 212   * @param  Analogx This parameter can be a combination of the following values:
 213   *         @arg @ref LL_PWR_SDADC_ANALOG1
 214   *         @arg @ref LL_PWR_SDADC_ANALOG2
 215   *         @arg @ref LL_PWR_SDADC_ANALOG3
 216   * @retval None
 217   */
 218 __STATIC_INLINE void LL_PWR_EnableSDADC(uint32_t Analogx)
 219 {
 220   SET_BIT(PWR->CR, Analogx);
 221 }
 222
 223 /**
 224   * @brief  Disables the SDADC peripheral functionality
 225   * @rmtoll CR   ENSD1       LL_PWR_EnableSDADC\n
 226   *         CR   ENSD2       LL_PWR_EnableSDADC\n
 227   *         CR   ENSD3       LL_PWR_EnableSDADC
 228   * @param  Analogx This parameter can be a combination of the following values:
 229   *         @arg @ref LL_PWR_SDADC_ANALOG1
 230   *         @arg @ref LL_PWR_SDADC_ANALOG2
 231   *         @arg @ref LL_PWR_SDADC_ANALOG3
 232   * @retval None
 233   */
 234 __STATIC_INLINE void LL_PWR_DisableSDADC(uint32_t Analogx)
 235 {
 236   CLEAR_BIT(PWR->CR, Analogx);
 237 }
 238
 239 /**
 240   * @brief  Check if SDADCx has been enabled or not
 241   * @rmtoll CR   ENSD1       LL_PWR_IsEnabledSDADC\n
 242   *         CR   ENSD2       LL_PWR_IsEnabledSDADC\n
 243   *         CR   ENSD3       LL_PWR_IsEnabledSDADC
 244   * @param  Analogx This parameter can be a combination of the following values:
 245   *         @arg @ref LL_PWR_SDADC_ANALOG1
 246   *         @arg @ref LL_PWR_SDADC_ANALOG2
 247   *         @arg @ref LL_PWR_SDADC_ANALOG3
 248   * @retval None
 249   */
 250 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSDADC(uint32_t Analogx)
 251 {
 252   return (READ_BIT(PWR->CR, Analogx) == (Analogx));
 253 }
 254
 255 /**
 256   * @brief  Enable access to the backup domain
 257   * @rmtoll CR    DBP       LL_PWR_EnableBkUpAccess
 258   * @retval None
 259   */
 260 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
 261 {
 262   SET_BIT(PWR->CR, PWR_CR_DBP);
 263 }
 264
 265 /**
 266   * @brief  Disable access to the backup domain
 267   * @rmtoll CR    DBP       LL_PWR_DisableBkUpAccess
 268   * @retval None
 269   */
 270 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
 271 {
 272   CLEAR_BIT(PWR->CR, PWR_CR_DBP);
 273 }
 274
 275 /**
 276   * @brief  Check if the backup domain is enabled
 277   * @rmtoll CR    DBP       LL_PWR_IsEnabledBkUpAccess
 278   * @retval State of bit (1 or 0).
 279   */
 280 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
 281 {
 282   return (READ_BIT(PWR->CR, PWR_CR_DBP) == (PWR_CR_DBP));
 283 }
 284
 285 #if defined(PWR_CR_LPDS)
 286 /**
 287   * @brief  Set voltage Regulator mode during deep sleep mode
 288   * @rmtoll CR    LPDS         LL_PWR_SetRegulModeDS
 289   * @param  RegulMode This parameter can be one of the following values:
 290   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
 291   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
 292   * @retval None
 293   */
 294 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
 295 {
 296   MODIFY_REG(PWR->CR, PWR_CR_LPDS, RegulMode);
 297 }
 298
 299 /**
 300   * @brief  Get voltage Regulator mode during deep sleep mode
 301   * @rmtoll CR    LPDS         LL_PWR_GetRegulModeDS
 302   * @retval Returned value can be one of the following values:
 303   *         @arg @ref LL_PWR_REGU_DSMODE_MAIN
 304   *         @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
 305   */
 306 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
 307 {
 308   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_LPDS));
 309 }
 310 #endif /* PWR_CR_LPDS */
 311
 312 /**
 313   * @brief  Set Power Down mode when CPU enters deepsleep
 314   * @rmtoll CR    PDDS         LL_PWR_SetPowerMode\n
 315   * @rmtoll CR    LPDS         LL_PWR_SetPowerMode
 316   * @param  PDMode This parameter can be one of the following values:
 317   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
 318   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
 319   *         @arg @ref LL_PWR_MODE_STANDBY
 320   * @retval None
 321   */
 322 __STATIC_INLINE void LL_PWR_SetPowerMode(uint32_t PDMode)
 323 {
 324   MODIFY_REG(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS), PDMode);
 325 }
 326
 327 /**
 328   * @brief  Get Power Down mode when CPU enters deepsleep
 329   * @rmtoll CR    PDDS         LL_PWR_GetPowerMode\n
 330   * @rmtoll CR    LPDS         LL_PWR_GetPowerMode
 331   * @retval Returned value can be one of the following values:
 332   *         @arg @ref LL_PWR_MODE_STOP_MAINREGU
 333   *         @arg @ref LL_PWR_MODE_STOP_LPREGU
 334   *         @arg @ref LL_PWR_MODE_STANDBY
 335   */
 336 __STATIC_INLINE uint32_t LL_PWR_GetPowerMode(void)
 337 {
 338   return (uint32_t)(READ_BIT(PWR->CR, (PWR_CR_PDDS| PWR_CR_LPDS)));
 339 }
 340
 341 #if defined(PWR_PVD_SUPPORT)
 342 /**
 343   * @brief  Configure the voltage threshold detected by the Power Voltage Detector
 344   * @rmtoll CR    PLS       LL_PWR_SetPVDLevel
 345   * @param  PVDLevel This parameter can be one of the following values:
 346   *         @arg @ref LL_PWR_PVDLEVEL_0
 347   *         @arg @ref LL_PWR_PVDLEVEL_1
 348   *         @arg @ref LL_PWR_PVDLEVEL_2
 349   *         @arg @ref LL_PWR_PVDLEVEL_3
 350   *         @arg @ref LL_PWR_PVDLEVEL_4
 351   *         @arg @ref LL_PWR_PVDLEVEL_5
 352   *         @arg @ref LL_PWR_PVDLEVEL_6
 353   *         @arg @ref LL_PWR_PVDLEVEL_7
 354   * @retval None
 355   */
 356 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
 357 {
 358   MODIFY_REG(PWR->CR, PWR_CR_PLS, PVDLevel);
 359 }
 360
 361 /**
 362   * @brief  Get the voltage threshold detection
 363   * @rmtoll CR    PLS       LL_PWR_GetPVDLevel
 364   * @retval Returned value can be one of the following values:
 365   *         @arg @ref LL_PWR_PVDLEVEL_0
 366   *         @arg @ref LL_PWR_PVDLEVEL_1
 367   *         @arg @ref LL_PWR_PVDLEVEL_2
 368   *         @arg @ref LL_PWR_PVDLEVEL_3
 369   *         @arg @ref LL_PWR_PVDLEVEL_4
 370   *         @arg @ref LL_PWR_PVDLEVEL_5
 371   *         @arg @ref LL_PWR_PVDLEVEL_6
 372   *         @arg @ref LL_PWR_PVDLEVEL_7
 373   */
 374 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
 375 {
 376   return (uint32_t)(READ_BIT(PWR->CR, PWR_CR_PLS));
 377 }
 378
 379 /**
 380   * @brief  Enable Power Voltage Detector
 381   * @rmtoll CR    PVDE       LL_PWR_EnablePVD
 382   * @retval None
 383   */
 384 __STATIC_INLINE void LL_PWR_EnablePVD(void)
 385 {
 386   SET_BIT(PWR->CR, PWR_CR_PVDE);
 387 }
 388
 389 /**
 390   * @brief  Disable Power Voltage Detector
 391   * @rmtoll CR    PVDE       LL_PWR_DisablePVD
 392   * @retval None
 393   */
 394 __STATIC_INLINE void LL_PWR_DisablePVD(void)
 395 {
 396   CLEAR_BIT(PWR->CR, PWR_CR_PVDE);
 397 }
 398
 399 /**
 400   * @brief  Check if Power Voltage Detector is enabled
 401   * @rmtoll CR    PVDE       LL_PWR_IsEnabledPVD
 402   * @retval State of bit (1 or 0).
 403   */
 404 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
 405 {
 406   return (READ_BIT(PWR->CR, PWR_CR_PVDE) == (PWR_CR_PVDE));
 407 }
 408 #endif /* PWR_PVD_SUPPORT */
 409
 410 /**
 411   * @brief  Enable the WakeUp PINx functionality
 412   * @rmtoll CSR   EWUP1       LL_PWR_EnableWakeUpPin\n
 413   * @rmtoll CSR   EWUP2       LL_PWR_EnableWakeUpPin\n
 414   * @rmtoll CSR   EWUP3       LL_PWR_EnableWakeUpPin
 415   * @param  WakeUpPin This parameter can be one of the following values:
 416   *         @arg @ref LL_PWR_WAKEUP_PIN1
 417   *         @arg @ref LL_PWR_WAKEUP_PIN2
 418   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
 419   *
 420   *         (*) not available on all devices
 421   * @retval None
 422   */
 423 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
 424 {
 425   SET_BIT(PWR->CSR, WakeUpPin);
 426 }
 427
 428 /**
 429   * @brief  Disable the WakeUp PINx functionality
 430   * @rmtoll CSR   EWUP1       LL_PWR_DisableWakeUpPin\n
 431   * @rmtoll CSR   EWUP2       LL_PWR_DisableWakeUpPin\n
 432   * @rmtoll CSR   EWUP3       LL_PWR_DisableWakeUpPin
 433   * @param  WakeUpPin This parameter can be one of the following values:
 434   *         @arg @ref LL_PWR_WAKEUP_PIN1
 435   *         @arg @ref LL_PWR_WAKEUP_PIN2
 436   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
 437   *
 438   *         (*) not available on all devices
 439   * @retval None
 440   */
 441 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
 442 {
 443   CLEAR_BIT(PWR->CSR, WakeUpPin);
 444 }
 445
 446 /**
 447   * @brief  Check if the WakeUp PINx functionality is enabled
 448   * @rmtoll CSR   EWUP1       LL_PWR_IsEnabledWakeUpPin\n
 449   * @rmtoll CSR   EWUP2       LL_PWR_IsEnabledWakeUpPin\n
 450   * @rmtoll CSR   EWUP3       LL_PWR_IsEnabledWakeUpPin
 451   * @param  WakeUpPin This parameter can be one of the following values:
 452   *         @arg @ref LL_PWR_WAKEUP_PIN1
 453   *         @arg @ref LL_PWR_WAKEUP_PIN2
 454   *         @arg @ref LL_PWR_WAKEUP_PIN3 (*)
 455   *
 456   *         (*) not available on all devices
 457   * @retval State of bit (1 or 0).
 458   */
 459 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
 460 {
 461   return (READ_BIT(PWR->CSR, WakeUpPin) == (WakeUpPin));
 462 }
 463
 464
 465 /**
 466   * @}
 467   */
 468
 469 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
 470   * @{
 471   */
 472
 473 /**
 474   * @brief  Get Wake-up Flag
 475   * @rmtoll CSR   WUF       LL_PWR_IsActiveFlag_WU
 476   * @retval State of bit (1 or 0).
 477   */
 478 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU(void)
 479 {
 480   return (READ_BIT(PWR->CSR, PWR_CSR_WUF) == (PWR_CSR_WUF));
 481 }
 482
 483 /**
 484   * @brief  Get Standby Flag
 485   * @rmtoll CSR   SBF       LL_PWR_IsActiveFlag_SB
 486   * @retval State of bit (1 or 0).
 487   */
 488 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SB(void)
 489 {
 490   return (READ_BIT(PWR->CSR, PWR_CSR_SBF) == (PWR_CSR_SBF));
 491 }
 492
 493 #if defined(PWR_PVD_SUPPORT)
 494 /**
 495   * @brief  Indicate whether VDD voltage is below the selected PVD threshold
 496   * @rmtoll CSR   PVDO       LL_PWR_IsActiveFlag_PVDO
 497   * @retval State of bit (1 or 0).
 498   */
 499 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
 500 {
 501   return (READ_BIT(PWR->CSR, PWR_CSR_PVDO) == (PWR_CSR_PVDO));
 502 }
 503 #endif /* PWR_PVD_SUPPORT */
 504
 505 #if defined(PWR_CSR_VREFINTRDYF)
 506 /**
 507   * @brief  Get Internal Reference VrefInt Flag
 508   * @rmtoll CSR   VREFINTRDYF       LL_PWR_IsActiveFlag_VREFINTRDY
 509   * @retval State of bit (1 or 0).
 510   */
 511 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VREFINTRDY(void)
 512 {
 513   return (READ_BIT(PWR->CSR, PWR_CSR_VREFINTRDYF) == (PWR_CSR_VREFINTRDYF));
 514 }
 515 #endif /* PWR_CSR_VREFINTRDYF */
 516 /**
 517   * @brief  Clear Standby Flag
 518   * @rmtoll CR   CSBF       LL_PWR_ClearFlag_SB
 519   * @retval None
 520   */
 521 __STATIC_INLINE void LL_PWR_ClearFlag_SB(void)
 522 {
 523   SET_BIT(PWR->CR, PWR_CR_CSBF);
 524 }
 525
 526 /**
 527   * @brief  Clear Wake-up Flags
 528   * @rmtoll CR   CWUF       LL_PWR_ClearFlag_WU
 529   * @retval None
 530   */
 531 __STATIC_INLINE void LL_PWR_ClearFlag_WU(void)
 532 {
 533   SET_BIT(PWR->CR, PWR_CR_CWUF);
 534 }
 535
 536 /**
 537   * @}
 538   */
 539
 540 #if defined(USE_FULL_LL_DRIVER)
 541 /** @defgroup PWR_LL_EF_Init De-initialization function
 542   * @{
 543   */
 544 ErrorStatus LL_PWR_DeInit(void);
 545 /**
 546   * @}
 547   */
 548 #endif /* USE_FULL_LL_DRIVER */
 549
 550 /**
 551   * @}
 552   */
 553
 554 /**
 555   * @}
 556   */
 557
 558 #endif /* defined(PWR) */
 559
 560 /**
 561   * @}
 562   */
 563
 564 #ifdef __cplusplus
 565 }
 566 #endif
 567
 568 #endif /* __STM32F3xx_LL_PWR_H */
 569
 570 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/