lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_sdadc.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_sdadc.h
   4   * @author  MCD Application Team
   5   * @brief   This file contains all the functions prototypes for the SDADC
   6   *          firmware library.
   7   ******************************************************************************
   8   * @attention
   9   *
  10   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  11   *
  12   * Redistribution and use in source and binary forms, with or without modification,
  13   * are permitted provided that the following conditions are met:
  14   *   1. Redistributions of source code must retain the above copyright notice,
  15   *      this list of conditions and the following disclaimer.
  16   *   2. Redistributions in binary form must reproduce the above copyright notice,
  17   *      this list of conditions and the following disclaimer in the documentation
  18   *      and/or other materials provided with the distribution.
  19   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  20   *      may be used to endorse or promote products derived from this software
  21   *      without specific prior written permission.
  22   *
  23   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  24   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  25   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  26   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  27   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  28   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  29   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  30   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  31   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  32   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  33   *
  34   ******************************************************************************
  35   */
  36
  37 /* Define to prevent recursive inclusion -------------------------------------*/
  38 #ifndef __STM32F3xx_SDADC_H
  39 #define __STM32F3xx_SDADC_H
  40
  41 #ifdef __cplusplus
  42  extern "C" {
  43 #endif
  44
  45 #if defined(STM32F373xC) || defined(STM32F378xx)
  46
  47 /* Includes ------------------------------------------------------------------*/
  48 #include "stm32f3xx_hal_def.h"
  49
  50 /** @addtogroup STM32F3xx_HAL_Driver
  51   * @{
  52   */
  53
  54 /** @addtogroup SDADC
  55   * @{
  56   */
  57
  58 /* Exported types ------------------------------------------------------------*/
  59 /** @defgroup SDADC_Exported_Types SDADC Exported Types
  60   * @{
  61   */
  62
  63
  64 /**
  65   * @brief  HAL SDADC States definition
  66   */
  67 typedef enum
  68 {
  69   HAL_SDADC_STATE_RESET                   = 0x00U,    /*!< SDADC not initialized */
  70   HAL_SDADC_STATE_READY                   = 0x01U,    /*!< SDADC initialized and ready for use */
  71   HAL_SDADC_STATE_CALIB                   = 0x02U,    /*!< SDADC calibration in progress */
  72   HAL_SDADC_STATE_REG                     = 0x03U,    /*!< SDADC regular conversion in progress */
  73   HAL_SDADC_STATE_INJ                     = 0x04U,    /*!< SDADC injected conversion in progress */
  74   HAL_SDADC_STATE_REG_INJ                 = 0x05U,    /*!< SDADC regular and injected conversions in progress */
  75   HAL_SDADC_STATE_ERROR                   = 0xFFU,    /*!< SDADC state error */
  76 }HAL_SDADC_StateTypeDef;
  77
  78 /**
  79   * @brief SDADC Init Structure definition
  80   */
  81 typedef struct
  82 {
  83   uint32_t IdleLowPowerMode;        /*!< Specifies if SDADC can enter in power down or standby when idle.
  84                                          This parameter can be a value of @ref SDADC_Idle_Low_Power_Mode */
  85   uint32_t FastConversionMode;      /*!< Specifies if Fast conversion mode is enabled or not.
  86                                          This parameter can be a value of @ref SDADC_Fast_Conv_Mode */
  87   uint32_t SlowClockMode;           /*!< Specifies if slow clock mode is enabled or not.
  88                                          This parameter can be a value of @ref SDADC_Slow_Clock_Mode */
  89   uint32_t ReferenceVoltage;        /*!< Specifies the reference voltage.
  90                                          Note: This parameter is common to all SDADC instances.
  91                                          This parameter can be a value of @ref SDADC_Reference_Voltage */
  92 }SDADC_InitTypeDef;
  93
  94 /**
  95   * @brief  SDADC handle Structure definition
  96   */
  97 typedef struct
  98 {
  99   SDADC_TypeDef            *Instance;           /*!< SDADC registers base address */
 100   SDADC_InitTypeDef        Init;                /*!< SDADC init parameters        */
 101   DMA_HandleTypeDef        *hdma;               /*!< SDADC DMA Handle parameters  */
 102   uint32_t                 RegularContMode;     /*!< Regular conversion continuous mode */
 103   uint32_t                 InjectedContMode;    /*!< Injected conversion continuous mode */
 104   uint32_t                 InjectedChannelsNbr; /*!< Number of channels in injected sequence */
 105   uint32_t                 InjConvRemaining;    /*!< Injected conversion remaining */
 106   uint32_t                 RegularTrigger;      /*!< Current trigger used for regular conversion */
 107   uint32_t                 InjectedTrigger;     /*!< Current trigger used for injected conversion */
 108   uint32_t                 ExtTriggerEdge;      /*!< Rising, falling or both edges selected */
 109   uint32_t                 RegularMultimode;    /*!< current type of regular multimode */
 110   uint32_t                 InjectedMultimode;   /*!< Current type of injected multimode */
 111   HAL_SDADC_StateTypeDef   State;               /*!< SDADC state */
 112   uint32_t                 ErrorCode;           /*!< SDADC Error code */
 113 }SDADC_HandleTypeDef;
 114
 115 /**
 116   * @brief  SDADC Configuration Register Parameter Structure
 117   */
 118 typedef struct
 119 {
 120   uint32_t InputMode;      /*!< Specifies the input mode (single ended, differential...)
 121                                 This parameter can be any value of @ref SDADC_InputMode */
 122   uint32_t Gain;           /*!< Specifies the gain setting.
 123                                 This parameter can be any value of @ref SDADC_Gain */
 124   uint32_t CommonMode;     /*!< Specifies the common mode setting (VSSA, VDDA, VDDA/2U).
 125                                 This parameter can be any value of @ref SDADC_CommonMode */
 126   uint32_t Offset;         /*!< Specifies the 12-bit offset value.
 127                                 This parameter can be any value lower or equal to 0x00000FFFU */
 128 }SDADC_ConfParamTypeDef;
 129
 130 /**
 131   * @}
 132   */
 133
 134 /* Exported constants --------------------------------------------------------*/
 135
 136 /** @defgroup SDADC_Exported_Constants SDADC Exported Constants
 137   * @{
 138   */
 139
 140 /** @defgroup SDADC_Idle_Low_Power_Mode SDADC Idle Low Power Mode
 141   * @{
 142   */
 143 #define SDADC_LOWPOWER_NONE                  (0x00000000U)
 144 #define SDADC_LOWPOWER_POWERDOWN             SDADC_CR1_PDI
 145 #define SDADC_LOWPOWER_STANDBY               SDADC_CR1_SBI
 146 /**
 147   * @}
 148   */
 149
 150 /** @defgroup SDADC_Fast_Conv_Mode SDADC Fast Conversion Mode
 151   * @{
 152   */
 153 #define SDADC_FAST_CONV_DISABLE              (0x00000000U)
 154 #define SDADC_FAST_CONV_ENABLE               SDADC_CR2_FAST
 155 /**
 156   * @}
 157   */
 158
 159 /** @defgroup SDADC_Slow_Clock_Mode SDADC Slow Clock Mode
 160   * @{
 161   */
 162 #define SDADC_SLOW_CLOCK_DISABLE             (0x00000000U)
 163 #define SDADC_SLOW_CLOCK_ENABLE              SDADC_CR1_SLOWCK
 164 /**
 165   * @}
 166   */
 167
 168 /** @defgroup SDADC_Reference_Voltage SDADC Reference Voltage
 169   * @{
 170   */
 171 #define SDADC_VREF_EXT                       (0x00000000U) /*!< The reference voltage is forced externally using VREF pin */
 172 #define SDADC_VREF_VREFINT1                  SDADC_CR1_REFV_0       /*!< The reference voltage is forced internally to 1.22V VREFINT */
 173 #define SDADC_VREF_VREFINT2                  SDADC_CR1_REFV_1       /*!< The reference voltage is forced internally to 1.8V VREFINT */
 174 #define SDADC_VREF_VDDA                      SDADC_CR1_REFV         /*!< The reference voltage is forced internally to VDDA */
 175 /**
 176   * @}
 177   */
 178
 179 /** @defgroup SDADC_ConfIndex SDADC Configuration Index
 180   * @{
 181   */
 182
 183 #define SDADC_CONF_INDEX_0                     (0x00000000U) /*!< Configuration 0 Register selected */
 184 #define SDADC_CONF_INDEX_1                     (0x00000001U) /*!< Configuration 1 Register selected */
 185 #define SDADC_CONF_INDEX_2                     (0x00000002U) /*!< Configuration 2 Register selected */
 186 /**
 187   * @}
 188   */
 189
 190 /** @defgroup SDADC_InputMode SDADC Input Mode
 191   * @{
 192   */
 193 #define SDADC_INPUT_MODE_DIFF                (0x00000000U) /*!< Conversions are executed in differential mode */
 194 #define SDADC_INPUT_MODE_SE_OFFSET           SDADC_CONF0R_SE0_0     /*!< Conversions are executed in single ended offset mode */
 195 #define SDADC_INPUT_MODE_SE_ZERO_REFERENCE   SDADC_CONF0R_SE0       /*!< Conversions are executed in single ended zero-volt reference mode */
 196 /**
 197   * @}
 198   */
 199
 200 /** @defgroup SDADC_Gain SDADC Gain
 201   * @{
 202   */
 203 #define SDADC_GAIN_1                         (0x00000000U)  /*!< Gain equal to 1U */
 204 #define SDADC_GAIN_2                         SDADC_CONF0R_GAIN0_0    /*!< Gain equal to 2U */
 205 #define SDADC_GAIN_4                         SDADC_CONF0R_GAIN0_1    /*!< Gain equal to 4U */
 206 #define SDADC_GAIN_8                         (0x00300000U)  /*!< Gain equal to 8U */
 207 #define SDADC_GAIN_16                        SDADC_CONF0R_GAIN0_2    /*!< Gain equal to 16U */
 208 #define SDADC_GAIN_32                        (0x00500000U)  /*!< Gain equal to 32U */
 209 #define SDADC_GAIN_1_2                       SDADC_CONF0R_GAIN0      /*!< Gain equal to 1U/2U */
 210 /**
 211   * @}
 212   */
 213
 214 /** @defgroup SDADC_CommonMode SDADC Common Mode
 215   * @{
 216   */
 217 #define SDADC_COMMON_MODE_VSSA               (0x00000000U) /*!< Select SDADC VSSA as common mode */
 218 #define SDADC_COMMON_MODE_VDDA_2             SDADC_CONF0R_COMMON0_0 /*!< Select SDADC VDDA/2 as common mode */
 219 #define SDADC_COMMON_MODE_VDDA               SDADC_CONF0R_COMMON0_1 /*!< Select SDADC VDDA as common mode */
 220 /**
 221   * @}
 222   */
 223
 224
 225
 226 /** @defgroup SDADC_Channel_Selection SDADC Channel Selection
 227   * @{
 228   */
 229
 230 /* SDADC Channels ------------------------------------------------------------*/
 231 /* The SDADC channels are defined as follows:
 232    - in 16-bit LSB the channel mask is set
 233    - in 16-bit MSB the channel number is set
 234    e.g. for channel 5 definition:
 235         - the channel mask is 0x00000020 (bit 5 is set)
 236         - the channel number 5 is 0x00050000
 237         --> Consequently, channel 5 definition is 0x00000020U | 0x00050000U = 0x00050020U */
 238 #define SDADC_CHANNEL_0                              (0x00000001U)
 239 #define SDADC_CHANNEL_1                              (0x00010002U)
 240 #define SDADC_CHANNEL_2                              (0x00020004U)
 241 #define SDADC_CHANNEL_3                              (0x00030008U)
 242 #define SDADC_CHANNEL_4                              (0x00040010U)
 243 #define SDADC_CHANNEL_5                              (0x00050020U)
 244 #define SDADC_CHANNEL_6                              (0x00060040U)
 245 #define SDADC_CHANNEL_7                              (0x00070080U)
 246 #define SDADC_CHANNEL_8                              (0x00080100U)
 247 /**
 248   * @}
 249   */
 250
 251 /** @defgroup SDADC_CalibrationSequence SDADC Calibration Sequence
 252   * @{
 253   */
 254 #define SDADC_CALIBRATION_SEQ_1                   (0x00000000U) /*!< One calibration sequence to calculate offset of conf0 (OFFSET0[11:0]) */
 255 #define SDADC_CALIBRATION_SEQ_2                   SDADC_CR2_CALIBCNT_0   /*!< Two calibration sequences to calculate offset of conf0 and conf1 (OFFSET0[11:0] and OFFSET1[11:0]) */
 256 #define SDADC_CALIBRATION_SEQ_3                   SDADC_CR2_CALIBCNT_1   /*!< Three calibration sequences to calculate offset of conf0, conf1 and conf2 (OFFSET0[11:0], OFFSET1[11:0], and OFFSET2[11:0]) */
 257 /**
 258   * @}
 259   */
 260
 261 /** @defgroup SDADC_ContinuousMode SDADC Continuous Mode
 262   * @{
 263   */
 264 #define SDADC_CONTINUOUS_CONV_OFF            (0x00000000U) /*!< Conversion are not continuous */
 265 #define SDADC_CONTINUOUS_CONV_ON             (0x00000001U) /*!< Conversion are continuous */
 266 /**
 267   * @}
 268   */
 269
 270 /** @defgroup SDADC_Trigger SDADC Trigger
 271   * @{
 272   */
 273 #define SDADC_SOFTWARE_TRIGGER               (0x00000000U) /*!< Software trigger */
 274 #define SDADC_SYNCHRONOUS_TRIGGER            (0x00000001U) /*!< Synchronous with SDADC1 (only for SDADC2 and SDADC3) */
 275 #define SDADC_EXTERNAL_TRIGGER               (0x00000002U) /*!< External trigger */
 276 /**
 277   * @}
 278   */
 279
 280 /** @defgroup SDADC_InjectedExtTrigger SDADC Injected External Trigger
 281   * @{
 282   */
 283 #define SDADC_EXT_TRIG_TIM13_CC1             (0x00000000U) /*!< Trigger source for SDADC1 */
 284 #define SDADC_EXT_TRIG_TIM14_CC1             (0x00000100U) /*!< Trigger source for SDADC1 */
 285 #define SDADC_EXT_TRIG_TIM16_CC1             (0x00000000U) /*!< Trigger source for SDADC3 */
 286 #define SDADC_EXT_TRIG_TIM17_CC1             (0x00000000U) /*!< Trigger source for SDADC2 */
 287 #define SDADC_EXT_TRIG_TIM12_CC1             (0x00000100U) /*!< Trigger source for SDADC2 */
 288 #define SDADC_EXT_TRIG_TIM12_CC2             (0x00000100U) /*!< Trigger source for SDADC3 */
 289 #define SDADC_EXT_TRIG_TIM15_CC2             (0x00000200U) /*!< Trigger source for SDADC1 */
 290 #define SDADC_EXT_TRIG_TIM2_CC3              (0x00000200U) /*!< Trigger source for SDADC2 */
 291 #define SDADC_EXT_TRIG_TIM2_CC4              (0x00000200U) /*!< Trigger source for SDADC3 */
 292 #define SDADC_EXT_TRIG_TIM3_CC1              (0x00000300U) /*!< Trigger source for SDADC1 */
 293 #define SDADC_EXT_TRIG_TIM3_CC2              (0x00000300U) /*!< Trigger source for SDADC2 */
 294 #define SDADC_EXT_TRIG_TIM3_CC3              (0x00000300U) /*!< Trigger source for SDADC3 */
 295 #define SDADC_EXT_TRIG_TIM4_CC1              (0x00000400U) /*!< Trigger source for SDADC1 */
 296 #define SDADC_EXT_TRIG_TIM4_CC2              (0x00000400U) /*!< Trigger source for SDADC2 */
 297 #define SDADC_EXT_TRIG_TIM4_CC3              (0x00000400U) /*!< Trigger source for SDADC3 */
 298 #define SDADC_EXT_TRIG_TIM19_CC2             (0x00000500U) /*!< Trigger source for SDADC1 */
 299 #define SDADC_EXT_TRIG_TIM19_CC3             (0x00000500U) /*!< Trigger source for SDADC2 */
 300 #define SDADC_EXT_TRIG_TIM19_CC4             (0x00000500U) /*!< Trigger source for SDADC3 */
 301 #define SDADC_EXT_TRIG_EXTI11                (0x00000700U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
 302 #define SDADC_EXT_TRIG_EXTI15                (0x00000600U) /*!< Trigger source for SDADC1, SDADC2 and SDADC3 */
 303 /**
 304   * @}
 305   */
 306
 307 /** @defgroup SDADC_ExtTriggerEdge SDADC External Trigger Edge
 308   * @{
 309   */
 310 #define SDADC_EXT_TRIG_RISING_EDGE           SDADC_CR2_JEXTEN_0     /*!< External rising edge */
 311 #define SDADC_EXT_TRIG_FALLING_EDGE          SDADC_CR2_JEXTEN_1     /*!< External falling edge */
 312 #define SDADC_EXT_TRIG_BOTH_EDGES            SDADC_CR2_JEXTEN       /*!< External rising and falling edges */
 313 /**
 314   * @}
 315   */
 316
 317 /** @defgroup SDADC_InjectedDelay SDADC Injected Conversion Delay
 318   * @{
 319   */
 320 #define SDADC_INJECTED_DELAY_NONE            (0x00000000U) /*!< No delay on injected conversion */
 321 #define SDADC_INJECTED_DELAY                 SDADC_CR2_JDS          /*!< Delay on injected conversion */
 322 /**
 323   * @}
 324   */
 325
 326 /** @defgroup SDADC_MultimodeType SDADC Multimode Type
 327   * @{
 328   */
 329 #define SDADC_MULTIMODE_SDADC1_SDADC2        (0x00000000U) /*!< Get conversion values for SDADC1 and SDADC2 */
 330 #define SDADC_MULTIMODE_SDADC1_SDADC3        (0x00000001U) /*!< Get conversion values for SDADC1 and SDADC3 */
 331 /**
 332   * @}
 333   */
 334
 335 /** @defgroup SDADC_ErrorCode SDADC Error Code
 336   * @{
 337   */
 338 #define SDADC_ERROR_NONE                     (0x00000000U) /*!< No error */
 339 #define SDADC_ERROR_REGULAR_OVERRUN          (0x00000001U) /*!< Overrun occurs during regular conversion */
 340 #define SDADC_ERROR_INJECTED_OVERRUN         (0x00000002U) /*!< Overrun occurs during injected conversion */
 341 #define SDADC_ERROR_DMA                      (0x00000003U) /*!< DMA error occurs */
 342 /**
 343   * @}
 344   */
 345
 346 /** @defgroup SDADC_interrupts_definition SDADC interrupts definition
 347   * @{
 348   */
 349 #define  SDADC_IT_EOCAL     SDADC_CR1_EOCALIE   /*!< End of calibration interrupt enable */
 350 #define  SDADC_IT_JEOC      SDADC_CR1_JEOCIE    /*!< Injected end of conversion interrupt enable */
 351 #define  SDADC_IT_JOVR      SDADC_CR1_JOVRIE    /*!< Injected data overrun interrupt enable */
 352 #define  SDADC_IT_REOC      SDADC_CR1_REOCIE    /*!< Regular end of conversion interrupt enable */
 353 #define  SDADC_IT_ROVR      SDADC_CR1_ROVRIE    /*!< Regular data overrun interrupt enable */
 354 /**
 355   * @}
 356   */
 357
 358 /** @defgroup SDADC_flags_definition SDADC flags definition
 359   * @{
 360   */
 361 #define SDADC_FLAG_EOCAL    SDADC_ISR_EOCALF    /*!< End of calibration flag */
 362 #define SDADC_FLAG_JEOC     SDADC_ISR_JEOCF     /*!< End of injected conversion flag */
 363 #define SDADC_FLAG_JOVR     SDADC_ISR_JOVRF     /*!< Injected conversion overrun flag */
 364 #define SDADC_FLAG_REOC     SDADC_ISR_REOCF     /*!< End of regular conversion flag */
 365 #define SDADC_FLAG_ROVR     SDADC_ISR_ROVRF     /*!< Regular conversion overrun flag */
 366 /**
 367   * @}
 368   */
 369
 370 /**
 371   * @}
 372   */
 373
 374 /* Exported macros -----------------------------------------------------------*/
 375 /** @defgroup SDADC_Exported_Macros SDADC Exported Macros
 376  * @{
 377  */
 378
 379 /* Macro for internal HAL driver usage, and possibly can be used into code of */
 380 /* final user.                                                                */
 381
 382 /** @brief Enable the ADC end of conversion interrupt.
 383   * @param __HANDLE__ ADC handle
 384   * @param __INTERRUPT__ ADC Interrupt
 385   *          This parameter can be any combination of the following values:
 386   *            @arg SDADC_IT_EOCAL: End of calibration interrupt enable
 387   *            @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
 388   *            @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
 389   *            @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
 390   *            @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
 391   * @retval None
 392   */
 393 #define __HAL_SDADC_ENABLE_IT(__HANDLE__, __INTERRUPT__)                       \
 394   (SET_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
 395
 396 /** @brief Disable the ADC end of conversion interrupt.
 397   * @param __HANDLE__ ADC handle
 398   * @param __INTERRUPT__ ADC Interrupt
 399   *          This parameter can be any combination of the following values:
 400   *            @arg SDADC_IT_EOCAL: End of calibration interrupt enable
 401   *            @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
 402   *            @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
 403   *            @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
 404   *            @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
 405   * @retval None
 406   */
 407 #define __HAL_SDADC_DISABLE_IT(__HANDLE__, __INTERRUPT__)                      \
 408   (CLEAR_BIT((__HANDLE__)->Instance->CR1, (__INTERRUPT__)))
 409
 410 /** @brief  Checks if the specified ADC interrupt source is enabled or disabled.
 411   * @param __HANDLE__ ADC handle
 412   * @param __INTERRUPT__ ADC interrupt source to check
 413   *          This parameter can be any combination of the following values:
 414   *            @arg SDADC_IT_EOCAL: End of calibration interrupt enable
 415   *            @arg SDADC_IT_JEOC: Injected end of conversion interrupt enable
 416   *            @arg SDADC_IT_JOVR: Injected data overrun interrupt enable
 417   *            @arg SDADC_IT_REOC: Regular end of conversion interrupt enable
 418   *            @arg SDADC_IT_ROVR: Regular data overrun interrupt enable
 419   * @retval State of interruption (SET or RESET)
 420   */
 421 #define __HAL_SDADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__)                   \
 422   (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
 423
 424 /** @brief Get the selected ADC's flag status.
 425   * @param __HANDLE__ ADC handle
 426   * @param __FLAG__ ADC flag
 427   *          This parameter can be any combination of the following values:
 428   *            @arg SDADC_FLAG_EOCAL: End of calibration flag
 429   *            @arg SDADC_FLAG_JEOC: End of injected conversion flag
 430   *            @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
 431   *            @arg SDADC_FLAG_REOC: End of regular conversion flag
 432   *            @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
 433   * @retval None
 434   */
 435 #define __HAL_SDADC_GET_FLAG(__HANDLE__, __FLAG__)                             \
 436   ((((__HANDLE__)->Instance->ISR) & (__FLAG__)) == (__FLAG__))
 437
 438 /** @brief Clear the ADC's pending flags
 439   * @param __HANDLE__ ADC handle
 440   * @param __FLAG__ ADC flag
 441   *          This parameter can be any combination of the following values:
 442   *            @arg SDADC_FLAG_EOCAL: End of calibration flag
 443   *            @arg SDADC_FLAG_JEOC: End of injected conversion flag
 444   *            @arg SDADC_FLAG_JOVR: Injected conversion overrun flag
 445   *            @arg SDADC_FLAG_REOC: End of regular conversion flag
 446   *            @arg SDADC_FLAG_ROVR: Regular conversion overrun flag
 447   * @retval None
 448   */
 449 #define __HAL_SDADC_CLEAR_FLAG(__HANDLE__, __FLAG__)                           \
 450   (CLEAR_BIT((__HANDLE__)->Instance->ISR, (__FLAG__)))
 451
 452 /** @brief  Reset SDADC handle state
 453   * @param  __HANDLE__ SDADC handle.
 454   * @retval None
 455   */
 456 #define __HAL_SDADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDADC_STATE_RESET)
 457
 458 /**
 459   * @}
 460   */
 461
 462 /* Private macros ------------------------------------------------------------*/
 463 /** @defgroup SDADC_Private_Macros SDADC Private Macros
 464  * @{
 465  */
 466
 467 #define IS_SDADC_LOWPOWER_MODE(LOWPOWER)     (((LOWPOWER) == SDADC_LOWPOWER_NONE)      || \
 468                                               ((LOWPOWER) == SDADC_LOWPOWER_POWERDOWN) || \
 469                                               ((LOWPOWER) == SDADC_LOWPOWER_STANDBY))
 470
 471 #define IS_SDADC_FAST_CONV_MODE(FAST)        (((FAST) == SDADC_FAST_CONV_DISABLE) || \
 472                                               ((FAST) == SDADC_FAST_CONV_ENABLE))
 473
 474 #define IS_SDADC_SLOW_CLOCK_MODE(MODE)       (((MODE) == SDADC_SLOW_CLOCK_DISABLE) || \
 475                                               ((MODE) == SDADC_SLOW_CLOCK_ENABLE))
 476
 477 #define IS_SDADC_VREF(VREF)                  (((VREF) == SDADC_VREF_EXT)      || \
 478                                               ((VREF) == SDADC_VREF_VREFINT1) || \
 479                                               ((VREF) == SDADC_VREF_VREFINT2) || \
 480                                               ((VREF) == SDADC_VREF_VDDA))
 481
 482 #define IS_SDADC_CONF_INDEX(CONF) (((CONF) == SDADC_CONF_INDEX_0)  || \
 483                                    ((CONF) == SDADC_CONF_INDEX_1)  || \
 484                                    ((CONF) == SDADC_CONF_INDEX_2))
 485
 486 #define IS_SDADC_INPUT_MODE(MODE) (((MODE) == SDADC_INPUT_MODE_DIFF)     || \
 487                                    ((MODE) == SDADC_INPUT_MODE_SE_OFFSET) || \
 488                                    ((MODE) == SDADC_INPUT_MODE_SE_ZERO_REFERENCE))
 489
 490 #define IS_SDADC_GAIN(GAIN) (((GAIN) == SDADC_GAIN_1)  || \
 491                              ((GAIN) == SDADC_GAIN_2)  || \
 492                              ((GAIN) == SDADC_GAIN_4)  || \
 493                              ((GAIN) == SDADC_GAIN_8)  || \
 494                              ((GAIN) == SDADC_GAIN_16)  || \
 495                              ((GAIN) == SDADC_GAIN_32)  || \
 496                              ((GAIN) == SDADC_GAIN_1_2))
 497
 498 #define IS_SDADC_COMMON_MODE(MODE) (((MODE) == SDADC_COMMON_MODE_VSSA)   || \
 499                                     ((MODE) == SDADC_COMMON_MODE_VDDA_2) || \
 500                                     ((MODE) == SDADC_COMMON_MODE_VDDA))
 501
 502 #define IS_SDADC_OFFSET_VALUE(VALUE) ((VALUE) <= 0x00000FFFU)
 503
 504 /* Just one channel of the 9 channels can be selected for regular conversion */
 505 #define IS_SDADC_REGULAR_CHANNEL(CHANNEL) (((CHANNEL) == SDADC_CHANNEL_0)  || \
 506                                            ((CHANNEL) == SDADC_CHANNEL_1)  || \
 507                                            ((CHANNEL) == SDADC_CHANNEL_2)  || \
 508                                            ((CHANNEL) == SDADC_CHANNEL_3)  || \
 509                                            ((CHANNEL) == SDADC_CHANNEL_4)  || \
 510                                            ((CHANNEL) == SDADC_CHANNEL_5)  || \
 511                                            ((CHANNEL) == SDADC_CHANNEL_6)  || \
 512                                            ((CHANNEL) == SDADC_CHANNEL_7)  || \
 513                                            ((CHANNEL) == SDADC_CHANNEL_8))
 514
 515 /* Any or all of the 9 channels can be selected for injected conversion */
 516 #define IS_SDADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) != 0U) && ((CHANNEL) <= 0x000F01FFU))
 517
 518
 519 #define IS_SDADC_CALIB_SEQUENCE(SEQUENCE)  (((SEQUENCE) == SDADC_CALIBRATION_SEQ_1)  || \
 520                                             ((SEQUENCE) == SDADC_CALIBRATION_SEQ_2)  || \
 521                                             ((SEQUENCE) == SDADC_CALIBRATION_SEQ_3))
 522
 523 #define IS_SDADC_CONTINUOUS_MODE(MODE)       (((MODE) == SDADC_CONTINUOUS_CONV_OFF)  || \
 524                                              ((MODE) == SDADC_CONTINUOUS_CONV_ON))
 525
 526
 527 #define IS_SDADC_REGULAR_TRIGGER(TRIGGER)    (((TRIGGER) == SDADC_SOFTWARE_TRIGGER)  || \
 528                                              ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER))
 529
 530 #define IS_SDADC_INJECTED_TRIGGER(TRIGGER)   (((TRIGGER) == SDADC_SOFTWARE_TRIGGER)  || \
 531                                              ((TRIGGER) == SDADC_SYNCHRONOUS_TRIGGER)  || \
 532                                              ((TRIGGER) == SDADC_EXTERNAL_TRIGGER))
 533
 534
 535 #define IS_SDADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == SDADC_EXT_TRIG_TIM13_CC1) || \
 536                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM14_CC1) || \
 537                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM16_CC1) || \
 538                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM17_CC1) || \
 539                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC1) || \
 540                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM12_CC2)  || \
 541                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM15_CC2)  || \
 542                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC3)  || \
 543                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM2_CC4)  || \
 544                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC1)  || \
 545                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC2)  || \
 546                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM3_CC3) || \
 547                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC1) || \
 548                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC2) || \
 549                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM4_CC3) || \
 550                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC2) || \
 551                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC3) || \
 552                                           ((INJTRIG) == SDADC_EXT_TRIG_TIM19_CC4) || \
 553                                           ((INJTRIG) == SDADC_EXT_TRIG_EXTI11) || \
 554                                           ((INJTRIG) == SDADC_EXT_TRIG_EXTI15))
 555
 556 #define IS_SDADC_EXT_TRIG_EDGE(TRIGGER)      (((TRIGGER) == SDADC_EXT_TRIG_RISING_EDGE)  || \
 557                                              ((TRIGGER) == SDADC_EXT_TRIG_FALLING_EDGE)  || \
 558                                              ((TRIGGER) == SDADC_EXT_TRIG_BOTH_EDGES))
 559
 560
 561 #define IS_SDADC_INJECTED_DELAY(DELAY)       (((DELAY) == SDADC_INJECTED_DELAY_NONE) || \
 562                                              ((DELAY) == SDADC_INJECTED_DELAY))
 563
 564 #define IS_SDADC_MULTIMODE_TYPE(TYPE)        (((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC2) || \
 565                                              ((TYPE) == SDADC_MULTIMODE_SDADC1_SDADC3))
 566 /**
 567   * @}
 568   */
 569
 570 /* Exported functions --------------------------------------------------------*/
 571 /** @addtogroup SDADC_Exported_Functions SDADC Exported Functions
 572   * @{
 573   */
 574
 575 /** @addtogroup SDADC_Exported_Functions_Group1 Initialization and de-initialization functions
 576   * @{
 577   */
 578
 579 /* Initialization and de-initialization functions *****************************/
 580 HAL_StatusTypeDef HAL_SDADC_Init(SDADC_HandleTypeDef *hsdadc);
 581 HAL_StatusTypeDef HAL_SDADC_DeInit(SDADC_HandleTypeDef *hsdadc);
 582 void HAL_SDADC_MspInit(SDADC_HandleTypeDef* hsdadc);
 583 void HAL_SDADC_MspDeInit(SDADC_HandleTypeDef* hsdadc);
 584
 585 /**
 586   * @}
 587   */
 588
 589 /** @addtogroup SDADC_Exported_Functions_Group2 peripheral control functions
 590   * @{
 591   */
 592
 593 /* Peripheral Control functions ***********************************************/
 594 HAL_StatusTypeDef HAL_SDADC_PrepareChannelConfig(SDADC_HandleTypeDef *hsdadc,
 595                                                  uint32_t ConfIndex,
 596                                                  SDADC_ConfParamTypeDef* ConfParamStruct);
 597 HAL_StatusTypeDef HAL_SDADC_AssociateChannelConfig(SDADC_HandleTypeDef *hsdadc,
 598                                                    uint32_t Channel,
 599                                                    uint32_t ConfIndex);
 600 HAL_StatusTypeDef HAL_SDADC_ConfigChannel(SDADC_HandleTypeDef *hsdadc,
 601                                           uint32_t Channel,
 602                                           uint32_t ContinuousMode);
 603 HAL_StatusTypeDef HAL_SDADC_InjectedConfigChannel(SDADC_HandleTypeDef *hsdadc,
 604                                                   uint32_t Channel,
 605                                                   uint32_t ContinuousMode);
 606 HAL_StatusTypeDef HAL_SDADC_SelectInjectedExtTrigger(SDADC_HandleTypeDef *hsdadc,
 607                                                      uint32_t InjectedExtTrigger,
 608                                                      uint32_t ExtTriggerEdge);
 609 HAL_StatusTypeDef HAL_SDADC_SelectInjectedDelay(SDADC_HandleTypeDef *hsdadc,
 610                                                 uint32_t InjectedDelay);
 611 HAL_StatusTypeDef HAL_SDADC_SelectRegularTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
 612 HAL_StatusTypeDef HAL_SDADC_SelectInjectedTrigger(SDADC_HandleTypeDef *hsdadc, uint32_t Trigger);
 613 HAL_StatusTypeDef HAL_SDADC_MultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
 614 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeConfigChannel(SDADC_HandleTypeDef* hsdadc, uint32_t MultimodeType);
 615
 616 /**
 617   * @}
 618   */
 619
 620 /** @addtogroup SDADC_Exported_Functions_Group3 Input and Output operation functions
 621   * @{
 622   */
 623
 624 /* IO operation functions *****************************************************/
 625 HAL_StatusTypeDef HAL_SDADC_CalibrationStart(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
 626 HAL_StatusTypeDef HAL_SDADC_CalibrationStart_IT(SDADC_HandleTypeDef *hsdadc, uint32_t CalibrationSequence);
 627
 628 HAL_StatusTypeDef HAL_SDADC_Start(SDADC_HandleTypeDef *hsdadc);
 629 HAL_StatusTypeDef HAL_SDADC_Start_IT(SDADC_HandleTypeDef *hsdadc);
 630 HAL_StatusTypeDef HAL_SDADC_Start_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
 631 HAL_StatusTypeDef HAL_SDADC_Stop(SDADC_HandleTypeDef *hsdadc);
 632 HAL_StatusTypeDef HAL_SDADC_Stop_IT(SDADC_HandleTypeDef *hsdadc);
 633 HAL_StatusTypeDef HAL_SDADC_Stop_DMA(SDADC_HandleTypeDef *hsdadc);
 634
 635 HAL_StatusTypeDef HAL_SDADC_InjectedStart(SDADC_HandleTypeDef *hsdadc);
 636 HAL_StatusTypeDef HAL_SDADC_InjectedStart_IT(SDADC_HandleTypeDef *hsdadc);
 637 HAL_StatusTypeDef HAL_SDADC_InjectedStart_DMA(SDADC_HandleTypeDef *hsdadc, uint32_t *pData, uint32_t Length);
 638 HAL_StatusTypeDef HAL_SDADC_InjectedStop(SDADC_HandleTypeDef *hsdadc);
 639 HAL_StatusTypeDef HAL_SDADC_InjectedStop_IT(SDADC_HandleTypeDef *hsdadc);
 640 HAL_StatusTypeDef HAL_SDADC_InjectedStop_DMA(SDADC_HandleTypeDef *hsdadc);
 641
 642 HAL_StatusTypeDef HAL_SDADC_MultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
 643 HAL_StatusTypeDef HAL_SDADC_MultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
 644 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStart_DMA(SDADC_HandleTypeDef* hsdadc, uint32_t* pData, uint32_t Length);
 645 HAL_StatusTypeDef HAL_SDADC_InjectedMultiModeStop_DMA(SDADC_HandleTypeDef* hsdadc);
 646
 647 uint32_t HAL_SDADC_GetValue(SDADC_HandleTypeDef *hsdadc);
 648 uint32_t HAL_SDADC_InjectedGetValue(SDADC_HandleTypeDef *hsdadc, uint32_t* Channel);
 649 uint32_t HAL_SDADC_MultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
 650 uint32_t HAL_SDADC_InjectedMultiModeGetValue(SDADC_HandleTypeDef* hsdadc);
 651
 652 void HAL_SDADC_IRQHandler(SDADC_HandleTypeDef* hsdadc);
 653
 654 HAL_StatusTypeDef HAL_SDADC_PollForCalibEvent(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
 655 HAL_StatusTypeDef HAL_SDADC_PollForConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
 656 HAL_StatusTypeDef HAL_SDADC_PollForInjectedConversion(SDADC_HandleTypeDef* hsdadc, uint32_t Timeout);
 657
 658 void HAL_SDADC_CalibrationCpltCallback(SDADC_HandleTypeDef* hsdadc);
 659 void HAL_SDADC_ConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
 660 void HAL_SDADC_ConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
 661 void HAL_SDADC_InjectedConvHalfCpltCallback(SDADC_HandleTypeDef* hsdadc);
 662 void HAL_SDADC_InjectedConvCpltCallback(SDADC_HandleTypeDef* hsdadc);
 663 void HAL_SDADC_ErrorCallback(SDADC_HandleTypeDef* hsdadc);
 664
 665 /**
 666   * @}
 667   */
 668
 669 /** @defgroup SDADC_Exported_Functions_Group4 Peripheral State functions
 670   * @{
 671   */
 672
 673 /* Peripheral State and Error functions ***************************************/
 674 HAL_SDADC_StateTypeDef HAL_SDADC_GetState(SDADC_HandleTypeDef* hsdadc);
 675 uint32_t               HAL_SDADC_GetError(SDADC_HandleTypeDef* hsdadc);
 676
 677 /* Private functions ---------------------------------------------------------*/
 678
 679 /**
 680   * @}
 681   */
 682
 683 /**
 684   * @}
 685   */
 686
 687 /**
 688   * @}
 689   */
 690
 691 /**
 692   * @}
 693   */
 694
 695 #endif /* defined(STM32F373xC) || defined(STM32F378xx) */
 696
 697 #ifdef __cplusplus
 698 }
 699 #endif
 700
 701 #endif /*__STM32F3xx_SDADC_H */
 702
 703
 704 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/