lib/main/STM32F3/Drivers/STM32F3xx_HAL_Driver/Inc/stm32f3xx_hal_nor.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f3xx_hal_nor.h
   4   * @author  MCD Application Team
   5   * @brief   Header file of NOR HAL module.
   6   ******************************************************************************
   7   * @attention
   8   *
   9   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  10   *
  11   * Redistribution and use in source and binary forms, with or without modification,
  12   * are permitted provided that the following conditions are met:
  13   *   1. Redistributions of source code must retain the above copyright notice,
  14   *      this list of conditions and the following disclaimer.
  15   *   2. Redistributions in binary form must reproduce the above copyright notice,
  16   *      this list of conditions and the following disclaimer in the documentation
  17   *      and/or other materials provided with the distribution.
  18   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  19   *      may be used to endorse or promote products derived from this software
  20   *      without specific prior written permission.
  21   *
  22   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  23   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  24   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  25   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  26   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  27   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  28   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  29   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  30   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  31   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  32   *
  33   ******************************************************************************
  34   */
  35
  36 /* Define to prevent recursive inclusion -------------------------------------*/
  37 #ifndef __STM32F3xx_HAL_NOR_H
  38 #define __STM32F3xx_HAL_NOR_H
  39
  40 #ifdef __cplusplus
  41  extern "C" {
  42 #endif
  43
  44 /* Includes ------------------------------------------------------------------*/
  45 #if defined(STM32F302xE) || defined(STM32F303xE) || defined(STM32F398xx)
  46 #include "stm32f3xx_ll_fmc.h"
  47
  48 /** @addtogroup STM32F3xx_HAL_Driver
  49   * @{
  50   */
  51
  52 /** @addtogroup NOR
  53   * @{
  54   */
  55
  56
  57 /** @addtogroup NOR_Private_Constants
  58   * @{
  59   */
  60
  61 /* NOR device IDs addresses */
  62 #define MC_ADDRESS               ((uint16_t)0x0000U)
  63 #define DEVICE_CODE1_ADDR        ((uint16_t)0x0001U)
  64 #define DEVICE_CODE2_ADDR        ((uint16_t)0x000EU)
  65 #define DEVICE_CODE3_ADDR        ((uint16_t)0x000FU)
  66
  67 /* NOR CFI IDs addresses */
  68 #define CFI1_ADDRESS             ((uint16_t)0x10U)
  69 #define CFI2_ADDRESS             ((uint16_t)0x11U)
  70 #define CFI3_ADDRESS             ((uint16_t)0x12U)
  71 #define CFI4_ADDRESS             ((uint16_t)0x13U)
  72
  73 /* NOR memory data width */
  74 #define NOR_MEMORY_8B            ((uint8_t)0x0U)
  75 #define NOR_MEMORY_16B           ((uint8_t)0x1U)
  76
  77 /* NOR memory device read/write start address */
  78 #define NOR_MEMORY_ADRESS1       FMC_BANK1_1
  79 #define NOR_MEMORY_ADRESS2       FMC_BANK1_2
  80 #define NOR_MEMORY_ADRESS3       FMC_BANK1_3
  81 #define NOR_MEMORY_ADRESS4       FMC_BANK1_4
  82
  83 /**
  84   * @}
  85   */
  86
  87 /** @addtogroup NOR_Private_Macros
  88   * @{
  89   */
  90
  91 /**
  92   * @brief  NOR memory address shifting.
  93   * @param  __NOR_ADDRESS NOR base address
  94   * @param  __NOR_MEMORY_WIDTH_ NOR memory width
  95   * @param  __ADDRESS__ NOR memory address
  96   * @retval NOR shifted address value
  97   */
  98 #define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__)       \
  99             ((uint32_t)(((__NOR_MEMORY_WIDTH_) == NOR_MEMORY_16B)?              \
 100               ((uint32_t)((__NOR_ADDRESS) + (2U * (__ADDRESS__)))):              \
 101               ((uint32_t)((__NOR_ADDRESS) + (__ADDRESS__)))))
 102
 103 /**
 104   * @brief  NOR memory write data to specified address.
 105   * @param  __ADDRESS__ NOR memory address
 106   * @param  __DATA__ Data to write
 107   * @retval None
 108   */
 109 #define NOR_WRITE(__ADDRESS__, __DATA__)  (*(__IO uint16_t *)((uint32_t)(__ADDRESS__)) = (__DATA__))
 110
 111 /**
 112   * @}
 113   */
 114
 115 /* Exported typedef ----------------------------------------------------------*/
 116 /** @defgroup NOR_Exported_Types NOR Exported Types
 117   * @{
 118   */
 119
 120 /**
 121   * @brief  HAL SRAM State structures definition
 122   */
 123 typedef enum
 124 {
 125   HAL_NOR_STATE_RESET             = 0x00U,  /*!< NOR not yet initialized or disabled  */
 126   HAL_NOR_STATE_READY             = 0x01U,  /*!< NOR initialized and ready for use    */
 127   HAL_NOR_STATE_BUSY              = 0x02U,  /*!< NOR internal processing is ongoing   */
 128   HAL_NOR_STATE_ERROR             = 0x03U,  /*!< NOR error state                      */
 129   HAL_NOR_STATE_PROTECTED         = 0x04   /*!< NOR NORSRAM device write protected  */
 130 }HAL_NOR_StateTypeDef;
 131
 132 /**
 133   * @brief  FMC NOR Status typedef
 134   */
 135 typedef enum
 136 {
 137   HAL_NOR_STATUS_SUCCESS = 0U,
 138   HAL_NOR_STATUS_ONGOING,
 139   HAL_NOR_STATUS_ERROR,
 140   HAL_NOR_STATUS_TIMEOUT
 141 }HAL_NOR_StatusTypeDef;
 142
 143 /**
 144   * @brief  FMC NOR ID typedef
 145   */
 146 typedef struct
 147 {
 148   uint16_t Manufacturer_Code;  /*!< Defines the device's manufacturer code used to identify the memory       */
 149
 150   uint16_t Device_Code1;
 151
 152   uint16_t Device_Code2;
 153
 154   uint16_t Device_Code3;       /*!< Defines the device's codes used to identify the memory.
 155                                     These codes can be accessed by performing read operations with specific
 156                                     control signals and addresses set.They can also be accessed by issuing
 157                                     an Auto Select command.                                                   */
 158 }NOR_IDTypeDef;
 159
 160 /**
 161   * @brief  FMC NOR CFI typedef
 162   */
 163 typedef struct
 164 {
 165   uint16_t CFI_1;
 166
 167   uint16_t CFI_2;
 168
 169   uint16_t CFI_3;
 170
 171   uint16_t CFI_4;  /*!< Defines the information stored in the memory's Common flash interface
 172                         which contains a description of various electrical and timing parameters,
 173                         density information and functions supported by the memory.                   */
 174 }NOR_CFITypeDef;
 175
 176 /**
 177   * @brief  NOR handle Structure definition
 178   */
 179 typedef struct
 180 {
 181   FMC_NORSRAM_TypeDef           *Instance;    /*!< Register base address                        */
 182
 183   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;    /*!< Extended mode register base address          */
 184
 185   FMC_NORSRAM_InitTypeDef       Init;         /*!< NOR device control configuration parameters  */
 186
 187   HAL_LockTypeDef               Lock;         /*!< NOR locking object                           */
 188
 189   __IO HAL_NOR_StateTypeDef     State;        /*!< NOR device access state                      */
 190
 191 }NOR_HandleTypeDef;
 192
 193 /**
 194   * @}
 195   */
 196
 197 /* Exported constants --------------------------------------------------------*/
 198 /* Exported macro ------------------------------------------------------------*/
 199 /** @defgroup NOR_Exported_Macros NOR Exported Macros
 200   * @{
 201   */
 202
 203 /** @brief Reset NOR handle state
 204   * @param  __HANDLE__ NOR handle
 205   * @retval None
 206   */
 207 #define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
 208
 209 /**
 210   * @}
 211   */
 212
 213 /* Exported functions --------------------------------------------------------*/
 214 /** @addtogroup NOR_Exported_Functions NOR Exported Functions
 215   * @{
 216   */
 217
 218 /** @addtogroup NOR_Exported_Functions_Group1 Initialization and de-initialization functions
 219   * @{
 220   */
 221
 222 /* Initialization/de-initialization functions  ********************************/
 223 HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
 224 HAL_StatusTypeDef HAL_NOR_DeInit(NOR_HandleTypeDef *hnor);
 225 void HAL_NOR_MspInit(NOR_HandleTypeDef *hnor);
 226 void HAL_NOR_MspDeInit(NOR_HandleTypeDef *hnor);
 227 void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout);
 228
 229 /**
 230   * @}
 231   */
 232
 233 /** @addtogroup NOR_Exported_Functions_Group2 Input and Output functions
 234   * @{
 235   */
 236
 237 /* I/O operation functions  ***************************************************/
 238 HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID);
 239 HAL_StatusTypeDef HAL_NOR_ReturnToReadMode(NOR_HandleTypeDef *hnor);
 240 HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
 241 HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData);
 242
 243 HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
 244 HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize);
 245
 246 HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address);
 247 HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address);
 248 HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI);
 249
 250 /**
 251   * @}
 252   */
 253
 254 /** @addtogroup NOR_Exported_Functions_Group3 Peripheral Control functions
 255   * @{
 256   */
 257
 258 /* NOR Control functions  *****************************************************/
 259 HAL_StatusTypeDef HAL_NOR_WriteOperation_Enable(NOR_HandleTypeDef *hnor);
 260 HAL_StatusTypeDef HAL_NOR_WriteOperation_Disable(NOR_HandleTypeDef *hnor);
 261
 262 /**
 263   * @}
 264   */
 265
 266 /** @addtogroup NOR_Exported_Functions_Group4 Peripheral State functions
 267   * @{
 268   */
 269
 270 /* NOR State functions ********************************************************/
 271 HAL_NOR_StateTypeDef HAL_NOR_GetState(NOR_HandleTypeDef *hnor);
 272 HAL_NOR_StatusTypeDef HAL_NOR_GetStatus(NOR_HandleTypeDef *hnor, uint32_t Address, uint32_t Timeout);
 273
 274 /**
 275   * @}
 276   */
 277
 278 /**
 279   * @}
 280   */
 281
 282 /**
 283   * @}
 284   */
 285
 286 /**
 287   * @}
 288   */
 289
 290 #endif /* STM32F302xE || STM32F303xE || STM32F398xx */
 291
 292 #ifdef __cplusplus
 293 }
 294 #endif
 295
 296 #endif /* __STM32F3xx_HAL_NOR_H */
 297
 298 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/