[betaflight.git] / lib / main / STM32F3 / Drivers / STM32F3xx_HAL_Driver / Inc / stm32f3xx_hal_hrtim.h
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1 /**
2 ******************************************************************************
3 * @file stm32f3xx_hal_hrtim.h
4 * @author MCD Application Team
5 * @brief Header file of HRTIM HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
10 *
11 * Redistribution and use in source and binary forms, with or without modification,
12 * are permitted provided that the following conditions are met:
13 * 1. Redistributions of source code must retain the above copyright notice,
14 * this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright notice,
16 * this list of conditions and the following disclaimer in the documentation
17 * and/or other materials provided with the distribution.
18 * 3. Neither the name of STMicroelectronics nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
25 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
28 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
29 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
30 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
31 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 *
33 ******************************************************************************
34 */
36 /* Define to prevent recursive inclusion -------------------------------------*/
37 #ifndef __STM32F3xx_HAL_HRTIM_H
38 #define __STM32F3xx_HAL_HRTIM_H
40 #ifdef __cplusplus
42 #endif
44 #if defined(STM32F334x8)
46 /* Includes ------------------------------------------------------------------*/
49 /** @addtogroup STM32F3xx_HAL_Driver
50 * @{
51 */
53 /** @addtogroup HRTIM HRTIM
54 * @{
55 */
57 /* Exported types ------------------------------------------------------------*/
58 /** @addtogroup HRTIM_Exported_Constants HRTIM Exported Constants
59 * @{
60 */
61 /** @defgroup HRTIM_Max_Timer HRTIM Max Timer
62 * @{
63 */
64 #define MAX_HRTIM_TIMER 6U
65 /**
66 * @}
67 */
68 /**
69 * @}
70 */
72 /** @defgroup HRTIM_Exported_Types HRTIM Exported Types
73 * @{
74 */
76 /**
77 * @brief HRTIM Configuration Structure definition - Time base related parameters
78 */
80 {
81 uint32_t HRTIMInterruptResquests; /*!< Specifies which interrupts requests must enabled for the HRTIM instance.
82 This parameter can be any combination of @ref HRTIM_Common_Interrupt_Enable */
83 uint32_t SyncOptions; /*!< Specifies how the HRTIM instance handles the external synchronization signals.
84 The HRTIM instance can be configured to act as a slave (waiting for a trigger
85 to be synchronized) or a master (generating a synchronization signal) or both.
86 This parameter can be a combination of @ref HRTIM_Synchronization_Options.*/
87 uint32_t SyncInputSource; /*!< Specifies the external synchronization input source (significant only when
88 the HRTIM instance is configured as a slave).
89 This parameter can be a value of @ref HRTIM_Synchronization_Input_Source. */
90 uint32_t SyncOutputSource; /*!< Specifies the source and event to be sent on the external synchronization outputs
91 (significant only when the HRTIM instance is configured as a master).
92 This parameter can be a value of @ref HRTIM_Synchronization_Output_Source */
93 uint32_t SyncOutputPolarity; /*!< Specifies the conditioning of the event to be sent on the external synchronization
94 outputs (significant only when the HRTIM instance is configured as a master).
95 This parameter can be a value of @ref HRTIM_Synchronization_Output_Polarity */
98 /**
99 * @brief HAL State structures definition
100 */
102 {
109 /**
110 * @brief HRTIM Timer Structure definition
111 */
113 {
115 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
116 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
118 When the timer operates in Simple mode, this parameter can be a value of @ref HRTIM_External_Event_Channels.
119 When the timer operates in Waveform mode, this parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger. */
127 /**
128 * @brief HRTIM Handle Structure definition
129 */
131 {
136 HRTIM_TimerParamTypeDef TimerParam[MAX_HRTIM_TIMER]; /*!< HRTIM timers - including the master - parameters */
150 /**
151 * @brief Simple output compare mode configuration definition
152 */
155 The period value must be above 3 periods of the fHRTIM clock.
156 Maximum value is = 0xFFDFU */
158 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
160 This parameter can be any value of @ref HRTIM_Prescaler_Ratio */
162 This parameter can be any value of @ref HRTIM_Counter_Operating_Mode */
165 /**
166 * @brief Simple output compare mode configuration definition
167 */
170 This parameter can be any value of of @ref HRTIM_Simple_OC_Mode */
172 The compare value must be above or equal to 3 periods of the fHRTIM clock */
174 This parameter can be any value of @ref HRTIM_Output_Polarity */
175 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
176 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
179 /**
180 * @brief Simple PWM output mode configuration definition
181 */
184 The compare value must be above or equal to 3 periods of the fHRTIM clock */
186 This parameter can be any value of @ref HRTIM_Output_Polarity */
187 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
188 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
191 /**
192 * @brief Simple capture mode configuration definition
193 */
196 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
197 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
198 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
200 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
201 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
202 This parameter can be a value of @ref HRTIM_External_Event_Filter */
205 /**
206 * @brief Simple One Pulse mode configuration definition
207 */
210 The compare value must be above or equal to 3 periods of the fHRTIM clock */
212 This parameter can be any value of @ref HRTIM_Output_Polarity */
213 uint32_t OutputIdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
214 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
216 This parameter can be any 'EEVx' value of @ref HRTIM_External_Event_Channels */
217 uint32_t EventPolarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
218 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
220 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity. */
221 uint32_t EventFilter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
222 This parameter can be a value of @ref HRTIM_External_Event_Filter */
225 /**
226 * @brief Timer configuration definition
227 */
230 Specifies which interrupts requests must enabled for the timer.
231 This parameter can be any combination of @ref HRTIM_Master_Interrupt_Enable
232 or @ref HRTIM_Timing_Unit_Interrupt_Enable */
234 Specifies which DMA requests must be enabled for the timer.
235 This parameter can be any combination of @ref HRTIM_Master_DMA_Request_Enable
236 or @ref HRTIM_Timing_Unit_DMA_Request_Enable */
238 Specifies the address of the source address of the DMA transfer */
240 Specifies the address of the destination address of the DMA transfer */
242 Specifies the size of the DMA transfer */
244 Specifies whether or not hald mode is enabled
245 This parameter can be any value of @ref HRTIM_Half_Mode_Enable */
247 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
248 This parameter can be any value of @ref HRTIM_Start_On_Sync_Input_Event */
250 Specifies whether or not timer is reset by a rising edge on the synchronization input (when enabled).
251 This parameter can be any value of @ref HRTIM_Reset_On_Sync_Input_Event */
253 Indicates whether or not the a DAC synchronization event is generated.
254 This parameter can be any value of @ref HRTIM_DAC_Synchronization */
256 Specifies whether or not register preload is enabled.
257 This parameter can be any value of @ref HRTIM_Register_Preload_Enable */
259 Specifies how the update occurs with respect to a burst DMA transaction or
260 update enable inputs (Slave timers only).
261 This parameter can be any value of @ref HRTIM_Update_Gating */
263 Specifies how the timer behaves during a burst mode operation.
264 This parameter can be any value of @ref HRTIM_Timer_Burst_Mode */
266 Specifies whether or not registers update is triggered by the repetition event.
267 This parameter can be any value of @ref HRTIM_Timer_Repetition_Update */
269 Specifies whether or not the push-pull mode is enabled.
270 This parameter can be any value of @ref HRTIM_Timer_Push_Pull_Mode */
272 Specifies which fault channels are enabled for the timer.
273 This parameter can be a combination of @ref HRTIM_Timer_Fault_Enabling */
275 Specifies whether or not fault enabling status is write protected.
276 This parameter can be a value of @ref HRTIM_Timer_Fault_Lock */
278 Specifies whether or not dead-time insertion is enabled for the timer.
279 This parameter can be a value of @ref HRTIM_Timer_Deadtime_Insertion */
281 Specifies the delayed protection mode.
282 This parameter can be a value of @ref HRTIM_Timer_Delayed_Protection_Mode */
284 Specifies source(s) triggering the timer registers update.
285 This parameter can be a combination of @ref HRTIM_Timer_Update_Trigger */
287 Specifies source(s) triggering the timer counter reset.
288 This parameter can be a combination of @ref HRTIM_Timer_Reset_Trigger */
290 Specifies whether or not registers update is triggered when the timer counter is reset.
291 This parameter can be a value of @ref HRTIM_Timer_Reset_Update */
294 /**
295 * @brief Compare unit configuration definition
296 */
299 The minimum value must be greater than or equal to 3 periods of the fHRTIM clock.
300 The maximum value must be less than or equal to 0xFFFFU - 1 periods of the fHRTIM clock */
302 This parameter can be a value of @ref HRTIM_Compare_Unit_Auto_Delayed_Mode */
303 uint32_t AutoDelayedTimeout; /*!< Specifies compare value for timing unit 1 or 3 when auto delayed mode with time out is selected.
304 CompareValue + AutoDelayedTimeout must be less than 0xFFFFU */
307 /**
308 * @brief Capture unit configuration definition
309 */
312 This parameter can be a combination of @ref HRTIM_Capture_Unit_Trigger */
315 /**
316 * @brief Output configuration definition
317 */
320 This parameter can be any value of @ref HRTIM_Output_Polarity */
321 uint32_t SetSource; /*!< Specifies the event(s) transitioning the output from its inactive level to its active level.
322 This parameter can be a combination of @ref HRTIM_Output_Set_Source */
323 uint32_t ResetSource; /*!< Specifies the event(s) transitioning the output from its active level to its inactive level.
324 This parameter can be a combination of @ref HRTIM_Output_Reset_Source */
325 uint32_t IdleMode; /*!< Specifies whether or not the output is affected by a burst mode operation.
326 This parameter can be any value of @ref HRTIM_Output_Idle_Mode */
327 uint32_t IdleLevel; /*!< Specifies whether the output level is active or inactive when in IDLE state.
328 This parameter can be any value of @ref HRTIM_Output_IDLE_Level */
329 uint32_t FaultLevel; /*!< Specifies whether the output level is active or inactive when in FAULT state.
330 This parameter can be any value of @ref HRTIM_Output_FAULT_Level */
332 This parameter can be any value of @ref HRTIM_Output_Chopper_Mode_Enable */
333 uint32_t BurstModeEntryDelayed; /*!< Indicates whether or not dead-time is inserted when entering the IDLE state during a burst mode operation.
334 This parameters can be any value of @ref HRTIM_Output_Burst_Mode_Entry_Delayed */
337 /**
338 * @brief External event filtering in timing units configuration definition
339 */
342 This parameter can be a value of @ref HRTIM_Timer_External_Event_Filter */
344 This parameter can be a value of @ref HRTIM_Timer_External_Event_Latch */
347 /**
348 * @brief Dead time feature configuration definition
349 */
352 This parameter can be a value of @ref HRTIM_Deadtime_Prescaler_Ratio */
354 This parameter can be a number between 0x0 and 0x1FFU */
355 uint32_t RisingSign; /*!< Specifies whether the deadtime is positive or negative on rising edge.
356 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign */
357 uint32_t RisingLock; /*!< Specifies whether or not deadtime rising settings (value and sign) are write protected.
358 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Lock */
360 This parameter can be a value of @ref HRTIM_Deadtime_Rising_Sign_Lock */
362 This parameter can be a number between 0x0 and 0x1FFU */
363 uint32_t FallingSign; /*!< Specifies whether the deadtime is positive or negative on falling edge.
364 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign */
365 uint32_t FallingLock; /*!< Specifies whether or not deadtime falling settings (value and sign) are write protected.
366 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Lock */
367 uint32_t FallingSignLock; /*!< Specifies whether or not deadtime falling sign is write protected.
368 This parameter can be a value of @ref HRTIM_Deadtime_Falling_Sign_Lock */
371 /**
372 * @brief Chopper mode configuration definition
373 */
376 This parameter can be a value of @ref HRTIM_Chopper_Frequency */
378 This parameter can be a value of @ref HRTIM_Chopper_Duty_Cycle */
380 This parameter can be a value of @ref HRTIM_Chopper_Start_Pulse_Width */
383 /**
384 * @brief External event channel configuration definition
385 */
388 This parameter can be a value of @ref HRTIM_External_Event_Sources */
389 uint32_t Polarity; /*!< Specifies the polarity of the external event (in case of level sensitivity).
390 This parameter can be a value of @ref HRTIM_External_Event_Polarity */
392 This parameter can be a value of @ref HRTIM_External_Event_Sensitivity */
393 uint32_t Filter; /*!< Defines the frequency used to sample the External Event and the length of the digital filter.
394 This parameter can be a value of @ref HRTIM_External_Event_Filter */
395 uint32_t FastMode; /*!< Indicates whether or not low latency mode is enabled for the external event.
396 This parameter can be a value of @ref HRTIM_External_Event_Fast_Mode */
399 /**
400 * @brief Fault channel configuration definition
401 */
404 This parameter can be a value of @ref HRTIM_Fault_Sources */
406 This parameter can be a value of @ref HRTIM_Fault_Polarity */
407 uint32_t Filter; /*!< Defines the frequency used to sample the Fault input and the length of the digital filter.
408 This parameter can be a value of @ref HRTIM_Fault_Filter */
410 This parameter can be a value of @ref HRTIM_Fault_Lock */
413 /**
414 * @brief Burst mode configuration definition
415 */
418 This parameter can be a value of @ref HRTIM_Burst_Mode_Operating_Mode */
420 This parameter can be a value of @ref HRTIM_Burst_Mode_Clock_Source */
422 This parameter can be a value of @ref HRTIM_Burst_Mode_Prescaler */
423 uint32_t PreloadEnable; /*!< Specifies whether or not preload is enabled for burst mode related registers (HRTIM_BMCMPR and HRTIM_BMPER).
424 This parameter can be a combination of @ref HRTIM_Burst_Mode_Register_Preload_Enable */
426 This parameter can be a combination of @ref HRTIM_Burst_Mode_Trigger */
427 uint32_t IdleDuration; /*!< Specifies number of periods during which the selected timers are in idle state.
428 This parameter can be a number between 0x0 and 0xFFFF */
430 This parameter can be a number between 0x1 and 0xFFFF */
433 /**
434 * @brief ADC trigger configuration definition
435 */
438 This parameter can be a combination of @ref HRTIM_ADC_Trigger_Update_Source */
440 This parameter can be a value of @ref HRTIM_ADC_Trigger_Event */
443 /**
444 * @}
445 */
447 /* Exported constants --------------------------------------------------------*/
448 /** @defgroup HRTIM_Exported_Constants HRTIM Exported Constants
449 * @{
450 */
452 /** @defgroup HRTIM_Timer_Index HRTIM Timer Index
453 * @{
454 * @brief Constants defining the timer indexes
455 */
463 /**
464 * @}
465 */
467 /** @defgroup HRTIM_Timer_identifier HRTIM Timer identifier
468 * @{
469 * @brief Constants defining timer identifiers
470 */
477 /**
478 * @}
479 */
481 /** @defgroup HRTIM_Compare_Unit HRTIM Compare Unit
482 * @{
483 * @brief Constants defining compare unit identifiers
484 */
489 /**
490 * @}
491 */
493 /** @defgroup HRTIM_Capture_Unit HRTIM Capture Unit
494 * @{
495 * @brief Constants defining capture unit identifiers
496 */
499 /**
500 * @}
501 */
503 /** @defgroup HRTIM_Timer_Output HRTIM Timer Output
504 * @{
505 * @brief Constants defining timer output identifiers
506 */
517 /**
518 * @}
519 */
521 /** @defgroup HRTIM_ADC_Trigger HRTIM ADC Trigger
522 * @{
523 * @brief Constants defining ADC triggers identifiers
524 */
530 #define IS_HRTIM_ADCTRIGGER(ADCTRIGGER)\
531 (((ADCTRIGGER) == HRTIM_ADCTRIGGER_1) || \
532 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_2) || \
533 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_3) || \
534 ((ADCTRIGGER) == HRTIM_ADCTRIGGER_4))
535 /**
536 * @}
537 */
539 /** @defgroup HRTIM_External_Event_Channels HRTIM External Event Channels
540 * @{
541 * @brief Constants defining external event channel identifiers
542 */
554 /**
555 * @}
556 */
558 /** @defgroup HRTIM_Fault_Channel HRTIM Fault Channel
559 * @{
560 * @brief Constants defining fault channel identifiers
561 */
567 /**
568 * @}
569 */
572 /** @defgroup HRTIM_Prescaler_Ratio HRTIM Prescaler Ratio
573 * @{
574 * @brief Constants defining timer high-resolution clock prescaler ratio.
575 */
576 #define HRTIM_PRESCALERRATIO_MUL32 (0x00000000U) /*!< fHRCK: fHRTIM x 32U = 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz) */
577 #define HRTIM_PRESCALERRATIO_MUL16 (0x00000001U) /*!< fHRCK: fHRTIM x 16U = 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz) */
578 #define HRTIM_PRESCALERRATIO_MUL8 (0x00000002U) /*!< fHRCK: fHRTIM x 8U = 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz) */
579 #define HRTIM_PRESCALERRATIO_MUL4 (0x00000003U) /*!< fHRCK: fHRTIM x 4U = 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz) */
580 #define HRTIM_PRESCALERRATIO_MUL2 (0x00000004U) /*!< fHRCK: fHRTIM x 2U = 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz) */
581 #define HRTIM_PRESCALERRATIO_DIV1 (0x00000005U) /*!< fHRCK: fHRTIM = 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz) */
582 #define HRTIM_PRESCALERRATIO_DIV2 (0x00000006U) /*!< fHRCK: fHRTIM / 2U = 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz) */
583 #define HRTIM_PRESCALERRATIO_DIV4 (0x00000007U) /*!< fHRCK: fHRTIM / 4U = 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz) */
584 /**
585 * @}
586 */
588 /** @defgroup HRTIM_Counter_Operating_Mode HRTIM Counter Operating Mode
589 * @{
590 * @brief Constants defining timer counter operating mode.
591 */
592 #define HRTIM_MODE_CONTINUOUS (0x00000008U) /*!< The timer operates in continuous (free-running) mode */
593 #define HRTIM_MODE_SINGLESHOT (0x00000000U) /*!< The timer operates in non retriggerable single-shot mode */
594 #define HRTIM_MODE_SINGLESHOT_RETRIGGERABLE (0x00000010U) /*!< The timer operates in retriggerable single-shot mode */
595 /**
596 * @}
597 */
599 /** @defgroup HRTIM_Half_Mode_Enable HRTIM Half Mode Enable
600 * @{
601 * @brief Constants defining half mode enabling status.
602 */
605 /**
606 * @}
607 */
609 /** @defgroup HRTIM_Start_On_Sync_Input_Event HRTIM Start On Sync Input Event
610 * @{
611 * @brief Constants defining the timer behavior following the synchronization event
612 */
613 #define HRTIM_SYNCSTART_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
614 #define HRTIM_SYNCSTART_ENABLED (HRTIM_MCR_SYNCSTRTM) /*!< Synchronization input event starts the timer */
615 /**
616 * @}
617 */
619 /** @defgroup HRTIM_Reset_On_Sync_Input_Event HRTIM Reset On Sync Input Event
620 * @{
621 * @brief Constants defining the timer behavior following the synchronization event
622 */
623 #define HRTIM_SYNCRESET_DISABLED (0x00000000U) /*!< Synchronization input event has effect on the timer */
624 #define HRTIM_SYNCRESET_ENABLED (HRTIM_MCR_SYNCRSTM) /*!< Synchronization input event resets the timer */
625 /**
626 * @}
627 */
629 /** @defgroup HRTIM_DAC_Synchronization HRTIM DAC Synchronization
630 * @{
631 * @brief Constants defining on which output the DAC synchronization event is sent
632 */
634 #define HRTIM_DACSYNC_DACTRIGOUT_1 (HRTIM_MCR_DACSYNC_0) /*!< DAC synchronization event generated on DACTrigOut1 output upon timer update */
635 #define HRTIM_DACSYNC_DACTRIGOUT_2 (HRTIM_MCR_DACSYNC_1) /*!< DAC synchronization event generated on DACTrigOut2 output upon timer update */
636 #define HRTIM_DACSYNC_DACTRIGOUT_3 (HRTIM_MCR_DACSYNC_1 | HRTIM_MCR_DACSYNC_0) /*!< DAC update generated on DACTrigOut3 output upon timer update */
637 /**
638 * @}
639 */
641 /** @defgroup HRTIM_Register_Preload_Enable HRTIM Register Preload Enable
642 * @{
643 * @brief Constants defining whether a write access into a preloadable
644 * register is done into the active or the preload register.
645 */
646 #define HRTIM_PRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into the active register */
647 #define HRTIM_PRELOAD_ENABLED (HRTIM_MCR_PREEN) /*!< Preload enabled: the write access is done into the preload register */
648 /**
649 * @}
650 */
652 /** @defgroup HRTIM_Update_Gating HRTIM Update Gating
653 * @{
654 * @brief Constants defining how the update occurs relatively to the burst DMA
655 * transaction and the external update request on update enable inputs 1 to 3.
656 */
657 #define HRTIM_UPDATEGATING_INDEPENDENT 0x00000000U /*!< Update done independently from the DMA burst transfer completion */
658 #define HRTIM_UPDATEGATING_DMABURST (HRTIM_TIMCR_UPDGAT_0) /*!< Update done when the DMA burst transfer is completed */
659 #define HRTIM_UPDATEGATING_DMABURST_UPDATE (HRTIM_TIMCR_UPDGAT_1) /*!< Update done on timer roll-over following a DMA burst transfer completion*/
660 #define HRTIM_UPDATEGATING_UPDEN1 (HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 1U */
661 #define HRTIM_UPDATEGATING_UPDEN2 (HRTIM_TIMCR_UPDGAT_2) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 2U */
662 #define HRTIM_UPDATEGATING_UPDEN3 (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on a rising edge of HRTIM update enable input 3U */
663 #define HRTIM_UPDATEGATING_UPDEN1_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 1U */
664 #define HRTIM_UPDATEGATING_UPDEN2_UPDATE (HRTIM_TIMCR_UPDGAT_2 | HRTIM_TIMCR_UPDGAT_1 | HRTIM_TIMCR_UPDGAT_0) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 2U */
665 #define HRTIM_UPDATEGATING_UPDEN3_UPDATE (HRTIM_TIMCR_UPDGAT_3) /*!< Slave timer only - Update done on the update event following a rising edge of HRTIM update enable input 3U */
666 /**
667 * @}
668 */
670 /** @defgroup HRTIM_Timer_Burst_Mode HRTIM Timer Burst Mode
671 * @{
672 * @brief Constants defining how the timer behaves during a burst
673 mode operation.
674 */
675 #define HRTIM_TIMERBURSTMODE_MAINTAINCLOCK 0x000000U /*!< Timer counter clock is maintained and the timer operates normally */
676 #define HRTIM_TIMERBURSTMODE_RESETCOUNTER (HRTIM_BMCR_MTBM) /*!< Timer counter clock is stopped and the counter is reset */
677 /**
678 * @}
679 */
681 /** @defgroup HRTIM_Timer_Repetition_Update HRTIM Timer Repetition Update
682 * @{
683 * @brief Constants defining whether registers are updated when the timer
684 * repetition period is completed (either due to roll-over or
685 * reset events)
686 */
689 /**
690 * @}
691 */
694 /** @defgroup HRTIM_Timer_Push_Pull_Mode HRTIM Timer Push Pull Mode
695 * @{
696 * @brief Constants defining whether or not the puhs-pull mode is enabled for
697 * a timer.
698 */
700 #define HRTIM_TIMPUSHPULLMODE_ENABLED ((uint32_t)HRTIM_TIMCR_PSHPLL) /*!< Push-Pull mode enabled */
701 /**
702 * @}
703 */
705 /** @defgroup HRTIM_Timer_Fault_Enabling HRTIM Timer Fault Enabling
706 * @{
707 * @brief Constants defining whether a faut channel is enabled for a timer
708 */
715 /**
716 * @}
717 */
719 /** @defgroup HRTIM_Timer_Fault_Lock HRTIM Timer Fault Lock
720 * @{
721 * @brief Constants defining whether or not fault enabling bits are write
722 * protected for a timer
723 */
724 #define HRTIM_TIMFAULTLOCK_READWRITE (0x00000000U) /*!< Timer fault enabling bits are read/write */
725 #define HRTIM_TIMFAULTLOCK_READONLY (HRTIM_FLTR_FLTLCK) /*!< Timer fault enabling bits are read only */
726 /**
727 * @}
728 */
730 /** @defgroup HRTIM_Timer_Deadtime_Insertion HRTIM Timer Deadtime Insertion
731 * @{
732 * @brief Constants defining whether or not fault the dead time insertion
733 * feature is enabled for a timer
734 */
735 #define HRTIM_TIMDEADTIMEINSERTION_DISABLED (0x00000000U) /*!< Output 1 and output 2 signals are independent */
736 #define HRTIM_TIMDEADTIMEINSERTION_ENABLED HRTIM_OUTR_DTEN /*!< Deadtime is inserted between output 1 and output 2U */
737 /**
738 * @}
739 */
741 /** @defgroup HRTIM_Timer_Delayed_Protection_Mode HRTIM Timer Delayed Protection Mode
742 * @{
743 * @brief Constants defining all possible delayed protection modes
744 * for a timer. Also definethe source and outputs on which the delayed
745 * protection schemes are applied
746 */
748 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6 (HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 6U */
749 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 6U */
750 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output 2 delayed Idle on external Event 6U */
751 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 6U */
752 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 delayed Idle on external Event 7U */
753 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 2 delayed Idle on external Event 7U */
754 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Output 1 and output2 delayed Idle on external Event 7U */
755 #define HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers A, B, C: Balanced Idle on external Event 7U */
758 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_EEV8 (HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 6U */
759 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_EEV8 (HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 6U */
760 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output 2 delayed Idle on external Event 6U */
761 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV8 (HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 6U */
762 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT1_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 delayed Idle on external Event 7U */
763 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDOUT2_DEEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 2 delayed Idle on external Event 7U */
764 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_DELAYEDBOTH_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Output 1 and output2 delayed Idle on external Event 7U */
765 #define HRTIM_TIMER_D_E_DELAYEDPROTECTION_BALANCED_EEV9 (HRTIM_OUTR_DLYPRT_2 | HRTIM_OUTR_DLYPRT_1 | HRTIM_OUTR_DLYPRT_0 | HRTIM_OUTR_DLYPRTEN) /*!< Timers D, E: Balanced Idle on external Event 7U */
766 /**
767 * @}
768 */
770 /** @defgroup HRTIM_Timer_Update_Trigger HRTIM Timer Update Trigger
771 * @{
772 * @brief Constants defining whether the registers update is done synchronously
773 * with any other timer or master update
774 */
776 #define HRTIM_TIMUPDATETRIGGER_MASTER (HRTIM_TIMCR_MSTU) /*!< Register update is triggered by the master timer update */
777 #define HRTIM_TIMUPDATETRIGGER_TIMER_A (HRTIM_TIMCR_TAU) /*!< Register update is triggered by the timer A update */
778 #define HRTIM_TIMUPDATETRIGGER_TIMER_B (HRTIM_TIMCR_TBU) /*!< Register update is triggered by the timer B update */
779 #define HRTIM_TIMUPDATETRIGGER_TIMER_C (HRTIM_TIMCR_TCU) /*!< Register update is triggered by the timer C update*/
780 #define HRTIM_TIMUPDATETRIGGER_TIMER_D (HRTIM_TIMCR_TDU) /*!< Register update is triggered by the timer D update */
781 #define HRTIM_TIMUPDATETRIGGER_TIMER_E (HRTIM_TIMCR_TEU) /*!< Register update is triggered by the timer E update */
782 /**
783 * @}
784 */
786 /** @defgroup HRTIM_Timer_Reset_Trigger HRTIM Timer Reset Trigger
787 * @{
788 * @brief Constants defining the events that can be selected to trigger the reset
789 * of the timer counter
790 */
792 #define HRTIM_TIMRESETTRIGGER_UPDATE (HRTIM_RSTR_UPDATE) /*!< The timer counter is reset upon update event */
793 #define HRTIM_TIMRESETTRIGGER_CMP2 (HRTIM_RSTR_CMP2) /*!< The timer counter is reset upon Timer Compare 2 event */
794 #define HRTIM_TIMRESETTRIGGER_CMP4 (HRTIM_RSTR_CMP4) /*!< The timer counter is reset upon Timer Compare 4 event */
795 #define HRTIM_TIMRESETTRIGGER_MASTER_PER (HRTIM_RSTR_MSTPER) /*!< The timer counter is reset upon master timer period event */
796 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP1 (HRTIM_RSTR_MSTCMP1) /*!< The timer counter is reset upon master timer Compare 1 event */
797 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP2 (HRTIM_RSTR_MSTCMP2) /*!< The timer counter is reset upon master timer Compare 2 event */
798 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP3 (HRTIM_RSTR_MSTCMP3) /*!< The timer counter is reset upon master timer Compare 3 event */
799 #define HRTIM_TIMRESETTRIGGER_MASTER_CMP4 (HRTIM_RSTR_MSTCMP4) /*!< The timer counter is reset upon master timer Compare 4 event */
800 #define HRTIM_TIMRESETTRIGGER_EEV_1 (HRTIM_RSTR_EXTEVNT1) /*!< The timer counter is reset upon external event 1U */
801 #define HRTIM_TIMRESETTRIGGER_EEV_2 (HRTIM_RSTR_EXTEVNT2) /*!< The timer counter is reset upon external event 2U */
802 #define HRTIM_TIMRESETTRIGGER_EEV_3 (HRTIM_RSTR_EXTEVNT3) /*!< The timer counter is reset upon external event 3U */
803 #define HRTIM_TIMRESETTRIGGER_EEV_4 (HRTIM_RSTR_EXTEVNT4) /*!< The timer counter is reset upon external event 4U */
804 #define HRTIM_TIMRESETTRIGGER_EEV_5 (HRTIM_RSTR_EXTEVNT5) /*!< The timer counter is reset upon external event 5U */
805 #define HRTIM_TIMRESETTRIGGER_EEV_6 (HRTIM_RSTR_EXTEVNT6) /*!< The timer counter is reset upon external event 6U */
806 #define HRTIM_TIMRESETTRIGGER_EEV_7 (HRTIM_RSTR_EXTEVNT7) /*!< The timer counter is reset upon external event 7U */
807 #define HRTIM_TIMRESETTRIGGER_EEV_8 (HRTIM_RSTR_EXTEVNT8) /*!< The timer counter is reset upon external event 8U */
808 #define HRTIM_TIMRESETTRIGGER_EEV_9 (HRTIM_RSTR_EXTEVNT9) /*!< The timer counter is reset upon external event 9U */
809 #define HRTIM_TIMRESETTRIGGER_EEV_10 (HRTIM_RSTR_EXTEVNT10) /*!< The timer counter is reset upon external event 10U */
810 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP1 (HRTIM_RSTR_TIMBCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
811 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP2 (HRTIM_RSTR_TIMBCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
812 #define HRTIM_TIMRESETTRIGGER_OTHER1_CMP4 (HRTIM_RSTR_TIMBCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
813 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP1 (HRTIM_RSTR_TIMCCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
814 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP2 (HRTIM_RSTR_TIMCCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
815 #define HRTIM_TIMRESETTRIGGER_OTHER2_CMP4 (HRTIM_RSTR_TIMCCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
816 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP1 (HRTIM_RSTR_TIMDCMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
817 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP2 (HRTIM_RSTR_TIMDCMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
818 #define HRTIM_TIMRESETTRIGGER_OTHER3_CMP4 (HRTIM_RSTR_TIMDCMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
819 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP1 (HRTIM_RSTR_TIMECMP1) /*!< The timer counter is reset upon other timer Compare 1 event */
820 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP2 (HRTIM_RSTR_TIMECMP2) /*!< The timer counter is reset upon other timer Compare 2 event */
821 #define HRTIM_TIMRESETTRIGGER_OTHER4_CMP4 (HRTIM_RSTR_TIMECMP4) /*!< The timer counter is reset upon other timer Compare 4 event */
822 /**
823 * @}
824 */
826 /** @defgroup HRTIM_Timer_Reset_Update HRTIM Timer Reset Update
827 * @{
828 * @brief Constants defining whether the register are updated upon Timerx
829 * counter reset or roll-over to 0 after reaching the period value
830 * in continuous mode
831 */
832 #define HRTIM_TIMUPDATEONRESET_DISABLED 0x00000000U /*!< Update by timer x reset / roll-over disabled */
833 #define HRTIM_TIMUPDATEONRESET_ENABLED (HRTIM_TIMCR_TRSTU) /*!< Update by timer x reset / roll-over enabled */
834 /**
835 * @}
836 */
838 /** @defgroup HRTIM_Compare_Unit_Auto_Delayed_Mode HRTIM Compare Unit Auto Delayed Mode
839 * @{
840 * @brief Constants defining whether the compare register is behaving in
841 * regular mode (compare match issued as soon as counter equal compare),
842 * or in auto-delayed mode
843 */
845 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT (HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated only if a capture has occurred */
846 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1 (HRTIM_TIMCR_DELCMP2_1) /*!< Compare event generated if a capture has occurred or after a Compare 1 match (timeout if capture event is missing) */
847 #define HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3 (HRTIM_TIMCR_DELCMP2_1 | HRTIM_TIMCR_DELCMP2_0) /*!< Compare event generated if a capture has occurred or after a Compare 3 match (timeout if capture event is missing) */
848 /**
849 * @}
850 */
852 /** @defgroup HRTIM_Simple_OC_Mode HRTIM Simple OC Mode
853 * @{
854 * @brief Constants defining the behavior of the output signal when the timer
855 operates in basic output compare mode
856 */
857 #define HRTIM_BASICOCMODE_TOGGLE (0x00000001U) /*!< Output toggles when the timer counter reaches the compare value */
858 #define HRTIM_BASICOCMODE_INACTIVE (0x00000002U) /*!< Output forced to active level when the timer counter reaches the compare value */
859 #define HRTIM_BASICOCMODE_ACTIVE (0x00000003U) /*!< Output forced to inactive level when the timer counter reaches the compare value */
861 #define IS_HRTIM_BASICOCMODE(BASICOCMODE)\
862 (((BASICOCMODE) == HRTIM_BASICOCMODE_TOGGLE) || \
863 ((BASICOCMODE) == HRTIM_BASICOCMODE_INACTIVE) || \
864 ((BASICOCMODE) == HRTIM_BASICOCMODE_ACTIVE))
865 /**
866 * @}
867 */
869 /** @defgroup HRTIM_Output_Polarity HRTIM Output Polarity
870 * @{
871 * @brief Constants defining the polarity of a timer output
872 */
875 /**
876 * @}
877 */
879 /** @defgroup HRTIM_Output_Set_Source HRTIM Output Set Source
880 * @{
881 * @brief Constants defining the events that can be selected to configure the
882 * set crossbar of a timer output
883 */
885 #define HRTIM_OUTPUTSET_RESYNC (HRTIM_SET1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its active state */
886 #define HRTIM_OUTPUTSET_TIMPER (HRTIM_SET1R_PER) /*!< Timer period event forces the output to its active state */
887 #define HRTIM_OUTPUTSET_TIMCMP1 (HRTIM_SET1R_CMP1) /*!< Timer compare 1 event forces the output to its active state */
888 #define HRTIM_OUTPUTSET_TIMCMP2 (HRTIM_SET1R_CMP2) /*!< Timer compare 2 event forces the output to its active state */
889 #define HRTIM_OUTPUTSET_TIMCMP3 (HRTIM_SET1R_CMP3) /*!< Timer compare 3 event forces the output to its active state */
890 #define HRTIM_OUTPUTSET_TIMCMP4 (HRTIM_SET1R_CMP4) /*!< Timer compare 4 event forces the output to its active state */
891 #define HRTIM_OUTPUTSET_MASTERPER (HRTIM_SET1R_MSTPER) /*!< The master timer period event forces the output to its active state */
892 #define HRTIM_OUTPUTSET_MASTERCMP1 (HRTIM_SET1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its active state */
893 #define HRTIM_OUTPUTSET_MASTERCMP2 (HRTIM_SET1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its active state */
894 #define HRTIM_OUTPUTSET_MASTERCMP3 (HRTIM_SET1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its active state */
895 #define HRTIM_OUTPUTSET_MASTERCMP4 (HRTIM_SET1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its active state */
896 #define HRTIM_OUTPUTSET_TIMEV_1 (HRTIM_SET1R_TIMEVNT1) /*!< Timer event 1 forces the output to its active state */
897 #define HRTIM_OUTPUTSET_TIMEV_2 (HRTIM_SET1R_TIMEVNT2) /*!< Timer event 2 forces the output to its active state */
898 #define HRTIM_OUTPUTSET_TIMEV_3 (HRTIM_SET1R_TIMEVNT3) /*!< Timer event 3 forces the output to its active state */
899 #define HRTIM_OUTPUTSET_TIMEV_4 (HRTIM_SET1R_TIMEVNT4) /*!< Timer event 4 forces the output to its active state */
900 #define HRTIM_OUTPUTSET_TIMEV_5 (HRTIM_SET1R_TIMEVNT5) /*!< Timer event 5 forces the output to its active state */
901 #define HRTIM_OUTPUTSET_TIMEV_6 (HRTIM_SET1R_TIMEVNT6) /*!< Timer event 6 forces the output to its active state */
902 #define HRTIM_OUTPUTSET_TIMEV_7 (HRTIM_SET1R_TIMEVNT7) /*!< Timer event 7 forces the output to its active state */
903 #define HRTIM_OUTPUTSET_TIMEV_8 (HRTIM_SET1R_TIMEVNT8) /*!< Timer event 8 forces the output to its active state */
904 #define HRTIM_OUTPUTSET_TIMEV_9 (HRTIM_SET1R_TIMEVNT9) /*!< Timer event 9 forces the output to its active state */
905 #define HRTIM_OUTPUTSET_EEV_1 (HRTIM_SET1R_EXTVNT1) /*!< External event 1 forces the output to its active state */
906 #define HRTIM_OUTPUTSET_EEV_2 (HRTIM_SET1R_EXTVNT2) /*!< External event 2 forces the output to its active state */
907 #define HRTIM_OUTPUTSET_EEV_3 (HRTIM_SET1R_EXTVNT3) /*!< External event 3 forces the output to its active state */
908 #define HRTIM_OUTPUTSET_EEV_4 (HRTIM_SET1R_EXTVNT4) /*!< External event 4 forces the output to its active state */
909 #define HRTIM_OUTPUTSET_EEV_5 (HRTIM_SET1R_EXTVNT5) /*!< External event 5 forces the output to its active state */
910 #define HRTIM_OUTPUTSET_EEV_6 (HRTIM_SET1R_EXTVNT6) /*!< External event 6 forces the output to its active state */
911 #define HRTIM_OUTPUTSET_EEV_7 (HRTIM_SET1R_EXTVNT7) /*!< External event 7 forces the output to its active state */
912 #define HRTIM_OUTPUTSET_EEV_8 (HRTIM_SET1R_EXTVNT8) /*!< External event 8 forces the output to its active state */
913 #define HRTIM_OUTPUTSET_EEV_9 (HRTIM_SET1R_EXTVNT9) /*!< External event 9 forces the output to its active state */
914 #define HRTIM_OUTPUTSET_EEV_10 (HRTIM_SET1R_EXTVNT10) /*!< External event 10 forces the output to its active state */
915 #define HRTIM_OUTPUTSET_UPDATE (HRTIM_SET1R_UPDATE) /*!< Timer register update event forces the output to its active state */
916 /**
917 * @}
918 */
920 /** @defgroup HRTIM_Output_Reset_Source HRTIM Output Reset Source
921 * @{
922 * @brief Constants defining the events that can be selected to configure the
923 * set crossbar of a timer output
924 */
926 #define HRTIM_OUTPUTRESET_RESYNC (HRTIM_RST1R_RESYNC) /*!< Timer reset event coming solely from software or SYNC input forces the output to its inactive state */
927 #define HRTIM_OUTPUTRESET_TIMPER (HRTIM_RST1R_PER) /*!< Timer period event forces the output to its inactive state */
928 #define HRTIM_OUTPUTRESET_TIMCMP1 (HRTIM_RST1R_CMP1) /*!< Timer compare 1 event forces the output to its inactive state */
929 #define HRTIM_OUTPUTRESET_TIMCMP2 (HRTIM_RST1R_CMP2) /*!< Timer compare 2 event forces the output to its inactive state */
930 #define HRTIM_OUTPUTRESET_TIMCMP3 (HRTIM_RST1R_CMP3) /*!< Timer compare 3 event forces the output to its inactive state */
931 #define HRTIM_OUTPUTRESET_TIMCMP4 (HRTIM_RST1R_CMP4) /*!< Timer compare 4 event forces the output to its inactive state */
932 #define HRTIM_OUTPUTRESET_MASTERPER (HRTIM_RST1R_MSTPER) /*!< The master timer period event forces the output to its inactive state */
933 #define HRTIM_OUTPUTRESET_MASTERCMP1 (HRTIM_RST1R_MSTCMP1) /*!< Master Timer compare 1 event forces the output to its inactive state */
934 #define HRTIM_OUTPUTRESET_MASTERCMP2 (HRTIM_RST1R_MSTCMP2) /*!< Master Timer compare 2 event forces the output to its inactive state */
935 #define HRTIM_OUTPUTRESET_MASTERCMP3 (HRTIM_RST1R_MSTCMP3) /*!< Master Timer compare 3 event forces the output to its inactive state */
936 #define HRTIM_OUTPUTRESET_MASTERCMP4 (HRTIM_RST1R_MSTCMP4) /*!< Master Timer compare 4 event forces the output to its inactive state */
937 #define HRTIM_OUTPUTRESET_TIMEV_1 (HRTIM_RST1R_TIMEVNT1) /*!< Timer event 1 forces the output to its inactive state */
938 #define HRTIM_OUTPUTRESET_TIMEV_2 (HRTIM_RST1R_TIMEVNT2) /*!< Timer event 2 forces the output to its inactive state */
939 #define HRTIM_OUTPUTRESET_TIMEV_3 (HRTIM_RST1R_TIMEVNT3) /*!< Timer event 3 forces the output to its inactive state */
940 #define HRTIM_OUTPUTRESET_TIMEV_4 (HRTIM_RST1R_TIMEVNT4) /*!< Timer event 4 forces the output to its inactive state */
941 #define HRTIM_OUTPUTRESET_TIMEV_5 (HRTIM_RST1R_TIMEVNT5) /*!< Timer event 5 forces the output to its inactive state */
942 #define HRTIM_OUTPUTRESET_TIMEV_6 (HRTIM_RST1R_TIMEVNT6) /*!< Timer event 6 forces the output to its inactive state */
943 #define HRTIM_OUTPUTRESET_TIMEV_7 (HRTIM_RST1R_TIMEVNT7) /*!< Timer event 7 forces the output to its inactive state */
944 #define HRTIM_OUTPUTRESET_TIMEV_8 (HRTIM_RST1R_TIMEVNT8) /*!< Timer event 8 forces the output to its inactive state */
945 #define HRTIM_OUTPUTRESET_TIMEV_9 (HRTIM_RST1R_TIMEVNT9) /*!< Timer event 9 forces the output to its inactive state */
946 #define HRTIM_OUTPUTRESET_EEV_1 (HRTIM_RST1R_EXTVNT1) /*!< External event 1 forces the output to its inactive state */
947 #define HRTIM_OUTPUTRESET_EEV_2 (HRTIM_RST1R_EXTVNT2) /*!< External event 2 forces the output to its inactive state */
948 #define HRTIM_OUTPUTRESET_EEV_3 (HRTIM_RST1R_EXTVNT3) /*!< External event 3 forces the output to its inactive state */
949 #define HRTIM_OUTPUTRESET_EEV_4 (HRTIM_RST1R_EXTVNT4) /*!< External event 4 forces the output to its inactive state */
950 #define HRTIM_OUTPUTRESET_EEV_5 (HRTIM_RST1R_EXTVNT5) /*!< External event 5 forces the output to its inactive state */
951 #define HRTIM_OUTPUTRESET_EEV_6 (HRTIM_RST1R_EXTVNT6) /*!< External event 6 forces the output to its inactive state */
952 #define HRTIM_OUTPUTRESET_EEV_7 (HRTIM_RST1R_EXTVNT7) /*!< External event 7 forces the output to its inactive state */
953 #define HRTIM_OUTPUTRESET_EEV_8 (HRTIM_RST1R_EXTVNT8) /*!< External event 8 forces the output to its inactive state */
954 #define HRTIM_OUTPUTRESET_EEV_9 (HRTIM_RST1R_EXTVNT9) /*!< External event 9 forces the output to its inactive state */
955 #define HRTIM_OUTPUTRESET_EEV_10 (HRTIM_RST1R_EXTVNT10) /*!< External event 10 forces the output to its inactive state */
956 #define HRTIM_OUTPUTRESET_UPDATE (HRTIM_RST1R_UPDATE) /*!< Timer register update event forces the output to its inactive state */
957 /**
958 * @}
959 */
961 /** @defgroup HRTIM_Output_Idle_Mode HRTIM Output Idle Mode
962 * @{
963 * @brief Constants defining whether or not the timer output transition to its
964 IDLE state when burst mode is entered
965 */
966 #define HRTIM_OUTPUTIDLEMODE_NONE 0x00000000U /*!< The output is not affected by the burst mode operation */
967 #define HRTIM_OUTPUTIDLEMODE_IDLE (HRTIM_OUTR_IDLM1) /*!< The output is in idle state when requested by the burst mode controller */
968 /**
969 * @}
970 */
972 /** @defgroup HRTIM_Output_IDLE_Level HRTIM Output IDLE Level
973 * @{
974 * @brief Constants defining the output level when output is in IDLE state
975 */
976 #define HRTIM_OUTPUTIDLELEVEL_INACTIVE 0x00000000U /*!< Output at inactive level when in IDLE state */
977 #define HRTIM_OUTPUTIDLELEVEL_ACTIVE (HRTIM_OUTR_IDLES1) /*!< Output at active level when in IDLE state */
978 /**
979 * @}
980 */
982 /** @defgroup HRTIM_Output_FAULT_Level HRTIM Output FAULT Level
983 * @{
984 * @brief Constants defining the output level when output is in FAULT state
985 */
986 #define HRTIM_OUTPUTFAULTLEVEL_NONE 0x00000000U /*!< The output is not affected by the fault input */
987 #define HRTIM_OUTPUTFAULTLEVEL_ACTIVE (HRTIM_OUTR_FAULT1_0) /*!< Output at active level when in FAULT state */
988 #define HRTIM_OUTPUTFAULTLEVEL_INACTIVE (HRTIM_OUTR_FAULT1_1) /*!< Output at inactive level when in FAULT state */
989 #define HRTIM_OUTPUTFAULTLEVEL_HIGHZ (HRTIM_OUTR_FAULT1_1 | HRTIM_OUTR_FAULT1_0) /*!< Output is tri-stated when in FAULT state */
990 /**
991 * @}
992 */
994 /** @defgroup HRTIM_Output_Chopper_Mode_Enable HRTIM Output Chopper Mode Enable
995 * @{
996 * @brief Constants defining whether or not chopper mode is enabled for a timer
997 output
998 */
1000 #define HRTIM_OUTPUTCHOPPERMODE_ENABLED (HRTIM_OUTR_CHP1) /*!< Output signal is chopped by a carrier signal */
1001 /**
1002 * @}
1003 */
1005 /** @defgroup HRTIM_Output_Burst_Mode_Entry_Delayed HRTIM Output Burst Mode Entry Delayed
1006 * @{
1007 * @brief Constants defining the idle mode entry is delayed by forcing a
1008 deadtime insertion before switching the outputs to their idle state
1009 */
1010 #define HRTIM_OUTPUTBURSTMODEENTRY_REGULAR 0x00000000U /*!< The programmed Idle state is applied immediately to the Output */
1011 #define HRTIM_OUTPUTBURSTMODEENTRY_DELAYED (HRTIM_OUTR_DIDL1) /*!< Deadtime is inserted on output before entering the idle mode */
1012 /**
1013 * @}
1014 */
1016 /** @defgroup HRTIM_Capture_Unit_Trigger HRTIM Capture Unit Trigger
1017 * @{
1018 * @brief Constants defining the events that can be selected to trigger the
1019 * capture of the timing unit counter
1020 */
1022 #define HRTIM_CAPTURETRIGGER_UPDATE (HRTIM_CPT1CR_UPDCPT) /*!< The update event triggers the Capture */
1023 #define HRTIM_CAPTURETRIGGER_EEV_1 (HRTIM_CPT1CR_EXEV1CPT) /*!< The External event 1 triggers the Capture */
1024 #define HRTIM_CAPTURETRIGGER_EEV_2 (HRTIM_CPT1CR_EXEV2CPT) /*!< The External event 2 triggers the Capture */
1025 #define HRTIM_CAPTURETRIGGER_EEV_3 (HRTIM_CPT1CR_EXEV3CPT) /*!< The External event 3 triggers the Capture */
1026 #define HRTIM_CAPTURETRIGGER_EEV_4 (HRTIM_CPT1CR_EXEV4CPT) /*!< The External event 4 triggers the Capture */
1027 #define HRTIM_CAPTURETRIGGER_EEV_5 (HRTIM_CPT1CR_EXEV5CPT) /*!< The External event 5 triggers the Capture */
1028 #define HRTIM_CAPTURETRIGGER_EEV_6 (HRTIM_CPT1CR_EXEV6CPT) /*!< The External event 6 triggers the Capture */
1029 #define HRTIM_CAPTURETRIGGER_EEV_7 (HRTIM_CPT1CR_EXEV7CPT) /*!< The External event 7 triggers the Capture */
1030 #define HRTIM_CAPTURETRIGGER_EEV_8 (HRTIM_CPT1CR_EXEV8CPT) /*!< The External event 8 triggers the Capture */
1031 #define HRTIM_CAPTURETRIGGER_EEV_9 (HRTIM_CPT1CR_EXEV9CPT) /*!< The External event 9 triggers the Capture */
1032 #define HRTIM_CAPTURETRIGGER_EEV_10 (HRTIM_CPT1CR_EXEV10CPT) /*!< The External event 10 triggers the Capture */
1033 #define HRTIM_CAPTURETRIGGER_TA1_SET (HRTIM_CPT1CR_TA1SET) /*!< Capture is triggered by TA1 output inactive to active transition */
1034 #define HRTIM_CAPTURETRIGGER_TA1_RESET (HRTIM_CPT1CR_TA1RST) /*!< Capture is triggered by TA1 output active to inactive transition */
1035 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP1 (HRTIM_CPT1CR_TIMACMP1) /*!< Timer A Compare 1 triggers Capture */
1036 #define HRTIM_CAPTURETRIGGER_TIMERA_CMP2 (HRTIM_CPT1CR_TIMACMP2) /*!< Timer A Compare 2 triggers Capture */
1037 #define HRTIM_CAPTURETRIGGER_TB1_SET (HRTIM_CPT1CR_TB1SET) /*!< Capture is triggered by TB1 output inactive to active transition */
1038 #define HRTIM_CAPTURETRIGGER_TB1_RESET (HRTIM_CPT1CR_TB1RST) /*!< Capture is triggered by TB1 output active to inactive transition */
1039 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP1 (HRTIM_CPT1CR_TIMBCMP1) /*!< Timer B Compare 1 triggers Capture */
1040 #define HRTIM_CAPTURETRIGGER_TIMERB_CMP2 (HRTIM_CPT1CR_TIMBCMP2) /*!< Timer B Compare 2 triggers Capture */
1041 #define HRTIM_CAPTURETRIGGER_TC1_SET (HRTIM_CPT1CR_TC1SET) /*!< Capture is triggered by TC1 output inactive to active transition */
1042 #define HRTIM_CAPTURETRIGGER_TC1_RESET (HRTIM_CPT1CR_TC1RST) /*!< Capture is triggered by TC1 output active to inactive transition */
1043 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP1 (HRTIM_CPT1CR_TIMCCMP1) /*!< Timer C Compare 1 triggers Capture */
1044 #define HRTIM_CAPTURETRIGGER_TIMERC_CMP2 (HRTIM_CPT1CR_TIMCCMP2) /*!< Timer C Compare 2 triggers Capture */
1045 #define HRTIM_CAPTURETRIGGER_TD1_SET (HRTIM_CPT1CR_TD1SET) /*!< Capture is triggered by TD1 output inactive to active transition */
1046 #define HRTIM_CAPTURETRIGGER_TD1_RESET (HRTIM_CPT1CR_TD1RST) /*!< Capture is triggered by TD1 output active to inactive transition */
1047 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP1 (HRTIM_CPT1CR_TIMDCMP1) /*!< Timer D Compare 1 triggers Capture */
1048 #define HRTIM_CAPTURETRIGGER_TIMERD_CMP2 (HRTIM_CPT1CR_TIMDCMP2) /*!< Timer D Compare 2 triggers Capture */
1049 #define HRTIM_CAPTURETRIGGER_TE1_SET (HRTIM_CPT1CR_TE1SET) /*!< Capture is triggered by TE1 output inactive to active transition */
1050 #define HRTIM_CAPTURETRIGGER_TE1_RESET (HRTIM_CPT1CR_TE1RST) /*!< Capture is triggered by TE1 output active to inactive transition */
1051 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP1 (HRTIM_CPT1CR_TIMECMP1) /*!< Timer E Compare 1 triggers Capture */
1052 #define HRTIM_CAPTURETRIGGER_TIMERE_CMP2 (HRTIM_CPT1CR_TIMECMP2) /*!< Timer E Compare 2 triggers Capture */
1053 /**
1054 * @}
1055 */
1057 /** @defgroup HRTIM_Timer_External_Event_Filter HRTIM Timer External Event Filter
1058 * @{
1059 * @brief Constants defining the event filtering apploed to external events
1060 * by a timer
1061 */
1062 #define HRTIM_TIMEVENTFILTER_NONE (0x00000000U)
1063 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP1 (HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 1U */
1064 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP2 (HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from counter reset/roll-over to Compare 2U */
1065 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP3 (HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from counter reset/roll-over to Compare 3U */
1066 #define HRTIM_TIMEVENTFILTER_BLANKINGCMP4 (HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from counter reset/roll-over to Compare 4U */
1067 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR1 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR1 source */
1068 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR2 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR2 source */
1069 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR3 (HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR3 source */
1070 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR4 (HRTIM_EEFR1_EE1FLTR_3) /*!< Blanking from another timing unit: TIMFLTR4 source */
1071 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR5 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR5 source */
1072 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR6 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1) /*!< Blanking from another timing unit: TIMFLTR6 source */
1073 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR7 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_0) /*!< Blanking from another timing unit: TIMFLTR7 source */
1074 #define HRTIM_TIMEVENTFILTER_BLANKINGFLTR8 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2) /*!< Blanking from another timing unit: TIMFLTR8 source */
1075 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP2 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from counter reset/roll-over to Compare 2U */
1076 #define HRTIM_TIMEVENTFILTER_WINDOWINGCMP3 (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1) /*!< Windowing from counter reset/roll-over to Compare 3U */
1077 #define HRTIM_TIMEVENTFILTER_WINDOWINGTIM (HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_1 | HRTIM_EEFR1_EE1FLTR_3 | HRTIM_EEFR1_EE1FLTR_2 | HRTIM_EEFR1_EE1FLTR_0) /*!< Windowing from another timing unit: TIMWIN source */
1078 /**
1079 * @}
1080 */
1082 /** @defgroup HRTIM_Timer_External_Event_Latch HRTIM Timer External Event Latch
1083 * @{
1084 * @brief Constants defining whether or not the external event is
1085 * memorized (latched) and generated as soon as the blanking period
1086 * is completed or the window ends
1087 */
1088 #define HRTIM_TIMEVENTLATCH_DISABLED (0x00000000U) /*!< Event is ignored if it happens during a blank, or passed through during a window */
1089 #define HRTIM_TIMEVENTLATCH_ENABLED HRTIM_EEFR1_EE1LTCH /*!< Event is latched and delayed till the end of the blanking or windowing period */
1090 /**
1091 * @}
1092 */
1094 /** @defgroup HRTIM_Deadtime_Prescaler_Ratio HRTIM Deadtime Prescaler Ratio
1095 * @{
1096 * @brief Constants defining division ratio between the timer clock frequency
1097 * (fHRTIM) and the deadtime generator clock (fDTG)
1098 */
1102 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1 (HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM */
1104 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 4U */
1105 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1) /*!< fDTG = fHRTIM / 8U */
1106 #define HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16 (HRTIM_DTR_DTPRSC_2 | HRTIM_DTR_DTPRSC_1 | HRTIM_DTR_DTPRSC_0) /*!< fDTG = fHRTIM / 16U */
1107 /**
1108 * @}
1109 */
1111 /** @defgroup HRTIM_Deadtime_Rising_Sign HRTIM Deadtime Rising Sign
1112 * @{
1113 * @brief Constants defining whether the deadtime is positive or negative
1114 * (overlapping signal) on rising edge
1115 */
1116 #define HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on rising edge */
1117 #define HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE (HRTIM_DTR_SDTR) /*!< Negative deadtime on rising edge */
1118 /**
1119 * @}
1120 */
1122 /** @defgroup HRTIM_Deadtime_Rising_Lock HRTIM Deadtime Rising Lock
1123 * @{
1124 * @brief Constants defining whether or not the deadtime (rising sign and
1125 * value) is write protected
1126 */
1127 #define HRTIM_TIMDEADTIME_RISINGLOCK_WRITE (0x00000000U) /*!< Deadtime rising value and sign is writeable */
1128 #define HRTIM_TIMDEADTIME_RISINGLOCK_READONLY (HRTIM_DTR_DTRLK) /*!< Deadtime rising value and sign is read-only */
1129 /**
1130 * @}
1131 */
1133 /** @defgroup HRTIM_Deadtime_Rising_Sign_Lock HRTIM Deadtime Rising Sign Lock
1134 * @{
1135 * @brief Constants defining whether or not the deadtime rising sign is write
1136 * protected
1137 */
1138 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime rising sign is writeable */
1139 #define HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY (HRTIM_DTR_DTRSLK) /*!< Deadtime rising sign is read-only */
1140 /**
1141 * @}
1142 */
1144 /** @defgroup HRTIM_Deadtime_Falling_Sign HRTIM Deadtime Falling Sign
1145 * @{
1146 * @brief Constants defining whether the deadtime is positive or negative
1147 * (overlapping signal) on falling edge
1148 */
1149 #define HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE (0x00000000U) /*!< Positive deadtime on falling edge */
1150 #define HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE (HRTIM_DTR_SDTF) /*!< Negative deadtime on falling edge */
1151 /**
1152 * @}
1153 */
1155 /** @defgroup HRTIM_Deadtime_Falling_Lock HRTIM Deadtime Falling Lock
1156 * @{
1157 * @brief Constants defining whether or not the deadtime (falling sign and
1158 * value) is write protected
1159 */
1160 #define HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE (0x00000000U) /*!< Deadtime falling value and sign is writeable */
1161 #define HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY (HRTIM_DTR_DTFLK) /*!< Deadtime falling value and sign is read-only */
1162 /**
1163 * @}
1164 */
1166 /** @defgroup HRTIM_Deadtime_Falling_Sign_Lock HRTIM Deadtime Falling Sign Lock
1167 * @{
1168 * @brief Constants defining whether or not the deadtime falling sign is write
1169 * protected
1170 */
1171 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE (0x00000000U) /*!< Deadtime falling sign is writeable */
1172 #define HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY (HRTIM_DTR_DTFSLK) /*!< Deadtime falling sign is read-only */
1173 /**
1174 * @}
1175 */
1177 /** @defgroup HRTIM_Chopper_Frequency HRTIM Chopper Frequency
1178 * @{
1179 * @brief Constants defining the frequency of the generated high frequency carrier
1180 */
1184 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV64 (HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 64 */
1186 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV96 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 96 */
1187 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV112 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 112 */
1188 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV128 (HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 128 */
1189 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV144 (HRTIM_CHPR_CARFRQ_3) /*!< fCHPFRQ = fHRTIM / 144 */
1190 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV160 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 160 */
1191 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV176 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 176 */
1192 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV192 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 192 */
1193 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV208 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2) /*!< fCHPFRQ = fHRTIM / 208 */
1194 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV224 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 224 */
1195 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV240 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1) /*!< fCHPFRQ = fHRTIM / 240 */
1196 #define HRTIM_CHOPPER_PRESCALERRATIO_DIV256 (HRTIM_CHPR_CARFRQ_3 | HRTIM_CHPR_CARFRQ_2 | HRTIM_CHPR_CARFRQ_1 | HRTIM_CHPR_CARFRQ_0) /*!< fCHPFRQ = fHRTIM / 256 */
1197 /**
1198 * @}
1199 */
1201 /** @defgroup HRTIM_Chopper_Duty_Cycle HRTIM Chopper Duty Cycle
1202 * @{
1203 * @brief Constants defining the duty cycle of the generated high frequency carrier
1204 * Duty cycle can be adjusted by 1/8 step (from 0/8 up to 7/8)
1205 */
1207 #define HRTIM_CHOPPER_DUTYCYCLE_125 (HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 12.5U % */
1208 #define HRTIM_CHOPPER_DUTYCYCLE_250 (HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 25U % */
1209 #define HRTIM_CHOPPER_DUTYCYCLE_375 (HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 37.5U % */
1210 #define HRTIM_CHOPPER_DUTYCYCLE_500 (HRTIM_CHPR_CARDTY_2) /*!< Duty cycle of the carrier signal is 50U % */
1211 #define HRTIM_CHOPPER_DUTYCYCLE_625 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 62.5U % */
1212 #define HRTIM_CHOPPER_DUTYCYCLE_750 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1) /*!< Duty cycle of the carrier signal is 75U % */
1213 #define HRTIM_CHOPPER_DUTYCYCLE_875 (HRTIM_CHPR_CARDTY_2 | HRTIM_CHPR_CARDTY_1 | HRTIM_CHPR_CARDTY_0) /*!< Duty cycle of the carrier signal is 87.5U % */
1214 /**
1215 * @}
1216 */
1218 /** @defgroup HRTIM_Chopper_Start_Pulse_Width HRTIM Chopper Start Pulse Width
1219 * @{
1220 * @brief Constants defining the pulse width of the first pulse of the generated
1221 * high frequency carrier
1222 */
1226 #define HRTIM_CHOPPER_PULSEWIDTH_64 (HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 64 */
1228 #define HRTIM_CHOPPER_PULSEWIDTH_96 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 96 */
1229 #define HRTIM_CHOPPER_PULSEWIDTH_112 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 112 */
1230 #define HRTIM_CHOPPER_PULSEWIDTH_128 (HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 128 */
1232 #define HRTIM_CHOPPER_PULSEWIDTH_160 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 160 */
1233 #define HRTIM_CHOPPER_PULSEWIDTH_176 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 176 */
1234 #define HRTIM_CHOPPER_PULSEWIDTH_192 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 192 */
1235 #define HRTIM_CHOPPER_PULSEWIDTH_208 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2) /*!< tSTPW = tHRTIM x 208 */
1236 #define HRTIM_CHOPPER_PULSEWIDTH_224 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 224 */
1237 #define HRTIM_CHOPPER_PULSEWIDTH_240 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1) /*!< tSTPW = tHRTIM x 240 */
1238 #define HRTIM_CHOPPER_PULSEWIDTH_256 (HRTIM_CHPR_STRPW_3 | HRTIM_CHPR_STRPW_2 | HRTIM_CHPR_STRPW_1 | HRTIM_CHPR_STRPW_0) /*!< tSTPW = tHRTIM x 256 */
1239 /**
1240 * @}
1241 */
1243 /** @defgroup HRTIM_Synchronization_Options HRTIM Synchronization Options
1244 * @{
1245 * @brief Constants defining the options for synchronizing multiple HRTIM
1246 * instances, as a master unit (generating a synchronization signal)
1247 * or as a slave (waiting for a trigger to be synchronized)
1248 */
1249 #define HRTIM_SYNCOPTION_NONE 0x00000000U /*!< HRTIM instance doesn't handle external synchronization signals (SYNCIN, SYNCOUT) */
1250 #define HRTIM_SYNCOPTION_MASTER 0x00000001U /*!< HRTIM instance acts as a MASTER, i.e. generates external synchronization output (SYNCOUT)*/
1251 #define HRTIM_SYNCOPTION_SLAVE 0x00000002U /*!< HRTIM instance acts as a SLAVE, i.e. it is synchronized by external sources (SYNCIN) */
1252 /**
1253 * @}
1254 */
1256 /** @defgroup HRTIM_Synchronization_Input_Source HRTIM Synchronization Input Source
1257 * @{
1258 * @brief Constants defining defining the synchronization input source
1259 */
1260 #define HRTIM_SYNCINPUTSOURCE_NONE 0x00000000U /*!< disabled. HRTIM is not synchronized and runs in standalone mode */
1261 #define HRTIM_SYNCINPUTSOURCE_INTERNALEVENT HRTIM_MCR_SYNC_IN_1 /*!< The HRTIM is synchronized with the on-chip timer */
1262 #define HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT (HRTIM_MCR_SYNC_IN_1 | HRTIM_MCR_SYNC_IN_0) /*!< A positive pulse on SYNCIN input triggers the HRTIM */
1263 /**
1264 * @}
1265 */
1267 /** @defgroup HRTIM_Synchronization_Output_Source HRTIM Synchronization Output Source
1268 * @{
1269 * @brief Constants defining the source and event to be sent on the
1270 * synchronization outputs
1271 */
1272 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_START 0x00000000U /*!< A pulse is sent on the SYNCOUT output upon master timer start event */
1273 #define HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1 (HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon master timer compare 1 event*/
1274 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_START (HRTIM_MCR_SYNC_SRC_1) /*!< A pulse is sent on the SYNCOUT output upon timer A start or reset events */
1275 #define HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1 (HRTIM_MCR_SYNC_SRC_1 | HRTIM_MCR_SYNC_SRC_0) /*!< A pulse is sent on the SYNCOUT output upon timer A compare 1 event */
1276 /**
1277 * @}
1278 */
1280 /** @defgroup HRTIM_Synchronization_Output_Polarity HRTIM Synchronization Output Polarity
1281 * @{
1282 * @brief Constants defining the routing and conditioning of the synchronization output event
1283 */
1284 #define HRTIM_SYNCOUTPUTPOLARITY_NONE 0x00000000U /*!< Synchronization output event is disabled */
1285 #define HRTIM_SYNCOUTPUTPOLARITY_POSITIVE (HRTIM_MCR_SYNC_OUT_1) /*!< SCOUT pin has a low idle level and issues a positive pulse of 16 fHRTIM clock cycles length for the synchronization */
1286 #define HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE (HRTIM_MCR_SYNC_OUT_1 | HRTIM_MCR_SYNC_OUT_0) /*!< SCOUT pin has a high idle level and issues a negative pulse of 16 fHRTIM clock cycles length for the synchronization */
1287 /**
1288 * @}
1289 */
1291 /** @defgroup HRTIM_External_Event_Sources HRTIM External Event Sources
1292 * @{
1293 * @brief Constants defining available sources associated to external events
1294 */
1298 #define HRTIM_EVENTSRC_4 (HRTIM_EECR1_EE1SRC_1 | HRTIM_EECR1_EE1SRC_0) /*!< External event source 4U */
1299 /**
1300 * @}
1301 */
1303 /** @defgroup HRTIM_External_Event_Polarity HRTIM External Event Polarity
1304 * @{
1305 * @brief Constants defining the polarity of an external event
1306 */
1309 /**
1310 * @}
1311 */
1313 /** @defgroup HRTIM_External_Event_Sensitivity HRTIM External Event Sensitivity
1314 * @{
1315 * @brief Constants defining the sensitivity (level-sensitive or edge-sensitive)
1316 * of an external event
1317 */
1319 #define HRTIM_EVENTSENSITIVITY_RISINGEDGE (HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising edge */
1320 #define HRTIM_EVENTSENSITIVITY_FALLINGEDGE (HRTIM_EECR1_EE1SNS_1) /*!< External event is active on Falling edge */
1321 #define HRTIM_EVENTSENSITIVITY_BOTHEDGES (HRTIM_EECR1_EE1SNS_1 | HRTIM_EECR1_EE1SNS_0) /*!< External event is active on Rising and Falling edges */
1322 /**
1323 * @}
1324 */
1326 /** @defgroup HRTIM_External_Event_Fast_Mode HRTIM External Event Fast Mode
1327 * @{
1328 * @brief Constants defining whether or not an external event is programmed in
1329 fast mode
1330 */
1332 #define HRTIM_EVENTFASTMODE_ENABLE (0x00000000U) /*!< External Event is re-synchronized by the HRTIM logic before acting on outputs */
1333 #define HRTIM_EVENTFASTMODE_DISABLE (HRTIM_EECR1_EE1FAST) /*!< External Event is acting asynchronously on outputs (low latency mode) */
1334 /**
1335 * @}
1336 */
1338 /** @defgroup HRTIM_External_Event_Filter HRTIM External Event Filter
1339 * @{
1340 * @brief Constants defining the frequency used to sample an external event 6
1341 * input and the length (N) of the digital filter applied
1342 */
1346 #define HRTIM_EVENTFILTER_3 (HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fHRTIM, N=8U */
1348 #define HRTIM_EVENTFILTER_5 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/2U, N=8U */
1349 #define HRTIM_EVENTFILTER_6 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/4U, N=6U */
1350 #define HRTIM_EVENTFILTER_7 (HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/4U, N=8U */
1352 #define HRTIM_EVENTFILTER_9 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/8U, N=8U */
1353 #define HRTIM_EVENTFILTER_10 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/16U, N=5U */
1354 #define HRTIM_EVENTFILTER_11 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/16U, N=6U */
1355 #define HRTIM_EVENTFILTER_12 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2) /*!< fSAMPLING= fEEVS/16U, N=8U */
1356 #define HRTIM_EVENTFILTER_13 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=5U */
1357 #define HRTIM_EVENTFILTER_14 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1) /*!< fSAMPLING= fEEVS/32U, N=6U */
1358 #define HRTIM_EVENTFILTER_15 (HRTIM_EECR3_EE6F_3 | HRTIM_EECR3_EE6F_2 | HRTIM_EECR3_EE6F_1 | HRTIM_EECR3_EE6F_0) /*!< fSAMPLING= fEEVS/32U, N=8U */
1359 /**
1360 * @}
1361 */
1363 /** @defgroup HRTIM_External_Event_Prescaler HRTIM External Event Prescaler
1364 * @{
1365 * @brief Constants defining division ratio between the timer clock frequency
1366 * fHRTIM) and the external event signal sampling clock (fEEVS)
1367 * used by the digital filters
1368 */
1372 #define HRTIM_EVENTPRESCALER_DIV8 (HRTIM_EECR3_EEVSD_1 | HRTIM_EECR3_EEVSD_0) /*!< fEEVS=fHRTIM / 8U */
1373 /**
1374 * @}
1375 */
1377 /** @defgroup HRTIM_Fault_Sources HRTIM Fault Sources
1378 * @{
1379 * @brief Constants defining whether a faults is be triggered by any external
1380 * or internal fault source
1381 */
1383 #define HRTIM_FAULTSOURCE_INTERNAL (HRTIM_FLTINR1_FLT1SRC) /*!< Fault input is FLT_Int signal (e.g. internal comparator) */
1384 /**
1385 * @}
1386 */
1388 /** @defgroup HRTIM_Fault_Polarity HRTIM Fault Polarity
1389 * @{
1390 * @brief Constants defining the polarity of a fault event
1391 */
1394 /**
1395 * @}
1396 */
1398 /** @defgroup HRTIM_Fault_Filter HRTIM Fault Filter
1399 * @{
1400 * @ brief Constants defining the frequency used to sample the fault input and
1401 * the length (N) of the digital filter applied
1402 */
1406 #define HRTIM_FAULTFILTER_3 (HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fHRTIM, N=8U */
1408 #define HRTIM_FAULTFILTER_5 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/2U, N=8U */
1409 #define HRTIM_FAULTFILTER_6 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/4U, N=6U */
1410 #define HRTIM_FAULTFILTER_7 (HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/4U, N=8U */
1412 #define HRTIM_FAULTFILTER_9 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/8U, N=8U */
1413 #define HRTIM_FAULTFILTER_10 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/16U, N=5U */
1414 #define HRTIM_FAULTFILTER_11 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/16U, N=6U */
1415 #define HRTIM_FAULTFILTER_12 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2) /*!< fSAMPLING= fFLTS/16U, N=8U */
1416 #define HRTIM_FAULTFILTER_13 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=5U */
1417 #define HRTIM_FAULTFILTER_14 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1) /*!< fSAMPLING= fFLTS/32U, N=6U */
1418 #define HRTIM_FAULTFILTER_15 (HRTIM_FLTINR1_FLT1F_3 | HRTIM_FLTINR1_FLT1F_2 | HRTIM_FLTINR1_FLT1F_1 | HRTIM_FLTINR1_FLT1F_0) /*!< fSAMPLING= fFLTS/32U, N=8U */
1419 /**
1420 * @}
1421 */
1423 /** @defgroup HRTIM_Fault_Lock HRTIM Fault Lock
1424 * @{
1425 * @brief Constants defining whether or not the fault programming bits are
1426 write protected
1427 */
1429 #define HRTIM_FAULTLOCK_READONLY (HRTIM_FLTINR1_FLT1LCK) /*!< Fault settings bits are read only */
1430 /**
1431 * @}
1432 */
1434 /** @defgroup HRTIM_External_Fault_Prescaler HRTIM External Fault Prescaler
1435 * @{
1436 * @brief Constants defining the division ratio between the timer clock
1437 * frequency (fHRTIM) and the fault signal sampling clock (fFLTS) used
1438 * by the digital filters.
1439 */
1443 #define HRTIM_FAULTPRESCALER_DIV8 (HRTIM_FLTINR2_FLTSD_1 | HRTIM_FLTINR2_FLTSD_0) /*!< fFLTS=fHRTIM / 8U */
1444 /**
1445 * @}
1446 */
1448 /** @defgroup HRTIM_Burst_Mode_Operating_Mode HRTIM Burst Mode Operating Mode
1449 * @{
1450 * @brief Constants defining if the burst mode is entered once or if it is
1451 * continuously operating
1452 */
1453 #define HRTIM_BURSTMODE_SINGLESHOT (0x00000000U) /*!< Burst mode operates in single shot mode */
1454 #define HRTIM_BURSTMODE_CONTINOUS (HRTIM_BMCR_BMOM) /*!< Burst mode operates in continuous mode */
1455 /**
1456 * @}
1457 */
1459 /** @defgroup HRTIM_Burst_Mode_Clock_Source HRTIM Burst Mode Clock Source
1460 * @{
1461 * @brief Constants defining the clock source for the burst mode counter
1462 */
1463 #define HRTIM_BURSTMODECLOCKSOURCE_MASTER (0x00000000U) /*!< Master timer counter reset/roll-over is used as clock source for the burst mode counter */
1464 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_A (HRTIM_BMCR_BMCLK_0) /*!< Timer A counter reset/roll-over is used as clock source for the burst mode counter */
1465 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_B (HRTIM_BMCR_BMCLK_1) /*!< Timer B counter reset/roll-over is used as clock source for the burst mode counter */
1466 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_C (HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< Timer C counter reset/roll-over is used as clock source for the burst mode counter */
1467 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_D (HRTIM_BMCR_BMCLK_2) /*!< Timer D counter reset/roll-over is used as clock source for the burst mode counter */
1468 #define HRTIM_BURSTMODECLOCKSOURCE_TIMER_E (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_0) /*!< Timer E counter reset/roll-over is used as clock source for the burst mode counter */
1469 #define HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1) /*!< On-chip Event 1 (BMClk[1]), acting as a burst mode counter clock */
1470 #define HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC (HRTIM_BMCR_BMCLK_2 | HRTIM_BMCR_BMCLK_1 | HRTIM_BMCR_BMCLK_0) /*!< On-chip Event 2 (BMClk[2]), acting as a burst mode counter clock */
1471 #define HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO (HRTIM_BMCR_BMCLK_3) /*!< On-chip Event 3 (BMClk[3]), acting as a burst mode counter clock */
1472 #define HRTIM_BURSTMODECLOCKSOURCE_FHRTIM (HRTIM_BMCR_BMCLK_3 | HRTIM_BMCR_BMCLK_1) /*!< Prescaled fHRTIM clock is used as clock source for the burst mode counter */
1473 /**
1474 * @}
1475 */
1477 /** @defgroup HRTIM_Burst_Mode_Prescaler HRTIM Burst Mode Prescaler
1478 * @{
1479 * @brief Constants defining the prescaling ratio of the fHRTIM clock
1480 * for the burst mode controller
1481 */
1485 #define HRTIM_BURSTMODEPRESCALER_DIV8 (HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8U */
1487 #define HRTIM_BURSTMODEPRESCALER_DIV32 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32U */
1488 #define HRTIM_BURSTMODEPRESCALER_DIV64 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/64U */
1489 #define HRTIM_BURSTMODEPRESCALER_DIV128 (HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/128U */
1491 #define HRTIM_BURSTMODEPRESCALER_DIV512 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/512U */
1492 #define HRTIM_BURSTMODEPRESCALER_DIV1024 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/1024U */
1493 #define HRTIM_BURSTMODEPRESCALER_DIV2048 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/2048U*/
1494 #define HRTIM_BURSTMODEPRESCALER_DIV4096 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2) /*!< fBRST = fHRTIM/4096U */
1495 #define HRTIM_BURSTMODEPRESCALER_DIV8192 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/8192U */
1496 #define HRTIM_BURSTMODEPRESCALER_DIV16384 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1) /*!< fBRST = fHRTIM/16384U */
1497 #define HRTIM_BURSTMODEPRESCALER_DIV32768 (HRTIM_BMCR_BMPRSC_3 | HRTIM_BMCR_BMPRSC_2 | HRTIM_BMCR_BMPRSC_1 | HRTIM_BMCR_BMPRSC_0) /*!< fBRST = fHRTIM/32768U */
1498 /**
1499 * @}
1500 */
1502 /** @defgroup HRTIM_Burst_Mode_Register_Preload_Enable HRTIM Burst Mode Register Preload Enable
1503 * @{
1504 * @brief Constants defining whether or not burst mode registers preload
1505 mechanism is enabled, i.e. a write access into a preloadable register
1506 (HRTIM_BMCMPR, HRTIM_BMPER) is done into the active or the preload register
1507 */
1508 #define HRIM_BURSTMODEPRELOAD_DISABLED (0x00000000U) /*!< Preload disabled: the write access is directly done into active registers */
1509 #define HRIM_BURSTMODEPRELOAD_ENABLED (HRTIM_BMCR_BMPREN) /*!< Preload enabled: the write access is done into preload registers */
1510 /**
1511 * @}
1512 */
1514 /** @defgroup HRTIM_Burst_Mode_Trigger HRTIM Burst Mode Trigger
1515 * @{
1516 * @brief Constants defining the events that can be used tor trig the burst
1517 * mode operation
1518 */
1521 #define HRTIM_BURSTMODETRIGGER_MASTER_REPETITION (HRTIM_BMTRGR_MSTREP) /*!< Master repetition */
1527 #define HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION (HRTIM_BMTRGR_TAREP) /*!< Timer A repetition */
1531 #define HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION (HRTIM_BMTRGR_TBREP) /*!< Timer B repetition */
1535 #define HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION (HRTIM_BMTRGR_TCREP) /*!< Timer C repetition */
1539 #define HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION (HRTIM_BMTRGR_TDREP) /*!< Timer D repetition */
1543 #define HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION (HRTIM_BMTRGR_TEREP) /*!< Timer E repetition */
1546 #define HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7 (HRTIM_BMTRGR_TAEEV7) /*!< Timer A period following External Event 7 */
1547 #define HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8 (HRTIM_BMTRGR_TDEEV8) /*!< Timer D period following External Event 8 */
1548 #define HRTIM_BURSTMODETRIGGER_EVENT_7 (HRTIM_BMTRGR_EEV7) /*!< External Event 7 (timer A filters applied) */
1549 #define HRTIM_BURSTMODETRIGGER_EVENT_8 (HRTIM_BMTRGR_EEV8) /*!< External Event 8 (timer D filters applied)*/
1551 /**
1552 * @}
1553 */
1555 /** @defgroup HRTIM_ADC_Trigger_Update_Source HRTIM ADC Trigger Update Source
1556 * @{
1557 * @brief constants defining the source triggering the update of the
1558 HRTIM_ADCxR register (transfer from preload to active register).
1559 */
1563 #define HRTIM_ADCTRIGGERUPDATE_TIMER_C (HRTIM_CR1_ADC1USRC_1 | HRTIM_CR1_ADC1USRC_0) /*!< Timer C */
1565 #define HRTIM_ADCTRIGGERUPDATE_TIMER_E (HRTIM_CR1_ADC1USRC_2 | HRTIM_CR1_ADC1USRC_0) /*!< Timer E */
1566 /**
1567 * @}
1568 */
1570 /** @defgroup HRTIM_ADC_Trigger_Event HRTIM ADC Trigger Event
1571 * @{
1572 * @brief constants defining the events triggering ADC conversion.
1573 * HRTIM_ADCTRIGGEREVENT13_*: ADC Triggers 1 and 3
1574 * HRTIM_ADCTRIGGEREVENT24_*: ADC Triggers 2 and 4
1575 */
1577 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP1 (HRTIM_ADC1R_AD1MC1) /*!< ADC Trigger on master compare 1U */
1578 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP2 (HRTIM_ADC1R_AD1MC2) /*!< ADC Trigger on master compare 2U */
1579 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP3 (HRTIM_ADC1R_AD1MC3) /*!< ADC Trigger on master compare 3U */
1580 #define HRTIM_ADCTRIGGEREVENT13_MASTER_CMP4 (HRTIM_ADC1R_AD1MC4) /*!< ADC Trigger on master compare 4U */
1581 #define HRTIM_ADCTRIGGEREVENT13_MASTER_PERIOD (HRTIM_ADC1R_AD1MPER) /*!< ADC Trigger on master period */
1582 #define HRTIM_ADCTRIGGEREVENT13_EVENT_1 (HRTIM_ADC1R_AD1EEV1) /*!< ADC Trigger on external event 1U */
1583 #define HRTIM_ADCTRIGGEREVENT13_EVENT_2 (HRTIM_ADC1R_AD1EEV2) /*!< ADC Trigger on external event 2U */
1584 #define HRTIM_ADCTRIGGEREVENT13_EVENT_3 (HRTIM_ADC1R_AD1EEV3) /*!< ADC Trigger on external event 3U */
1585 #define HRTIM_ADCTRIGGEREVENT13_EVENT_4 (HRTIM_ADC1R_AD1EEV4) /*!< ADC Trigger on external event 4U */
1586 #define HRTIM_ADCTRIGGEREVENT13_EVENT_5 (HRTIM_ADC1R_AD1EEV5) /*!< ADC Trigger on external event 5U */
1587 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP2 (HRTIM_ADC1R_AD1TAC2) /*!< ADC Trigger on Timer A compare 2U */
1588 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP3 (HRTIM_ADC1R_AD1TAC3) /*!< ADC Trigger on Timer A compare 3U */
1589 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_CMP4 (HRTIM_ADC1R_AD1TAC4) /*!< ADC Trigger on Timer A compare 4U */
1590 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_PERIOD (HRTIM_ADC1R_AD1TAPER) /*!< ADC Trigger on Timer A period */
1591 #define HRTIM_ADCTRIGGEREVENT13_TIMERA_RESET (HRTIM_ADC1R_AD1TARST) /*!< ADC Trigger on Timer A reset */
1592 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP2 (HRTIM_ADC1R_AD1TBC2) /*!< ADC Trigger on Timer B compare 2U */
1593 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP3 (HRTIM_ADC1R_AD1TBC3) /*!< ADC Trigger on Timer B compare 3U */
1594 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_CMP4 (HRTIM_ADC1R_AD1TBC4) /*!< ADC Trigger on Timer B compare 4U */
1595 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_PERIOD (HRTIM_ADC1R_AD1TBPER) /*!< ADC Trigger on Timer B period */
1596 #define HRTIM_ADCTRIGGEREVENT13_TIMERB_RESET (HRTIM_ADC1R_AD1TBRST) /*!< ADC Trigger on Timer B reset */
1597 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP2 (HRTIM_ADC1R_AD1TCC2) /*!< ADC Trigger on Timer C compare 2U */
1598 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP3 (HRTIM_ADC1R_AD1TCC3) /*!< ADC Trigger on Timer C compare 3U */
1599 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_CMP4 (HRTIM_ADC1R_AD1TCC4) /*!< ADC Trigger on Timer C compare 4U */
1600 #define HRTIM_ADCTRIGGEREVENT13_TIMERC_PERIOD (HRTIM_ADC1R_AD1TCPER) /*!< ADC Trigger on Timer C period */
1601 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP2 (HRTIM_ADC1R_AD1TDC2) /*!< ADC Trigger on Timer D compare 2U */
1602 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP3 (HRTIM_ADC1R_AD1TDC3) /*!< ADC Trigger on Timer D compare 3U */
1603 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_CMP4 (HRTIM_ADC1R_AD1TDC4) /*!< ADC Trigger on Timer D compare 4U */
1604 #define HRTIM_ADCTRIGGEREVENT13_TIMERD_PERIOD (HRTIM_ADC1R_AD1TDPER) /*!< ADC Trigger on Timer D period */
1605 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP2 (HRTIM_ADC1R_AD1TEC2) /*!< ADC Trigger on Timer E compare 2U */
1606 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP3 (HRTIM_ADC1R_AD1TEC3) /*!< ADC Trigger on Timer E compare 3U */
1607 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_CMP4 (HRTIM_ADC1R_AD1TEC4) /*!< ADC Trigger on Timer E compare 4U */
1608 #define HRTIM_ADCTRIGGEREVENT13_TIMERE_PERIOD (HRTIM_ADC1R_AD1TEPER) /*!< ADC Trigger on Timer E period */
1611 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP1 (HRTIM_ADC2R_AD2MC1) /*!< ADC Trigger on master compare 1U */
1612 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP2 (HRTIM_ADC2R_AD2MC2) /*!< ADC Trigger on master compare 2U */
1613 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP3 (HRTIM_ADC2R_AD2MC3) /*!< ADC Trigger on master compare 3U */
1614 #define HRTIM_ADCTRIGGEREVENT24_MASTER_CMP4 (HRTIM_ADC2R_AD2MC4) /*!< ADC Trigger on master compare 4U */
1615 #define HRTIM_ADCTRIGGEREVENT24_MASTER_PERIOD (HRTIM_ADC2R_AD2MPER) /*!< ADC Trigger on master period */
1616 #define HRTIM_ADCTRIGGEREVENT24_EVENT_6 (HRTIM_ADC2R_AD2EEV6) /*!< ADC Trigger on external event 6U */
1617 #define HRTIM_ADCTRIGGEREVENT24_EVENT_7 (HRTIM_ADC2R_AD2EEV7) /*!< ADC Trigger on external event 7U */
1618 #define HRTIM_ADCTRIGGEREVENT24_EVENT_8 (HRTIM_ADC2R_AD2EEV8) /*!< ADC Trigger on external event 8U */
1619 #define HRTIM_ADCTRIGGEREVENT24_EVENT_9 (HRTIM_ADC2R_AD2EEV9) /*!< ADC Trigger on external event 9U */
1620 #define HRTIM_ADCTRIGGEREVENT24_EVENT_10 (HRTIM_ADC2R_AD2EEV10) /*!< ADC Trigger on external event 10U */
1621 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP2 (HRTIM_ADC2R_AD2TAC2) /*!< ADC Trigger on Timer A compare 2U */
1622 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP3 (HRTIM_ADC2R_AD2TAC3) /*!< ADC Trigger on Timer A compare 3U */
1623 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_CMP4 (HRTIM_ADC2R_AD2TAC4) /*!< ADC Trigger on Timer A compare 4U */
1624 #define HRTIM_ADCTRIGGEREVENT24_TIMERA_PERIOD (HRTIM_ADC2R_AD2TAPER) /*!< ADC Trigger on Timer A period */
1625 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP2 (HRTIM_ADC2R_AD2TBC2) /*!< ADC Trigger on Timer B compare 2U */
1626 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP3 (HRTIM_ADC2R_AD2TBC3) /*!< ADC Trigger on Timer B compare 3U */
1627 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_CMP4 (HRTIM_ADC2R_AD2TBC4) /*!< ADC Trigger on Timer B compare 4U */
1628 #define HRTIM_ADCTRIGGEREVENT24_TIMERB_PERIOD (HRTIM_ADC2R_AD2TBPER) /*!< ADC Trigger on Timer B period */
1629 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP2 (HRTIM_ADC2R_AD2TCC2) /*!< ADC Trigger on Timer C compare 2U */
1630 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP3 (HRTIM_ADC2R_AD2TCC3) /*!< ADC Trigger on Timer C compare 3U */
1631 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_CMP4 (HRTIM_ADC2R_AD2TCC4) /*!< ADC Trigger on Timer C compare 4U */
1632 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_PERIOD (HRTIM_ADC2R_AD2TCPER) /*!< ADC Trigger on Timer C period */
1633 #define HRTIM_ADCTRIGGEREVENT24_TIMERC_RESET (HRTIM_ADC2R_AD2TCRST) /*!< ADC Trigger on Timer C reset */
1634 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP2 (HRTIM_ADC2R_AD2TDC2) /*!< ADC Trigger on Timer D compare 2U */
1635 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP3 (HRTIM_ADC2R_AD2TDC3) /*!< ADC Trigger on Timer D compare 3U */
1636 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_CMP4 (HRTIM_ADC2R_AD2TDC4) /*!< ADC Trigger on Timer D compare 4U */
1637 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_PERIOD (HRTIM_ADC2R_AD2TDPER) /*!< ADC Trigger on Timer D period */
1638 #define HRTIM_ADCTRIGGEREVENT24_TIMERD_RESET (HRTIM_ADC2R_AD2TDRST) /*!< ADC Trigger on Timer D reset */
1639 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP2 (HRTIM_ADC2R_AD2TEC2) /*!< ADC Trigger on Timer E compare 2U */
1640 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP3 (HRTIM_ADC2R_AD2TEC3) /*!< ADC Trigger on Timer E compare 3U */
1641 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_CMP4 (HRTIM_ADC2R_AD2TEC4) /*!< ADC Trigger on Timer E compare 4U */
1642 #define HRTIM_ADCTRIGGEREVENT24_TIMERE_RESET (HRTIM_ADC2R_AD2TERST) /*!< ADC Trigger on Timer E reset */
1644 /**
1645 * @}
1646 */
1648 /** @defgroup HRTIM_DLL_Calibration_Rate HRTIM DLL Calibration Rate
1649 * @{
1650 * @brief Constants defining the DLL calibration periods (in micro seconds)
1651 */
1653 #define HRTIM_CALIBRATIONRATE_7300 0x00000000U /*!< Periodic DLL calibration: T = 1048576U * tHRTIM (7.3 ms) */
1654 #define HRTIM_CALIBRATIONRATE_910 (HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 131072U * tHRTIM (910 ms) */
1655 #define HRTIM_CALIBRATIONRATE_114 (HRTIM_DLLCR_CALRTE_1) /*!< Periodic DLL calibration: T = 16384U * tHRTIM (114 ms) */
1656 #define HRTIM_CALIBRATIONRATE_14 (HRTIM_DLLCR_CALRTE_1 | HRTIM_DLLCR_CALRTE_0) /*!< Periodic DLL calibration: T = 2048U * tHRTIM (14 ms) */
1657 /**
1658 * @}
1659 */
1661 /** @defgroup HRTIM_Burst_DMA_Registers_Update HRTIM Burst DMA Registers Update
1662 * @{
1663 * @brief Constants defining the registers that can be written during a burst
1664 * DMA operation
1665 */
1667 #define HRTIM_BURSTDMA_CR (HRTIM_BDTUPR_TIMCR) /*!< MCR or TIMxCR register is updated by Burst DMA accesses */
1668 #define HRTIM_BURSTDMA_ICR (HRTIM_BDTUPR_TIMICR) /*!< MICR or TIMxICR register is updated by Burst DMA accesses */
1669 #define HRTIM_BURSTDMA_DIER (HRTIM_BDTUPR_TIMDIER) /*!< MDIER or TIMxDIER register is updated by Burst DMA accesses */
1670 #define HRTIM_BURSTDMA_CNT (HRTIM_BDTUPR_TIMCNT) /*!< MCNTR or CNTxCR register is updated by Burst DMA accesses */
1671 #define HRTIM_BURSTDMA_PER (HRTIM_BDTUPR_TIMPER) /*!< MPER or PERxR register is updated by Burst DMA accesses */
1672 #define HRTIM_BURSTDMA_REP (HRTIM_BDTUPR_TIMREP) /*!< MREPR or REPxR register is updated by Burst DMA accesses */
1673 #define HRTIM_BURSTDMA_CMP1 (HRTIM_BDTUPR_TIMCMP1) /*!< MCMP1R or CMP1xR register is updated by Burst DMA accesses */
1674 #define HRTIM_BURSTDMA_CMP2 (HRTIM_BDTUPR_TIMCMP2) /*!< MCMP2R or CMP2xR register is updated by Burst DMA accesses */
1675 #define HRTIM_BURSTDMA_CMP3 (HRTIM_BDTUPR_TIMCMP3) /*!< MCMP3R or CMP3xR register is updated by Burst DMA accesses */
1676 #define HRTIM_BURSTDMA_CMP4 (HRTIM_BDTUPR_TIMCMP4) /*!< MCMP4R or CMP4xR register is updated by Burst DMA accesses */
1677 #define HRTIM_BURSTDMA_DTR (HRTIM_BDTUPR_TIMDTR) /*!< TDxR register is updated by Burst DMA accesses */
1678 #define HRTIM_BURSTDMA_SET1R (HRTIM_BDTUPR_TIMSET1R) /*!< SET1R register is updated by Burst DMA accesses */
1679 #define HRTIM_BURSTDMA_RST1R (HRTIM_BDTUPR_TIMRST1R) /*!< RST1R register is updated by Burst DMA accesses */
1680 #define HRTIM_BURSTDMA_SET2R (HRTIM_BDTUPR_TIMSET2R) /*!< SET2R register is updated by Burst DMA accesses */
1681 #define HRTIM_BURSTDMA_RST2R (HRTIM_BDTUPR_TIMRST2R) /*!< RST1R register is updated by Burst DMA accesses */
1682 #define HRTIM_BURSTDMA_EEFR1 (HRTIM_BDTUPR_TIMEEFR1) /*!< EEFxR1 register is updated by Burst DMA accesses */
1683 #define HRTIM_BURSTDMA_EEFR2 (HRTIM_BDTUPR_TIMEEFR2) /*!< EEFxR2 register is updated by Burst DMA accesses */
1684 #define HRTIM_BURSTDMA_RSTR (HRTIM_BDTUPR_TIMRSTR) /*!< RSTxR register is updated by Burst DMA accesses */
1685 #define HRTIM_BURSTDMA_CHPR (HRTIM_BDTUPR_TIMCHPR) /*!< CHPxR register is updated by Burst DMA accesses */
1686 #define HRTIM_BURSTDMA_OUTR (HRTIM_BDTUPR_TIMOUTR) /*!< OUTxR register is updated by Burst DMA accesses */
1687 #define HRTIM_BURSTDMA_FLTR (HRTIM_BDTUPR_TIMFLTR) /*!< FLTxR register is updated by Burst DMA accesses */
1688 /**
1689 * @}
1690 */
1692 /** @defgroup HRTIM_Burst_Mode_Control HRTIM Burst Mode Control
1693 * @{
1694 * @brief Constants used to enable or disable the burst mode controller
1695 */
1698 /**
1699 * @}
1700 */
1702 /** @defgroup HRTIM_Fault_Mode_Control HRTIM Fault Mode Control
1703 * @{
1704 * @brief Constants used to enable or disable a fault channel
1705 */
1709 #define IS_HRTIM_FAULTMODECTL(FAULTMODECTL)\
1710 (((FAULTMODECTL) == HRTIM_FAULTMODECTL_DISABLED) || \
1711 ((FAULTMODECTL) == HRTIM_FAULTMODECTL_ENABLED))
1712 /**
1713 * @}
1714 */
1716 /** @defgroup HRTIM_Software_Timer_Update HRTIM Software Timer Update
1717 * @{
1718 * @brief Constants used to force timer registers update
1719 */
1720 #define HRTIM_TIMERUPDATE_MASTER (HRTIM_CR2_MSWU) /*!< Forces an immediate transfer from the preload to the active register in the master timer */
1721 #define HRTIM_TIMERUPDATE_A (HRTIM_CR2_TASWU) /*!< Forces an immediate transfer from the preload to the active register in the timer A */
1722 #define HRTIM_TIMERUPDATE_B (HRTIM_CR2_TBSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer B */
1723 #define HRTIM_TIMERUPDATE_C (HRTIM_CR2_TCSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer C */
1724 #define HRTIM_TIMERUPDATE_D (HRTIM_CR2_TDSWU) /*!< Forces an immediate transfer from the preload to the active register in the timer D */
1725 #define HRTIM_TIMERUPDATE_E (HRTIM_CR2_TESWU) /*!< Forces an immediate transfer from the preload to the active register in the timer E */
1726 /**
1727 * @}
1728 */
1730 /** @defgroup HRTIM_Software_Timer_Reset HRTIM Software Timer Reset
1731 * @{
1732 * @brief Constants used to force timer counter reset
1733 */
1740 /**
1741 * @}
1742 */
1744 /** @defgroup HRTIM_Output_Level HRTIM Output Level
1745 * @{
1746 * @brief Constants defining the level of a timer output
1747 */
1749 #define HRTIM_OUTPUTLEVEL_INACTIVE (0x00000002U) /*!< Forces the output to its inactive state */
1751 #define IS_HRTIM_OUTPUTLEVEL(OUTPUTLEVEL)\
1752 (((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_ACTIVE) || \
1753 ((OUTPUTLEVEL) == HRTIM_OUTPUTLEVEL_INACTIVE))
1754 /**
1755 * @}
1756 */
1758 /** @defgroup HRTIM_Output_State HRTIM Output State
1759 * @{
1760 * @brief Constants defining the state of a timer output
1761 */
1762 #define HRTIM_OUTPUTSTATE_IDLE (0x00000001U) /*!< Main operating mode, where the output can take the active or
1763 inactive level as programmed in the crossbar unit */
1764 #define HRTIM_OUTPUTSTATE_RUN (0x00000002U) /*!< Default operating state (e.g. after an HRTIM reset, when the
1765 outputs are disabled by software or during a burst mode operation */
1766 #define HRTIM_OUTPUTSTATE_FAULT (0x00000003U) /*!< Safety state, entered in case of a shut-down request on
1767 FAULTx inputs */
1768 /**
1769 * @}
1770 */
1772 /** @defgroup HRTIM_Burst_Mode_Status HRTIM Burst Mode Status
1773 * @{
1774 * @brief Constants defining the operating state of the burst mode controller
1775 */
1778 /**
1779 * @}
1780 */
1782 /** @defgroup HRTIM_Current_Push_Pull_Status HRTIM Current Push Pull Status
1783 * @{
1784 * @brief Constants defining on which output the signal is currently applied
1785 * in push-pull mode
1786 */
1787 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT1 0x00000000U /*!< Signal applied on output 1 and output 2 forced inactive */
1788 #define HRTIM_PUSHPULL_CURRENTSTATUS_OUTPUT2 (HRTIM_TIMISR_CPPSTAT) /*!< Signal applied on output 2 and output 1 forced inactive */
1789 /**
1790 * @}
1791 */
1793 /** @defgroup HRTIM_Idle_Push_Pull_Status HRTIM Idle Push Pull Status
1794 * @{
1795 * @brief Constants defining on which output the signal was applied, in
1796 * push-pull mode balanced fault mode or delayed idle mode, when the
1797 * protection was triggered
1798 */
1799 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT1 0x00000000U /*!< Protection occurred when the output 1 was active and output 2 forced inactive */
1800 #define HRTIM_PUSHPULL_IDLESTATUS_OUTPUT2 (HRTIM_TIMISR_IPPSTAT) /*!< Protection occurred when the output 2 was active and output 1 forced inactive */
1801 /**
1802 * @}
1803 */
1805 /** @defgroup HRTIM_Common_Interrupt_Enable HRTIM Common Interrupt Enable
1806 * @{
1807 */
1817 /**
1818 * @}
1819 */
1821 /** @defgroup HRTIM_Master_Interrupt_Enable HRTIM Master Interrupt Enable
1822 * @{
1823 */
1832 /**
1833 * @}
1834 */
1836 /** @defgroup HRTIM_Timing_Unit_Interrupt_Enable HRTIM Timing Unit Interrupt Enable
1837 * @{
1838 */
1853 #define HRTIM_TIM_IT_DLYPRT HRTIM_TIMDIER_DLYPRTIE /*!< Timer delay protection interrupt enable */
1854 /**
1855 * @}
1856 */
1858 /** @defgroup HRTIM_Common_Interrupt_Flag HRTIM Common Interrupt Flag
1859 * @{
1860 */
1869 /**
1870 * @}
1871 */
1873 /** @defgroup HRTIM_Master_Interrupt_Flag HRTIM Master Interrupt Flag
1874 * @{
1875 */
1883 /**
1884 * @}
1885 */
1887 /** @defgroup HRTIM_Timing_Unit_Interrupt_Flag HRTIM Timing Unit Interrupt Flag
1888 * @{
1889 */
1903 #define HRTIM_TIM_FLAG_DLYPRT HRTIM_TIMISR_DLYPRT /*!< Timer delay protection interrupt flag */
1904 /**
1905 * @}
1906 */
1908 /** @defgroup HRTIM_Master_DMA_Request_Enable HRTIM Master DMA Request Enable
1909 * @{
1910 */
1917 #define HRTIM_MASTER_DMA_SYNC HRTIM_MDIER_SYNCDE /*!< Synchronization input DMA request enable */
1919 /**
1920 * @}
1921 */
1923 /** @defgroup HRTIM_Timing_Unit_DMA_Request_Enable HRTIM Timing Unit DMA Request Enable
1924 * @{
1925 */
1936 #define HRTIM_TIM_DMA_RST1 HRTIM_TIMDIER_RST1DE /*!< Timer output 1 reset DMA request enable */
1938 #define HRTIM_TIM_DMA_RST2 HRTIM_TIMDIER_RST2DE /*!< Timer output 2 reset DMA request enable */
1940 #define HRTIM_TIM_DMA_DLYPRT HRTIM_TIMDIER_DLYPRTDE /*!< Timer delay protection DMA request enable */
1941 /**
1942 * @}
1943 */
1945 /**
1946 * @}
1947 */
1949 /* Private macros --------------------------------------------------------*/
1950 /** @addtogroup HRTIM_Private_Macros HRTIM Private Macros
1951 * @{
1952 */
1954 #define IS_HRTIM_TIMERINDEX(TIMERINDEX)\
1955 (((TIMERINDEX) == HRTIM_TIMERINDEX_MASTER) || \
1956 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
1957 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
1958 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
1959 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
1960 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
1962 #define IS_HRTIM_TIMING_UNIT(TIMERINDEX)\
1963 (((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_A) || \
1964 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_B) || \
1965 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_C) || \
1966 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_D) || \
1967 ((TIMERINDEX) == HRTIM_TIMERINDEX_TIMER_E))
1969 #define IS_HRTIM_TIMERID(TIMERID) (((TIMERID) & 0xFFC0FFFFU) == 0x00000000U)
1971 #define IS_HRTIM_COMPAREUNIT(COMPAREUNIT)\
1972 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_1) || \
1973 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) || \
1974 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_3) || \
1975 ((COMPAREUNIT) == HRTIM_COMPAREUNIT_4))
1977 #define IS_HRTIM_CAPTUREUNIT(CAPTUREUNIT)\
1978 (((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_1) || \
1979 ((CAPTUREUNIT) == HRTIM_CAPTUREUNIT_2))
1981 #define IS_HRTIM_OUTPUT(OUTPUT) (((OUTPUT) & 0xFFFFFC00U) == 0x00000000U)
1983 #define IS_HRTIM_TIMER_OUTPUT(TIMER, OUTPUT)\
1984 ((((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
1985 (((OUTPUT) == HRTIM_OUTPUT_TA1) || \
1986 ((OUTPUT) == HRTIM_OUTPUT_TA2))) \
1987 || \
1988 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
1989 (((OUTPUT) == HRTIM_OUTPUT_TB1) || \
1990 ((OUTPUT) == HRTIM_OUTPUT_TB2))) \
1991 || \
1992 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
1993 (((OUTPUT) == HRTIM_OUTPUT_TC1) || \
1994 ((OUTPUT) == HRTIM_OUTPUT_TC2))) \
1995 || \
1996 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
1997 (((OUTPUT) == HRTIM_OUTPUT_TD1) || \
1998 ((OUTPUT) == HRTIM_OUTPUT_TD2))) \
1999 || \
2000 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
2001 (((OUTPUT) == HRTIM_OUTPUT_TE1) || \
2002 ((OUTPUT) == HRTIM_OUTPUT_TE2))))
2004 #define IS_HRTIM_EVENT(EVENT)\
2005 (((EVENT) == HRTIM_EVENT_1) || \
2006 ((EVENT) == HRTIM_EVENT_2) || \
2007 ((EVENT) == HRTIM_EVENT_3) || \
2008 ((EVENT) == HRTIM_EVENT_4) || \
2009 ((EVENT) == HRTIM_EVENT_5) || \
2010 ((EVENT) == HRTIM_EVENT_6) || \
2011 ((EVENT) == HRTIM_EVENT_7) || \
2012 ((EVENT) == HRTIM_EVENT_8) || \
2013 ((EVENT) == HRTIM_EVENT_9) || \
2014 ((EVENT) == HRTIM_EVENT_10))
2016 #define IS_HRTIM_FAULT(FAULT)\
2017 (((FAULT) == HRTIM_FAULT_1) || \
2018 ((FAULT) == HRTIM_FAULT_2) || \
2019 ((FAULT) == HRTIM_FAULT_3) || \
2020 ((FAULT) == HRTIM_FAULT_4) || \
2021 ((FAULT) == HRTIM_FAULT_5))
2023 #define IS_HRTIM_PRESCALERRATIO(PRESCALERRATIO)\
2024 (((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL32) || \
2025 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL16) || \
2026 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL8) || \
2027 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL4) || \
2028 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_MUL2) || \
2029 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV1) || \
2030 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV2) || \
2031 ((PRESCALERRATIO) == HRTIM_PRESCALERRATIO_DIV4))
2033 #define IS_HRTIM_MODE(MODE)\
2034 (((MODE) == HRTIM_MODE_CONTINUOUS) || \
2035 ((MODE) == HRTIM_MODE_SINGLESHOT) || \
2036 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
2038 #define IS_HRTIM_MODE_ONEPULSE(MODE)\
2039 (((MODE) == HRTIM_MODE_SINGLESHOT) || \
2040 ((MODE) == HRTIM_MODE_SINGLESHOT_RETRIGGERABLE))
2043 #define IS_HRTIM_HALFMODE(HALFMODE)\
2044 (((HALFMODE) == HRTIM_HALFMODE_DISABLED) || \
2045 ((HALFMODE) == HRTIM_HALFMODE_ENABLED))
2047 #define IS_HRTIM_SYNCSTART(SYNCSTART)\
2048 (((SYNCSTART) == HRTIM_SYNCSTART_DISABLED) || \
2049 ((SYNCSTART) == HRTIM_SYNCSTART_ENABLED))
2051 #define IS_HRTIM_SYNCRESET(SYNCRESET)\
2052 (((SYNCRESET) == HRTIM_SYNCRESET_DISABLED) || \
2053 ((SYNCRESET) == HRTIM_SYNCRESET_ENABLED))
2055 #define IS_HHRTIM_DACSYNC(DACSYNC)\
2056 (((DACSYNC) == HRTIM_DACSYNC_NONE) || \
2057 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_1) || \
2058 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_2) || \
2059 ((DACSYNC) == HRTIM_DACSYNC_DACTRIGOUT_3))
2061 #define IS_HRTIM_PRELOAD(PRELOAD)\
2062 (((PRELOAD) == HRTIM_PRELOAD_DISABLED) || \
2063 ((PRELOAD) == HRTIM_PRELOAD_ENABLED))
2065 #define IS_HRTIM_UPDATEGATING_MASTER(UPDATEGATING)\
2066 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
2067 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
2068 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE))
2070 #define IS_HRTIM_UPDATEGATING_TIM(UPDATEGATING)\
2071 (((UPDATEGATING) == HRTIM_UPDATEGATING_INDEPENDENT) || \
2072 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST) || \
2073 ((UPDATEGATING) == HRTIM_UPDATEGATING_DMABURST_UPDATE) || \
2074 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1) || \
2075 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2) || \
2076 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3) || \
2077 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN1_UPDATE) || \
2078 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN2_UPDATE) || \
2079 ((UPDATEGATING) == HRTIM_UPDATEGATING_UPDEN3_UPDATE))
2081 #define IS_HRTIM_TIMERBURSTMODE(TIMERBURSTMODE) \
2082 (((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_MAINTAINCLOCK) || \
2083 ((TIMERBURSTMODE) == HRTIM_TIMERBURSTMODE_RESETCOUNTER))
2085 #define IS_HRTIM_UPDATEONREPETITION(UPDATEONREPETITION) \
2086 (((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_DISABLED) || \
2087 ((UPDATEONREPETITION) == HRTIM_UPDATEONREPETITION_ENABLED))
2089 #define IS_HRTIM_TIMPUSHPULLMODE(TIMPUSHPULLMODE)\
2090 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) || \
2091 ((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED))
2093 #define IS_HRTIM_TIMFAULTENABLE(TIMFAULTENABLE) (((TIMFAULTENABLE) & 0xFFFFFFE0U) == 0x00000000U)
2096 #define IS_HRTIM_TIMFAULTLOCK(TIMFAULTLOCK)\
2097 (((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READWRITE) || \
2098 ((TIMFAULTLOCK) == HRTIM_TIMFAULTLOCK_READONLY))
2100 #define IS_HRTIM_TIMDEADTIMEINSERTION(TIMPUSHPULLMODE, TIMDEADTIMEINSERTION)\
2101 ((((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_DISABLED) && \
2102 ((((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED) || \
2103 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_ENABLED)))) \
2104 || \
2105 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
2106 ((TIMDEADTIMEINSERTION) == HRTIM_TIMDEADTIMEINSERTION_DISABLED)))
2108 #define IS_HRTIM_TIMDELAYEDPROTECTION(TIMPUSHPULLMODE, TIMDELAYEDPROTECTION)\
2109 ((((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DISABLED) || \
2110 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_EEV6) || \
2111 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_EEV6) || \
2112 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV6) || \
2113 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT1_DEEV7) || \
2114 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7) || \
2115 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7)) \
2116 || \
2117 (((TIMPUSHPULLMODE) == HRTIM_TIMPUSHPULLMODE_ENABLED) && \
2118 (((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV6) || \
2119 ((TIMDELAYEDPROTECTION) == HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7))))
2121 #define IS_HRTIM_TIMUPDATETRIGGER(TIMUPDATETRIGGER) (((TIMUPDATETRIGGER) & 0xFE07FFFFU) == 0x00000000U)
2123 #define IS_HRTIM_TIMRESETTRIGGER(TIMRESETTRIGGER) (((TIMRESETTRIGGER) & 0x800000001U) == 0x00000000U)
2126 #define IS_HRTIM_TIMUPDATEONRESET(TIMUPDATEONRESET) \
2127 (((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_DISABLED) || \
2128 ((TIMUPDATEONRESET) == HRTIM_TIMUPDATEONRESET_ENABLED))
2130 #define IS_HRTIM_AUTODELAYEDMODE(AUTODELAYEDMODE)\
2131 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
2132 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
2133 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
2134 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))
2136 /* Auto delayed mode is only available for compare units 2 and 4U */
2137 #define IS_HRTIM_COMPAREUNIT_AUTODELAYEDMODE(COMPAREUNIT, AUTODELAYEDMODE) \
2138 ((((COMPAREUNIT) == HRTIM_COMPAREUNIT_2) && \
2139 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
2140 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
2141 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
2142 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))) \
2143 || \
2144 (((COMPAREUNIT) == HRTIM_COMPAREUNIT_4) && \
2145 (((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_REGULAR) || \
2146 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_NOTIMEOUT) || \
2147 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP1) || \
2148 ((AUTODELAYEDMODE) == HRTIM_AUTODELAYEDMODE_AUTODELAYED_TIMEOUTCMP3))))
2150 #define IS_HRTIM_OUTPUTPOLARITY(OUTPUTPOLARITY)\
2151 (((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_HIGH) || \
2152 ((OUTPUTPOLARITY) == HRTIM_OUTPUTPOLARITY_LOW))
2154 #define IS_HRTIM_OUTPUTSET(OUTPUTSET)\
2155 (((OUTPUTSET) == HRTIM_OUTPUTSET_NONE) || \
2156 ((OUTPUTSET) == HRTIM_OUTPUTSET_RESYNC) || \
2157 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMPER) || \
2158 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP1) || \
2159 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP2) || \
2160 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP3) || \
2161 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMCMP4) || \
2162 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERPER) || \
2163 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP1) || \
2164 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP2) || \
2165 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP3) || \
2166 ((OUTPUTSET) == HRTIM_OUTPUTSET_MASTERCMP4) || \
2167 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_1) || \
2168 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_2) || \
2169 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_3) || \
2170 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_4) || \
2171 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_5) || \
2172 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_6) || \
2173 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_7) || \
2174 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_8) || \
2175 ((OUTPUTSET) == HRTIM_OUTPUTSET_TIMEV_9) || \
2176 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_1) || \
2177 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_2) || \
2178 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_3) || \
2179 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_4) || \
2180 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_5) || \
2181 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_6) || \
2182 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_7) || \
2183 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_8) || \
2184 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_9) || \
2185 ((OUTPUTSET) == HRTIM_OUTPUTSET_EEV_10) || \
2186 ((OUTPUTSET) == HRTIM_OUTPUTSET_UPDATE))
2188 #define IS_HRTIM_OUTPUTRESET(OUTPUTRESET)\
2189 (((OUTPUTRESET) == HRTIM_OUTPUTRESET_NONE) || \
2190 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_RESYNC) || \
2191 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMPER) || \
2192 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP1) || \
2193 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP2) || \
2194 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP3) || \
2195 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMCMP4) || \
2196 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERPER) || \
2197 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP1) || \
2198 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP2) || \
2199 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP3) || \
2200 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_MASTERCMP4) || \
2201 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_1) || \
2202 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_2) || \
2203 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_3) || \
2204 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_4) || \
2205 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_5) || \
2206 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_6) || \
2207 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_7) || \
2208 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_8) || \
2209 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_TIMEV_9) || \
2210 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_1) || \
2211 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_2) || \
2212 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_3) || \
2213 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_4) || \
2214 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_5) || \
2215 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_6) || \
2216 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_7) || \
2217 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_8) || \
2218 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_9) || \
2219 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_EEV_10) || \
2220 ((OUTPUTRESET) == HRTIM_OUTPUTRESET_UPDATE))
2222 #define IS_HRTIM_OUTPUTIDLEMODE(OUTPUTIDLEMODE)\
2223 (((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_NONE) || \
2224 ((OUTPUTIDLEMODE) == HRTIM_OUTPUTIDLEMODE_IDLE))
2226 #define IS_HRTIM_OUTPUTIDLELEVEL(OUTPUTIDLELEVEL)\
2227 (((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_INACTIVE) || \
2228 ((OUTPUTIDLELEVEL) == HRTIM_OUTPUTIDLELEVEL_ACTIVE))
2230 #define IS_HRTIM_OUTPUTFAULTLEVEL(OUTPUTFAULTLEVEL)\
2231 (((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_NONE) || \
2232 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_ACTIVE) || \
2233 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_INACTIVE) || \
2234 ((OUTPUTFAULTLEVEL) == HRTIM_OUTPUTFAULTLEVEL_HIGHZ))
2236 #define IS_HRTIM_OUTPUTCHOPPERMODE(OUTPUTCHOPPERMODE)\
2237 (((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_DISABLED) || \
2238 ((OUTPUTCHOPPERMODE) == HRTIM_OUTPUTCHOPPERMODE_ENABLED))
2240 #define IS_HRTIM_OUTPUTBURSTMODEENTRY(OUTPUTBURSTMODEENTRY)\
2241 (((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_REGULAR) || \
2242 ((OUTPUTBURSTMODEENTRY) == HRTIM_OUTPUTBURSTMODEENTRY_DELAYED))
2244 #define IS_HRTIM_TIMER_CAPTURETRIGGER(TIMER, CAPTURETRIGGER) \
2245 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_NONE) || \
2246 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_UPDATE) || \
2247 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_1) || \
2248 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_2) || \
2249 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_3) || \
2250 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_4) || \
2251 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_5) || \
2252 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_6) || \
2253 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_7) || \
2254 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_8) || \
2255 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_9) || \
2256 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_EEV_10) \
2257 || \
2258 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && \
2259 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
2260 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
2261 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
2262 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
2263 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
2264 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
2265 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
2266 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
2267 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
2268 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
2269 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
2270 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
2271 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
2272 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
2273 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
2274 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
2275 || \
2276 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && \
2277 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
2278 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
2279 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
2280 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
2281 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
2282 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
2283 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
2284 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
2285 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
2286 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
2287 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
2288 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
2289 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
2290 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
2291 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
2292 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
2293 || \
2294 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && \
2295 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
2296 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
2297 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
2298 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
2299 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
2300 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
2301 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
2302 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
2303 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
2304 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
2305 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
2306 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2) || \
2307 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
2308 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
2309 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
2310 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
2311 || \
2312 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && \
2313 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
2314 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
2315 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
2316 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
2317 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
2318 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
2319 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
2320 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
2321 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
2322 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
2323 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
2324 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
2325 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_SET) || \
2326 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TE1_RESET) || \
2327 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP1) || \
2328 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERE_CMP2))) \
2329 || \
2330 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && \
2331 (((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_SET) || \
2332 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TA1_RESET) || \
2333 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP1) || \
2334 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERA_CMP2) || \
2335 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_SET) || \
2336 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TB1_RESET) || \
2337 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP1) || \
2338 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERB_CMP2) || \
2339 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_SET) || \
2340 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TC1_RESET) || \
2341 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP1) || \
2342 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERC_CMP2) || \
2343 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_SET) || \
2344 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TD1_RESET) || \
2345 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP1) || \
2346 ((CAPTURETRIGGER) == HRTIM_CAPTURETRIGGER_TIMERD_CMP2))))
2348 #define IS_HRTIM_TIMEVENTFILTER(TIMEVENTFILTER)\
2349 (((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_NONE) || \
2350 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP1) || \
2351 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP2) || \
2352 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP3) || \
2353 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGCMP4) || \
2354 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR1) || \
2355 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR2) || \
2356 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR3) || \
2357 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR4) || \
2358 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR5) || \
2359 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR6) || \
2360 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR7) || \
2361 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_BLANKINGFLTR8) || \
2362 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP2) || \
2363 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGCMP3) || \
2364 ((TIMEVENTFILTER) == HRTIM_TIMEVENTFILTER_WINDOWINGTIM))
2366 #define IS_HRTIM_TIMEVENTLATCH(TIMEVENTLATCH)\
2367 (((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_DISABLED) || \
2368 ((TIMEVENTLATCH) == HRTIM_TIMEVENTLATCH_ENABLED))
2370 #define IS_HRTIM_TIMDEADTIME_PRESCALERRATIO(PRESCALERRATIO)\
2371 (((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL8) || \
2372 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL4) || \
2373 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_MUL2) || \
2374 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV1) || \
2375 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV2) || \
2376 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV4) || \
2377 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV8) || \
2378 ((PRESCALERRATIO) == HRTIM_TIMDEADTIME_PRESCALERRATIO_DIV16))
2380 #define IS_HRTIM_TIMDEADTIME_RISINGSIGN(RISINGSIGN)\
2381 (((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_POSITIVE) || \
2382 ((RISINGSIGN) == HRTIM_TIMDEADTIME_RISINGSIGN_NEGATIVE))
2384 #define IS_HRTIM_TIMDEADTIME_RISINGLOCK(RISINGLOCK)\
2385 (((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_WRITE) || \
2386 ((RISINGLOCK) == HRTIM_TIMDEADTIME_RISINGLOCK_READONLY))
2388 #define IS_HRTIM_TIMDEADTIME_RISINGSIGNLOCK(RISINGSIGNLOCK)\
2389 (((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_WRITE) || \
2390 ((RISINGSIGNLOCK) == HRTIM_TIMDEADTIME_RISINGSIGNLOCK_READONLY))
2392 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGN(FALLINGSIGN)\
2393 (((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_POSITIVE) || \
2394 ((FALLINGSIGN) == HRTIM_TIMDEADTIME_FALLINGSIGN_NEGATIVE))
2396 #define IS_HRTIM_TIMDEADTIME_FALLINGLOCK(FALLINGLOCK)\
2397 (((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_WRITE) || \
2398 ((FALLINGLOCK) == HRTIM_TIMDEADTIME_FALLINGLOCK_READONLY))
2400 #define IS_HRTIM_TIMDEADTIME_FALLINGSIGNLOCK(FALLINGSIGNLOCK)\
2401 (((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_WRITE) || \
2402 ((FALLINGSIGNLOCK) == HRTIM_TIMDEADTIME_FALLINGSIGNLOCK_READONLY))
2404 #define IS_HRTIM_CHOPPER_PRESCALERRATIO(PRESCALERRATIO)\
2405 (((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV16) || \
2406 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV32) || \
2407 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV48) || \
2408 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV64) || \
2409 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV80) || \
2410 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV96) || \
2411 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV112) || \
2412 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV128) || \
2413 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV144) || \
2414 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV160) || \
2415 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV176) || \
2416 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV192) || \
2417 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV208) || \
2418 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV224) || \
2419 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV240) || \
2420 ((PRESCALERRATIO) == HRTIM_CHOPPER_PRESCALERRATIO_DIV256))
2422 #define IS_HRTIM_CHOPPER_DUTYCYCLE(DUTYCYCLE)\
2423 (((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_0) || \
2424 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_125) || \
2425 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_250) || \
2426 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_375) || \
2427 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_500) || \
2428 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_625) || \
2429 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_750) || \
2430 ((DUTYCYCLE) == HRTIM_CHOPPER_DUTYCYCLE_875))
2432 #define IS_HRTIM_CHOPPER_PULSEWIDTH(PULSEWIDTH)\
2433 (((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_16) || \
2434 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_32) || \
2435 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_48) || \
2436 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_64) || \
2437 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_80) || \
2438 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_96) || \
2439 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_112) || \
2440 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_128) || \
2441 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_144) || \
2442 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_160) || \
2443 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_176) || \
2444 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_192) || \
2445 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_208) || \
2446 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_224) || \
2447 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_240) || \
2448 ((PULSEWIDTH) == HRTIM_CHOPPER_PULSEWIDTH_256))
2450 #define IS_HRTIM_SYNCINPUTSOURCE(SYNCINPUTSOURCE)\
2451 (((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_NONE) || \
2452 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_INTERNALEVENT) || \
2453 ((SYNCINPUTSOURCE) == HRTIM_SYNCINPUTSOURCE_EXTERNALEVENT))
2455 #define IS_HRTIM_SYNCOUTPUTSOURCE(SYNCOUTPUTSOURCE)\
2456 (((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_START) || \
2457 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_MASTER_CMP1) || \
2458 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_START) || \
2459 ((SYNCOUTPUTSOURCE) == HRTIM_SYNCOUTPUTSOURCE_TIMA_CMP1))
2461 #define IS_HRTIM_SYNCOUTPUTPOLARITY(SYNCOUTPUTPOLARITY)\
2462 (((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NONE) || \
2463 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_POSITIVE) || \
2464 ((SYNCOUTPUTPOLARITY) == HRTIM_SYNCOUTPUTPOLARITY_NEGATIVE))
2466 #define IS_HRTIM_EVENTSRC(EVENTSRC)\
2467 (((EVENTSRC) == HRTIM_EVENTSRC_1) || \
2468 ((EVENTSRC) == HRTIM_EVENTSRC_2) || \
2469 ((EVENTSRC) == HRTIM_EVENTSRC_3) || \
2470 ((EVENTSRC) == HRTIM_EVENTSRC_4))
2472 #define IS_HRTIM_EVENTPOLARITY(EVENTSENSITIVITY, EVENTPOLARITY)\
2473 ((((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) && \
2474 (((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_HIGH) || \
2475 ((EVENTPOLARITY) == HRTIM_EVENTPOLARITY_LOW))) \
2476 || \
2477 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
2478 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE)|| \
2479 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES)))
2481 #define IS_HRTIM_EVENTSENSITIVITY(EVENTSENSITIVITY)\
2482 (((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_LEVEL) || \
2483 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_RISINGEDGE) || \
2484 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_FALLINGEDGE) || \
2485 ((EVENTSENSITIVITY) == HRTIM_EVENTSENSITIVITY_BOTHEDGES))
2487 #define IS_HRTIM_EVENTFASTMODE(EVENT, FASTMODE)\
2488 (((((EVENT) == HRTIM_EVENT_1) || \
2489 ((EVENT) == HRTIM_EVENT_2) || \
2490 ((EVENT) == HRTIM_EVENT_3) || \
2491 ((EVENT) == HRTIM_EVENT_4) || \
2492 ((EVENT) == HRTIM_EVENT_5)) && \
2493 (((FASTMODE) == HRTIM_EVENTFASTMODE_ENABLE) || \
2494 ((FASTMODE) == HRTIM_EVENTFASTMODE_DISABLE))) \
2495 || \
2496 (((EVENT) == HRTIM_EVENT_6) || \
2497 ((EVENT) == HRTIM_EVENT_7) || \
2498 ((EVENT) == HRTIM_EVENT_8) || \
2499 ((EVENT) == HRTIM_EVENT_9) || \
2500 ((EVENT) == HRTIM_EVENT_10)))
2503 #define IS_HRTIM_EVENTFILTER(EVENT, FILTER)\
2504 ((((EVENT) == HRTIM_EVENT_1) || \
2505 ((EVENT) == HRTIM_EVENT_2) || \
2506 ((EVENT) == HRTIM_EVENT_3) || \
2507 ((EVENT) == HRTIM_EVENT_4) || \
2508 ((EVENT) == HRTIM_EVENT_5)) \
2509 || \
2510 ((((EVENT) == HRTIM_EVENT_6) || \
2511 ((EVENT) == HRTIM_EVENT_7) || \
2512 ((EVENT) == HRTIM_EVENT_8) || \
2513 ((EVENT) == HRTIM_EVENT_9) || \
2514 ((EVENT) == HRTIM_EVENT_10)) && \
2515 (((FILTER) == HRTIM_EVENTFILTER_NONE) || \
2516 ((FILTER) == HRTIM_EVENTFILTER_1) || \
2517 ((FILTER) == HRTIM_EVENTFILTER_2) || \
2518 ((FILTER) == HRTIM_EVENTFILTER_3) || \
2519 ((FILTER) == HRTIM_EVENTFILTER_4) || \
2520 ((FILTER) == HRTIM_EVENTFILTER_5) || \
2521 ((FILTER) == HRTIM_EVENTFILTER_6) || \
2522 ((FILTER) == HRTIM_EVENTFILTER_7) || \
2523 ((FILTER) == HRTIM_EVENTFILTER_8) || \
2524 ((FILTER) == HRTIM_EVENTFILTER_9) || \
2525 ((FILTER) == HRTIM_EVENTFILTER_10) || \
2526 ((FILTER) == HRTIM_EVENTFILTER_11) || \
2527 ((FILTER) == HRTIM_EVENTFILTER_12) || \
2528 ((FILTER) == HRTIM_EVENTFILTER_13) || \
2529 ((FILTER) == HRTIM_EVENTFILTER_14) || \
2530 ((FILTER) == HRTIM_EVENTFILTER_15))))
2532 #define IS_HRTIM_EVENTPRESCALER(EVENTPRESCALER)\
2533 (((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV1) || \
2534 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV2) || \
2535 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV4) || \
2536 ((EVENTPRESCALER) == HRTIM_EVENTPRESCALER_DIV8))
2537 #define IS_HRTIM_FAULTSOURCE(FAULTSOURCE)\
2538 (((FAULTSOURCE) == HRTIM_FAULTSOURCE_DIGITALINPUT) || \
2539 ((FAULTSOURCE) == HRTIM_FAULTSOURCE_INTERNAL))
2541 #define IS_HRTIM_FAULTPOLARITY(HRTIM_FAULTPOLARITY)\
2542 (((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_LOW) || \
2543 ((HRTIM_FAULTPOLARITY) == HRTIM_FAULTPOLARITY_HIGH))
2545 #define IS_HRTIM_FAULTFILTER(FAULTFILTER)\
2546 (((FAULTFILTER) == HRTIM_FAULTFILTER_NONE) || \
2547 ((FAULTFILTER) == HRTIM_FAULTFILTER_1) || \
2548 ((FAULTFILTER) == HRTIM_FAULTFILTER_2) || \
2549 ((FAULTFILTER) == HRTIM_FAULTFILTER_3) || \
2550 ((FAULTFILTER) == HRTIM_FAULTFILTER_4) || \
2551 ((FAULTFILTER) == HRTIM_FAULTFILTER_5) || \
2552 ((FAULTFILTER) == HRTIM_FAULTFILTER_6) || \
2553 ((FAULTFILTER) == HRTIM_FAULTFILTER_7) || \
2554 ((FAULTFILTER) == HRTIM_FAULTFILTER_8) || \
2555 ((FAULTFILTER) == HRTIM_FAULTFILTER_9) || \
2556 ((FAULTFILTER) == HRTIM_FAULTFILTER_10) || \
2557 ((FAULTFILTER) == HRTIM_FAULTFILTER_11) || \
2558 ((FAULTFILTER) == HRTIM_FAULTFILTER_12) || \
2559 ((FAULTFILTER) == HRTIM_FAULTFILTER_13) || \
2560 ((FAULTFILTER) == HRTIM_FAULTFILTER_14) || \
2561 ((FAULTFILTER) == HRTIM_FAULTFILTER_15))
2563 #define IS_HRTIM_FAULTLOCK(FAULTLOCK)\
2564 (((FAULTLOCK) == HRTIM_FAULTLOCK_READWRITE) || \
2565 ((FAULTLOCK) == HRTIM_FAULTLOCK_READONLY))
2567 #define IS_HRTIM_FAULTPRESCALER(FAULTPRESCALER)\
2568 (((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV1) || \
2569 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV2) || \
2570 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV4) || \
2571 ((FAULTPRESCALER) == HRTIM_FAULTPRESCALER_DIV8))
2573 #define IS_HRTIM_BURSTMODE(BURSTMODE)\
2574 (((BURSTMODE) == HRTIM_BURSTMODE_SINGLESHOT) || \
2575 ((BURSTMODE) == HRTIM_BURSTMODE_CONTINOUS))
2577 #define IS_HRTIM_BURSTMODECLOCKSOURCE(BURSTMODECLOCKSOURCE)\
2578 (((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_MASTER) || \
2579 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_A) || \
2580 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_B) || \
2581 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_C) || \
2582 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_D) || \
2583 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIMER_E) || \
2584 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM16_OC) || \
2585 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM17_OC) || \
2586 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_TIM7_TRGO) || \
2587 ((BURSTMODECLOCKSOURCE) == HRTIM_BURSTMODECLOCKSOURCE_FHRTIM))
2589 #define IS_HRTIM_HRTIM_BURSTMODEPRESCALER(BURSTMODEPRESCALER)\
2590 (((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1) || \
2591 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2) || \
2592 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4) || \
2593 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8) || \
2594 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16) || \
2595 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32) || \
2596 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV64) || \
2597 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV128) || \
2598 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV256) || \
2599 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV512) || \
2600 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV1024) || \
2601 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV2048) || \
2602 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV4096) || \
2603 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV8192) || \
2604 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV16384) || \
2605 ((BURSTMODEPRESCALER) == HRTIM_BURSTMODEPRESCALER_DIV32768))
2607 #define IS_HRTIM_BURSTMODEPRELOAD(BURSTMODEPRELOAD)\
2608 (((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_DISABLED) || \
2609 ((BURSTMODEPRELOAD) == HRIM_BURSTMODEPRELOAD_ENABLED))
2611 #define IS_HRTIM_BURSTMODETRIGGER(BURSTMODETRIGGER)\
2612 (((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_NONE) || \
2613 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_RESET) || \
2614 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_REPETITION) || \
2615 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP1) || \
2616 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP2) || \
2617 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP3) || \
2618 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_MASTER_CMP4) || \
2619 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_RESET) || \
2620 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_REPETITION) || \
2621 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP1) || \
2622 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_CMP2) || \
2623 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_RESET) || \
2624 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_REPETITION) || \
2625 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP1) || \
2626 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERB_CMP2) || \
2627 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_RESET) || \
2628 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_REPETITION) || \
2629 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP1) || \
2630 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERC_CMP2) || \
2631 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_RESET) || \
2632 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_REPETITION) || \
2633 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP1) || \
2634 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_CMP2) || \
2635 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_RESET) || \
2636 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_REPETITION) || \
2637 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP1) || \
2638 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERE_CMP2) || \
2639 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERA_EVENT7) || \
2640 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_TIMERD_EVENT8) || \
2641 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_7) || \
2642 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_8) || \
2643 ((BURSTMODETRIGGER) == HRTIM_BURSTMODETRIGGER_EVENT_ONCHIP))
2645 #define IS_HRTIM_ADCTRIGGERUPDATE(ADCTRIGGERUPDATE)\
2646 (((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_MASTER) || \
2647 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_A) || \
2648 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_B) || \
2649 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_C) || \
2650 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_D) || \
2651 ((ADCTRIGGERUPDATE) == HRTIM_ADCTRIGGERUPDATE_TIMER_E))
2653 #define IS_HRTIM_CALIBRATIONRATE(CALIBRATIONRATE)\
2654 (((CALIBRATIONRATE) == HRTIM_SINGLE_CALIBRATION) || \
2655 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_7300) || \
2656 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_910) || \
2657 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_114) || \
2658 ((CALIBRATIONRATE) == HRTIM_CALIBRATIONRATE_14))
2660 #define IS_HRTIM_TIMER_BURSTDMA(TIMER, BURSTDMA) \
2661 ((((TIMER) == HRTIM_TIMERINDEX_MASTER) && (((BURSTDMA) & 0xFFFFFC000U) == 0x00000000U)) \
2662 || \
2663 (((TIMER) == HRTIM_TIMERINDEX_TIMER_A) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
2664 || \
2665 (((TIMER) == HRTIM_TIMERINDEX_TIMER_B) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
2666 || \
2667 (((TIMER) == HRTIM_TIMERINDEX_TIMER_C) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
2668 || \
2669 (((TIMER) == HRTIM_TIMERINDEX_TIMER_D) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)) \
2670 || \
2671 (((TIMER) == HRTIM_TIMERINDEX_TIMER_E) && (((BURSTDMA) & 0xFFE00000U) == 0x00000000U)))
2673 #define IS_HRTIM_BURSTMODECTL(BURSTMODECTL)\
2674 (((BURSTMODECTL) == HRTIM_BURSTMODECTL_DISABLED) || \
2675 ((BURSTMODECTL) == HRTIM_BURSTMODECTL_ENABLED))
2677 #define IS_HRTIM_TIMERUPDATE(TIMERUPDATE) (((TIMERUPDATE) & 0xFFFFFFC0U) == 0x00000000U)
2679 #define IS_HRTIM_TIMERRESET(TIMERRESET) (((TIMERRESET) & 0xFFFFC0FFU) == 0x00000000U)
2681 #define IS_HRTIM_IT(IT) (((IT) & 0xFFFCFFC0U) == 0x00000000U)
2684 #define IS_HRTIM_MASTER_IT(MASTER_IT) (((MASTER_IT) & 0xFFFFFF80U) == 0x00000000U)
2687 #define IS_HRTIM_TIM_IT(IS_HRTIM_TIM_IT) (((IS_HRTIM_TIM_IT) & 0xFFFF8020U) == 0x00000000U)
2690 #define IS_HRTIM_MASTER_DMA(MASTER_DMA) (((MASTER_DMA) & 0xFF80FFFFU) == 0x00000000U)
2692 #define IS_HRTIM_TIM_DMA(TIM_DMA) (((TIM_DMA) & 0x8020FFFFU) == 0x00000000U)
2693 /**
2694 * @}
2695 */
2697 /* Exported macros -----------------------------------------------------------*/
2698 /** @defgroup HRTIM_Exported_Macros HRTIM Exported Macros
2699 * @{
2700 */
2702 /** @brief Reset HRTIM handle state
2703 * @param __HANDLE__ HRTIM handle.
2704 * @retval None
2705 */
2706 #define __HAL_HRTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HRTIM_STATE_RESET)
2708 /** @brief Enables or disables the timer counter(s)
2709 * @param __HANDLE__ specifies the HRTIM Handle.
2710 * @param __TIMERS__ timers to enable/disable
2711 * This parameter can be any combinations of the following values:
2712 * @arg HRTIM_TIMERID_MASTER: Master timer identifier
2713 * @arg HRTIM_TIMERID_TIMER_A: Timer A identifier
2714 * @arg HRTIM_TIMERID_TIMER_B: Timer B identifier
2715 * @arg HRTIM_TIMERID_TIMER_C: Timer C identifier
2716 * @arg HRTIM_TIMERID_TIMER_D: Timer D identifier
2717 * @arg HRTIM_TIMERID_TIMER_E: Timer E identifier
2718 * @retval None
2719 */
2720 #define __HAL_HRTIM_ENABLE(__HANDLE__, __TIMERS__) ((__HANDLE__)->Instance->sMasterRegs.MCR |= (__TIMERS__))
2722 /* The counter of a timing unit is disabled only if all the timer outputs */
2723 /* are disabled and no capture is configured */
2724 #define HRTIM_TAOEN_MASK (HRTIM_OENR_TA2OEN | HRTIM_OENR_TA1OEN)
2725 #define HRTIM_TBOEN_MASK (HRTIM_OENR_TB2OEN | HRTIM_OENR_TB1OEN)
2726 #define HRTIM_TCOEN_MASK (HRTIM_OENR_TC2OEN | HRTIM_OENR_TC1OEN)
2727 #define HRTIM_TDOEN_MASK (HRTIM_OENR_TD2OEN | HRTIM_OENR_TD1OEN)
2728 #define HRTIM_TEOEN_MASK (HRTIM_OENR_TE2OEN | HRTIM_OENR_TE1OEN)
2729 #define __HAL_HRTIM_DISABLE(__HANDLE__, __TIMERS__)\
2730 do {\
2731 if (((__TIMERS__) & HRTIM_TIMERID_MASTER) == HRTIM_TIMERID_MASTER)\
2732 {\
2733 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_MASTER);\
2734 }\
2735 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_A) == HRTIM_TIMERID_TIMER_A)\
2736 {\
2737 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TAOEN_MASK) == RESET)\
2738 {\
2739 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_A);\
2740 }\
2741 }\
2742 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_B) == HRTIM_TIMERID_TIMER_B)\
2743 {\
2744 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TBOEN_MASK) == RESET)\
2745 {\
2746 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_B);\
2747 }\
2748 }\
2749 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_C) == HRTIM_TIMERID_TIMER_C)\
2750 {\
2751 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TCOEN_MASK) == RESET)\
2752 {\
2753 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_C);\
2754 }\
2755 }\
2756 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_D) == HRTIM_TIMERID_TIMER_D)\
2757 {\
2758 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TDOEN_MASK) == RESET)\
2759 {\
2760 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_D);\
2761 }\
2762 }\
2763 if (((__TIMERS__) & HRTIM_TIMERID_TIMER_E) == HRTIM_TIMERID_TIMER_E)\
2764 {\
2765 if (((__HANDLE__)->Instance->sCommonRegs.OENR & HRTIM_TEOEN_MASK) == RESET)\
2766 {\
2767 ((__HANDLE__)->Instance->sMasterRegs.MCR &= ~HRTIM_TIMERID_TIMER_E);\
2768 }\
2769 }\
2770 } while(0U)
2772 /** @brief Enables or disables the specified HRTIM common interrupts.
2773 * @param __HANDLE__ specifies the HRTIM Handle.
2774 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
2775 * This parameter can be one of the following values:
2776 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
2777 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
2778 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
2779 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
2780 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
2781 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
2782 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
2783 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
2784 * @retval None
2785 */
2786 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
2787 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
2789 /** @brief Enables or disables the specified HRTIM Master timer interrupts.
2790 * @param __HANDLE__ specifies the HRTIM Handle.
2791 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
2792 * This parameter can be one of the following values:
2793 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
2794 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
2795 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
2796 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
2797 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
2798 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
2799 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
2800 * @retval None
2801 */
2802 #define __HAL_HRTIM_MASTER_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__INTERRUPT__))
2803 #define __HAL_HRTIM_MASTER_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__INTERRUPT__))
2805 /** @brief Enables or disables the specified HRTIM Timerx interrupts.
2806 * @param __HANDLE__ specifies the HRTIM Handle.
2807 * @param __TIMER__ specified the timing unit (Timer A to E)
2808 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
2809 * This parameter can be one of the following values:
2810 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
2811 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
2812 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
2813 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
2814 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
2815 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
2816 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
2817 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
2818 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
2819 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
2820 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
2821 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
2822 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
2823 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
2824 * @retval None
2825 */
2826 #define __HAL_HRTIM_TIMER_ENABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__INTERRUPT__))
2827 #define __HAL_HRTIM_TIMER_DISABLE_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__INTERRUPT__))
2829 /** @brief Checks if the specified HRTIM common interrupt source is enabled or disabled.
2830 * @param __HANDLE__ specifies the HRTIM Handle.
2831 * @param __INTERRUPT__ specifies the interrupt source to check.
2832 * This parameter can be one of the following values:
2833 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
2834 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
2835 * @arg HRTIM_IT_FLT3: Fault 3 enable
2836 * @arg HRTIM_IT_FLT4: Fault 4 enable
2837 * @arg HRTIM_IT_FLT5: Fault 5 enable
2838 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
2839 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
2840 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
2841 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
2842 */
2843 #define __HAL_HRTIM_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sCommonRegs.IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
2845 /** @brief Checks if the specified HRTIM Master interrupt source is enabled or disabled.
2846 * @param __HANDLE__ specifies the HRTIM Handle.
2847 * @param __INTERRUPT__ specifies the interrupt source to check.
2848 * This parameter can be one of the following values:
2849 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
2850 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
2851 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
2852 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
2853 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
2854 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
2855 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
2856 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
2857 */
2858 #define __HAL_HRTIM_MASTER_GET_ITSTATUS(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->sMasterRegs.MDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
2860 /** @brief Checks if the specified HRTIM Timerx interrupt source is enabled or disabled.
2861 * @param __HANDLE__ specifies the HRTIM Handle.
2862 * @param __TIMER__ specified the timing unit (Timer A to E)
2863 * @param __INTERRUPT__ specifies the interrupt source to check.
2864 * This parameter can be one of the following values:
2865 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt enable
2866 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt enable
2867 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt enable
2868 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt enable
2869 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt enable
2870 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt enable
2871 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt enable
2872 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt enable
2873 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt enable
2874 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt enable
2875 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt enable
2876 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt enable
2877 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt enable
2878 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt enable
2879 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt enable
2880 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt enable
2881 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt enable
2882 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt enable
2883 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt enable
2884 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt enable
2885 * @arg HRTIM_TIM_IT_DLYPRT: Timer delay protection interrupt enable
2886 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
2887 */
2888 #define __HAL_HRTIM_TIMER_GET_ITSTATUS(__HANDLE__, __TIMER__, __INTERRUPT__) ((((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
2890 /** @brief Clears the specified HRTIM common pending flag.
2891 * @param __HANDLE__ specifies the HRTIM Handle.
2892 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
2893 * This parameter can be one of the following values:
2894 * @arg HRTIM_IT_FLT1: Fault 1 interrupt clear flag
2895 * @arg HRTIM_IT_FLT2: Fault 2 interrupt clear flag
2896 * @arg HRTIM_IT_FLT3: Fault 3 clear flag
2897 * @arg HRTIM_IT_FLT4: Fault 4 clear flag
2898 * @arg HRTIM_IT_FLT5: Fault 5 clear flag
2899 * @arg HRTIM_IT_SYSFLT: System Fault interrupt clear flag
2900 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt clear flag
2901 * @arg HRTIM_IT_BMPER: Burst mode period interrupt clear flag
2902 * @retval None
2903 */
2904 #define __HAL_HRTIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__INTERRUPT__))
2906 /** @brief Clears the specified HRTIM Master pending flag.
2907 * @param __HANDLE__ specifies the HRTIM Handle.
2908 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
2909 * This parameter can be one of the following values:
2910 * @arg HRTIM_MASTER_IT_MCMP1: Master compare 1 interrupt clear flag
2911 * @arg HRTIM_MASTER_IT_MCMP2: Master compare 2 interrupt clear flag
2912 * @arg HRTIM_MASTER_IT_MCMP3: Master compare 3 interrupt clear flag
2913 * @arg HRTIM_MASTER_IT_MCMP4: Master compare 4 interrupt clear flag
2914 * @arg HRTIM_MASTER_IT_MREP: Master Repetition interrupt clear flag
2915 * @arg HRTIM_MASTER_IT_SYNC: Synchronization input interrupt clear flag
2916 * @arg HRTIM_MASTER_IT_MUPD: Master update interrupt clear flag
2917 * @retval None
2918 */
2919 #define __HAL_HRTIM_MASTER_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__INTERRUPT__))
2921 /** @brief Clears the specified HRTIM Timerx pending flag.
2922 * @param __HANDLE__ specifies the HRTIM Handle.
2923 * @param __TIMER__ specified the timing unit (Timer A to E)
2924 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
2925 * This parameter can be one of the following values:
2926 * @arg HRTIM_TIM_IT_CMP1: Timer compare 1 interrupt clear flag
2927 * @arg HRTIM_TIM_IT_CMP2: Timer compare 2 interrupt clear flag
2928 * @arg HRTIM_TIM_IT_CMP3: Timer compare 3 interrupt clear flag
2929 * @arg HRTIM_TIM_IT_CMP4: Timer compare 4 interrupt clear flag
2930 * @arg HRTIM_TIM_IT_REP: Timer repetition interrupt clear flag
2931 * @arg HRTIM_TIM_IT_UPD: Timer update interrupt clear flag
2932 * @arg HRTIM_TIM_IT_CPT1: Timer capture 1 interrupt clear flag
2933 * @arg HRTIM_TIM_IT_CPT2: Timer capture 2 interrupt clear flag
2934 * @arg HRTIM_TIM_IT_SET1: Timer output 1 set interrupt clear flag
2935 * @arg HRTIM_TIM_IT_RST1: Timer output 1 reset interrupt clear flag
2936 * @arg HRTIM_TIM_IT_SET2: Timer output 2 set interrupt clear flag
2937 * @arg HRTIM_TIM_IT_RST2: Timer output 2 reset interrupt clear flag
2938 * @arg HRTIM_TIM_IT_RST: Timer reset interrupt clear flag
2939 * @arg HRTIM_TIM_IT_DLYPRT: Timer output 1 delay protection interrupt clear flag
2940 * @retval None
2941 */
2942 #define __HAL_HRTIM_TIMER_CLEAR_IT(__HANDLE__, __TIMER__, __INTERRUPT__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__INTERRUPT__))
2944 /* DMA HANDLING */
2945 /** @brief Enables or disables the specified HRTIM common interrupts.
2946 * @param __HANDLE__ specifies the HRTIM Handle.
2947 * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
2948 * This parameter can be one of the following values:
2949 * @arg HRTIM_IT_FLT1: Fault 1 interrupt enable
2950 * @arg HRTIM_IT_FLT2: Fault 2 interrupt enable
2951 * @arg HRTIM_IT_FLT3: Fault 3 interrupt enable
2952 * @arg HRTIM_IT_FLT4: Fault 4 interrupt enable
2953 * @arg HRTIM_IT_FLT5: Fault 5 interrupt enable
2954 * @arg HRTIM_IT_SYSFLT: System Fault interrupt enable
2955 * @arg HRTIM_IT_DLLRDY: DLL ready interrupt enable
2956 * @arg HRTIM_IT_BMPER: Burst mode period interrupt enable
2957 * @retval None
2958 */
2959 #define __HAL_HRTIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER |= (__INTERRUPT__))
2960 #define __HAL_HRTIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->sCommonRegs.IER &= ~(__INTERRUPT__))
2962 /** @brief Enables or disables the specified HRTIM Master timer DMA requets.
2963 * @param __HANDLE__ specifies the HRTIM Handle.
2964 * @param __DMA__ specifies the DMA request to enable or disable.
2965 * This parameter can be one of the following values:
2966 * @arg HRTIM_MASTER_DMA_MCMP1: Master compare 1 DMA resquest enable
2967 * @arg HRTIM_MASTER_DMA_MCMP2: Master compare 2 DMA resquest enable
2968 * @arg HRTIM_MASTER_DMA_MCMP3: Master compare 3 DMA resquest enable
2969 * @arg HRTIM_MASTER_DMA_MCMP4: Master compare 4 DMA resquest enable
2970 * @arg HRTIM_MASTER_DMA_MREP: Master Repetition DMA resquest enable
2971 * @arg HRTIM_MASTER_DMA_SYNC: Synchronization input DMA resquest enable
2972 * @arg HRTIM_MASTER_DMA_MUPD: Master update DMA resquest enable
2973 * @retval None
2974 */
2975 #define __HAL_HRTIM_MASTER_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER |= (__DMA__))
2976 #define __HAL_HRTIM_MASTER_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->sMasterRegs.MDIER &= ~(__DMA__))
2978 /** @brief Enables or disables the specified HRTIM Timerx DMA requests.
2979 * @param __HANDLE__ specifies the HRTIM Handle.
2980 * @param __TIMER__ specified the timing unit (Timer A to E)
2981 * @param __DMA__ specifies the DMA request to enable or disable.
2982 * This parameter can be one of the following values:
2983 * @arg HRTIM_TIM_DMA_CMP1: Timer compare 1 DMA resquest enable
2984 * @arg HRTIM_TIM_DMA_CMP2: Timer compare 2 DMA resquest enable
2985 * @arg HRTIM_TIM_DMA_CMP3: Timer compare 3 DMA resquest enable
2986 * @arg HRTIM_TIM_DMA_CMP4: Timer compare 4 DMA resquest enable
2987 * @arg HRTIM_TIM_DMA_REP: Timer repetition DMA resquest enable
2988 * @arg HRTIM_TIM_DMA_UPD: Timer update DMA resquest enable
2989 * @arg HRTIM_TIM_DMA_CPT1: Timer capture 1 DMA resquest enable
2990 * @arg HRTIM_TIM_DMA_CPT2: Timer capture 2 DMA resquest enable
2991 * @arg HRTIM_TIM_DMA_SET1: Timer output 1 set DMA resquest enable
2992 * @arg HRTIM_TIM_DMA_RST1: Timer output 1 reset DMA resquest enable
2993 * @arg HRTIM_TIM_DMA_SET2: Timer output 2 set DMA resquest enable
2994 * @arg HRTIM_TIM_DMA_RST2: Timer output 2 reset DMA resquest enable
2995 * @arg HRTIM_TIM_DMA_RST: Timer reset DMA resquest enable
2996 * @arg HRTIM_TIM_DMA_DLYPRT: Timer delay protection DMA resquest enable
2997 * @retval None
2998 */
2999 #define __HAL_HRTIM_TIMER_ENABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER |= (__DMA__))
3000 #define __HAL_HRTIM_TIMER_DISABLE_DMA(__HANDLE__, __TIMER__, __DMA__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxDIER &= ~(__DMA__))
3002 #define __HAL_HRTIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sCommonRegs.ISR & (__FLAG__)) == (__FLAG__))
3003 #define __HAL_HRTIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sCommonRegs.ICR = (__FLAG__))
3005 #define __HAL_HRTIM_MASTER_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->sMasterRegs.MISR & (__FLAG__)) == (__FLAG__))
3006 #define __HAL_HRTIM_MASTER_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->sMasterRegs.MICR = (__FLAG__))
3008 #define __HAL_HRTIM_TIMER_GET_FLAG(__HANDLE__, __TIMER__, __FLAG__) (((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxISR & (__FLAG__)) == (__FLAG__))
3009 #define __HAL_HRTIM_TIMER_CLEAR_FLAG(__HANDLE__, __TIMER__, __FLAG__) ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxICR = (__FLAG__))
3011 /** @brief Sets the HRTIM timer Counter Register value on runtime
3012 * @param __HANDLE__ HRTIM Handle.
3013 * @param __TIMER__ HRTIM timer
3014 * This parameter can be one of the following values:
3015 * @arg 0x5 for master timer
3016 * @arg 0x0 to 0x4 for timers A to E
3017 * @param __COUNTER__ specifies the Counter Register new value.
3018 * @retval None
3019 */
3020 #define __HAL_HRTIM_SETCOUNTER(__HANDLE__, __TIMER__, __COUNTER__) \
3021 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR = (__COUNTER__)) :\
3022 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR = (__COUNTER__)))
3024 /** @brief Gets the HRTIM timer Counter Register value on runtime
3025 * @param __HANDLE__ HRTIM Handle.
3026 * @param __TIMER__ HRTIM timer
3027 * This parameter can be one of the following values:
3028 * @arg 0x5 for master timer
3029 * @arg 0x0 to 0x4 for timers A to E
3030 * @retval HRTIM timer Counter Register value
3031 */
3032 #define __HAL_HRTIM_GETCOUNTER(__HANDLE__, __TIMER__) \
3033 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCNTR) :\
3034 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CNTxR))
3036 /** @brief Sets the HRTIM timer Period value on runtime
3037 * @param __HANDLE__ HRTIM Handle.
3038 * @param __TIMER__ HRTIM timer
3039 * This parameter can be one of the following values:
3040 * @arg 0x5 for master timer
3041 * @arg 0x0 to 0x4 for timers A to E
3042 * @param __PERIOD__ specifies the Period Register new value.
3043 * @retval None
3044 */
3045 #define __HAL_HRTIM_SETPERIOD(__HANDLE__, __TIMER__, __PERIOD__) \
3046 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER = (__PERIOD__)) :\
3047 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR = (__PERIOD__)))
3049 /** @brief Gets the HRTIM timer Period Register value on runtime
3050 * @param __HANDLE__ HRTIM Handle.
3051 * @param __TIMER__ HRTIM timer
3052 * This parameter can be one of the following values:
3053 * @arg 0x5 for master timer
3054 * @arg 0x0 to 0x4 for timers A to E
3055 * @retval timer Period Register
3056 */
3057 #define __HAL_HRTIM_GETPERIOD(__HANDLE__, __TIMER__) \
3058 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MPER) :\
3059 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].PERxR))
3061 /** @brief Sets the HRTIM timer clock prescaler value on runtime
3062 * @param __HANDLE__ HRTIM Handle.
3063 * @param __TIMER__ HRTIM timer
3064 * This parameter can be one of the following values:
3065 * @arg 0x5 for master timer
3066 * @arg 0x0 to 0x4 for timers A to E
3067 * @param __PRESCALER__ specifies the clock prescaler new value.
3068 * This parameter can be one of the following values:
3069 * @arg HRTIM_PRESCALERRATIO_MUL32: fHRCK: 4.608 GHz - Resolution: 217 ps - Min PWM frequency: 70.3 kHz (fHRTIM=144MHz)
3070 * @arg HRTIM_PRESCALERRATIO_MUL16: fHRCK: 2.304 GHz - Resolution: 434 ps - Min PWM frequency: 35.1 KHz (fHRTIM=144MHz)
3071 * @arg HRTIM_PRESCALERRATIO_MUL8: fHRCK: 1.152 GHz - Resolution: 868 ps - Min PWM frequency: 17.6 kHz (fHRTIM=144MHz)
3072 * @arg HRTIM_PRESCALERRATIO_MUL4: fHRCK: 576 MHz - Resolution: 1.73 ns - Min PWM frequency: 8.8 kHz (fHRTIM=144MHz)
3073 * @arg HRTIM_PRESCALERRATIO_MUL2: fHRCK: 288 MHz - Resolution: 3.47 ns - Min PWM frequency: 4.4 kHz (fHRTIM=144MHz)
3074 * @arg HRTIM_PRESCALERRATIO_DIV1: fHRCK: 144 MHz - Resolution: 6.95 ns - Min PWM frequency: 2.2 kHz (fHRTIM=144MHz)
3075 * @arg HRTIM_PRESCALERRATIO_DIV2: fHRCK: 72 MHz - Resolution: 13.88 ns- Min PWM frequency: 1.1 kHz (fHRTIM=144MHz)
3076 * @arg HRTIM_PRESCALERRATIO_DIV4: fHRCK: 36 MHz - Resolution: 27.7 ns- Min PWM frequency: 550Hz (fHRTIM=144MHz)
3077 * @retval None
3078 */
3079 #define __HAL_HRTIM_SETCLOCKPRESCALER(__HANDLE__, __TIMER__, __PRESCALER__) \
3080 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? (MODIFY_REG((__HANDLE__)->Instance->sMasterRegs.MCR, HRTIM_MCR_CK_PSC, (__PRESCALER__))) :\
3081 (MODIFY_REG((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR, HRTIM_TIMCR_CK_PSC, (__PRESCALER__))))
3083 /** @brief Gets the HRTIM timer clock prescaler value on runtime
3084 * @param __HANDLE__ HRTIM Handle.
3085 * @param __TIMER__ HRTIM timer
3086 * This parameter can be one of the following values:
3087 * @arg 0x5 for master timer
3088 * @arg 0x0 to 0x4 for timers A to E
3089 * @retval timer clock prescaler value
3090 */
3091 #define __HAL_HRTIM_GETCLOCKPRESCALER(__HANDLE__, __TIMER__) \
3092 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? ((__HANDLE__)->Instance->sMasterRegs.MCR & HRTIM_MCR_CK_PSC) :\
3093 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].TIMxCR & HRTIM_TIMCR_CK_PSC))
3095 /** @brief Sets the HRTIM timer Compare Register value on runtime
3096 * @param __HANDLE__ HRTIM Handle.
3097 * @param __TIMER__ HRTIM timer
3098 * This parameter can be one of the following values:
3099 * @arg 0x0 to 0x4 for timers A to E
3100 * @param __COMPAREUNIT__ timer compare unit
3101 * This parameter can be one of the following values:
3102 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
3103 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
3104 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
3105 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
3106 * @param __COMPARE__ specifies the Compare new value.
3107 * @retval None
3108 */
3109 #define __HAL_HRTIM_SETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__, __COMPARE__) \
3110 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
3111 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R = (__COMPARE__)) :\
3112 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R = (__COMPARE__)) :\
3113 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R = (__COMPARE__)) :\
3114 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R = (__COMPARE__))) \
3115 : \
3116 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR = (__COMPARE__)) :\
3117 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR = (__COMPARE__)) :\
3118 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR = (__COMPARE__)) :\
3119 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR = (__COMPARE__))))
3121 /** @brief Gets the HRTIM timer Compare Register value on runtime
3122 * @param __HANDLE__ HRTIM Handle.
3123 * @param __TIMER__ HRTIM timer
3124 * This parameter can be one of the following values:
3125 * @arg 0x0 to 0x4 for timers A to E
3126 * @param __COMPAREUNIT__ timer compare unit
3127 * This parameter can be one of the following values:
3128 * @arg HRTIM_COMPAREUNIT_1: Compare unit 1
3129 * @arg HRTIM_COMPAREUNIT_2: Compare unit 2
3130 * @arg HRTIM_COMPAREUNIT_3: Compare unit 3
3131 * @arg HRTIM_COMPAREUNIT_4: Compare unit 4
3132 * @retval Compare value
3133 */
3134 #define __HAL_HRTIM_GETCOMPARE(__HANDLE__, __TIMER__, __COMPAREUNIT__) \
3135 (((__TIMER__) == HRTIM_TIMERINDEX_MASTER) ? \
3136 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP1R) :\
3137 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP2R) :\
3138 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sMasterRegs.MCMP3R) :\
3139 ((__HANDLE__)->Instance->sMasterRegs.MCMP4R)) \
3140 : \
3141 (((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_1) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP1xR) :\
3142 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_2) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP2xR) :\
3143 ((__COMPAREUNIT__) == HRTIM_COMPAREUNIT_3) ? ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP3xR) :\
3144 ((__HANDLE__)->Instance->sTimerxRegs[(__TIMER__)].CMP4xR)))
3146 /**
3147 * @}
3148 */
3150 /* Exported functions --------------------------------------------------------*/
3151 /** @addtogroup HRTIM_Exported_Functions
3152 * @{
3153 */
3155 /** @addtogroup HRTIM_Exported_Functions_Group1
3156 * @{
3157 */
3159 /* Initialization and Configuration functions ********************************/
3181 /**
3182 * @}
3183 */
3185 /** @addtogroup HRTIM_Exported_Functions_Group2
3186 * @{
3187 */
3189 /* Simple time base related functions *****************************************/
3211 /**
3212 * @}
3213 */
3215 /** @addtogroup HRTIM_Exported_Functions_Group3
3216 * @{
3217 */
3218 /* Simple output compare related functions ************************************/
3251 /**
3252 * @}
3253 */
3255 /** @addtogroup HRTIM_Exported_Functions_Group4
3256 * @{
3257 */
3258 /* Simple PWM output related functions ****************************************/
3291 /**
3292 * @}
3293 */
3295 /** @addtogroup HRTIM_Exported_Functions_Group5
3296 * @{
3297 */
3298 /* Simple capture related functions *******************************************/
3331 /**
3332 * @}
3333 */
3335 /** @addtogroup HRTIM_Exported_Functions_Group6
3336 * @{
3337 */
3338 /* Simple one pulse related functions *****************************************/
3360 /**
3361 * @}
3362 */
3364 /** @addtogroup HRTIM_Exported_Functions_Group7
3365 * @{
3366 */
3392 /**
3393 * @}
3394 */
3396 /** @addtogroup HRTIM_Exported_Functions_Group8
3397 * @{
3398 */
3399 /* Waveform related functions *************************************************/
3494 /**
3495 * @}
3496 */
3498 /** @addtogroup HRTIM_Exported_Functions_Group9
3499 * @{
3500 */
3501 /* HRTIM peripheral state functions */
3528 /**
3529 * @}
3530 */
3532 /** @addtogroup HRTIM_Exported_Functions_Group10
3533 * @{
3534 */
3535 /* IRQ handler */
3539 /* HRTIM events related callback functions */
3550 /* Timer events related callback functions */
3583 /**
3584 * @}
3585 */
3587 /**
3588 * @}
3589 */
3591 /**
3592 * @}
3593 */
3595 /**
3596 * @}
3597 */
3601 #ifdef __cplusplus
3602 }
3603 #endif
3607 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/