F1 and F3 HAL / LL libraries
[betaflight.git] / lib / main / STM32F3 / Drivers / CMSIS / Device / ST / STM32F3xx / Source / Templates / arm / startup_stm32f302xc.s
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1 ;******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
2 ;* File Name : startup_stm32f302xc.s
3 ;* Author : MCD Application Team
4 ;* Description : STM32F302xB/xC devices vector table for MDK-ARM toolchain.
5 ;* This module performs:
6 ;* - Set the initial SP
7 ;* - Set the initial PC == Reset_Handler
8 ;* - Set the vector table entries with the exceptions ISR address
9 ;* - Branches to __main in the C library (which eventually
10 ;* calls main()).
11 ;* After Reset the CortexM4 processor is in Thread mode,
12 ;* priority is Privileged, and the Stack is set to Main.
14 ;*******************************************************************************
16 ;* Redistribution and use in source and binary forms, with or without modification,
17 ;* are permitted provided that the following conditions are met:
18 ;* 1. Redistributions of source code must retain the above copyright notice,
19 ;* this list of conditions and the following disclaimer.
20 ;* 2. Redistributions in binary form must reproduce the above copyright notice,
21 ;* this list of conditions and the following disclaimer in the documentation
22 ;* and/or other materials provided with the distribution.
23 ;* 3. Neither the name of STMicroelectronics nor the names of its contributors
24 ;* may be used to endorse or promote products derived from this software
25 ;* without specific prior written permission.
27 ;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
28 ;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
29 ;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
30 ;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
31 ;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
32 ;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
33 ;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
34 ;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
35 ;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
36 ;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 ;*******************************************************************************
40 ; Amount of memory (in bytes) allocated for Stack
41 ; Tailor this value to your application needs
42 ; <h> Stack Configuration
43 ; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
44 ; </h>
46 Stack_Size EQU 0x00000400
48 AREA STACK, NOINIT, READWRITE, ALIGN=3
49 Stack_Mem SPACE Stack_Size
50 __initial_sp
53 ; <h> Heap Configuration
54 ; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
55 ; </h>
57 Heap_Size EQU 0x00000200
59 AREA HEAP, NOINIT, READWRITE, ALIGN=3
60 __heap_base
61 Heap_Mem SPACE Heap_Size
62 __heap_limit
64 PRESERVE8
65 THUMB
68 ; Vector Table Mapped to Address 0 at Reset
69 AREA RESET, DATA, READONLY
70 EXPORT __Vectors
71 EXPORT __Vectors_End
72 EXPORT __Vectors_Size
74 __Vectors DCD __initial_sp ; Top of Stack
75 DCD Reset_Handler ; Reset Handler
76 DCD NMI_Handler ; NMI Handler
77 DCD HardFault_Handler ; Hard Fault Handler
78 DCD MemManage_Handler ; MPU Fault Handler
79 DCD BusFault_Handler ; Bus Fault Handler
80 DCD UsageFault_Handler ; Usage Fault Handler
81 DCD 0 ; Reserved
82 DCD 0 ; Reserved
83 DCD 0 ; Reserved
84 DCD 0 ; Reserved
85 DCD SVC_Handler ; SVCall Handler
86 DCD DebugMon_Handler ; Debug Monitor Handler
87 DCD 0 ; Reserved
88 DCD PendSV_Handler ; PendSV Handler
89 DCD SysTick_Handler ; SysTick Handler
91 ; External Interrupts
92 DCD WWDG_IRQHandler ; Window WatchDog
93 DCD PVD_IRQHandler ; PVD through EXTI Line detection
94 DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
95 DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
96 DCD FLASH_IRQHandler ; FLASH
97 DCD RCC_IRQHandler ; RCC
98 DCD EXTI0_IRQHandler ; EXTI Line0
99 DCD EXTI1_IRQHandler ; EXTI Line1
100 DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller
101 DCD EXTI3_IRQHandler ; EXTI Line3
102 DCD EXTI4_IRQHandler ; EXTI Line4
103 DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1
104 DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2
105 DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3
106 DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4
107 DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5
108 DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6
109 DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7
110 DCD ADC1_2_IRQHandler ; ADC1 and ADC2
111 DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX
112 DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0
113 DCD CAN_RX1_IRQHandler ; CAN RX1
114 DCD CAN_SCE_IRQHandler ; CAN SCE
115 DCD EXTI9_5_IRQHandler ; External Line[9:5]s
116 DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15
117 DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16
118 DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17
119 DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
120 DCD TIM2_IRQHandler ; TIM2
121 DCD TIM3_IRQHandler ; TIM3
122 DCD TIM4_IRQHandler ; TIM4
123 DCD I2C1_EV_IRQHandler ; I2C1 Event
124 DCD I2C1_ER_IRQHandler ; I2C1 Error
125 DCD I2C2_EV_IRQHandler ; I2C2 Event
126 DCD I2C2_ER_IRQHandler ; I2C2 Error
127 DCD SPI1_IRQHandler ; SPI1
128 DCD SPI2_IRQHandler ; SPI2
129 DCD USART1_IRQHandler ; USART1
130 DCD USART2_IRQHandler ; USART2
131 DCD USART3_IRQHandler ; USART3
132 DCD EXTI15_10_IRQHandler ; External Line[15:10]s
133 DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
134 DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line
135 DCD 0 ; Reserved
136 DCD 0 ; Reserved
137 DCD 0 ; Reserved
138 DCD 0 ; Reserved
139 DCD 0 ; Reserved
140 DCD 0 ; Reserved
141 DCD 0 ; Reserved
142 DCD 0 ; Reserved
143 DCD SPI3_IRQHandler ; SPI3
144 DCD UART4_IRQHandler ; UART4
145 DCD UART5_IRQHandler ; UART5
146 DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors
147 DCD 0 ; Reserved
148 DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1
149 DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2
150 DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3
151 DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4
152 DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5
153 DCD 0 ; Reserved
154 DCD 0 ; Reserved
155 DCD 0 ; Reserved
156 DCD COMP1_2_IRQHandler ; COMP1 and COMP2
157 DCD COMP4_6_IRQHandler ; COMP4 and COMP6
158 DCD 0 ; Reserved
159 DCD 0 ; Reserved
160 DCD 0 ; Reserved
161 DCD 0 ; Reserved
162 DCD 0 ; Reserved
163 DCD 0 ; Reserved
164 DCD 0 ; Reserved
165 DCD 0 ; Reserved
166 DCD USB_HP_IRQHandler ; USB High Priority remap
167 DCD USB_LP_IRQHandler ; USB Low Priority remap
168 DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI
169 DCD 0 ; Reserved
170 DCD 0 ; Reserved
171 DCD 0 ; Reserved
172 DCD 0 ; Reserved
173 DCD FPU_IRQHandler ; FPU
175 __Vectors_End
177 __Vectors_Size EQU __Vectors_End - __Vectors
179 AREA |.text|, CODE, READONLY
181 ; Reset handler
182 Reset_Handler PROC
183 EXPORT Reset_Handler [WEAK]
184 IMPORT SystemInit
185 IMPORT __main
187 LDR R0, =SystemInit
188 BLX R0
189 LDR R0, =__main
190 BX R0
191 ENDP
193 ; Dummy Exception Handlers (infinite loops which can be modified)
195 NMI_Handler PROC
196 EXPORT NMI_Handler [WEAK]
198 ENDP
199 HardFault_Handler\
200 PROC
201 EXPORT HardFault_Handler [WEAK]
203 ENDP
204 MemManage_Handler\
205 PROC
206 EXPORT MemManage_Handler [WEAK]
208 ENDP
209 BusFault_Handler\
210 PROC
211 EXPORT BusFault_Handler [WEAK]
213 ENDP
214 UsageFault_Handler\
215 PROC
216 EXPORT UsageFault_Handler [WEAK]
218 ENDP
219 SVC_Handler PROC
220 EXPORT SVC_Handler [WEAK]
222 ENDP
223 DebugMon_Handler\
224 PROC
225 EXPORT DebugMon_Handler [WEAK]
227 ENDP
228 PendSV_Handler PROC
229 EXPORT PendSV_Handler [WEAK]
231 ENDP
232 SysTick_Handler PROC
233 EXPORT SysTick_Handler [WEAK]
235 ENDP
237 Default_Handler PROC
239 EXPORT WWDG_IRQHandler [WEAK]
240 EXPORT PVD_IRQHandler [WEAK]
241 EXPORT TAMP_STAMP_IRQHandler [WEAK]
242 EXPORT RTC_WKUP_IRQHandler [WEAK]
243 EXPORT FLASH_IRQHandler [WEAK]
244 EXPORT RCC_IRQHandler [WEAK]
245 EXPORT EXTI0_IRQHandler [WEAK]
246 EXPORT EXTI1_IRQHandler [WEAK]
247 EXPORT EXTI2_TSC_IRQHandler [WEAK]
248 EXPORT EXTI3_IRQHandler [WEAK]
249 EXPORT EXTI4_IRQHandler [WEAK]
250 EXPORT DMA1_Channel1_IRQHandler [WEAK]
251 EXPORT DMA1_Channel2_IRQHandler [WEAK]
252 EXPORT DMA1_Channel3_IRQHandler [WEAK]
253 EXPORT DMA1_Channel4_IRQHandler [WEAK]
254 EXPORT DMA1_Channel5_IRQHandler [WEAK]
255 EXPORT DMA1_Channel6_IRQHandler [WEAK]
256 EXPORT DMA1_Channel7_IRQHandler [WEAK]
257 EXPORT ADC1_2_IRQHandler [WEAK]
258 EXPORT USB_HP_CAN_TX_IRQHandler [WEAK]
259 EXPORT USB_LP_CAN_RX0_IRQHandler [WEAK]
260 EXPORT CAN_RX1_IRQHandler [WEAK]
261 EXPORT CAN_SCE_IRQHandler [WEAK]
262 EXPORT EXTI9_5_IRQHandler [WEAK]
263 EXPORT TIM1_BRK_TIM15_IRQHandler [WEAK]
264 EXPORT TIM1_UP_TIM16_IRQHandler [WEAK]
265 EXPORT TIM1_TRG_COM_TIM17_IRQHandler [WEAK]
266 EXPORT TIM1_CC_IRQHandler [WEAK]
267 EXPORT TIM2_IRQHandler [WEAK]
268 EXPORT TIM3_IRQHandler [WEAK]
269 EXPORT TIM4_IRQHandler [WEAK]
270 EXPORT I2C1_EV_IRQHandler [WEAK]
271 EXPORT I2C1_ER_IRQHandler [WEAK]
272 EXPORT I2C2_EV_IRQHandler [WEAK]
273 EXPORT I2C2_ER_IRQHandler [WEAK]
274 EXPORT SPI1_IRQHandler [WEAK]
275 EXPORT SPI2_IRQHandler [WEAK]
276 EXPORT USART1_IRQHandler [WEAK]
277 EXPORT USART2_IRQHandler [WEAK]
278 EXPORT USART3_IRQHandler [WEAK]
279 EXPORT EXTI15_10_IRQHandler [WEAK]
280 EXPORT RTC_Alarm_IRQHandler [WEAK]
281 EXPORT USBWakeUp_IRQHandler [WEAK]
282 EXPORT SPI3_IRQHandler [WEAK]
283 EXPORT UART4_IRQHandler [WEAK]
284 EXPORT UART5_IRQHandler [WEAK]
285 EXPORT TIM6_DAC_IRQHandler [WEAK]
286 EXPORT DMA2_Channel1_IRQHandler [WEAK]
287 EXPORT DMA2_Channel2_IRQHandler [WEAK]
288 EXPORT DMA2_Channel3_IRQHandler [WEAK]
289 EXPORT DMA2_Channel4_IRQHandler [WEAK]
290 EXPORT DMA2_Channel5_IRQHandler [WEAK]
291 EXPORT COMP1_2_IRQHandler [WEAK]
292 EXPORT COMP4_6_IRQHandler [WEAK]
293 EXPORT USB_HP_IRQHandler [WEAK]
294 EXPORT USB_LP_IRQHandler [WEAK]
295 EXPORT USBWakeUp_RMP_IRQHandler [WEAK]
296 EXPORT FPU_IRQHandler [WEAK]
298 WWDG_IRQHandler
299 PVD_IRQHandler
300 TAMP_STAMP_IRQHandler
301 RTC_WKUP_IRQHandler
302 FLASH_IRQHandler
303 RCC_IRQHandler
304 EXTI0_IRQHandler
305 EXTI1_IRQHandler
306 EXTI2_TSC_IRQHandler
307 EXTI3_IRQHandler
308 EXTI4_IRQHandler
309 DMA1_Channel1_IRQHandler
310 DMA1_Channel2_IRQHandler
311 DMA1_Channel3_IRQHandler
312 DMA1_Channel4_IRQHandler
313 DMA1_Channel5_IRQHandler
314 DMA1_Channel6_IRQHandler
315 DMA1_Channel7_IRQHandler
316 ADC1_2_IRQHandler
317 USB_HP_CAN_TX_IRQHandler
318 USB_LP_CAN_RX0_IRQHandler
319 CAN_RX1_IRQHandler
320 CAN_SCE_IRQHandler
321 EXTI9_5_IRQHandler
322 TIM1_BRK_TIM15_IRQHandler
323 TIM1_UP_TIM16_IRQHandler
324 TIM1_TRG_COM_TIM17_IRQHandler
325 TIM1_CC_IRQHandler
326 TIM2_IRQHandler
327 TIM3_IRQHandler
328 TIM4_IRQHandler
329 I2C1_EV_IRQHandler
330 I2C1_ER_IRQHandler
331 I2C2_EV_IRQHandler
332 I2C2_ER_IRQHandler
333 SPI1_IRQHandler
334 SPI2_IRQHandler
335 USART1_IRQHandler
336 USART2_IRQHandler
337 USART3_IRQHandler
338 EXTI15_10_IRQHandler
339 RTC_Alarm_IRQHandler
340 USBWakeUp_IRQHandler
341 SPI3_IRQHandler
342 UART4_IRQHandler
343 UART5_IRQHandler
344 TIM6_DAC_IRQHandler
345 DMA2_Channel1_IRQHandler
346 DMA2_Channel2_IRQHandler
347 DMA2_Channel3_IRQHandler
348 DMA2_Channel4_IRQHandler
349 DMA2_Channel5_IRQHandler
350 COMP1_2_IRQHandler
351 COMP4_6_IRQHandler
352 USB_HP_IRQHandler
353 USB_LP_IRQHandler
354 USBWakeUp_RMP_IRQHandler
355 FPU_IRQHandler
359 ENDP
361 ALIGN
363 ;*******************************************************************************
364 ; User Stack and Heap initialization
365 ;*******************************************************************************
366 IF :DEF:__MICROLIB
368 EXPORT __initial_sp
369 EXPORT __heap_base
370 EXPORT __heap_limit
372 ELSE
374 IMPORT __use_two_region_memory
375 EXPORT __user_initial_stackheap
377 __user_initial_stackheap
379 LDR R0, = Heap_Mem
380 LDR R1, =(Stack_Mem + Stack_Size)
381 LDR R2, = (Heap_Mem + Heap_Size)
382 LDR R3, = Stack_Mem
383 BX LR
385 ALIGN
387 ENDIF
391 ;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****