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F1 and F3 HAL / LL libraries
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_ll_dma.h
blob9683c21ddf6e7c7a3a02d0190be94bcedc9f68a1
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_ll_dma.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of DMA LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_LL_DMA_H
40 #define __STM32F1xx_LL_DMA_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx.h"
48
49 /** @addtogroup STM32F1xx_LL_Driver
50 * @{
51 */
52
53 #if defined (DMA1) || defined (DMA2)
54
55 /** @defgroup DMA_LL DMA
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
62 * @{
63 */
64 /* Array used to get the DMA channel register offset versus channel index LL_DMA_CHANNEL_x */
65 static const uint8_t CHANNEL_OFFSET_TAB[] =
66 {
67 (uint8_t)(DMA1_Channel1_BASE - DMA1_BASE),
68 (uint8_t)(DMA1_Channel2_BASE - DMA1_BASE),
69 (uint8_t)(DMA1_Channel3_BASE - DMA1_BASE),
70 (uint8_t)(DMA1_Channel4_BASE - DMA1_BASE),
71 (uint8_t)(DMA1_Channel5_BASE - DMA1_BASE),
72 (uint8_t)(DMA1_Channel6_BASE - DMA1_BASE),
73 (uint8_t)(DMA1_Channel7_BASE - DMA1_BASE)
74 };
75 /**
76 * @}
77 */
78 /* Private constants ---------------------------------------------------------*/
79 /* Private macros ------------------------------------------------------------*/
80 #if defined(USE_FULL_LL_DRIVER)
81 /** @defgroup DMA_LL_Private_Macros DMA Private Macros
82 * @{
83 */
84 /**
85 * @}
86 */
87 #endif /*USE_FULL_LL_DRIVER*/
88
89 /* Exported types ------------------------------------------------------------*/
90 #if defined(USE_FULL_LL_DRIVER)
91 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
92 * @{
93 */
94 typedef struct
95 {
96 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
97 or as Source base address in case of memory to memory transfer direction.
98
99 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
100
101 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
102 or as Destination base address in case of memory to memory transfer direction.
103
104 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
105
106 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
107 from memory to memory or from peripheral to memory.
108 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
109
110 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
111
112 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
113 This parameter can be a value of @ref DMA_LL_EC_MODE
114 @note: The circular buffer mode cannot be used if the memory to memory
115 data transfer direction is configured on the selected Channel
116
117 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
118
119 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
120 is incremented or not.
121 This parameter can be a value of @ref DMA_LL_EC_PERIPH
122
123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
124
125 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
126 is incremented or not.
127 This parameter can be a value of @ref DMA_LL_EC_MEMORY
128
129 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
130
131 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
132 in case of memory to memory transfer direction.
133 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
134
135 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
136
137 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
138 in case of memory to memory transfer direction.
139 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
140
141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
142
143 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
144 The data unit is equal to the source buffer configuration set in PeripheralSize
145 or MemorySize parameters depending in the transfer direction.
146 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
147
148 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
149
150 uint32_t Priority; /*!< Specifies the channel priority level.
151 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
152
153 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelPriorityLevel(). */
154
155 } LL_DMA_InitTypeDef;
156 /**
157 * @}
158 */
159 #endif /*USE_FULL_LL_DRIVER*/
160
161 /* Exported constants --------------------------------------------------------*/
162 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
163 * @{
164 */
165 /** @defgroup DMA_LL_EC_CLEAR_FLAG Clear Flags Defines
166 * @brief Flags defines which can be used with LL_DMA_WriteReg function
167 * @{
168 */
169 #define LL_DMA_IFCR_CGIF1 DMA_IFCR_CGIF1 /*!< Channel 1 global flag */
170 #define LL_DMA_IFCR_CTCIF1 DMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
171 #define LL_DMA_IFCR_CHTIF1 DMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
172 #define LL_DMA_IFCR_CTEIF1 DMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
173 #define LL_DMA_IFCR_CGIF2 DMA_IFCR_CGIF2 /*!< Channel 2 global flag */
174 #define LL_DMA_IFCR_CTCIF2 DMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
175 #define LL_DMA_IFCR_CHTIF2 DMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
176 #define LL_DMA_IFCR_CTEIF2 DMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
177 #define LL_DMA_IFCR_CGIF3 DMA_IFCR_CGIF3 /*!< Channel 3 global flag */
178 #define LL_DMA_IFCR_CTCIF3 DMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
179 #define LL_DMA_IFCR_CHTIF3 DMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
180 #define LL_DMA_IFCR_CTEIF3 DMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
181 #define LL_DMA_IFCR_CGIF4 DMA_IFCR_CGIF4 /*!< Channel 4 global flag */
182 #define LL_DMA_IFCR_CTCIF4 DMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
183 #define LL_DMA_IFCR_CHTIF4 DMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
184 #define LL_DMA_IFCR_CTEIF4 DMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
185 #define LL_DMA_IFCR_CGIF5 DMA_IFCR_CGIF5 /*!< Channel 5 global flag */
186 #define LL_DMA_IFCR_CTCIF5 DMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
187 #define LL_DMA_IFCR_CHTIF5 DMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
188 #define LL_DMA_IFCR_CTEIF5 DMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
189 #define LL_DMA_IFCR_CGIF6 DMA_IFCR_CGIF6 /*!< Channel 6 global flag */
190 #define LL_DMA_IFCR_CTCIF6 DMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
191 #define LL_DMA_IFCR_CHTIF6 DMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
192 #define LL_DMA_IFCR_CTEIF6 DMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
193 #define LL_DMA_IFCR_CGIF7 DMA_IFCR_CGIF7 /*!< Channel 7 global flag */
194 #define LL_DMA_IFCR_CTCIF7 DMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
195 #define LL_DMA_IFCR_CHTIF7 DMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
196 #define LL_DMA_IFCR_CTEIF7 DMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
197 /**
198 * @}
199 */
200
201 /** @defgroup DMA_LL_EC_GET_FLAG Get Flags Defines
202 * @brief Flags defines which can be used with LL_DMA_ReadReg function
203 * @{
204 */
205 #define LL_DMA_ISR_GIF1 DMA_ISR_GIF1 /*!< Channel 1 global flag */
206 #define LL_DMA_ISR_TCIF1 DMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
207 #define LL_DMA_ISR_HTIF1 DMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
208 #define LL_DMA_ISR_TEIF1 DMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
209 #define LL_DMA_ISR_GIF2 DMA_ISR_GIF2 /*!< Channel 2 global flag */
210 #define LL_DMA_ISR_TCIF2 DMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
211 #define LL_DMA_ISR_HTIF2 DMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
212 #define LL_DMA_ISR_TEIF2 DMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
213 #define LL_DMA_ISR_GIF3 DMA_ISR_GIF3 /*!< Channel 3 global flag */
214 #define LL_DMA_ISR_TCIF3 DMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
215 #define LL_DMA_ISR_HTIF3 DMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
216 #define LL_DMA_ISR_TEIF3 DMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
217 #define LL_DMA_ISR_GIF4 DMA_ISR_GIF4 /*!< Channel 4 global flag */
218 #define LL_DMA_ISR_TCIF4 DMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
219 #define LL_DMA_ISR_HTIF4 DMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
220 #define LL_DMA_ISR_TEIF4 DMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
221 #define LL_DMA_ISR_GIF5 DMA_ISR_GIF5 /*!< Channel 5 global flag */
222 #define LL_DMA_ISR_TCIF5 DMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
223 #define LL_DMA_ISR_HTIF5 DMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
224 #define LL_DMA_ISR_TEIF5 DMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
225 #define LL_DMA_ISR_GIF6 DMA_ISR_GIF6 /*!< Channel 6 global flag */
226 #define LL_DMA_ISR_TCIF6 DMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
227 #define LL_DMA_ISR_HTIF6 DMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
228 #define LL_DMA_ISR_TEIF6 DMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
229 #define LL_DMA_ISR_GIF7 DMA_ISR_GIF7 /*!< Channel 7 global flag */
230 #define LL_DMA_ISR_TCIF7 DMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
231 #define LL_DMA_ISR_HTIF7 DMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
232 #define LL_DMA_ISR_TEIF7 DMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
233 /**
234 * @}
235 */
236
237 /** @defgroup DMA_LL_EC_IT IT Defines
238 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMA_WriteReg functions
239 * @{
240 */
241 #define LL_DMA_CCR_TCIE DMA_CCR_TCIE /*!< Transfer complete interrupt */
242 #define LL_DMA_CCR_HTIE DMA_CCR_HTIE /*!< Half Transfer interrupt */
243 #define LL_DMA_CCR_TEIE DMA_CCR_TEIE /*!< Transfer error interrupt */
244 /**
245 * @}
246 */
247
248 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
249 * @{
250 */
251 #define LL_DMA_CHANNEL_1 0x00000001U /*!< DMA Channel 1 */
252 #define LL_DMA_CHANNEL_2 0x00000002U /*!< DMA Channel 2 */
253 #define LL_DMA_CHANNEL_3 0x00000003U /*!< DMA Channel 3 */
254 #define LL_DMA_CHANNEL_4 0x00000004U /*!< DMA Channel 4 */
255 #define LL_DMA_CHANNEL_5 0x00000005U /*!< DMA Channel 5 */
256 #define LL_DMA_CHANNEL_6 0x00000006U /*!< DMA Channel 6 */
257 #define LL_DMA_CHANNEL_7 0x00000007U /*!< DMA Channel 7 */
258 #if defined(USE_FULL_LL_DRIVER)
259 #define LL_DMA_CHANNEL_ALL 0xFFFF0000U /*!< DMA Channel all (used only for function @ref LL_DMA_DeInit(). */
260 #endif /*USE_FULL_LL_DRIVER*/
261 /**
262 * @}
263 */
264
265 /** @defgroup DMA_LL_EC_DIRECTION Transfer Direction
266 * @{
267 */
268 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
269 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_CCR_DIR /*!< Memory to peripheral direction */
270 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_CCR_MEM2MEM /*!< Memory to memory direction */
271 /**
272 * @}
273 */
274
275 /** @defgroup DMA_LL_EC_MODE Transfer mode
276 * @{
277 */
278 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
279 #define LL_DMA_MODE_CIRCULAR DMA_CCR_CIRC /*!< Circular Mode */
280 /**
281 * @}
282 */
283
284 /** @defgroup DMA_LL_EC_PERIPH Peripheral increment mode
285 * @{
286 */
287 #define LL_DMA_PERIPH_INCREMENT DMA_CCR_PINC /*!< Peripheral increment mode Enable */
288 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
289 /**
290 * @}
291 */
292
293 /** @defgroup DMA_LL_EC_MEMORY Memory increment mode
294 * @{
295 */
296 #define LL_DMA_MEMORY_INCREMENT DMA_CCR_MINC /*!< Memory increment mode Enable */
297 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
298 /**
299 * @}
300 */
301
302 /** @defgroup DMA_LL_EC_PDATAALIGN Peripheral data alignment
303 * @{
304 */
305 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
306 #define LL_DMA_PDATAALIGN_HALFWORD DMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
307 #define LL_DMA_PDATAALIGN_WORD DMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
308 /**
309 * @}
310 */
311
312 /** @defgroup DMA_LL_EC_MDATAALIGN Memory data alignment
313 * @{
314 */
315 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
316 #define LL_DMA_MDATAALIGN_HALFWORD DMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
317 #define LL_DMA_MDATAALIGN_WORD DMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
318 /**
319 * @}
320 */
321
322 /** @defgroup DMA_LL_EC_PRIORITY Transfer Priority level
323 * @{
324 */
325 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
326 #define LL_DMA_PRIORITY_MEDIUM DMA_CCR_PL_0 /*!< Priority level : Medium */
327 #define LL_DMA_PRIORITY_HIGH DMA_CCR_PL_1 /*!< Priority level : High */
328 #define LL_DMA_PRIORITY_VERYHIGH DMA_CCR_PL /*!< Priority level : Very_High */
329 /**
330 * @}
331 */
332
333 /**
334 * @}
335 */
336
337 /* Exported macro ------------------------------------------------------------*/
338 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
339 * @{
340 */
341
342 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
343 * @{
344 */
345 /**
346 * @brief Write a value in DMA register
347 * @param __INSTANCE__ DMA Instance
348 * @param __REG__ Register to be written
349 * @param __VALUE__ Value to be written in the register
350 * @retval None
351 */
352 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
353
354 /**
355 * @brief Read a value in DMA register
356 * @param __INSTANCE__ DMA Instance
357 * @param __REG__ Register to be read
358 * @retval Register value
359 */
360 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
361 /**
362 * @}
363 */
364
365 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxChannely
366 * @{
367 */
368
369 /**
370 * @brief Convert DMAx_Channely into DMAx
371 * @param __CHANNEL_INSTANCE__ DMAx_Channely
372 * @retval DMAx
373 */
374 #if defined(DMA2)
375 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
376 (((uint32_t)(__CHANNEL_INSTANCE__) > ((uint32_t)DMA1_Channel7)) ? DMA2 : DMA1)
377 #else
378 #define __LL_DMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (DMA1)
379 #endif
380
381 /**
382 * @brief Convert DMAx_Channely into LL_DMA_CHANNEL_y
383 * @param __CHANNEL_INSTANCE__ DMAx_Channely
384 * @retval LL_DMA_CHANNEL_y
385 */
386 #if defined (DMA2)
387 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
388 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
389 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel1)) ? LL_DMA_CHANNEL_1 : \
390 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
391 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel2)) ? LL_DMA_CHANNEL_2 : \
392 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
393 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel3)) ? LL_DMA_CHANNEL_3 : \
394 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
395 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel4)) ? LL_DMA_CHANNEL_4 : \
396 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
397 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA2_Channel5)) ? LL_DMA_CHANNEL_5 : \
398 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
399 LL_DMA_CHANNEL_7)
400 #else
401 #define __LL_DMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
402 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel1)) ? LL_DMA_CHANNEL_1 : \
403 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel2)) ? LL_DMA_CHANNEL_2 : \
404 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel3)) ? LL_DMA_CHANNEL_3 : \
405 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel4)) ? LL_DMA_CHANNEL_4 : \
406 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel5)) ? LL_DMA_CHANNEL_5 : \
407 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)DMA1_Channel6)) ? LL_DMA_CHANNEL_6 : \
408 LL_DMA_CHANNEL_7)
409 #endif
410
411 /**
412 * @brief Convert DMA Instance DMAx and LL_DMA_CHANNEL_y into DMAx_Channely
413 * @param __DMA_INSTANCE__ DMAx
414 * @param __CHANNEL__ LL_DMA_CHANNEL_y
415 * @retval DMAx_Channely
416 */
417 #if defined (DMA2)
418 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
419 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
420 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA2_Channel1 : \
421 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
422 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA2_Channel2 : \
423 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
424 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA2_Channel3 : \
425 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
426 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA2_Channel4 : \
427 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA2_Channel5 : \
429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
430 DMA1_Channel7)
431 #else
432 #define __LL_DMA_GET_CHANNEL_INSTANCE(__DMA_INSTANCE__, __CHANNEL__) \
433 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_1))) ? DMA1_Channel1 : \
434 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_2))) ? DMA1_Channel2 : \
435 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_3))) ? DMA1_Channel3 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_4))) ? DMA1_Channel4 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_5))) ? DMA1_Channel5 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_DMA_CHANNEL_6))) ? DMA1_Channel6 : \
439 DMA1_Channel7)
440 #endif
441
442 /**
443 * @}
444 */
445
446 /**
447 * @}
448 */
449
450 /* Exported functions --------------------------------------------------------*/
451 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
452 * @{
453 */
454
455 /** @defgroup DMA_LL_EF_Configuration Configuration
456 * @{
457 */
458 /**
459 * @brief Enable DMA channel.
460 * @rmtoll CCR EN LL_DMA_EnableChannel
461 * @param DMAx DMAx Instance
462 * @param Channel This parameter can be one of the following values:
463 * @arg @ref LL_DMA_CHANNEL_1
464 * @arg @ref LL_DMA_CHANNEL_2
465 * @arg @ref LL_DMA_CHANNEL_3
466 * @arg @ref LL_DMA_CHANNEL_4
467 * @arg @ref LL_DMA_CHANNEL_5
468 * @arg @ref LL_DMA_CHANNEL_6
469 * @arg @ref LL_DMA_CHANNEL_7
470 * @retval None
471 */
472 __STATIC_INLINE void LL_DMA_EnableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
473 {
474 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
475 }
476
477 /**
478 * @brief Disable DMA channel.
479 * @rmtoll CCR EN LL_DMA_DisableChannel
480 * @param DMAx DMAx Instance
481 * @param Channel This parameter can be one of the following values:
482 * @arg @ref LL_DMA_CHANNEL_1
483 * @arg @ref LL_DMA_CHANNEL_2
484 * @arg @ref LL_DMA_CHANNEL_3
485 * @arg @ref LL_DMA_CHANNEL_4
486 * @arg @ref LL_DMA_CHANNEL_5
487 * @arg @ref LL_DMA_CHANNEL_6
488 * @arg @ref LL_DMA_CHANNEL_7
489 * @retval None
490 */
491 __STATIC_INLINE void LL_DMA_DisableChannel(DMA_TypeDef *DMAx, uint32_t Channel)
492 {
493 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_EN);
494 }
495
496 /**
497 * @brief Check if DMA channel is enabled or disabled.
498 * @rmtoll CCR EN LL_DMA_IsEnabledChannel
499 * @param DMAx DMAx Instance
500 * @param Channel This parameter can be one of the following values:
501 * @arg @ref LL_DMA_CHANNEL_1
502 * @arg @ref LL_DMA_CHANNEL_2
503 * @arg @ref LL_DMA_CHANNEL_3
504 * @arg @ref LL_DMA_CHANNEL_4
505 * @arg @ref LL_DMA_CHANNEL_5
506 * @arg @ref LL_DMA_CHANNEL_6
507 * @arg @ref LL_DMA_CHANNEL_7
508 * @retval State of bit (1 or 0).
509 */
510 __STATIC_INLINE uint32_t LL_DMA_IsEnabledChannel(DMA_TypeDef *DMAx, uint32_t Channel)
511 {
512 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
513 DMA_CCR_EN) == (DMA_CCR_EN));
514 }
515
516 /**
517 * @brief Configure all parameters link to DMA transfer.
518 * @rmtoll CCR DIR LL_DMA_ConfigTransfer\n
519 * CCR MEM2MEM LL_DMA_ConfigTransfer\n
520 * CCR CIRC LL_DMA_ConfigTransfer\n
521 * CCR PINC LL_DMA_ConfigTransfer\n
522 * CCR MINC LL_DMA_ConfigTransfer\n
523 * CCR PSIZE LL_DMA_ConfigTransfer\n
524 * CCR MSIZE LL_DMA_ConfigTransfer\n
525 * CCR PL LL_DMA_ConfigTransfer
526 * @param DMAx DMAx Instance
527 * @param Channel This parameter can be one of the following values:
528 * @arg @ref LL_DMA_CHANNEL_1
529 * @arg @ref LL_DMA_CHANNEL_2
530 * @arg @ref LL_DMA_CHANNEL_3
531 * @arg @ref LL_DMA_CHANNEL_4
532 * @arg @ref LL_DMA_CHANNEL_5
533 * @arg @ref LL_DMA_CHANNEL_6
534 * @arg @ref LL_DMA_CHANNEL_7
535 * @param Configuration This parameter must be a combination of all the following values:
536 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
537 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR
538 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
539 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
540 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
541 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
542 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
543 * @retval None
544 */
545 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Configuration)
546 {
547 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
548 DMA_CCR_DIR | DMA_CCR_MEM2MEM | DMA_CCR_CIRC | DMA_CCR_PINC | DMA_CCR_MINC | DMA_CCR_PSIZE | DMA_CCR_MSIZE | DMA_CCR_PL,
549 Configuration);
550 }
551
552 /**
553 * @brief Set Data transfer direction (read from peripheral or from memory).
554 * @rmtoll CCR DIR LL_DMA_SetDataTransferDirection\n
555 * CCR MEM2MEM LL_DMA_SetDataTransferDirection
556 * @param DMAx DMAx Instance
557 * @param Channel This parameter can be one of the following values:
558 * @arg @ref LL_DMA_CHANNEL_1
559 * @arg @ref LL_DMA_CHANNEL_2
560 * @arg @ref LL_DMA_CHANNEL_3
561 * @arg @ref LL_DMA_CHANNEL_4
562 * @arg @ref LL_DMA_CHANNEL_5
563 * @arg @ref LL_DMA_CHANNEL_6
564 * @arg @ref LL_DMA_CHANNEL_7
565 * @param Direction This parameter can be one of the following values:
566 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
567 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
568 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
569 * @retval None
570 */
571 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Direction)
572 {
573 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
574 DMA_CCR_DIR | DMA_CCR_MEM2MEM, Direction);
575 }
576
577 /**
578 * @brief Get Data transfer direction (read from peripheral or from memory).
579 * @rmtoll CCR DIR LL_DMA_GetDataTransferDirection\n
580 * CCR MEM2MEM LL_DMA_GetDataTransferDirection
581 * @param DMAx DMAx Instance
582 * @param Channel This parameter can be one of the following values:
583 * @arg @ref LL_DMA_CHANNEL_1
584 * @arg @ref LL_DMA_CHANNEL_2
585 * @arg @ref LL_DMA_CHANNEL_3
586 * @arg @ref LL_DMA_CHANNEL_4
587 * @arg @ref LL_DMA_CHANNEL_5
588 * @arg @ref LL_DMA_CHANNEL_6
589 * @arg @ref LL_DMA_CHANNEL_7
590 * @retval Returned value can be one of the following values:
591 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
592 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
593 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
594 */
595 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Channel)
596 {
597 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
598 DMA_CCR_DIR | DMA_CCR_MEM2MEM));
599 }
600
601 /**
602 * @brief Set DMA mode circular or normal.
603 * @note The circular buffer mode cannot be used if the memory-to-memory
604 * data transfer is configured on the selected Channel.
605 * @rmtoll CCR CIRC LL_DMA_SetMode
606 * @param DMAx DMAx Instance
607 * @param Channel This parameter can be one of the following values:
608 * @arg @ref LL_DMA_CHANNEL_1
609 * @arg @ref LL_DMA_CHANNEL_2
610 * @arg @ref LL_DMA_CHANNEL_3
611 * @arg @ref LL_DMA_CHANNEL_4
612 * @arg @ref LL_DMA_CHANNEL_5
613 * @arg @ref LL_DMA_CHANNEL_6
614 * @arg @ref LL_DMA_CHANNEL_7
615 * @param Mode This parameter can be one of the following values:
616 * @arg @ref LL_DMA_MODE_NORMAL
617 * @arg @ref LL_DMA_MODE_CIRCULAR
618 * @retval None
619 */
620 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Mode)
621 {
622 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_CIRC,
623 Mode);
624 }
625
626 /**
627 * @brief Get DMA mode circular or normal.
628 * @rmtoll CCR CIRC LL_DMA_GetMode
629 * @param DMAx DMAx Instance
630 * @param Channel This parameter can be one of the following values:
631 * @arg @ref LL_DMA_CHANNEL_1
632 * @arg @ref LL_DMA_CHANNEL_2
633 * @arg @ref LL_DMA_CHANNEL_3
634 * @arg @ref LL_DMA_CHANNEL_4
635 * @arg @ref LL_DMA_CHANNEL_5
636 * @arg @ref LL_DMA_CHANNEL_6
637 * @arg @ref LL_DMA_CHANNEL_7
638 * @retval Returned value can be one of the following values:
639 * @arg @ref LL_DMA_MODE_NORMAL
640 * @arg @ref LL_DMA_MODE_CIRCULAR
641 */
642 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Channel)
643 {
644 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
645 DMA_CCR_CIRC));
646 }
647
648 /**
649 * @brief Set Peripheral increment mode.
650 * @rmtoll CCR PINC LL_DMA_SetPeriphIncMode
651 * @param DMAx DMAx Instance
652 * @param Channel This parameter can be one of the following values:
653 * @arg @ref LL_DMA_CHANNEL_1
654 * @arg @ref LL_DMA_CHANNEL_2
655 * @arg @ref LL_DMA_CHANNEL_3
656 * @arg @ref LL_DMA_CHANNEL_4
657 * @arg @ref LL_DMA_CHANNEL_5
658 * @arg @ref LL_DMA_CHANNEL_6
659 * @arg @ref LL_DMA_CHANNEL_7
660 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
661 * @arg @ref LL_DMA_PERIPH_INCREMENT
662 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
663 * @retval None
664 */
665 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
666 {
667 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PINC,
668 PeriphOrM2MSrcIncMode);
669 }
670
671 /**
672 * @brief Get Peripheral increment mode.
673 * @rmtoll CCR PINC LL_DMA_GetPeriphIncMode
674 * @param DMAx DMAx Instance
675 * @param Channel This parameter can be one of the following values:
676 * @arg @ref LL_DMA_CHANNEL_1
677 * @arg @ref LL_DMA_CHANNEL_2
678 * @arg @ref LL_DMA_CHANNEL_3
679 * @arg @ref LL_DMA_CHANNEL_4
680 * @arg @ref LL_DMA_CHANNEL_5
681 * @arg @ref LL_DMA_CHANNEL_6
682 * @arg @ref LL_DMA_CHANNEL_7
683 * @retval Returned value can be one of the following values:
684 * @arg @ref LL_DMA_PERIPH_INCREMENT
685 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
686 */
687 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
688 {
689 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
690 DMA_CCR_PINC));
691 }
692
693 /**
694 * @brief Set Memory increment mode.
695 * @rmtoll CCR MINC LL_DMA_SetMemoryIncMode
696 * @param DMAx DMAx Instance
697 * @param Channel This parameter can be one of the following values:
698 * @arg @ref LL_DMA_CHANNEL_1
699 * @arg @ref LL_DMA_CHANNEL_2
700 * @arg @ref LL_DMA_CHANNEL_3
701 * @arg @ref LL_DMA_CHANNEL_4
702 * @arg @ref LL_DMA_CHANNEL_5
703 * @arg @ref LL_DMA_CHANNEL_6
704 * @arg @ref LL_DMA_CHANNEL_7
705 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
706 * @arg @ref LL_DMA_MEMORY_INCREMENT
707 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
708 * @retval None
709 */
710 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
711 {
712 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MINC,
713 MemoryOrM2MDstIncMode);
714 }
715
716 /**
717 * @brief Get Memory increment mode.
718 * @rmtoll CCR MINC LL_DMA_GetMemoryIncMode
719 * @param DMAx DMAx Instance
720 * @param Channel This parameter can be one of the following values:
721 * @arg @ref LL_DMA_CHANNEL_1
722 * @arg @ref LL_DMA_CHANNEL_2
723 * @arg @ref LL_DMA_CHANNEL_3
724 * @arg @ref LL_DMA_CHANNEL_4
725 * @arg @ref LL_DMA_CHANNEL_5
726 * @arg @ref LL_DMA_CHANNEL_6
727 * @arg @ref LL_DMA_CHANNEL_7
728 * @retval Returned value can be one of the following values:
729 * @arg @ref LL_DMA_MEMORY_INCREMENT
730 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
731 */
732 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Channel)
733 {
734 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
735 DMA_CCR_MINC));
736 }
737
738 /**
739 * @brief Set Peripheral size.
740 * @rmtoll CCR PSIZE LL_DMA_SetPeriphSize
741 * @param DMAx DMAx Instance
742 * @param Channel This parameter can be one of the following values:
743 * @arg @ref LL_DMA_CHANNEL_1
744 * @arg @ref LL_DMA_CHANNEL_2
745 * @arg @ref LL_DMA_CHANNEL_3
746 * @arg @ref LL_DMA_CHANNEL_4
747 * @arg @ref LL_DMA_CHANNEL_5
748 * @arg @ref LL_DMA_CHANNEL_6
749 * @arg @ref LL_DMA_CHANNEL_7
750 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
751 * @arg @ref LL_DMA_PDATAALIGN_BYTE
752 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
753 * @arg @ref LL_DMA_PDATAALIGN_WORD
754 * @retval None
755 */
756 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
757 {
758 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PSIZE,
759 PeriphOrM2MSrcDataSize);
760 }
761
762 /**
763 * @brief Get Peripheral size.
764 * @rmtoll CCR PSIZE LL_DMA_GetPeriphSize
765 * @param DMAx DMAx Instance
766 * @param Channel This parameter can be one of the following values:
767 * @arg @ref LL_DMA_CHANNEL_1
768 * @arg @ref LL_DMA_CHANNEL_2
769 * @arg @ref LL_DMA_CHANNEL_3
770 * @arg @ref LL_DMA_CHANNEL_4
771 * @arg @ref LL_DMA_CHANNEL_5
772 * @arg @ref LL_DMA_CHANNEL_6
773 * @arg @ref LL_DMA_CHANNEL_7
774 * @retval Returned value can be one of the following values:
775 * @arg @ref LL_DMA_PDATAALIGN_BYTE
776 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
777 * @arg @ref LL_DMA_PDATAALIGN_WORD
778 */
779 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Channel)
780 {
781 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
782 DMA_CCR_PSIZE));
783 }
784
785 /**
786 * @brief Set Memory size.
787 * @rmtoll CCR MSIZE LL_DMA_SetMemorySize
788 * @param DMAx DMAx Instance
789 * @param Channel This parameter can be one of the following values:
790 * @arg @ref LL_DMA_CHANNEL_1
791 * @arg @ref LL_DMA_CHANNEL_2
792 * @arg @ref LL_DMA_CHANNEL_3
793 * @arg @ref LL_DMA_CHANNEL_4
794 * @arg @ref LL_DMA_CHANNEL_5
795 * @arg @ref LL_DMA_CHANNEL_6
796 * @arg @ref LL_DMA_CHANNEL_7
797 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
798 * @arg @ref LL_DMA_MDATAALIGN_BYTE
799 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
800 * @arg @ref LL_DMA_MDATAALIGN_WORD
801 * @retval None
802 */
803 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
804 {
805 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_MSIZE,
806 MemoryOrM2MDstDataSize);
807 }
808
809 /**
810 * @brief Get Memory size.
811 * @rmtoll CCR MSIZE LL_DMA_GetMemorySize
812 * @param DMAx DMAx Instance
813 * @param Channel This parameter can be one of the following values:
814 * @arg @ref LL_DMA_CHANNEL_1
815 * @arg @ref LL_DMA_CHANNEL_2
816 * @arg @ref LL_DMA_CHANNEL_3
817 * @arg @ref LL_DMA_CHANNEL_4
818 * @arg @ref LL_DMA_CHANNEL_5
819 * @arg @ref LL_DMA_CHANNEL_6
820 * @arg @ref LL_DMA_CHANNEL_7
821 * @retval Returned value can be one of the following values:
822 * @arg @ref LL_DMA_MDATAALIGN_BYTE
823 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
824 * @arg @ref LL_DMA_MDATAALIGN_WORD
825 */
826 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Channel)
827 {
828 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
829 DMA_CCR_MSIZE));
830 }
831
832 /**
833 * @brief Set Channel priority level.
834 * @rmtoll CCR PL LL_DMA_SetChannelPriorityLevel
835 * @param DMAx DMAx Instance
836 * @param Channel This parameter can be one of the following values:
837 * @arg @ref LL_DMA_CHANNEL_1
838 * @arg @ref LL_DMA_CHANNEL_2
839 * @arg @ref LL_DMA_CHANNEL_3
840 * @arg @ref LL_DMA_CHANNEL_4
841 * @arg @ref LL_DMA_CHANNEL_5
842 * @arg @ref LL_DMA_CHANNEL_6
843 * @arg @ref LL_DMA_CHANNEL_7
844 * @param Priority This parameter can be one of the following values:
845 * @arg @ref LL_DMA_PRIORITY_LOW
846 * @arg @ref LL_DMA_PRIORITY_MEDIUM
847 * @arg @ref LL_DMA_PRIORITY_HIGH
848 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
849 * @retval None
850 */
851 __STATIC_INLINE void LL_DMA_SetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t Priority)
852 {
853 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_PL,
854 Priority);
855 }
856
857 /**
858 * @brief Get Channel priority level.
859 * @rmtoll CCR PL LL_DMA_GetChannelPriorityLevel
860 * @param DMAx DMAx Instance
861 * @param Channel This parameter can be one of the following values:
862 * @arg @ref LL_DMA_CHANNEL_1
863 * @arg @ref LL_DMA_CHANNEL_2
864 * @arg @ref LL_DMA_CHANNEL_3
865 * @arg @ref LL_DMA_CHANNEL_4
866 * @arg @ref LL_DMA_CHANNEL_5
867 * @arg @ref LL_DMA_CHANNEL_6
868 * @arg @ref LL_DMA_CHANNEL_7
869 * @retval Returned value can be one of the following values:
870 * @arg @ref LL_DMA_PRIORITY_LOW
871 * @arg @ref LL_DMA_PRIORITY_MEDIUM
872 * @arg @ref LL_DMA_PRIORITY_HIGH
873 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
874 */
875 __STATIC_INLINE uint32_t LL_DMA_GetChannelPriorityLevel(DMA_TypeDef *DMAx, uint32_t Channel)
876 {
877 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
878 DMA_CCR_PL));
879 }
880
881 /**
882 * @brief Set Number of data to transfer.
883 * @note This action has no effect if
884 * channel is enabled.
885 * @rmtoll CNDTR NDT LL_DMA_SetDataLength
886 * @param DMAx DMAx Instance
887 * @param Channel This parameter can be one of the following values:
888 * @arg @ref LL_DMA_CHANNEL_1
889 * @arg @ref LL_DMA_CHANNEL_2
890 * @arg @ref LL_DMA_CHANNEL_3
891 * @arg @ref LL_DMA_CHANNEL_4
892 * @arg @ref LL_DMA_CHANNEL_5
893 * @arg @ref LL_DMA_CHANNEL_6
894 * @arg @ref LL_DMA_CHANNEL_7
895 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
896 * @retval None
897 */
898 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t NbData)
899 {
900 MODIFY_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
901 DMA_CNDTR_NDT, NbData);
902 }
903
904 /**
905 * @brief Get Number of data to transfer.
906 * @note Once the channel is enabled, the return value indicate the
907 * remaining bytes to be transmitted.
908 * @rmtoll CNDTR NDT LL_DMA_GetDataLength
909 * @param DMAx DMAx Instance
910 * @param Channel This parameter can be one of the following values:
911 * @arg @ref LL_DMA_CHANNEL_1
912 * @arg @ref LL_DMA_CHANNEL_2
913 * @arg @ref LL_DMA_CHANNEL_3
914 * @arg @ref LL_DMA_CHANNEL_4
915 * @arg @ref LL_DMA_CHANNEL_5
916 * @arg @ref LL_DMA_CHANNEL_6
917 * @arg @ref LL_DMA_CHANNEL_7
918 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
919 */
920 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef *DMAx, uint32_t Channel)
921 {
922 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CNDTR,
923 DMA_CNDTR_NDT));
924 }
925
926 /**
927 * @brief Configure the Source and Destination addresses.
928 * @note This API must not be called when the DMA channel is enabled.
929 * @note Each IP using DMA provides an API to get directly the register adress (LL_PPP_DMA_GetRegAddr).
930 * @rmtoll CPAR PA LL_DMA_ConfigAddresses\n
931 * CMAR MA LL_DMA_ConfigAddresses
932 * @param DMAx DMAx Instance
933 * @param Channel This parameter can be one of the following values:
934 * @arg @ref LL_DMA_CHANNEL_1
935 * @arg @ref LL_DMA_CHANNEL_2
936 * @arg @ref LL_DMA_CHANNEL_3
937 * @arg @ref LL_DMA_CHANNEL_4
938 * @arg @ref LL_DMA_CHANNEL_5
939 * @arg @ref LL_DMA_CHANNEL_6
940 * @arg @ref LL_DMA_CHANNEL_7
941 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
942 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
943 * @param Direction This parameter can be one of the following values:
944 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
945 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
946 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
947 * @retval None
948 */
949 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t SrcAddress,
950 uint32_t DstAddress, uint32_t Direction)
951 {
952 /* Direction Memory to Periph */
953 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
954 {
955 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, SrcAddress);
956 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, DstAddress);
957 }
958 /* Direction Periph to Memory and Memory to Memory */
959 else
960 {
961 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, SrcAddress);
962 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, DstAddress);
963 }
964 }
965
966 /**
967 * @brief Set the Memory address.
968 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
969 * @note This API must not be called when the DMA channel is enabled.
970 * @rmtoll CMAR MA LL_DMA_SetMemoryAddress
971 * @param DMAx DMAx Instance
972 * @param Channel This parameter can be one of the following values:
973 * @arg @ref LL_DMA_CHANNEL_1
974 * @arg @ref LL_DMA_CHANNEL_2
975 * @arg @ref LL_DMA_CHANNEL_3
976 * @arg @ref LL_DMA_CHANNEL_4
977 * @arg @ref LL_DMA_CHANNEL_5
978 * @arg @ref LL_DMA_CHANNEL_6
979 * @arg @ref LL_DMA_CHANNEL_7
980 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
981 * @retval None
982 */
983 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
984 {
985 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
986 }
987
988 /**
989 * @brief Set the Peripheral address.
990 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
991 * @note This API must not be called when the DMA channel is enabled.
992 * @rmtoll CPAR PA LL_DMA_SetPeriphAddress
993 * @param DMAx DMAx Instance
994 * @param Channel This parameter can be one of the following values:
995 * @arg @ref LL_DMA_CHANNEL_1
996 * @arg @ref LL_DMA_CHANNEL_2
997 * @arg @ref LL_DMA_CHANNEL_3
998 * @arg @ref LL_DMA_CHANNEL_4
999 * @arg @ref LL_DMA_CHANNEL_5
1000 * @arg @ref LL_DMA_CHANNEL_6
1001 * @arg @ref LL_DMA_CHANNEL_7
1002 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1003 * @retval None
1004 */
1005 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t PeriphAddress)
1006 {
1007 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, PeriphAddress);
1008 }
1009
1010 /**
1011 * @brief Get Memory address.
1012 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1013 * @rmtoll CMAR MA LL_DMA_GetMemoryAddress
1014 * @param DMAx DMAx Instance
1015 * @param Channel This parameter can be one of the following values:
1016 * @arg @ref LL_DMA_CHANNEL_1
1017 * @arg @ref LL_DMA_CHANNEL_2
1018 * @arg @ref LL_DMA_CHANNEL_3
1019 * @arg @ref LL_DMA_CHANNEL_4
1020 * @arg @ref LL_DMA_CHANNEL_5
1021 * @arg @ref LL_DMA_CHANNEL_6
1022 * @arg @ref LL_DMA_CHANNEL_7
1023 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1024 */
1025 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1026 {
1027 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1028 }
1029
1030 /**
1031 * @brief Get Peripheral address.
1032 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1033 * @rmtoll CPAR PA LL_DMA_GetPeriphAddress
1034 * @param DMAx DMAx Instance
1035 * @param Channel This parameter can be one of the following values:
1036 * @arg @ref LL_DMA_CHANNEL_1
1037 * @arg @ref LL_DMA_CHANNEL_2
1038 * @arg @ref LL_DMA_CHANNEL_3
1039 * @arg @ref LL_DMA_CHANNEL_4
1040 * @arg @ref LL_DMA_CHANNEL_5
1041 * @arg @ref LL_DMA_CHANNEL_6
1042 * @arg @ref LL_DMA_CHANNEL_7
1043 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1044 */
1045 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1046 {
1047 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1048 }
1049
1050 /**
1051 * @brief Set the Memory to Memory Source address.
1052 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1053 * @note This API must not be called when the DMA channel is enabled.
1054 * @rmtoll CPAR PA LL_DMA_SetM2MSrcAddress
1055 * @param DMAx DMAx Instance
1056 * @param Channel This parameter can be one of the following values:
1057 * @arg @ref LL_DMA_CHANNEL_1
1058 * @arg @ref LL_DMA_CHANNEL_2
1059 * @arg @ref LL_DMA_CHANNEL_3
1060 * @arg @ref LL_DMA_CHANNEL_4
1061 * @arg @ref LL_DMA_CHANNEL_5
1062 * @arg @ref LL_DMA_CHANNEL_6
1063 * @arg @ref LL_DMA_CHANNEL_7
1064 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1065 * @retval None
1066 */
1067 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1068 {
1069 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR, MemoryAddress);
1070 }
1071
1072 /**
1073 * @brief Set the Memory to Memory Destination address.
1074 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1075 * @note This API must not be called when the DMA channel is enabled.
1076 * @rmtoll CMAR MA LL_DMA_SetM2MDstAddress
1077 * @param DMAx DMAx Instance
1078 * @param Channel This parameter can be one of the following values:
1079 * @arg @ref LL_DMA_CHANNEL_1
1080 * @arg @ref LL_DMA_CHANNEL_2
1081 * @arg @ref LL_DMA_CHANNEL_3
1082 * @arg @ref LL_DMA_CHANNEL_4
1083 * @arg @ref LL_DMA_CHANNEL_5
1084 * @arg @ref LL_DMA_CHANNEL_6
1085 * @arg @ref LL_DMA_CHANNEL_7
1086 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1087 * @retval None
1088 */
1089 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel, uint32_t MemoryAddress)
1090 {
1091 WRITE_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR, MemoryAddress);
1092 }
1093
1094 /**
1095 * @brief Get the Memory to Memory Source address.
1096 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1097 * @rmtoll CPAR PA LL_DMA_GetM2MSrcAddress
1098 * @param DMAx DMAx Instance
1099 * @param Channel This parameter can be one of the following values:
1100 * @arg @ref LL_DMA_CHANNEL_1
1101 * @arg @ref LL_DMA_CHANNEL_2
1102 * @arg @ref LL_DMA_CHANNEL_3
1103 * @arg @ref LL_DMA_CHANNEL_4
1104 * @arg @ref LL_DMA_CHANNEL_5
1105 * @arg @ref LL_DMA_CHANNEL_6
1106 * @arg @ref LL_DMA_CHANNEL_7
1107 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1108 */
1109 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1110 {
1111 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CPAR));
1112 }
1113
1114 /**
1115 * @brief Get the Memory to Memory Destination address.
1116 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1117 * @rmtoll CMAR MA LL_DMA_GetM2MDstAddress
1118 * @param DMAx DMAx Instance
1119 * @param Channel This parameter can be one of the following values:
1120 * @arg @ref LL_DMA_CHANNEL_1
1121 * @arg @ref LL_DMA_CHANNEL_2
1122 * @arg @ref LL_DMA_CHANNEL_3
1123 * @arg @ref LL_DMA_CHANNEL_4
1124 * @arg @ref LL_DMA_CHANNEL_5
1125 * @arg @ref LL_DMA_CHANNEL_6
1126 * @arg @ref LL_DMA_CHANNEL_7
1127 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1128 */
1129 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Channel)
1130 {
1131 return (READ_REG(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CMAR));
1132 }
1133
1134 /**
1135 * @}
1136 */
1137
1138 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1139 * @{
1140 */
1141
1142 /**
1143 * @brief Get Channel 1 global interrupt flag.
1144 * @rmtoll ISR GIF1 LL_DMA_IsActiveFlag_GI1
1145 * @param DMAx DMAx Instance
1146 * @retval State of bit (1 or 0).
1147 */
1148 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI1(DMA_TypeDef *DMAx)
1149 {
1150 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF1) == (DMA_ISR_GIF1));
1151 }
1152
1153 /**
1154 * @brief Get Channel 2 global interrupt flag.
1155 * @rmtoll ISR GIF2 LL_DMA_IsActiveFlag_GI2
1156 * @param DMAx DMAx Instance
1157 * @retval State of bit (1 or 0).
1158 */
1159 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI2(DMA_TypeDef *DMAx)
1160 {
1161 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF2) == (DMA_ISR_GIF2));
1162 }
1163
1164 /**
1165 * @brief Get Channel 3 global interrupt flag.
1166 * @rmtoll ISR GIF3 LL_DMA_IsActiveFlag_GI3
1167 * @param DMAx DMAx Instance
1168 * @retval State of bit (1 or 0).
1169 */
1170 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI3(DMA_TypeDef *DMAx)
1171 {
1172 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF3) == (DMA_ISR_GIF3));
1173 }
1174
1175 /**
1176 * @brief Get Channel 4 global interrupt flag.
1177 * @rmtoll ISR GIF4 LL_DMA_IsActiveFlag_GI4
1178 * @param DMAx DMAx Instance
1179 * @retval State of bit (1 or 0).
1180 */
1181 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI4(DMA_TypeDef *DMAx)
1182 {
1183 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF4) == (DMA_ISR_GIF4));
1184 }
1185
1186 /**
1187 * @brief Get Channel 5 global interrupt flag.
1188 * @rmtoll ISR GIF5 LL_DMA_IsActiveFlag_GI5
1189 * @param DMAx DMAx Instance
1190 * @retval State of bit (1 or 0).
1191 */
1192 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI5(DMA_TypeDef *DMAx)
1193 {
1194 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF5) == (DMA_ISR_GIF5));
1195 }
1196
1197 /**
1198 * @brief Get Channel 6 global interrupt flag.
1199 * @rmtoll ISR GIF6 LL_DMA_IsActiveFlag_GI6
1200 * @param DMAx DMAx Instance
1201 * @retval State of bit (1 or 0).
1202 */
1203 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI6(DMA_TypeDef *DMAx)
1204 {
1205 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF6) == (DMA_ISR_GIF6));
1206 }
1207
1208 /**
1209 * @brief Get Channel 7 global interrupt flag.
1210 * @rmtoll ISR GIF7 LL_DMA_IsActiveFlag_GI7
1211 * @param DMAx DMAx Instance
1212 * @retval State of bit (1 or 0).
1213 */
1214 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_GI7(DMA_TypeDef *DMAx)
1215 {
1216 return (READ_BIT(DMAx->ISR, DMA_ISR_GIF7) == (DMA_ISR_GIF7));
1217 }
1218
1219 /**
1220 * @brief Get Channel 1 transfer complete flag.
1221 * @rmtoll ISR TCIF1 LL_DMA_IsActiveFlag_TC1
1222 * @param DMAx DMAx Instance
1223 * @retval State of bit (1 or 0).
1224 */
1225 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1226 {
1227 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF1) == (DMA_ISR_TCIF1));
1228 }
1229
1230 /**
1231 * @brief Get Channel 2 transfer complete flag.
1232 * @rmtoll ISR TCIF2 LL_DMA_IsActiveFlag_TC2
1233 * @param DMAx DMAx Instance
1234 * @retval State of bit (1 or 0).
1235 */
1236 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1237 {
1238 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF2) == (DMA_ISR_TCIF2));
1239 }
1240
1241 /**
1242 * @brief Get Channel 3 transfer complete flag.
1243 * @rmtoll ISR TCIF3 LL_DMA_IsActiveFlag_TC3
1244 * @param DMAx DMAx Instance
1245 * @retval State of bit (1 or 0).
1246 */
1247 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1248 {
1249 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF3) == (DMA_ISR_TCIF3));
1250 }
1251
1252 /**
1253 * @brief Get Channel 4 transfer complete flag.
1254 * @rmtoll ISR TCIF4 LL_DMA_IsActiveFlag_TC4
1255 * @param DMAx DMAx Instance
1256 * @retval State of bit (1 or 0).
1257 */
1258 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1259 {
1260 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF4) == (DMA_ISR_TCIF4));
1261 }
1262
1263 /**
1264 * @brief Get Channel 5 transfer complete flag.
1265 * @rmtoll ISR TCIF5 LL_DMA_IsActiveFlag_TC5
1266 * @param DMAx DMAx Instance
1267 * @retval State of bit (1 or 0).
1268 */
1269 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1270 {
1271 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF5) == (DMA_ISR_TCIF5));
1272 }
1273
1274 /**
1275 * @brief Get Channel 6 transfer complete flag.
1276 * @rmtoll ISR TCIF6 LL_DMA_IsActiveFlag_TC6
1277 * @param DMAx DMAx Instance
1278 * @retval State of bit (1 or 0).
1279 */
1280 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1281 {
1282 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF6) == (DMA_ISR_TCIF6));
1283 }
1284
1285 /**
1286 * @brief Get Channel 7 transfer complete flag.
1287 * @rmtoll ISR TCIF7 LL_DMA_IsActiveFlag_TC7
1288 * @param DMAx DMAx Instance
1289 * @retval State of bit (1 or 0).
1290 */
1291 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1292 {
1293 return (READ_BIT(DMAx->ISR, DMA_ISR_TCIF7) == (DMA_ISR_TCIF7));
1294 }
1295
1296 /**
1297 * @brief Get Channel 1 half transfer flag.
1298 * @rmtoll ISR HTIF1 LL_DMA_IsActiveFlag_HT1
1299 * @param DMAx DMAx Instance
1300 * @retval State of bit (1 or 0).
1301 */
1302 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1303 {
1304 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF1) == (DMA_ISR_HTIF1));
1305 }
1306
1307 /**
1308 * @brief Get Channel 2 half transfer flag.
1309 * @rmtoll ISR HTIF2 LL_DMA_IsActiveFlag_HT2
1310 * @param DMAx DMAx Instance
1311 * @retval State of bit (1 or 0).
1312 */
1313 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1314 {
1315 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF2) == (DMA_ISR_HTIF2));
1316 }
1317
1318 /**
1319 * @brief Get Channel 3 half transfer flag.
1320 * @rmtoll ISR HTIF3 LL_DMA_IsActiveFlag_HT3
1321 * @param DMAx DMAx Instance
1322 * @retval State of bit (1 or 0).
1323 */
1324 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1325 {
1326 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF3) == (DMA_ISR_HTIF3));
1327 }
1328
1329 /**
1330 * @brief Get Channel 4 half transfer flag.
1331 * @rmtoll ISR HTIF4 LL_DMA_IsActiveFlag_HT4
1332 * @param DMAx DMAx Instance
1333 * @retval State of bit (1 or 0).
1334 */
1335 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1336 {
1337 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF4) == (DMA_ISR_HTIF4));
1338 }
1339
1340 /**
1341 * @brief Get Channel 5 half transfer flag.
1342 * @rmtoll ISR HTIF5 LL_DMA_IsActiveFlag_HT5
1343 * @param DMAx DMAx Instance
1344 * @retval State of bit (1 or 0).
1345 */
1346 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1347 {
1348 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF5) == (DMA_ISR_HTIF5));
1349 }
1350
1351 /**
1352 * @brief Get Channel 6 half transfer flag.
1353 * @rmtoll ISR HTIF6 LL_DMA_IsActiveFlag_HT6
1354 * @param DMAx DMAx Instance
1355 * @retval State of bit (1 or 0).
1356 */
1357 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1358 {
1359 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF6) == (DMA_ISR_HTIF6));
1360 }
1361
1362 /**
1363 * @brief Get Channel 7 half transfer flag.
1364 * @rmtoll ISR HTIF7 LL_DMA_IsActiveFlag_HT7
1365 * @param DMAx DMAx Instance
1366 * @retval State of bit (1 or 0).
1367 */
1368 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1369 {
1370 return (READ_BIT(DMAx->ISR, DMA_ISR_HTIF7) == (DMA_ISR_HTIF7));
1371 }
1372
1373 /**
1374 * @brief Get Channel 1 transfer error flag.
1375 * @rmtoll ISR TEIF1 LL_DMA_IsActiveFlag_TE1
1376 * @param DMAx DMAx Instance
1377 * @retval State of bit (1 or 0).
1378 */
1379 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1380 {
1381 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF1) == (DMA_ISR_TEIF1));
1382 }
1383
1384 /**
1385 * @brief Get Channel 2 transfer error flag.
1386 * @rmtoll ISR TEIF2 LL_DMA_IsActiveFlag_TE2
1387 * @param DMAx DMAx Instance
1388 * @retval State of bit (1 or 0).
1389 */
1390 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1391 {
1392 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF2) == (DMA_ISR_TEIF2));
1393 }
1394
1395 /**
1396 * @brief Get Channel 3 transfer error flag.
1397 * @rmtoll ISR TEIF3 LL_DMA_IsActiveFlag_TE3
1398 * @param DMAx DMAx Instance
1399 * @retval State of bit (1 or 0).
1400 */
1401 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1402 {
1403 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF3) == (DMA_ISR_TEIF3));
1404 }
1405
1406 /**
1407 * @brief Get Channel 4 transfer error flag.
1408 * @rmtoll ISR TEIF4 LL_DMA_IsActiveFlag_TE4
1409 * @param DMAx DMAx Instance
1410 * @retval State of bit (1 or 0).
1411 */
1412 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1413 {
1414 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF4) == (DMA_ISR_TEIF4));
1415 }
1416
1417 /**
1418 * @brief Get Channel 5 transfer error flag.
1419 * @rmtoll ISR TEIF5 LL_DMA_IsActiveFlag_TE5
1420 * @param DMAx DMAx Instance
1421 * @retval State of bit (1 or 0).
1422 */
1423 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1424 {
1425 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF5) == (DMA_ISR_TEIF5));
1426 }
1427
1428 /**
1429 * @brief Get Channel 6 transfer error flag.
1430 * @rmtoll ISR TEIF6 LL_DMA_IsActiveFlag_TE6
1431 * @param DMAx DMAx Instance
1432 * @retval State of bit (1 or 0).
1433 */
1434 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1435 {
1436 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF6) == (DMA_ISR_TEIF6));
1437 }
1438
1439 /**
1440 * @brief Get Channel 7 transfer error flag.
1441 * @rmtoll ISR TEIF7 LL_DMA_IsActiveFlag_TE7
1442 * @param DMAx DMAx Instance
1443 * @retval State of bit (1 or 0).
1444 */
1445 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1446 {
1447 return (READ_BIT(DMAx->ISR, DMA_ISR_TEIF7) == (DMA_ISR_TEIF7));
1448 }
1449
1450 /**
1451 * @brief Clear Channel 1 global interrupt flag.
1452 * @rmtoll IFCR CGIF1 LL_DMA_ClearFlag_GI1
1453 * @param DMAx DMAx Instance
1454 * @retval None
1455 */
1456 __STATIC_INLINE void LL_DMA_ClearFlag_GI1(DMA_TypeDef *DMAx)
1457 {
1458 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF1);
1459 }
1460
1461 /**
1462 * @brief Clear Channel 2 global interrupt flag.
1463 * @rmtoll IFCR CGIF2 LL_DMA_ClearFlag_GI2
1464 * @param DMAx DMAx Instance
1465 * @retval None
1466 */
1467 __STATIC_INLINE void LL_DMA_ClearFlag_GI2(DMA_TypeDef *DMAx)
1468 {
1469 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF2);
1470 }
1471
1472 /**
1473 * @brief Clear Channel 3 global interrupt flag.
1474 * @rmtoll IFCR CGIF3 LL_DMA_ClearFlag_GI3
1475 * @param DMAx DMAx Instance
1476 * @retval None
1477 */
1478 __STATIC_INLINE void LL_DMA_ClearFlag_GI3(DMA_TypeDef *DMAx)
1479 {
1480 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF3);
1481 }
1482
1483 /**
1484 * @brief Clear Channel 4 global interrupt flag.
1485 * @rmtoll IFCR CGIF4 LL_DMA_ClearFlag_GI4
1486 * @param DMAx DMAx Instance
1487 * @retval None
1488 */
1489 __STATIC_INLINE void LL_DMA_ClearFlag_GI4(DMA_TypeDef *DMAx)
1490 {
1491 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF4);
1492 }
1493
1494 /**
1495 * @brief Clear Channel 5 global interrupt flag.
1496 * @rmtoll IFCR CGIF5 LL_DMA_ClearFlag_GI5
1497 * @param DMAx DMAx Instance
1498 * @retval None
1499 */
1500 __STATIC_INLINE void LL_DMA_ClearFlag_GI5(DMA_TypeDef *DMAx)
1501 {
1502 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF5);
1503 }
1504
1505 /**
1506 * @brief Clear Channel 6 global interrupt flag.
1507 * @rmtoll IFCR CGIF6 LL_DMA_ClearFlag_GI6
1508 * @param DMAx DMAx Instance
1509 * @retval None
1510 */
1511 __STATIC_INLINE void LL_DMA_ClearFlag_GI6(DMA_TypeDef *DMAx)
1512 {
1513 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF6);
1514 }
1515
1516 /**
1517 * @brief Clear Channel 7 global interrupt flag.
1518 * @rmtoll IFCR CGIF7 LL_DMA_ClearFlag_GI7
1519 * @param DMAx DMAx Instance
1520 * @retval None
1521 */
1522 __STATIC_INLINE void LL_DMA_ClearFlag_GI7(DMA_TypeDef *DMAx)
1523 {
1524 WRITE_REG(DMAx->IFCR, DMA_IFCR_CGIF7);
1525 }
1526
1527 /**
1528 * @brief Clear Channel 1 transfer complete flag.
1529 * @rmtoll IFCR CTCIF1 LL_DMA_ClearFlag_TC1
1530 * @param DMAx DMAx Instance
1531 * @retval None
1532 */
1533 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
1534 {
1535 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF1);
1536 }
1537
1538 /**
1539 * @brief Clear Channel 2 transfer complete flag.
1540 * @rmtoll IFCR CTCIF2 LL_DMA_ClearFlag_TC2
1541 * @param DMAx DMAx Instance
1542 * @retval None
1543 */
1544 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
1545 {
1546 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF2);
1547 }
1548
1549 /**
1550 * @brief Clear Channel 3 transfer complete flag.
1551 * @rmtoll IFCR CTCIF3 LL_DMA_ClearFlag_TC3
1552 * @param DMAx DMAx Instance
1553 * @retval None
1554 */
1555 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
1556 {
1557 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF3);
1558 }
1559
1560 /**
1561 * @brief Clear Channel 4 transfer complete flag.
1562 * @rmtoll IFCR CTCIF4 LL_DMA_ClearFlag_TC4
1563 * @param DMAx DMAx Instance
1564 * @retval None
1565 */
1566 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
1567 {
1568 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF4);
1569 }
1570
1571 /**
1572 * @brief Clear Channel 5 transfer complete flag.
1573 * @rmtoll IFCR CTCIF5 LL_DMA_ClearFlag_TC5
1574 * @param DMAx DMAx Instance
1575 * @retval None
1576 */
1577 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
1578 {
1579 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF5);
1580 }
1581
1582 /**
1583 * @brief Clear Channel 6 transfer complete flag.
1584 * @rmtoll IFCR CTCIF6 LL_DMA_ClearFlag_TC6
1585 * @param DMAx DMAx Instance
1586 * @retval None
1587 */
1588 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
1589 {
1590 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF6);
1591 }
1592
1593 /**
1594 * @brief Clear Channel 7 transfer complete flag.
1595 * @rmtoll IFCR CTCIF7 LL_DMA_ClearFlag_TC7
1596 * @param DMAx DMAx Instance
1597 * @retval None
1598 */
1599 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
1600 {
1601 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTCIF7);
1602 }
1603
1604 /**
1605 * @brief Clear Channel 1 half transfer flag.
1606 * @rmtoll IFCR CHTIF1 LL_DMA_ClearFlag_HT1
1607 * @param DMAx DMAx Instance
1608 * @retval None
1609 */
1610 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
1611 {
1612 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF1);
1613 }
1614
1615 /**
1616 * @brief Clear Channel 2 half transfer flag.
1617 * @rmtoll IFCR CHTIF2 LL_DMA_ClearFlag_HT2
1618 * @param DMAx DMAx Instance
1619 * @retval None
1620 */
1621 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
1622 {
1623 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF2);
1624 }
1625
1626 /**
1627 * @brief Clear Channel 3 half transfer flag.
1628 * @rmtoll IFCR CHTIF3 LL_DMA_ClearFlag_HT3
1629 * @param DMAx DMAx Instance
1630 * @retval None
1631 */
1632 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
1633 {
1634 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF3);
1635 }
1636
1637 /**
1638 * @brief Clear Channel 4 half transfer flag.
1639 * @rmtoll IFCR CHTIF4 LL_DMA_ClearFlag_HT4
1640 * @param DMAx DMAx Instance
1641 * @retval None
1642 */
1643 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
1644 {
1645 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF4);
1646 }
1647
1648 /**
1649 * @brief Clear Channel 5 half transfer flag.
1650 * @rmtoll IFCR CHTIF5 LL_DMA_ClearFlag_HT5
1651 * @param DMAx DMAx Instance
1652 * @retval None
1653 */
1654 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
1655 {
1656 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF5);
1657 }
1658
1659 /**
1660 * @brief Clear Channel 6 half transfer flag.
1661 * @rmtoll IFCR CHTIF6 LL_DMA_ClearFlag_HT6
1662 * @param DMAx DMAx Instance
1663 * @retval None
1664 */
1665 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
1666 {
1667 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF6);
1668 }
1669
1670 /**
1671 * @brief Clear Channel 7 half transfer flag.
1672 * @rmtoll IFCR CHTIF7 LL_DMA_ClearFlag_HT7
1673 * @param DMAx DMAx Instance
1674 * @retval None
1675 */
1676 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
1677 {
1678 WRITE_REG(DMAx->IFCR, DMA_IFCR_CHTIF7);
1679 }
1680
1681 /**
1682 * @brief Clear Channel 1 transfer error flag.
1683 * @rmtoll IFCR CTEIF1 LL_DMA_ClearFlag_TE1
1684 * @param DMAx DMAx Instance
1685 * @retval None
1686 */
1687 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
1688 {
1689 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF1);
1690 }
1691
1692 /**
1693 * @brief Clear Channel 2 transfer error flag.
1694 * @rmtoll IFCR CTEIF2 LL_DMA_ClearFlag_TE2
1695 * @param DMAx DMAx Instance
1696 * @retval None
1697 */
1698 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
1699 {
1700 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF2);
1701 }
1702
1703 /**
1704 * @brief Clear Channel 3 transfer error flag.
1705 * @rmtoll IFCR CTEIF3 LL_DMA_ClearFlag_TE3
1706 * @param DMAx DMAx Instance
1707 * @retval None
1708 */
1709 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
1710 {
1711 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF3);
1712 }
1713
1714 /**
1715 * @brief Clear Channel 4 transfer error flag.
1716 * @rmtoll IFCR CTEIF4 LL_DMA_ClearFlag_TE4
1717 * @param DMAx DMAx Instance
1718 * @retval None
1719 */
1720 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
1721 {
1722 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF4);
1723 }
1724
1725 /**
1726 * @brief Clear Channel 5 transfer error flag.
1727 * @rmtoll IFCR CTEIF5 LL_DMA_ClearFlag_TE5
1728 * @param DMAx DMAx Instance
1729 * @retval None
1730 */
1731 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
1732 {
1733 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF5);
1734 }
1735
1736 /**
1737 * @brief Clear Channel 6 transfer error flag.
1738 * @rmtoll IFCR CTEIF6 LL_DMA_ClearFlag_TE6
1739 * @param DMAx DMAx Instance
1740 * @retval None
1741 */
1742 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
1743 {
1744 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF6);
1745 }
1746
1747 /**
1748 * @brief Clear Channel 7 transfer error flag.
1749 * @rmtoll IFCR CTEIF7 LL_DMA_ClearFlag_TE7
1750 * @param DMAx DMAx Instance
1751 * @retval None
1752 */
1753 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
1754 {
1755 WRITE_REG(DMAx->IFCR, DMA_IFCR_CTEIF7);
1756 }
1757
1758 /**
1759 * @}
1760 */
1761
1762 /** @defgroup DMA_LL_EF_IT_Management IT_Management
1763 * @{
1764 */
1765
1766 /**
1767 * @brief Enable Transfer complete interrupt.
1768 * @rmtoll CCR TCIE LL_DMA_EnableIT_TC
1769 * @param DMAx DMAx Instance
1770 * @param Channel This parameter can be one of the following values:
1771 * @arg @ref LL_DMA_CHANNEL_1
1772 * @arg @ref LL_DMA_CHANNEL_2
1773 * @arg @ref LL_DMA_CHANNEL_3
1774 * @arg @ref LL_DMA_CHANNEL_4
1775 * @arg @ref LL_DMA_CHANNEL_5
1776 * @arg @ref LL_DMA_CHANNEL_6
1777 * @arg @ref LL_DMA_CHANNEL_7
1778 * @retval None
1779 */
1780 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1781 {
1782 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1783 }
1784
1785 /**
1786 * @brief Enable Half transfer interrupt.
1787 * @rmtoll CCR HTIE LL_DMA_EnableIT_HT
1788 * @param DMAx DMAx Instance
1789 * @param Channel This parameter can be one of the following values:
1790 * @arg @ref LL_DMA_CHANNEL_1
1791 * @arg @ref LL_DMA_CHANNEL_2
1792 * @arg @ref LL_DMA_CHANNEL_3
1793 * @arg @ref LL_DMA_CHANNEL_4
1794 * @arg @ref LL_DMA_CHANNEL_5
1795 * @arg @ref LL_DMA_CHANNEL_6
1796 * @arg @ref LL_DMA_CHANNEL_7
1797 * @retval None
1798 */
1799 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1800 {
1801 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1802 }
1803
1804 /**
1805 * @brief Enable Transfer error interrupt.
1806 * @rmtoll CCR TEIE LL_DMA_EnableIT_TE
1807 * @param DMAx DMAx Instance
1808 * @param Channel This parameter can be one of the following values:
1809 * @arg @ref LL_DMA_CHANNEL_1
1810 * @arg @ref LL_DMA_CHANNEL_2
1811 * @arg @ref LL_DMA_CHANNEL_3
1812 * @arg @ref LL_DMA_CHANNEL_4
1813 * @arg @ref LL_DMA_CHANNEL_5
1814 * @arg @ref LL_DMA_CHANNEL_6
1815 * @arg @ref LL_DMA_CHANNEL_7
1816 * @retval None
1817 */
1818 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1819 {
1820 SET_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1821 }
1822
1823 /**
1824 * @brief Disable Transfer complete interrupt.
1825 * @rmtoll CCR TCIE LL_DMA_DisableIT_TC
1826 * @param DMAx DMAx Instance
1827 * @param Channel This parameter can be one of the following values:
1828 * @arg @ref LL_DMA_CHANNEL_1
1829 * @arg @ref LL_DMA_CHANNEL_2
1830 * @arg @ref LL_DMA_CHANNEL_3
1831 * @arg @ref LL_DMA_CHANNEL_4
1832 * @arg @ref LL_DMA_CHANNEL_5
1833 * @arg @ref LL_DMA_CHANNEL_6
1834 * @arg @ref LL_DMA_CHANNEL_7
1835 * @retval None
1836 */
1837 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1838 {
1839 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TCIE);
1840 }
1841
1842 /**
1843 * @brief Disable Half transfer interrupt.
1844 * @rmtoll CCR HTIE LL_DMA_DisableIT_HT
1845 * @param DMAx DMAx Instance
1846 * @param Channel This parameter can be one of the following values:
1847 * @arg @ref LL_DMA_CHANNEL_1
1848 * @arg @ref LL_DMA_CHANNEL_2
1849 * @arg @ref LL_DMA_CHANNEL_3
1850 * @arg @ref LL_DMA_CHANNEL_4
1851 * @arg @ref LL_DMA_CHANNEL_5
1852 * @arg @ref LL_DMA_CHANNEL_6
1853 * @arg @ref LL_DMA_CHANNEL_7
1854 * @retval None
1855 */
1856 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1857 {
1858 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_HTIE);
1859 }
1860
1861 /**
1862 * @brief Disable Transfer error interrupt.
1863 * @rmtoll CCR TEIE LL_DMA_DisableIT_TE
1864 * @param DMAx DMAx Instance
1865 * @param Channel This parameter can be one of the following values:
1866 * @arg @ref LL_DMA_CHANNEL_1
1867 * @arg @ref LL_DMA_CHANNEL_2
1868 * @arg @ref LL_DMA_CHANNEL_3
1869 * @arg @ref LL_DMA_CHANNEL_4
1870 * @arg @ref LL_DMA_CHANNEL_5
1871 * @arg @ref LL_DMA_CHANNEL_6
1872 * @arg @ref LL_DMA_CHANNEL_7
1873 * @retval None
1874 */
1875 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1876 {
1877 CLEAR_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR, DMA_CCR_TEIE);
1878 }
1879
1880 /**
1881 * @brief Check if Transfer complete Interrupt is enabled.
1882 * @rmtoll CCR TCIE LL_DMA_IsEnabledIT_TC
1883 * @param DMAx DMAx Instance
1884 * @param Channel This parameter can be one of the following values:
1885 * @arg @ref LL_DMA_CHANNEL_1
1886 * @arg @ref LL_DMA_CHANNEL_2
1887 * @arg @ref LL_DMA_CHANNEL_3
1888 * @arg @ref LL_DMA_CHANNEL_4
1889 * @arg @ref LL_DMA_CHANNEL_5
1890 * @arg @ref LL_DMA_CHANNEL_6
1891 * @arg @ref LL_DMA_CHANNEL_7
1892 * @retval State of bit (1 or 0).
1893 */
1894 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Channel)
1895 {
1896 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1897 DMA_CCR_TCIE) == (DMA_CCR_TCIE));
1898 }
1899
1900 /**
1901 * @brief Check if Half transfer Interrupt is enabled.
1902 * @rmtoll CCR HTIE LL_DMA_IsEnabledIT_HT
1903 * @param DMAx DMAx Instance
1904 * @param Channel This parameter can be one of the following values:
1905 * @arg @ref LL_DMA_CHANNEL_1
1906 * @arg @ref LL_DMA_CHANNEL_2
1907 * @arg @ref LL_DMA_CHANNEL_3
1908 * @arg @ref LL_DMA_CHANNEL_4
1909 * @arg @ref LL_DMA_CHANNEL_5
1910 * @arg @ref LL_DMA_CHANNEL_6
1911 * @arg @ref LL_DMA_CHANNEL_7
1912 * @retval State of bit (1 or 0).
1913 */
1914 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Channel)
1915 {
1916 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1917 DMA_CCR_HTIE) == (DMA_CCR_HTIE));
1918 }
1919
1920 /**
1921 * @brief Check if Transfer error Interrupt is enabled.
1922 * @rmtoll CCR TEIE LL_DMA_IsEnabledIT_TE
1923 * @param DMAx DMAx Instance
1924 * @param Channel This parameter can be one of the following values:
1925 * @arg @ref LL_DMA_CHANNEL_1
1926 * @arg @ref LL_DMA_CHANNEL_2
1927 * @arg @ref LL_DMA_CHANNEL_3
1928 * @arg @ref LL_DMA_CHANNEL_4
1929 * @arg @ref LL_DMA_CHANNEL_5
1930 * @arg @ref LL_DMA_CHANNEL_6
1931 * @arg @ref LL_DMA_CHANNEL_7
1932 * @retval State of bit (1 or 0).
1933 */
1934 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Channel)
1935 {
1936 return (READ_BIT(((DMA_Channel_TypeDef *)((uint32_t)((uint32_t)DMAx + CHANNEL_OFFSET_TAB[Channel - 1U])))->CCR,
1937 DMA_CCR_TEIE) == (DMA_CCR_TEIE));
1938 }
1939
1940 /**
1941 * @}
1942 */
1943
1944 #if defined(USE_FULL_LL_DRIVER)
1945 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
1946 * @{
1947 */
1948
1949 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Channel, LL_DMA_InitTypeDef *DMA_InitStruct);
1950 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Channel);
1951 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
1952
1953 /**
1954 * @}
1955 */
1956 #endif /* USE_FULL_LL_DRIVER */
1957
1958 /**
1959 * @}
1960 */
1961
1962 /**
1963 * @}
1964 */
1965
1966 #endif /* DMA1 || DMA2 */
1967
1968 /**
1969 * @}
1970 */
1971
1972 #ifdef __cplusplus
1973 }
1974 #endif
1975
1976 #endif /* __STM32F1xx_LL_DMA_H */
1977
1978 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/