lib/main/STM32F1/Drivers/STM32F1xx_HAL_Driver/Inc/stm32f1xx_ll_cortex.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f1xx_ll_cortex.h
   4   * @author  MCD Application Team
   5   * @version V1.1.1
   6   * @date    12-May-2017
   7   * @brief   Header file of CORTEX LL module.
   8   @verbatim
   9   ==============================================================================
  10                      ##### How to use this driver #####
  11   ==============================================================================
  12     [..]
  13     The LL CORTEX driver contains a set of generic APIs that can be
  14     used by user:
  15       (+) SYSTICK configuration used by @ref LL_mDelay and @ref LL_Init1msTick
  16           functions
  17       (+) Low power mode configuration (SCB register of Cortex-MCU)
  18       (+) MPU API to configure and enable regions
  19           (MPU services provided only on some devices)
  20       (+) API to access to MCU info (CPUID register)
  21       (+) API to enable fault handler (SHCSR accesses)
  22
  23   @endverbatim
  24   ******************************************************************************
  25   * @attention
  26   *
  27   * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
  28   *
  29   * Redistribution and use in source and binary forms, with or without modification,
  30   * are permitted provided that the following conditions are met:
  31   *   1. Redistributions of source code must retain the above copyright notice,
  32   *      this list of conditions and the following disclaimer.
  33   *   2. Redistributions in binary form must reproduce the above copyright notice,
  34   *      this list of conditions and the following disclaimer in the documentation
  35   *      and/or other materials provided with the distribution.
  36   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  37   *      may be used to endorse or promote products derived from this software
  38   *      without specific prior written permission.
  39   *
  40   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  41   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  42   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  43   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  44   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  45   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  46   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  47   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  48   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  49   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  50   *
  51   ******************************************************************************
  52   */
  53
  54 /* Define to prevent recursive inclusion -------------------------------------*/
  55 #ifndef __STM32F1xx_LL_CORTEX_H
  56 #define __STM32F1xx_LL_CORTEX_H
  57
  58 #ifdef __cplusplus
  59 extern "C" {
  60 #endif
  61
  62 /* Includes ------------------------------------------------------------------*/
  63 #include "stm32f1xx.h"
  64
  65 /** @addtogroup STM32F1xx_LL_Driver
  66   * @{
  67   */
  68
  69 /** @defgroup CORTEX_LL CORTEX
  70   * @{
  71   */
  72
  73 /* Private types -------------------------------------------------------------*/
  74 /* Private variables ---------------------------------------------------------*/
  75
  76 /* Private constants ---------------------------------------------------------*/
  77
  78 /* Private macros ------------------------------------------------------------*/
  79
  80 /* Exported types ------------------------------------------------------------*/
  81 /* Exported constants --------------------------------------------------------*/
  82 /** @defgroup CORTEX_LL_Exported_Constants CORTEX Exported Constants
  83   * @{
  84   */
  85
  86 /** @defgroup CORTEX_LL_EC_CLKSOURCE_HCLK SYSTICK Clock Source
  87   * @{
  88   */
  89 #define LL_SYSTICK_CLKSOURCE_HCLK_DIV8     0x00000000U                 /*!< AHB clock divided by 8 selected as SysTick clock source.*/
  90 #define LL_SYSTICK_CLKSOURCE_HCLK          SysTick_CTRL_CLKSOURCE_Msk  /*!< AHB clock selected as SysTick clock source. */
  91 /**
  92   * @}
  93   */
  94
  95 /** @defgroup CORTEX_LL_EC_FAULT Handler Fault type
  96   * @{
  97   */
  98 #define LL_HANDLER_FAULT_USG               SCB_SHCSR_USGFAULTENA_Msk              /*!< Usage fault */
  99 #define LL_HANDLER_FAULT_BUS               SCB_SHCSR_BUSFAULTENA_Msk              /*!< Bus fault */
 100 #define LL_HANDLER_FAULT_MEM               SCB_SHCSR_MEMFAULTENA_Msk              /*!< Memory management fault */
 101 /**
 102   * @}
 103   */
 104
 105 #if __MPU_PRESENT
 106
 107 /** @defgroup CORTEX_LL_EC_CTRL_HFNMI_PRIVDEF MPU Control
 108   * @{
 109   */
 110 #define LL_MPU_CTRL_HFNMI_PRIVDEF_NONE     0x00000000U                                       /*!< Disable NMI and privileged SW access */
 111 #define LL_MPU_CTRL_HARDFAULT_NMI          MPU_CTRL_HFNMIENA_Msk                             /*!< Enables the operation of MPU during hard fault, NMI, and FAULTMASK handlers */
 112 #define LL_MPU_CTRL_PRIVILEGED_DEFAULT     MPU_CTRL_PRIVDEFENA_Msk                           /*!< Enable privileged software access to default memory map */
 113 #define LL_MPU_CTRL_HFNMI_PRIVDEF          (MPU_CTRL_HFNMIENA_Msk | MPU_CTRL_PRIVDEFENA_Msk) /*!< Enable NMI and privileged SW access */
 114 /**
 115   * @}
 116   */
 117
 118 /** @defgroup CORTEX_LL_EC_REGION MPU Region Number
 119   * @{
 120   */
 121 #define LL_MPU_REGION_NUMBER0              0x00U /*!< REGION Number 0 */
 122 #define LL_MPU_REGION_NUMBER1              0x01U /*!< REGION Number 1 */
 123 #define LL_MPU_REGION_NUMBER2              0x02U /*!< REGION Number 2 */
 124 #define LL_MPU_REGION_NUMBER3              0x03U /*!< REGION Number 3 */
 125 #define LL_MPU_REGION_NUMBER4              0x04U /*!< REGION Number 4 */
 126 #define LL_MPU_REGION_NUMBER5              0x05U /*!< REGION Number 5 */
 127 #define LL_MPU_REGION_NUMBER6              0x06U /*!< REGION Number 6 */
 128 #define LL_MPU_REGION_NUMBER7              0x07U /*!< REGION Number 7 */
 129 /**
 130   * @}
 131   */
 132
 133 /** @defgroup CORTEX_LL_EC_REGION_SIZE MPU Region Size
 134   * @{
 135   */
 136 #define LL_MPU_REGION_SIZE_32B             (0x04U << MPU_RASR_SIZE_Pos) /*!< 32B Size of the MPU protection region */
 137 #define LL_MPU_REGION_SIZE_64B             (0x05U << MPU_RASR_SIZE_Pos) /*!< 64B Size of the MPU protection region */
 138 #define LL_MPU_REGION_SIZE_128B            (0x06U << MPU_RASR_SIZE_Pos) /*!< 128B Size of the MPU protection region */
 139 #define LL_MPU_REGION_SIZE_256B            (0x07U << MPU_RASR_SIZE_Pos) /*!< 256B Size of the MPU protection region */
 140 #define LL_MPU_REGION_SIZE_512B            (0x08U << MPU_RASR_SIZE_Pos) /*!< 512B Size of the MPU protection region */
 141 #define LL_MPU_REGION_SIZE_1KB             (0x09U << MPU_RASR_SIZE_Pos) /*!< 1KB Size of the MPU protection region */
 142 #define LL_MPU_REGION_SIZE_2KB             (0x0AU << MPU_RASR_SIZE_Pos) /*!< 2KB Size of the MPU protection region */
 143 #define LL_MPU_REGION_SIZE_4KB             (0x0BU << MPU_RASR_SIZE_Pos) /*!< 4KB Size of the MPU protection region */
 144 #define LL_MPU_REGION_SIZE_8KB             (0x0CU << MPU_RASR_SIZE_Pos) /*!< 8KB Size of the MPU protection region */
 145 #define LL_MPU_REGION_SIZE_16KB            (0x0DU << MPU_RASR_SIZE_Pos) /*!< 16KB Size of the MPU protection region */
 146 #define LL_MPU_REGION_SIZE_32KB            (0x0EU << MPU_RASR_SIZE_Pos) /*!< 32KB Size of the MPU protection region */
 147 #define LL_MPU_REGION_SIZE_64KB            (0x0FU << MPU_RASR_SIZE_Pos) /*!< 64KB Size of the MPU protection region */
 148 #define LL_MPU_REGION_SIZE_128KB           (0x10U << MPU_RASR_SIZE_Pos) /*!< 128KB Size of the MPU protection region */
 149 #define LL_MPU_REGION_SIZE_256KB           (0x11U << MPU_RASR_SIZE_Pos) /*!< 256KB Size of the MPU protection region */
 150 #define LL_MPU_REGION_SIZE_512KB           (0x12U << MPU_RASR_SIZE_Pos) /*!< 512KB Size of the MPU protection region */
 151 #define LL_MPU_REGION_SIZE_1MB             (0x13U << MPU_RASR_SIZE_Pos) /*!< 1MB Size of the MPU protection region */
 152 #define LL_MPU_REGION_SIZE_2MB             (0x14U << MPU_RASR_SIZE_Pos) /*!< 2MB Size of the MPU protection region */
 153 #define LL_MPU_REGION_SIZE_4MB             (0x15U << MPU_RASR_SIZE_Pos) /*!< 4MB Size of the MPU protection region */
 154 #define LL_MPU_REGION_SIZE_8MB             (0x16U << MPU_RASR_SIZE_Pos) /*!< 8MB Size of the MPU protection region */
 155 #define LL_MPU_REGION_SIZE_16MB            (0x17U << MPU_RASR_SIZE_Pos) /*!< 16MB Size of the MPU protection region */
 156 #define LL_MPU_REGION_SIZE_32MB            (0x18U << MPU_RASR_SIZE_Pos) /*!< 32MB Size of the MPU protection region */
 157 #define LL_MPU_REGION_SIZE_64MB            (0x19U << MPU_RASR_SIZE_Pos) /*!< 64MB Size of the MPU protection region */
 158 #define LL_MPU_REGION_SIZE_128MB           (0x1AU << MPU_RASR_SIZE_Pos) /*!< 128MB Size of the MPU protection region */
 159 #define LL_MPU_REGION_SIZE_256MB           (0x1BU << MPU_RASR_SIZE_Pos) /*!< 256MB Size of the MPU protection region */
 160 #define LL_MPU_REGION_SIZE_512MB           (0x1CU << MPU_RASR_SIZE_Pos) /*!< 512MB Size of the MPU protection region */
 161 #define LL_MPU_REGION_SIZE_1GB             (0x1DU << MPU_RASR_SIZE_Pos) /*!< 1GB Size of the MPU protection region */
 162 #define LL_MPU_REGION_SIZE_2GB             (0x1EU << MPU_RASR_SIZE_Pos) /*!< 2GB Size of the MPU protection region */
 163 #define LL_MPU_REGION_SIZE_4GB             (0x1FU << MPU_RASR_SIZE_Pos) /*!< 4GB Size of the MPU protection region */
 164 /**
 165   * @}
 166   */
 167
 168 /** @defgroup CORTEX_LL_EC_REGION_PRIVILEDGES MPU Region Privileges
 169   * @{
 170   */
 171 #define LL_MPU_REGION_NO_ACCESS            (0x00U << MPU_RASR_AP_Pos) /*!< No access*/
 172 #define LL_MPU_REGION_PRIV_RW              (0x01U << MPU_RASR_AP_Pos) /*!< RW privileged (privileged access only)*/
 173 #define LL_MPU_REGION_PRIV_RW_URO          (0x02U << MPU_RASR_AP_Pos) /*!< RW privileged - RO user (Write in a user program generates a fault) */
 174 #define LL_MPU_REGION_FULL_ACCESS          (0x03U << MPU_RASR_AP_Pos) /*!< RW privileged & user (Full access) */
 175 #define LL_MPU_REGION_PRIV_RO              (0x05U << MPU_RASR_AP_Pos) /*!< RO privileged (privileged read only)*/
 176 #define LL_MPU_REGION_PRIV_RO_URO          (0x06U << MPU_RASR_AP_Pos) /*!< RO privileged & user (read only) */
 177 /**
 178   * @}
 179   */
 180
 181 /** @defgroup CORTEX_LL_EC_TEX MPU TEX Level
 182   * @{
 183   */
 184 #define LL_MPU_TEX_LEVEL0                  (0x00U << MPU_RASR_TEX_Pos) /*!< b000 for TEX bits */
 185 #define LL_MPU_TEX_LEVEL1                  (0x01U << MPU_RASR_TEX_Pos) /*!< b001 for TEX bits */
 186 #define LL_MPU_TEX_LEVEL2                  (0x02U << MPU_RASR_TEX_Pos) /*!< b010 for TEX bits */
 187 #define LL_MPU_TEX_LEVEL4                  (0x04U << MPU_RASR_TEX_Pos) /*!< b100 for TEX bits */
 188 /**
 189   * @}
 190   */
 191
 192 /** @defgroup CORTEX_LL_EC_INSTRUCTION_ACCESS MPU Instruction Access
 193   * @{
 194   */
 195 #define LL_MPU_INSTRUCTION_ACCESS_ENABLE   0x00U            /*!< Instruction fetches enabled */
 196 #define LL_MPU_INSTRUCTION_ACCESS_DISABLE  MPU_RASR_XN_Msk  /*!< Instruction fetches disabled*/
 197 /**
 198   * @}
 199   */
 200
 201 /** @defgroup CORTEX_LL_EC_SHAREABLE_ACCESS MPU Shareable Access
 202   * @{
 203   */
 204 #define LL_MPU_ACCESS_SHAREABLE            MPU_RASR_S_Msk   /*!< Shareable memory attribute */
 205 #define LL_MPU_ACCESS_NOT_SHAREABLE        0x00U            /*!< Not Shareable memory attribute */
 206 /**
 207   * @}
 208   */
 209
 210 /** @defgroup CORTEX_LL_EC_CACHEABLE_ACCESS MPU Cacheable Access
 211   * @{
 212   */
 213 #define LL_MPU_ACCESS_CACHEABLE            MPU_RASR_C_Msk   /*!< Cacheable memory attribute */
 214 #define LL_MPU_ACCESS_NOT_CACHEABLE        0x00U            /*!< Not Cacheable memory attribute */
 215 /**
 216   * @}
 217   */
 218
 219 /** @defgroup CORTEX_LL_EC_BUFFERABLE_ACCESS MPU Bufferable Access
 220   * @{
 221   */
 222 #define LL_MPU_ACCESS_BUFFERABLE           MPU_RASR_B_Msk   /*!< Bufferable memory attribute */
 223 #define LL_MPU_ACCESS_NOT_BUFFERABLE       0x00U            /*!< Not Bufferable memory attribute */
 224 /**
 225   * @}
 226   */
 227 #endif /* __MPU_PRESENT */
 228 /**
 229   * @}
 230   */
 231
 232 /* Exported macro ------------------------------------------------------------*/
 233
 234 /* Exported functions --------------------------------------------------------*/
 235 /** @defgroup CORTEX_LL_Exported_Functions CORTEX Exported Functions
 236   * @{
 237   */
 238
 239 /** @defgroup CORTEX_LL_EF_SYSTICK SYSTICK
 240   * @{
 241   */
 242
 243 /**
 244   * @brief  This function checks if the Systick counter flag is active or not.
 245   * @note   It can be used in timeout function on application side.
 246   * @rmtoll STK_CTRL     COUNTFLAG     LL_SYSTICK_IsActiveCounterFlag
 247   * @retval State of bit (1 or 0).
 248   */
 249 __STATIC_INLINE uint32_t LL_SYSTICK_IsActiveCounterFlag(void)
 250 {
 251   return ((SysTick->CTRL & SysTick_CTRL_COUNTFLAG_Msk) == (SysTick_CTRL_COUNTFLAG_Msk));
 252 }
 253
 254 /**
 255   * @brief  Configures the SysTick clock source
 256   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_SetClkSource
 257   * @param  Source This parameter can be one of the following values:
 258   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
 259   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
 260   * @retval None
 261   */
 262 __STATIC_INLINE void LL_SYSTICK_SetClkSource(uint32_t Source)
 263 {
 264   if (Source == LL_SYSTICK_CLKSOURCE_HCLK)
 265   {
 266     SET_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
 267   }
 268   else
 269   {
 270     CLEAR_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
 271   }
 272 }
 273
 274 /**
 275   * @brief  Get the SysTick clock source
 276   * @rmtoll STK_CTRL     CLKSOURCE     LL_SYSTICK_GetClkSource
 277   * @retval Returned value can be one of the following values:
 278   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK_DIV8
 279   *         @arg @ref LL_SYSTICK_CLKSOURCE_HCLK
 280   */
 281 __STATIC_INLINE uint32_t LL_SYSTICK_GetClkSource(void)
 282 {
 283   return READ_BIT(SysTick->CTRL, LL_SYSTICK_CLKSOURCE_HCLK);
 284 }
 285
 286 /**
 287   * @brief  Enable SysTick exception request
 288   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_EnableIT
 289   * @retval None
 290   */
 291 __STATIC_INLINE void LL_SYSTICK_EnableIT(void)
 292 {
 293   SET_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
 294 }
 295
 296 /**
 297   * @brief  Disable SysTick exception request
 298   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_DisableIT
 299   * @retval None
 300   */
 301 __STATIC_INLINE void LL_SYSTICK_DisableIT(void)
 302 {
 303   CLEAR_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk);
 304 }
 305
 306 /**
 307   * @brief  Checks if the SYSTICK interrupt is enabled or disabled.
 308   * @rmtoll STK_CTRL     TICKINT       LL_SYSTICK_IsEnabledIT
 309   * @retval State of bit (1 or 0).
 310   */
 311 __STATIC_INLINE uint32_t LL_SYSTICK_IsEnabledIT(void)
 312 {
 313   return (READ_BIT(SysTick->CTRL, SysTick_CTRL_TICKINT_Msk) == (SysTick_CTRL_TICKINT_Msk));
 314 }
 315
 316 /**
 317   * @}
 318   */
 319
 320 /** @defgroup CORTEX_LL_EF_LOW_POWER_MODE LOW POWER MODE
 321   * @{
 322   */
 323
 324 /**
 325   * @brief  Processor uses sleep as its low power mode
 326   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableSleep
 327   * @retval None
 328   */
 329 __STATIC_INLINE void LL_LPM_EnableSleep(void)
 330 {
 331   /* Clear SLEEPDEEP bit of Cortex System Control Register */
 332   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 333 }
 334
 335 /**
 336   * @brief  Processor uses deep sleep as its low power mode
 337   * @rmtoll SCB_SCR      SLEEPDEEP     LL_LPM_EnableDeepSleep
 338   * @retval None
 339   */
 340 __STATIC_INLINE void LL_LPM_EnableDeepSleep(void)
 341 {
 342   /* Set SLEEPDEEP bit of Cortex System Control Register */
 343   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
 344 }
 345
 346 /**
 347   * @brief  Configures sleep-on-exit when returning from Handler mode to Thread mode.
 348   * @note   Setting this bit to 1 enables an interrupt-driven application to avoid returning to an
 349   *         empty main application.
 350   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_EnableSleepOnExit
 351   * @retval None
 352   */
 353 __STATIC_INLINE void LL_LPM_EnableSleepOnExit(void)
 354 {
 355   /* Set SLEEPONEXIT bit of Cortex System Control Register */
 356   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 357 }
 358
 359 /**
 360   * @brief  Do not sleep when returning to Thread mode.
 361   * @rmtoll SCB_SCR      SLEEPONEXIT   LL_LPM_DisableSleepOnExit
 362   * @retval None
 363   */
 364 __STATIC_INLINE void LL_LPM_DisableSleepOnExit(void)
 365 {
 366   /* Clear SLEEPONEXIT bit of Cortex System Control Register */
 367   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPONEXIT_Msk));
 368 }
 369
 370 /**
 371   * @brief  Enabled events and all interrupts, including disabled interrupts, can wakeup the
 372   *         processor.
 373   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_EnableEventOnPend
 374   * @retval None
 375   */
 376 __STATIC_INLINE void LL_LPM_EnableEventOnPend(void)
 377 {
 378   /* Set SEVEONPEND bit of Cortex System Control Register */
 379   SET_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 380 }
 381
 382 /**
 383   * @brief  Only enabled interrupts or events can wakeup the processor, disabled interrupts are
 384   *         excluded
 385   * @rmtoll SCB_SCR      SEVEONPEND    LL_LPM_DisableEventOnPend
 386   * @retval None
 387   */
 388 __STATIC_INLINE void LL_LPM_DisableEventOnPend(void)
 389 {
 390   /* Clear SEVEONPEND bit of Cortex System Control Register */
 391   CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SEVONPEND_Msk));
 392 }
 393
 394 /**
 395   * @}
 396   */
 397
 398 /** @defgroup CORTEX_LL_EF_HANDLER HANDLER
 399   * @{
 400   */
 401
 402 /**
 403   * @brief  Enable a fault in System handler control register (SHCSR)
 404   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_EnableFault
 405   * @param  Fault This parameter can be a combination of the following values:
 406   *         @arg @ref LL_HANDLER_FAULT_USG
 407   *         @arg @ref LL_HANDLER_FAULT_BUS
 408   *         @arg @ref LL_HANDLER_FAULT_MEM
 409   * @retval None
 410   */
 411 __STATIC_INLINE void LL_HANDLER_EnableFault(uint32_t Fault)
 412 {
 413   /* Enable the system handler fault */
 414   SET_BIT(SCB->SHCSR, Fault);
 415 }
 416
 417 /**
 418   * @brief  Disable a fault in System handler control register (SHCSR)
 419   * @rmtoll SCB_SHCSR    MEMFAULTENA   LL_HANDLER_DisableFault
 420   * @param  Fault This parameter can be a combination of the following values:
 421   *         @arg @ref LL_HANDLER_FAULT_USG
 422   *         @arg @ref LL_HANDLER_FAULT_BUS
 423   *         @arg @ref LL_HANDLER_FAULT_MEM
 424   * @retval None
 425   */
 426 __STATIC_INLINE void LL_HANDLER_DisableFault(uint32_t Fault)
 427 {
 428   /* Disable the system handler fault */
 429   CLEAR_BIT(SCB->SHCSR, Fault);
 430 }
 431
 432 /**
 433   * @}
 434   */
 435
 436 /** @defgroup CORTEX_LL_EF_MCU_INFO MCU INFO
 437   * @{
 438   */
 439
 440 /**
 441   * @brief  Get Implementer code
 442   * @rmtoll SCB_CPUID    IMPLEMENTER   LL_CPUID_GetImplementer
 443   * @retval Value should be equal to 0x41 for ARM
 444   */
 445 __STATIC_INLINE uint32_t LL_CPUID_GetImplementer(void)
 446 {
 447   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_IMPLEMENTER_Msk) >> SCB_CPUID_IMPLEMENTER_Pos);
 448 }
 449
 450 /**
 451   * @brief  Get Variant number (The r value in the rnpn product revision identifier)
 452   * @rmtoll SCB_CPUID    VARIANT       LL_CPUID_GetVariant
 453   * @retval Value between 0 and 255 (0x1: revision 1, 0x2: revision 2)
 454   */
 455 __STATIC_INLINE uint32_t LL_CPUID_GetVariant(void)
 456 {
 457   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_VARIANT_Msk) >> SCB_CPUID_VARIANT_Pos);
 458 }
 459
 460 /**
 461   * @brief  Get Constant number
 462   * @rmtoll SCB_CPUID    ARCHITECTURE  LL_CPUID_GetConstant
 463   * @retval Value should be equal to 0xF for Cortex-M3 devices
 464   */
 465 __STATIC_INLINE uint32_t LL_CPUID_GetConstant(void)
 466 {
 467   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_ARCHITECTURE_Msk) >> SCB_CPUID_ARCHITECTURE_Pos);
 468 }
 469
 470 /**
 471   * @brief  Get Part number
 472   * @rmtoll SCB_CPUID    PARTNO        LL_CPUID_GetParNo
 473   * @retval Value should be equal to 0xC23 for Cortex-M3
 474   */
 475 __STATIC_INLINE uint32_t LL_CPUID_GetParNo(void)
 476 {
 477   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_PARTNO_Msk) >> SCB_CPUID_PARTNO_Pos);
 478 }
 479
 480 /**
 481   * @brief  Get Revision number (The p value in the rnpn product revision identifier, indicates patch release)
 482   * @rmtoll SCB_CPUID    REVISION      LL_CPUID_GetRevision
 483   * @retval Value between 0 and 255 (0x0: patch 0, 0x1: patch 1)
 484   */
 485 __STATIC_INLINE uint32_t LL_CPUID_GetRevision(void)
 486 {
 487   return (uint32_t)(READ_BIT(SCB->CPUID, SCB_CPUID_REVISION_Msk) >> SCB_CPUID_REVISION_Pos);
 488 }
 489
 490 /**
 491   * @}
 492   */
 493
 494 #if __MPU_PRESENT
 495 /** @defgroup CORTEX_LL_EF_MPU MPU
 496   * @{
 497   */
 498
 499 /**
 500   * @brief  Enable MPU with input options
 501   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Enable
 502   * @param  Options This parameter can be one of the following values:
 503   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF_NONE
 504   *         @arg @ref LL_MPU_CTRL_HARDFAULT_NMI
 505   *         @arg @ref LL_MPU_CTRL_PRIVILEGED_DEFAULT
 506   *         @arg @ref LL_MPU_CTRL_HFNMI_PRIVDEF
 507   * @retval None
 508   */
 509 __STATIC_INLINE void LL_MPU_Enable(uint32_t Options)
 510 {
 511   /* Enable the MPU*/
 512   WRITE_REG(MPU->CTRL, (MPU_CTRL_ENABLE_Msk | Options));
 513   /* Ensure MPU settings take effects */
 514   __DSB();
 515   /* Sequence instruction fetches using update settings */
 516   __ISB();
 517 }
 518
 519 /**
 520   * @brief  Disable MPU
 521   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_Disable
 522   * @retval None
 523   */
 524 __STATIC_INLINE void LL_MPU_Disable(void)
 525 {
 526   /* Make sure outstanding transfers are done */
 527   __DMB();
 528   /* Disable MPU*/
 529   WRITE_REG(MPU->CTRL, 0U);
 530 }
 531
 532 /**
 533   * @brief  Check if MPU is enabled or not
 534   * @rmtoll MPU_CTRL     ENABLE        LL_MPU_IsEnabled
 535   * @retval State of bit (1 or 0).
 536   */
 537 __STATIC_INLINE uint32_t LL_MPU_IsEnabled(void)
 538 {
 539   return (READ_BIT(MPU->CTRL, MPU_CTRL_ENABLE_Msk) == (MPU_CTRL_ENABLE_Msk));
 540 }
 541
 542 /**
 543   * @brief  Enable a MPU region
 544   * @rmtoll MPU_RASR     ENABLE        LL_MPU_EnableRegion
 545   * @param  Region This parameter can be one of the following values:
 546   *         @arg @ref LL_MPU_REGION_NUMBER0
 547   *         @arg @ref LL_MPU_REGION_NUMBER1
 548   *         @arg @ref LL_MPU_REGION_NUMBER2
 549   *         @arg @ref LL_MPU_REGION_NUMBER3
 550   *         @arg @ref LL_MPU_REGION_NUMBER4
 551   *         @arg @ref LL_MPU_REGION_NUMBER5
 552   *         @arg @ref LL_MPU_REGION_NUMBER6
 553   *         @arg @ref LL_MPU_REGION_NUMBER7
 554   * @retval None
 555   */
 556 __STATIC_INLINE void LL_MPU_EnableRegion(uint32_t Region)
 557 {
 558   /* Set Region number */
 559   WRITE_REG(MPU->RNR, Region);
 560   /* Enable the MPU region */
 561   SET_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 562 }
 563
 564 /**
 565   * @brief  Configure and enable a region
 566   * @rmtoll MPU_RNR      REGION        LL_MPU_ConfigRegion\n
 567   *         MPU_RBAR     REGION        LL_MPU_ConfigRegion\n
 568   *         MPU_RBAR     ADDR          LL_MPU_ConfigRegion\n
 569   *         MPU_RASR     XN            LL_MPU_ConfigRegion\n
 570   *         MPU_RASR     AP            LL_MPU_ConfigRegion\n
 571   *         MPU_RASR     S             LL_MPU_ConfigRegion\n
 572   *         MPU_RASR     C             LL_MPU_ConfigRegion\n
 573   *         MPU_RASR     B             LL_MPU_ConfigRegion\n
 574   *         MPU_RASR     SIZE          LL_MPU_ConfigRegion
 575   * @param  Region This parameter can be one of the following values:
 576   *         @arg @ref LL_MPU_REGION_NUMBER0
 577   *         @arg @ref LL_MPU_REGION_NUMBER1
 578   *         @arg @ref LL_MPU_REGION_NUMBER2
 579   *         @arg @ref LL_MPU_REGION_NUMBER3
 580   *         @arg @ref LL_MPU_REGION_NUMBER4
 581   *         @arg @ref LL_MPU_REGION_NUMBER5
 582   *         @arg @ref LL_MPU_REGION_NUMBER6
 583   *         @arg @ref LL_MPU_REGION_NUMBER7
 584   * @param  Address Value of region base address
 585   * @param  SubRegionDisable Sub-region disable value between Min_Data = 0x00 and Max_Data = 0xFF
 586   * @param  Attributes This parameter can be a combination of the following values:
 587   *         @arg @ref LL_MPU_REGION_SIZE_32B or @ref LL_MPU_REGION_SIZE_64B or @ref LL_MPU_REGION_SIZE_128B or @ref LL_MPU_REGION_SIZE_256B or @ref LL_MPU_REGION_SIZE_512B
 588   *           or @ref LL_MPU_REGION_SIZE_1KB or @ref LL_MPU_REGION_SIZE_2KB or @ref LL_MPU_REGION_SIZE_4KB or @ref LL_MPU_REGION_SIZE_8KB or @ref LL_MPU_REGION_SIZE_16KB
 589   *           or @ref LL_MPU_REGION_SIZE_32KB or @ref LL_MPU_REGION_SIZE_64KB or @ref LL_MPU_REGION_SIZE_128KB or @ref LL_MPU_REGION_SIZE_256KB or @ref LL_MPU_REGION_SIZE_512KB
 590   *           or @ref LL_MPU_REGION_SIZE_1MB or @ref LL_MPU_REGION_SIZE_2MB or @ref LL_MPU_REGION_SIZE_4MB or @ref LL_MPU_REGION_SIZE_8MB or @ref LL_MPU_REGION_SIZE_16MB
 591   *           or @ref LL_MPU_REGION_SIZE_32MB or @ref LL_MPU_REGION_SIZE_64MB or @ref LL_MPU_REGION_SIZE_128MB or @ref LL_MPU_REGION_SIZE_256MB or @ref LL_MPU_REGION_SIZE_512MB
 592   *           or @ref LL_MPU_REGION_SIZE_1GB or @ref LL_MPU_REGION_SIZE_2GB or @ref LL_MPU_REGION_SIZE_4GB
 593   *         @arg @ref LL_MPU_REGION_NO_ACCESS or @ref LL_MPU_REGION_PRIV_RW or @ref LL_MPU_REGION_PRIV_RW_URO or @ref LL_MPU_REGION_FULL_ACCESS
 594   *           or @ref LL_MPU_REGION_PRIV_RO or @ref LL_MPU_REGION_PRIV_RO_URO
 595   *         @arg @ref LL_MPU_TEX_LEVEL0 or @ref LL_MPU_TEX_LEVEL1 or @ref LL_MPU_TEX_LEVEL2 or @ref LL_MPU_TEX_LEVEL4
 596   *         @arg @ref LL_MPU_INSTRUCTION_ACCESS_ENABLE or  @ref LL_MPU_INSTRUCTION_ACCESS_DISABLE
 597   *         @arg @ref LL_MPU_ACCESS_SHAREABLE or @ref LL_MPU_ACCESS_NOT_SHAREABLE
 598   *         @arg @ref LL_MPU_ACCESS_CACHEABLE or @ref LL_MPU_ACCESS_NOT_CACHEABLE
 599   *         @arg @ref LL_MPU_ACCESS_BUFFERABLE or @ref LL_MPU_ACCESS_NOT_BUFFERABLE
 600   * @retval None
 601   */
 602 __STATIC_INLINE void LL_MPU_ConfigRegion(uint32_t Region, uint32_t SubRegionDisable, uint32_t Address, uint32_t Attributes)
 603 {
 604   /* Set Region number */
 605   WRITE_REG(MPU->RNR, Region);
 606   /* Set base address */
 607   WRITE_REG(MPU->RBAR, (Address & 0xFFFFFFE0U));
 608   /* Configure MPU */
 609   WRITE_REG(MPU->RASR, (MPU_RASR_ENABLE_Msk | Attributes | SubRegionDisable << MPU_RASR_SRD_Pos));
 610 }
 611
 612 /**
 613   * @brief  Disable a region
 614   * @rmtoll MPU_RNR      REGION        LL_MPU_DisableRegion\n
 615   *         MPU_RASR     ENABLE        LL_MPU_DisableRegion
 616   * @param  Region This parameter can be one of the following values:
 617   *         @arg @ref LL_MPU_REGION_NUMBER0
 618   *         @arg @ref LL_MPU_REGION_NUMBER1
 619   *         @arg @ref LL_MPU_REGION_NUMBER2
 620   *         @arg @ref LL_MPU_REGION_NUMBER3
 621   *         @arg @ref LL_MPU_REGION_NUMBER4
 622   *         @arg @ref LL_MPU_REGION_NUMBER5
 623   *         @arg @ref LL_MPU_REGION_NUMBER6
 624   *         @arg @ref LL_MPU_REGION_NUMBER7
 625   * @retval None
 626   */
 627 __STATIC_INLINE void LL_MPU_DisableRegion(uint32_t Region)
 628 {
 629   /* Set Region number */
 630   WRITE_REG(MPU->RNR, Region);
 631   /* Disable the MPU region */
 632   CLEAR_BIT(MPU->RASR, MPU_RASR_ENABLE_Msk);
 633 }
 634
 635 /**
 636   * @}
 637   */
 638
 639 #endif /* __MPU_PRESENT */
 640 /**
 641   * @}
 642   */
 643
 644 /**
 645   * @}
 646   */
 647
 648 /**
 649   * @}
 650   */
 651
 652 #ifdef __cplusplus
 653 }
 654 #endif
 655
 656 #endif /* __STM32F1xx_LL_CORTEX_H */
 657
 658 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/