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F1 and F3 HAL / LL libraries
[betaflight.git] / lib / main / STM32F1 / Drivers / STM32F1xx_HAL_Driver / Inc / stm32f1xx_hal_rcc.h
blobf098d9caa0d5a435cd7f8cf98b734b3f8ca23faa
1 /**
2 ******************************************************************************
3 * @file stm32f1xx_hal_rcc.h
4 * @author MCD Application Team
5 * @version V1.1.1
6 * @date 12-May-2017
7 * @brief Header file of RCC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F1xx_HAL_RCC_H
40 #define __STM32F1xx_HAL_RCC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f1xx_hal_def.h"
48
49 /** @addtogroup STM32F1xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup RCC
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58
59 /** @defgroup RCC_Exported_Types RCC Exported Types
60 * @{
61 */
62
63 /**
64 * @brief RCC PLL configuration structure definition
65 */
66 typedef struct
67 {
68 uint32_t PLLState; /*!< PLLState: The new state of the PLL.
69 This parameter can be a value of @ref RCC_PLL_Config */
70
71 uint32_t PLLSource; /*!< PLLSource: PLL entry clock source.
72 This parameter must be a value of @ref RCC_PLL_Clock_Source */
73
74 uint32_t PLLMUL; /*!< PLLMUL: Multiplication factor for PLL VCO input clock
75 This parameter must be a value of @ref RCCEx_PLL_Multiplication_Factor */
76 } RCC_PLLInitTypeDef;
77
78 /**
79 * @brief RCC System, AHB and APB busses clock configuration structure definition
80 */
81 typedef struct
82 {
83 uint32_t ClockType; /*!< The clock to be configured.
84 This parameter can be a value of @ref RCC_System_Clock_Type */
85
86 uint32_t SYSCLKSource; /*!< The clock source (SYSCLKS) used as system clock.
87 This parameter can be a value of @ref RCC_System_Clock_Source */
88
89 uint32_t AHBCLKDivider; /*!< The AHB clock (HCLK) divider. This clock is derived from the system clock (SYSCLK).
90 This parameter can be a value of @ref RCC_AHB_Clock_Source */
91
92 uint32_t APB1CLKDivider; /*!< The APB1 clock (PCLK1) divider. This clock is derived from the AHB clock (HCLK).
93 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
94
95 uint32_t APB2CLKDivider; /*!< The APB2 clock (PCLK2) divider. This clock is derived from the AHB clock (HCLK).
96 This parameter can be a value of @ref RCC_APB1_APB2_Clock_Source */
97 } RCC_ClkInitTypeDef;
98
99 /**
100 * @}
101 */
102
103 /* Exported constants --------------------------------------------------------*/
104 /** @defgroup RCC_Exported_Constants RCC Exported Constants
105 * @{
106 */
107
108 /** @defgroup RCC_PLL_Clock_Source PLL Clock Source
109 * @{
110 */
111
112 #define RCC_PLLSOURCE_HSI_DIV2 0x00000000U /*!< HSI clock divided by 2 selected as PLL entry clock source */
113 #define RCC_PLLSOURCE_HSE RCC_CFGR_PLLSRC /*!< HSE clock selected as PLL entry clock source */
114
115 /**
116 * @}
117 */
118
119 /** @defgroup RCC_Oscillator_Type Oscillator Type
120 * @{
121 */
122 #define RCC_OSCILLATORTYPE_NONE 0x00000000U
123 #define RCC_OSCILLATORTYPE_HSE 0x00000001U
124 #define RCC_OSCILLATORTYPE_HSI 0x00000002U
125 #define RCC_OSCILLATORTYPE_LSE 0x00000004U
126 #define RCC_OSCILLATORTYPE_LSI 0x00000008U
127 /**
128 * @}
129 */
130
131 /** @defgroup RCC_HSE_Config HSE Config
132 * @{
133 */
134 #define RCC_HSE_OFF 0x00000000U /*!< HSE clock deactivation */
135 #define RCC_HSE_ON RCC_CR_HSEON /*!< HSE clock activation */
136 #define RCC_HSE_BYPASS ((uint32_t)(RCC_CR_HSEBYP | RCC_CR_HSEON)) /*!< External clock source for HSE clock */
137 /**
138 * @}
139 */
140
141 /** @defgroup RCC_LSE_Config LSE Config
142 * @{
143 */
144 #define RCC_LSE_OFF 0x00000000U /*!< LSE clock deactivation */
145 #define RCC_LSE_ON RCC_BDCR_LSEON /*!< LSE clock activation */
146 #define RCC_LSE_BYPASS ((uint32_t)(RCC_BDCR_LSEBYP | RCC_BDCR_LSEON)) /*!< External clock source for LSE clock */
147
148 /**
149 * @}
150 */
151
152 /** @defgroup RCC_HSI_Config HSI Config
153 * @{
154 */
155 #define RCC_HSI_OFF 0x00000000U /*!< HSI clock deactivation */
156 #define RCC_HSI_ON RCC_CR_HSION /*!< HSI clock activation */
157
158 #define RCC_HSICALIBRATION_DEFAULT 0x10U /* Default HSI calibration trimming value */
159
160 /**
161 * @}
162 */
163
164 /** @defgroup RCC_LSI_Config LSI Config
165 * @{
166 */
167 #define RCC_LSI_OFF 0x00000000U /*!< LSI clock deactivation */
168 #define RCC_LSI_ON RCC_CSR_LSION /*!< LSI clock activation */
169
170 /**
171 * @}
172 */
173
174 /** @defgroup RCC_PLL_Config PLL Config
175 * @{
176 */
177 #define RCC_PLL_NONE 0x00000000U /*!< PLL is not configured */
178 #define RCC_PLL_OFF 0x00000001U /*!< PLL deactivation */
179 #define RCC_PLL_ON 0x00000002U /*!< PLL activation */
180
181 /**
182 * @}
183 */
184
185 /** @defgroup RCC_System_Clock_Type System Clock Type
186 * @{
187 */
188 #define RCC_CLOCKTYPE_SYSCLK 0x00000001U /*!< SYSCLK to configure */
189 #define RCC_CLOCKTYPE_HCLK 0x00000002U /*!< HCLK to configure */
190 #define RCC_CLOCKTYPE_PCLK1 0x00000004U /*!< PCLK1 to configure */
191 #define RCC_CLOCKTYPE_PCLK2 0x00000008U /*!< PCLK2 to configure */
192
193 /**
194 * @}
195 */
196
197 /** @defgroup RCC_System_Clock_Source System Clock Source
198 * @{
199 */
200 #define RCC_SYSCLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selected as system clock */
201 #define RCC_SYSCLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selected as system clock */
202 #define RCC_SYSCLKSOURCE_PLLCLK RCC_CFGR_SW_PLL /*!< PLL selected as system clock */
203
204 /**
205 * @}
206 */
207
208 /** @defgroup RCC_System_Clock_Source_Status System Clock Source Status
209 * @{
210 */
211 #define RCC_SYSCLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
212 #define RCC_SYSCLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
213 #define RCC_SYSCLKSOURCE_STATUS_PLLCLK RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
214
215 /**
216 * @}
217 */
218
219 /** @defgroup RCC_AHB_Clock_Source AHB Clock Source
220 * @{
221 */
222 #define RCC_SYSCLK_DIV1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
223 #define RCC_SYSCLK_DIV2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
224 #define RCC_SYSCLK_DIV4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
225 #define RCC_SYSCLK_DIV8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
226 #define RCC_SYSCLK_DIV16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
227 #define RCC_SYSCLK_DIV64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
228 #define RCC_SYSCLK_DIV128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
229 #define RCC_SYSCLK_DIV256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
230 #define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
231
232 /**
233 * @}
234 */
235
236 /** @defgroup RCC_APB1_APB2_Clock_Source APB1 APB2 Clock Source
237 * @{
238 */
239 #define RCC_HCLK_DIV1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
240 #define RCC_HCLK_DIV2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
241 #define RCC_HCLK_DIV4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
242 #define RCC_HCLK_DIV8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
243 #define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
244
245 /**
246 * @}
247 */
248
249 /** @defgroup RCC_RTC_Clock_Source RTC Clock Source
250 * @{
251 */
252 #define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U /*!< No clock */
253 #define RCC_RTCCLKSOURCE_LSE RCC_BDCR_RTCSEL_LSE /*!< LSE oscillator clock used as RTC clock */
254 #define RCC_RTCCLKSOURCE_LSI RCC_BDCR_RTCSEL_LSI /*!< LSI oscillator clock used as RTC clock */
255 #define RCC_RTCCLKSOURCE_HSE_DIV128 RCC_BDCR_RTCSEL_HSE /*!< HSE oscillator clock divided by 128 used as RTC clock */
256 /**
257 * @}
258 */
259
260
261 /** @defgroup RCC_MCO_Index MCO Index
262 * @{
263 */
264 #define RCC_MCO1 0x00000000U
265 #define RCC_MCO RCC_MCO1 /*!< MCO1 to be compliant with other families with 2 MCOs*/
266
267 /**
268 * @}
269 */
270
271 /** @defgroup RCC_MCOx_Clock_Prescaler MCO Clock Prescaler
272 * @{
273 */
274 #define RCC_MCODIV_1 0x00000000U
275
276 /**
277 * @}
278 */
279
280 /** @defgroup RCC_Interrupt Interrupts
281 * @{
282 */
283 #define RCC_IT_LSIRDY ((uint8_t)RCC_CIR_LSIRDYF) /*!< LSI Ready Interrupt flag */
284 #define RCC_IT_LSERDY ((uint8_t)RCC_CIR_LSERDYF) /*!< LSE Ready Interrupt flag */
285 #define RCC_IT_HSIRDY ((uint8_t)RCC_CIR_HSIRDYF) /*!< HSI Ready Interrupt flag */
286 #define RCC_IT_HSERDY ((uint8_t)RCC_CIR_HSERDYF) /*!< HSE Ready Interrupt flag */
287 #define RCC_IT_PLLRDY ((uint8_t)RCC_CIR_PLLRDYF) /*!< PLL Ready Interrupt flag */
288 #define RCC_IT_CSS ((uint8_t)RCC_CIR_CSSF) /*!< Clock Security System Interrupt flag */
289 /**
290 * @}
291 */
292
293 /** @defgroup RCC_Flag Flags
294 * Elements values convention: XXXYYYYYb
295 * - YYYYY : Flag position in the register
296 * - XXX : Register index
297 * - 001: CR register
298 * - 010: BDCR register
299 * - 011: CSR register
300 * @{
301 */
302 /* Flags in the CR register */
303 #define RCC_FLAG_HSIRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSIRDY_Pos)) /*!< Internal High Speed clock ready flag */
304 #define RCC_FLAG_HSERDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_HSERDY_Pos)) /*!< External High Speed clock ready flag */
305 #define RCC_FLAG_PLLRDY ((uint8_t)((CR_REG_INDEX << 5U) | RCC_CR_PLLRDY_Pos)) /*!< PLL clock ready flag */
306
307 /* Flags in the CSR register */
308 #define RCC_FLAG_LSIRDY ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LSIRDY_Pos)) /*!< Internal Low Speed oscillator Ready */
309 #define RCC_FLAG_PINRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PINRSTF_Pos)) /*!< PIN reset flag */
310 #define RCC_FLAG_PORRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_PORRSTF_Pos)) /*!< POR/PDR reset flag */
311 #define RCC_FLAG_SFTRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_SFTRSTF_Pos)) /*!< Software Reset flag */
312 #define RCC_FLAG_IWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_IWDGRSTF_Pos)) /*!< Independent Watchdog reset flag */
313 #define RCC_FLAG_WWDGRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_WWDGRSTF_Pos)) /*!< Window watchdog reset flag */
314 #define RCC_FLAG_LPWRRST ((uint8_t)((CSR_REG_INDEX << 5U) | RCC_CSR_LPWRRSTF_Pos)) /*!< Low-Power reset flag */
315
316 /* Flags in the BDCR register */
317 #define RCC_FLAG_LSERDY ((uint8_t)((BDCR_REG_INDEX << 5U) | RCC_BDCR_LSERDY_Pos)) /*!< External Low Speed oscillator Ready */
318
319 /**
320 * @}
321 */
322
323 /**
324 * @}
325 */
326
327 /* Exported macro ------------------------------------------------------------*/
328
329 /** @defgroup RCC_Exported_Macros RCC Exported Macros
330 * @{
331 */
332
333 /** @defgroup RCC_Peripheral_Clock_Enable_Disable Peripheral Clock Enable Disable
334 * @brief Enable or disable the AHB1 peripheral clock.
335 * @note After reset, the peripheral clock (used for registers read/write access)
336 * is disabled and the application software has to enable this clock before
337 * using it.
338 * @{
339 */
340 #define __HAL_RCC_DMA1_CLK_ENABLE() do { \
341 __IO uint32_t tmpreg; \
342 SET_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
343 /* Delay after an RCC peripheral clock enabling */\
344 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_DMA1EN);\
345 UNUSED(tmpreg); \
346 } while(0U)
347
348 #define __HAL_RCC_SRAM_CLK_ENABLE() do { \
349 __IO uint32_t tmpreg; \
350 SET_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
351 /* Delay after an RCC peripheral clock enabling */\
352 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_SRAMEN);\
353 UNUSED(tmpreg); \
354 } while(0U)
355
356 #define __HAL_RCC_FLITF_CLK_ENABLE() do { \
357 __IO uint32_t tmpreg; \
358 SET_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
359 /* Delay after an RCC peripheral clock enabling */\
360 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_FLITFEN);\
361 UNUSED(tmpreg); \
362 } while(0U)
363
364 #define __HAL_RCC_CRC_CLK_ENABLE() do { \
365 __IO uint32_t tmpreg; \
366 SET_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
367 /* Delay after an RCC peripheral clock enabling */\
368 tmpreg = READ_BIT(RCC->AHBENR, RCC_AHBENR_CRCEN);\
369 UNUSED(tmpreg); \
370 } while(0U)
371
372 #define __HAL_RCC_DMA1_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_DMA1EN))
373 #define __HAL_RCC_SRAM_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_SRAMEN))
374 #define __HAL_RCC_FLITF_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_FLITFEN))
375 #define __HAL_RCC_CRC_CLK_DISABLE() (RCC->AHBENR &= ~(RCC_AHBENR_CRCEN))
376
377 /**
378 * @}
379 */
380
381 /** @defgroup RCC_AHB_Peripheral_Clock_Enable_Disable_Status AHB Peripheral Clock Enable Disable Status
382 * @brief Get the enable or disable status of the AHB peripheral clock.
383 * @note After reset, the peripheral clock (used for registers read/write access)
384 * is disabled and the application software has to enable this clock before
385 * using it.
386 * @{
387 */
388
389 #define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) != RESET)
390 #define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_DMA1EN)) == RESET)
391 #define __HAL_RCC_SRAM_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) != RESET)
392 #define __HAL_RCC_SRAM_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_SRAMEN)) == RESET)
393 #define __HAL_RCC_FLITF_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) != RESET)
394 #define __HAL_RCC_FLITF_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_FLITFEN)) == RESET)
395 #define __HAL_RCC_CRC_IS_CLK_ENABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) != RESET)
396 #define __HAL_RCC_CRC_IS_CLK_DISABLED() ((RCC->AHBENR & (RCC_AHBENR_CRCEN)) == RESET)
397
398 /**
399 * @}
400 */
401
402 /** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Clock Enable Disable
403 * @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
404 * @note After reset, the peripheral clock (used for registers read/write access)
405 * is disabled and the application software has to enable this clock before
406 * using it.
407 * @{
408 */
409 #define __HAL_RCC_TIM2_CLK_ENABLE() do { \
410 __IO uint32_t tmpreg; \
411 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
412 /* Delay after an RCC peripheral clock enabling */\
413 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM2EN);\
414 UNUSED(tmpreg); \
415 } while(0U)
416
417 #define __HAL_RCC_TIM3_CLK_ENABLE() do { \
418 __IO uint32_t tmpreg; \
419 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
420 /* Delay after an RCC peripheral clock enabling */\
421 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_TIM3EN);\
422 UNUSED(tmpreg); \
423 } while(0U)
424
425 #define __HAL_RCC_WWDG_CLK_ENABLE() do { \
426 __IO uint32_t tmpreg; \
427 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
428 /* Delay after an RCC peripheral clock enabling */\
429 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_WWDGEN);\
430 UNUSED(tmpreg); \
431 } while(0U)
432
433 #define __HAL_RCC_USART2_CLK_ENABLE() do { \
434 __IO uint32_t tmpreg; \
435 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
436 /* Delay after an RCC peripheral clock enabling */\
437 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_USART2EN);\
438 UNUSED(tmpreg); \
439 } while(0U)
440
441 #define __HAL_RCC_I2C1_CLK_ENABLE() do { \
442 __IO uint32_t tmpreg; \
443 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
444 /* Delay after an RCC peripheral clock enabling */\
445 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_I2C1EN);\
446 UNUSED(tmpreg); \
447 } while(0U)
448
449 #define __HAL_RCC_BKP_CLK_ENABLE() do { \
450 __IO uint32_t tmpreg; \
451 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
452 /* Delay after an RCC peripheral clock enabling */\
453 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_BKPEN);\
454 UNUSED(tmpreg); \
455 } while(0U)
456
457 #define __HAL_RCC_PWR_CLK_ENABLE() do { \
458 __IO uint32_t tmpreg; \
459 SET_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
460 /* Delay after an RCC peripheral clock enabling */\
461 tmpreg = READ_BIT(RCC->APB1ENR, RCC_APB1ENR_PWREN);\
462 UNUSED(tmpreg); \
463 } while(0U)
464
465 #define __HAL_RCC_TIM2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM2EN))
466 #define __HAL_RCC_TIM3_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_TIM3EN))
467 #define __HAL_RCC_WWDG_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_WWDGEN))
468 #define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
469 #define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
470
471 #define __HAL_RCC_BKP_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_BKPEN))
472 #define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
473
474 /**
475 * @}
476 */
477
478 /** @defgroup RCC_APB1_Peripheral_Clock_Enable_Disable_Status APB1 Peripheral Clock Enable Disable Status
479 * @brief Get the enable or disable status of the APB1 peripheral clock.
480 * @note After reset, the peripheral clock (used for registers read/write access)
481 * is disabled and the application software has to enable this clock before
482 * using it.
483 * @{
484 */
485
486 #define __HAL_RCC_TIM2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) != RESET)
487 #define __HAL_RCC_TIM2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM2EN)) == RESET)
488 #define __HAL_RCC_TIM3_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) != RESET)
489 #define __HAL_RCC_TIM3_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_TIM3EN)) == RESET)
490 #define __HAL_RCC_WWDG_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) != RESET)
491 #define __HAL_RCC_WWDG_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_WWDGEN)) == RESET)
492 #define __HAL_RCC_USART2_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) != RESET)
493 #define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
494 #define __HAL_RCC_I2C1_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) != RESET)
495 #define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
496 #define __HAL_RCC_BKP_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) != RESET)
497 #define __HAL_RCC_BKP_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_BKPEN)) == RESET)
498 #define __HAL_RCC_PWR_IS_CLK_ENABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) != RESET)
499 #define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
500
501 /**
502 * @}
503 */
504
505 /** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Clock Enable Disable
506 * @brief Enable or disable the High Speed APB (APB2) peripheral clock.
507 * @note After reset, the peripheral clock (used for registers read/write access)
508 * is disabled and the application software has to enable this clock before
509 * using it.
510 * @{
511 */
512 #define __HAL_RCC_AFIO_CLK_ENABLE() do { \
513 __IO uint32_t tmpreg; \
514 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
515 /* Delay after an RCC peripheral clock enabling */\
516 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_AFIOEN);\
517 UNUSED(tmpreg); \
518 } while(0U)
519
520 #define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
521 __IO uint32_t tmpreg; \
522 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
523 /* Delay after an RCC peripheral clock enabling */\
524 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPAEN);\
525 UNUSED(tmpreg); \
526 } while(0U)
527
528 #define __HAL_RCC_GPIOB_CLK_ENABLE() do { \
529 __IO uint32_t tmpreg; \
530 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
531 /* Delay after an RCC peripheral clock enabling */\
532 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPBEN);\
533 UNUSED(tmpreg); \
534 } while(0U)
535
536 #define __HAL_RCC_GPIOC_CLK_ENABLE() do { \
537 __IO uint32_t tmpreg; \
538 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
539 /* Delay after an RCC peripheral clock enabling */\
540 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPCEN);\
541 UNUSED(tmpreg); \
542 } while(0U)
543
544 #define __HAL_RCC_GPIOD_CLK_ENABLE() do { \
545 __IO uint32_t tmpreg; \
546 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
547 /* Delay after an RCC peripheral clock enabling */\
548 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_IOPDEN);\
549 UNUSED(tmpreg); \
550 } while(0U)
551
552 #define __HAL_RCC_ADC1_CLK_ENABLE() do { \
553 __IO uint32_t tmpreg; \
554 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
555 /* Delay after an RCC peripheral clock enabling */\
556 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_ADC1EN);\
557 UNUSED(tmpreg); \
558 } while(0U)
559
560 #define __HAL_RCC_TIM1_CLK_ENABLE() do { \
561 __IO uint32_t tmpreg; \
562 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
563 /* Delay after an RCC peripheral clock enabling */\
564 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_TIM1EN);\
565 UNUSED(tmpreg); \
566 } while(0U)
567
568 #define __HAL_RCC_SPI1_CLK_ENABLE() do { \
569 __IO uint32_t tmpreg; \
570 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
571 /* Delay after an RCC peripheral clock enabling */\
572 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_SPI1EN);\
573 UNUSED(tmpreg); \
574 } while(0U)
575
576 #define __HAL_RCC_USART1_CLK_ENABLE() do { \
577 __IO uint32_t tmpreg; \
578 SET_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
579 /* Delay after an RCC peripheral clock enabling */\
580 tmpreg = READ_BIT(RCC->APB2ENR, RCC_APB2ENR_USART1EN);\
581 UNUSED(tmpreg); \
582 } while(0U)
583
584 #define __HAL_RCC_AFIO_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_AFIOEN))
585 #define __HAL_RCC_GPIOA_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPAEN))
586 #define __HAL_RCC_GPIOB_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPBEN))
587 #define __HAL_RCC_GPIOC_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPCEN))
588 #define __HAL_RCC_GPIOD_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_IOPDEN))
589 #define __HAL_RCC_ADC1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_ADC1EN))
590
591 #define __HAL_RCC_TIM1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_TIM1EN))
592 #define __HAL_RCC_SPI1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_SPI1EN))
593 #define __HAL_RCC_USART1_CLK_DISABLE() (RCC->APB2ENR &= ~(RCC_APB2ENR_USART1EN))
594
595 /**
596 * @}
597 */
598
599 /** @defgroup RCC_APB2_Peripheral_Clock_Enable_Disable_Status APB2 Peripheral Clock Enable Disable Status
600 * @brief Get the enable or disable status of the APB2 peripheral clock.
601 * @note After reset, the peripheral clock (used for registers read/write access)
602 * is disabled and the application software has to enable this clock before
603 * using it.
604 * @{
605 */
606
607 #define __HAL_RCC_AFIO_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) != RESET)
608 #define __HAL_RCC_AFIO_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_AFIOEN)) == RESET)
609 #define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) != RESET)
610 #define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPAEN)) == RESET)
611 #define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) != RESET)
612 #define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPBEN)) == RESET)
613 #define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) != RESET)
614 #define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPCEN)) == RESET)
615 #define __HAL_RCC_GPIOD_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) != RESET)
616 #define __HAL_RCC_GPIOD_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_IOPDEN)) == RESET)
617 #define __HAL_RCC_ADC1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) != RESET)
618 #define __HAL_RCC_ADC1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_ADC1EN)) == RESET)
619 #define __HAL_RCC_TIM1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) != RESET)
620 #define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
621 #define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
622 #define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
623 #define __HAL_RCC_USART1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) != RESET)
624 #define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
625
626 /**
627 * @}
628 */
629
630 /** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
631 * @brief Force or release APB1 peripheral reset.
632 * @{
633 */
634 #define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
635 #define __HAL_RCC_TIM2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM2RST))
636 #define __HAL_RCC_TIM3_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM3RST))
637 #define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
638 #define __HAL_RCC_USART2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_USART2RST))
639 #define __HAL_RCC_I2C1_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C1RST))
640
641 #define __HAL_RCC_BKP_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_BKPRST))
642 #define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
643
644 #define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00)
645 #define __HAL_RCC_TIM2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM2RST))
646 #define __HAL_RCC_TIM3_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM3RST))
647 #define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
648 #define __HAL_RCC_USART2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_USART2RST))
649 #define __HAL_RCC_I2C1_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_I2C1RST))
650
651 #define __HAL_RCC_BKP_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_BKPRST))
652 #define __HAL_RCC_PWR_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_PWRRST))
653
654 /**
655 * @}
656 */
657
658 /** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
659 * @brief Force or release APB2 peripheral reset.
660 * @{
661 */
662 #define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
663 #define __HAL_RCC_AFIO_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_AFIORST))
664 #define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPARST))
665 #define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPBRST))
666 #define __HAL_RCC_GPIOC_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPCRST))
667 #define __HAL_RCC_GPIOD_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_IOPDRST))
668 #define __HAL_RCC_ADC1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_ADC1RST))
669
670 #define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
671 #define __HAL_RCC_SPI1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_SPI1RST))
672 #define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
673
674 #define __HAL_RCC_APB2_RELEASE_RESET() (RCC->APB2RSTR = 0x00)
675 #define __HAL_RCC_AFIO_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_AFIORST))
676 #define __HAL_RCC_GPIOA_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPARST))
677 #define __HAL_RCC_GPIOB_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPBRST))
678 #define __HAL_RCC_GPIOC_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPCRST))
679 #define __HAL_RCC_GPIOD_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_IOPDRST))
680 #define __HAL_RCC_ADC1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_ADC1RST))
681
682 #define __HAL_RCC_TIM1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_TIM1RST))
683 #define __HAL_RCC_SPI1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_SPI1RST))
684 #define __HAL_RCC_USART1_RELEASE_RESET() (RCC->APB2RSTR &= ~(RCC_APB2RSTR_USART1RST))
685
686 /**
687 * @}
688 */
689
690 /** @defgroup RCC_HSI_Configuration HSI Configuration
691 * @{
692 */
693
694 /** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
695 * @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
696 * @note HSI can not be stopped if it is used as system clock source. In this case,
697 * you have to select another source of the system clock then stop the HSI.
698 * @note After enabling the HSI, the application software should wait on HSIRDY
699 * flag to be set indicating that HSI clock is stable and can be used as
700 * system clock source.
701 * @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
702 * clock cycles.
703 */
704 #define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
705 #define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
706
707 /** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
708 * @note The calibration is used to compensate for the variations in voltage
709 * and temperature that influence the frequency of the internal HSI RC.
710 * @param _HSICALIBRATIONVALUE_ specifies the calibration trimming value.
711 * (default is RCC_HSICALIBRATION_DEFAULT).
712 * This parameter must be a number between 0 and 0x1F.
713 */
714 #define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(_HSICALIBRATIONVALUE_) \
715 (MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, (uint32_t)(_HSICALIBRATIONVALUE_) << RCC_CR_HSITRIM_Pos))
716
717 /**
718 * @}
719 */
720
721 /** @defgroup RCC_LSI_Configuration LSI Configuration
722 * @{
723 */
724
725 /** @brief Macro to enable the Internal Low Speed oscillator (LSI).
726 * @note After enabling the LSI, the application software should wait on
727 * LSIRDY flag to be set indicating that LSI clock is stable and can
728 * be used to clock the IWDG and/or the RTC.
729 */
730 #define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
731
732 /** @brief Macro to disable the Internal Low Speed oscillator (LSI).
733 * @note LSI can not be disabled if the IWDG is running.
734 * @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
735 * clock cycles.
736 */
737 #define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
738
739 /**
740 * @}
741 */
742
743 /** @defgroup RCC_HSE_Configuration HSE Configuration
744 * @{
745 */
746
747 /**
748 * @brief Macro to configure the External High Speed oscillator (HSE).
749 * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
750 * supported by this macro. User should request a transition to HSE Off
751 * first and then HSE On or HSE Bypass.
752 * @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
753 * software should wait on HSERDY flag to be set indicating that HSE clock
754 * is stable and can be used to clock the PLL and/or system clock.
755 * @note HSE state can not be changed if it is used directly or through the
756 * PLL as system clock. In this case, you have to select another source
757 * of the system clock then change the HSE state (ex. disable it).
758 * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
759 * @note This function reset the CSSON bit, so if the clock security system(CSS)
760 * was previously enabled you have to enable it again after calling this
761 * function.
762 * @param __STATE__ specifies the new state of the HSE.
763 * This parameter can be one of the following values:
764 * @arg @ref RCC_HSE_OFF turn OFF the HSE oscillator, HSERDY flag goes low after
765 * 6 HSE oscillator clock cycles.
766 * @arg @ref RCC_HSE_ON turn ON the HSE oscillator
767 * @arg @ref RCC_HSE_BYPASS HSE oscillator bypassed with external clock
768 */
769 #define __HAL_RCC_HSE_CONFIG(__STATE__) \
770 do{ \
771 if ((__STATE__) == RCC_HSE_ON) \
772 { \
773 SET_BIT(RCC->CR, RCC_CR_HSEON); \
774 } \
775 else if ((__STATE__) == RCC_HSE_OFF) \
776 { \
777 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
778 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
779 } \
780 else if ((__STATE__) == RCC_HSE_BYPASS) \
781 { \
782 SET_BIT(RCC->CR, RCC_CR_HSEBYP); \
783 SET_BIT(RCC->CR, RCC_CR_HSEON); \
784 } \
785 else \
786 { \
787 CLEAR_BIT(RCC->CR, RCC_CR_HSEON); \
788 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP); \
789 } \
790 }while(0U)
791
792 /**
793 * @}
794 */
795
796 /** @defgroup RCC_LSE_Configuration LSE Configuration
797 * @{
798 */
799
800 /**
801 * @brief Macro to configure the External Low Speed oscillator (LSE).
802 * @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
803 * @note As the LSE is in the Backup domain and write access is denied to
804 * this domain after reset, you have to enable write access using
805 * @ref HAL_PWR_EnableBkUpAccess() function before to configure the LSE
806 * (to be done once after reset).
807 * @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
808 * software should wait on LSERDY flag to be set indicating that LSE clock
809 * is stable and can be used to clock the RTC.
810 * @param __STATE__ specifies the new state of the LSE.
811 * This parameter can be one of the following values:
812 * @arg @ref RCC_LSE_OFF turn OFF the LSE oscillator, LSERDY flag goes low after
813 * 6 LSE oscillator clock cycles.
814 * @arg @ref RCC_LSE_ON turn ON the LSE oscillator.
815 * @arg @ref RCC_LSE_BYPASS LSE oscillator bypassed with external clock.
816 */
817 #define __HAL_RCC_LSE_CONFIG(__STATE__) \
818 do{ \
819 if ((__STATE__) == RCC_LSE_ON) \
820 { \
821 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
822 } \
823 else if ((__STATE__) == RCC_LSE_OFF) \
824 { \
825 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
826 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
827 } \
828 else if ((__STATE__) == RCC_LSE_BYPASS) \
829 { \
830 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
831 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
832 } \
833 else \
834 { \
835 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON); \
836 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP); \
837 } \
838 }while(0U)
839
840 /**
841 * @}
842 */
843
844 /** @defgroup RCC_PLL_Configuration PLL Configuration
845 * @{
846 */
847
848 /** @brief Macro to enable the main PLL.
849 * @note After enabling the main PLL, the application software should wait on
850 * PLLRDY flag to be set indicating that PLL clock is stable and can
851 * be used as system clock source.
852 * @note The main PLL is disabled by hardware when entering STOP and STANDBY modes.
853 */
854 #define __HAL_RCC_PLL_ENABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = ENABLE)
855
856 /** @brief Macro to disable the main PLL.
857 * @note The main PLL can not be disabled if it is used as system clock source
858 */
859 #define __HAL_RCC_PLL_DISABLE() (*(__IO uint32_t *) RCC_CR_PLLON_BB = DISABLE)
860
861 /** @brief Macro to configure the main PLL clock source and multiplication factors.
862 * @note This function must be used only when the main PLL is disabled.
863 *
864 * @param __RCC_PLLSOURCE__ specifies the PLL entry clock source.
865 * This parameter can be one of the following values:
866 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL clock entry
867 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL clock entry
868 * @param __PLLMUL__ specifies the multiplication factor for PLL VCO output clock
869 * This parameter can be one of the following values:
870 * @arg @ref RCC_PLL_MUL4 PLLVCO = PLL clock entry x 4
871 * @arg @ref RCC_PLL_MUL6 PLLVCO = PLL clock entry x 6
872 @if STM32F105xC
873 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
874 @elseif STM32F107xC
875 * @arg @ref RCC_PLL_MUL6_5 PLLVCO = PLL clock entry x 6.5
876 @else
877 * @arg @ref RCC_PLL_MUL2 PLLVCO = PLL clock entry x 2
878 * @arg @ref RCC_PLL_MUL3 PLLVCO = PLL clock entry x 3
879 * @arg @ref RCC_PLL_MUL10 PLLVCO = PLL clock entry x 10
880 * @arg @ref RCC_PLL_MUL11 PLLVCO = PLL clock entry x 11
881 * @arg @ref RCC_PLL_MUL12 PLLVCO = PLL clock entry x 12
882 * @arg @ref RCC_PLL_MUL13 PLLVCO = PLL clock entry x 13
883 * @arg @ref RCC_PLL_MUL14 PLLVCO = PLL clock entry x 14
884 * @arg @ref RCC_PLL_MUL15 PLLVCO = PLL clock entry x 15
885 * @arg @ref RCC_PLL_MUL16 PLLVCO = PLL clock entry x 16
886 @endif
887 * @arg @ref RCC_PLL_MUL8 PLLVCO = PLL clock entry x 8
888 * @arg @ref RCC_PLL_MUL9 PLLVCO = PLL clock entry x 9
889 *
890 */
891 #define __HAL_RCC_PLL_CONFIG(__RCC_PLLSOURCE__, __PLLMUL__)\
892 MODIFY_REG(RCC->CFGR, (RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL),((__RCC_PLLSOURCE__) | (__PLLMUL__) ))
893
894 /** @brief Get oscillator clock selected as PLL input clock
895 * @retval The clock source used for PLL entry. The returned value can be one
896 * of the following:
897 * @arg @ref RCC_PLLSOURCE_HSI_DIV2 HSI oscillator clock selected as PLL input clock
898 * @arg @ref RCC_PLLSOURCE_HSE HSE oscillator clock selected as PLL input clock
899 */
900 #define __HAL_RCC_GET_PLL_OSCSOURCE() ((uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PLLSRC)))
901
902 /**
903 * @}
904 */
905
906 /** @defgroup RCC_Get_Clock_source Get Clock source
907 * @{
908 */
909
910 /**
911 * @brief Macro to configure the system clock source.
912 * @param __SYSCLKSOURCE__ specifies the system clock source.
913 * This parameter can be one of the following values:
914 * @arg @ref RCC_SYSCLKSOURCE_HSI HSI oscillator is used as system clock source.
915 * @arg @ref RCC_SYSCLKSOURCE_HSE HSE oscillator is used as system clock source.
916 * @arg @ref RCC_SYSCLKSOURCE_PLLCLK PLL output is used as system clock source.
917 */
918 #define __HAL_RCC_SYSCLK_CONFIG(__SYSCLKSOURCE__) \
919 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__SYSCLKSOURCE__))
920
921 /** @brief Macro to get the clock source used as system clock.
922 * @retval The clock source used as system clock. The returned value can be one
923 * of the following:
924 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSI HSI used as system clock
925 * @arg @ref RCC_SYSCLKSOURCE_STATUS_HSE HSE used as system clock
926 * @arg @ref RCC_SYSCLKSOURCE_STATUS_PLLCLK PLL used as system clock
927 */
928 #define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(READ_BIT(RCC->CFGR,RCC_CFGR_SWS)))
929
930 /**
931 * @}
932 */
933
934 /** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
935 * @{
936 */
937
938 #if defined(RCC_CFGR_MCO_3)
939 /** @brief Macro to configure the MCO clock.
940 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
941 * This parameter can be one of the following values:
942 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
943 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
944 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
945 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
946 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
947 * @arg @ref RCC_MCO1SOURCE_PLL2CLK PLL2 clock selected by 2 selected as MCO clock
948 * @arg @ref RCC_MCO1SOURCE_PLL3CLK_DIV2 PLL3 clock divided by 2 selected as MCO clock
949 * @arg @ref RCC_MCO1SOURCE_EXT_HSE XT1 external 3-25 MHz oscillator clock selected (for Ethernet) as MCO clock
950 * @arg @ref RCC_MCO1SOURCE_PLL3CLK PLL3 clock selected (for Ethernet) as MCO clock
951 * @param __MCODIV__ specifies the MCO clock prescaler.
952 * This parameter can be one of the following values:
953 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
954 */
955 #else
956 /** @brief Macro to configure the MCO clock.
957 * @param __MCOCLKSOURCE__ specifies the MCO clock source.
958 * This parameter can be one of the following values:
959 * @arg @ref RCC_MCO1SOURCE_NOCLOCK No clock selected as MCO clock
960 * @arg @ref RCC_MCO1SOURCE_SYSCLK System clock (SYSCLK) selected as MCO clock
961 * @arg @ref RCC_MCO1SOURCE_HSI HSI selected as MCO clock
962 * @arg @ref RCC_MCO1SOURCE_HSE HSE selected as MCO clock
963 * @arg @ref RCC_MCO1SOURCE_PLLCLK PLL clock divided by 2 selected as MCO clock
964 * @param __MCODIV__ specifies the MCO clock prescaler.
965 * This parameter can be one of the following values:
966 * @arg @ref RCC_MCODIV_1 No division applied on MCO clock source
967 */
968 #endif
969
970 #define __HAL_RCC_MCO1_CONFIG(__MCOCLKSOURCE__, __MCODIV__) \
971 MODIFY_REG(RCC->CFGR, RCC_CFGR_MCO, (__MCOCLKSOURCE__))
972
973
974 /**
975 * @}
976 */
977
978 /** @defgroup RCC_RTC_Clock_Configuration RCC RTC Clock Configuration
979 * @{
980 */
981
982 /** @brief Macro to configure the RTC clock (RTCCLK).
983 * @note As the RTC clock configuration bits are in the Backup domain and write
984 * access is denied to this domain after reset, you have to enable write
985 * access using the Power Backup Access macro before to configure
986 * the RTC clock source (to be done once after reset).
987 * @note Once the RTC clock is configured it can't be changed unless the
988 * Backup domain is reset using @ref __HAL_RCC_BACKUPRESET_FORCE() macro, or by
989 * a Power On Reset (POR).
990 *
991 * @param __RTC_CLKSOURCE__ specifies the RTC clock source.
992 * This parameter can be one of the following values:
993 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
994 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
995 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
996 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
997 * @note If the LSE or LSI is used as RTC clock source, the RTC continues to
998 * work in STOP and STANDBY modes, and can be used as wakeup source.
999 * However, when the HSE clock is used as RTC clock source, the RTC
1000 * cannot be used in STOP and STANDBY modes.
1001 * @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
1002 * RTC clock source).
1003 */
1004 #define __HAL_RCC_RTC_CONFIG(__RTC_CLKSOURCE__) MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, (__RTC_CLKSOURCE__))
1005
1006 /** @brief Macro to get the RTC clock source.
1007 * @retval The clock source can be one of the following values:
1008 * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
1009 * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
1010 * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
1011 * @arg @ref RCC_RTCCLKSOURCE_HSE_DIV128 HSE divided by 128 selected as RTC clock
1012 */
1013 #define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
1014
1015 /** @brief Macro to enable the the RTC clock.
1016 * @note These macros must be used only after the RTC clock source was selected.
1017 */
1018 #define __HAL_RCC_RTC_ENABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = ENABLE)
1019
1020 /** @brief Macro to disable the the RTC clock.
1021 * @note These macros must be used only after the RTC clock source was selected.
1022 */
1023 #define __HAL_RCC_RTC_DISABLE() (*(__IO uint32_t *) RCC_BDCR_RTCEN_BB = DISABLE)
1024
1025 /** @brief Macro to force the Backup domain reset.
1026 * @note This function resets the RTC peripheral (including the backup registers)
1027 * and the RTC clock source selection in RCC_BDCR register.
1028 */
1029 #define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
1030
1031 /** @brief Macros to release the Backup domain reset.
1032 */
1033 #define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
1034
1035 /**
1036 * @}
1037 */
1038
1039 /** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
1040 * @brief macros to manage the specified RCC Flags and interrupts.
1041 * @{
1042 */
1043
1044 /** @brief Enable RCC interrupt.
1045 * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
1046 * This parameter can be any combination of the following values:
1047 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1048 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
1049 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1050 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
1051 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1052 @if STM32F105xx
1053 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
1054 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
1055 @elsif STM32F107xx
1056 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
1057 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
1058 @endif
1059 */
1060 #define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
1061
1062 /** @brief Disable RCC interrupt.
1063 * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
1064 * This parameter can be any combination of the following values:
1065 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt
1066 * @arg @ref RCC_IT_LSERDY LSE ready interrupt
1067 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt
1068 * @arg @ref RCC_IT_HSERDY HSE ready interrupt
1069 * @arg @ref RCC_IT_PLLRDY main PLL ready interrupt
1070 @if STM32F105xx
1071 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
1072 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
1073 @elsif STM32F107xx
1074 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
1075 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
1076 @endif
1077 */
1078 #define __HAL_RCC_DISABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS &= (uint8_t)(~(__INTERRUPT__)))
1079
1080 /** @brief Clear the RCC's interrupt pending bits.
1081 * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
1082 * This parameter can be any combination of the following values:
1083 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
1084 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
1085 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
1086 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
1087 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
1088 @if STM32F105xx
1089 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
1090 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
1091 @elsif STM32F107xx
1092 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
1093 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
1094 @endif
1095 * @arg @ref RCC_IT_CSS Clock Security System interrupt
1096 */
1097 #define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
1098
1099 /** @brief Check the RCC's interrupt has occurred or not.
1100 * @param __INTERRUPT__ specifies the RCC interrupt source to check.
1101 * This parameter can be one of the following values:
1102 * @arg @ref RCC_IT_LSIRDY LSI ready interrupt.
1103 * @arg @ref RCC_IT_LSERDY LSE ready interrupt.
1104 * @arg @ref RCC_IT_HSIRDY HSI ready interrupt.
1105 * @arg @ref RCC_IT_HSERDY HSE ready interrupt.
1106 * @arg @ref RCC_IT_PLLRDY Main PLL ready interrupt.
1107 @if STM32F105xx
1108 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
1109 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
1110 @elsif STM32F107xx
1111 * @arg @ref RCC_IT_PLL2RDY Main PLL2 ready interrupt.
1112 * @arg @ref RCC_IT_PLLI2S2RDY Main PLLI2S ready interrupt.
1113 @endif
1114 * @arg @ref RCC_IT_CSS Clock Security System interrupt
1115 * @retval The new state of __INTERRUPT__ (TRUE or FALSE).
1116 */
1117 #define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
1118
1119 /** @brief Set RMVF bit to clear the reset flags.
1120 * The reset flags are RCC_FLAG_PINRST, RCC_FLAG_PORRST, RCC_FLAG_SFTRST,
1121 * RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
1122 */
1123 #define __HAL_RCC_CLEAR_RESET_FLAGS() (*(__IO uint32_t *)RCC_CSR_RMVF_BB = ENABLE)
1124
1125 /** @brief Check RCC flag is set or not.
1126 * @param __FLAG__ specifies the flag to check.
1127 * This parameter can be one of the following values:
1128 * @arg @ref RCC_FLAG_HSIRDY HSI oscillator clock ready.
1129 * @arg @ref RCC_FLAG_HSERDY HSE oscillator clock ready.
1130 * @arg @ref RCC_FLAG_PLLRDY Main PLL clock ready.
1131 @if STM32F105xx
1132 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
1133 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
1134 @elsif STM32F107xx
1135 * @arg @ref RCC_FLAG_PLL2RDY Main PLL2 clock ready.
1136 * @arg @ref RCC_FLAG_PLLI2SRDY Main PLLI2S clock ready.
1137 @endif
1138 * @arg @ref RCC_FLAG_LSERDY LSE oscillator clock ready.
1139 * @arg @ref RCC_FLAG_LSIRDY LSI oscillator clock ready.
1140 * @arg @ref RCC_FLAG_PINRST Pin reset.
1141 * @arg @ref RCC_FLAG_PORRST POR/PDR reset.
1142 * @arg @ref RCC_FLAG_SFTRST Software reset.
1143 * @arg @ref RCC_FLAG_IWDGRST Independent Watchdog reset.
1144 * @arg @ref RCC_FLAG_WWDGRST Window Watchdog reset.
1145 * @arg @ref RCC_FLAG_LPWRRST Low Power reset.
1146 * @retval The new state of __FLAG__ (TRUE or FALSE).
1147 */
1148 #define __HAL_RCC_GET_FLAG(__FLAG__) (((((__FLAG__) >> 5U) == CR_REG_INDEX)? RCC->CR : \
1149 ((((__FLAG__) >> 5U) == BDCR_REG_INDEX)? RCC->BDCR : \
1150 RCC->CSR)) & (1U << ((__FLAG__) & RCC_FLAG_MASK)))
1151
1152 /**
1153 * @}
1154 */
1155
1156 /**
1157 * @}
1158 */
1159
1160 /* Include RCC HAL Extension module */
1161 #include "stm32f1xx_hal_rcc_ex.h"
1162
1163 /* Exported functions --------------------------------------------------------*/
1164 /** @addtogroup RCC_Exported_Functions
1165 * @{
1166 */
1167
1168 /** @addtogroup RCC_Exported_Functions_Group1
1169 * @{
1170 */
1171
1172 /* Initialization and de-initialization functions ******************************/
1173 void HAL_RCC_DeInit(void);
1174 HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1175 HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
1176
1177 /**
1178 * @}
1179 */
1180
1181 /** @addtogroup RCC_Exported_Functions_Group2
1182 * @{
1183 */
1184
1185 /* Peripheral Control functions ************************************************/
1186 void HAL_RCC_MCOConfig(uint32_t RCC_MCOx, uint32_t RCC_MCOSource, uint32_t RCC_MCODiv);
1187 void HAL_RCC_EnableCSS(void);
1188 void HAL_RCC_DisableCSS(void);
1189 uint32_t HAL_RCC_GetSysClockFreq(void);
1190 uint32_t HAL_RCC_GetHCLKFreq(void);
1191 uint32_t HAL_RCC_GetPCLK1Freq(void);
1192 uint32_t HAL_RCC_GetPCLK2Freq(void);
1193 void HAL_RCC_GetOscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
1194 void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency);
1195
1196 /* CSS NMI IRQ handler */
1197 void HAL_RCC_NMI_IRQHandler(void);
1198
1199 /* User Callbacks in non blocking mode (IT mode) */
1200 void HAL_RCC_CSSCallback(void);
1201
1202 /**
1203 * @}
1204 */
1205
1206 /**
1207 * @}
1208 */
1209
1210 /** @addtogroup RCC_Private_Constants
1211 * @{
1212 */
1213
1214 /** @defgroup RCC_Timeout RCC Timeout
1215 * @{
1216 */
1217
1218 /* Disable Backup domain write protection state change timeout */
1219 #define RCC_DBP_TIMEOUT_VALUE 100U /* 100 ms */
1220 /* LSE state change timeout */
1221 #define RCC_LSE_TIMEOUT_VALUE LSE_STARTUP_TIMEOUT
1222 #define CLOCKSWITCH_TIMEOUT_VALUE 5000 /* 5 s */
1223 #define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
1224 #define HSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
1225 #define LSI_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
1226 #define PLL_TIMEOUT_VALUE 2U /* 2 ms (minimum Tick + 1) */
1227
1228 /**
1229 * @}
1230 */
1231
1232 /** @defgroup RCC_Register_Offset Register offsets
1233 * @{
1234 */
1235 #define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
1236 #define RCC_CR_OFFSET 0x00U
1237 #define RCC_CFGR_OFFSET 0x04U
1238 #define RCC_CIR_OFFSET 0x08U
1239 #define RCC_BDCR_OFFSET 0x20U
1240 #define RCC_CSR_OFFSET 0x24U
1241
1242 /**
1243 * @}
1244 */
1245
1246 /** @defgroup RCC_BitAddress_AliasRegion BitAddress AliasRegion
1247 * @brief RCC registers bit address in the alias region
1248 * @{
1249 */
1250 #define RCC_CR_OFFSET_BB (RCC_OFFSET + RCC_CR_OFFSET)
1251 #define RCC_CFGR_OFFSET_BB (RCC_OFFSET + RCC_CFGR_OFFSET)
1252 #define RCC_CIR_OFFSET_BB (RCC_OFFSET + RCC_CIR_OFFSET)
1253 #define RCC_BDCR_OFFSET_BB (RCC_OFFSET + RCC_BDCR_OFFSET)
1254 #define RCC_CSR_OFFSET_BB (RCC_OFFSET + RCC_CSR_OFFSET)
1255
1256 /* --- CR Register ---*/
1257 /* Alias word address of HSION bit */
1258 #define RCC_HSION_BIT_NUMBER RCC_CR_HSION_Pos
1259 #define RCC_CR_HSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSION_BIT_NUMBER * 4U)))
1260 /* Alias word address of HSEON bit */
1261 #define RCC_HSEON_BIT_NUMBER RCC_CR_HSEON_Pos
1262 #define RCC_CR_HSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_HSEON_BIT_NUMBER * 4U)))
1263 /* Alias word address of CSSON bit */
1264 #define RCC_CSSON_BIT_NUMBER RCC_CR_CSSON_Pos
1265 #define RCC_CR_CSSON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_CSSON_BIT_NUMBER * 4U)))
1266 /* Alias word address of PLLON bit */
1267 #define RCC_PLLON_BIT_NUMBER RCC_CR_PLLON_Pos
1268 #define RCC_CR_PLLON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CR_OFFSET_BB * 32U) + (RCC_PLLON_BIT_NUMBER * 4U)))
1269
1270 /* --- CSR Register ---*/
1271 /* Alias word address of LSION bit */
1272 #define RCC_LSION_BIT_NUMBER RCC_CSR_LSION_Pos
1273 #define RCC_CSR_LSION_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_LSION_BIT_NUMBER * 4U)))
1274
1275 /* Alias word address of RMVF bit */
1276 #define RCC_RMVF_BIT_NUMBER RCC_CSR_RMVF_Pos
1277 #define RCC_CSR_RMVF_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_CSR_OFFSET_BB * 32U) + (RCC_RMVF_BIT_NUMBER * 4U)))
1278
1279 /* --- BDCR Registers ---*/
1280 /* Alias word address of LSEON bit */
1281 #define RCC_LSEON_BIT_NUMBER RCC_BDCR_LSEON_Pos
1282 #define RCC_BDCR_LSEON_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEON_BIT_NUMBER * 4U)))
1283
1284 /* Alias word address of LSEON bit */
1285 #define RCC_LSEBYP_BIT_NUMBER RCC_BDCR_LSEBYP_Pos
1286 #define RCC_BDCR_LSEBYP_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_LSEBYP_BIT_NUMBER * 4U)))
1287
1288 /* Alias word address of RTCEN bit */
1289 #define RCC_RTCEN_BIT_NUMBER RCC_BDCR_RTCEN_Pos
1290 #define RCC_BDCR_RTCEN_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_RTCEN_BIT_NUMBER * 4U)))
1291
1292 /* Alias word address of BDRST bit */
1293 #define RCC_BDRST_BIT_NUMBER RCC_BDCR_BDRST_Pos
1294 #define RCC_BDCR_BDRST_BB ((uint32_t)(PERIPH_BB_BASE + (RCC_BDCR_OFFSET_BB * 32U) + (RCC_BDRST_BIT_NUMBER * 4U)))
1295
1296 /**
1297 * @}
1298 */
1299
1300 /* CR register byte 2 (Bits[23:16]) base address */
1301 #define RCC_CR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CR_OFFSET + 0x02U))
1302
1303 /* CIR register byte 1 (Bits[15:8]) base address */
1304 #define RCC_CIR_BYTE1_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x01U))
1305
1306 /* CIR register byte 2 (Bits[23:16]) base address */
1307 #define RCC_CIR_BYTE2_ADDRESS ((uint32_t)(RCC_BASE + RCC_CIR_OFFSET + 0x02U))
1308
1309 /* Defines used for Flags */
1310 #define CR_REG_INDEX ((uint8_t)1)
1311 #define BDCR_REG_INDEX ((uint8_t)2)
1312 #define CSR_REG_INDEX ((uint8_t)3)
1313
1314 #define RCC_FLAG_MASK ((uint8_t)0x1F)
1315
1316 /**
1317 * @}
1318 */
1319
1320 /** @addtogroup RCC_Private_Macros
1321 * @{
1322 */
1323 /** @defgroup RCC_Alias_For_Legacy Alias define maintained for legacy
1324 * @{
1325 */
1326 #define __HAL_RCC_SYSCFG_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
1327 #define __HAL_RCC_SYSCFG_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
1328 #define __HAL_RCC_SYSCFG_FORCE_RESET __HAL_RCC_AFIO_FORCE_RESET
1329 #define __HAL_RCC_SYSCFG_RELEASE_RESET __HAL_RCC_AFIO_RELEASE_RESET
1330 /**
1331 * @}
1332 */
1333
1334 #define IS_RCC_PLLSOURCE(__SOURCE__) (((__SOURCE__) == RCC_PLLSOURCE_HSI_DIV2) || \
1335 ((__SOURCE__) == RCC_PLLSOURCE_HSE))
1336 #define IS_RCC_OSCILLATORTYPE(__OSCILLATOR__) (((__OSCILLATOR__) == RCC_OSCILLATORTYPE_NONE) || \
1337 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE) || \
1338 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI) || \
1339 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSI) == RCC_OSCILLATORTYPE_LSI) || \
1340 (((__OSCILLATOR__) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE))
1341 #define IS_RCC_HSE(__HSE__) (((__HSE__) == RCC_HSE_OFF) || ((__HSE__) == RCC_HSE_ON) || \
1342 ((__HSE__) == RCC_HSE_BYPASS))
1343 #define IS_RCC_LSE(__LSE__) (((__LSE__) == RCC_LSE_OFF) || ((__LSE__) == RCC_LSE_ON) || \
1344 ((__LSE__) == RCC_LSE_BYPASS))
1345 #define IS_RCC_HSI(__HSI__) (((__HSI__) == RCC_HSI_OFF) || ((__HSI__) == RCC_HSI_ON))
1346 #define IS_RCC_CALIBRATION_VALUE(__VALUE__) ((__VALUE__) <= 0x1FU)
1347 #define IS_RCC_LSI(__LSI__) (((__LSI__) == RCC_LSI_OFF) || ((__LSI__) == RCC_LSI_ON))
1348 #define IS_RCC_PLL(__PLL__) (((__PLL__) == RCC_PLL_NONE) || ((__PLL__) == RCC_PLL_OFF) || \
1349 ((__PLL__) == RCC_PLL_ON))
1350
1351 #define IS_RCC_CLOCKTYPE(CLK) ((((CLK) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK) || \
1352 (((CLK) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK) || \
1353 (((CLK) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1) || \
1354 (((CLK) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2))
1355 #define IS_RCC_SYSCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_HSI) || \
1356 ((__SOURCE__) == RCC_SYSCLKSOURCE_HSE) || \
1357 ((__SOURCE__) == RCC_SYSCLKSOURCE_PLLCLK))
1358 #define IS_RCC_SYSCLKSOURCE_STATUS(__SOURCE__) (((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSI) || \
1359 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_HSE) || \
1360 ((__SOURCE__) == RCC_SYSCLKSOURCE_STATUS_PLLCLK))
1361 #define IS_RCC_HCLK(__HCLK__) (((__HCLK__) == RCC_SYSCLK_DIV1) || ((__HCLK__) == RCC_SYSCLK_DIV2) || \
1362 ((__HCLK__) == RCC_SYSCLK_DIV4) || ((__HCLK__) == RCC_SYSCLK_DIV8) || \
1363 ((__HCLK__) == RCC_SYSCLK_DIV16) || ((__HCLK__) == RCC_SYSCLK_DIV64) || \
1364 ((__HCLK__) == RCC_SYSCLK_DIV128) || ((__HCLK__) == RCC_SYSCLK_DIV256) || \
1365 ((__HCLK__) == RCC_SYSCLK_DIV512))
1366 #define IS_RCC_PCLK(__PCLK__) (((__PCLK__) == RCC_HCLK_DIV1) || ((__PCLK__) == RCC_HCLK_DIV2) || \
1367 ((__PCLK__) == RCC_HCLK_DIV4) || ((__PCLK__) == RCC_HCLK_DIV8) || \
1368 ((__PCLK__) == RCC_HCLK_DIV16))
1369 #define IS_RCC_MCO(__MCO__) ((__MCO__) == RCC_MCO)
1370 #define IS_RCC_MCODIV(__DIV__) (((__DIV__) == RCC_MCODIV_1))
1371 #define IS_RCC_RTCCLKSOURCE(__SOURCE__) (((__SOURCE__) == RCC_RTCCLKSOURCE_NO_CLK) || \
1372 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSE) || \
1373 ((__SOURCE__) == RCC_RTCCLKSOURCE_LSI) || \
1374 ((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV128))
1375
1376 /**
1377 * @}
1378 */
1379
1380 /**
1381 * @}
1382 */
1383
1384 /**
1385 * @}
1386 */
1387
1388 #ifdef __cplusplus
1389 }
1390 #endif
1391
1392 #endif /* __STM32F1xx_HAL_RCC_H */
1393
1394 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
1395